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https://github.com/espressif/esp-idf.git
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Merge branch 'bugfix/minor_fixes' into 'master'
Minor fixes from various sources - Fix memory debugging code. Noticed by Tuan. - intr_enable/disable should be in IRAM. Noticed by rojer - Still old timer code in examples in doxygen comments. Noticed on the forum by jumjum123 - Timer example was broken. Noticed on the forum by jumjum123 See merge request !325
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@ -343,9 +343,6 @@ esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num);
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/**
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* @brief register GPIO interrupt handler, the handler is an ISR.
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* The handler will be attached to the same CPU core that this function is running on.
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* @note
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* Users should know that which CPU is running and then pick a INUM that is not used by system.
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* We can find the information of INUM and interrupt level in soc.h.
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*
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* @param fn Interrupt handler function.
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* @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
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@ -444,12 +441,8 @@ esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num);
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/**
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*----------EXAMPLE TO SET ISR HANDLER ----------------------
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* @code{c}
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* gpio_isr_register(gpio_intr_test,NULL, 0); //hook the isr handler for GPIO interrupt
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* gpio_isr_register(gpio_intr_test, 0, NULL); //hook the isr handler for GPIO interrupt
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* @endcode
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* @note
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* 1. user should arrange the INUMs that used, better not to use a same INUM for different interrupt.
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* 2. do not pick the INUM that already occupied by the system.
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* 3. refer to soc.h to check which INUMs that can be used.
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*/
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/**
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*-------------EXAMPLE OF HANDLER FUNCTION-------------------*
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@ -463,8 +463,6 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_
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* @brief Install UART driver.
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*
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* UART ISR handler will be attached to the same CPU core that this function is running on.
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* Users should know that which CPU is running and then pick a INUM that is not used by system.
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* We can find the information of INUM and interrupt level in soc.h.
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*
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* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
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* @param rx_buffer_size UART RX ring buffer size
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@ -595,7 +593,6 @@ esp_err_t uart_flush(uart_port_t uart_num);
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* @code{c}
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* //1. Setup UART
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* #include "freertos/queue.h"
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* #define UART_INTR_NUM 17 //choose one interrupt number from soc.h
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* //a. Set UART parameter
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* int uart_num = 0; //uart port number
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* uart_config_t uart_config = {
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@ -658,7 +655,7 @@ esp_err_t uart_flush(uart_port_t uart_num);
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* //Set UART1 pins(TX: IO16, RX: IO17, RTS: IO18, CTS: IO19)
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* uart_set_pin(uart_num, 16, 17, 18, 19);
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* //Install UART driver( We don't need an event queue here)
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* uart_driver_install(uart_num, 1024 * 2, 1024*4, 10, 17, NULL, RINGBUF_TYPE_BYTEBUF);
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* uart_driver_install(uart_num, 1024 * 2, 1024*4, 10, NULL, 0);
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* uint8_t data[1000];
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* while(1) {
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* //Read data from UART
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@ -636,7 +636,7 @@ int esp_intr_get_cpu(intr_handle_t handle)
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//Muxing an interrupt source to interrupt 6, 7, 11, 15, 16 or 29 cause the interrupt to effectively be disabled.
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#define INT_MUX_DISABLED_INTNO 6
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esp_err_t esp_intr_enable(intr_handle_t handle)
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esp_err_t IRAM_ATTR esp_intr_enable(intr_handle_t handle)
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{
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if (!handle) return ESP_ERR_INVALID_ARG;
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portENTER_CRITICAL(&spinlock);
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@ -659,7 +659,7 @@ esp_err_t esp_intr_enable(intr_handle_t handle)
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return ESP_OK;
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}
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esp_err_t esp_intr_disable(intr_handle_t handle)
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esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
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{
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if (!handle) return ESP_ERR_INVALID_ARG;
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portENTER_CRITICAL(&spinlock);
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@ -174,7 +174,7 @@ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
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/*-----------------------------------------------------------*/
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/* The size of the structure placed at the beginning of each allocated memory
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block must by correctly byte aligned. */
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block must be correctly byte aligned. */
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static const uint32_t uxHeapStructSize = ( ( sizeof ( BlockLink_t ) + BLOCK_HEAD_LEN + BLOCK_TAIL_LEN + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
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/* Create a couple of list links to mark the start and end of the list. */
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@ -583,7 +583,7 @@ const HeapRegionTagged_t *pxHeapRegion;
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#if (configENABLE_MEMORY_DEBUG == 1)
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{
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mem_debug_init(uxHeapStructSize, &xStart, pxEnd, &xMallocMutex, xBlockAllocatedBit);
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mem_debug_init(uxHeapStructSize, &xStart, pxEnd, &xMallocMutex);
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mem_check_all(0);
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}
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#endif
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@ -22,9 +22,10 @@ typedef struct {
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/* Please keep this definition same as BlockLink_t */
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typedef struct _os_block_t {
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struct _os_block_t *next;
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size_t size;
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unsigned int xtag;
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struct _os_block_t *next; /*<< The next free block in the list. */
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int size: 24; /*<< The size of the free block. */
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int xtag: 7; /*<< Tag of this region */
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int xAllocated: 1; /*<< 1 if allocated */
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}os_block_t;
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typedef struct {
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@ -50,7 +51,7 @@ typedef struct _mem_dbg_ctl{
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#define OS_BLOCK(_b) ((os_block_t*)((debug_block_t*)((char*)(_b) + BLOCK_HEAD_LEN)))
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#define DEBUG_BLOCK(_b) ((debug_block_t*)((char*)(_b) - BLOCK_HEAD_LEN))
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#define HEAD_DOG(_b) ((_b)->head.dog)
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#define TAIL_DOG(_b) (*(unsigned int*)((char*)(_b) + (((_b)->os_block.size & (~g_alloc_bit) ) - BLOCK_TAIL_LEN)))
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#define TAIL_DOG(_b) (*(unsigned int*)((char*)(_b) + (((_b)->os_block.size ) - BLOCK_TAIL_LEN)))
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#define DOG_ASSERT()\
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{\
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@ -83,7 +83,7 @@ void IRAM_ATTR timer_group0_isr(void *para)
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uint32_t intr_status = TIMERG0.int_st_timers.val;
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timer_event_t evt;
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if((intr_status & BIT(timer_idx)) && timer_idx == TIMER_0) {
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/*Timer0 is an example that don't reload counter value*/
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/*Timer0 is an example that doesn't reload counter value*/
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TIMERG0.hw_timer[timer_idx].update = 1;
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/* We don't call a API here because they are not declared with IRAM_ATTR.
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@ -197,9 +197,9 @@ void tg0_timer1_init()
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*/
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void app_main()
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{
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timer_queue = xQueueCreate(10, sizeof(timer_event_t));
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tg0_timer0_init();
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tg0_timer1_init();
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timer_queue = xQueueCreate(10, sizeof(timer_event_t));
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xTaskCreate(timer_evt_task, "timer_evt_task", 1024, NULL, 5, NULL);
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xTaskCreate(timer_evt_task, "timer_evt_task", 2048, NULL, 5, NULL);
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}
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