* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
longer signed/unsigned int).
Changes come from internal branch commit a6723fc
correct generation.py script to be silent when file: function is not in the object list (just ignore placement)
correct linker.lf to place task functions into flash if CONFIG_FREERTOS_TASK_FUNCTIONS_INTO_FLASH is active otherwise into IRAM
update kconfig option to place functions into IRAM
update linker file after tests
fix spi_device_polling_end crash when xTaskGetTickCount() in flash
disable "yield from lower priority task, other CPU" test case when placing rtos functions into flash
upadate ut app config freertos_flash
combine spi_flash driver and freertos ut configs into one file
remove TEST_EXCLUDE_COMPONENTS
ci: fix ut job
remove functions that are called from ISR funcs
add port module functions to place into Flash
place snapshot funcs into Flash when ESP_PANIC_HANDLER_IRAM is not set
ci: add job with tags UT_T1_GPIO,ESP32_IDF
* partition api changed from spi_flash* API to
esp_partition* API and is abstracted as a C++
interface.
* The old nvs encryption is still possible
* changed default unit test app partition table
* Partitions coming from esp_partition API are
checked for generic flash encryption. If yes,
an error is returned since generic flash
encryption isn't compatible with nvs
encryption
* esp32, esp32s2 tests don't require nvs_flash
but mbedtls now
Closes IDF-1340
Closes IDF-858
* changing dependencies from unity->cmock
* added component.mk and Makefile.projbuild
* ignore test dir in gen_esp_err_to_name.py
* added some brief introduction of CMock in IDF
If esp_restart_noos() is run and the stack address points to external memory (SPIRAM)
then Cache_Read_Disable() raises up the error "Cache disabled but cached memory region accessed"
to fix this we switch stack to internal RAM before disable cache.
Added unit tests.
Closes: https://github.com/espressif/esp-idf/issues/5107
The SPI bus lock on SPI1 introduces two side effects:
1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.
2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.
This commit:
1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.
2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.
3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.
introduced in 49a48644e4.
Closes https://github.com/espressif/esp-idf/issues/5046
This configuration overflows DRAM size for esp32s2 and hence
resulting in CI failure. Removing this config as it does not
add any value in esp32s2 context.
Ensure that newly spawned task stack (dynamic) is getting freed up before
test completion and thus preventing false memory leak indication failure.
unit-test-app: add an API test_utils_task_delete
This API ensures that dynamic memory of deleted task gets freed up
before return. This helps for preventing false memory leak detections
in test failures.
Allocation of the temporary internal buffer will now repeat until a small enough buffer can be
allocated, and only fail if less than a 256 byte block of internal RAM is free.
Adds unit test for the same, and generic test utility for creating memory pressure.
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
* moved C++ examples to a new cxx folder in
examples
* added experimental C++ component
* added ESPException class to the C++ experimental
component
* added test cases for ESPException and
corresponding test macros
DISABLED_FOR_TARGETS macros are used
Partly revert "ci: disable unavailable tests for esp32s2beta"
This partly reverts commit 76a3a5fb48.
Partly revert "ci: disable UTs for esp32s2beta without runners"
This partly reverts commit eb158e9a22.
Partly revert "fix unit test and examples for s2beta"
This partly reverts commit 9baa7826be.
Partly revert "efuse: Add support for esp32s2beta"
This partly reverts commit db84ba868c.
Activated AES, RSA and SHA hardware acceleration for esp32s2 and enabled related unit tests.
Updated with changes made for ESP32 from 0a04034, 961f59f and caea288.
Added performance targets for esp32s2beta
Closes IDF-757
If we have multiple configs, we need to flash DUT with different binaries. But if we don't close DUT before apply new config, the old DUT will be reused, so new config name will not be applied.
It gave us a better performance of RSA operations. (2~11 times)
The old modexp implementation (Z = X ^ Y mod M) loaded all the data into
the hw registers and was waiting for completion, but due to
the hardware RSA implementation, the calculations always started with 4096 bit,
which took a lot of time.
Measurement results (measurements were made for keys: 2048, 3072 and 4096 bits)
(Old) - Sliding-window exponentiation (HAC 14.85):
keysize = 2048 bits
RSA key operation (performance): public [93206 us], private [280189 us]
keysize = 3072 bits
RSA key operation (performance): public [293614 us], private [858157 us]
keysize = 4096 bits
RSA key operation (performance): public [653192 us], private [1912126 us]
Instead (Old) - Sliding-window exponentiation (HAC 14.85) was implemented
(New) - Montgomery exponentiation (HAC 14.94) which showed
better performance on private and public keys.
keysize = 2048 bits
RSA key operation (performance): public [14504 us], private [149456 us]
keysize = 3072 bits
RSA key operation (performance): public [35073 us], private [392743 us]
keysize = 4096 bits
RSA key operation (performance): public [58650 us], private [787186 us]
For this reason, the old implementation was removed
and the MBEDTLS_HARDWARE_MPI option was turned on by default.
Why the MPI_INTERRUPT option is removed:
the old implementation used calculations on the hardware and
it took a lot of time (10ms - 500ms). And in order not to stand idle
while waiting for completion, an interrupt option was added.
This made it possible to carry out other tasks during the calculation,
and this one to block. The new method is free from such a drawback and
the maximum duration of one RSA HW operation does not exceed 70us (usually 2-70 μs).
This option is no longer needed.
Closes: IDF-965
The workaround for PSRAM that will occupy an SPI bus is enabled only when:
1. used on 32MBit ver 0 PSRAM.
2. work at 80MHz.
The test used to only check 32MBit by the config option, but for PSRAM
on Wrover-B module seems to use a newer version of 32MBit PSRAM. So it
expects the workaround to be enabled, but actually not.
This commit split the unit test into two parts:
1. check all SPI buses are available, for all configs except psram_hspi
and psram_vspi, run on regular runners (including Wrover and Wrover-B).
a hidden option is enabled so that the compiler knows it's not building
psram_hspi or psram_vspi.
2. check the specified bus are acquired, for config psram_hspi and
psram_vspi. This only run on special runner (legacy Wrover module).
DEFAULT_CPU_FREQ and ULP_COPROC_ENABLED options have chip-specific
names, and should be set in a chip-specific sdkconfig.defaults file.
This commit also changes the default CPU frequency for ESP32S2 unit
tests to 240 MHz.
Bug was this sequence:
1. old sdkconfig file has some settings (maybe target=esp32s2beta)
2. idf.py builds a new sdkconfig.defaults file with full new settings
3. new settings includes something that conflicts with the old settings (for example,
CONFIG_IDF_TARGET=esp32 and BT_ENABLE=y)
4. confgen tries to apply the new "defaults" to the existing sdkconfig, settings end up a mix of both due to the conflicts
Fix is to generate the sdkconfig file directly.
Since pyyaml 5.1 yaml.load without specifing loader is deprecated
Details: https://msg.pyyaml.org/load
To keep code compatible with older versions of pyyaml
and keep best perfomance CLoader with fallback to Loader is used.
The build system automatically determines offsets of partitions from
the partition table, so no manual changes are needed. Instead, add a
note that partition offsets may need to be updated when increasing
the bootloader size.
We could split cases of same config into multiple binaries as we have limited rom space. So we should regard those configs like `default` and `default_2` as the same config.
