Commit Graph

371 Commits

Author SHA1 Message Date
morris
753a929525 global: fix sign-compare warnings 2021-01-12 14:05:08 +08:00
Angus Gratton
edac64b703 Merge branch 'feature/c3_master_unit_test' into 'master'
C3: build unit tests for C3

See merge request espressif/esp-idf!11856
2021-01-11 18:11:06 +08:00
Marius Vikhammer
9c8e4fd4c5 C3: build and run unit tests
Enable building and running of unit tests in CI for C3 as well as fix
related compile errors

Also enables building of C3 test apps
2021-01-11 11:34:37 +08:00
Cao Sen Miao
228a819a42 spi_flash: idf repo stuff tobe consistent with that in rom 2021-01-08 18:36:23 +08:00
Michael (XIAO Xufeng)
56cdf4268f Merge branch 'ci/alternative_flash_performance' into 'master'
ci: only run flash performance test on specified runners

Closes IDF-2520

See merge request espressif/esp-idf!11673
2021-01-04 15:35:53 +08:00
Ivan Grokhotkov
7f3b16a99d freertos: always enable static allocation
to use it for newlib locks
2020-12-29 16:18:04 +01:00
Angus Gratton
c3ba995f2c Merge branch 'ci/ccomp_performance_tests' into 'master'
unit_test: Refactor all performance tests that rely on cache compensated timer

See merge request espressif/esp-idf!11709
2020-12-24 13:44:52 +08:00
Michael (XIAO Xufeng)
d5e1f43175 Merge branch 'feature/support_ext_flash_c3' into 'master'
esp_flash: support external flash on C3

Closes IDF-2123

See merge request espressif/esp-idf!11648
2020-12-24 10:30:20 +08:00
Cao Sen Miao
83f6eaf0d2 ci: make flash performance test alternative 2020-12-22 16:46:04 +08:00
Marius Vikhammer
0a95151a75 unit_test: Refactor all performance tests that rely on cache compensated timer
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.

This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
2020-12-22 18:56:24 +11:00
Michael (XIAO Xufeng)
ad6ed3fd2e mmap: fixed the issue mmap cannot be called with pointers to psram 2020-12-22 13:42:42 +08:00
Michael (XIAO Xufeng)
7f3e61cf63 esp_flash: add support for external flash on C3 2020-12-22 13:31:04 +08:00
Angus Gratton
06ec032c0c spi_flash: Simplify init-time size check 2020-12-17 15:34:13 +11:00
Cao Sen Miao
0736c91d68 soc: Remove cache constants from soc.h 2020-12-17 15:34:13 +11:00
Angus Gratton
d4c9a45675 spi_flash: Add ESP32-C3 support
Based on internal commit 3ef01301fff
2020-12-17 15:34:13 +11:00
Jakob Hasse
00819a3022 NVS flash: host-based unit test of nvs::Page
* General tests like page loading from flash
* Rough test of fixed-size data types
* Rough test of blob read
* Added coverage target in cmake, also accessible
  via `idf.py coverage`
* Fixed unsigned comparison in comp. enum table
* introducing temporary LINUX_TARGET define
2020-12-14 18:53:14 +08:00
Jakob Hasse
c233ce0449 spi_flash: mocking should be possible now
The following three headers will be mockes:
* esp_flash.h
* esp_spi_flash.h
* esp_partition.h
* counter functions live in own header
* add spi_flash sim dir for esp_err.h to Unity
* modified gen_esp_err_to_name.py to ignore
  sim/ dir in spi_flash component

Add cmock .yaml config file
Add spi hal header until soc can mock the hal
  layer as well.
2020-12-14 18:53:14 +08:00
Jakob Hasse
52093fa4ef linux: added linux target
* add toolchain file
* add linux to preview targets
* add stub for dfu number in cmake
* excluded unity runner per default
* Added esp_attr.h and esp_partition.h linux stubs
* component.cmake check list for emptyness
* added switch for linux in unity cmake file
* Added Linux host example app
2020-12-14 18:53:14 +08:00
Jakob Hasse
60dfd87e65 SPI Flash: fix doc error in esp_partition.h 2020-12-10 17:03:56 +08:00
Cao Sen Miao
eeddd44d0a esp_flash: update document to reflect the restrictions of mmap/cache 2020-12-04 11:10:43 +08:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Cao Sen Miao
a610b3ac42 spi_flash: add a block of flash chip supports in the document 2020-11-24 15:46:53 +08:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Angus Gratton
1a35b5ac9b Merge branch 'feat/esp_flash_yield_refactor' into 'master'
esp_flash: refactor to support various type of yield

See merge request espressif/esp-idf!10425
2020-11-12 16:23:02 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Angus Gratton
e82eac4354 cmake: Apply cmakelint fixes 2020-11-11 07:36:35 +00:00
Michael (XIAO Xufeng)
7ddfcfb8d2 esp_flash_test: improve unit test
From now on, we have two tags for esp_flash tests:

- [esp_flash] for main flash chip only tests
- [esp_flash_3] for tests with external flash chips

To Run all tests, type `[esp_flash`; to run tests for main flash chip
only, type `[esp_flash].
2020-11-10 19:05:28 +08:00
Michael (XIAO Xufeng)
8ae09194ac esp_flash: refactor to support various type of yield
There is a periodically yield in the esp_flash driver, to ensure the
cache will not be disabled for too long on ESP32.

On ESP32-S2 and later, we need to support more different kind of yield:

1. polling conditions, including timeout, SW read request, etc.
2. wait for events, including HW done/error/auto-suspend, timeout
semaphore, etc.

The check_yield() and yield() is separated into two parts, because we
may need to insert suspend, etc. between them.
2020-11-10 19:05:22 +08:00
Michael (XIAO Xufeng)
d48c4e1da7 spi_flash_test: workaround for broken ROM API after new API calls. 2020-10-29 18:21:44 +08:00
Michael (XIAO Xufeng)
b4c3718e39 flash_test: test 32bit address region if chip size meet 2020-10-29 18:21:27 +08:00
Michael (XIAO Xufeng)
3bacf35310 esp_flash: support high capacity flash chips (32-bit address) 2020-10-29 18:20:11 +08:00
Renz Bagaporo
79887fdc6c soc: descriptive part occupy whole component 2020-10-28 07:21:29 +08:00
Michael (XIAO Xufeng)
2a329df051 Merge branch 'feat/spi_flash_qio_test' into 'master'
spi_flash: add unit tests for qio mode

See merge request espressif/esp-idf!8303
2020-10-27 12:24:05 +08:00
Renz Bagaporo
21e46d5b3c ci: use actual esp_system headers for host test 2020-10-22 19:42:34 +08:00
Renz Bagaporo
b3a7c6e27e components: remove some unneeded headers from source files 2020-10-22 19:37:10 +08:00
Michael (XIAO Xufeng)
3c167497ad Merge branch 'bugfix/esp_flash_erase_timeout' into 'master'
esp_flash: change timeout threshold and can close timeout

Closes IDF-2023

See merge request espressif/esp-idf!10138
2020-10-12 12:49:36 +08:00
Cao Sen Miao
b9f6efd99a esp_flash: change timeout threshold and can close timeout 2020-10-12 10:43:25 +08:00
Cao Sen Miao
98cb2e5af3 spi_flash: add a unit test for HSPI on esp32s2 2020-10-09 20:57:00 +08:00
Michael (XIAO Xufeng)
fe37db3271 esp_flash: fix the incorrect check_idle logic in LL and chip_driver 2020-10-02 05:34:36 +00:00
Cao Sen Miao
f448e97fea flash:patch for clearing WEL in ROM 2020-09-28 12:53:06 +08:00
Jiang Jiang Jian
b626e306da Merge branch 'bugfix/can_mmap_after_get_enough_free_mmu_pages' into 'master'
flash_mmap: can mmap after get enough free MMU pages

Closes IDFCI-49 and IDFCI-84

See merge request espressif/esp-idf!9728
2020-09-23 21:03:53 +08:00
jiangguangming
28145e0894 support flash instr and rodata copy to SPIRAM 2020-09-22 15:15:03 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
Cao Sen Miao
d7e50c6457 spi_flash:bringup some flash supports for esp32s3 2020-09-22 15:15:03 +08:00
jiangguangming
052f88f1d1 flash_mmap: restore interrupt and cache before err return 2020-09-21 07:37:50 +00:00
jiangguangming
61e341e791 flash_mmap: can mmap after get enough free MMU pages 2020-09-21 07:37:50 +00:00
Michael (XIAO Xufeng)
4e287a09fe spi_flash: add unit tests for qio mode 2020-09-20 01:57:14 +08:00
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
Ivan Grokhotkov
96db25c861 Merge branch 'feature/nvs_encryption_s2' into 'master'
NVS: using esp_partition API

Closes IDF-1340 and IDF-858

See merge request espressif/esp-idf!8683
2020-09-16 02:12:54 +08:00
Jakob Hasse
aca9ec28b3 NVS: using esp_partition API
* partition api changed from spi_flash* API to
  esp_partition* API and is abstracted as a C++
  interface.
* The old nvs encryption is still possible
* changed default unit test app partition table
* Partitions coming from esp_partition API are
  checked for generic flash encryption. If yes,
  an error is returned since generic flash
  encryption isn't compatible with nvs
  encryption
* esp32, esp32s2 tests don't require nvs_flash
  but mbedtls now

Closes IDF-1340
Closes IDF-858
2020-09-14 10:34:34 +08:00