Commit Graph

14 Commits

Author SHA1 Message Date
jiangguangming
ae04518a32 spi_flash: make spiflash compatible with ESP32C3 and ESP32S3 ROM 2021-03-12 17:31:13 +08:00
Cao Sen Miao
f3e79ca166 spi_flash(c3): add boya chip support for suspend feature 2021-01-25 11:14:06 +08:00
Cao Sen Miao
9905da46e0 spi_flash: Add auto suspend mode on esp32c3 2021-01-25 11:14:02 +08:00
KonstantinKondrashov
60e58eaddb spi_flash: Add auto-suspend mode for ESP32-S2
Uses HW auto_wait_idle, HW auto_suspend and SW resume
2021-01-25 11:13:38 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Michael (XIAO Xufeng)
3bacf35310 esp_flash: support high capacity flash chips (32-bit address) 2020-10-29 18:20:11 +08:00
Marius Vikhammer
b2f390df01 hal: update link to HAL readme.md
The HAL readme was moved during refactoring, but links were not updated.
2020-09-11 15:48:08 +08:00
Michael (XIAO Xufeng)
c796bd5e63 esp_flash: refactor to make host driver function a const table
This is also part of ESP32-S3 ROM changes
2020-07-13 03:10:00 +08:00
Michael (XIAO Xufeng)
a9c8895bb2 esp_flash: refactor to be compatible with the latest ROM
Including:
1. Change the write bytes/read bytes parameter in the host driver into slicers to meet the requirements of complicated cases.
2. Refactor the esp_flash_api code a bit so that we can use the code in the ROM laster
3. Provide get_temp_buffer and release_temp_buffer in the os_functions when the buffer passed by application cannot be used directly.
4. Make timeout of operations configurable in the chip_driver.
5. Make dummy number configurable.
2020-07-12 02:09:45 +08:00
Renz Christian Bagaporo
e6ad330018 ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation
Otherwise IRAM usage is too high in this example.
2019-11-28 09:20:00 +08:00
Michael (XIAO Xufeng)
571864e8ae esp_flash: fix set qe bit and write command issues
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
2019-10-14 17:25:58 +08:00
Michael (XIAO Xufeng)
511820820e esp_flash: fix the coredump issue
During coredump, dangerous-area-checking should be disabled, and cache
disabling should be replaced by a safer version.

Dangerous-area-checking used to be in the HAL, but it seems to be more
fit to os functions. So it's moved to os functions. Interfaces are
provided to switch between os functions during coredump.
2019-09-14 17:01:36 +08:00
Michael (XIAO Xufeng)
e947522f38 esp_flash: improve the comments a bit 2019-08-08 23:18:01 +08:00
Michael (XIAO Xufeng)
1036a091fe spi_flash: support working on differnt buses and frequency 2019-06-18 06:32:52 +00:00