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spi_flash: make spiflash compatible with ESP32C3 and ESP32S3 ROM
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@ -189,6 +189,11 @@ struct spi_flash_host_driver_s {
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*/
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esp_err_t (*flush_cache)(spi_flash_host_inst_t* host, uint32_t addr, uint32_t size);
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/**
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* Suspend check erase/program operation, reserved for ESP32-C3 and ESP32-S3 spi flash ROM IMPL.
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*/
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void (*check_suspend)(spi_flash_host_inst_t *host);
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/**
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* Resume flash from suspend manually
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*/
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@ -20,10 +20,11 @@ void spi_flash_hal_disable_auto_resume_mode(spi_flash_host_inst_t *host);
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void spi_flash_hal_disable_auto_suspend_mode(spi_flash_host_inst_t *host);
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void spi_flash_hal_setup_auto_resume_mode(spi_flash_host_inst_t *host);
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#endif //SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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#include "spi_flash_hal_common.inc"
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#ifndef CONFIG_SPI_FLASH_ROM_IMPL
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#include "spi_flash_hal_common.inc"
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// HAL for
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// - MEMSPI
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// - SPI1~3 on ESP32/S2/S3/C3
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@ -93,6 +94,19 @@ esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_inst_t *host, bool wp)
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return ESP_OK;
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}
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#else // defined CONFIG_SPI_FLASH_ROM_IMPL
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static inline spi_dev_t *get_spi_dev(spi_flash_host_inst_t *host)
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{
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return ((spi_flash_hal_context_t*)host)->spi;
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}
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static inline int get_host_id(spi_flash_host_inst_t* host)
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{
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spi_dev_t *dev = get_spi_dev(host);
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return spi_flash_ll_hw_get_id(dev);
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}
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#endif // !CONFIG_SPI_FLASH_ROM_IMPL
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uint32_t spi_flash_hal_check_status(spi_flash_host_inst_t *host)
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@ -35,6 +35,7 @@
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.configure_host_io_mode = spi_flash_hal_configure_host_io_mode, \
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.poll_cmd_done = spi_flash_hal_poll_cmd_done, \
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.flush_cache = memspi_host_flush_cache, \
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.check_suspend = NULL, \
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.resume = spi_flash_hal_resume, \
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.suspend = spi_flash_hal_suspend,\
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.sus_setup = spi_flash_hal_setup_read_suspend,\
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@ -61,6 +61,7 @@ static const spi_flash_host_driver_t esp_flash_gpspi_host = {
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.configure_host_io_mode = spi_flash_hal_gpspi_configure_host_io_mode,
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.poll_cmd_done = spi_flash_hal_gpspi_poll_cmd_done,
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.flush_cache = NULL,
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.check_suspend = NULL,
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.resume = spi_flash_hal_resume,
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.suspend = spi_flash_hal_suspend,
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};
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