Commit Graph

59 Commits

Author SHA1 Message Date
Ricardo Quesada
f21a43b622 fix(uart): add missing include for rom/uart.h
Without this include it fails to compile with this error:

```
esp/esp-idf-v5.2/components/esp_rom/include/esp32/rom/uart.h:262:32: error: implicit declaration of function 'UART_STATUS_REG' [-Werror=implicit-function-declaration]
  262 |         status = READ_PERI_REG(UART_STATUS_REG(uart_no));
```

Merges https://github.com/espressif/esp-idf/pull/13025
2024-03-01 14:36:50 +08:00
Jakob Hasse
a6cbf68991 compiler: replaced noreturn by __noreturn__ in header files
* noreturn may be replaced by third-party macros,
  rendering it ineffective

* Closes https://github.com/espressif/esp-idf/issues/11339
2023-05-18 12:49:40 +08:00
Gustavo Henrique Nihei
50145ed179 esp_rom: Remove STATUS struct in favor of ETS_STATUS
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-16 01:50:21 +08:00
Alexey Lapshin
84ff4d6e37 esp_rom: always inline cache.h functions for esp32 2023-02-22 05:33:03 +00:00
jiangguangming
7c0c5481c8 esp_rom: update rom gpio.h
Closes https://github.com/espressif/esp-idf/issues/10205
2022-12-14 15:14:38 +08:00
Omar Chebib
cd21058097 C/Cxx: unify static assertions with the macro ESP_STATIC_ASSERT
Closes https://github.com/espressif/esp-idf/issues/9938
2022-11-21 16:18:08 +08:00
jiangguangming
08fd77a09a move {target}/rom/miniz.h to a common miniz.h
- Move {target}/rom/miniz.h to common miniz.h
- Add ESP_ROM_HAS_MZ_CRC32 for ESP32/S2/S3/C3/H4
- Alias mz_crc32 to crc32_le if chips not support ESP_ROM_HAS_MZ_CRC32

Closes https://github.com/espressif/esp-idf/issues/10177
2022-11-15 15:39:39 +08:00
KonstantinKondrashov
1f9260d790 all: Apply new version logic (major * 100 + minor) 2022-11-03 08:36:23 +00:00
Marius Vikhammer
acc8b8ee0a esp-rom: fixed error in miniz header documention for tdefl_init
Closes https://github.com/espressif/esp-idf/issues/8435
2022-08-31 11:36:56 +08:00
morris
b82d6ce928 md5_hash: fix copyright checker 2022-08-29 15:40:37 +08:00
Marius Vikhammer
cfbe0a035b esp-rom: add missing spi-flash ROM API functions
Added symbols for the SPI flash API which we export from the ROM interface,
deleted functions which are not exported.

Closes https://github.com/espressif/esp-idf/issues/1212
2022-08-08 16:34:10 +08:00
wanlei
bb5a95f1aa soc: fix register header files not self-contain 2022-07-29 11:18:06 +08:00
Jakob Hasse
f8b5ed5d6c refactor (soc, esp_rom)!: removed target-specific ROM dependencies 2022-07-05 13:57:58 +08:00
KonstantinKondrashov
ac4c7d99fe dport: Move DPORT workaround to G0 2022-05-31 13:44:18 +08:00
morris
869bed1bb5 soc: don't expose unstable soc header files in public api 2022-01-06 23:10:22 +08:00
Cao Sen Miao
d397464fc4 spi_flash: refactor spi_flash.h to esp_rom_spiflash.h but keep the content in spi_flash.h 2021-12-30 14:12:31 +08:00
Cao Sen Miao
b0decda1e3 bootloader: move bootloader flash support to isolate folders 2021-12-30 14:05:12 +08:00
Cao Sen Miao
3a4db97cec spi_flash: move patch files to common rom patch folder 2021-12-30 14:05:12 +08:00
Cao Sen Miao
3dd1cfea18 spi_flash: refactor spi_flash.h to decline duplicated code 2021-12-30 14:05:12 +08:00
Mahavir Jain
f667b1039b Fix copyright headers for few include files 2021-11-30 22:25:33 +05:30
lovyan03
cb91b51c52 bugfix: Conflicting declaration error with include<esp_efuse.h>, and Unified secure_boot.h include guard to "pragma once". 2021-11-30 15:46:49 +09:00
Cao Sen Miao
c29b3e2e36 spi_flash: move the unlock patch to bootloader and add support for GD 2021-07-29 10:46:33 +08:00
morris
1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Angus Gratton
6a29b45bd4 secure boot v2: Fix issue checking multiple signature blocks on OTA update 2021-03-15 12:30:20 +00:00
KonstantinKondrashov
95564b4687 secure_boot: Secure Boot V2 verify app signature on update (without Secure boot)
- ESP32 ECO3, ESP32-S2/C3/S3
2021-03-15 12:30:20 +00:00
morris
0f5d1c1c46 rtc: supported disable rom log temporarily 2021-02-22 20:56:43 +08:00
Cao Sen Miao
c1b41ece32 flash_encryption: Quick fixed the issue that block when flash_encryption_write, Related https://github.com/espressif/esp-idf/issues/6322, Related https://github.com/espressif/esp-idf/issues/6254 2021-02-05 20:10:42 +08:00
Angus Gratton
a5aac93051 esp_rom: Small changes for esp32c3 support
Updated from internal commit 6d894813
2020-12-24 13:40:01 +11:00
Marius Vikhammer
457ce080ae AES: refactor and add HAL layer
Refactor the AES driver and add HAL, LL and caps.

Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
Angus Gratton
b68094199f esp_rom: Add initial ESP32-C3 support
From internal commit 7761d6e8
2020-11-30 11:12:56 +11:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit)
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
Ivan Grokhotkov
48f27cb5ab Merge branch 'feature/esp32_ulp_allow_8kb' into 'master'
esp32: allow up to 8 kB of ULP program size

Closes IDFGH-1772

See merge request espressif/esp-idf!10727
2020-10-20 04:08:57 +08:00
Michael (XIAO Xufeng)
647dea9395 soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
2020-10-17 16:10:15 +08:00
Marius Vikhammer
949fb8e63a SHA: add HAL layer and refactor driver
Add a LL and HAL layer for SHA.
2020-10-09 08:24:08 +00:00
Ivan Grokhotkov
ef10c2576f esp32: allow up to 8 kB of ULP program size
The remaining 4 kB had been reserved for storing RF calibration and
BT stack state since 4e092be6. However, these features never got
implemented. If we ever need to place RF related data into RTC slow
memory, we can do this by creating a variable with RTC_NOINIT_ATTR
instead.

Closes https://github.com/espressif/esp-idf/issues/3993
2020-10-05 11:41:39 +02:00
Angus Gratton
033f49f974 Merge branch 'bugfix/cpp_header_rom_secure_boot' into 'master'
Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.

Closes IDFGH-3998

See merge request espressif/esp-idf!10528
2020-09-21 15:51:03 +08:00
Supreet Deshpande
0e940c80d4 Secure Boot: Fixes the cpp macro in esp32 secure boot rom functions.
Closes https://github.com/espressif/esp-idf/issues/5878
2020-09-20 22:50:44 +05:30
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
Fu Hanxi
6885421976 CI: add size info for binaries 2020-07-21 16:00:05 +08:00
morris
a34409cffc esp_rom: extract common CRC apis into esp_rom_crc.h 2020-06-23 16:40:14 +08:00
morris
5d0860f2e8 fix broken CONFIG_LEGACY_INCLUDE_COMMON_HEADERS 2020-04-20 14:01:09 +08:00
Supreet Deshpande
a9ccc5e5c8 feat/secure_boot_v2: Adding secure boot v2 support for ESP32-ECO3 2020-02-25 01:28:22 +05:30
Michael (XIAO Xufeng)
278634dcbd sdspi: support crc16_be for esp32s2 2020-02-12 15:15:46 +08:00
Angus Gratton
438d513a95 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-16 16:18:48 +10:00
Angus Gratton
f23b3fdbe4 rom: Add warnings for miniz functions that won't work due to missing malloc
Closes https://github.com/espressif/esp-idf/issues/4024
2019-09-06 11:01:34 +10:00
Angus Gratton
8f74271d5d esp_rom: Fail immediately if the wrong SoC's header file is included 2019-08-12 16:57:40 +10:00
Angus Gratton
04ae56806c Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 15:26:58 +10:00
Angus Gratton
24d26fccde Merge branch 'master' into feature/esp32s2beta_update 2019-08-08 13:44:24 +10:00
Anton Maklakov
afbaf74007 tools: Mass fixing of empty prototypes (for -Wstrict-prototypes) 2019-08-01 16:28:56 +07:00