Marius Vikhammer
51169b0e0c
AES/SHA: use GDMA driver instead of LL
2021-01-19 11:02:51 +08:00
Marius Vikhammer
0713e93b8f
TWAI: bringup for S3 and C3
2021-01-14 20:30:31 +08:00
morris
e6d23a35ec
gdma: dynamic alloc DMA channels
2021-01-13 10:52:27 +08:00
Chen Jian Xing
5b44295cb9
esp_wifi: fix esp32c3 code issues
...
1. enable wifi clk and rm dport header
2.syn phy_init_data.h from esp32
2021-01-10 16:16:28 +08:00
Angus Gratton
5b68cf9de4
Merge branch 'feature/c3_ds' into 'master'
...
ESP32-C3 Digital Signature, HAL layer for DS.
Closes IDF-2111
See merge request espressif/esp-idf!10813
2021-01-07 13:07:28 +08:00
morris
7a71cedf87
interrupt: filter out reserved int number by decoding risc-v JAL instruction
2021-01-05 15:39:46 +08:00
morris
9e7d2c0065
esp32c3: format and clean up interrupt and os port code
2021-01-05 15:39:46 +08:00
Felipe Neves
5d316ac142
interrupt: added INTC FLEXIBLE capabillity to esp32c3 CPU caps
2021-01-05 15:39:46 +08:00
Jakob Hasse
e532a29288
[Peripheral/Security] DS peripheral driver
2021-01-05 12:26:59 +08:00
chaijie
d505474f78
1. Fix CPU switch to 160M issue;
...
2. increase lightsleep voltage to make sure wakeup successfully;
3. add judgement code to whether wait or not when switch CPU frequency.
2020-12-30 12:32:31 +08:00
Marius Vikhammer
eb788deb03
esp_hw_support: merge C3 changes to master
...
Merge RTC related C3 changes to master
2020-12-30 12:20:41 +08:00
Marius Vikhammer
1b6891c5d8
mbedtls: merge changes from C3
2020-12-29 10:56:13 +08:00
Angus Gratton
b7f4c46a82
soc: Update esp32c3 soc headers
...
From internal commit 6d894813
2020-12-24 10:47:34 +11:00
Angus Gratton
6d6510c39b
soc: Move esp32c3 soc_memory_layout.c to soc component
...
Was incorrectly placed in esp_hw_support
2020-12-23 11:49:16 +11:00
Armando
2d37bfa126
driver: Add adc_digi single conversion mode
...
- add lock for single read and continuous read APIs
- update onetime read start singal delay for hardware limitation[*]
- move adc_caps to soc_caps.h
- update license dates
[*] There is a hardware limitation. If the APB clock frequency is high, the
step of this reg signal: ``onetime_start`` may not be captured by the
ADC digital controller (when its clock frequency is too slow). A rough
estimate for this step should be at least 3 ADC digital controller
clock cycle.
2020-12-23 09:53:24 +11:00
Angus Gratton
fa892eb017
soc: Explain units for rtc_clk_cal() function, fix typo
2020-12-23 09:53:24 +11:00
Cao Sen Miao
e338a2e3df
rtc: add function to en/disable the rtc clock
2020-12-23 09:53:24 +11:00
Angus Gratton
f09b8ae7a4
driver: Add esp32c3 ADC driver
...
Based on internal commit 3ef01301fffa552d4be6d81bc9d199c223224305
2020-12-23 09:53:24 +11:00
Angus Gratton
27a9cf861e
driver: Add esp32c3 drivers (except ADC/DAC) and update tests
...
Some ESP32-C3 drivers are still pending.
Based on internal commit 3ef01301fffa552d4be6d81bc9d199c223224305
2020-12-23 09:53:24 +11:00
Cao Sen Miao
0736c91d68
soc: Remove cache constants from soc.h
2020-12-17 15:34:13 +11:00
Marius Vikhammer
457ce080ae
AES: refactor and add HAL layer
...
Refactor the AES driver and add HAL, LL and caps.
Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
Armando
d393699ab6
uart: bringup on esp32c3
2020-11-30 15:23:15 +11:00
Angus Gratton
c29d93986d
soc: Add initial ESP32-C3 support
...
From internal commit 7761d6e8
2020-11-30 11:12:56 +11:00
