This commit adds the ability to use LP ROM functions from the LP core.
This allows the LP core code to utilize standard functions such as those
for printing from the LP ROM and therefore help reduce the code size on
the LP core.
There are redefinition compilation warnings for the register operation
macros when a ULP program was compiled which included soc.h before
ulp_riscv_register_ops.h. This commit fixes the issues by delegating the
exclusion macro to the CMakeLists.txt file.
Closes: https://github.com/espressif/esp-idf/issues/12116
This commit adds a minimal logging driver for the LP core. The logging
driver provides a printf function which is built on top of the LP UART
driver. The commit also adds an example to demonstrate how to use print
statements in an LP core program.
This commit adds a UART driver for the LP core to interact with the LP
UART. The commit also adds an example to demonstrate the usage of the LP
UART driver.
This commit adds a driver for reading the touch sensor from the ULP
RISC-V core during sleep. The commit also adds an example to demonstrate
this feature.
Closes https://github.com/espressif/esp-idf/issues/10480
This commit adds support for the LP I2C peripheral driver to be used by
the LP core. An example is also added to demonstrate the usage of the LP
I2C peripheral from the LP core.
This commit adds support for using the RTC I2C peripheral on the ULP
RISC-V core for esp32s2 and esp32s3. It also adds an example to demonstrate the
usage of the RTC I2C peripheral.
This commit also modifies the rtc_i2c register structure files to enable
the use of bitfields in the ULP RISC-V RTC I2C driver.
There are multiple changes in this commit:
1. Unify the RISC-V and ULP-FSM code paths in esp32ulp_mapgen.py.
It seems that these were originally introduced because `nm` output
for the RISC-V case contained symbol sizes, while for the ULP-FSM
no symbol sizes were reported. This makes sense, because the
ULP-FSM object files are produced from assembly source, symbol
sizes have to be added manually using the .size directive.
In the case of RISC-V, the object files are built from C sources
and the sizes are automatically added by the compiler.
Now 'posix' output format is used for both RISC-V and ULP-FSM.
2. Move BASE_ADDR out of esp32ulp_mapgen.py. This now has to be passed
from CMake, which should make it easier to modify if a new chip
with a different RTC RAM base address is added.
3. Add C++ guards to the generated header file.
4. Switch from optparse to argparse for similarity with other IDF
tools.
5. Add type annotations.
* "dummy loop to force pre-processed linker file generation" seems to
be unnecessary. It looks like the idea was copied from the
dependency of ULP-FSM preprocessed source files on the LD script.
* Can use add_dependencies instead of
set_target_properties(...LINK_DEPENDS...) which is more readable
* Use target_link_options instead of target_link_libraries, which is
supported starting from CMake 3.13. Unlike target_link_libraries,
it doesn't require manually quoting the pats.
the variable "IDF_TARGET" is only used under a if clause
"if(ULP_C0CPU_IS_RISCV)". while building a non-riscv target,
there will be a cmake warning:
CMake Warning:
Manually-specified variables were not used by the project:
IDF_TARGET
This updates the minimal supported version of CMake to 3.16, which in turn enables us to use more CMake features and have a cleaner build system.
This is the version that provides most new features and also the one we use in our latest docker image for CI.
This commit enables ULP FSM support for esp32s3 and updates ULP FSM code
flow for other chips.
It adds C Macro support for the ULP FSM instruction set on esp32s2 and
esp32s3.
The unit tests are also updated to test ULP FSM on ep32s2 and esp32s3.
This commit refactors the ulp component.
Files are now divided based on type of ulp, viz., fsm or risc-v.
Files common to both are maintained in the ulp_common folder.
This commit also adds menuconfig options for ULP within the ulp
component instead of presenting target specific configuations for ulp.
riscv32-esp-elf toolchain (used for ESP32-C3) can also be used for
ESP32-S2 RISC-V ULP coprocessor.
This removes the riscv-none-embed-gcc toolchain which was originally
used for the ULP, and updates the docs and CMake files to use
riscv32-esp-elf.
Some flags are cleaned up and workarounds removed from CMake toolchain
file.
