lp-core-uart: Added LP UART support for LP core

This commit adds a UART driver for the LP core to interact with the LP
UART. The commit also adds an example to demonstrate the usage of the LP
UART driver.

components/ulp/CMakeLists.txt

@@ -43,7 +43,8 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
         "lp_core/lp_core.c"
         "lp_core/shared/ulp_lp_core_memory_shared.c"
         "lp_core/shared/ulp_lp_core_lp_timer_shared.c"
-        "lp_core/lp_core_i2c.c")
+        "lp_core/lp_core_i2c.c"
+        "lp_core/lp_core_uart.c")
 
     list(APPEND includes
         "lp_core/include"

components/ulp/cmake/CMakeLists.txt

@@ -85,7 +85,10 @@ elseif(ULP_COCPU_IS_LP_CORE)
     "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c"
     "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_startup.c"
     "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_utils.c"
-    "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_i2c.c")
+    "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_i2c.c"
+    "${IDF_PATH}/components/hal/uart_hal_iram.c"
+    "${IDF_PATH}/components/hal/uart_hal.c"
+    "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_uart.c")
 
     target_link_options(${ULP_APP_NAME} PRIVATE "-nostartfiles")
     target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments")
@@ -96,6 +99,7 @@ elseif(ULP_COCPU_IS_LP_CORE)
     target_sources(${ULP_APP_NAME} PRIVATE ${ULP_S_SOURCES})
     target_include_directories(${ULP_APP_NAME} PRIVATE "${IDF_PATH}/components/ulp/lp_core/lp_core/include"
                                                        "${IDF_PATH}/components/ulp/lp_core/shared/include")
+    target_compile_definitions(${ULP_APP_NAME} PRIVATE IS_ULP_COCPU)
 
 else()
     foreach(ulp_s_source ${ULP_S_SOURCES})

components/ulp/lp_core/include/lp_core_uart.h

@@ -0,0 +1,89 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "hal/uart_types.h"
+#include "hal/gpio_types.h"
+
+/**
+ * @brief LP UART IO pins configuration
+ */
+typedef struct {
+    gpio_num_t tx_io_num;               /*!< GPIO pin for UART Tx signal. Only GPIO#5 can be used as the UART Tx pin */
+    gpio_num_t rx_io_num;               /*!< GPIO pin for UART Rx signal. Only GPIO#4 can be used as the UART Rx pin */
+    gpio_num_t rts_io_num;              /*!< GPIO pin for UART RTS signal. Only GPIO#2 can be used as the UART RTS pin */
+    gpio_num_t cts_io_num;              /*!< GPIO pin for UART CTS signal. Only GPIO#3 can be used as the UART CTS pin */
+} lp_core_uart_pin_cfg_t;
+
+/**
+ * @brief LP UART protocol configuration
+ */
+typedef struct {
+    int baud_rate;                      /*!< LP UART baud rate */
+    uart_word_length_t data_bits;       /*!< LP UART byte size */
+    uart_parity_t parity;               /*!< LP UART parity mode */
+    uart_stop_bits_t stop_bits;         /*!< LP UART stop bits */
+    uart_hw_flowcontrol_t flow_ctrl;    /*!< LP UART HW flow control mode (cts/rts) */
+    uint8_t rx_flow_ctrl_thresh;        /*!< LP UART HW RTS threshold */
+} lp_core_uart_proto_cfg_t;
+
+/**
+ * @brief LP UART configuration parameters
+ */
+typedef struct {
+    lp_core_uart_pin_cfg_t uart_pin_cfg;        /*!< LP UART pin configuration */
+    lp_core_uart_proto_cfg_t uart_proto_cfg;    /*!< LP UART protocol configuration */
+    lp_uart_sclk_t lp_uart_source_clk;          /*!< LP UART source clock selection */
+} lp_core_uart_cfg_t;
+
+/* Default LP UART GPIO settings */
+#define LP_UART_DEFAULT_GPIO_CONFIG()           \
+        .uart_pin_cfg.tx_io_num = GPIO_NUM_5,   \
+        .uart_pin_cfg.rx_io_num = GPIO_NUM_4,   \
+        .uart_pin_cfg.rts_io_num = GPIO_NUM_2,  \
+        .uart_pin_cfg.cts_io_num = GPIO_NUM_3,  \
+
+/* Default LP UART protocol config */
+#define LP_UART_DEFAULT_PROTO_CONFIG()                           \
+        .uart_proto_cfg.baud_rate = 115200,                      \
+        .uart_proto_cfg.data_bits = UART_DATA_8_BITS,            \
+        .uart_proto_cfg.parity = UART_PARITY_DISABLE,            \
+        .uart_proto_cfg.stop_bits = UART_STOP_BITS_1,            \
+        .uart_proto_cfg.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,    \
+        .uart_proto_cfg.rx_flow_ctrl_thresh = 0,                 \
+
+/* Default LP UART source clock config */
+#define LP_UART_DEFAULT_CLOCK_CONFIG()              \
+        .lp_uart_source_clk = LP_UART_SCLK_DEFAULT, \
+
+/* Default LP UART GPIO settings and protocol parametes */
+#define LP_CORE_UART_DEFAULT_CONFIG()               \
+    {                                               \
+        LP_UART_DEFAULT_GPIO_CONFIG()               \
+        LP_UART_DEFAULT_PROTO_CONFIG()              \
+        LP_UART_DEFAULT_CLOCK_CONFIG()              \
+    }
+
+/**
+ * @brief Initialize and configure the LP UART to be used from the LP core
+ *
+ * @note The LP UART initialization must be called from the main core (HP CPU)
+ *
+ * @param cfg           Configuration parameters
+ * @return esp_err_t    ESP_OK when successful
+ */
+esp_err_t lp_core_uart_init(const lp_core_uart_cfg_t *cfg);
+
+#ifdef __cplusplus
+}
+#endif

components/ulp/lp_core/lp_core/include/ulp_lp_core_uart.h

@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "hal/uart_types.h"
+
+/**
+ * @brief Send data to the LP UART port if there is space available in the Tx FIFO
+ *
+ * This function will not wait for enough space in the Tx FIFO to be available.
+ * It will just fill the available Tx FIFO slots and return when the FIFO is full.
+ * If there are no empty slots in the Tx FIFO, this function will not write any data.
+ *
+ * @param lp_uart_num   LP UART port number
+ * @param src           data buffer address
+ * @param size          data length to send
+ *
+ * @return              - (-1) Error
+ *                      - OTHERS (>=0) The number of bytes pushed to the Tx FIFO
+ */
+int lp_core_uart_tx_chars(uart_port_t lp_uart_num, const void *src, size_t size);
+
+/**
+ * @brief Write data to the LP UART port
+ *
+ * This function will write data to the Tx FIFO. If a timeout value is configured, this function will timeout once the number of CPU cycles expire.
+ *
+ * @param lp_uart_num   LP UART port number
+ * @param src           data buffer address
+ * @param size          data length to send
+ * @param timeout       Operation timeout in CPU cycles. Set to -1 to wait forever.
+ *
+ * @return esp_err_t    ESP_OK when successful
+ */
+esp_err_t lp_core_uart_write_bytes(uart_port_t lp_uart_num, const void *src, size_t size, int32_t timeout);
+
+/**
+ * @brief Read data from the LP UART port
+ *
+ * This function will read data from the Rx FIFO. If a timeout value is configured, then this function will timeout once the number of CPU cycles expire.
+ *
+ * @param lp_uart_num   LP UART port number
+ * @param src           data buffer address
+ * @param size          data length to send
+ * @param timeout       Operation timeout in CPU cycles. Set to -1 to wait forever.
+ *
+ * @return              - (-1) Error
+ *                      - OTHERS (>=0) The number of bytes read from the Rx FIFO
+ */
+int lp_core_uart_read_bytes(uart_port_t lp_uart_num, void *buf, size_t size, int32_t timeout);
+
+#ifdef __cplusplus
+}
+#endif

components/ulp/lp_core/lp_core/lp_core_uart.c

@@ -0,0 +1,218 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "ulp_lp_core_uart.h"
+#include "ulp_lp_core_utils.h"
+#include "soc/lp_uart_struct.h"
+#include "hal/uart_hal.h"
+
+#define LP_UART_ERR_INT_FLAG        (UART_INTR_PARITY_ERR | UART_INTR_FRAM_ERR)
+#define LP_UART_TX_INT_FLAG         (UART_INTR_TX_DONE)
+#define LP_UART_RX_INT_FLAG         (UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_OVF)
+#define LP_UART_TOUT_THRESH_DEFAULT (10U)
+#define LP_UART_FULL_THRESH_DEFAULT (10U)
+
+/* LP UART HAL Context */
+uart_hal_context_t hal = {
+    .dev = (uart_dev_t *)UART_LL_GET_HW(LP_UART_NUM_0),
+};
+
+static esp_err_t lp_core_uart_check_timeout(uint32_t intr_mask, int32_t timeout, uint32_t *ticker)
+{
+    if (timeout > -1) {
+        /* If the timeout value is not -1, delay for 1 CPU cycle and keep track of ticks */
+        ulp_lp_core_delay_cycles(1);
+        *ticker = *ticker + 1;
+        if (*ticker >= timeout) {
+            /* Disable and clear interrupt bits */
+            uart_hal_disable_intr_mask(&hal, intr_mask);
+            uart_hal_clr_intsts_mask(&hal, intr_mask);
+
+            return ESP_ERR_TIMEOUT;
+        }
+    }
+
+    return ESP_OK;
+}
+
+int lp_core_uart_tx_chars(uart_port_t lp_uart_num, const void *src, size_t size)
+{
+    (void)lp_uart_num;
+    uint32_t tx_len = 0;
+
+    /* Argument sanity check */
+    if (!src) {
+        /* Invalid input arguments */
+        return -1;
+    }
+
+    /* Nothing to do if the length is 0 */
+    if (size == 0) {
+        return 0;
+    }
+
+    /* Write the data to the Tx FIFO */
+    uart_hal_write_txfifo(&hal, src, size, &tx_len);
+
+    /* Return the number of bytes written */
+    return tx_len;
+}
+
+esp_err_t lp_core_uart_write_bytes(uart_port_t lp_uart_num, const void *src, size_t size, int32_t timeout)
+{
+    (void)lp_uart_num;
+
+    /* Argument sanity check */
+    if (!src) {
+        /* Invalid input arguments */
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    /* Nothing to do if the length is 0 */
+    if (size == 0) {
+        return ESP_OK;
+    }
+
+    /* Enable the Tx done interrupt */
+    uint32_t intr_mask = LP_UART_TX_INT_FLAG | LP_UART_ERR_INT_FLAG;
+    uart_hal_clr_intsts_mask(&hal, intr_mask);
+    uart_hal_ena_intr_mask(&hal, intr_mask);
+
+    /* Transmit data */
+    uint32_t tx_len;
+    uint32_t bytes_sent = 0;
+    int32_t remaining_bytes = size;
+    esp_err_t ret = ESP_OK;
+    uint32_t intr_status = 0;
+    uint32_t to = 0;
+
+    while (remaining_bytes > 0) {
+        /* Write to the Tx FIFO */
+        tx_len = 0;
+        uart_hal_write_txfifo(&hal, src + bytes_sent, remaining_bytes, &tx_len);
+
+        if (tx_len) {
+            /* We have managed to write some data to the Tx FIFO. Check Tx interrupt status */
+            while (1) {
+                /* Fetch the interrupt status */
+                intr_status = uart_hal_get_intsts_mask(&hal);
+                if (intr_status & LP_UART_TX_INT_FLAG) {
+                    /* Clear interrupt status and break */
+                    uart_hal_clr_intsts_mask(&hal, intr_mask);
+                    break;
+                } else if ((intr_status & LP_UART_ERR_INT_FLAG)) {
+                    /* Transaction error. Abort */
+                    return ESP_FAIL;
+                }
+
+                /* Check for transaction timeout */
+                ret = lp_core_uart_check_timeout(intr_mask, timeout, &to);
+                if (ret == ESP_ERR_TIMEOUT) {
+                    /* Timeout */
+                    uart_hal_disable_intr_mask(&hal, intr_mask);
+                    return ret;
+                }
+            }
+
+            /* Update the byte counters */
+            bytes_sent += tx_len;
+            remaining_bytes -= tx_len;
+        } else {
+            /* Tx FIFO does not have empty slots. Check for transaction timeout */
+            ret = lp_core_uart_check_timeout(intr_mask, timeout, &to);
+            if (ret == ESP_ERR_TIMEOUT) {
+                /* Timeout */
+                uart_hal_disable_intr_mask(&hal, intr_mask);
+                return ret;
+            }
+        }
+    }
+
+    /* Disable the Tx done interrupt */
+    uart_hal_disable_intr_mask(&hal, intr_mask);
+
+    return ret;
+}
+
+int lp_core_uart_read_bytes(uart_port_t lp_uart_num, void *buf, size_t size, int32_t timeout)
+{
+    (void)lp_uart_num;
+
+    /* Argument sanity check */
+    if (!buf) {
+        /* Invalid input arguments */
+        return -1;
+    }
+
+    /* Nothing to do if the length is 0 */
+    if (size == 0) {
+        return 0;
+    }
+
+    /* Set the Rx interrupt thresholds */
+    uart_hal_set_rx_timeout(&hal, LP_UART_TOUT_THRESH_DEFAULT);
+    uart_hal_set_rxfifo_full_thr(&hal, LP_UART_FULL_THRESH_DEFAULT);
+
+    /* Enable the Rx interrupts */
+    uint32_t intr_mask = LP_UART_RX_INT_FLAG | LP_UART_ERR_INT_FLAG;
+    uart_hal_clr_intsts_mask(&hal, intr_mask);
+    uart_hal_ena_intr_mask(&hal, intr_mask);
+
+    /* Receive data */
+    int rx_len = 0;
+    uint32_t bytes_rcvd = 0;
+    int32_t remaining_bytes = size;
+    esp_err_t ret = ESP_OK;
+    uint32_t intr_status = 0;
+    uint32_t to = 0;
+
+    while (remaining_bytes > 0) {
+        /* Read from the Rx FIFO
+         * We set rx_len to -1 to read all bytes in the Rx FIFO
+         */
+        rx_len = -1;
+        uart_hal_read_rxfifo(&hal, (uint8_t *)(buf + bytes_rcvd), &rx_len);
+
+        if (rx_len) {
+            /* We have some data to read from the Rx FIFO. Check Rx interrupt status */
+            intr_status = uart_hal_get_intsts_mask(&hal);
+            if ((intr_status & UART_INTR_RXFIFO_FULL) ||
+                (intr_status & UART_INTR_RXFIFO_TOUT)) {
+                /* This is expected. Clear interrupt status and break */
+                uart_hal_clr_intsts_mask(&hal, intr_mask);
+                break;
+            } else if ((intr_status & UART_INTR_RXFIFO_OVF)) {
+                /* We reset the Rx FIFO if it overflows */
+                uart_hal_clr_intsts_mask(&hal, intr_mask);
+                uart_hal_rxfifo_rst(&hal);
+                break;
+            } else if ((intr_status & LP_UART_ERR_INT_FLAG)) {
+                /* Transaction error. Abort */
+                uart_hal_clr_intsts_mask(&hal, intr_mask);
+                uart_hal_disable_intr_mask(&hal, intr_mask);
+                return -1;
+            }
+
+            /* Update the byte counters */
+            bytes_rcvd += rx_len;
+            remaining_bytes -= rx_len;
+        } else {
+            /* We have no data to read from the Rx FIFO. Check for transaction timeout */
+            ret = lp_core_uart_check_timeout(intr_mask, timeout, &to);
+            if (ret == ESP_ERR_TIMEOUT) {
+                break;
+            }
+        }
+    }
+
+    /* Disable the Rx interrupts */
+    uart_hal_disable_intr_mask(&hal, intr_mask);
+
+    /* Return the number of bytes received */
+    return bytes_rcvd;
+}

components/ulp/lp_core/lp_core_uart.c

@@ -0,0 +1,135 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "lp_core_uart.h"
+#include "driver/rtc_io.h"
+#include "soc/lp_uart_struct.h"
+#include "hal/uart_hal.h"
+#include "hal/rtc_io_types.h"
+#include "esp_clk_tree.h"
+#include "esp_private/lp_periph_ctrl.h"
+
+#define LP_UART_PORT_NUM    LP_UART_NUM_0
+#define LP_UART_TX_IDLE_NUM_DEFAULT     (0U)
+
+/* LP UART HAL Context */
+uart_hal_context_t hal = {
+    .dev = (uart_dev_t *)UART_LL_GET_HW(LP_UART_NUM_0),
+};
+
+static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
+{
+    esp_err_t ret = ESP_OK;
+
+    /* Argument sanity check */
+    if ((cfg->uart_proto_cfg.rx_flow_ctrl_thresh > SOC_LP_UART_FIFO_LEN) ||
+        (cfg->uart_proto_cfg.flow_ctrl > UART_HW_FLOWCTRL_MAX) ||
+        (cfg->uart_proto_cfg.data_bits > UART_DATA_BITS_MAX)) {
+        // Invalid config
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    /* Initialize LP UART HAL with default parameters */
+    uart_hal_init(&hal, LP_UART_PORT_NUM);
+
+    /* Get LP UART source clock frequency */
+    uint32_t sclk_freq = 0;
+    soc_module_clk_t clk_src = (soc_module_clk_t)(cfg->lp_uart_source_clk) ? (cfg->lp_uart_source_clk) : LP_UART_SCLK_DEFAULT;
+    ret = esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq);
+    if (ret != ESP_OK) {
+        // Unable to fetch LP UART source clock frequency
+        return ESP_FAIL;
+    }
+
+    /* Override protocol parameters from the configuration */
+    lp_periph_set_clk_src(LP_PERIPH_UART0_MODULE, clk_src);
+    uart_hal_set_baudrate(&hal, cfg->uart_proto_cfg.baud_rate, sclk_freq);
+    uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);
+    uart_hal_set_data_bit_num(&hal, cfg->uart_proto_cfg.data_bits);
+    uart_hal_set_stop_bits(&hal, cfg->uart_proto_cfg.stop_bits);
+    uart_hal_set_tx_idle_num(&hal, LP_UART_TX_IDLE_NUM_DEFAULT);
+    uart_hal_set_hw_flow_ctrl(&hal, cfg->uart_proto_cfg.flow_ctrl, cfg->uart_proto_cfg.rx_flow_ctrl_thresh);
+
+    /* Reset Tx/Rx FIFOs */
+    uart_hal_rxfifo_rst(&hal);
+    uart_hal_txfifo_rst(&hal);
+
+    return ret;
+}
+
+static esp_err_t lp_uart_config_io(gpio_num_t pin, rtc_gpio_mode_t direction)
+{
+    /* Initialize LP_IO */
+    esp_err_t ret = rtc_gpio_init(pin);
+    if (ret != ESP_OK) {
+        return ESP_FAIL;
+    }
+
+    /* Set LP_IO direction */
+    ret = rtc_gpio_set_direction(pin, direction);
+    if (ret != ESP_OK) {
+        return ESP_FAIL;
+    }
+
+    /* Set LP_IO function */
+    ret = rtc_gpio_iomux_func_sel(pin, 1);
+
+    return ret;
+}
+
+static esp_err_t lp_core_uart_set_pin(const lp_core_uart_cfg_t *cfg)
+{
+    esp_err_t ret = ESP_OK;
+
+    /* Argument sanity check */
+    if ((cfg->uart_pin_cfg.tx_io_num != GPIO_NUM_5) ||
+        (cfg->uart_pin_cfg.rx_io_num != GPIO_NUM_4) ||
+        (cfg->uart_pin_cfg.rts_io_num != GPIO_NUM_2) ||
+        (cfg->uart_pin_cfg.cts_io_num != GPIO_NUM_3)) {
+        // Invalid IO config
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    /* Configure Tx Pin */
+    ret = lp_uart_config_io(cfg->uart_pin_cfg.tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
+    /* Configure Rx Pin */
+    ret = lp_uart_config_io(cfg->uart_pin_cfg.rx_io_num, RTC_GPIO_MODE_INPUT_ONLY);
+    /* Configure RTS Pin */
+    ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
+    /* Configure CTS Pin */
+    ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY);
+
+    return ret;
+}
+
+esp_err_t lp_core_uart_init(const lp_core_uart_cfg_t *cfg)
+{
+    esp_err_t ret = ESP_OK;
+
+    /* Argument sanity check */
+    if (!cfg) {
+        // NULL configuration
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    /* Configure LP UART protocol parameters */
+    ret = lp_core_uart_param_config(cfg);
+    if (ret != ESP_OK) {
+        // Invalid protocol configuration
+        return ESP_FAIL;
+    }
+
+    /* Configure LP UART IO pins */
+    ret = lp_core_uart_set_pin(cfg);
+    if (ret != ESP_OK) {
+        // Invalid IO configuration
+        return ESP_FAIL;
+    }
+
+    return ret;
+}

examples/system/.build-test-rules.yml

@@ -78,6 +78,10 @@ examples/system/light_sleep:
       temporary: true
       reason: target(s) not supported yet
 
+examples/system/lp_core/lp_i2c:
+  enable:
+    - if: SOC_LP_I2C_SUPPORTED == 1
+
 examples/system/ota/advanced_https_ota:
   disable:
     - if: IDF_TARGET == "esp32h2"
@@ -173,6 +177,10 @@ examples/system/ulp/lp_core/lp_i2c:
   enable:
     - if: SOC_LP_I2C_SUPPORTED == 1
 
+examples/system/ulp/lp_core/lp_uart/lp_uart_echo:
+  enable:
+    - if: SOC_UART_LP_NUM > 0
+
 examples/system/ulp/ulp_fsm/ulp:
   disable:
     - if: SOC_ULP_FSM_SUPPORTED != 1

examples/system/ulp/lp_core/lp_uart/lp_uart_echo/CMakeLists.txt

@@ -0,0 +1,7 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.16)
+
+list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults")
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(lp_uart_echo_example)

examples/system/ulp/lp_core/lp_uart/lp_uart_echo/README.md

@@ -0,0 +1,53 @@
+| Supported Targets | ESP32-C6 |
+| ----------------- | -------- |
+
+# LP UART Echo Example
+
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+## Overview
+
+This example demonstrates the usage of the LP UART driver from the LP core by reading data written to a serial console and echoing it back while the main core is in deepsleep.
+
+## How to use example
+
+### Hardware Required
+
+To run this example, you should have an ESP32-C6 based development board and a host machine with a serial input connection.
+
+#### Pin Assignment:
+
+**Note:** The following pin assignments are used by default.
+
+|                         | Rx    | Tx    |
+| ----------------------- | ------| ------|
+| ESP32-C6                | GPIO4 | GPIO5 |
+| Host machine            | Tx    | Rx    |
+
+### Build and Flash
+
+Enter `idf.py -p PORT flash monitor` to build, flash and monitor the project.
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.
+
+Use another serial monitor program/instance such as idf.py monitor, minicom or miniterm to send and receive data from the LP core.
+
+## Example Output
+
+The log output from the serial monitor connected to the main core should indicate that the LP core and the LP UART peripheral have been successfully initialized. The main CPU would then enter deep sleep mode.
+
+```bash
+Not an LP core wakeup. Cause = 0
+Initializing...
+LP UART initialized successfully
+LP core loaded with firmware and running successfully
+Entering deep sleep...
+```
+
+The log output from the serial monitor connected to the LP core would be blank. Type using a keyboard and the monitor should echo the characters being typed.
+
+## Troubleshooting
+
+(For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you as soon as possible.)

examples/system/ulp/lp_core/lp_uart/lp_uart_echo/main/CMakeLists.txt

@@ -0,0 +1,25 @@
+# Register the component
+idf_component_register(SRCS "lp_uart_main.c"
+                       INCLUDE_DIRS ""
+                       REQUIRES ulp)
+
+#
+# ULP support additions to component CMakeLists.txt.
+#
+# 1. The LP Core app name must be unique (if multiple components use LP Core).
+set(ulp_app_name lp_core_${COMPONENT_NAME})
+#
+# 2. Specify all C files.
+#    Files should be placed into a separate directory (in this case, lp_core/),
+#    which should not be added to COMPONENT_SRCS.
+set(ulp_lp_core_sources "lp_core/main.c")
+
+#
+# 3. List all the component source files which include automatically
+#    generated LP Core export file, ${ulp_app_name}.h:
+set(ulp_exp_dep_srcs "lp_uart_main.c")
+
+#
+# 4. Call function to build ULP binary and embed in project using the argument
+#    values above.
+ulp_embed_binary(${ulp_app_name} "${ulp_lp_core_sources}" "${ulp_exp_dep_srcs}")

examples/system/ulp/lp_core/lp_uart/lp_uart_echo/main/lp_core/main.c

@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "ulp_lp_core_uart.h"
+#include "ulp_lp_core_utils.h"
+
+#define LP_UART_PORT_NUM    LP_UART_NUM_0
+
+int main (void)
+{
+    esp_err_t ret;
+    uint8_t data[1024] = {0};
+    int len = 0;
+
+    while (1) {
+        /* Read data from the LP_UART */
+        len = lp_core_uart_read_bytes(LP_UART_PORT_NUM, data, (sizeof(data) - 1), 10);
+        if (len > 0) {
+            /* Write data back to the LP_UART */
+            ret = lp_core_uart_write_bytes(LP_UART_PORT_NUM, (const char *)data, len, 500);
+            if (ret != ESP_OK) {
+                /* Error in writing. Bail */
+                continue;
+            }
+        }
+    }
+
+    return 0;
+}

examples/system/ulp/lp_core/lp_uart/lp_uart_echo/main/lp_uart_main.c

@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include "esp_sleep.h"
+#include "esp_err.h"
+#include "lp_core_main.h"
+#include "ulp_lp_core.h"
+#include "lp_core_uart.h"
+
+extern const uint8_t lp_core_main_bin_start[] asm("_binary_lp_core_main_bin_start");
+extern const uint8_t lp_core_main_bin_end[]   asm("_binary_lp_core_main_bin_end");
+
+static void lp_uart_init()
+{
+    lp_core_uart_cfg_t cfg = LP_CORE_UART_DEFAULT_CONFIG();
+
+    ESP_ERROR_CHECK(lp_core_uart_init(&cfg));
+
+    printf("LP UART initialized successfully\n");
+}
+
+static void lp_core_init(void)
+{
+    /* Set LP core wakeup source as the HP CPU */
+    ulp_lp_core_cfg_t cfg = {
+        .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU,
+    };
+
+    /* Load LP core firmware */
+    ESP_ERROR_CHECK(ulp_lp_core_load_binary(lp_core_main_bin_start, (lp_core_main_bin_end - lp_core_main_bin_start)));
+
+    /* Run LP core */
+    ESP_ERROR_CHECK(ulp_lp_core_run(&cfg));
+
+    printf("LP core loaded with firmware and running successfully\n");
+}
+
+void app_main(void)
+{
+    esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
+    if (cause != ESP_SLEEP_WAKEUP_ULP) {
+        printf("Not an LP core wakeup. Cause = %d\n", cause);
+        printf("Initializing...\n");
+
+        /* Initialize LP_UART */
+        lp_uart_init();
+
+        /* Load LP Core binary and start the coprocessor */
+        lp_core_init();
+    }
+
+    /* Setup wakeup triggers */
+    ESP_ERROR_CHECK(esp_sleep_enable_ulp_wakeup());
+
+    /* Enter Deep Sleep */
+    printf("Entering deep sleep...\n");
+    esp_deep_sleep_start();
+}

examples/system/ulp/lp_core/lp_uart/lp_uart_echo/sdkconfig.defaults

@@ -0,0 +1,4 @@
+# Enable LP Core
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_ULP_COPROC_TYPE_LP_CORE=y
+CONFIG_ULP_COPROC_RESERVE_MEM=4096