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38 Commits

Author SHA1 Message Date
Marius Vikhammer
ff6f927b5f ULP: add functions for stopping/restarting the ulp-riscv 
Closes https://github.com/espressif/esp-idf/issues/8232
 2022-01-20 11:34:53 +08:00
Sudeep Mohanty
2ed15d8b1e ulp: Added ULP RISC-V support for esp32s3 
This commit adds support for ULP RISC-V for esp32s3.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
 2022-01-18 10:58:00 +05:30
morris
869bed1bb5 soc: don't expose unstable soc header files in public api 2022-01-06 23:10:22 +08:00
boarchuz
7e7c044afa update ulp st doc 
Merges https://github.com/espressif/esp-idf/pull/5222
 2021-04-15 16:16:11 +02:00
Angus Gratton
66fb5a29bb Whitespace: Automated whitespace fixes (large commit) 
Apply the pre-commit hook whitespace fixes to all files in the repo.

(Line endings, blank lines at end of file, trailing whitespace)
 2020-11-11 07:36:35 +00:00
Dmitry Yakovlev
0a8afd13a2 Udate instruction set documentation for Esp32 and Esp32s2. 
Sleep instruction removed from S2 instruction set.
LDx/STx instructions descritioin fix offset range to 13 bits (11 bits signed 32 bit words offset).
Remove I2C RD/WR operations from S2.
 2020-10-17 02:44:47 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
boarchuz
137bc6658c ulp: typo fix 
rd_reg comment references incorrect OPCODE ("OPCODE_WR_REG"); amended to "OPCODE_RD_REG".

Merges https://github.com/espressif/esp-idf/pull/4098
 2020-09-10 01:33:50 +02:00
He Hui Zi
dfa59e3d22 docs: translate api-guides/ulp-risc-v from EN to CN 2020-08-13 19:44:46 +08:00
Felipe Neves
b6dba84323 ulp: added support to building code for riscv ULP coprocessor 2020-07-15 15:28:49 -03:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
morris
1c2cc5430e global: bring up esp32s2(not beta) 2020-01-16 17:41:31 +08:00
Dmitry
1518c410bc A switch between esp32 and esp32s2betta added to the ULP build process. 
The new bin utils will have extension esp32s2ulp-elf, and they have to be placed to the bin directory.
 2019-11-22 09:03:13 +03:00
Angus Gratton
6b7da96d5b ulp: Add header for common ULP definitions 
Fixes problems with duplicate error codes in the two chip-specific ulp headers
 2019-09-16 16:18:53 +10:00
Angus Gratton
438d513a95 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-16 16:18:48 +10:00
Saket Dandawate
ccc95191ea ulp: Add aditional uint32_t object to ulp_insn_t 
Used to get the encoded instruction from bit-field structs.

Merges https://github.com/espressif/esp-idf/pull/3759
 2019-08-15 17:34:26 +02:00
boarchuz
28ca2d72b8 ulp: Correct misleading corrections of i2c comments 
Merges https://github.com/espressif/esp-idf/pull/3580
 2019-08-15 17:34:19 +02:00
boarchuz
68b3677daa ulp: Correct misleading i2c write mask comments 
Merges https://github.com/espressif/esp-idf/pull/3580
 2019-08-15 17:34:11 +02:00
boarchuz
88a69823cf ulp: Expand ULP macro functionality 
Merges https://github.com/espressif/esp-idf/pull/3580
 2019-08-15 17:34:11 +02:00
suda-morris
84b2f9f14d build and link hello-world for esp32s2beta 2019-06-11 13:07:37 +08:00
Mahavir Jain
588ecaae09 ulp: add note regarding limitation of ulp_set_wakeup_period in deep sleep mode 2018-12-03 11:41:10 +05:30
krzychb
f6b0b27026 Corrected number of FSM cycles and related description 2018-09-10 07:14:19 +02:00
krzychb
5eee2bf37d Corrected ULP wakeup period setup API to account for time the ULP FSM spends on internal tasks before being able to execute the program. Inspired by https://esp32.com/viewtopic.php?f=2&t=7081. 2018-09-10 07:08:12 +02:00
Ivan Grokhotkov
323caed83b ulp: fix ULP binary format documentation 
Fix incorrect offset value (4+2+2+2+2=12) of arbitrary data in ULP
binary format.

Closes https://github.com/espressif/esp-idf/issues/1705.
 2018-08-07 16:14:57 +03:00
Ivan Grokhotkov
33153748ba ulp: fix missing include in esp32/ulp.h header 
ulp.h uses some register base addresses, so needs to include soc.h
 2018-08-07 16:14:57 +03:00
Ivan Grokhotkov
dba291416f soc,ulp: add register definitions of RTC_I2C peripheral 2018-01-08 21:28:14 +08:00
robotrovsky
6a51a13b70 Bugfix I_DELAY macro 
When compiling

> const ulp_insn_t program[] = {
> I_DELAY(1)
> };

with the xtensa-esp32-elf-g++ compiler i always got the error:

> sorry, unimplemented: non-trivial designated initializers not supported
>
>        };

This was due to the different order in the macro and the struct. The struct has another order of the fields (opcode, unused, cycles) vs (cycles, unused, opcode):
>    struct {
>        uint32_t cycles : 16;       /*!< Number of cycles to sleep */
>        uint32_t unused : 12;       /*!< Unused */
>        uint32_t opcode : 4;        /*!< Opcode (OPCODE_DELAY) */
>    } delay;                        /*!< Format of DELAY instruction */

After updating the order in the macro it is possible to compile with the g++ compiler.

Merges https://github.com/espressif/esp-idf/pull/1310
 2017-12-07 10:02:45 +11:00
Ivan Grokhotkov
98e15df7f6 examples: add ULP ADC example 2017-05-16 13:15:02 +08:00
Dmitry Yakovlev
a6e4e89592 ulp: add build system integration and example 2017-03-27 12:41:00 +08:00
Ivan Grokhotkov
5cab04075e ulp: rename I_SLEEP, redefine I_WAKE, add I_ADC, add tests 
This fixes incorrect descriptions of I_END/I_SLEEP instructions and
changes the definition of I_END. New instruction, I_WAKE, is added,
which wakes up the SoC. Macro for ADC instruction is defined, and new
tests are added.
 2017-02-22 15:00:36 +08:00
Ivan Grokhotkov
0fcc8918dd ulp: add I_WR_REG_BIT convenience macro 2017-02-22 14:40:36 +08:00
Ivan Grokhotkov
d0d2c4cb49 esp32,ulp: add tests for TSENS 2017-02-22 14:40:36 +08:00
Ivan Grokhotkov
611e510c49 ulp: add I_SLEEP instruction and improve comments 2017-02-22 14:40:36 +08:00
Ivan Grokhotkov
0483548a39 ulp: fix I_{RD,WR}_REG definitions 
- I_RD_REG used the wrong union member (.rd_reg) due to a copy-paste
  mistake

- Peripheral register address in bits[7:0] should be given in words,
  not in bytes

Fixes https://github.com/espressif/esp-idf/issues/297
 2017-02-22 14:40:36 +08:00
Ivan Grokhotkov
b62f8b42d4 ulp: document peripherals accessible using RD_REG and WR_REG 2016-12-16 20:32:34 +08:00
Ivan Grokhotkov
7a527896dc ulp: use timer to start ULP, fix I_ANDI bug, add tests 
Starting the ULP using SENS_SAR_START_FORCE_REG doesn’t disable clock gating of RTC fast clock.
When SoC goes into deep sleep mode, RTC fast clock gets gated, so ULP can no longer run.
Instead, it has to be started using the timer (RTC_CNTL_ULP_CP_SLP_TIMER_EN bit).
When ULP is enabled by the timer, clock also gets enabled.
 2016-12-16 20:25:38 +08:00
Ivan Grokhotkov
7b02eae9e6 ulp: add RD_REG, WR_REG, END instruction 2016-12-16 20:01:15 +08:00
Ivan Grokhotkov
ab3677d64c initial support for generation of ULP coprocessor code 2016-12-01 20:26:47 -08:00