songruojing
c8752cee6a
clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem
2022-06-13 17:47:50 +08:00
Wu Zheng Hui
b98622c624
efuse: update efuse name
2022-05-28 22:03:16 +08:00
Michael (XIAO Xufeng)
6f507d527c
rtc: fixed 8MD256 can't be used as RTC slow src on ESP32
...
Sync configuration from other chips
Closes: https://github.com/espressif/esp-idf/issues/8007 , https://github.com/espressif/esp-idf/pull/8089
2022-05-14 22:35:41 +08:00
songruo
60bb5c913d
clk_tree: prework of introducing clk subsystem control
...
1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with
upper level API esp_clk_xtal/apb_freq
2. Fix small errors and wrong comments related to clock
3. Add clk_tree_defs.h to provide an unified clock id for each chip
Modify the NGed drivers to adopt new clock ids
2022-04-11 12:09:06 +08:00
Song Ruo Jing
e13bb580c7
Merge branch 'refactor/gpio_unit_test' into 'master'
...
gpio: Clean up unit tests and enable ci ut on some previously disabled test cases
Closes IDF-4620
See merge request espressif/esp-idf!17417
2022-04-01 18:38:19 +08:00
songruojing
8d84033b8c
gpio: Clean up unit tests and enable ci ut on some previously disabled test cases
...
Eliminate UT_T1_GPIO runner requirement by routing internally through gpio matrix and by setting gpio pins to GPIO_MODE_INPUT_OUTPUT mode for all interrupt related test cases.
2022-03-30 15:11:08 +08:00
laokaiyao
f29d329e55
esp32h2beta2: fixed reg base name
2022-03-29 15:17:23 +08:00
songruojing
c8c137f2b7
esp32h2: support GPIO peripheral, IO_MUX, GPIO matrix.
...
Generic GPIO example is supported as well.
2022-03-04 11:25:05 +08:00
wuzhenghui
1a4d4b9cd6
remove esp32h2 rev1/2 unsupported efuse field
2022-02-28 19:37:43 +08:00
KonstantinKondrashov
9605f3eb1a
soc: Adds efuse hal
...
Replaced eFuse ROM funcs with hal layer
2022-02-24 22:20:09 +08:00
Marius Vikhammer
97d11c709d
soc: Merge soc_caps for H2 rev1 and rev2
...
These files were identical.
2021-12-06 12:37:11 +08:00
Marius Vikhammer
c6d60615c6
build-system: include soc_caps defines into kconfig
...
Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into
a format that can be included in kconfig.
2021-12-06 12:37:07 +08:00
laokaiyao
f21020ce04
esp32h2: update reg and struct for beta2
2021-11-24 12:34:17 +08:00
wuzhenghui
388615add0
update esp32h2beta2 chip_id to 14
2021-11-24 12:30:43 +08:00
