5 Commits

Author	SHA1	Message	Date
Ivan Grokhotkov	0483548a39	ulp: fix I_{RD,WR}_REG definitions ... - I_RD_REG used the wrong union member (.rd_reg) due to a copy-paste mistake - Peripheral register address in bits[7:0] should be given in words, not in bytes Fixes https://github.com/espressif/esp-idf/issues/297	2017-02-22 14:40:36 +08:00
Ivan Grokhotkov	b62f8b42d4	ulp: document peripherals accessible using RD_REG and WR_REG	2016-12-16 20:32:34 +08:00
Ivan Grokhotkov	7a527896dc	ulp: use timer to start ULP, fix I_ANDI bug, add tests ... Starting the ULP using SENS_SAR_START_FORCE_REG doesn’t disable clock gating of RTC fast clock. When SoC goes into deep sleep mode, RTC fast clock gets gated, so ULP can no longer run. Instead, it has to be started using the timer (RTC_CNTL_ULP_CP_SLP_TIMER_EN bit). When ULP is enabled by the timer, clock also gets enabled.	2016-12-16 20:25:38 +08:00
Ivan Grokhotkov	7b02eae9e6	ulp: add RD_REG, WR_REG, END instruction	2016-12-16 20:01:15 +08:00
Ivan Grokhotkov	ab3677d64c	initial support for generation of ULP coprocessor code	2016-12-01 20:26:47 -08:00