* Closes https://github.com/espressif/esp-idf/issues/12849
In former versions of ESP-IDF, the user custom memory data in the retained memory
was taken into account during the CRC calculation. This was changed in a later
commit, the custom memory was ignored, therefore this can seen as a breaking change.
This commit gives the possibility to choose between the former (legacy) or
new way of calculating the CRC.
All the log messages of espcoredump component used to be in DRAM, which would
lower the available RAM space for the user application. Since the cache is always
enabled after an exception, constants can be put in flash.
Secure version in the image header is only available for the application
image. However, for certain security workflows, bootloader verifies
itself (own image) and hence the secure version check during that must be
avoided.
Regression introduced in recent commit-id: 3305cb4d
Tested that both secure boot and flash-enc workflows work correctly
with the anti-rollback scenario.
Some additional checks related to secure version of the application in
anti-rollback case have been added to avoid any attempts to boot lower
security version but valid application (e.g., passive partition image).
- Read secure_version under sha256 protection
- First check has been added in the bootloader to ensure correct secure
version after application verification and loading stage. This check
happens before setting up the flash cache mapping and handling over
the final control to application. This check ensures that application
was not swapped (e.g., to lower security version but valid image) just
before the load stage in bootloader.
- Second check has been added in the application startup code to ensure
that currently booting app has higher security version than the one
programmed in the eFuse for anti-rollback scenario. This will ensure
that only the legit application boots-up on the device for
anti-rollback case.
There are a bunch of cases you might want some pins not exposed.
Eg.
* Reading say 8 bit data and outputting the top 5 bits, discarding the rest by not mapping those data pins to output pins
* Not using hsync/vsync because sync data is embedded within the data bits for more timing flexibility (eg. interlacing).
* Using the LCD module as a high speed parallel data output bus, with no need for sync/control pins.
Removing this validation makes these cases work.
Merges https://github.com/espressif/esp-idf/pull/13103
