Commit Graph

102 Commits

Author SHA1 Message Date
Xiao Xufeng
194ea85ee8 spi_flash: fixed issue that enabling HPM-DC by default may cause app unable to restart 2024-03-12 10:48:08 +08:00
laokaiyao
804a9ea1f6 esp32h4: remove esp32h4 target from peripherals 2023-04-26 18:53:10 +08:00
gaoxu
542a61b6cb support SPI_FLASH_ENABLE_COUNTERS feature on esp_flash driver and rename the functions to esp_flash_xx 2023-04-06 11:40:40 +08:00
laokaiyao
c9f780dc2e gpio: support runtime preserve 2023-03-17 11:59:49 +08:00
Cao Sen Miao
bc655a6890 spi_flash: Allow clock frequency up to 64M, and make it default on ESP32H2 2023-03-10 11:39:53 +08:00
Armando
b46cfd15a2 mspi: move timing tuning to esp_hw_support 2023-01-06 14:41:20 +08:00
laokaiyao
8677216576 esp32h2: renaming esp32h2 to esp32h4 2022-11-08 17:05:33 +08:00
Cao Sen Miao
2c9bb4eb7d spi_flash: Support select flash mode automatically at run time(Quad flash or Octal flash) 2022-10-18 11:25:35 +08:00
wuzhenghui
ff8dd1e1a8 esp32c6: add spi_flash support 2022-09-26 20:32:13 +08:00
Guillaume Souchere
6005cc9163 hal: Deprecate interrupt_controller_hal.h, cpu_hal.h and cpu_ll.h interfaces
This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
2022-07-22 00:06:06 +08:00
Jing Li
66395a5c00 system/sleep: further fix spi flash/ram current leakage 2022-07-21 19:14:26 +08:00
Cao Sen Miao
683d92bc88 flash_encryption: Fix issue that flash encryption cannot work when 8-line psram enabled,
Closes https://github.com/espressif/esp-idf/issues/9244,
                  Closes https://github.com/espressif/esp-idf/issues/9287
2022-07-12 16:08:57 +08:00
Cao Sen Miao
a690a87829 spi_flash: Remove legacy spi_flash drivers 2022-07-01 11:01:34 +08:00
Cao Sen Miao
85dd785d8d spi_flash: Building a framework to enable HPM when flash works under high speed mode 2022-03-09 18:49:34 +08:00
Mahavir Jain
98a74e431c spi_flash: fix unused variable warning with SPI_FLASH_DANGEROUS_WRITE_ALLOWED
Closes https://github.com/espressif/esp-idf/issues/8329
Closes IDFGH-6700
2022-02-03 09:52:06 +05:30
laokaiyao
cf049e15ed esp8684: rename target to esp32c2 2022-01-19 11:08:57 +08:00
Cao Sen Miao
b0decda1e3 bootloader: move bootloader flash support to isolate folders 2021-12-30 14:05:12 +08:00
Cao Sen Miao
3a4db97cec spi_flash: move patch files to common rom patch folder 2021-12-30 14:05:12 +08:00
Cao Sen Miao
3dd1cfea18 spi_flash: refactor spi_flash.h to decline duplicated code 2021-12-30 14:05:12 +08:00
Cao Sen Miao
eddc196081 esp_clk: refactor target/clk.h to private/esp_clk.h 2021-11-26 14:56:30 +08:00
Cao Sen Miao
3934e24d22 ESP8684: add spi_flash, efuse, hw_support support 2021-11-06 17:33:44 +08:00
KonstantinKondrashov
884a6b17cc spi_flash: No CPU release time for an erase operation when OS is not running
During the early start, the virtual eFuse mode can call erase operations when OS is not yet running.

Possible workaround: CONFIG_SPI_FLASH_YIELD_DURING_ERASE=n

Fixed for the legacy flash driver as well.
2021-11-01 21:49:24 +08:00
Armando
2655a506c9 mspi: support auto detect octal flash vendor 2021-10-08 15:59:57 +08:00
Cao Sen Miao
6c0aebe279 esp_flash: add opi flash support in esp_flash chip driver, for MXIC 2021-09-07 14:44:40 +08:00
Cao Sen Miao
559c1ac3f9 esp_flash: add support mxic as a main flash under spi mode 2021-09-05 00:33:28 +08:00
Armando
0f91a01a46 mspi: support up-to-80MHz quad flash & up-to-80MHz octal psram on esp32s3 2021-08-03 16:54:00 +08:00
Cao Sen Miao
c29b3e2e36 spi_flash: move the unlock patch to bootloader and add support for GD 2021-07-29 10:46:33 +08:00
Shu Chen
6fce2930d0 esp32h2: enable more components to support esp32h2
Involved components:
 * app_trace
 * esp-tls
 * esp_adc_cal
 * esp_pm
 * esp_serial_slave_link
 * esp_timer
 * freertos
 * idf_test
 * log
 * mbedtls
 * newlib
 * perfmon
 * spi_flash
 * spiffs
 * ulp
 * unity
 * vfs
2021-07-01 19:53:11 +08:00
Armando
bc248278f8 spiflash: add octal spi psram support on 727 2021-06-25 19:41:57 +08:00
Cao Sen Miao
0d81edb174 spi_flash: refactoring flash encryption into new api 2021-04-25 17:09:25 +08:00
Renz Bagaporo
e6edf34e82 esp32: move esp_clk functions 2021-03-31 19:17:33 +08:00
Cao Sen Miao
6fbf61493c ota: fix ota with flash encryption 2021-03-01 14:11:55 +08:00
Cao Sen Miao
c1b41ece32 flash_encryption: Quick fixed the issue that block when flash_encryption_write, Related https://github.com/espressif/esp-idf/issues/6322, Related https://github.com/espressif/esp-idf/issues/6254 2021-02-05 20:10:42 +08:00
Angus Gratton
d4c9a45675 spi_flash: Add ESP32-C3 support
Based on internal commit 3ef01301fff
2020-12-17 15:34:13 +11:00
Angus Gratton
5228d9f9ce esp32c3: Apply one-liner/small changes for ESP32-C3 2020-12-01 10:58:50 +11:00
Cao Sen Miao
11188d2143 esp_flash:fix bug about clearing WLE automatically after actions 2020-11-12 16:44:29 +08:00
Renz Bagaporo
21e46d5b3c ci: use actual esp_system headers for host test 2020-10-22 19:42:34 +08:00
Renz Bagaporo
b3a7c6e27e components: remove some unneeded headers from source files 2020-10-22 19:37:10 +08:00
morris
61f89b97c6 bringup esp32-s3 on FPGA 2020-09-22 15:15:03 +08:00
Michael (XIAO Xufeng)
fefdee1349 bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.

   This commit helps to clear WEL when flash configuration is done.

   **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.

2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.

   Status register bitmap of ISSI chip and GD chip:

| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0  | WIP  | WIP       |
| 1  | WEL  | WEL       |
| 2  | BP0  | BP0       |
| 3  | BP1  | BP1       |
| 4  | BP2  | BP2       |
| 5  | BP3  | BP3       |
| 6  | QE   | BP4       |
| 7  | SRWD | SRP0      |
| 8  |      | SRP1      |
| 9  |      | QE        |
| 10 |      | SUS2      |
| 11 |      | LB1       |
| 12 |      | LB2       |
| 13 |      | LB3       |
| 14 |      | CMP       |
| 15 |      | SUS1      |

   QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.

   However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.

   Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.

   This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).

3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.

   This commit skips the clearing of status register if there is no protection bits active.

Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-09-19 10:51:51 +08:00
Michael (XIAO Xufeng)
479269a52b Merge branch 'feature/configure_flash_write_chunk_size' into 'master'
spi_flash: add configuration option to select flash write chunk size

See merge request espressif/esp-idf!9067
2020-06-22 14:50:42 +08:00
Mahavir Jain
05da91f0db spi_flash: add configuration option to select flash write chunk size
Flash write operation is broken down into smaller chunk writes. Size
of this chunk was previously set to 8K but that in-turn meant cache and
non-IRAM resident interrupts could stay disabled upto ~24msec for 8K flash
write operation. If chunk size is brought down to 256 (typical flash page size)
then it brings down cache and non-IRAM interrupts disable duration to ~1msec.

Fix here keeps defaults same but provides configuration option to tweak the
setting based on application requirement.
2020-06-05 14:45:41 +05:30
Ivan Grokhotkov
03bb2774d9 spi_flash: don't call vTaskDelay in non-os context
Fixes regression in core dump, when a crash happens in interrupt
context.
2020-06-02 15:42:24 +02:00
Darian Leung
11d96b39d0 esp_ipc: Move to new component
This commit moves esp_ipc into a separate component.
2020-05-18 16:51:45 +08:00
KonstantinKondrashov
304f67e42a spi_flash(LEGACY_IMPL): Add a Kconfig option - Bypass a block erase and always do sector erase
Closes: IDF-1561
2020-04-30 13:58:13 +08:00
KonstantinKondrashov
3cb655eaab spi_flash(LEGACY_IMPL): Add vTaskDelay while a long erasing
Added Kconfig options to enable yield operation during flash erase

Closes: https://github.com/espressif/esp-idf/issues/2083
Closes: https://github.com/espressif/esp-idf/issues/4916
Closes: IDFGH-261
2020-04-30 13:58:13 +08:00
Angus Gratton
dbdce93d23 spi_flash: Use per-chip flash_ops files for legacy API
Looks like when ESP32-S2 Beta support was merged, the separate files
were dropped by accident.
2020-04-24 12:43:47 -03:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
morris
1c2cc5430e global: bring up esp32s2(not beta) 2020-01-16 17:41:31 +08:00
Michael (XIAO Xufeng)
2660cb82ae spi_flash: support to verify written encrypted data
Also add unit test for encrypted_read
2019-10-30 05:49:50 +00:00