Commit Graph

20 Commits

Author SHA1 Message Date
morris
f5b03c9ea3 misc adjustment of esp32 component 2019-04-03 19:57:46 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
2019-03-21 18:51:45 +08:00
Konstantin Kondrashov
e5b280f173 dport: Bigfix dport_read code move to IRAM
A new method of workaround an error with DPORT is to ensure that the APB is read and followed by the DPORT register without interruptions and pauses. This fix places this implementation in the IRAM to exclude errors associated with the cache miss.
2018-05-21 22:00:51 +05:00
Konstantin Kondrashov
8f80cc733d soc: Change DPORT access
When two CPUs read the area of the DPORT and the area of the APB, the result is corrupted for the CPU that read the APB area.
And another CPU has valid data.

The method of eliminating this error.
Before reading the registers of the DPORT, make a preliminary reading of the APB register.
In this case, the joint access of the two CPUs to the registers of the APB and the DPORT is successful.
2018-05-14 17:54:57 +05:00
Ivan Grokhotkov
6b61c6d39f esp32: exclude DPORT-related code in single core mode 2017-09-22 12:07:05 +08:00
Jeroen Domburg
b3fd494e71 Panic: stop dport access handler without trying to use a lock 2017-09-11 17:24:22 +08:00
Ivan Grokhotkov
33cb16fd2a esp32: fix cache error interrupt handler
Cache error interrupt would read DPORT registers, which caused DPORT
access protection to kick in. Disable DPORT protection before doing the
reads.
2017-09-08 09:59:09 +08:00
Ivan Grokhotkov
65b046f17f dport access: introduce pause/resume instead of deinit 2017-09-01 10:36:14 +08:00
Angus Gratton
afb6119504 dport access: Fix WDT bug (permanent locking) in non-pinned tasks
If scheduler switches cores in narrow window during esp_dport_access_stall_other_cpu_start(), could cause the stall
interrupt to occur on the running CPU - halting the CPU until WDT cleans up.

Related to https://github.com/espressif/esp-idf/issues/630
2017-08-25 16:08:03 +10:00
Angus Gratton
dc8c33892e dport access: Fix nested calls to DPORT_STALL_OTHER_CPU_START() 2017-08-25 16:08:02 +10:00
Angus Gratton
99fe61716c startup: Add assertion checks around various initialisation sequences
These may fail if close to 192KB of static RAM is allocated (remaining early heap RAM is too small.)
2017-07-12 13:06:56 +08:00
Angus Gratton
3fe0022efa stack sizes: Revert stack size increases added in 8d43859
Set min stack size to 2048 if AppTrace support is enabled, 512 bytes otherwise.
2017-06-29 14:57:13 +10:00
Angus Gratton
415a7d742a dport_access: Fix spurious warning in unicore mode, refactor 2017-06-29 13:57:13 +10:00
Alexey Gerenkov
8d43859b6a esp32: SEGGER SystemView Tracing Support
Implements support for system level traces compatible with SEGGER
SystemView tool on top of ESP32 application tracing module.
That kind of traces can help to analyse program's behaviour.
SystemView can show timeline of tasks/ISRs execution, context switches,
statistics related to the CPUs' load distribution etc.

Also this commit adds useful feature to ESP32 application tracing module:
 - Trace data buffering is implemented to handle temporary peaks of events load
2017-06-27 20:52:43 +03:00
Ivan Grokhotkov
a72b1abc51 esp32: disable DPORT access protection when doing esp_restart
DPORT access protection can not work when the other CPU is stalled.
Writes to DPORT registers in esp_restart caused the program to hang due
to access protection, and the reset happened due to RTC_WDT, not SW_RST.
This change adds esp_dport_access_int_deinit function and calls it from
esp_restart once the other core is stalled.
2017-06-15 18:15:35 +08:00
jack
fc130fba86 fix bug that files missing commit in MR 773 2017-05-31 19:37:39 +08:00
Tian Hao
3d22f1ee2f component/esp32 : fix library sport access protections.
1. add esp32 library access DPORT register protections.
2. add bluetooth library access DPORT register protections.
3. change register operation(suffix/prefix) to new style.
2017-05-13 19:55:11 +08:00
Tian Hao
377a1f5ea1 component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
2017-05-12 15:41:51 +08:00
Tian Hao
26a3cb93c7 component/soc : move dport access header files to soc
1. move dport access header files to soc
2. reduce dport register write protection. Only protect read operation
2017-05-09 18:06:00 +08:00
Tian Hao
f7e8856520 component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
2017-05-08 21:53:43 +08:00