mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
This commit is contained in:
Tian Hao
parent
c518325385
commit
377a1f5ea1
@ -84,9 +84,9 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
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dport_access_end[cpu_id] = 0;
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if (cpu_id == 0) {
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WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
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} else {
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WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
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_DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
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}
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while (!dport_access_start[cpu_id]) {};
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37
components/esp32/include/esp_assert.h
Normal file
37
components/esp32/include/esp_assert.h
Normal file
@ -0,0 +1,37 @@
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __ESP_ASSERT_H__
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#define __ESP_ASSERT_H__
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#include "assert.h"
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/* Assert at compile time if possible, runtime otherwise */
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#ifndef __cplusplus
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/* __builtin_choose_expr() is only in C, makes this a lot cleaner */
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#define TRY_STATIC_ASSERT(CONDITION, MSG) do { \
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_Static_assert(__builtin_choose_expr(__builtin_constant_p(CONDITION), (CONDITION), 1), #MSG); \
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assert(#MSG && (CONDITION)); \
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} while(0)
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#else
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/* for C++, use __attribute__((error)) - works almost as well as _Static_assert */
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#define TRY_STATIC_ASSERT(CONDITION, MSG) do { \
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if (__builtin_constant_p(CONDITION) && !(CONDITION)) { \
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extern __attribute__((error(#MSG))) void failed_compile_time_assert(void); \
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failed_compile_time_assert(); \
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} \
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assert(#MSG && (CONDITION)); \
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} while(0)
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#endif /* __cplusplus */
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#endif /* __ESP_ASSERT_H__ */
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@ -15,6 +15,8 @@
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#ifndef _ROM_CACHE_H_
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#define _ROM_CACHE_H_
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#include "soc/dport_access.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -64,7 +66,18 @@ void mmu_init(int cpu_no);
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* 4 : mmu table to be written is out of range
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* 5 : vaddr is out of range
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*/
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unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
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{
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extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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unsigned int ret;
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DPORT_STALL_OTHER_CPU_START();
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ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
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DPORT_STALL_OTHER_CPU_END();
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return ret;
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}
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/**
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* @brief Set Ext-SRAM-Cache mmu mapping.
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@ -93,7 +106,18 @@ unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsign
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* 4 : mmu table to be written is out of range
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* 5 : vaddr is out of range
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*/
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unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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static inline unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
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{
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extern unsigned int cache_sram_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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unsigned int ret;
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DPORT_STALL_OTHER_CPU_START();
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ret = cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
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DPORT_STALL_OTHER_CPU_END();
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return ret;
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}
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/**
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* @brief Initialise cache access for the cpu.
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@ -103,7 +127,13 @@ unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigne
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*
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* @return None
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*/
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void Cache_Read_Init(int cpu_no);
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static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
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{
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extern void Cache_Read_Init_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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Cache_Read_Init_rom(cpu_no);
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DPORT_STALL_OTHER_CPU_END();
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}
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/**
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* @brief Flush the cache value for the cpu.
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@ -113,7 +143,13 @@ void Cache_Read_Init(int cpu_no);
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*
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* @return None
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*/
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void Cache_Flush(int cpu_no);
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static inline void IRAM_ATTR Cache_Flush(int cpu_no)
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{
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extern void Cache_Flush_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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Cache_Flush_rom(cpu_no);
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DPORT_STALL_OTHER_CPU_END();
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}
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/**
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* @brief Disable Cache access for the cpu.
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@ -123,7 +159,13 @@ void Cache_Flush(int cpu_no);
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*
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* @return None
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*/
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void Cache_Read_Disable(int cpu_no);
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static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
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{
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extern void Cache_Read_Disable_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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Cache_Read_Disable_rom(cpu_no);
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DPORT_STALL_OTHER_CPU_END();
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}
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/**
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* @brief Enable Cache access for the cpu.
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@ -133,7 +175,13 @@ void Cache_Read_Disable(int cpu_no);
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*
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* @return None
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*/
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void Cache_Read_Enable(int cpu_no);
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static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
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{
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extern void Cache_Read_Enable_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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Cache_Read_Enable_rom(cpu_no);
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DPORT_STALL_OTHER_CPU_END();
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}
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/**
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* @}
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@ -50,12 +50,12 @@ PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );
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PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );
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PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );
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PROVIDE ( bzero = 0x4000c1f4 );
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PROVIDE ( cache_flash_mmu_set = 0x400095e0 );
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PROVIDE ( Cache_Flush = 0x40009a14 );
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PROVIDE ( Cache_Read_Disable = 0x40009ab8 );
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PROVIDE ( Cache_Read_Enable = 0x40009a84 );
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PROVIDE ( Cache_Read_Init = 0x40009950 );
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PROVIDE ( cache_sram_mmu_set = 0x400097f4 );
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PROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 );
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PROVIDE ( Cache_Flush_rom = 0x40009a14 );
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PROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );
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PROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );
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PROVIDE ( Cache_Read_Init_rom = 0x40009950 );
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PROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );
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/* This is static function, but can be used, not generated by script*/
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PROVIDE ( calc_rtc_memory_crc = 0x40008170 );
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PROVIDE ( calloc = 0x4000bee4 );
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@ -95,9 +95,9 @@ void emac_reset(void)
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void emac_enable_clk(bool enable)
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{
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if (enable == true) {
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REG_SET_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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DPORT_REG_SET_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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} else {
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REG_CLR_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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DPORT_REG_CLR_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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}
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}
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@ -22,30 +22,29 @@ void esp_dport_access_stall_other_cpu_start(void);
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void esp_dport_access_stall_other_cpu_end(void);
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#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
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#define DPORT_STAL_OTHER_CPU_START()
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#define DPORT_STAL_OTHER_CPU_END()
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#define DPORT_STALL_OTHER_CPU_START()
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#define DPORT_STALL_OTHER_CPU_END()
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#else
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#define DPORT_STAL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
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#define DPORT_STAL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
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#define DPORT_STALL_OTHER_CPU_START() esp_dport_access_stall_other_cpu_start()
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#define DPORT_STALL_OTHER_CPU_END() esp_dport_access_stall_other_cpu_end()
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#endif
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DPORT_DATE_REG)
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//Registers Operation {{
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#define _REG_READ(_r) (*(volatile uint32_t *)(_r))
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#define _REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//Origin access operation for the base and some special scene
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#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
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#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//write value to register
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#define DPORT_REG_WRITE(_r, _v) _REG_WRITE(_r, _v)
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#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE(_r, _v)
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//read value from register
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inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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{
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uint32_t val;
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DPORT_STAL_OTHER_CPU_START();
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val = _REG_READ(reg);
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DPORT_STAL_OTHER_CPU_END();
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DPORT_STALL_OTHER_CPU_START();
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val = _DPORT_REG_READ(reg);
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DPORT_STALL_OTHER_CPU_END();
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return val;
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}
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@ -54,19 +53,19 @@ inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
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//set bit or set bits to register
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#define DPORT_REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
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#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
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//clear bit or clear bits of register
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#define DPORT_REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
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#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
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//set bits of register controlled by mask
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#define DPORT_REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (DPORT_REG_READ(_r) & ~(_m)) | ((_b) & (_m)))
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#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
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//get field from register, uses field _S & _V to determine mask
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#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
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//set field to register, used when _f is not left shifted by _f##_S
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#define DPORT_REG_SET_FIELD(_r, _f, _v) (DPORT_REG_WRITE((_r),((DPORT_REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
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#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f) << (_f##_S))))|(((_v) & (_f))<<(_f##_S))))
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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@ -90,13 +89,13 @@ inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
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#define _WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
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//read value from register
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inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr)
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{
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uint32_t val;
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DPORT_STAL_OTHER_CPU_START();
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DPORT_STALL_OTHER_CPU_START();
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val = _READ_PERI_REG(addr);
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DPORT_STAL_OTHER_CPU_END();
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DPORT_STALL_OTHER_CPU_END();
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return val;
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}
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@ -17,6 +17,7 @@
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include "esp_assert.h"
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#endif
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//Register Bits{{
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@ -57,98 +58,6 @@
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#define PRO_CPU_NUM (0)
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#define APP_CPU_NUM (1)
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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#define BIT(nr) (1UL << (nr))
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#else
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#define BIT(nr) (1 << (nr))
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#endif
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#ifndef __ASSEMBLER__
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//write value to register
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#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
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//read value from register
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#define REG_READ(_r) (*(volatile uint32_t *)(_r))
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
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//write value to register
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#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
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||||
//}}
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM ( 26*1000000 )
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
#define SOC_IROM_LOW 0x400D0000
|
||||
#define SOC_IROM_HIGH 0x40400000
|
||||
@ -160,6 +69,7 @@
|
||||
#define SOC_RTC_DATA_HIGH 0x50002000
|
||||
|
||||
#define DR_REG_DPORT_BASE 0x3ff00000
|
||||
#define DR_REG_DPORT_END 0x3ff00FFC
|
||||
#define DR_REG_RSA_BASE 0x3ff02000
|
||||
#define DR_REG_SHA_BASE 0x3ff03000
|
||||
#define DR_REG_UART_BASE 0x3ff40000
|
||||
@ -210,6 +120,155 @@
|
||||
#define DR_REG_PWM3_BASE 0x3ff70000
|
||||
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#else
|
||||
#define BIT(nr) (1 << (nr))
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
|
||||
|
||||
#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
|
||||
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
|
||||
#else
|
||||
#define ASSERT_IF_DPORT_REG(_r, OP)
|
||||
#endif
|
||||
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) ({ \
|
||||
ASSERT_IF_DPORT_REG(_r, REG_WRITE); \
|
||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
||||
})
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_READ); \
|
||||
(*(volatile uint32_t *)_r); \
|
||||
})
|
||||
|
||||
//get bit or get bits from register
|
||||
#define REG_GET_BIT(_r, _b) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
|
||||
(*(volatile uint32_t*)(_r) & (_b)); \
|
||||
})
|
||||
|
||||
//set bit or set bits to register
|
||||
#define REG_SET_BIT(_r, _b) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
|
||||
(*(volatile uint32_t*)(_r) |= (_b)); \
|
||||
})
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define REG_CLR_BIT(_r, _b) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
|
||||
(*(volatile uint32_t*)(_r) &= ~(_b)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define REG_SET_BITS(_r, _b, _m) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
|
||||
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
|
||||
})
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
|
||||
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
|
||||
})
|
||||
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) ({ \
|
||||
ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
|
||||
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
|
||||
})
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//read value from register
|
||||
#define READ_PERI_REG(addr) ({ \
|
||||
ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
|
||||
})
|
||||
|
||||
//write value to register
|
||||
#define WRITE_PERI_REG(addr, val) ({ \
|
||||
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
||||
})
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define SET_PERI_REG_MASK(reg, mask) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
|
||||
(READ_PERI_REG(reg) & (mask)); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
|
||||
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
|
||||
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
|
||||
})
|
||||
|
||||
//get field of register
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
||||
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
|
||||
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
||||
})
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
//}}
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM ( 26*1000000 )
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
|
||||
//}}
|
||||
|
||||
//Interrupt hardware source table
|
||||
//This table is decided by hardware, don't touch this.
|
||||
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user