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Merge branch 'refactor/format_esp_mm_psram_adc_2' into 'master'

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refactor: format esp mm psram adc 2

See merge request espressif/esp-idf!26372
This commit is contained in:
Armando (Dou Yiwen) 2023-10-10 18:00:07 +08:00
commit fede09a4ea
23 changed files with 354 additions and 399 deletions
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2
components/esp_adc/test_apps/adc/main/test_adc_wifi.c
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@ -179,13 +179,11 @@ __attribute__((unused)) static void adc_work_with_wifi(adc_unit_t unit_id, adc_c
test_adc_set_io_level(unit_id, channel, test_list[i]);
target_value = test_list[i] ? ADC_TEST_HIGH_VAL : ADC_TEST_LOW_VAL;
/* ADC single read before WIFI start */
TEST_ESP_OK(adc_oneshot_read(adc_handle, channel, &read_raw));
printf("Before WiFi starts, ADC read: %d (target_value: %d)\n", read_raw, target_value);
TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw);
/* ADC single read when WIFI is on */
TEST_ESP_OK(esp_wifi_start());
#if CONFIG_IDF_TARGET_ESP32

1
components/esp_mm/include/esp_mmu_map.h
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@ -35,7 +35,6 @@ extern "C" {
* - A Slot is the vaddr range between 2 blocks.
*/
/**
* MMAP flags
*/

1
components/esp_mm/include/esp_private/esp_cache_esp32_private.h
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@ -53,7 +53,6 @@ void cache_register_writeback(cache_driver_t *func);
*/
void cache_sync(void);
#ifdef __cplusplus
}
#endif

1
components/esp_mm/include/esp_private/esp_cache_private.h
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@ -58,7 +58,6 @@ esp_err_t esp_cache_aligned_malloc(size_t size, uint32_t flags, void **out_ptr,
*/
esp_err_t esp_cache_aligned_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, size_t *actual_size);
#ifdef __cplusplus
}
#endif

2
components/esp_mm/include/esp_private/esp_mmu_map_private.h
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@ -14,7 +14,6 @@
extern "C" {
#endif
/**
* Memory Mapping Private APIs for MMU supported memory
*/
@ -52,7 +51,6 @@ esp_err_t esp_mmu_map_reserve_block_with_caps(size_t size, mmu_mem_caps_t caps,
*/
esp_err_t esp_mmu_map_dump_mapped_blocks_private(void);
#ifdef __cplusplus
}
#endif

1
components/esp_mm/test_apps/components/test_mm_utils/include/test_mm_utils.h
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@ -14,7 +14,6 @@
extern "C" {
#endif
/**
* Set addr space dirty
*

1
components/esp_mm/test_apps/mm/main/test_app_main.c
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@ -61,6 +61,5 @@ void app_main(void)
printf("| |___/\\__/ / | | | | || | | | | | | |___/\\__/ / | |\r\n");
printf("\\____/\\____/\\_| \\_| |_/\\_| |_/ \\_/ \\____/\\____/ \\_/\r\n");
unity_run_menu();
}

4
components/esp_mm/test_apps/mm/main/test_cache_msync.c
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@ -30,7 +30,6 @@ const static char *TAG = "CACHE_TEST";
#define TEST_NUM 10
#define TEST_BUF {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9}
#define TEST_OFFSET 0x100000
#if CONFIG_IDF_TARGET_ESP32S2
#define TEST_SYNC_START (SOC_DPORT_CACHE_ADDRESS_LOW + TEST_OFFSET)
@ -41,13 +40,11 @@ const static char *TAG = "CACHE_TEST";
#endif
#define TEST_SYNC_SIZE 0x8000
#define RECORD_TIME_PREPARE() uint32_t __t1, __t2
#define RECORD_TIME_START() do {__t1 = esp_cpu_get_cycle_count();} while(0)
#define RECORD_TIME_END(p_time) do{__t2 = esp_cpu_get_cycle_count(); p_time = (__t2 - __t1);} while(0)
#define GET_US_BY_CCOUNT(t) ((double)(t)/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ)
static void s_test_with_msync_cb(void *arg)
{
(void)arg;
@ -156,7 +153,6 @@ TEST_CASE("test cache msync work with Flash operation when XIP from PSRAM", "[ca
}
#endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA
#if CONFIG_SPIRAM
/*---------------------------------------------------------------
Test esp_cache_msync with PSRAM stack

6
components/esp_mm/test_apps/mmap_hw/main/test_mmap_hw.c
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@ -56,7 +56,6 @@ typedef struct test_block_info_ {
static LIST_HEAD(test_block_list_head_, test_block_info_) test_block_head;
static void s_fill_random_data(uint8_t *buffer, size_t size, int random_seed)
{
srand(random_seed);
@ -102,7 +101,6 @@ TEST_CASE("test all readable vaddr can map to flash", "[mmu]")
ESP_LOGV(TAG, "rand seed: %d, write flash addr: %p...", test_seed, (void *)part->address);
TEST_ESP_OK(esp_flash_write(part->flash_chip, sector_buf, part->address, sizeof(sector_buf)));
esp_err_t ret = ESP_FAIL;
int count = 0;
LIST_INIT(&test_block_head);
@ -144,7 +142,6 @@ TEST_CASE("test all readable vaddr can map to flash", "[mmu]")
free(sector_buf);
}
TEST_CASE("test all executable vaddr can map to flash", "[mmu]")
{
//Get the partition used for SPI1 erase operation
@ -173,8 +170,7 @@ TEST_CASE("test all executable vaddr can map to flash", "[mmu]")
TEST_ASSERT(paddr == part->address + i);
ESP_LOGV(TAG, "paddr: %p, on %s", (void *)paddr, (mem_target) == MMU_TARGET_FLASH0 ? "Flash" : "PSRAM");
}
}
else if (ret == ESP_ERR_NOT_FOUND) {
} else if (ret == ESP_ERR_NOT_FOUND) {
free(block_info);
break;
} else {

5
components/esp_psram/device/esp_psram_impl_ap_hex.c
View File

@ -16,7 +16,6 @@
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define PSRAM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define AP_HEX_PSRAM_SYNC_READ 0x0000
#define AP_HEX_PSRAM_SYNC_WRITE 0x8080
#define AP_HEX_PSRAM_BURST_READ 0x2020
@ -35,7 +34,6 @@
#define AP_HEX_PSRAM_CS_ECC_HOLD_TIME 4
#define AP_HEX_PSRAM_CS_HOLD_DELAY 3
typedef struct {
union {
struct {
@ -96,7 +94,6 @@ typedef struct {
static const char* TAG = "hex_psram";
static uint32_t s_psram_size; //this stands for physical psram size in bytes
/**
* Common psram transaction
*/
@ -235,7 +232,6 @@ static void s_print_psram_info(hex_psram_mode_reg_t *reg_val)
reg_val->mr8.bl == 0x10 ? 64 : 2048);
ESP_EARLY_LOGI(TAG, "BitMode : 0x%02x (%s Mode)", reg_val->mr8.x16, reg_val->mr8.x16 == 1 ? "X16" : "X8");
ESP_EARLY_LOGI(TAG, "Readlatency : 0x%02x (%d cycles@%s)", reg_val->mr0.read_latency, reg_val->mr0.read_latency * 2 + 6,
reg_val->mr0.lt == 1 ? "Fixed" : "Variable");
ESP_EARLY_LOGI(TAG, "DriveStrength: 0x%02x (1/%d)", reg_val->mr0.drive_str, reg_val->mr0.drive_str == 0x00 ? 1 :
@ -326,7 +322,6 @@ static void s_configure_psram_ecc(void)
}
#endif //#if CONFIG_SPIRAM_ECC_ENABLE
esp_err_t esp_psram_impl_enable(void)
{
PSRAM_RCC_ATOMIC() {

18
components/esp_psram/esp32/esp_himem.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -122,19 +122,23 @@ size_t esp_himem_get_free_size(void)
{
size_t ret = 0;
for (int i = 0; i < s_ramblockcnt; i++) {
if (!s_ram_descriptor[i].is_alloced) ret+=CACHE_BLOCKSIZE;
if (!s_ram_descriptor[i].is_alloced) {
ret += CACHE_BLOCKSIZE;
}
}
return ret;
}
size_t esp_himem_reserved_area_size(void) {
size_t esp_himem_reserved_area_size(void)
{
return CACHE_BLOCKSIZE * SPIRAM_BANKSWITCH_RESERVE;
}
void __attribute__((constructor)) esp_himem_init(void)
{
if (SPIRAM_BANKSWITCH_RESERVE == 0) return;
if (SPIRAM_BANKSWITCH_RESERVE == 0) {
return;
}
uint32_t maxram = 0;
esp_psram_impl_get_available_size(&maxram);
//catch double init
@ -161,7 +165,6 @@ void __attribute__((constructor)) esp_himem_init(void)
SPIRAM_BANKSWITCH_RESERVE, (paddr_end - paddr_start) / 1024);
}
//Allocate count not-necessarily consecutive physical RAM blocks, return numbers in blocks[]. Return
//true if blocks can be allocated, false if not.
static bool allocate_blocks(int count, uint16_t *blocks_out)
@ -186,7 +189,6 @@ static bool allocate_blocks(int count, uint16_t *blocks_out)
}
}
esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out)
{
if (size % CACHE_BLOCKSIZE != 0) {
@ -238,7 +240,6 @@ esp_err_t esp_himem_free(esp_himem_handle_t handle)
return ESP_OK;
}
esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle_out)
{
ESP_RETURN_ON_FALSE(s_ram_descriptor != NULL, ESP_ERR_INVALID_STATE, TAG, "Himem not available!");
@ -296,7 +297,6 @@ esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle)
return ESP_OK;
}
esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr)
{
int ram_block = ram_offset / CACHE_BLOCKSIZE;

7
components/esp_psram/esp32/esp_psram_extram_cache.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,7 +15,6 @@
#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
#endif
/*
Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
@ -29,7 +28,9 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
volatile uint8_t *psram = (volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
int cache_was_disabled = 0;
if (!esp_psram_is_initialized()) return;
if (!esp_psram_is_initialized()) {
return;
}
//We need cache enabled for this to work. Re-enable it if needed; make sure we
//disable it again on exit as well.

3
components/esp_psram/esp32/esp_psram_impl_quad.c
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@ -8,7 +8,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "string.h"
#include "esp_attr.h"
@ -291,7 +290,6 @@ static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
}
//start sending cmd/addr and optionally, receiving data
static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t *pRxData, uint16_t rxByteLen,
psram_cmd_mode_t cmd_mode)
@ -1148,7 +1146,6 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
{
if (!out_size_bytes) {

3
components/esp_psram/esp32s2/esp_psram_impl_quad.c
View File

@ -8,7 +8,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "string.h"
#include "esp_attr.h"
@ -105,7 +104,6 @@ typedef enum {
PSRAM_CLK_MODE_MAX,
} psram_clk_mode_t;
typedef enum {
PSRAM_EID_SIZE_16MBITS = 0,
PSRAM_EID_SIZE_32MBITS = 1,
@ -548,7 +546,6 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
/*---------------------------------------------------------------------------------
* Following APIs are not required to be IRAM-Safe
*

4
components/esp_psram/esp32s3/esp_psram_impl_octal.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -43,7 +43,6 @@
#define OCT_PSRAM_PAGE_SIZE 2 //2 for 1024B
#define OCT_PSRAM_ECC_ENABLE_MASK BIT(8)
typedef struct {
union {
struct {
@ -377,7 +376,6 @@ static void s_config_psram_spi_phases(void)
Cache_Resume_DCache(0);
}
/*---------------------------------------------------------------------------------
* Following APIs are not required to be IRAM-Safe
*

4
components/esp_psram/esp32s3/esp_psram_impl_quad.c
View File

@ -1,10 +1,9 @@
/*
* SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2013-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "string.h"
#include "esp_attr.h"
@ -378,7 +377,6 @@ static void config_psram_spi_phases(void)
CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
/*---------------------------------------------------------------------------------
* Following APIs are not required to be IRAM-Safe
*

10
components/esp_psram/include/esp32/himem.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -40,7 +40,6 @@ typedef struct esp_himem_rangedata_t *esp_himem_rangehandle_t;
*/
esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out);
/**
* @brief Allocate a memory region to map blocks into
*
@ -79,7 +78,6 @@ esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle
*/
esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr);
/**
* @brief Free a block of physical memory
*
@ -92,8 +90,6 @@ esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range
*/
esp_err_t esp_himem_free(esp_himem_handle_t handle);
/**
* @brief Free a mapping range
*
@ -106,7 +102,6 @@ esp_err_t esp_himem_free(esp_himem_handle_t handle);
*/
esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle);
/**
* @brief Unmap a region
*
@ -118,7 +113,6 @@ esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle);
*/
esp_err_t esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len);
/**
* @brief Get total amount of memory under control of himem API
*
@ -133,7 +127,6 @@ size_t esp_himem_get_phys_size(void);
*/
size_t esp_himem_get_free_size(void);
/**
* @brief Get amount of SPI memory address space needed for bankswitching
*
@ -144,7 +137,6 @@ size_t esp_himem_get_free_size(void);
*/
size_t esp_himem_reserved_area_size(void);
#ifdef __cplusplus
}
#endif

2
components/esp_psram/include/esp_private/esp_psram_io.h
View File

@ -14,7 +14,6 @@
extern "C" {
#endif
/**
* @brief get psram CS IO
*
@ -25,7 +24,6 @@ extern "C" {
*/
uint8_t esp_psram_io_get_cs_io(void);
#ifdef __cplusplus
}
#endif

2
components/esp_psram/include/esp_private/mmu_psram_flash.h
View File

@ -60,7 +60,6 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page);
#endif //#if CONFIG_SPIRAM_RODATA
/*----------------------------------------------------------------------------
Part 2 APIs (See @Backgrounds on top of this file)
-------------------------------------------------------------------------------*/
@ -132,7 +131,6 @@ uint32_t rodata_flash_end_page_get(void);
int rodata_flash2spiram_offset(void);
#endif // #if CONFIG_SPIRAM_RODATA
#ifdef __cplusplus
}
#endif

1
components/esp_psram/include/esp_psram.h
View File

@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stddef.h>

14
components/esp_psram/test_apps/psram/main/test_4mpsram.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -29,7 +29,9 @@ static void test_psram_content(void)
for (p = 0; p < (s / sizeof(int)); p += 4) {
if (test_area[p] != (p ^ 0xAAAAAAAA)) {
errct++;
if (errct==1) initial_err=p*4;
if (errct == 1) {
initial_err = p * 4;
}
}
}
if (errct) {
@ -48,10 +50,14 @@ bool psram_is_32mbit_ver0(void);
static void test_spi_bus_occupy(spi_host_device_t expected_occupied_host)
{
bool claim_hspi = spicommon_periph_claim(HSPI_HOST, "ut-hspi");
if (claim_hspi) ESP_LOGI(TAG, "HSPI claimed.");
if (claim_hspi) {
ESP_LOGI(TAG, "HSPI claimed.");
}
bool claim_vspi = spicommon_periph_claim(VSPI_HOST, "ut-vspi");
if (claim_vspi) ESP_LOGI(TAG, "VSPI claimed.");
if (claim_vspi) {
ESP_LOGI(TAG, "VSPI claimed.");
}
if (expected_occupied_host == HSPI_HOST) {
TEST_ASSERT_FALSE(claim_hspi);

3
components/esp_psram/test_apps/psram/main/test_himem.c
View File

@ -75,7 +75,6 @@ static bool test_region(int check_size, int seed)
return ret;
}
static volatile int testsDone;
static void memtest_thread(void *arg)
@ -90,7 +89,6 @@ static void memtest_thread(void *arg)
vTaskDelete(NULL);
}
TEST_CASE("high psram memory test", "[himem]")
{
printf("Doing single-core test\n");
@ -108,7 +106,6 @@ TEST_CASE("high psram memory test", "[himem]")
vTaskDelay(100);
}
#endif
#endif // CONFIG_IDF_TARGET_ESP32

4
components/esp_psram/test_apps/psram/main/test_psram.c
View File

@ -22,7 +22,6 @@
__attribute__((unused)) const static char *TAG = "PSRAM";
TEST_CASE("test psram heap allocable", "[psram]")
{
size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM);
@ -47,7 +46,6 @@ TEST_CASE("test psram heap allocable","[psram]")
free(ext_buffer);
}
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA
#include "esp_partition.h"
#include "driver/gptimer.h"
@ -132,7 +130,6 @@ TEST_CASE("test spi1 flash operation after putting .text and .rodata into psram"
}
#endif //CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA
TEST_CASE("test psram unaligned access", "[psram]")
{
size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
@ -174,7 +171,6 @@ TEST_CASE("test psram unaligned access", "[psram]")
uint32_t val_32bit = *(uint32_t *)unaligned_ptr;
ESP_LOGV(TAG, "i is %d, j is %d, val_32bit val is 0x%"PRIx32, i, j, val_32bit);
uint8_t second_byte = ((i + j) & 0xff) + 1;
uint8_t third_byte = ((i + j) & 0xff) + 2;
uint8_t fourth_byte = ((i + j) & 0xff) + 3;