From 3de0b7218faea1b595acd553ee3ec9d75f50942d Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 9 Oct 2023 15:27:41 +0800 Subject: [PATCH 1/3] refactor(esp_adc): reformat code with astyle_py 2 --- .../test_apps/adc/main/test_adc_wifi.c | 52 +++++++++---------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/components/esp_adc/test_apps/adc/main/test_adc_wifi.c b/components/esp_adc/test_apps/adc/main/test_adc_wifi.c index d0ef8d3f0f..a967fcf9f8 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc_wifi.c +++ b/components/esp_adc/test_apps/adc/main/test_adc_wifi.c @@ -46,38 +46,38 @@ static int test_adc_io; static bool test_list[TEST_NUM] = {1, 1, 0, 0, 1, 0, 1, 0}; static void wifi_event_handler(void* arg, esp_event_base_t event_base, - int32_t event_id, void* event_data) + int32_t event_id, void* event_data) { printf("ev_handle_called.\n"); - switch(event_id) { - case WIFI_EVENT_STA_START: - ESP_LOGI(TAG, "WIFI_EVENT_STA_START"); - //do not actually connect in test case - //; - break; - case WIFI_EVENT_STA_DISCONNECTED: - ESP_LOGI(TAG, "WIFI_EVENT_STA_DISCONNECTED"); - TEST_ESP_OK(esp_wifi_connect()); - break; - default: - break; + switch (event_id) { + case WIFI_EVENT_STA_START: + ESP_LOGI(TAG, "WIFI_EVENT_STA_START"); + //do not actually connect in test case + //; + break; + case WIFI_EVENT_STA_DISCONNECTED: + ESP_LOGI(TAG, "WIFI_EVENT_STA_DISCONNECTED"); + TEST_ESP_OK(esp_wifi_connect()); + break; + default: + break; } return ; } static void ip_event_handler(void* arg, esp_event_base_t event_base, - int32_t event_id, void* event_data) + int32_t event_id, void* event_data) { ip_event_got_ip_t *event; printf("ev_handle_called.\n"); - switch(event_id) { - case IP_EVENT_STA_GOT_IP: - event = (ip_event_got_ip_t*)event_data; - ESP_LOGI(TAG, "IP_EVENT_STA_GOT_IP"); - ESP_LOGI(TAG, "got ip:" IPSTR, IP2STR(&event->ip_info.ip)); - break; - default: - break; + switch (event_id) { + case IP_EVENT_STA_GOT_IP: + event = (ip_event_got_ip_t*)event_data; + ESP_LOGI(TAG, "IP_EVENT_STA_GOT_IP"); + ESP_LOGI(TAG, "got ip:" IPSTR, IP2STR(&event->ip_info.ip)); + break; + default: + break; } return ; @@ -133,7 +133,7 @@ __attribute__((unused)) static void adc_work_with_wifi(adc_unit_t unit_id, adc_c TEST_ESP_OK(nvs_flash_erase()); r = nvs_flash_init(); } - TEST_ESP_OK( r); + TEST_ESP_OK(r); esp_netif_init(); event_init(); esp_netif_create_default_wifi_sta(); @@ -179,13 +179,11 @@ __attribute__((unused)) static void adc_work_with_wifi(adc_unit_t unit_id, adc_c test_adc_set_io_level(unit_id, channel, test_list[i]); target_value = test_list[i] ? ADC_TEST_HIGH_VAL : ADC_TEST_LOW_VAL; - /* ADC single read before WIFI start */ TEST_ESP_OK(adc_oneshot_read(adc_handle, channel, &read_raw)); printf("Before WiFi starts, ADC read: %d (target_value: %d)\n", read_raw, target_value); TEST_ASSERT_INT_WITHIN(ADC_ERROR_THRES, target_value, read_raw); - /* ADC single read when WIFI is on */ TEST_ESP_OK(esp_wifi_start()); #if CONFIG_IDF_TARGET_ESP32 @@ -220,7 +218,7 @@ __attribute__((unused)) static void adc_work_with_wifi(adc_unit_t unit_id, adc_c #if CONFIG_IDF_TARGET_ESP32C6 // On ESP32C6, ADC need to call two modem clocks: modem_syscon_ll_enable_fe_80m_clock and modem_syscon_ll_enable_fe_apb_clock. // Without calling these two clocks, PWDET mode will not take into effect, so ADC readings will be wrong. -TEST_CASE("ADC1 work with WiFi","[adc]") +TEST_CASE("ADC1 work with WiFi", "[adc]") { adc_work_with_wifi(ADC_UNIT_1, ADC1_WIFI_TEST_CHAN0); } @@ -228,7 +226,7 @@ TEST_CASE("ADC1 work with WiFi","[adc]") #if (SOC_ADC_PERIPH_NUM >= 2) && !CONFIG_IDF_TARGET_ESP32C3 // On ESP32C3, ADC2 is no longer supported, due to its HW limitation. -TEST_CASE("ADC2 work with WiFi","[adc]") +TEST_CASE("ADC2 work with WiFi", "[adc]") { adc_work_with_wifi(ADC_UNIT_2, ADC2_WIFI_TEST_CHAN0); } From fc4b9d95079270c035b7fa0f745c14c41a28d374 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 9 Oct 2023 15:28:11 +0800 Subject: [PATCH 2/3] refactor(esp_mm): reformat code with astyle_py 2 --- components/esp_mm/include/esp_mmu_map.h | 1 - .../include/esp_private/esp_cache_esp32_private.h | 1 - .../esp_mm/include/esp_private/esp_cache_private.h | 1 - .../esp_mm/include/esp_private/esp_mmu_map_private.h | 2 -- .../components/test_mm_utils/include/test_mm_utils.h | 1 - components/esp_mm/test_apps/mm/main/test_app_main.c | 1 - .../esp_mm/test_apps/mm/main/test_cache_msync.c | 4 ---- .../esp_mm/test_apps/mmap_hw/main/test_mmap_hw.c | 12 ++++-------- 8 files changed, 4 insertions(+), 19 deletions(-) diff --git a/components/esp_mm/include/esp_mmu_map.h b/components/esp_mm/include/esp_mmu_map.h index 355b0c9750..e4a42e483d 100644 --- a/components/esp_mm/include/esp_mmu_map.h +++ b/components/esp_mm/include/esp_mmu_map.h @@ -35,7 +35,6 @@ extern "C" { * - A Slot is the vaddr range between 2 blocks. */ - /** * MMAP flags */ diff --git a/components/esp_mm/include/esp_private/esp_cache_esp32_private.h b/components/esp_mm/include/esp_private/esp_cache_esp32_private.h index a8642daf5c..2180e64aa5 100644 --- a/components/esp_mm/include/esp_private/esp_cache_esp32_private.h +++ b/components/esp_mm/include/esp_private/esp_cache_esp32_private.h @@ -53,7 +53,6 @@ void cache_register_writeback(cache_driver_t *func); */ void cache_sync(void); - #ifdef __cplusplus } #endif diff --git a/components/esp_mm/include/esp_private/esp_cache_private.h b/components/esp_mm/include/esp_private/esp_cache_private.h index 7735d298b9..624e6dd087 100644 --- a/components/esp_mm/include/esp_private/esp_cache_private.h +++ b/components/esp_mm/include/esp_private/esp_cache_private.h @@ -58,7 +58,6 @@ esp_err_t esp_cache_aligned_malloc(size_t size, uint32_t flags, void **out_ptr, */ esp_err_t esp_cache_aligned_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, size_t *actual_size); - #ifdef __cplusplus } #endif diff --git a/components/esp_mm/include/esp_private/esp_mmu_map_private.h b/components/esp_mm/include/esp_private/esp_mmu_map_private.h index d51817542b..b66d6c390c 100644 --- a/components/esp_mm/include/esp_private/esp_mmu_map_private.h +++ b/components/esp_mm/include/esp_private/esp_mmu_map_private.h @@ -14,7 +14,6 @@ extern "C" { #endif - /** * Memory Mapping Private APIs for MMU supported memory */ @@ -52,7 +51,6 @@ esp_err_t esp_mmu_map_reserve_block_with_caps(size_t size, mmu_mem_caps_t caps, */ esp_err_t esp_mmu_map_dump_mapped_blocks_private(void); - #ifdef __cplusplus } #endif diff --git a/components/esp_mm/test_apps/components/test_mm_utils/include/test_mm_utils.h b/components/esp_mm/test_apps/components/test_mm_utils/include/test_mm_utils.h index ded087a326..1e6d2f8223 100644 --- a/components/esp_mm/test_apps/components/test_mm_utils/include/test_mm_utils.h +++ b/components/esp_mm/test_apps/components/test_mm_utils/include/test_mm_utils.h @@ -14,7 +14,6 @@ extern "C" { #endif - /** * Set addr space dirty * diff --git a/components/esp_mm/test_apps/mm/main/test_app_main.c b/components/esp_mm/test_apps/mm/main/test_app_main.c index 03bdfb96dc..1632fa3c8c 100644 --- a/components/esp_mm/test_apps/mm/main/test_app_main.c +++ b/components/esp_mm/test_apps/mm/main/test_app_main.c @@ -61,6 +61,5 @@ void app_main(void) printf("| |___/\\__/ / | | | | || | | | | | | |___/\\__/ / | |\r\n"); printf("\\____/\\____/\\_| \\_| |_/\\_| |_/ \\_/ \\____/\\____/ \\_/\r\n"); - unity_run_menu(); } diff --git a/components/esp_mm/test_apps/mm/main/test_cache_msync.c b/components/esp_mm/test_apps/mm/main/test_cache_msync.c index 21ad6e5f00..8b4c2200dd 100644 --- a/components/esp_mm/test_apps/mm/main/test_cache_msync.c +++ b/components/esp_mm/test_apps/mm/main/test_cache_msync.c @@ -30,7 +30,6 @@ const static char *TAG = "CACHE_TEST"; #define TEST_NUM 10 #define TEST_BUF {0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9} - #define TEST_OFFSET 0x100000 #if CONFIG_IDF_TARGET_ESP32S2 #define TEST_SYNC_START (SOC_DPORT_CACHE_ADDRESS_LOW + TEST_OFFSET) @@ -41,13 +40,11 @@ const static char *TAG = "CACHE_TEST"; #endif #define TEST_SYNC_SIZE 0x8000 - #define RECORD_TIME_PREPARE() uint32_t __t1, __t2 #define RECORD_TIME_START() do {__t1 = esp_cpu_get_cycle_count();} while(0) #define RECORD_TIME_END(p_time) do{__t2 = esp_cpu_get_cycle_count(); p_time = (__t2 - __t1);} while(0) #define GET_US_BY_CCOUNT(t) ((double)(t)/CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) - static void s_test_with_msync_cb(void *arg) { (void)arg; @@ -156,7 +153,6 @@ TEST_CASE("test cache msync work with Flash operation when XIP from PSRAM", "[ca } #endif //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA - #if CONFIG_SPIRAM /*--------------------------------------------------------------- Test esp_cache_msync with PSRAM stack diff --git a/components/esp_mm/test_apps/mmap_hw/main/test_mmap_hw.c b/components/esp_mm/test_apps/mmap_hw/main/test_mmap_hw.c index e34a0c56d7..0df1c5b6d0 100644 --- a/components/esp_mm/test_apps/mmap_hw/main/test_mmap_hw.c +++ b/components/esp_mm/test_apps/mmap_hw/main/test_mmap_hw.c @@ -56,7 +56,6 @@ typedef struct test_block_info_ { static LIST_HEAD(test_block_list_head_, test_block_info_) test_block_head; - static void s_fill_random_data(uint8_t *buffer, size_t size, int random_seed) { srand(random_seed); @@ -72,7 +71,7 @@ static bool s_test_mmap_data_by_random(uint8_t *mblock_ptr, size_t size, int ran for (int i = 0; i < size; i++) { uint8_t test_data = rand() % 0xff; - if(test_data != test_ptr[i]) { + if (test_data != test_ptr[i]) { printf("i: %d\n", i); printf("test_data: %d\n", test_data); printf("test_ptr[%d]: %d\n", i, test_ptr[i]); @@ -102,12 +101,11 @@ TEST_CASE("test all readable vaddr can map to flash", "[mmu]") ESP_LOGV(TAG, "rand seed: %d, write flash addr: %p...", test_seed, (void *)part->address); TEST_ESP_OK(esp_flash_write(part->flash_chip, sector_buf, part->address, sizeof(sector_buf))); - esp_err_t ret = ESP_FAIL; int count = 0; LIST_INIT(&test_block_head); while (1) { - test_block_info_t *block_info = heap_caps_calloc(1, sizeof(test_block_info_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + test_block_info_t *block_info = heap_caps_calloc(1, sizeof(test_block_info_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); TEST_ASSERT(block_info && "no mem"); void *ptr = NULL; @@ -144,7 +142,6 @@ TEST_CASE("test all readable vaddr can map to flash", "[mmu]") free(sector_buf); } - TEST_CASE("test all executable vaddr can map to flash", "[mmu]") { //Get the partition used for SPI1 erase operation @@ -157,7 +154,7 @@ TEST_CASE("test all executable vaddr can map to flash", "[mmu]") int count = 0; LIST_INIT(&test_block_head); while (1) { - test_block_info_t *block_info = heap_caps_calloc(1, sizeof(test_block_info_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT); + test_block_info_t *block_info = heap_caps_calloc(1, sizeof(test_block_info_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); TEST_ASSERT(block_info && "no mem"); void *ptr = NULL; @@ -173,8 +170,7 @@ TEST_CASE("test all executable vaddr can map to flash", "[mmu]") TEST_ASSERT(paddr == part->address + i); ESP_LOGV(TAG, "paddr: %p, on %s", (void *)paddr, (mem_target) == MMU_TARGET_FLASH0 ? "Flash" : "PSRAM"); } - } - else if (ret == ESP_ERR_NOT_FOUND) { + } else if (ret == ESP_ERR_NOT_FOUND) { free(block_info); break; } else { From 0beb637563e1e484d37e91b2377baa6af45b58c3 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 9 Oct 2023 15:28:42 +0800 Subject: [PATCH 3/3] refactor(esp_psram): reformat code with astyle_py 2 --- .../esp_psram/device/esp_psram_impl_ap_hex.c | 59 +++-- components/esp_psram/esp32/esp_himem.c | 32 +-- .../esp_psram/esp32/esp_psram_extram_cache.c | 35 +-- .../esp_psram/esp32/esp_psram_impl_quad.c | 11 +- .../esp_psram/esp32s2/esp_psram_impl_quad.c | 207 +++++++++--------- .../esp_psram/esp32s3/esp_psram_impl_octal.c | 132 ++++++----- .../esp_psram/esp32s3/esp_psram_impl_quad.c | 148 ++++++------- components/esp_psram/include/esp32/himem.h | 10 +- .../include/esp_private/esp_psram_io.h | 2 - .../include/esp_private/mmu_psram_flash.h | 2 - components/esp_psram/include/esp_psram.h | 1 - .../test_apps/psram/main/test_4mpsram.c | 30 ++- .../test_apps/psram/main/test_himem.c | 3 - .../test_apps/psram/main/test_psram.c | 6 +- 14 files changed, 325 insertions(+), 353 deletions(-) diff --git a/components/esp_psram/device/esp_psram_impl_ap_hex.c b/components/esp_psram/device/esp_psram_impl_ap_hex.c index 6f0eb248e6..cbf7990690 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_hex.c +++ b/components/esp_psram/device/esp_psram_impl_ap_hex.c @@ -16,7 +16,6 @@ // Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section #define PSRAM_RCC_ATOMIC() PERIPH_RCC_ATOMIC() - #define AP_HEX_PSRAM_SYNC_READ 0x0000 #define AP_HEX_PSRAM_SYNC_WRITE 0x8080 #define AP_HEX_PSRAM_BURST_READ 0x2020 @@ -35,7 +34,6 @@ #define AP_HEX_PSRAM_CS_ECC_HOLD_TIME 4 #define AP_HEX_PSRAM_CS_HOLD_DELAY 3 - typedef struct { union { struct { @@ -96,7 +94,6 @@ typedef struct { static const char* TAG = "hex_psram"; static uint32_t s_psram_size; //this stands for physical psram size in bytes - /** * Common psram transaction */ @@ -192,55 +189,54 @@ static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg) false); //Read MR2~3 register s_psram_common_transaction(spi_num, - AP_HEX_PSRAM_REG_READ, cmd_len, - 0x2, addr_bit_len, - dummy, - NULL, 0, - &out_reg->mr2.val, data_bit_len, - false); + AP_HEX_PSRAM_REG_READ, cmd_len, + 0x2, addr_bit_len, + dummy, + NULL, 0, + &out_reg->mr2.val, data_bit_len, + false); data_bit_len = 8; //Read MR4 register s_psram_common_transaction(spi_num, - AP_HEX_PSRAM_REG_READ, cmd_len, - 0x4, addr_bit_len, - dummy, - NULL, 0, - &out_reg->mr4.val, data_bit_len, - false); + AP_HEX_PSRAM_REG_READ, cmd_len, + 0x4, addr_bit_len, + dummy, + NULL, 0, + &out_reg->mr4.val, data_bit_len, + false); //Read MR8 register s_psram_common_transaction(spi_num, - AP_HEX_PSRAM_REG_READ, cmd_len, - 0x8, addr_bit_len, - dummy, - NULL, 0, - &out_reg->mr8.val, data_bit_len, - false); + AP_HEX_PSRAM_REG_READ, cmd_len, + 0x8, addr_bit_len, + dummy, + NULL, 0, + &out_reg->mr8.val, data_bit_len, + false); } static void s_print_psram_info(hex_psram_mode_reg_t *reg_val) { ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0x0d ? "AP" : "UNKNOWN"); ESP_EARLY_LOGI(TAG, "Latency : 0x%02x (%s)", reg_val->mr0.lt, reg_val->mr0.lt == 1 ? "Fixed" : "Variable"); - ESP_EARLY_LOGI(TAG, "DriveStr. : 0x%02x (%d Ohm)", reg_val->mr0.drive_str, reg_val->mr0.drive_str < 2 ? 25*(reg_val->mr0.drive_str + 1): 100*(reg_val->mr0.drive_str-1)); + ESP_EARLY_LOGI(TAG, "DriveStr. : 0x%02x (%d Ohm)", reg_val->mr0.drive_str, reg_val->mr0.drive_str < 2 ? 25 * (reg_val->mr0.drive_str + 1) : 100 * (reg_val->mr0.drive_str - 1)); ESP_EARLY_LOGI(TAG, "dev id : 0x%02x (generation %d)", reg_val->mr2.dev_id, reg_val->mr2.dev_id + 1); ESP_EARLY_LOGI(TAG, "density : 0x%02x (%d Mbit)", reg_val->mr2.density, reg_val->mr2.density == 0x1 ? 32 : - reg_val->mr2.density == 0X3 ? 64 : - reg_val->mr2.density == 0x5 ? 128 : - reg_val->mr2.density == 0x7 ? 256 : 0); + reg_val->mr2.density == 0X3 ? 64 : + reg_val->mr2.density == 0x5 ? 128 : + reg_val->mr2.density == 0x7 ? 256 : 0); ESP_EARLY_LOGI(TAG, "good-die : 0x%02x (%s)", reg_val->mr2.kgd, reg_val->mr2.kgd == 6 ? "Pass" : "Fail"); ESP_EARLY_LOGI(TAG, "SRF : 0x%02x (%s Refresh)", reg_val->mr3.srf, reg_val->mr3.srf == 0x1 ? "Fast" : "Slow"); ESP_EARLY_LOGI(TAG, "BurstType : 0x%02x (%s Wrap)", reg_val->mr8.bt, reg_val->mr8.bt == 1 && reg_val->mr8.bl != 3 ? "Hybrid" : ""); ESP_EARLY_LOGI(TAG, "BurstLen : 0x%02x (%d Byte)", reg_val->mr8.bl, reg_val->mr8.bl == 0x00 ? 16 : - reg_val->mr8.bl == 0x01 ? 32 : - reg_val->mr8.bl == 0x10 ? 64 : 2048); + reg_val->mr8.bl == 0x01 ? 32 : + reg_val->mr8.bl == 0x10 ? 64 : 2048); ESP_EARLY_LOGI(TAG, "BitMode : 0x%02x (%s Mode)", reg_val->mr8.x16, reg_val->mr8.x16 == 1 ? "X16" : "X8"); - ESP_EARLY_LOGI(TAG, "Readlatency : 0x%02x (%d cycles@%s)", reg_val->mr0.read_latency, reg_val->mr0.read_latency * 2 + 6, - reg_val->mr0.lt == 1 ? "Fixed" : "Variable"); + reg_val->mr0.lt == 1 ? "Fixed" : "Variable"); ESP_EARLY_LOGI(TAG, "DriveStrength: 0x%02x (1/%d)", reg_val->mr0.drive_str, reg_val->mr0.drive_str == 0x00 ? 1 : - reg_val->mr0.drive_str == 0x01 ? 2 : - reg_val->mr0.drive_str == 0x02 ? 4 : 8); + reg_val->mr0.drive_str == 0x01 ? 2 : + reg_val->mr0.drive_str == 0x02 ? 4 : 8); } static void s_config_mspi_for_psram(void) @@ -326,7 +322,6 @@ static void s_configure_psram_ecc(void) } #endif //#if CONFIG_SPIRAM_ECC_ENABLE - esp_err_t esp_psram_impl_enable(void) { PSRAM_RCC_ATOMIC() { diff --git a/components/esp_psram/esp32/esp_himem.c b/components/esp_psram/esp32/esp_himem.c index 3650bbfebc..40adecbab3 100644 --- a/components/esp_psram/esp32/esp_himem.c +++ b/components/esp_psram/esp32/esp_himem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -104,9 +104,9 @@ static inline int rangeblock_idx_valid(int rangeblock_idx) static void set_bank(int virt_bank, int phys_bank, int ct) { int r __attribute__((unused)); - r = cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct ); + r = cache_sram_mmu_set(0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct); assert(r == 0); - r = cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct ); + r = cache_sram_mmu_set(1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct); assert(r == 0); } @@ -120,28 +120,32 @@ size_t esp_himem_get_phys_size(void) size_t esp_himem_get_free_size(void) { - size_t ret=0; + size_t ret = 0; for (int i = 0; i < s_ramblockcnt; i++) { - if (!s_ram_descriptor[i].is_alloced) ret+=CACHE_BLOCKSIZE; + if (!s_ram_descriptor[i].is_alloced) { + ret += CACHE_BLOCKSIZE; + } } return ret; } -size_t esp_himem_reserved_area_size(void) { +size_t esp_himem_reserved_area_size(void) +{ return CACHE_BLOCKSIZE * SPIRAM_BANKSWITCH_RESERVE; } - void __attribute__((constructor)) esp_himem_init(void) { - if (SPIRAM_BANKSWITCH_RESERVE == 0) return; + if (SPIRAM_BANKSWITCH_RESERVE == 0) { + return; + } uint32_t maxram = 0; esp_psram_impl_get_available_size(&maxram); //catch double init - ESP_RETURN_ON_FALSE(s_ram_descriptor == NULL, , TAG, "already initialized"); //Looks weird; last arg is empty so it expands to 'return ;' - ESP_RETURN_ON_FALSE(s_range_descriptor == NULL, , TAG, "already initialized"); + ESP_RETURN_ON_FALSE(s_ram_descriptor == NULL,, TAG, "already initialized"); //Looks weird; last arg is empty so it expands to 'return ;' + ESP_RETURN_ON_FALSE(s_range_descriptor == NULL,, TAG, "already initialized"); //need to have some reserved banks - ESP_RETURN_ON_FALSE(SPIRAM_BANKSWITCH_RESERVE != 0, , TAG, "No banks reserved for himem"); + ESP_RETURN_ON_FALSE(SPIRAM_BANKSWITCH_RESERVE != 0,, TAG, "No banks reserved for himem"); //Start and end of physical reserved memory. Note it starts slightly under //the 4MiB mark as the reserved banks can't have an unity mapping to be used by malloc //anymore; we treat them as himem instead. @@ -158,10 +162,9 @@ void __attribute__((constructor)) esp_himem_init(void) return; } ESP_EARLY_LOGI(TAG, "Initialized. Using last %d 32KB address blocks for bank switching on %d KB of physical memory.", - SPIRAM_BANKSWITCH_RESERVE, (paddr_end - paddr_start)/1024); + SPIRAM_BANKSWITCH_RESERVE, (paddr_end - paddr_start) / 1024); } - //Allocate count not-necessarily consecutive physical RAM blocks, return numbers in blocks[]. Return //true if blocks can be allocated, false if not. static bool allocate_blocks(int count, uint16_t *blocks_out) @@ -186,7 +189,6 @@ static bool allocate_blocks(int count, uint16_t *blocks_out) } } - esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out) { if (size % CACHE_BLOCKSIZE != 0) { @@ -238,7 +240,6 @@ esp_err_t esp_himem_free(esp_himem_handle_t handle) return ESP_OK; } - esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle_out) { ESP_RETURN_ON_FALSE(s_ram_descriptor != NULL, ESP_ERR_INVALID_STATE, TAG, "Himem not available!"); @@ -296,7 +297,6 @@ esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle) return ESP_OK; } - esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr) { int ram_block = ram_offset / CACHE_BLOCKSIZE; diff --git a/components/esp_psram/esp32/esp_psram_extram_cache.c b/components/esp_psram/esp32/esp_psram_extram_cache.c index b21bbb7456..3184160100 100644 --- a/components/esp_psram/esp32/esp_psram_extram_cache.c +++ b/components/esp_psram/esp32/esp_psram_extram_cache.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,7 +15,6 @@ #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH #endif - /* Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first, otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this. @@ -25,21 +24,23 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void) { int x; - volatile int i=0; - volatile uint8_t *psram=(volatile uint8_t*)SOC_EXTRAM_DATA_LOW; - int cache_was_disabled=0; + volatile int i = 0; + volatile uint8_t *psram = (volatile uint8_t*)SOC_EXTRAM_DATA_LOW; + int cache_was_disabled = 0; - if (!esp_psram_is_initialized()) return; + if (!esp_psram_is_initialized()) { + return; + } //We need cache enabled for this to work. Re-enable it if needed; make sure we //disable it again on exit as well. - if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) { - cache_was_disabled|=(1<<0); + if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) == 0) { + cache_was_disabled |= (1 << 0); DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); } #ifndef CONFIG_FREERTOS_UNICORE - if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) { - cache_was_disabled|=(1<<1); + if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) == 0) { + cache_was_disabled |= (1 << 1); DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S); } #endif @@ -49,8 +50,8 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void) Single-core and even/odd mode only have 32K of cache evenly distributed over the address lines. We can clear the cache by just reading 64K worth of cache lines. */ - for (x=0; x<1024*64; x+=32) { - i+=psram[x]; + for (x = 0; x < 1024 * 64; x += 32) { + i += psram[x]; } #else /* @@ -59,18 +60,18 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void) Note: this assumes the amount of external RAM is >2M. If it is 2M or less, what this code does is undefined. If we ever support external RAM chips of 2M or smaller, this may need adjusting. */ - for (x=0; x<1024*64; x+=32) { - i+=psram[x]; - i+=psram[x+(1024*1024*2)]; + for (x = 0; x < 1024 * 64; x += 32) { + i += psram[x]; + i += psram[x + (1024 * 1024 * 2)]; } #endif - if (cache_was_disabled&(1<<0)) { + if (cache_was_disabled & (1 << 0)) { while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ; DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); } #ifndef CONFIG_FREERTOS_UNICORE - if (cache_was_disabled&(1<<1)) { + if (cache_was_disabled & (1 << 1)) { while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1); DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S); } diff --git a/components/esp_psram/esp32/esp_psram_impl_quad.c b/components/esp_psram/esp32/esp_psram_impl_quad.c index b8c951aa4c..cac52cf9a9 100644 --- a/components/esp_psram/esp32/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32/esp_psram_impl_quad.c @@ -8,7 +8,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include "sdkconfig.h" #include "string.h" #include "esp_attr.h" @@ -291,10 +290,9 @@ static void psram_set_basic_read_mode(psram_spi_num_t spi_num) CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO); } - //start sending cmd/addr and optionally, receiving data static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t *pRxData, uint16_t rxByteLen, - psram_cmd_mode_t cmd_mode) + psram_cmd_mode_t cmd_mode) { //get cs1 CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M); @@ -311,7 +309,7 @@ static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t *pR } //Wait for SPI0 to idle - while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0); + while (READ_PERI_REG(SPI_EXT2_REG(0)) != 0); DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14); // Start send data @@ -838,7 +836,7 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_speed_ BIT64(psram_io->psram_spiq_sd0_io) | BIT64(psram_io->psram_spid_sd1_io) | BIT64(psram_io->psram_spihd_sd2_io) | - BIT64(psram_io->psram_spiwp_sd3_io) ); + BIT64(psram_io->psram_spiwp_sd3_io)); } //used in UT only @@ -871,7 +869,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init abort(); } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH)) { ESP_EARLY_LOGI(TAG, "This chip is %s", - (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)? "ESP32-PICO": "ESP32-U4WDH"); + (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) ? "ESP32-PICO" : "ESP32-U4WDH"); // We have better alternatives, though it's possible to use U4WDH together with PSRAM. // U4WDH shares the same pin config with PICO for historical reasons. rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config(); @@ -1148,7 +1146,6 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) } - esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes) { if (!out_size_bytes) { diff --git a/components/esp_psram/esp32s2/esp_psram_impl_quad.c b/components/esp_psram/esp32s2/esp_psram_impl_quad.c index 03f4a36c2f..a151af93a9 100644 --- a/components/esp_psram/esp32s2/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s2/esp_psram_impl_quad.c @@ -8,7 +8,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include "sdkconfig.h" #include "string.h" #include "esp_attr.h" @@ -105,7 +104,6 @@ typedef enum { PSRAM_CLK_MODE_MAX, } psram_clk_mode_t; - typedef enum { PSRAM_EID_SIZE_16MBITS = 0, PSRAM_EID_SIZE_32MBITS = 1, @@ -138,7 +136,7 @@ typedef enum { PSRAM_SPI_1 = 0x1, /* PSRAM_SPI_2, */ /* PSRAM_SPI_3, */ - PSRAM_SPI_MAX , + PSRAM_SPI_MAX, } psram_spi_num_t; typedef enum { @@ -168,7 +166,7 @@ static uint32_t s_psram_id = 0; static void psram_cache_init(psram_cache_speed_t psram_cache_mode, psram_vaddr_mode_t vaddrmode); extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); -static uint8_t s_psram_cs_io = (uint8_t)-1; +static uint8_t s_psram_cs_io = (uint8_t) -1; uint8_t esp_psram_impl_get_cs_io(void) { @@ -185,11 +183,11 @@ static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode) } } static void _psram_exec_cmd(int spi_num, - uint32_t cmd, int cmd_bit_len, - uint32_t addr, int addr_bit_len, - int dummy_bits, - uint8_t* mosi_data, int mosi_bit_len, - uint8_t* miso_data, int miso_bit_len) + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len) { esp_rom_spi_cmd_t conf; uint32_t _addr = addr; @@ -206,13 +204,13 @@ static void _psram_exec_cmd(int spi_num, } void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, - uint32_t cmd, int cmd_bit_len, - uint32_t addr, int addr_bit_len, - int dummy_bits, - uint8_t* mosi_data, int mosi_bit_len, - uint8_t* miso_data, int miso_bit_len, - uint32_t cs_mask, - bool is_write_erase_operation) + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation) { uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); @@ -220,7 +218,7 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); psram_set_op_mode(spi_num, mode); _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len, - dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len); + dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len); esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation); WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); @@ -233,13 +231,13 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, static void psram_disable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_CMD_QPI, - PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //switch psram burst length(32 bytes or 1024 bytes) @@ -247,35 +245,35 @@ static void psram_disable_qio_mode(int spi_num) static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode) { psram_exec_cmd(spi_num, mode, - PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //send reset command to psram, in spi mode static void psram_reset_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_RESET_EN, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_RESET_EN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_RESET, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_RESET, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } esp_err_t psram_enable_wrap(uint32_t wrap_size) @@ -285,28 +283,28 @@ esp_err_t psram_enable_wrap(uint32_t wrap_size) return ESP_OK; } switch (wrap_size) { - case 32: - case 0: - psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI); - current_wrap_size = wrap_size; - return ESP_OK; - case 16: - case 64: - default: - return ESP_FAIL; + case 32: + case 0: + psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI); + current_wrap_size = wrap_size; + return ESP_OK; + case 16: + case 64: + default: + return ESP_FAIL; } } bool psram_support_wrap_size(uint32_t wrap_size) { switch (wrap_size) { - case 0: - case 32: - return true; - case 16: - case 64: - default: - return false; + case 0: + case 32: + return true; + case 16: + case 64: + default: + return false; } } @@ -315,26 +313,26 @@ bool psram_support_wrap_size(uint32_t wrap_size) static void psram_read_id(int spi_num, uint32_t* dev_id) { psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_DEVICE_ID, 8, /* command and command bit len*/ - 0, 24, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - (uint8_t*) dev_id, 24, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_DEVICE_ID, 8, /* command and command bit len*/ + 0, 24, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + (uint8_t*) dev_id, 24, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //enter QPI mode static void IRAM_ATTR psram_enable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode) @@ -392,7 +390,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_speed_t mode) BIT64(psram_io.psram_spiq_sd0_io) | BIT64(psram_io.psram_spid_sd1_io) | BIT64(psram_io.psram_spihd_sd2_io) | - BIT64(psram_io.psram_spiwp_sd3_io) ); + BIT64(psram_io.psram_spiwp_sd3_io)); } //used in UT only @@ -456,7 +454,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(void) //psram init /* SPI1: send psram reset command */ /* SPI1: send QPI enable command */ - psram_reset_mode(PSRAM_SPI_1); + psram_reset_mode(PSRAM_SPI_1); psram_enable_qio_mode(PSRAM_SPI_1); // after sending commands, set spi1 clock mode and cs timing to normal mode. @@ -483,7 +481,7 @@ static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv) if (1 >= freqdiv) { WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); } else { - freqbits = (((freqdiv-1)<mr0.lt; @@ -137,26 +136,26 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co //write esp_rom_opiflash_exec_cmd(spi_num, mode, - OPI_PSRAM_REG_WRITE, cmd_len, - addr, addr_bit_len, - 0, - &mode_reg.mr0.val, 16, - NULL, 0, - BIT(1), - false); + OPI_PSRAM_REG_WRITE, cmd_len, + addr, addr_bit_len, + 0, + &mode_reg.mr0.val, 16, + NULL, 0, + BIT(1), + false); #if CONFIG_SPIRAM_ECC_ENABLE addr = 0x8; //0x8 is the MR8 register data_bit_len = 8; //read esp_rom_opiflash_exec_cmd(spi_num, mode, - OPI_PSRAM_REG_READ, cmd_len, - addr, addr_bit_len, - dummy, - NULL, 0, - &mode_reg.mr8.val, data_bit_len, - BIT(1), - false); + OPI_PSRAM_REG_READ, cmd_len, + addr, addr_bit_len, + dummy, + NULL, 0, + &mode_reg.mr8.val, data_bit_len, + BIT(1), + false); //modify mode_reg.mr8.bt = mode_reg_config->mr8.bt; @@ -164,13 +163,13 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co //write esp_rom_opiflash_exec_cmd(spi_num, mode, - OPI_PSRAM_REG_WRITE, cmd_len, - addr, addr_bit_len, - 0, - &mode_reg.mr8.val, 16, - NULL, 0, - BIT(1), - false); + OPI_PSRAM_REG_WRITE, cmd_len, + addr, addr_bit_len, + 0, + &mode_reg.mr8.val, 16, + NULL, 0, + BIT(1), + false); #endif } @@ -184,41 +183,41 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg) //Read MR0~1 register esp_rom_opiflash_exec_cmd(spi_num, mode, - OPI_PSRAM_REG_READ, cmd_len, - 0x0, addr_bit_len, - dummy, - NULL, 0, - &out_reg->mr0.val, data_bit_len, - BIT(1), - false); + OPI_PSRAM_REG_READ, cmd_len, + 0x0, addr_bit_len, + dummy, + NULL, 0, + &out_reg->mr0.val, data_bit_len, + BIT(1), + false); //Read MR2~3 register esp_rom_opiflash_exec_cmd(spi_num, mode, - OPI_PSRAM_REG_READ, cmd_len, - 0x2, addr_bit_len, - dummy, - NULL, 0, - &out_reg->mr2.val, data_bit_len, - BIT(1), - false); + OPI_PSRAM_REG_READ, cmd_len, + 0x2, addr_bit_len, + dummy, + NULL, 0, + &out_reg->mr2.val, data_bit_len, + BIT(1), + false); data_bit_len = 8; //Read MR4 register esp_rom_opiflash_exec_cmd(spi_num, mode, - OPI_PSRAM_REG_READ, cmd_len, - 0x4, addr_bit_len, - dummy, - NULL, 0, - &out_reg->mr4.val, data_bit_len, - BIT(1), - false); + OPI_PSRAM_REG_READ, cmd_len, + 0x4, addr_bit_len, + dummy, + NULL, 0, + &out_reg->mr4.val, data_bit_len, + BIT(1), + false); //Read MR8 register esp_rom_opiflash_exec_cmd(spi_num, mode, - OPI_PSRAM_REG_READ, cmd_len, - 0x8, addr_bit_len, - dummy, - NULL, 0, - &out_reg->mr8.val, data_bit_len, - BIT(1), - false); + OPI_PSRAM_REG_READ, cmd_len, + 0x8, addr_bit_len, + dummy, + NULL, 0, + &out_reg->mr8.val, data_bit_len, + BIT(1), + false); } static void s_print_psram_info(opi_psram_mode_reg_t *reg_val) @@ -226,22 +225,22 @@ static void s_print_psram_info(opi_psram_mode_reg_t *reg_val) ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0x0d ? "AP" : "UNKNOWN"); ESP_EARLY_LOGI(TAG, "dev id : 0x%02x (generation %d)", reg_val->mr2.dev_id, reg_val->mr2.dev_id + 1); ESP_EARLY_LOGI(TAG, "density : 0x%02x (%d Mbit)", reg_val->mr2.density, reg_val->mr2.density == 0x1 ? 32 : - reg_val->mr2.density == 0X3 ? 64 : - reg_val->mr2.density == 0x5 ? 128 : - reg_val->mr2.density == 0x7 ? 256 : 0); + reg_val->mr2.density == 0X3 ? 64 : + reg_val->mr2.density == 0x5 ? 128 : + reg_val->mr2.density == 0x7 ? 256 : 0); ESP_EARLY_LOGI(TAG, "good-die : 0x%02x (%s)", reg_val->mr2.gb, reg_val->mr2.gb == 1 ? "Pass" : "Fail"); ESP_EARLY_LOGI(TAG, "Latency : 0x%02x (%s)", reg_val->mr0.lt, reg_val->mr0.lt == 1 ? "Fixed" : "Variable"); ESP_EARLY_LOGI(TAG, "VCC : 0x%02x (%s)", reg_val->mr3.vcc, reg_val->mr3.vcc == 1 ? "3V" : "1.8V"); ESP_EARLY_LOGI(TAG, "SRF : 0x%02x (%s Refresh)", reg_val->mr3.srf, reg_val->mr3.srf == 0x1 ? "Fast" : "Slow"); ESP_EARLY_LOGI(TAG, "BurstType : 0x%02x (%s Wrap)", reg_val->mr8.bt, reg_val->mr8.bt == 1 && reg_val->mr8.bl != 3 ? "Hybrid" : ""); ESP_EARLY_LOGI(TAG, "BurstLen : 0x%02x (%d Byte)", reg_val->mr8.bl, reg_val->mr8.bl == 0x00 ? 16 : - reg_val->mr8.bl == 0x01 ? 32 : - reg_val->mr8.bl == 0x10 ? 64 : 1024); + reg_val->mr8.bl == 0x01 ? 32 : + reg_val->mr8.bl == 0x10 ? 64 : 1024); ESP_EARLY_LOGI(TAG, "Readlatency : 0x%02x (%d cycles@%s)", reg_val->mr0.read_latency, reg_val->mr0.read_latency * 2 + 6, - reg_val->mr0.lt == 1 ? "Fixed" : "Variable"); + reg_val->mr0.lt == 1 ? "Fixed" : "Variable"); ESP_EARLY_LOGI(TAG, "DriveStrength: 0x%02x (1/%d)", reg_val->mr0.drive_str, reg_val->mr0.drive_str == 0x00 ? 1 : - reg_val->mr0.drive_str == 0x01 ? 2 : - reg_val->mr0.drive_str == 0x02 ? 4 : 8); + reg_val->mr0.drive_str == 0x01 ? 2 : + reg_val->mr0.drive_str == 0x02 ? 4 : 8); } static void s_set_psram_cs_timing(void) @@ -377,7 +376,6 @@ static void s_config_psram_spi_phases(void) Cache_Resume_DCache(0); } - /*--------------------------------------------------------------------------------- * Following APIs are not required to be IRAM-Safe * diff --git a/components/esp_psram/esp32s3/esp_psram_impl_quad.c b/components/esp_psram/esp32s3/esp_psram_impl_quad.c index 644a7bdb91..27234062bf 100644 --- a/components/esp_psram/esp32s3/esp_psram_impl_quad.c +++ b/components/esp_psram/esp32s3/esp_psram_impl_quad.c @@ -1,10 +1,9 @@ /* - * SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2013-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - #include "sdkconfig.h" #include "string.h" #include "esp_attr.h" @@ -96,7 +95,7 @@ static uint32_t s_psram_size = 0; //this stands for physical psram size in byt static void config_psram_spi_phases(void); extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); -static uint8_t s_psram_cs_io = (uint8_t)-1; +static uint8_t s_psram_cs_io = (uint8_t) -1; uint8_t esp_psram_impl_get_cs_io(void) { @@ -113,11 +112,11 @@ static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode) } } static void _psram_exec_cmd(int spi_num, - uint32_t cmd, int cmd_bit_len, - uint32_t addr, int addr_bit_len, - int dummy_bits, - uint8_t* mosi_data, int mosi_bit_len, - uint8_t* miso_data, int miso_bit_len) + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len) { esp_rom_spi_cmd_t conf; uint32_t _addr = addr; @@ -134,13 +133,13 @@ static void _psram_exec_cmd(int spi_num, } void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, - uint32_t cmd, int cmd_bit_len, - uint32_t addr, int addr_bit_len, - int dummy_bits, - uint8_t* mosi_data, int mosi_bit_len, - uint8_t* miso_data, int miso_bit_len, - uint32_t cs_mask, - bool is_write_erase_operation) + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation) { uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); @@ -148,7 +147,7 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); psram_set_op_mode(spi_num, mode); _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len, - dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len); + dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len); esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation); WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); @@ -161,13 +160,13 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, static void psram_disable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_CMD_QPI, - PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //TODO IDF-4307 @@ -176,35 +175,35 @@ static void psram_disable_qio_mode(int spi_num) static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode) { psram_exec_cmd(spi_num, mode, - PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //send reset command to psram, in spi mode static void psram_reset_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_RESET_EN, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_RESET_EN, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_RESET, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_RESET, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } esp_err_t psram_enable_wrap(uint32_t wrap_size) @@ -215,28 +214,28 @@ esp_err_t psram_enable_wrap(uint32_t wrap_size) return ESP_OK; } switch (wrap_size) { - case 32: - case 0: - psram_set_wrap_burst_length(1, PSRAM_CMD_QPI); - current_wrap_size = wrap_size; - return ESP_OK; - case 16: - case 64: - default: - return ESP_FAIL; + case 32: + case 0: + psram_set_wrap_burst_length(1, PSRAM_CMD_QPI); + current_wrap_size = wrap_size; + return ESP_OK; + case 16: + case 64: + default: + return ESP_FAIL; } } bool psram_support_wrap_size(uint32_t wrap_size) { switch (wrap_size) { - case 0: - case 32: - return true; - case 16: - case 64: - default: - return false; + case 0: + case 32: + return true; + case 16: + case 64: + default: + return false; } } @@ -245,26 +244,26 @@ bool psram_support_wrap_size(uint32_t wrap_size) static void psram_read_id(int spi_num, uint32_t* dev_id) { psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_DEVICE_ID, 8, /* command and command bit len*/ - 0, 24, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - (uint8_t*) dev_id, 24, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_DEVICE_ID, 8, /* command and command bit len*/ + 0, 24, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + (uint8_t*) dev_id, 24, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } //enter QPI mode static void psram_enable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_CMD_SPI, - PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ - 0, 0, /* address and address bit len*/ - 0, /* dummy bit len */ - NULL, 0, /* tx data and tx bit len*/ - NULL, 0, /* rx data and rx bit len*/ - CS_PSRAM_SEL, /* cs bit mask*/ - false); /* whether is program/erase operation */ + PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ + 0, 0, /* address and address bit len*/ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len*/ + NULL, 0, /* rx data and rx bit len*/ + CS_PSRAM_SEL, /* cs bit mask*/ + false); /* whether is program/erase operation */ } static void psram_set_cs_timing(void) @@ -378,7 +377,6 @@ static void config_psram_spi_phases(void) CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) } - /*--------------------------------------------------------------------------------- * Following APIs are not required to be IRAM-Safe * diff --git a/components/esp_psram/include/esp32/himem.h b/components/esp_psram/include/esp32/himem.h index fb28f399df..e1af784453 100644 --- a/components/esp_psram/include/esp32/himem.h +++ b/components/esp_psram/include/esp32/himem.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,7 +40,6 @@ typedef struct esp_himem_rangedata_t *esp_himem_rangehandle_t; */ esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out); - /** * @brief Allocate a memory region to map blocks into * @@ -79,7 +78,6 @@ esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle */ esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr); - /** * @brief Free a block of physical memory * @@ -92,8 +90,6 @@ esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range */ esp_err_t esp_himem_free(esp_himem_handle_t handle); - - /** * @brief Free a mapping range * @@ -106,7 +102,6 @@ esp_err_t esp_himem_free(esp_himem_handle_t handle); */ esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle); - /** * @brief Unmap a region * @@ -118,7 +113,6 @@ esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle); */ esp_err_t esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len); - /** * @brief Get total amount of memory under control of himem API * @@ -133,7 +127,6 @@ size_t esp_himem_get_phys_size(void); */ size_t esp_himem_get_free_size(void); - /** * @brief Get amount of SPI memory address space needed for bankswitching * @@ -144,7 +137,6 @@ size_t esp_himem_get_free_size(void); */ size_t esp_himem_reserved_area_size(void); - #ifdef __cplusplus } #endif diff --git a/components/esp_psram/include/esp_private/esp_psram_io.h b/components/esp_psram/include/esp_private/esp_psram_io.h index d36faee9bf..34df2aa33a 100644 --- a/components/esp_psram/include/esp_private/esp_psram_io.h +++ b/components/esp_psram/include/esp_private/esp_psram_io.h @@ -14,7 +14,6 @@ extern "C" { #endif - /** * @brief get psram CS IO * @@ -25,7 +24,6 @@ extern "C" { */ uint8_t esp_psram_io_get_cs_io(void); - #ifdef __cplusplus } #endif diff --git a/components/esp_psram/include/esp_private/mmu_psram_flash.h b/components/esp_psram/include/esp_private/mmu_psram_flash.h index 9c0b62ee2b..b45b140100 100644 --- a/components/esp_psram/include/esp_private/mmu_psram_flash.h +++ b/components/esp_psram/include/esp_private/mmu_psram_flash.h @@ -60,7 +60,6 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page); #endif //#if CONFIG_SPIRAM_RODATA - /*---------------------------------------------------------------------------- Part 2 APIs (See @Backgrounds on top of this file) -------------------------------------------------------------------------------*/ @@ -132,7 +131,6 @@ uint32_t rodata_flash_end_page_get(void); int rodata_flash2spiram_offset(void); #endif // #if CONFIG_SPIRAM_RODATA - #ifdef __cplusplus } #endif diff --git a/components/esp_psram/include/esp_psram.h b/components/esp_psram/include/esp_psram.h index 75487573f0..8692aef7cf 100644 --- a/components/esp_psram/include/esp_psram.h +++ b/components/esp_psram/include/esp_psram.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #pragma once #include diff --git a/components/esp_psram/test_apps/psram/main/test_4mpsram.c b/components/esp_psram/test_apps/psram/main/test_4mpsram.c index 3994f59f0f..5395b9c1bb 100644 --- a/components/esp_psram/test_apps/psram/main/test_4mpsram.c +++ b/components/esp_psram/test_apps/psram/main/test_4mpsram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,20 +20,22 @@ static void test_psram_content(void) uint32_t *test_area = heap_caps_malloc(test_size, MALLOC_CAP_SPIRAM); size_t p; - size_t s=test_size; - int errct=0; - int initial_err=-1; - for (p=0; p<(s/sizeof(int)); p+=4) { - test_area[p]=p^0xAAAAAAAA; + size_t s = test_size; + int errct = 0; + int initial_err = -1; + for (p = 0; p < (s / sizeof(int)); p += 4) { + test_area[p] = p ^ 0xAAAAAAAA; } - for (p=0; p<(s/sizeof(int)); p+=4) { - if (test_area[p]!=(p^0xAAAAAAAA)) { + for (p = 0; p < (s / sizeof(int)); p += 4) { + if (test_area[p] != (p ^ 0xAAAAAAAA)) { errct++; - if (errct==1) initial_err=p*4; + if (errct == 1) { + initial_err = p * 4; + } } } if (errct) { - ESP_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %p", errct, s/32, initial_err+test_area); + ESP_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %p", errct, s / 32, initial_err + test_area); TEST_FAIL(); } else { ESP_LOGI(TAG, "SPI SRAM memory test OK"); @@ -48,10 +50,14 @@ bool psram_is_32mbit_ver0(void); static void test_spi_bus_occupy(spi_host_device_t expected_occupied_host) { bool claim_hspi = spicommon_periph_claim(HSPI_HOST, "ut-hspi"); - if (claim_hspi) ESP_LOGI(TAG, "HSPI claimed."); + if (claim_hspi) { + ESP_LOGI(TAG, "HSPI claimed."); + } bool claim_vspi = spicommon_periph_claim(VSPI_HOST, "ut-vspi"); - if (claim_vspi) ESP_LOGI(TAG, "VSPI claimed."); + if (claim_vspi) { + ESP_LOGI(TAG, "VSPI claimed."); + } if (expected_occupied_host == HSPI_HOST) { TEST_ASSERT_FALSE(claim_hspi); diff --git a/components/esp_psram/test_apps/psram/main/test_himem.c b/components/esp_psram/test_apps/psram/main/test_himem.c index 6f0d658f1f..cfb4372d20 100644 --- a/components/esp_psram/test_apps/psram/main/test_himem.c +++ b/components/esp_psram/test_apps/psram/main/test_himem.c @@ -75,7 +75,6 @@ static bool test_region(int check_size, int seed) return ret; } - static volatile int testsDone; static void memtest_thread(void *arg) @@ -90,7 +89,6 @@ static void memtest_thread(void *arg) vTaskDelete(NULL); } - TEST_CASE("high psram memory test", "[himem]") { printf("Doing single-core test\n"); @@ -108,7 +106,6 @@ TEST_CASE("high psram memory test", "[himem]") vTaskDelay(100); } - #endif #endif // CONFIG_IDF_TARGET_ESP32 diff --git a/components/esp_psram/test_apps/psram/main/test_psram.c b/components/esp_psram/test_apps/psram/main/test_psram.c index a471685c67..886afe7c1c 100644 --- a/components/esp_psram/test_apps/psram/main/test_psram.c +++ b/components/esp_psram/test_apps/psram/main/test_psram.c @@ -22,8 +22,7 @@ __attribute__((unused)) const static char *TAG = "PSRAM"; - -TEST_CASE("test psram heap allocable","[psram]") +TEST_CASE("test psram heap allocable", "[psram]") { size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM); ESP_LOGI(TAG, "largest size is %zu", largest_size); @@ -47,7 +46,6 @@ TEST_CASE("test psram heap allocable","[psram]") free(ext_buffer); } - #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA #include "esp_partition.h" #include "driver/gptimer.h" @@ -132,7 +130,6 @@ TEST_CASE("test spi1 flash operation after putting .text and .rodata into psram" } #endif //CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_RODATA - TEST_CASE("test psram unaligned access", "[psram]") { size_t largest_size = heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT); @@ -174,7 +171,6 @@ TEST_CASE("test psram unaligned access", "[psram]") uint32_t val_32bit = *(uint32_t *)unaligned_ptr; ESP_LOGV(TAG, "i is %d, j is %d, val_32bit val is 0x%"PRIx32, i, j, val_32bit); - uint8_t second_byte = ((i + j) & 0xff) + 1; uint8_t third_byte = ((i + j) & 0xff) + 2; uint8_t fourth_byte = ((i + j) & 0xff) + 3;