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Update LEDC, PCNT,Timer_Group driver for esp32s2beta.

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This commit is contained in:
kooho 2019-06-06 14:20:39 +08:00
parent eae6f5a1d6
commit f98e7bbccf
22 changed files with 1442 additions and 3733 deletions
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4
components/driver/include/driver/ledc.h
View File

@ -30,7 +30,9 @@ extern "C" {
#define LEDC_ERR_VAL (-1) #define LEDC_ERR_VAL (-1)
typedef enum { typedef enum {
#ifdef CONFIG_IDF_TARGET_ESP32
LEDC_HIGH_SPEED_MODE = 0, /*!< LEDC high speed speed_mode */ LEDC_HIGH_SPEED_MODE = 0, /*!< LEDC high speed speed_mode */
#endif
LEDC_LOW_SPEED_MODE, /*!< LEDC low speed speed_mode */ LEDC_LOW_SPEED_MODE, /*!< LEDC low speed speed_mode */
LEDC_SPEED_MODE_MAX, /*!< LEDC speed limit */ LEDC_SPEED_MODE_MAX, /*!< LEDC speed limit */
} ledc_mode_t; } ledc_mode_t;
@ -86,12 +88,14 @@ typedef enum {
LEDC_TIMER_12_BIT, /*!< LEDC PWM duty resolution of 12 bits */ LEDC_TIMER_12_BIT, /*!< LEDC PWM duty resolution of 12 bits */
LEDC_TIMER_13_BIT, /*!< LEDC PWM duty resolution of 13 bits */ LEDC_TIMER_13_BIT, /*!< LEDC PWM duty resolution of 13 bits */
LEDC_TIMER_14_BIT, /*!< LEDC PWM duty resolution of 14 bits */ LEDC_TIMER_14_BIT, /*!< LEDC PWM duty resolution of 14 bits */
#ifdef CONFIG_IDF_TARGET_ESP32
LEDC_TIMER_15_BIT, /*!< LEDC PWM duty resolution of 15 bits */ LEDC_TIMER_15_BIT, /*!< LEDC PWM duty resolution of 15 bits */
LEDC_TIMER_16_BIT, /*!< LEDC PWM duty resolution of 16 bits */ LEDC_TIMER_16_BIT, /*!< LEDC PWM duty resolution of 16 bits */
LEDC_TIMER_17_BIT, /*!< LEDC PWM duty resolution of 17 bits */ LEDC_TIMER_17_BIT, /*!< LEDC PWM duty resolution of 17 bits */
LEDC_TIMER_18_BIT, /*!< LEDC PWM duty resolution of 18 bits */ LEDC_TIMER_18_BIT, /*!< LEDC PWM duty resolution of 18 bits */
LEDC_TIMER_19_BIT, /*!< LEDC PWM duty resolution of 19 bits */ LEDC_TIMER_19_BIT, /*!< LEDC PWM duty resolution of 19 bits */
LEDC_TIMER_20_BIT, /*!< LEDC PWM duty resolution of 20 bits */ LEDC_TIMER_20_BIT, /*!< LEDC PWM duty resolution of 20 bits */
#endif
LEDC_TIMER_BIT_MAX, LEDC_TIMER_BIT_MAX,
} ledc_timer_bit_t; } ledc_timer_bit_t;

13
components/driver/include/driver/pcnt.h
View File

@ -47,10 +47,13 @@ typedef enum {
PCNT_UNIT_1 = 1, /*!< PCNT unit 1 */ PCNT_UNIT_1 = 1, /*!< PCNT unit 1 */
PCNT_UNIT_2 = 2, /*!< PCNT unit 2 */ PCNT_UNIT_2 = 2, /*!< PCNT unit 2 */
PCNT_UNIT_3 = 3, /*!< PCNT unit 3 */ PCNT_UNIT_3 = 3, /*!< PCNT unit 3 */
//ESP32-S2 only have 4 unit
#ifdef CONFIG_IDF_TARGET_ESP32
PCNT_UNIT_4 = 4, /*!< PCNT unit 4 */ PCNT_UNIT_4 = 4, /*!< PCNT unit 4 */
PCNT_UNIT_5 = 5, /*!< PCNT unit 5 */ PCNT_UNIT_5 = 5, /*!< PCNT unit 5 */
PCNT_UNIT_6 = 6, /*!< PCNT unit 6 */ PCNT_UNIT_6 = 6, /*!< PCNT unit 6 */
PCNT_UNIT_7 = 7, /*!< PCNT unit 7 */ PCNT_UNIT_7 = 7, /*!< PCNT unit 7 */
#endif
PCNT_UNIT_MAX, PCNT_UNIT_MAX,
} pcnt_unit_t; } pcnt_unit_t;
@ -67,11 +70,11 @@ typedef enum {
* @brief Selection of counter's events the may trigger an interrupt * @brief Selection of counter's events the may trigger an interrupt
*/ */
typedef enum { typedef enum {
PCNT_EVT_L_LIM = 0, /*!< PCNT watch point event: Minimum counter value */ PCNT_EVT_THRES_1 = BIT(2), /*!< PCNT watch point event: threshold1 value event */
PCNT_EVT_H_LIM = 1, /*!< PCNT watch point event: Maximum counter value */ PCNT_EVT_THRES_0 = BIT(3), /*!< PCNT watch point event: threshold0 value event */
PCNT_EVT_THRES_0 = 2, /*!< PCNT watch point event: threshold0 value event */ PCNT_EVT_L_LIM = BIT(4), /*!< PCNT watch point event: Minimum counter value */
PCNT_EVT_THRES_1 = 3, /*!< PCNT watch point event: threshold1 value event */ PCNT_EVT_H_LIM = BIT(5), /*!< PCNT watch point event: Maximum counter value */
PCNT_EVT_ZERO = 4, /*!< PCNT watch point event: counter value zero event */ PCNT_EVT_ZERO = BIT(6), /*!< PCNT watch point event: counter value zero event */
PCNT_EVT_MAX PCNT_EVT_MAX
} pcnt_evt_type_t; } pcnt_evt_type_t;

13
components/driver/include/driver/timer.h
View File

@ -89,6 +89,16 @@ typedef enum {
TIMER_AUTORELOAD_MAX, TIMER_AUTORELOAD_MAX,
} timer_autoreload_t; } timer_autoreload_t;
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
/**
* @brief Select timer source clock.
*/
typedef enum {
TIMER_SRC_CLK_APB = 0, /*!< Select APB as the source clock*/
TIMER_SRC_CLK_XTAL = 1, /*!< Select XTAL as the source clock*/
} timer_src_clk_t;
#endif
/** /**
* @brief Data structure with timer's configuration settings * @brief Data structure with timer's configuration settings
*/ */
@ -99,6 +109,9 @@ typedef struct {
timer_count_dir_t counter_dir; /*!< Counter direction */ timer_count_dir_t counter_dir; /*!< Counter direction */
bool auto_reload; /*!< Timer auto-reload */ bool auto_reload; /*!< Timer auto-reload */
uint32_t divider; /*!< Counter clock divider. The divider's range is from from 2 to 65536. */ uint32_t divider; /*!< Counter clock divider. The divider's range is from from 2 to 65536. */
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
timer_src_clk_t clk_sel; /*!< Use XTAL as source clock. */
#endif
} timer_config_t; } timer_config_t;

208
components/driver/ledc.c
View File

@ -1,4 +1,4 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@ -11,8 +11,8 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
#include <esp_types.h>
#include <string.h> #include <string.h>
#include <esp_types.h>
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/semphr.h" #include "freertos/semphr.h"
#include "freertos/xtensa_api.h" #include "freertos/xtensa_api.h"
@ -51,7 +51,11 @@ static ledc_isr_handle_t s_ledc_fade_isr_handle = NULL;
#define LEDC_VAL_NO_CHANGE (-1) #define LEDC_VAL_NO_CHANGE (-1)
#define LEDC_STEP_NUM_MAX (1023) #define LEDC_STEP_NUM_MAX (1023)
#define LEDC_DUTY_DECIMAL_BIT_NUM (4) #define LEDC_DUTY_DECIMAL_BIT_NUM (4)
#define LEDC_HPOINT_VAL_MAX (LEDC_HPOINT_HSCH1_V) #define LEDC_TIMER_DIV_NUM_MAX (0x3FFFF)
#define LEDC_DUTY_NUM_MAX (LEDC_DUTY_NUM_LSCH0_V)
#define LEDC_DUTY_CYCLE_MAX (LEDC_DUTY_CYCLE_LSCH0_V)
#define LEDC_DUTY_SCALE_MAX (LEDC_DUTY_SCALE_LSCH0_V)
#define LEDC_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH1_V)
#define LEDC_FADE_TOO_SLOW_STR "LEDC FADE TOO SLOW" #define LEDC_FADE_TOO_SLOW_STR "LEDC FADE TOO SLOW"
#define LEDC_FADE_TOO_FAST_STR "LEDC FADE TOO FAST" #define LEDC_FADE_TOO_FAST_STR "LEDC FADE TOO FAST"
static const char *LEDC_FADE_SERVICE_ERR_STR = "LEDC fade service not installed"; static const char *LEDC_FADE_SERVICE_ERR_STR = "LEDC fade service not installed";
@ -78,7 +82,11 @@ static esp_err_t ledc_enable_intr_type(ledc_mode_t speed_mode, uint32_t channel,
uint32_t intr_type = type; uint32_t intr_type = type;
portENTER_CRITICAL(&ledc_spinlock); portENTER_CRITICAL(&ledc_spinlock);
value = LEDC.int_ena.val; value = LEDC.int_ena.val;
#ifdef CONFIG_IDF_TARGET_ESP32
uint8_t int_en_base = LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S; uint8_t int_en_base = LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
uint8_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
#endif
if (speed_mode == LEDC_LOW_SPEED_MODE) { if (speed_mode == LEDC_LOW_SPEED_MODE) {
int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
} }
@ -139,7 +147,18 @@ esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_
LEDC_ARG_CHECK(timer_sel < LEDC_TIMER_MAX, "timer_select"); LEDC_ARG_CHECK(timer_sel < LEDC_TIMER_MAX, "timer_select");
portENTER_CRITICAL(&ledc_spinlock); portENTER_CRITICAL(&ledc_spinlock);
LEDC.timer_group[speed_mode].timer[timer_sel].conf.clock_divider = clock_divider; LEDC.timer_group[speed_mode].timer[timer_sel].conf.clock_divider = clock_divider;
LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = clk_src; #ifdef CONFIG_IDF_TARGET_ESP32
LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = clk_src;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
if(clk_src == LEDC_REF_TICK) {
//REF_TICK can only be used when APB is selected.
LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 1;
LEDC.conf.apb_clk_sel = 1;
} else {
LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 0;
LEDC.conf.apb_clk_sel = clk_src;
}
#endif
LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_resolution = duty_resolution; LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_resolution = duty_resolution;
ledc_ls_timer_update(speed_mode, timer_sel); ledc_ls_timer_update(speed_mode, timer_sel);
portEXIT_CRITICAL(&ledc_spinlock); portEXIT_CRITICAL(&ledc_spinlock);
@ -151,15 +170,18 @@ static IRAM_ATTR esp_err_t ledc_duty_config(ledc_mode_t speed_mode, ledc_channel
{ {
portENTER_CRITICAL(&ledc_spinlock); portENTER_CRITICAL(&ledc_spinlock);
if (hpoint_val >= 0) { if (hpoint_val >= 0) {
LEDC.channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val & LEDC_HPOINT_HSCH1_V; LEDC.channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val;
} }
if (duty_val >= 0) { if (duty_val >= 0) {
LEDC.channel_group[speed_mode].channel[channel_num].duty.duty = duty_val; LEDC.channel_group[speed_mode].channel[channel_num].duty.duty = duty_val;
} }
LEDC.channel_group[speed_mode].channel[channel_num].conf1.val = ((duty_direction & LEDC_DUTY_INC_HSCH0_V) << LEDC_DUTY_INC_HSCH0_S) | typeof(LEDC.channel_group[0].channel[0].conf1) channel_cfg;
((duty_num & LEDC_DUTY_NUM_HSCH0_V) << LEDC_DUTY_NUM_HSCH0_S) | channel_cfg.val = 0;
((duty_cycle & LEDC_DUTY_CYCLE_HSCH0_V) << LEDC_DUTY_CYCLE_HSCH0_S) | channel_cfg.duty_inc = duty_direction;
((duty_scale & LEDC_DUTY_SCALE_HSCH0_V) << LEDC_DUTY_SCALE_HSCH0_S); channel_cfg.duty_num = duty_num;
channel_cfg.duty_cycle = duty_cycle;
channel_cfg.duty_scale = duty_scale;
LEDC.channel_group[speed_mode].channel[channel_num].conf1.val = channel_cfg.val;
ledc_ls_channel_update(speed_mode, channel_num); ledc_ls_channel_update(speed_mode, channel_num);
portEXIT_CRITICAL(&ledc_spinlock); portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK; return ESP_OK;
@ -248,20 +270,22 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t* timer_conf)
(uint32_t ) div_param); (uint32_t ) div_param);
ret = ESP_FAIL; ret = ESP_FAIL;
} }
if (div_param > LEDC_DIV_NUM_HSTIMER0_V) { if (div_param > LEDC_TIMER_DIV_NUM_MAX) {
// APB_CLK results in divisor which too high. Try using REF_TICK as clock source. // APB_CLK results in divisor which too high. Try using REF_TICK as clock source.
timer_clk_src = LEDC_REF_TICK; timer_clk_src = LEDC_REF_TICK;
div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision;
if (div_param < 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { if (div_param < 256 || div_param > LEDC_TIMER_DIV_NUM_MAX) {
ESP_LOGE(LEDC_TAG, "requested frequency and duty resolution can not be achieved, try increasing freq_hz or duty_resolution. div_param=%d", ESP_LOGE(LEDC_TAG, "requested frequency and duty resolution can not be achieved, try increasing freq_hz or duty_resolution. div_param=%d",
(uint32_t ) div_param); (uint32_t ) div_param);
ret = ESP_FAIL; ret = ESP_FAIL;
} }
} else { } else {
if (speed_mode == LEDC_LOW_SPEED_MODE) { #ifdef CONFIG_IDF_TARGET_ESP32
if (speed_mode == LEDC_LOW_SPEED_MODE) {
//for now, we only select 80mhz for slow clk of LEDC low speed channels. //for now, we only select 80mhz for slow clk of LEDC low speed channels.
LEDC.conf.slow_clk_sel = 1; LEDC.conf.slow_clk_sel = 1;
} }
#endif
} }
// set timer parameters // set timer parameters
ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src); ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src);
@ -277,13 +301,7 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc
LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
if (speed_mode == LEDC_HIGH_SPEED_MODE) { gpio_matrix_out(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0);
#if CONFIG_IDF_TARGET_ESP32
gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0);
#endif
} else {
gpio_matrix_out(gpio_num, LEDC_LS_SIG_OUT0_IDX + ledc_channel, 0, 0);
}
return ESP_OK; return ESP_OK;
} }
@ -319,13 +337,8 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf)
/*set LEDC signal in gpio matrix*/ /*set LEDC signal in gpio matrix*/
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
if (speed_mode == LEDC_HIGH_SPEED_MODE) { gpio_matrix_out(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0);
#if CONFIG_IDF_TARGET_ESP32
gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0);
#endif
} else {
gpio_matrix_out(gpio_num, LEDC_LS_SIG_OUT0_IDX + ledc_channel, 0, 0);
}
return ret; return ret;
} }
@ -360,9 +373,9 @@ esp_err_t ledc_set_fade(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t
LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel"); LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
LEDC_ARG_CHECK(fade_direction < LEDC_DUTY_DIR_MAX, "fade_direction"); LEDC_ARG_CHECK(fade_direction < LEDC_DUTY_DIR_MAX, "fade_direction");
LEDC_ARG_CHECK(step_num <= LEDC_DUTY_NUM_HSCH0_V, "step_num"); LEDC_ARG_CHECK(step_num <= LEDC_DUTY_NUM_MAX, "step_num");
LEDC_ARG_CHECK(duty_cyle_num <= LEDC_DUTY_CYCLE_HSCH0_V, "duty_cycle_num"); LEDC_ARG_CHECK(duty_cyle_num <= LEDC_DUTY_CYCLE_MAX, "duty_cycle_num");
LEDC_ARG_CHECK(duty_scale <= LEDC_DUTY_SCALE_HSCH0_V, "duty_scale"); LEDC_ARG_CHECK(duty_scale <= LEDC_DUTY_SCALE_MAX, "duty_scale");
_ledc_fade_hw_acquire(speed_mode, channel); _ledc_fade_hw_acquire(speed_mode, channel);
ledc_duty_config(speed_mode, ledc_duty_config(speed_mode,
channel, //uint32_t chan_num, channel, //uint32_t chan_num,
@ -445,7 +458,7 @@ esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t
} else { } else {
clock_divider = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; clock_divider = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision;
} }
if (clock_divider <= 256 || clock_divider > LEDC_DIV_NUM_HSTIMER0) { if (clock_divider <= 256 || clock_divider > LEDC_TIMER_DIV_NUM_MAX) {
ESP_LOGE(LEDC_TAG, "div param err,div_param=%u", clock_divider); ESP_LOGE(LEDC_TAG, "div param err,div_param=%u", clock_divider);
ret = ESP_FAIL; ret = ESP_FAIL;
} }
@ -473,66 +486,75 @@ uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num)
return freq; return freq;
} }
static inline void ledc_calc_fade_end_channel(uint32_t *fade_end_status, int *channel, int *speed_mode)
{
int i = __builtin_ffs((*fade_end_status)) - 1;
(*fade_end_status) &= ~(1 << i);
*speed_mode = LEDC_LOW_SPEED_MODE;
*channel = i;
#ifdef CONFIG_IDF_TARGET_ESP32
if (i < LEDC_CHANNEL_MAX) {
*speed_mode = LEDC_HIGH_SPEED_MODE;
} else {
*channel = i - LEDC_CHANNEL_MAX;
}
#endif
}
void IRAM_ATTR ledc_fade_isr(void* arg) void IRAM_ATTR ledc_fade_isr(void* arg)
{ {
int channel;
portBASE_TYPE HPTaskAwoken = pdFALSE; portBASE_TYPE HPTaskAwoken = pdFALSE;
uint32_t intr_status = LEDC.int_st.val; //read LEDC interrupt status. uint32_t intr_status = LEDC.int_st.val; //read LEDC interrupt status.
LEDC.int_clr.val = intr_status; //clear LEDC interrupt status. uint32_t fade_end_status = (intr_status >> LEDC_LSTIMER0_OVF_INT_ST_S);
int speed_mode = LEDC_HIGH_SPEED_MODE; int speed_mode;
for (channel = 0; channel < LEDC_CHANNEL_MAX; channel++) { int channel;
if (intr_status & (BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S + channel) | BIT(LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S + channel))) { while (fade_end_status) {
if (intr_status & BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S + channel)) { ledc_calc_fade_end_channel(&fade_end_status, &channel, &speed_mode);
speed_mode = LEDC_HIGH_SPEED_MODE; if (s_ledc_fade_rec[speed_mode][channel] == NULL) {
} else { //fade object not initialized yet.
speed_mode = LEDC_LOW_SPEED_MODE; continue;
}
if (s_ledc_fade_rec[speed_mode][channel] == NULL) {
//fade object not initialized yet.
continue;
}
uint32_t duty_cur = LEDC.channel_group[speed_mode].channel[channel].duty_rd.duty_read >> LEDC_DUTY_DECIMAL_BIT_NUM;
if (duty_cur == s_ledc_fade_rec[speed_mode][channel]->target_duty) {
xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken);
if (HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR();
}
continue;
}
uint32_t duty_tar = s_ledc_fade_rec[speed_mode][channel]->target_duty;
int scale = s_ledc_fade_rec[speed_mode][channel]->scale;
if (scale == 0) {
xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken);
continue;
}
int cycle = s_ledc_fade_rec[speed_mode][channel]->cycle_num;
int delta = s_ledc_fade_rec[speed_mode][channel]->direction == LEDC_DUTY_DIR_DECREASE ? duty_cur - duty_tar : duty_tar - duty_cur;
int step = delta / scale > LEDC_STEP_NUM_MAX ? LEDC_STEP_NUM_MAX : delta / scale;
if (delta > scale) {
ledc_duty_config(
speed_mode,
channel,
LEDC_VAL_NO_CHANGE,
duty_cur << LEDC_DUTY_DECIMAL_BIT_NUM,
s_ledc_fade_rec[speed_mode][channel]->direction,
step,
cycle,
scale);
} else {
ledc_duty_config(
speed_mode,
channel,
LEDC_VAL_NO_CHANGE,
duty_tar << LEDC_DUTY_DECIMAL_BIT_NUM,
s_ledc_fade_rec[speed_mode][channel]->direction,
1,
1,
0);
}
LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 1;
} }
uint32_t duty_cur = LEDC.channel_group[speed_mode].channel[channel].duty_rd.duty_read >> LEDC_DUTY_DECIMAL_BIT_NUM;
if (duty_cur == s_ledc_fade_rec[speed_mode][channel]->target_duty) {
xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken);
continue;
}
uint32_t duty_tar = s_ledc_fade_rec[speed_mode][channel]->target_duty;
int scale = s_ledc_fade_rec[speed_mode][channel]->scale;
if (scale == 0) {
xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken);
continue;
}
int cycle = s_ledc_fade_rec[speed_mode][channel]->cycle_num;
int delta = s_ledc_fade_rec[speed_mode][channel]->direction == LEDC_DUTY_DIR_DECREASE ? duty_cur - duty_tar : duty_tar - duty_cur;
int step = delta / scale > LEDC_STEP_NUM_MAX ? LEDC_STEP_NUM_MAX : delta / scale;
if (delta > scale) {
ledc_duty_config(
speed_mode,
channel,
LEDC_VAL_NO_CHANGE,
duty_cur << LEDC_DUTY_DECIMAL_BIT_NUM,
s_ledc_fade_rec[speed_mode][channel]->direction,
step,
cycle,
scale);
} else {
ledc_duty_config(
speed_mode,
channel,
LEDC_VAL_NO_CHANGE,
duty_tar << LEDC_DUTY_DECIMAL_BIT_NUM,
s_ledc_fade_rec[speed_mode][channel]->direction,
1,
1,
0);
}
LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 1;
} }
LEDC.int_clr.val = intr_status; //clear LEDC interrupt status. LEDC.int_clr.val = intr_status; //clear LEDC interrupt status.
if (HPTaskAwoken == pdTRUE) {
portYIELD_FROM_ISR();
}
} }
static esp_err_t ledc_fade_channel_deinit(ledc_mode_t speed_mode, ledc_channel_t channel) static esp_err_t ledc_fade_channel_deinit(ledc_mode_t speed_mode, ledc_channel_t channel)
@ -643,16 +665,16 @@ static esp_err_t _ledc_set_fade_with_time(ledc_mode_t speed_mode, ledc_channel_t
if (total_cycles > duty_delta) { if (total_cycles > duty_delta) {
scale = 1; scale = 1;
cycle_num = total_cycles / duty_delta; cycle_num = total_cycles / duty_delta;
if (cycle_num > LEDC_DUTY_NUM_HSCH0_V) { if (cycle_num > LEDC_DUTY_NUM_MAX) {
ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_SLOW_STR); ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_SLOW_STR);
cycle_num = LEDC_DUTY_NUM_HSCH0_V; cycle_num = LEDC_DUTY_NUM_MAX;
} }
} else { } else {
cycle_num = 1; cycle_num = 1;
scale = duty_delta / total_cycles; scale = duty_delta / total_cycles;
if (scale > LEDC_DUTY_SCALE_HSCH0_V) { if (scale > LEDC_DUTY_SCALE_MAX) {
ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_FAST_STR); ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_FAST_STR);
scale = LEDC_DUTY_SCALE_HSCH0_V; scale = LEDC_DUTY_SCALE_MAX;
} }
} }
return _ledc_set_fade_with_step(speed_mode, channel, target_duty, scale, cycle_num); return _ledc_set_fade_with_step(speed_mode, channel, target_duty, scale, cycle_num);
@ -662,7 +684,11 @@ static void _ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, led
{ {
s_ledc_fade_rec[speed_mode][channel]->mode = fade_mode; s_ledc_fade_rec[speed_mode][channel]->mode = fade_mode;
// Clear interrupt status of channel // Clear interrupt status of channel
#ifdef CONFIG_IDF_TARGET_ESP32
int duty_resolution_ch0 = (speed_mode == LEDC_HIGH_SPEED_MODE) ? LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S : LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; int duty_resolution_ch0 = (speed_mode == LEDC_HIGH_SPEED_MODE) ? LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S : LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
int duty_resolution_ch0 = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S;
#endif
LEDC.int_clr.val |= BIT(duty_resolution_ch0 + channel); LEDC.int_clr.val |= BIT(duty_resolution_ch0 + channel);
// Enable interrupt for channel // Enable interrupt for channel
ledc_enable_intr_type(speed_mode, channel, LEDC_INTR_FADE_END); ledc_enable_intr_type(speed_mode, channel, LEDC_INTR_FADE_END);
@ -689,8 +715,8 @@ esp_err_t ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t channel
{ {
LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel"); LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_HSCH0_V), "fade scale"); LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_MAX), "fade scale");
LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_HSCH0_V), "cycle_num"); LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_MAX), "cycle_num");
LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty"); LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty");
LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK , LEDC_FADE_INIT_ERROR_STR, ESP_FAIL); LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK , LEDC_FADE_INIT_ERROR_STR, ESP_FAIL);
@ -777,8 +803,8 @@ esp_err_t ledc_set_fade_step_and_start(ledc_mode_t speed_mode, ledc_channel_t ch
LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel"); LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
LEDC_ARG_CHECK(fade_mode < LEDC_FADE_MAX, "fade_mode"); LEDC_ARG_CHECK(fade_mode < LEDC_FADE_MAX, "fade_mode");
LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK , LEDC_FADE_INIT_ERROR_STR, ESP_FAIL); LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK , LEDC_FADE_INIT_ERROR_STR, ESP_FAIL);
LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_HSCH0_V), "fade scale"); LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_MAX), "fade scale");
LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_HSCH0_V), "cycle_num"); LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_MAX), "cycle_num");
LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty"); LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty");
_ledc_op_lock_acquire(speed_mode, channel); _ledc_op_lock_acquire(speed_mode, channel);
_ledc_fade_hw_acquire(speed_mode, channel); _ledc_fade_hw_acquire(speed_mode, channel);

8
components/driver/pcnt.c
View File

@ -1,4 +1,4 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@ -53,7 +53,7 @@ esp_err_t pcnt_unit_config(const pcnt_config_t *pcnt_config)
PCNT_CHECK(unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_CHECK(unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_CHECK(channel < PCNT_CHANNEL_MAX, PCNT_CHANNEL_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_CHECK(channel < PCNT_CHANNEL_MAX, PCNT_CHANNEL_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_CHECK(input_io < 0 || (GPIO_IS_VALID_GPIO(input_io) && (input_io != ctrl_io)), "PCNT pluse input io error", ESP_ERR_INVALID_ARG); PCNT_CHECK(input_io < 0 || (GPIO_IS_VALID_GPIO(input_io) && (input_io != ctrl_io)), "PCNT pulse input io error", ESP_ERR_INVALID_ARG);
PCNT_CHECK(ctrl_io < 0 || GPIO_IS_VALID_GPIO(ctrl_io), "PCNT ctrl io error", ESP_ERR_INVALID_ARG); PCNT_CHECK(ctrl_io < 0 || GPIO_IS_VALID_GPIO(ctrl_io), "PCNT ctrl io error", ESP_ERR_INVALID_ARG);
PCNT_CHECK((pcnt_config->pos_mode < PCNT_COUNT_MAX) && (pcnt_config->neg_mode < PCNT_COUNT_MAX), PCNT_COUNT_MODE_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_CHECK((pcnt_config->pos_mode < PCNT_COUNT_MAX) && (pcnt_config->neg_mode < PCNT_COUNT_MAX), PCNT_COUNT_MODE_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_CHECK((pcnt_config->hctrl_mode < PCNT_MODE_MAX) && (pcnt_config->lctrl_mode < PCNT_MODE_MAX), PCNT_CTRL_MODE_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_CHECK((pcnt_config->hctrl_mode < PCNT_MODE_MAX) && (pcnt_config->lctrl_mode < PCNT_MODE_MAX), PCNT_CTRL_MODE_ERR_STR, ESP_ERR_INVALID_ARG);
@ -156,9 +156,9 @@ esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit)
{ {
PCNT_CHECK(pcnt_unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_CHECK(pcnt_unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG);
PCNT_ENTER_CRITICAL(&pcnt_spinlock); PCNT_ENTER_CRITICAL(&pcnt_spinlock);
#if CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
uint32_t reset_bit = BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2)); uint32_t reset_bit = BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2));
#elif CONFIG_IDF_TARGET_ESP32S2BETA #elif defined CONFIG_IDF_TARGET_ESP32S2BETA
uint32_t reset_bit = BIT(PCNT_PULSE_CNT_RST_U0_S + (pcnt_unit * 2)); uint32_t reset_bit = BIT(PCNT_PULSE_CNT_RST_U0_S + (pcnt_unit * 2));
#endif #endif
PCNT.ctrl.val |= reset_bit; PCNT.ctrl.val |= reset_bit;

24
components/driver/timer.c
View File

@ -1,4 +1,4 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@ -19,6 +19,7 @@
#include "freertos/xtensa_api.h" #include "freertos/xtensa_api.h"
#include "driver/timer.h" #include "driver/timer.h"
#include "driver/periph_ctrl.h" #include "driver/periph_ctrl.h"
#include "soc/rtc.h"
#include "sdkconfig.h" #include "sdkconfig.h"
static const char* TIMER_TAG = "timer_group"; static const char* TIMER_TAG = "timer_group";
@ -48,9 +49,9 @@ esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG); TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
TIMER_CHECK(timer_val != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG); TIMER_CHECK(timer_val != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
portENTER_CRITICAL_SAFE(&timer_spinlock[group_num]); portENTER_CRITICAL_SAFE(&timer_spinlock[group_num]);
#if CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
TG[group_num]->hw_timer[timer_num].update = 1; TG[group_num]->hw_timer[timer_num].update = 1;
#elif CONFIG_IDF_TARGET_ESP32S2BETA #elif defined CONFIG_IDF_TARGET_ESP32S2BETA
TG[group_num]->hw_timer[timer_num].update.update = 1; TG[group_num]->hw_timer[timer_num].update.update = 1;
#endif #endif
*timer_val = ((uint64_t) TG[group_num]->hw_timer[timer_num].cnt_high << 32) *timer_val = ((uint64_t) TG[group_num]->hw_timer[timer_num].cnt_high << 32)
@ -69,7 +70,15 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
esp_err_t err = timer_get_counter_value(group_num, timer_num, &timer_val); esp_err_t err = timer_get_counter_value(group_num, timer_num, &timer_val);
if (err == ESP_OK) { if (err == ESP_OK) {
uint16_t div = TG[group_num]->hw_timer[timer_num].config.divider; uint16_t div = TG[group_num]->hw_timer[timer_num].config.divider;
#ifdef CONFIG_IDF_TARGET_ESP32
*time = (double)timer_val * div / TIMER_BASE_CLK; *time = (double)timer_val * div / TIMER_BASE_CLK;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
if(TG[group_num]->hw_timer[timer_num].config.use_xtal) {
*time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000);
} else {
*time = (double)timer_val * div / rtc_clk_apb_freq_get();
}
#endif
} }
return err; return err;
} }
@ -227,9 +236,9 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
//but software reset does not clear interrupt status. This is not safe for application when enable the interrupt of timer_group. //but software reset does not clear interrupt status. This is not safe for application when enable the interrupt of timer_group.
//we need to disable the interrupt and clear the interrupt status here. //we need to disable the interrupt and clear the interrupt status here.
TG[group_num]->int_ena.val &= (~BIT(timer_num)); TG[group_num]->int_ena.val &= (~BIT(timer_num));
#if CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
TG[group_num]->int_clr_timers.val = BIT(timer_num); TG[group_num]->int_clr_timers.val = BIT(timer_num);
#elif CONFIG_IDF_TARGET_ESP32S2BETA #elif defined CONFIG_IDF_TARGET_ESP32S2BETA
TG[group_num]->int_clr.val = BIT(timer_num); TG[group_num]->int_clr.val = BIT(timer_num);
#endif #endif
TG[group_num]->hw_timer[timer_num].config.autoreload = config->auto_reload; TG[group_num]->hw_timer[timer_num].config.autoreload = config->auto_reload;
@ -239,6 +248,9 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
TG[group_num]->hw_timer[timer_num].config.alarm_en = config->alarm_en; TG[group_num]->hw_timer[timer_num].config.alarm_en = config->alarm_en;
TG[group_num]->hw_timer[timer_num].config.level_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 1 : 0); TG[group_num]->hw_timer[timer_num].config.level_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 1 : 0);
TG[group_num]->hw_timer[timer_num].config.edge_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 0 : 1); TG[group_num]->hw_timer[timer_num].config.edge_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 0 : 1);
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
TG[group_num]->hw_timer[timer_num].config.use_xtal = config->clk_sel;
#endif
TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]); TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
return ESP_OK; return ESP_OK;
} }
@ -293,5 +305,3 @@ esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG); TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
return timer_group_intr_disable(group_num, BIT(timer_num)); return timer_group_intr_disable(group_num, BIT(timer_num));
} }

28
components/soc/esp32/ledc_periph.c Normal file
View File

@ -0,0 +1,28 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/ledc_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every LEDC peripheral: GPIO signals
*/
const ledc_signal_conn_t ledc_periph_signal[2] = {
{
.sig_out0_idx = LEDC_HS_SIG_OUT0_IDX,
},
{
.sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
}
};

3
components/soc/esp32/sources.cmake
View File

@ -11,7 +11,8 @@ set(SOC_SRCS "cpu_util.c"
"sdio_slave_periph.c" "sdio_slave_periph.c"
"sdmmc_periph.c" "sdmmc_periph.c"
"soc_memory_layout.c" "soc_memory_layout.c"
"spi_periph.c") "spi_periph.c"
"ledc_periph.c")
if(NOT CMAKE_BUILD_EARLY_EXPANSION) if(NOT CMAKE_BUILD_EARLY_EXPANSION)
set_source_files_properties("esp32/rtc_clk.c" PROPERTIES set_source_files_properties("esp32/rtc_clk.c" PROPERTIES

3184
components/soc/esp32s2beta/include/soc/ledc_reg.h
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File diff suppressed because it is too large Load Diff

306
components/soc/esp32s2beta/include/soc/ledc_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@ -22,43 +22,31 @@ typedef volatile struct {
struct { struct {
struct { struct {
union { union {
struct {
uint32_t htimer_sel: 2;
uint32_t hsig_out_en: 1;
uint32_t hidle_lv: 1;
uint32_t hovf_num: 10;
uint32_t hovf_cnt_en: 1;
uint32_t reserved15: 16;
uint32_t clk_en: 1;
};
struct {
uint32_t ltimer_sel: 2;
uint32_t lsig_out_en: 1;
uint32_t lidle_lv: 1;
uint32_t low_speed_update: 1;
uint32_t lovf_num: 10;
uint32_t lovf_cnt_en: 1;
uint32_t reserved16: 16;
};
struct { struct {
uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/
uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/
uint32_t reserved28: 28; uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
uint32_t ovf_num: 10;
uint32_t ovf_cnt_en: 1;
uint32_t ovf_cnt_rst: 1;
uint32_t ovf_cnt_rst_st: 1;
uint32_t reserved18: 13;
uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/
}; };
uint32_t val; uint32_t val;
} conf0; } conf0;
union { union {
struct { struct {
uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ uint32_t hpoint: 14; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
uint32_t reserved20: 12; uint32_t reserved14: 16;
}; };
uint32_t val; uint32_t val;
} hpoint; } hpoint;
union { union {
struct { struct {
uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ uint32_t duty: 19; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
uint32_t reserved25: 7; uint32_t reserved19: 11;
}; };
uint32_t val; uint32_t val;
} duty; } duty;
@ -74,54 +62,42 @@ typedef volatile struct {
} conf1; } conf1;
union { union {
struct { struct {
uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ uint32_t duty_read: 19; /*This register represents the current duty of the output signal for high speed channel.*/
uint32_t reserved25: 7; uint32_t reserved19: 11;
}; };
uint32_t val; uint32_t val;
} duty_rd; } duty_rd;
} channel[8]; } channel[8];
} channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ } channel_group[1]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
struct { struct {
struct { struct {
union { union {
struct { struct {
uint32_t duty_resolution: 5; uint32_t duty_resolution: 4;
uint32_t clock_divider: 18; uint32_t clock_divider: 18;
uint32_t pause: 1; uint32_t pause: 1;
uint32_t rst: 1; uint32_t rst: 1;
uint32_t tick_sel: 1; uint32_t tick_sel: 1;
uint32_t low_speed_update: 1; uint32_t low_speed_update: 1;
uint32_t reserved27: 5; uint32_t reserved26: 6;
}; };
uint32_t val; uint32_t val;
} conf; } conf;
union { union {
struct { struct {
uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ uint32_t timer_cnt: 14; /*software can read this register to get the current counter value in high speed timer*/
uint32_t reserved20: 12; uint32_t reserved14: 16;
}; };
uint32_t val; uint32_t val;
} value; } value;
} timer[4]; } timer[4];
} timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ } timer_group[1]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
union { union {
struct { struct {
uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/
uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/
uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/
uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/
uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/
uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/
uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/
uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/
uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/
uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/
uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/
uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/
uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/
@ -130,97 +106,93 @@ typedef volatile struct {
uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/
uint32_t reserved24: 8; uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved20: 12;
}; };
uint32_t val; uint32_t val;
} int_raw; } int_raw;
union { union {
struct { struct {
uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ uint32_t lstimer0_ovf: 1;
uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ uint32_t lstimer1_ovf: 1;
uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ uint32_t lstimer2_ovf: 1;
uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ uint32_t lstimer3_ovf: 1;
uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ uint32_t duty_chng_end_lsch0: 1;
uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ uint32_t duty_chng_end_lsch1: 1;
uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ uint32_t duty_chng_end_lsch2: 1;
uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ uint32_t duty_chng_end_lsch3: 1;
uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done event.*/ uint32_t duty_chng_end_lsch4: 1;
uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ uint32_t duty_chng_end_lsch5: 1;
uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ uint32_t duty_chng_end_lsch6: 1;
uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ uint32_t duty_chng_end_lsch7: 1;
uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ uint32_t ovf_cnt_lsch0: 1;
uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ uint32_t ovf_cnt_lsch1: 1;
uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ uint32_t ovf_cnt_lsch2: 1;
uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ uint32_t ovf_cnt_lsch3: 1;
uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ uint32_t ovf_cnt_lsch4: 1;
uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ uint32_t ovf_cnt_lsch5: 1;
uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ uint32_t ovf_cnt_lsch6: 1;
uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ uint32_t ovf_cnt_lsch7: 1;
uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ uint32_t reserved20: 12;
uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/
uint32_t reserved24: 8;
}; };
uint32_t val; uint32_t val;
} int_st; } int_st;
union { union {
struct { struct {
uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ uint32_t lstimer0_ovf: 1;
uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ uint32_t lstimer1_ovf: 1;
uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ uint32_t lstimer2_ovf: 1;
uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ uint32_t lstimer3_ovf: 1;
uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch0: 1;
uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch1: 1;
uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch2: 1;
uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch3: 1;
uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ uint32_t duty_chng_end_lsch4: 1;
uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ uint32_t duty_chng_end_lsch5: 1;
uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ uint32_t duty_chng_end_lsch6: 1;
uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ uint32_t duty_chng_end_lsch7: 1;
uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ uint32_t ovf_cnt_lsch0: 1;
uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ uint32_t ovf_cnt_lsch1: 1;
uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ uint32_t ovf_cnt_lsch2: 1;
uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ uint32_t ovf_cnt_lsch3: 1;
uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ uint32_t ovf_cnt_lsch4: 1;
uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ uint32_t ovf_cnt_lsch5: 1;
uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ uint32_t ovf_cnt_lsch6: 1;
uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ uint32_t ovf_cnt_lsch7: 1;
uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ uint32_t reserved20: 12;
uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
}; };
uint32_t val; uint32_t val;
} int_ena; } int_ena;
union { union {
struct { struct {
uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ uint32_t lstimer0_ovf: 1;
uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ uint32_t lstimer1_ovf: 1;
uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ uint32_t lstimer2_ovf: 1;
uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ uint32_t lstimer3_ovf: 1;
uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch0: 1;
uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch1: 1;
uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch2: 1;
uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ uint32_t duty_chng_end_lsch3: 1;
uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ uint32_t duty_chng_end_lsch4: 1;
uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ uint32_t duty_chng_end_lsch5: 1;
uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ uint32_t duty_chng_end_lsch6: 1;
uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ uint32_t duty_chng_end_lsch7: 1;
uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ uint32_t ovf_cnt_lsch0: 1;
uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ uint32_t ovf_cnt_lsch1: 1;
uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ uint32_t ovf_cnt_lsch2: 1;
uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ uint32_t ovf_cnt_lsch3: 1;
uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ uint32_t ovf_cnt_lsch4: 1;
uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ uint32_t ovf_cnt_lsch5: 1;
uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ uint32_t ovf_cnt_lsch6: 1;
uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ uint32_t ovf_cnt_lsch7: 1;
uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ uint32_t reserved20: 12;
uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/
uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/
uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/
uint32_t reserved24: 8;
}; };
uint32_t val; uint32_t val;
} int_clr; } int_clr;
@ -229,100 +201,8 @@ typedef volatile struct {
uint32_t apb_clk_sel: 2; uint32_t apb_clk_sel: 2;
uint32_t reserved2: 30; uint32_t reserved2: 30;
}; };
struct {
uint32_t slow_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz, (only used by LEDC low speed channels/timers)*/
uint32_t reserved: 31;
};
uint32_t val; uint32_t val;
} conf; } conf;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_raw;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_st;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_ena;
union {
struct {
uint32_t ovf_cnt_hsch0: 1;
uint32_t ovf_cnt_hsch1: 1;
uint32_t ovf_cnt_hsch2: 1;
uint32_t ovf_cnt_hsch3: 1;
uint32_t ovf_cnt_hsch4: 1;
uint32_t ovf_cnt_hsch5: 1;
uint32_t ovf_cnt_hsch6: 1;
uint32_t ovf_cnt_hsch7: 1;
uint32_t ovf_cnt_lsch0: 1;
uint32_t ovf_cnt_lsch1: 1;
uint32_t ovf_cnt_lsch2: 1;
uint32_t ovf_cnt_lsch3: 1;
uint32_t ovf_cnt_lsch4: 1;
uint32_t ovf_cnt_lsch5: 1;
uint32_t ovf_cnt_lsch6: 1;
uint32_t ovf_cnt_lsch7: 1;
uint32_t reserved16: 16;
};
uint32_t val;
} int1_clr;
uint32_t reserved_1a4; uint32_t reserved_1a4;
uint32_t reserved_1a8; uint32_t reserved_1a8;
uint32_t reserved_1ac; uint32_t reserved_1ac;

1104
components/soc/esp32s2beta/include/soc/pcnt_reg.h
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File diff suppressed because it is too large Load Diff

42
components/soc/esp32s2beta/include/soc/pcnt_struct.h
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@ -1,4 +1,4 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@ -53,25 +53,21 @@ typedef volatile struct {
}; };
uint32_t val; uint32_t val;
} conf2; } conf2;
} conf_unit[8]; } conf_unit[4];
union { union {
struct { struct {
uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/
uint32_t reserved16: 16; uint32_t reserved16: 16;
}; };
uint32_t val; uint32_t val;
} cnt_unit[8]; } cnt_unit[4];
union { union {
struct { struct {
uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/ uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/ uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/ uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/ uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/ uint32_t reserved4: 28;
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/
uint32_t reserved8: 24;
}; };
uint32_t val; uint32_t val;
} int_raw; } int_raw;
@ -81,11 +77,7 @@ typedef volatile struct {
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/ uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/ uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/ uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/ uint32_t reserved4: 28;
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/
uint32_t reserved8: 24;
}; };
uint32_t val; uint32_t val;
} int_st; } int_st;
@ -95,11 +87,7 @@ typedef volatile struct {
uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/ uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/
uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/ uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/
uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/ uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/
uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/ uint32_t reserved4: 28;
uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/
uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/
uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/
uint32_t reserved8: 24;
}; };
uint32_t val; uint32_t val;
} int_ena; } int_ena;
@ -109,11 +97,7 @@ typedef volatile struct {
uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/ uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/
uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/ uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/
uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/ uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/
uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/ uint32_t reserved4: 28;
uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/
uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/
uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/
uint32_t reserved8: 24;
}; };
uint32_t val; uint32_t val;
} int_clr; } int_clr;
@ -128,7 +112,7 @@ typedef volatile struct {
uint32_t reserved7:25; uint32_t reserved7:25;
}; };
uint32_t val; uint32_t val;
} status_unit[8]; } status_unit[4];
union { union {
struct { struct {
uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/
@ -139,16 +123,8 @@ typedef volatile struct {
uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/
uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/
uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/
uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/
uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/
uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/
uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/
uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/
uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/
uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/
uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/
uint32_t clk_en: 1; uint32_t clk_en: 1;
uint32_t reserved17: 15; uint32_t reserved9: 13;
}; };
uint32_t val; uint32_t val;
} ctrl; } ctrl;

2
components/soc/esp32s2beta/include/soc/timer_group_reg.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.

2
components/soc/esp32s2beta/include/soc/timer_group_struct.h
View File

@ -1,4 +1,4 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.

25
components/soc/esp32s2beta/ledc_periph.c Normal file
View File

@ -0,0 +1,25 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/ledc_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every LEDC peripheral: GPIO signals
*/
const ledc_signal_conn_t ledc_periph_signal[1] = {
{
.sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
}
};

3
components/soc/esp32s2beta/sources.cmake
View File

@ -7,7 +7,8 @@ set(SOC_SRCS "cpu_util.c"
"rtc_sleep.c" "rtc_sleep.c"
"rtc_time.c" "rtc_time.c"
"soc_memory_layout.c" "soc_memory_layout.c"
"spi_periph.c") "spi_periph.c"
"ledc_periph.c")
if(NOT CMAKE_BUILD_EARLY_EXPANSION) if(NOT CMAKE_BUILD_EARLY_EXPANSION)
set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES

13
components/soc/include/soc/ledc_periph.h
View File

@ -15,3 +15,16 @@
#pragma once #pragma once
#include "soc/ledc_reg.h" #include "soc/ledc_reg.h"
#include "soc/ledc_struct.h" #include "soc/ledc_struct.h"
/*
Stores a bunch of per-ledc-peripheral data.
*/
typedef struct {
const uint8_t sig_out0_idx;
} ledc_signal_conn_t;
#if CONFIG_IDF_TARGET_ESP32S2BETA
extern const ledc_signal_conn_t ledc_periph_signal[1];
#elif defined CONFIG_IDF_TARGET_ESP32
extern const ledc_signal_conn_t ledc_periph_signal[2];
#endif

61
examples/mesh/internal_communication/main/mesh_light.c
View File

@ -41,7 +41,7 @@ esp_err_t mesh_light_init(void)
ledc_timer_config_t ledc_timer = { ledc_timer_config_t ledc_timer = {
.bit_num = LEDC_TIMER_13_BIT, .bit_num = LEDC_TIMER_13_BIT,
.freq_hz = 5000, .freq_hz = 5000,
.speed_mode = LEDC_HIGH_SPEED_MODE, .speed_mode = LEDC_LOW_SPEED_MODE,
.timer_num = LEDC_TIMER_0 .timer_num = LEDC_TIMER_0
}; };
ledc_timer_config(&ledc_timer); ledc_timer_config(&ledc_timer);
@ -51,8 +51,9 @@ esp_err_t mesh_light_init(void)
.duty = 100, .duty = 100,
.gpio_num = LEDC_IO_0, .gpio_num = LEDC_IO_0,
.intr_type = LEDC_INTR_FADE_END, .intr_type = LEDC_INTR_FADE_END,
.speed_mode = LEDC_HIGH_SPEED_MODE, .speed_mode = LEDC_LOW_SPEED_MODE,
.timer_sel = LEDC_TIMER_0 .timer_sel = LEDC_TIMER_0,
.hpoint = 0,
}; };
ledc_channel_config(&ledc_channel); ledc_channel_config(&ledc_channel);
ledc_channel.channel = LEDC_CHANNEL_1; ledc_channel.channel = LEDC_CHANNEL_1;
@ -75,56 +76,56 @@ esp_err_t mesh_light_set(int color)
switch (color) { switch (color) {
case MESH_LIGHT_RED: case MESH_LIGHT_RED:
/* Red */ /* Red */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
break; break;
case MESH_LIGHT_GREEN: case MESH_LIGHT_GREEN:
/* Green */ /* Green */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
break; break;
case MESH_LIGHT_BLUE: case MESH_LIGHT_BLUE:
/* Blue */ /* Blue */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
case MESH_LIGHT_YELLOW: case MESH_LIGHT_YELLOW:
/* Yellow */ /* Yellow */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
break; break;
case MESH_LIGHT_PINK: case MESH_LIGHT_PINK:
/* Pink */ /* Pink */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
case MESH_LIGHT_INIT: case MESH_LIGHT_INIT:
/* can't say */ /* can't say */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
case MESH_LIGHT_WARNING: case MESH_LIGHT_WARNING:
/* warning */ /* warning */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
default: default:
/* off */ /* off */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
} }
ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0); ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0);
ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1); ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1);
ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2); ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2);
return ESP_OK; return ESP_OK;
} }

61
examples/mesh/manual_networking/main/mesh_light.c
View File

@ -41,7 +41,7 @@ esp_err_t mesh_light_init(void)
ledc_timer_config_t ledc_timer = { ledc_timer_config_t ledc_timer = {
.bit_num = LEDC_TIMER_13_BIT, .bit_num = LEDC_TIMER_13_BIT,
.freq_hz = 5000, .freq_hz = 5000,
.speed_mode = LEDC_HIGH_SPEED_MODE, .speed_mode = LEDC_LOW_SPEED_MODE,
.timer_num = LEDC_TIMER_0 .timer_num = LEDC_TIMER_0
}; };
ledc_timer_config(&ledc_timer); ledc_timer_config(&ledc_timer);
@ -51,8 +51,9 @@ esp_err_t mesh_light_init(void)
.duty = 100, .duty = 100,
.gpio_num = LEDC_IO_0, .gpio_num = LEDC_IO_0,
.intr_type = LEDC_INTR_FADE_END, .intr_type = LEDC_INTR_FADE_END,
.speed_mode = LEDC_HIGH_SPEED_MODE, .speed_mode = LEDC_LOW_SPEED_MODE,
.timer_sel = LEDC_TIMER_0 .timer_sel = LEDC_TIMER_0,
.hpoint = 0,
}; };
ledc_channel_config(&ledc_channel); ledc_channel_config(&ledc_channel);
ledc_channel.channel = LEDC_CHANNEL_1; ledc_channel.channel = LEDC_CHANNEL_1;
@ -75,56 +76,56 @@ esp_err_t mesh_light_set(int color)
switch (color) { switch (color) {
case MESH_LIGHT_RED: case MESH_LIGHT_RED:
/* Red */ /* Red */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
break; break;
case MESH_LIGHT_GREEN: case MESH_LIGHT_GREEN:
/* Green */ /* Green */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
break; break;
case MESH_LIGHT_BLUE: case MESH_LIGHT_BLUE:
/* Blue */ /* Blue */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
case MESH_LIGHT_YELLOW: case MESH_LIGHT_YELLOW:
/* Yellow */ /* Yellow */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
break; break;
case MESH_LIGHT_PINK: case MESH_LIGHT_PINK:
/* Pink */ /* Pink */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
case MESH_LIGHT_INIT: case MESH_LIGHT_INIT:
/* can't say */ /* can't say */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
case MESH_LIGHT_WARNING: case MESH_LIGHT_WARNING:
/* warning */ /* warning */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000);
break; break;
default: default:
/* off */ /* off */
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0);
ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0);
} }
ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0); ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0);
ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1); ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1);
ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2); ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2);
return ESP_OK; return ESP_OK;
} }

40
examples/peripherals/ledc/main/ledc_example_main.c
View File

@ -33,15 +33,22 @@
* GPIO4/5 are from low speed channel group. * GPIO4/5 are from low speed channel group.
* *
*/ */
#ifdef CONFIG_IDF_TARGET_ESP32
#define LEDC_HS_TIMER LEDC_TIMER_0 #define LEDC_HS_TIMER LEDC_TIMER_0
#define LEDC_HS_MODE LEDC_HIGH_SPEED_MODE #define LEDC_HS_MODE LEDC_HIGH_SPEED_MODE
#define LEDC_HS_CH0_GPIO (18) #define LEDC_HS_CH0_GPIO (18)
#define LEDC_HS_CH0_CHANNEL LEDC_CHANNEL_0 #define LEDC_HS_CH0_CHANNEL LEDC_CHANNEL_0
#define LEDC_HS_CH1_GPIO (19) #define LEDC_HS_CH1_GPIO (19)
#define LEDC_HS_CH1_CHANNEL LEDC_CHANNEL_1 #define LEDC_HS_CH1_CHANNEL LEDC_CHANNEL_1
#endif
#define LEDC_LS_TIMER LEDC_TIMER_1 #define LEDC_LS_TIMER LEDC_TIMER_1
#define LEDC_LS_MODE LEDC_LOW_SPEED_MODE #define LEDC_LS_MODE LEDC_LOW_SPEED_MODE
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
#define LEDC_LS_CH0_GPIO (18)
#define LEDC_LS_CH0_CHANNEL LEDC_CHANNEL_0
#define LEDC_LS_CH1_GPIO (19)
#define LEDC_LS_CH1_CHANNEL LEDC_CHANNEL_1
#endif
#define LEDC_LS_CH2_GPIO (4) #define LEDC_LS_CH2_GPIO (4)
#define LEDC_LS_CH2_CHANNEL LEDC_CHANNEL_2 #define LEDC_LS_CH2_CHANNEL LEDC_CHANNEL_2
#define LEDC_LS_CH3_GPIO (5) #define LEDC_LS_CH3_GPIO (5)
@ -62,17 +69,17 @@ void app_main()
ledc_timer_config_t ledc_timer = { ledc_timer_config_t ledc_timer = {
.duty_resolution = LEDC_TIMER_13_BIT, // resolution of PWM duty .duty_resolution = LEDC_TIMER_13_BIT, // resolution of PWM duty
.freq_hz = 5000, // frequency of PWM signal .freq_hz = 5000, // frequency of PWM signal
.speed_mode = LEDC_HS_MODE, // timer mode .speed_mode = LEDC_LS_MODE, // timer mode
.timer_num = LEDC_HS_TIMER // timer index .timer_num = LEDC_LS_TIMER // timer index
}; };
// Set configuration of timer0 for high speed channels // Set configuration of timer0 for high speed channels
ledc_timer_config(&ledc_timer); ledc_timer_config(&ledc_timer);
#ifdef CONFIG_IDF_TARGET_ESP32
// Prepare and set configuration of timer1 for low speed channels // Prepare and set configuration of timer1 for low speed channels
ledc_timer.speed_mode = LEDC_LS_MODE; ledc_timer.speed_mode = LEDC_HS_MODE;
ledc_timer.timer_num = LEDC_LS_TIMER; ledc_timer.timer_num = LEDC_HS_TIMER;
ledc_timer_config(&ledc_timer); ledc_timer_config(&ledc_timer);
#endif
/* /*
* Prepare individual configuration * Prepare individual configuration
* for each channel of LED Controller * for each channel of LED Controller
@ -87,6 +94,7 @@ void app_main()
* will be the same * will be the same
*/ */
ledc_channel_config_t ledc_channel[LEDC_TEST_CH_NUM] = { ledc_channel_config_t ledc_channel[LEDC_TEST_CH_NUM] = {
#ifdef CONFIG_IDF_TARGET_ESP32
{ {
.channel = LEDC_HS_CH0_CHANNEL, .channel = LEDC_HS_CH0_CHANNEL,
.duty = 0, .duty = 0,
@ -103,6 +111,24 @@ void app_main()
.hpoint = 0, .hpoint = 0,
.timer_sel = LEDC_HS_TIMER .timer_sel = LEDC_HS_TIMER
}, },
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
{
.channel = LEDC_LS_CH0_CHANNEL,
.duty = 0,
.gpio_num = LEDC_LS_CH0_GPIO,
.speed_mode = LEDC_LS_MODE,
.hpoint = 0,
.timer_sel = LEDC_LS_TIMER
},
{
.channel = LEDC_LS_CH1_CHANNEL,
.duty = 0,
.gpio_num = LEDC_LS_CH1_GPIO,
.speed_mode = LEDC_LS_MODE,
.hpoint = 0,
.timer_sel = LEDC_LS_TIMER
},
#endif
{ {
.channel = LEDC_LS_CH2_CHANNEL, .channel = LEDC_LS_CH2_CHANNEL,
.duty = 0, .duty = 0,

14
examples/peripherals/pcnt/main/pcnt_example_main.c
View File

@ -96,7 +96,7 @@ static void ledc_init(void)
{ {
// Prepare and then apply the LEDC PWM timer configuration // Prepare and then apply the LEDC PWM timer configuration
ledc_timer_config_t ledc_timer; ledc_timer_config_t ledc_timer;
ledc_timer.speed_mode = LEDC_HIGH_SPEED_MODE; ledc_timer.speed_mode = LEDC_LOW_SPEED_MODE;
ledc_timer.timer_num = LEDC_TIMER_1; ledc_timer.timer_num = LEDC_TIMER_1;
ledc_timer.duty_resolution = LEDC_TIMER_10_BIT; ledc_timer.duty_resolution = LEDC_TIMER_10_BIT;
ledc_timer.freq_hz = 1; // set output frequency at 1 Hz ledc_timer.freq_hz = 1; // set output frequency at 1 Hz
@ -104,7 +104,7 @@ static void ledc_init(void)
// Prepare and then apply the LEDC PWM channel configuration // Prepare and then apply the LEDC PWM channel configuration
ledc_channel_config_t ledc_channel; ledc_channel_config_t ledc_channel;
ledc_channel.speed_mode = LEDC_HIGH_SPEED_MODE; ledc_channel.speed_mode = LEDC_LOW_SPEED_MODE;
ledc_channel.channel = LEDC_CHANNEL_1; ledc_channel.channel = LEDC_CHANNEL_1;
ledc_channel.timer_sel = LEDC_TIMER_1; ledc_channel.timer_sel = LEDC_TIMER_1;
ledc_channel.intr_type = LEDC_INTR_DISABLE; ledc_channel.intr_type = LEDC_INTR_DISABLE;
@ -187,19 +187,19 @@ void app_main()
if (res == pdTRUE) { if (res == pdTRUE) {
pcnt_get_counter_value(PCNT_TEST_UNIT, &count); pcnt_get_counter_value(PCNT_TEST_UNIT, &count);
printf("Event PCNT unit[%d]; cnt: %d\n", evt.unit, count); printf("Event PCNT unit[%d]; cnt: %d\n", evt.unit, count);
if (evt.status & PCNT_STATUS_THRES1_M) { if (evt.status & PCNT_EVT_THRES_1) {
printf("THRES1 EVT\n"); printf("THRES1 EVT\n");
} }
if (evt.status & PCNT_STATUS_THRES0_M) { if (evt.status & PCNT_EVT_THRES_0) {
printf("THRES0 EVT\n"); printf("THRES0 EVT\n");
} }
if (evt.status & PCNT_STATUS_L_LIM_M) { if (evt.status & PCNT_EVT_L_LIM) {
printf("L_LIM EVT\n"); printf("L_LIM EVT\n");
} }
if (evt.status & PCNT_STATUS_H_LIM_M) { if (evt.status & PCNT_EVT_H_LIM) {
printf("H_LIM EVT\n"); printf("H_LIM EVT\n");
} }
if (evt.status & PCNT_STATUS_ZERO_M) { if (evt.status & PCNT_EVT_ZERO) {
printf("ZERO EVT\n"); printf("ZERO EVT\n");
} }
} else { } else {

17
examples/peripherals/timer_group/main/timer_group_example_main.c
View File

@ -6,7 +6,6 @@
software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied. CONDITIONS OF ANY KIND, either express or implied.
*/ */
#include <stdio.h> #include <stdio.h>
#include "esp_types.h" #include "esp_types.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
@ -60,8 +59,13 @@ void IRAM_ATTR timer_group0_isr(void *para)
/* Retrieve the interrupt status and the counter value /* Retrieve the interrupt status and the counter value
from the timer that reported the interrupt */ from the timer that reported the interrupt */
#ifdef CONFIG_IDF_TARGET_ESP32
uint32_t intr_status = TIMERG0.int_st_timers.val; uint32_t intr_status = TIMERG0.int_st_timers.val;
TIMERG0.hw_timer[timer_idx].update = 1; TIMERG0.hw_timer[timer_idx].update = 1;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
uint32_t intr_status = TIMERG0.int_st.val;
TIMERG0.hw_timer[timer_idx].update.update = 1;
#endif
uint64_t timer_counter_value = uint64_t timer_counter_value =
((uint64_t) TIMERG0.hw_timer[timer_idx].cnt_high) << 32 ((uint64_t) TIMERG0.hw_timer[timer_idx].cnt_high) << 32
| TIMERG0.hw_timer[timer_idx].cnt_low; | TIMERG0.hw_timer[timer_idx].cnt_low;
@ -77,13 +81,21 @@ void IRAM_ATTR timer_group0_isr(void *para)
and update the alarm time for the timer with without reload */ and update the alarm time for the timer with without reload */
if ((intr_status & BIT(timer_idx)) && timer_idx == TIMER_0) { if ((intr_status & BIT(timer_idx)) && timer_idx == TIMER_0) {
evt.type = TEST_WITHOUT_RELOAD; evt.type = TEST_WITHOUT_RELOAD;
#ifdef CONFIG_IDF_TARGET_ESP32
TIMERG0.int_clr_timers.t0 = 1; TIMERG0.int_clr_timers.t0 = 1;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
TIMERG0.int_clr.t0 = 1;
#endif
timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE); timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE);
TIMERG0.hw_timer[timer_idx].alarm_high = (uint32_t) (timer_counter_value >> 32); TIMERG0.hw_timer[timer_idx].alarm_high = (uint32_t) (timer_counter_value >> 32);
TIMERG0.hw_timer[timer_idx].alarm_low = (uint32_t) timer_counter_value; TIMERG0.hw_timer[timer_idx].alarm_low = (uint32_t) timer_counter_value;
} else if ((intr_status & BIT(timer_idx)) && timer_idx == TIMER_1) { } else if ((intr_status & BIT(timer_idx)) && timer_idx == TIMER_1) {
evt.type = TEST_WITH_RELOAD; evt.type = TEST_WITH_RELOAD;
#ifdef CONFIG_IDF_TARGET_ESP32
TIMERG0.int_clr_timers.t1 = 1; TIMERG0.int_clr_timers.t1 = 1;
#elif defined CONFIG_IDF_TARGET_ESP32S2BETA
TIMERG0.int_clr.t1 = 1;
#endif
} else { } else {
evt.type = -1; // not supported even type evt.type = -1; // not supported even type
} }
@ -114,6 +126,9 @@ static void example_tg0_timer_init(int timer_idx,
config.alarm_en = TIMER_ALARM_EN; config.alarm_en = TIMER_ALARM_EN;
config.intr_type = TIMER_INTR_LEVEL; config.intr_type = TIMER_INTR_LEVEL;
config.auto_reload = auto_reload; config.auto_reload = auto_reload;
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
config.clk_sel = TIMER_SRC_CLK_APB;
#endif
timer_init(TIMER_GROUP_0, timer_idx, &config); timer_init(TIMER_GROUP_0, timer_idx, &config);
/* Timer's counter will initially start from value below. /* Timer's counter will initially start from value below.