From f98e7bbccf382aa1ed75d22e6daa5b668f59b7bc Mon Sep 17 00:00:00 2001 From: kooho <2229179028@qq.com> Date: Thu, 6 Jun 2019 14:20:39 +0800 Subject: [PATCH] Update LEDC, PCNT,Timer_Group driver for esp32s2beta. --- components/driver/include/driver/ledc.h | 4 + components/driver/include/driver/pcnt.h | 13 +- components/driver/include/driver/timer.h | 13 + components/driver/ledc.c | 208 +- components/driver/pcnt.c | 8 +- components/driver/timer.c | 24 +- components/soc/esp32/ledc_periph.c | 28 + components/soc/esp32/sources.cmake | 3 +- .../soc/esp32s2beta/include/soc/ledc_reg.h | 3184 +++++------------ .../soc/esp32s2beta/include/soc/ledc_struct.h | 306 +- .../soc/esp32s2beta/include/soc/pcnt_reg.h | 1104 +----- .../soc/esp32s2beta/include/soc/pcnt_struct.h | 42 +- .../esp32s2beta/include/soc/timer_group_reg.h | 2 +- .../include/soc/timer_group_struct.h | 2 +- components/soc/esp32s2beta/ledc_periph.c | 25 + components/soc/esp32s2beta/sources.cmake | 3 +- components/soc/include/soc/ledc_periph.h | 13 + .../internal_communication/main/mesh_light.c | 61 +- .../mesh/manual_networking/main/mesh_light.c | 61 +- .../peripherals/ledc/main/ledc_example_main.c | 40 +- .../peripherals/pcnt/main/pcnt_example_main.c | 14 +- .../main/timer_group_example_main.c | 17 +- 22 files changed, 1442 insertions(+), 3733 deletions(-) create mode 100644 components/soc/esp32/ledc_periph.c create mode 100644 components/soc/esp32s2beta/ledc_periph.c diff --git a/components/driver/include/driver/ledc.h b/components/driver/include/driver/ledc.h index 6a82c19a2f..bd54c23de4 100644 --- a/components/driver/include/driver/ledc.h +++ b/components/driver/include/driver/ledc.h @@ -30,7 +30,9 @@ extern "C" { #define LEDC_ERR_VAL (-1) typedef enum { +#ifdef CONFIG_IDF_TARGET_ESP32 LEDC_HIGH_SPEED_MODE = 0, /*!< LEDC high speed speed_mode */ +#endif LEDC_LOW_SPEED_MODE, /*!< LEDC low speed speed_mode */ LEDC_SPEED_MODE_MAX, /*!< LEDC speed limit */ } ledc_mode_t; @@ -86,12 +88,14 @@ typedef enum { LEDC_TIMER_12_BIT, /*!< LEDC PWM duty resolution of 12 bits */ LEDC_TIMER_13_BIT, /*!< LEDC PWM duty resolution of 13 bits */ LEDC_TIMER_14_BIT, /*!< LEDC PWM duty resolution of 14 bits */ +#ifdef CONFIG_IDF_TARGET_ESP32 LEDC_TIMER_15_BIT, /*!< LEDC PWM duty resolution of 15 bits */ LEDC_TIMER_16_BIT, /*!< LEDC PWM duty resolution of 16 bits */ LEDC_TIMER_17_BIT, /*!< LEDC PWM duty resolution of 17 bits */ LEDC_TIMER_18_BIT, /*!< LEDC PWM duty resolution of 18 bits */ LEDC_TIMER_19_BIT, /*!< LEDC PWM duty resolution of 19 bits */ LEDC_TIMER_20_BIT, /*!< LEDC PWM duty resolution of 20 bits */ +#endif LEDC_TIMER_BIT_MAX, } ledc_timer_bit_t; diff --git a/components/driver/include/driver/pcnt.h b/components/driver/include/driver/pcnt.h index 76202cf902..f984dc68d3 100644 --- a/components/driver/include/driver/pcnt.h +++ b/components/driver/include/driver/pcnt.h @@ -47,10 +47,13 @@ typedef enum { PCNT_UNIT_1 = 1, /*!< PCNT unit 1 */ PCNT_UNIT_2 = 2, /*!< PCNT unit 2 */ PCNT_UNIT_3 = 3, /*!< PCNT unit 3 */ +//ESP32-S2 only have 4 unit +#ifdef CONFIG_IDF_TARGET_ESP32 PCNT_UNIT_4 = 4, /*!< PCNT unit 4 */ PCNT_UNIT_5 = 5, /*!< PCNT unit 5 */ PCNT_UNIT_6 = 6, /*!< PCNT unit 6 */ PCNT_UNIT_7 = 7, /*!< PCNT unit 7 */ +#endif PCNT_UNIT_MAX, } pcnt_unit_t; @@ -67,11 +70,11 @@ typedef enum { * @brief Selection of counter's events the may trigger an interrupt */ typedef enum { - PCNT_EVT_L_LIM = 0, /*!< PCNT watch point event: Minimum counter value */ - PCNT_EVT_H_LIM = 1, /*!< PCNT watch point event: Maximum counter value */ - PCNT_EVT_THRES_0 = 2, /*!< PCNT watch point event: threshold0 value event */ - PCNT_EVT_THRES_1 = 3, /*!< PCNT watch point event: threshold1 value event */ - PCNT_EVT_ZERO = 4, /*!< PCNT watch point event: counter value zero event */ + PCNT_EVT_THRES_1 = BIT(2), /*!< PCNT watch point event: threshold1 value event */ + PCNT_EVT_THRES_0 = BIT(3), /*!< PCNT watch point event: threshold0 value event */ + PCNT_EVT_L_LIM = BIT(4), /*!< PCNT watch point event: Minimum counter value */ + PCNT_EVT_H_LIM = BIT(5), /*!< PCNT watch point event: Maximum counter value */ + PCNT_EVT_ZERO = BIT(6), /*!< PCNT watch point event: counter value zero event */ PCNT_EVT_MAX } pcnt_evt_type_t; diff --git a/components/driver/include/driver/timer.h b/components/driver/include/driver/timer.h index cbf2a5bd23..b694bc8393 100644 --- a/components/driver/include/driver/timer.h +++ b/components/driver/include/driver/timer.h @@ -89,6 +89,16 @@ typedef enum { TIMER_AUTORELOAD_MAX, } timer_autoreload_t; +#ifdef CONFIG_IDF_TARGET_ESP32S2BETA +/** + * @brief Select timer source clock. + */ +typedef enum { + TIMER_SRC_CLK_APB = 0, /*!< Select APB as the source clock*/ + TIMER_SRC_CLK_XTAL = 1, /*!< Select XTAL as the source clock*/ +} timer_src_clk_t; +#endif + /** * @brief Data structure with timer's configuration settings */ @@ -99,6 +109,9 @@ typedef struct { timer_count_dir_t counter_dir; /*!< Counter direction */ bool auto_reload; /*!< Timer auto-reload */ uint32_t divider; /*!< Counter clock divider. The divider's range is from from 2 to 65536. */ +#ifdef CONFIG_IDF_TARGET_ESP32S2BETA + timer_src_clk_t clk_sel; /*!< Use XTAL as source clock. */ +#endif } timer_config_t; diff --git a/components/driver/ledc.c b/components/driver/ledc.c index 17354bbffd..31545ded25 100644 --- a/components/driver/ledc.c +++ b/components/driver/ledc.c @@ -1,4 +1,4 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,8 +11,8 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#include #include +#include #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/xtensa_api.h" @@ -51,7 +51,11 @@ static ledc_isr_handle_t s_ledc_fade_isr_handle = NULL; #define LEDC_VAL_NO_CHANGE (-1) #define LEDC_STEP_NUM_MAX (1023) #define LEDC_DUTY_DECIMAL_BIT_NUM (4) -#define LEDC_HPOINT_VAL_MAX (LEDC_HPOINT_HSCH1_V) +#define LEDC_TIMER_DIV_NUM_MAX (0x3FFFF) +#define LEDC_DUTY_NUM_MAX (LEDC_DUTY_NUM_LSCH0_V) +#define LEDC_DUTY_CYCLE_MAX (LEDC_DUTY_CYCLE_LSCH0_V) +#define LEDC_DUTY_SCALE_MAX (LEDC_DUTY_SCALE_LSCH0_V) +#define LEDC_HPOINT_VAL_MAX (LEDC_HPOINT_LSCH1_V) #define LEDC_FADE_TOO_SLOW_STR "LEDC FADE TOO SLOW" #define LEDC_FADE_TOO_FAST_STR "LEDC FADE TOO FAST" static const char *LEDC_FADE_SERVICE_ERR_STR = "LEDC fade service not installed"; @@ -78,7 +82,11 @@ static esp_err_t ledc_enable_intr_type(ledc_mode_t speed_mode, uint32_t channel, uint32_t intr_type = type; portENTER_CRITICAL(&ledc_spinlock); value = LEDC.int_ena.val; +#ifdef CONFIG_IDF_TARGET_ESP32 uint8_t int_en_base = LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S; +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + uint8_t int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; +#endif if (speed_mode == LEDC_LOW_SPEED_MODE) { int_en_base = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; } @@ -139,7 +147,18 @@ esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_ LEDC_ARG_CHECK(timer_sel < LEDC_TIMER_MAX, "timer_select"); portENTER_CRITICAL(&ledc_spinlock); LEDC.timer_group[speed_mode].timer[timer_sel].conf.clock_divider = clock_divider; - LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = clk_src; +#ifdef CONFIG_IDF_TARGET_ESP32 + LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = clk_src; +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + if(clk_src == LEDC_REF_TICK) { + //REF_TICK can only be used when APB is selected. + LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 1; + LEDC.conf.apb_clk_sel = 1; + } else { + LEDC.timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 0; + LEDC.conf.apb_clk_sel = clk_src; + } +#endif LEDC.timer_group[speed_mode].timer[timer_sel].conf.duty_resolution = duty_resolution; ledc_ls_timer_update(speed_mode, timer_sel); portEXIT_CRITICAL(&ledc_spinlock); @@ -151,15 +170,18 @@ static IRAM_ATTR esp_err_t ledc_duty_config(ledc_mode_t speed_mode, ledc_channel { portENTER_CRITICAL(&ledc_spinlock); if (hpoint_val >= 0) { - LEDC.channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val & LEDC_HPOINT_HSCH1_V; + LEDC.channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val; } if (duty_val >= 0) { LEDC.channel_group[speed_mode].channel[channel_num].duty.duty = duty_val; } - LEDC.channel_group[speed_mode].channel[channel_num].conf1.val = ((duty_direction & LEDC_DUTY_INC_HSCH0_V) << LEDC_DUTY_INC_HSCH0_S) | - ((duty_num & LEDC_DUTY_NUM_HSCH0_V) << LEDC_DUTY_NUM_HSCH0_S) | - ((duty_cycle & LEDC_DUTY_CYCLE_HSCH0_V) << LEDC_DUTY_CYCLE_HSCH0_S) | - ((duty_scale & LEDC_DUTY_SCALE_HSCH0_V) << LEDC_DUTY_SCALE_HSCH0_S); + typeof(LEDC.channel_group[0].channel[0].conf1) channel_cfg; + channel_cfg.val = 0; + channel_cfg.duty_inc = duty_direction; + channel_cfg.duty_num = duty_num; + channel_cfg.duty_cycle = duty_cycle; + channel_cfg.duty_scale = duty_scale; + LEDC.channel_group[speed_mode].channel[channel_num].conf1.val = channel_cfg.val; ledc_ls_channel_update(speed_mode, channel_num); portEXIT_CRITICAL(&ledc_spinlock); return ESP_OK; @@ -248,20 +270,22 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t* timer_conf) (uint32_t ) div_param); ret = ESP_FAIL; } - if (div_param > LEDC_DIV_NUM_HSTIMER0_V) { + if (div_param > LEDC_TIMER_DIV_NUM_MAX) { // APB_CLK results in divisor which too high. Try using REF_TICK as clock source. timer_clk_src = LEDC_REF_TICK; div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; - if (div_param < 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { + if (div_param < 256 || div_param > LEDC_TIMER_DIV_NUM_MAX) { ESP_LOGE(LEDC_TAG, "requested frequency and duty resolution can not be achieved, try increasing freq_hz or duty_resolution. div_param=%d", (uint32_t ) div_param); ret = ESP_FAIL; } } else { - if (speed_mode == LEDC_LOW_SPEED_MODE) { +#ifdef CONFIG_IDF_TARGET_ESP32 + if (speed_mode == LEDC_LOW_SPEED_MODE) { //for now, we only select 80mhz for slow clk of LEDC low speed channels. LEDC.conf.slow_clk_sel = 1; } +#endif } // set timer parameters ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src); @@ -277,13 +301,7 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); - if (speed_mode == LEDC_HIGH_SPEED_MODE) { -#if CONFIG_IDF_TARGET_ESP32 - gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0); -#endif - } else { - gpio_matrix_out(gpio_num, LEDC_LS_SIG_OUT0_IDX + ledc_channel, 0, 0); - } + gpio_matrix_out(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0); return ESP_OK; } @@ -319,13 +337,8 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf) /*set LEDC signal in gpio matrix*/ PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); - if (speed_mode == LEDC_HIGH_SPEED_MODE) { -#if CONFIG_IDF_TARGET_ESP32 - gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0); -#endif - } else { - gpio_matrix_out(gpio_num, LEDC_LS_SIG_OUT0_IDX + ledc_channel, 0, 0); - } + gpio_matrix_out(gpio_num, ledc_periph_signal[speed_mode].sig_out0_idx + ledc_channel, 0, 0); + return ret; } @@ -360,9 +373,9 @@ esp_err_t ledc_set_fade(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel"); LEDC_ARG_CHECK(fade_direction < LEDC_DUTY_DIR_MAX, "fade_direction"); - LEDC_ARG_CHECK(step_num <= LEDC_DUTY_NUM_HSCH0_V, "step_num"); - LEDC_ARG_CHECK(duty_cyle_num <= LEDC_DUTY_CYCLE_HSCH0_V, "duty_cycle_num"); - LEDC_ARG_CHECK(duty_scale <= LEDC_DUTY_SCALE_HSCH0_V, "duty_scale"); + LEDC_ARG_CHECK(step_num <= LEDC_DUTY_NUM_MAX, "step_num"); + LEDC_ARG_CHECK(duty_cyle_num <= LEDC_DUTY_CYCLE_MAX, "duty_cycle_num"); + LEDC_ARG_CHECK(duty_scale <= LEDC_DUTY_SCALE_MAX, "duty_scale"); _ledc_fade_hw_acquire(speed_mode, channel); ledc_duty_config(speed_mode, channel, //uint32_t chan_num, @@ -445,7 +458,7 @@ esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t } else { clock_divider = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision; } - if (clock_divider <= 256 || clock_divider > LEDC_DIV_NUM_HSTIMER0) { + if (clock_divider <= 256 || clock_divider > LEDC_TIMER_DIV_NUM_MAX) { ESP_LOGE(LEDC_TAG, "div param err,div_param=%u", clock_divider); ret = ESP_FAIL; } @@ -473,66 +486,75 @@ uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num) return freq; } +static inline void ledc_calc_fade_end_channel(uint32_t *fade_end_status, int *channel, int *speed_mode) +{ + int i = __builtin_ffs((*fade_end_status)) - 1; + (*fade_end_status) &= ~(1 << i); + *speed_mode = LEDC_LOW_SPEED_MODE; + *channel = i; +#ifdef CONFIG_IDF_TARGET_ESP32 + if (i < LEDC_CHANNEL_MAX) { + *speed_mode = LEDC_HIGH_SPEED_MODE; + } else { + *channel = i - LEDC_CHANNEL_MAX; + } +#endif +} + void IRAM_ATTR ledc_fade_isr(void* arg) { - int channel; portBASE_TYPE HPTaskAwoken = pdFALSE; uint32_t intr_status = LEDC.int_st.val; //read LEDC interrupt status. - LEDC.int_clr.val = intr_status; //clear LEDC interrupt status. - int speed_mode = LEDC_HIGH_SPEED_MODE; - for (channel = 0; channel < LEDC_CHANNEL_MAX; channel++) { - if (intr_status & (BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S + channel) | BIT(LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S + channel))) { - if (intr_status & BIT(LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S + channel)) { - speed_mode = LEDC_HIGH_SPEED_MODE; - } else { - speed_mode = LEDC_LOW_SPEED_MODE; - } - if (s_ledc_fade_rec[speed_mode][channel] == NULL) { - //fade object not initialized yet. - continue; - } - uint32_t duty_cur = LEDC.channel_group[speed_mode].channel[channel].duty_rd.duty_read >> LEDC_DUTY_DECIMAL_BIT_NUM; - if (duty_cur == s_ledc_fade_rec[speed_mode][channel]->target_duty) { - xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken); - if (HPTaskAwoken == pdTRUE) { - portYIELD_FROM_ISR(); - } - continue; - } - uint32_t duty_tar = s_ledc_fade_rec[speed_mode][channel]->target_duty; - int scale = s_ledc_fade_rec[speed_mode][channel]->scale; - if (scale == 0) { - xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken); - continue; - } - int cycle = s_ledc_fade_rec[speed_mode][channel]->cycle_num; - int delta = s_ledc_fade_rec[speed_mode][channel]->direction == LEDC_DUTY_DIR_DECREASE ? duty_cur - duty_tar : duty_tar - duty_cur; - int step = delta / scale > LEDC_STEP_NUM_MAX ? LEDC_STEP_NUM_MAX : delta / scale; - if (delta > scale) { - ledc_duty_config( - speed_mode, - channel, - LEDC_VAL_NO_CHANGE, - duty_cur << LEDC_DUTY_DECIMAL_BIT_NUM, - s_ledc_fade_rec[speed_mode][channel]->direction, - step, - cycle, - scale); - } else { - ledc_duty_config( - speed_mode, - channel, - LEDC_VAL_NO_CHANGE, - duty_tar << LEDC_DUTY_DECIMAL_BIT_NUM, - s_ledc_fade_rec[speed_mode][channel]->direction, - 1, - 1, - 0); - } - LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 1; + uint32_t fade_end_status = (intr_status >> LEDC_LSTIMER0_OVF_INT_ST_S); + int speed_mode; + int channel; + while (fade_end_status) { + ledc_calc_fade_end_channel(&fade_end_status, &channel, &speed_mode); + if (s_ledc_fade_rec[speed_mode][channel] == NULL) { + //fade object not initialized yet. + continue; } + uint32_t duty_cur = LEDC.channel_group[speed_mode].channel[channel].duty_rd.duty_read >> LEDC_DUTY_DECIMAL_BIT_NUM; + if (duty_cur == s_ledc_fade_rec[speed_mode][channel]->target_duty) { + xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken); + continue; + } + uint32_t duty_tar = s_ledc_fade_rec[speed_mode][channel]->target_duty; + int scale = s_ledc_fade_rec[speed_mode][channel]->scale; + if (scale == 0) { + xSemaphoreGiveFromISR(s_ledc_fade_rec[speed_mode][channel]->ledc_fade_sem, &HPTaskAwoken); + continue; + } + int cycle = s_ledc_fade_rec[speed_mode][channel]->cycle_num; + int delta = s_ledc_fade_rec[speed_mode][channel]->direction == LEDC_DUTY_DIR_DECREASE ? duty_cur - duty_tar : duty_tar - duty_cur; + int step = delta / scale > LEDC_STEP_NUM_MAX ? LEDC_STEP_NUM_MAX : delta / scale; + if (delta > scale) { + ledc_duty_config( + speed_mode, + channel, + LEDC_VAL_NO_CHANGE, + duty_cur << LEDC_DUTY_DECIMAL_BIT_NUM, + s_ledc_fade_rec[speed_mode][channel]->direction, + step, + cycle, + scale); + } else { + ledc_duty_config( + speed_mode, + channel, + LEDC_VAL_NO_CHANGE, + duty_tar << LEDC_DUTY_DECIMAL_BIT_NUM, + s_ledc_fade_rec[speed_mode][channel]->direction, + 1, + 1, + 0); + } + LEDC.channel_group[speed_mode].channel[channel].conf1.duty_start = 1; } LEDC.int_clr.val = intr_status; //clear LEDC interrupt status. + if (HPTaskAwoken == pdTRUE) { + portYIELD_FROM_ISR(); + } } static esp_err_t ledc_fade_channel_deinit(ledc_mode_t speed_mode, ledc_channel_t channel) @@ -643,16 +665,16 @@ static esp_err_t _ledc_set_fade_with_time(ledc_mode_t speed_mode, ledc_channel_t if (total_cycles > duty_delta) { scale = 1; cycle_num = total_cycles / duty_delta; - if (cycle_num > LEDC_DUTY_NUM_HSCH0_V) { + if (cycle_num > LEDC_DUTY_NUM_MAX) { ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_SLOW_STR); - cycle_num = LEDC_DUTY_NUM_HSCH0_V; + cycle_num = LEDC_DUTY_NUM_MAX; } } else { cycle_num = 1; scale = duty_delta / total_cycles; - if (scale > LEDC_DUTY_SCALE_HSCH0_V) { + if (scale > LEDC_DUTY_SCALE_MAX) { ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_FAST_STR); - scale = LEDC_DUTY_SCALE_HSCH0_V; + scale = LEDC_DUTY_SCALE_MAX; } } return _ledc_set_fade_with_step(speed_mode, channel, target_duty, scale, cycle_num); @@ -662,7 +684,11 @@ static void _ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, led { s_ledc_fade_rec[speed_mode][channel]->mode = fade_mode; // Clear interrupt status of channel +#ifdef CONFIG_IDF_TARGET_ESP32 int duty_resolution_ch0 = (speed_mode == LEDC_HIGH_SPEED_MODE) ? LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S : LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + int duty_resolution_ch0 = LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S; +#endif LEDC.int_clr.val |= BIT(duty_resolution_ch0 + channel); // Enable interrupt for channel ledc_enable_intr_type(speed_mode, channel, LEDC_INTR_FADE_END); @@ -689,8 +715,8 @@ esp_err_t ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t channel { LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel"); - LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_HSCH0_V), "fade scale"); - LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_HSCH0_V), "cycle_num"); + LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_MAX), "fade scale"); + LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_MAX), "cycle_num"); LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty"); LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK , LEDC_FADE_INIT_ERROR_STR, ESP_FAIL); @@ -777,8 +803,8 @@ esp_err_t ledc_set_fade_step_and_start(ledc_mode_t speed_mode, ledc_channel_t ch LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel"); LEDC_ARG_CHECK(fade_mode < LEDC_FADE_MAX, "fade_mode"); LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK , LEDC_FADE_INIT_ERROR_STR, ESP_FAIL); - LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_HSCH0_V), "fade scale"); - LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_HSCH0_V), "cycle_num"); + LEDC_ARG_CHECK((scale > 0) && (scale <= LEDC_DUTY_SCALE_MAX), "fade scale"); + LEDC_ARG_CHECK((cycle_num > 0) && (cycle_num <= LEDC_DUTY_CYCLE_MAX), "cycle_num"); LEDC_ARG_CHECK(target_duty <= ledc_get_max_duty(speed_mode, channel), "target_duty"); _ledc_op_lock_acquire(speed_mode, channel); _ledc_fade_hw_acquire(speed_mode, channel); diff --git a/components/driver/pcnt.c b/components/driver/pcnt.c index 16bf9a9ae2..7b6bfc52eb 100644 --- a/components/driver/pcnt.c +++ b/components/driver/pcnt.c @@ -1,4 +1,4 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -53,7 +53,7 @@ esp_err_t pcnt_unit_config(const pcnt_config_t *pcnt_config) PCNT_CHECK(unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_CHECK(channel < PCNT_CHANNEL_MAX, PCNT_CHANNEL_ERR_STR, ESP_ERR_INVALID_ARG); - PCNT_CHECK(input_io < 0 || (GPIO_IS_VALID_GPIO(input_io) && (input_io != ctrl_io)), "PCNT pluse input io error", ESP_ERR_INVALID_ARG); + PCNT_CHECK(input_io < 0 || (GPIO_IS_VALID_GPIO(input_io) && (input_io != ctrl_io)), "PCNT pulse input io error", ESP_ERR_INVALID_ARG); PCNT_CHECK(ctrl_io < 0 || GPIO_IS_VALID_GPIO(ctrl_io), "PCNT ctrl io error", ESP_ERR_INVALID_ARG); PCNT_CHECK((pcnt_config->pos_mode < PCNT_COUNT_MAX) && (pcnt_config->neg_mode < PCNT_COUNT_MAX), PCNT_COUNT_MODE_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_CHECK((pcnt_config->hctrl_mode < PCNT_MODE_MAX) && (pcnt_config->lctrl_mode < PCNT_MODE_MAX), PCNT_CTRL_MODE_ERR_STR, ESP_ERR_INVALID_ARG); @@ -156,9 +156,9 @@ esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit) { PCNT_CHECK(pcnt_unit < PCNT_UNIT_MAX, PCNT_UNIT_ERR_STR, ESP_ERR_INVALID_ARG); PCNT_ENTER_CRITICAL(&pcnt_spinlock); -#if CONFIG_IDF_TARGET_ESP32 +#ifdef CONFIG_IDF_TARGET_ESP32 uint32_t reset_bit = BIT(PCNT_PLUS_CNT_RST_U0_S + (pcnt_unit * 2)); -#elif CONFIG_IDF_TARGET_ESP32S2BETA +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA uint32_t reset_bit = BIT(PCNT_PULSE_CNT_RST_U0_S + (pcnt_unit * 2)); #endif PCNT.ctrl.val |= reset_bit; diff --git a/components/driver/timer.c b/components/driver/timer.c index 69248252b7..f6f3b344ba 100644 --- a/components/driver/timer.c +++ b/components/driver/timer.c @@ -1,4 +1,4 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -19,6 +19,7 @@ #include "freertos/xtensa_api.h" #include "driver/timer.h" #include "driver/periph_ctrl.h" +#include "soc/rtc.h" #include "sdkconfig.h" static const char* TIMER_TAG = "timer_group"; @@ -48,9 +49,9 @@ esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG); TIMER_CHECK(timer_val != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG); portENTER_CRITICAL_SAFE(&timer_spinlock[group_num]); -#if CONFIG_IDF_TARGET_ESP32 +#ifdef CONFIG_IDF_TARGET_ESP32 TG[group_num]->hw_timer[timer_num].update = 1; -#elif CONFIG_IDF_TARGET_ESP32S2BETA +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA TG[group_num]->hw_timer[timer_num].update.update = 1; #endif *timer_val = ((uint64_t) TG[group_num]->hw_timer[timer_num].cnt_high << 32) @@ -69,7 +70,15 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_ esp_err_t err = timer_get_counter_value(group_num, timer_num, &timer_val); if (err == ESP_OK) { uint16_t div = TG[group_num]->hw_timer[timer_num].config.divider; +#ifdef CONFIG_IDF_TARGET_ESP32 *time = (double)timer_val * div / TIMER_BASE_CLK; +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + if(TG[group_num]->hw_timer[timer_num].config.use_xtal) { + *time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000); + } else { + *time = (double)timer_val * div / rtc_clk_apb_freq_get(); + } +#endif } return err; } @@ -227,9 +236,9 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer //but software reset does not clear interrupt status. This is not safe for application when enable the interrupt of timer_group. //we need to disable the interrupt and clear the interrupt status here. TG[group_num]->int_ena.val &= (~BIT(timer_num)); -#if CONFIG_IDF_TARGET_ESP32 +#ifdef CONFIG_IDF_TARGET_ESP32 TG[group_num]->int_clr_timers.val = BIT(timer_num); -#elif CONFIG_IDF_TARGET_ESP32S2BETA +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA TG[group_num]->int_clr.val = BIT(timer_num); #endif TG[group_num]->hw_timer[timer_num].config.autoreload = config->auto_reload; @@ -239,6 +248,9 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer TG[group_num]->hw_timer[timer_num].config.alarm_en = config->alarm_en; TG[group_num]->hw_timer[timer_num].config.level_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 1 : 0); TG[group_num]->hw_timer[timer_num].config.edge_int_en = (config->intr_type == TIMER_INTR_LEVEL ? 0 : 1); +#ifdef CONFIG_IDF_TARGET_ESP32S2BETA + TG[group_num]->hw_timer[timer_num].config.use_xtal = config->clk_sel; +#endif TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]); return ESP_OK; } @@ -293,5 +305,3 @@ esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num) TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG); return timer_group_intr_disable(group_num, BIT(timer_num)); } - - diff --git a/components/soc/esp32/ledc_periph.c b/components/soc/esp32/ledc_periph.c new file mode 100644 index 0000000000..6380fbad1c --- /dev/null +++ b/components/soc/esp32/ledc_periph.c @@ -0,0 +1,28 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[2] = { + { + .sig_out0_idx = LEDC_HS_SIG_OUT0_IDX, + }, + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; \ No newline at end of file diff --git a/components/soc/esp32/sources.cmake b/components/soc/esp32/sources.cmake index 4f6e2e3af5..c6cb1965fc 100644 --- a/components/soc/esp32/sources.cmake +++ b/components/soc/esp32/sources.cmake @@ -11,7 +11,8 @@ set(SOC_SRCS "cpu_util.c" "sdio_slave_periph.c" "sdmmc_periph.c" "soc_memory_layout.c" - "spi_periph.c") + "spi_periph.c" + "ledc_periph.c") if(NOT CMAKE_BUILD_EARLY_EXPANSION) set_source_files_properties("esp32/rtc_clk.c" PROPERTIES diff --git a/components/soc/esp32s2beta/include/soc/ledc_reg.h b/components/soc/esp32s2beta/include/soc/ledc_reg.h index f3fcdd03b2..1110b9987f 100644 --- a/components/soc/esp32s2beta/include/soc/ledc_reg.h +++ b/components/soc/esp32s2beta/include/soc/ledc_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -19,790 +19,25 @@ extern "C" { #endif #include "soc.h" -#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) +#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) /* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: This bit is clock gating control signal. when software config - LED_PWM internal registers it controls the register clock.*/ +/*description: */ #define LEDC_CLK_EN (BIT(31)) #define LEDC_CLK_EN_M (BIT(31)) #define LEDC_CLK_EN_V 0x1 #define LEDC_CLK_EN_S 31 -/* LEDC_OVF_CNT_EN_HSCH0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */ /*description: */ -#define LEDC_OVF_CNT_EN_HSCH0 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH0_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH0_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH0_S 14 -/* LEDC_OVF_NUM_HSCH0 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ +#define LEDC_OVF_CNT_RESET_ST_LSCH0 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH0_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH0_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH0_S 17 +/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */ /*description: */ -#define LEDC_OVF_NUM_HSCH0 0x000003FF -#define LEDC_OVF_NUM_HSCH0_M ((LEDC_OVF_NUM_HSCH0_V)<<(LEDC_OVF_NUM_HSCH0_S)) -#define LEDC_OVF_NUM_HSCH0_V 0x3FF -#define LEDC_OVF_NUM_HSCH0_S 4 -/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel0 is off.*/ -#define LEDC_IDLE_LV_HSCH0 (BIT(3)) -#define LEDC_IDLE_LV_HSCH0_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH0_V 0x1 -#define LEDC_IDLE_LV_HSCH0_S 3 -/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel0*/ -#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH0_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH0_S 2 -/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH0 0x00000003 -#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) -#define LEDC_TIMER_SEL_HSCH0_V 0x3 -#define LEDC_TIMER_SEL_HSCH0_S 0 - -#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) -/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ -#define LEDC_HPOINT_HSCH0 0x000FFFFF -#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) -#define LEDC_HPOINT_HSCH0_V 0xFFFFF -#define LEDC_HPOINT_HSCH0_S 0 - -#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) -/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH0 0x01FFFFFF -#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) -#define LEDC_DUTY_HSCH0_V 0x1FFFFFF -#define LEDC_DUTY_HSCH0_S 0 - -#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) -/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 - has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH0 (BIT(31)) -#define LEDC_DUTY_START_HSCH0_M (BIT(31)) -#define LEDC_DUTY_START_HSCH0_V 0x1 -#define LEDC_DUTY_START_HSCH0_S 31 -/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel0.*/ -#define LEDC_DUTY_INC_HSCH0 (BIT(30)) -#define LEDC_DUTY_INC_HSCH0_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH0_V 0x1 -#define LEDC_DUTY_INC_HSCH0_S 30 -/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel0.*/ -#define LEDC_DUTY_NUM_HSCH0 0x000003FF -#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) -#define LEDC_DUTY_NUM_HSCH0_V 0x3FF -#define LEDC_DUTY_NUM_HSCH0_S 20 -/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch0 cycles for high speed channel0.*/ -#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) -#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH0_S 10 -/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel0.*/ -#define LEDC_DUTY_SCALE_HSCH0 0x000003FF -#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) -#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH0_S 0 - -#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) -/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel0.*/ -#define LEDC_DUTY_HSCH0 0x01FFFFFF -#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) -#define LEDC_DUTY_HSCH0_V 0x1FFFFFF -#define LEDC_DUTY_HSCH0_S 0 - -#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) -/* LEDC_OVF_CNT_EN_HSCH1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_HSCH1 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH1_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH1_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH1_S 14 -/* LEDC_OVF_NUM_HSCH1 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_HSCH1 0x000003FF -#define LEDC_OVF_NUM_HSCH1_M ((LEDC_OVF_NUM_HSCH1_V)<<(LEDC_OVF_NUM_HSCH1_S)) -#define LEDC_OVF_NUM_HSCH1_V 0x3FF -#define LEDC_OVF_NUM_HSCH1_S 4 -/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel1 is off.*/ -#define LEDC_IDLE_LV_HSCH1 (BIT(3)) -#define LEDC_IDLE_LV_HSCH1_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH1_V 0x1 -#define LEDC_IDLE_LV_HSCH1_S 3 -/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel1*/ -#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH1_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH1_S 2 -/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH1 0x00000003 -#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) -#define LEDC_TIMER_SEL_HSCH1_V 0x3 -#define LEDC_TIMER_SEL_HSCH1_S 0 - -#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) -/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ -#define LEDC_HPOINT_HSCH1 0x000FFFFF -#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) -#define LEDC_HPOINT_HSCH1_V 0xFFFFF -#define LEDC_HPOINT_HSCH1_S 0 - -#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) -/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH1 0x01FFFFFF -#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) -#define LEDC_DUTY_HSCH1_V 0x1FFFFFF -#define LEDC_DUTY_HSCH1_S 0 - -#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) -/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH1 (BIT(31)) -#define LEDC_DUTY_START_HSCH1_M (BIT(31)) -#define LEDC_DUTY_START_HSCH1_V 0x1 -#define LEDC_DUTY_START_HSCH1_S 31 -/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel1.*/ -#define LEDC_DUTY_INC_HSCH1 (BIT(30)) -#define LEDC_DUTY_INC_HSCH1_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH1_V 0x1 -#define LEDC_DUTY_INC_HSCH1_S 30 -/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel1.*/ -#define LEDC_DUTY_NUM_HSCH1 0x000003FF -#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) -#define LEDC_DUTY_NUM_HSCH1_V 0x3FF -#define LEDC_DUTY_NUM_HSCH1_S 20 -/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch1 cycles for high speed channel1.*/ -#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) -#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH1_S 10 -/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel1.*/ -#define LEDC_DUTY_SCALE_HSCH1 0x000003FF -#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) -#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH1_S 0 - -#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) -/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel1.*/ -#define LEDC_DUTY_HSCH1 0x01FFFFFF -#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) -#define LEDC_DUTY_HSCH1_V 0x1FFFFFF -#define LEDC_DUTY_HSCH1_S 0 - -#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) -/* LEDC_OVF_CNT_EN_HSCH2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_HSCH2 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH2_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH2_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH2_S 14 -/* LEDC_OVF_NUM_HSCH2 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_HSCH2 0x000003FF -#define LEDC_OVF_NUM_HSCH2_M ((LEDC_OVF_NUM_HSCH2_V)<<(LEDC_OVF_NUM_HSCH2_S)) -#define LEDC_OVF_NUM_HSCH2_V 0x3FF -#define LEDC_OVF_NUM_HSCH2_S 4 -/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel2 is off.*/ -#define LEDC_IDLE_LV_HSCH2 (BIT(3)) -#define LEDC_IDLE_LV_HSCH2_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH2_V 0x1 -#define LEDC_IDLE_LV_HSCH2_S 3 -/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel2*/ -#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH2_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH2_S 2 -/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH2 0x00000003 -#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) -#define LEDC_TIMER_SEL_HSCH2_V 0x3 -#define LEDC_TIMER_SEL_HSCH2_S 0 - -#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) -/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ -#define LEDC_HPOINT_HSCH2 0x000FFFFF -#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) -#define LEDC_HPOINT_HSCH2_V 0xFFFFF -#define LEDC_HPOINT_HSCH2_S 0 - -#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) -/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH2 0x01FFFFFF -#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) -#define LEDC_DUTY_HSCH2_V 0x1FFFFFF -#define LEDC_DUTY_HSCH2_S 0 - -#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) -/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 - has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH2 (BIT(31)) -#define LEDC_DUTY_START_HSCH2_M (BIT(31)) -#define LEDC_DUTY_START_HSCH2_V 0x1 -#define LEDC_DUTY_START_HSCH2_S 31 -/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel2.*/ -#define LEDC_DUTY_INC_HSCH2 (BIT(30)) -#define LEDC_DUTY_INC_HSCH2_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH2_V 0x1 -#define LEDC_DUTY_INC_HSCH2_S 30 -/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel2.*/ -#define LEDC_DUTY_NUM_HSCH2 0x000003FF -#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) -#define LEDC_DUTY_NUM_HSCH2_V 0x3FF -#define LEDC_DUTY_NUM_HSCH2_S 20 -/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch2 cycles for high speed channel2.*/ -#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) -#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH2_S 10 -/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel2.*/ -#define LEDC_DUTY_SCALE_HSCH2 0x000003FF -#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) -#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH2_S 0 - -#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) -/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel2.*/ -#define LEDC_DUTY_HSCH2 0x01FFFFFF -#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) -#define LEDC_DUTY_HSCH2_V 0x1FFFFFF -#define LEDC_DUTY_HSCH2_S 0 - -#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) -/* LEDC_OVF_CNT_EN_HSCH3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_HSCH3 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH3_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH3_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH3_S 14 -/* LEDC_OVF_NUM_HSCH3 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_HSCH3 0x000003FF -#define LEDC_OVF_NUM_HSCH3_M ((LEDC_OVF_NUM_HSCH3_V)<<(LEDC_OVF_NUM_HSCH3_S)) -#define LEDC_OVF_NUM_HSCH3_V 0x3FF -#define LEDC_OVF_NUM_HSCH3_S 4 -/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel3 is off.*/ -#define LEDC_IDLE_LV_HSCH3 (BIT(3)) -#define LEDC_IDLE_LV_HSCH3_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH3_V 0x1 -#define LEDC_IDLE_LV_HSCH3_S 3 -/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel3*/ -#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH3_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH3_S 2 -/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH3 0x00000003 -#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) -#define LEDC_TIMER_SEL_HSCH3_V 0x3 -#define LEDC_TIMER_SEL_HSCH3_S 0 - -#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) -/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ -#define LEDC_HPOINT_HSCH3 0x000FFFFF -#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) -#define LEDC_HPOINT_HSCH3_V 0xFFFFF -#define LEDC_HPOINT_HSCH3_S 0 - -#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) -/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH3 0x01FFFFFF -#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) -#define LEDC_DUTY_HSCH3_V 0x1FFFFFF -#define LEDC_DUTY_HSCH3_S 0 - -#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) -/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 - has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH3 (BIT(31)) -#define LEDC_DUTY_START_HSCH3_M (BIT(31)) -#define LEDC_DUTY_START_HSCH3_V 0x1 -#define LEDC_DUTY_START_HSCH3_S 31 -/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel3.*/ -#define LEDC_DUTY_INC_HSCH3 (BIT(30)) -#define LEDC_DUTY_INC_HSCH3_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH3_V 0x1 -#define LEDC_DUTY_INC_HSCH3_S 30 -/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel3.*/ -#define LEDC_DUTY_NUM_HSCH3 0x000003FF -#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) -#define LEDC_DUTY_NUM_HSCH3_V 0x3FF -#define LEDC_DUTY_NUM_HSCH3_S 20 -/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch3 cycles for high speed channel3.*/ -#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) -#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH3_S 10 -/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel3.*/ -#define LEDC_DUTY_SCALE_HSCH3 0x000003FF -#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) -#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH3_S 0 - -#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) -/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel3.*/ -#define LEDC_DUTY_HSCH3 0x01FFFFFF -#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) -#define LEDC_DUTY_HSCH3_V 0x1FFFFFF -#define LEDC_DUTY_HSCH3_S 0 - -#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) -/* LEDC_OVF_CNT_EN_HSCH4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_HSCH4 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH4_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH4_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH4_S 14 -/* LEDC_OVF_NUM_HSCH4 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_HSCH4 0x000003FF -#define LEDC_OVF_NUM_HSCH4_M ((LEDC_OVF_NUM_HSCH4_V)<<(LEDC_OVF_NUM_HSCH4_S)) -#define LEDC_OVF_NUM_HSCH4_V 0x3FF -#define LEDC_OVF_NUM_HSCH4_S 4 -/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel4 is off.*/ -#define LEDC_IDLE_LV_HSCH4 (BIT(3)) -#define LEDC_IDLE_LV_HSCH4_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH4_V 0x1 -#define LEDC_IDLE_LV_HSCH4_S 3 -/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel4*/ -#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH4_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH4_S 2 -/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH4 0x00000003 -#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) -#define LEDC_TIMER_SEL_HSCH4_V 0x3 -#define LEDC_TIMER_SEL_HSCH4_S 0 - -#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) -/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ -#define LEDC_HPOINT_HSCH4 0x000FFFFF -#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) -#define LEDC_HPOINT_HSCH4_V 0xFFFFF -#define LEDC_HPOINT_HSCH4_S 0 - -#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) -/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH4 0x01FFFFFF -#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) -#define LEDC_DUTY_HSCH4_V 0x1FFFFFF -#define LEDC_DUTY_HSCH4_S 0 - -#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) -/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH4 (BIT(31)) -#define LEDC_DUTY_START_HSCH4_M (BIT(31)) -#define LEDC_DUTY_START_HSCH4_V 0x1 -#define LEDC_DUTY_START_HSCH4_S 31 -/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel4.*/ -#define LEDC_DUTY_INC_HSCH4 (BIT(30)) -#define LEDC_DUTY_INC_HSCH4_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH4_V 0x1 -#define LEDC_DUTY_INC_HSCH4_S 30 -/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel1.*/ -#define LEDC_DUTY_NUM_HSCH4 0x000003FF -#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) -#define LEDC_DUTY_NUM_HSCH4_V 0x3FF -#define LEDC_DUTY_NUM_HSCH4_S 20 -/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch4 cycles for high speed channel4.*/ -#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) -#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH4_S 10 -/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel4.*/ -#define LEDC_DUTY_SCALE_HSCH4 0x000003FF -#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) -#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH4_S 0 - -#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) -/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel4.*/ -#define LEDC_DUTY_HSCH4 0x01FFFFFF -#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) -#define LEDC_DUTY_HSCH4_V 0x1FFFFFF -#define LEDC_DUTY_HSCH4_S 0 - -#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) -/* LEDC_OVF_CNT_EN_HSCH5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_HSCH5 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH5_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH5_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH5_S 14 -/* LEDC_OVF_NUM_HSCH5 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_HSCH5 0x000003FF -#define LEDC_OVF_NUM_HSCH5_M ((LEDC_OVF_NUM_HSCH5_V)<<(LEDC_OVF_NUM_HSCH5_S)) -#define LEDC_OVF_NUM_HSCH5_V 0x3FF -#define LEDC_OVF_NUM_HSCH5_S 4 -/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel5 is off.*/ -#define LEDC_IDLE_LV_HSCH5 (BIT(3)) -#define LEDC_IDLE_LV_HSCH5_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH5_V 0x1 -#define LEDC_IDLE_LV_HSCH5_S 3 -/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel5.*/ -#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH5_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH5_S 2 -/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH5 0x00000003 -#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) -#define LEDC_TIMER_SEL_HSCH5_V 0x3 -#define LEDC_TIMER_SEL_HSCH5_S 0 - -#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) -/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ -#define LEDC_HPOINT_HSCH5 0x000FFFFF -#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) -#define LEDC_HPOINT_HSCH5_V 0xFFFFF -#define LEDC_HPOINT_HSCH5_S 0 - -#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) -/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH5 0x01FFFFFF -#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) -#define LEDC_DUTY_HSCH5_V 0x1FFFFFF -#define LEDC_DUTY_HSCH5_S 0 - -#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) -/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 - has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH5 (BIT(31)) -#define LEDC_DUTY_START_HSCH5_M (BIT(31)) -#define LEDC_DUTY_START_HSCH5_V 0x1 -#define LEDC_DUTY_START_HSCH5_S 31 -/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel5.*/ -#define LEDC_DUTY_INC_HSCH5 (BIT(30)) -#define LEDC_DUTY_INC_HSCH5_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH5_V 0x1 -#define LEDC_DUTY_INC_HSCH5_S 30 -/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel5.*/ -#define LEDC_DUTY_NUM_HSCH5 0x000003FF -#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) -#define LEDC_DUTY_NUM_HSCH5_V 0x3FF -#define LEDC_DUTY_NUM_HSCH5_S 20 -/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch5 cycles for high speed channel5.*/ -#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) -#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH5_S 10 -/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel5.*/ -#define LEDC_DUTY_SCALE_HSCH5 0x000003FF -#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) -#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH5_S 0 - -#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) -/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel5.*/ -#define LEDC_DUTY_HSCH5 0x01FFFFFF -#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) -#define LEDC_DUTY_HSCH5_V 0x1FFFFFF -#define LEDC_DUTY_HSCH5_S 0 - -#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) -/* LEDC_OVF_CNT_EN_HSCH6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_HSCH6 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH6_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH6_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH6_S 14 -/* LEDC_OVF_NUM_HSCH6 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_HSCH6 0x000003FF -#define LEDC_OVF_NUM_HSCH6_M ((LEDC_OVF_NUM_HSCH6_V)<<(LEDC_OVF_NUM_HSCH6_S)) -#define LEDC_OVF_NUM_HSCH6_V 0x3FF -#define LEDC_OVF_NUM_HSCH6_S 4 -/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel6 is off.*/ -#define LEDC_IDLE_LV_HSCH6 (BIT(3)) -#define LEDC_IDLE_LV_HSCH6_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH6_V 0x1 -#define LEDC_IDLE_LV_HSCH6_S 3 -/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel6*/ -#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH6_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH6_S 2 -/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH6 0x00000003 -#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) -#define LEDC_TIMER_SEL_HSCH6_V 0x3 -#define LEDC_TIMER_SEL_HSCH6_S 0 - -#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) -/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ -#define LEDC_HPOINT_HSCH6 0x000FFFFF -#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) -#define LEDC_HPOINT_HSCH6_V 0xFFFFF -#define LEDC_HPOINT_HSCH6_S 0 - -#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) -/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH6 0x01FFFFFF -#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) -#define LEDC_DUTY_HSCH6_V 0x1FFFFFF -#define LEDC_DUTY_HSCH6_S 0 - -#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) -/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH6 (BIT(31)) -#define LEDC_DUTY_START_HSCH6_M (BIT(31)) -#define LEDC_DUTY_START_HSCH6_V 0x1 -#define LEDC_DUTY_START_HSCH6_S 31 -/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel6.*/ -#define LEDC_DUTY_INC_HSCH6 (BIT(30)) -#define LEDC_DUTY_INC_HSCH6_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH6_V 0x1 -#define LEDC_DUTY_INC_HSCH6_S 30 -/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel6.*/ -#define LEDC_DUTY_NUM_HSCH6 0x000003FF -#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) -#define LEDC_DUTY_NUM_HSCH6_V 0x3FF -#define LEDC_DUTY_NUM_HSCH6_S 20 -/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch6 cycles for high speed channel6.*/ -#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) -#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH6_S 10 -/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel6.*/ -#define LEDC_DUTY_SCALE_HSCH6 0x000003FF -#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) -#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH6_S 0 - -#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) -/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel6.*/ -#define LEDC_DUTY_HSCH6 0x01FFFFFF -#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) -#define LEDC_DUTY_HSCH6_V 0x1FFFFFF -#define LEDC_DUTY_HSCH6_S 0 - -#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) -/* LEDC_OVF_CNT_EN_HSCH7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_EN_HSCH7 (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH7_M (BIT(14)) -#define LEDC_OVF_CNT_EN_HSCH7_V 0x1 -#define LEDC_OVF_CNT_EN_HSCH7_S 14 -/* LEDC_OVF_NUM_HSCH7 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */ -/*description: */ -#define LEDC_OVF_NUM_HSCH7 0x000003FF -#define LEDC_OVF_NUM_HSCH7_M ((LEDC_OVF_NUM_HSCH7_V)<<(LEDC_OVF_NUM_HSCH7_S)) -#define LEDC_OVF_NUM_HSCH7_V 0x3FF -#define LEDC_OVF_NUM_HSCH7_S 4 -/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when high speed channel7 is off.*/ -#define LEDC_IDLE_LV_HSCH7 (BIT(3)) -#define LEDC_IDLE_LV_HSCH7_M (BIT(3)) -#define LEDC_IDLE_LV_HSCH7_V 0x1 -#define LEDC_IDLE_LV_HSCH7_S 3 -/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for high speed channel7.*/ -#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) -#define LEDC_SIG_OUT_EN_HSCH7_V 0x1 -#define LEDC_SIG_OUT_EN_HSCH7_S 2 -/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four high speed timers the two bits are used to select - one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ -#define LEDC_TIMER_SEL_HSCH7 0x00000003 -#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) -#define LEDC_TIMER_SEL_HSCH7_V 0x3 -#define LEDC_TIMER_SEL_HSCH7_S 0 - -#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) -/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when htimerx(x=[0 3]) selected - by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ -#define LEDC_HPOINT_HSCH7 0x000FFFFF -#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) -#define LEDC_HPOINT_HSCH7_V 0xFFFFF -#define LEDC_HPOINT_HSCH7_S 0 - -#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) -/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When hstimerx(x=[0 - 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_HSCH7 0x01FFFFFF -#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) -#define LEDC_DUTY_HSCH7_V 0x1FFFFFF -#define LEDC_DUTY_HSCH7_S 0 - -#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) -/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ -#define LEDC_DUTY_START_HSCH7 (BIT(31)) -#define LEDC_DUTY_START_HSCH7_M (BIT(31)) -#define LEDC_DUTY_START_HSCH7_V 0x1 -#define LEDC_DUTY_START_HSCH7_S 31 -/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for high speed channel6.*/ -#define LEDC_DUTY_INC_HSCH7 (BIT(30)) -#define LEDC_DUTY_INC_HSCH7_M (BIT(30)) -#define LEDC_DUTY_INC_HSCH7_V 0x1 -#define LEDC_DUTY_INC_HSCH7_S 30 -/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for high speed channel6.*/ -#define LEDC_DUTY_NUM_HSCH7 0x000003FF -#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) -#define LEDC_DUTY_NUM_HSCH7_V 0x3FF -#define LEDC_DUTY_NUM_HSCH7_S 20 -/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_hsch7 cycles for high speed channel7.*/ -#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF -#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) -#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF -#define LEDC_DUTY_CYCLE_HSCH7_S 10 -/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - high speed channel7.*/ -#define LEDC_DUTY_SCALE_HSCH7 0x000003FF -#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) -#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF -#define LEDC_DUTY_SCALE_HSCH7_S 0 - -#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) -/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for high speed channel7.*/ -#define LEDC_DUTY_HSCH7 0x01FFFFFF -#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) -#define LEDC_DUTY_HSCH7_V 0x1FFFFFF -#define LEDC_DUTY_HSCH7_S 0 - -#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) +#define LEDC_OVF_CNT_RESET_LSCH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH0_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH0_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH0_S 16 /* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH0 (BIT(15)) @@ -815,98 +50,100 @@ extern "C" { #define LEDC_OVF_NUM_LSCH0_M ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S)) #define LEDC_OVF_NUM_LSCH0_V 0x3FF #define LEDC_OVF_NUM_LSCH0_S 5 -/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY - for low speed channel0.*/ +/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH0 (BIT(4)) #define LEDC_PARA_UP_LSCH0_M (BIT(4)) #define LEDC_PARA_UP_LSCH0_V 0x1 #define LEDC_PARA_UP_LSCH0_S 4 /* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel0 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH0 (BIT(3)) #define LEDC_IDLE_LV_LSCH0_M (BIT(3)) #define LEDC_IDLE_LV_LSCH0_V 0x1 #define LEDC_IDLE_LV_LSCH0_S 3 /* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel0.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH0_V 0x1 #define LEDC_SIG_OUT_EN_LSCH0_S 2 /* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH0 0x00000003 #define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) #define LEDC_TIMER_SEL_LSCH0_V 0x3 #define LEDC_TIMER_SEL_LSCH0_S 0 -#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) -/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ -#define LEDC_HPOINT_LSCH0 0x000FFFFF +#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) +/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH0 0x00003FFF #define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) -#define LEDC_HPOINT_LSCH0_V 0xFFFFF +#define LEDC_HPOINT_LSCH0_V 0x3FFF #define LEDC_HPOINT_LSCH0_S 0 -#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) -/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) +/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH0 0x0007FFFF #define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_V 0x7FFFF #define LEDC_DUTY_LSCH0_S 0 -#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) +#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) /* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH0 (BIT(31)) #define LEDC_DUTY_START_LSCH0_M (BIT(31)) #define LEDC_DUTY_START_LSCH0_V 0x1 #define LEDC_DUTY_START_LSCH0_S 31 /* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel6.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH0 (BIT(30)) #define LEDC_DUTY_INC_LSCH0_M (BIT(30)) #define LEDC_DUTY_INC_LSCH0_V 0x1 #define LEDC_DUTY_INC_LSCH0_S 30 /* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel6.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH0 0x000003FF #define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) #define LEDC_DUTY_NUM_LSCH0_V 0x3FF #define LEDC_DUTY_NUM_LSCH0_S 20 /* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch0 cycles for low speed channel0.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH0 0x000003FF #define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) #define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH0_S 10 /* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel0.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH0 0x000003FF #define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) #define LEDC_DUTY_SCALE_LSCH0_V 0x3FF #define LEDC_DUTY_SCALE_LSCH0_S 0 -#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) -/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel0.*/ -#define LEDC_DUTY_LSCH0 0x01FFFFFF +#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) +/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH0 0x0007FFFF #define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) -#define LEDC_DUTY_LSCH0_V 0x1FFFFFF +#define LEDC_DUTY_LSCH0_V 0x7FFFF #define LEDC_DUTY_LSCH0_S 0 -#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) +#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) +/* LEDC_OVF_CNT_RESET_ST_LSCH1 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH1 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH1_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH1_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH1_S 17 +/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH1_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH1_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH1_S 16 /* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH1 (BIT(15)) @@ -919,98 +156,100 @@ extern "C" { #define LEDC_OVF_NUM_LSCH1_M ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S)) #define LEDC_OVF_NUM_LSCH1_V 0x3FF #define LEDC_OVF_NUM_LSCH1_S 5 -/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY - for low speed channel1.*/ +/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH1 (BIT(4)) #define LEDC_PARA_UP_LSCH1_M (BIT(4)) #define LEDC_PARA_UP_LSCH1_V 0x1 #define LEDC_PARA_UP_LSCH1_S 4 /* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel1 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH1 (BIT(3)) #define LEDC_IDLE_LV_LSCH1_M (BIT(3)) #define LEDC_IDLE_LV_LSCH1_V 0x1 #define LEDC_IDLE_LV_LSCH1_S 3 /* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel1.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH1_V 0x1 #define LEDC_SIG_OUT_EN_LSCH1_S 2 /* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH1 0x00000003 #define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) #define LEDC_TIMER_SEL_LSCH1_V 0x3 #define LEDC_TIMER_SEL_LSCH1_S 0 -#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) -/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ -#define LEDC_HPOINT_LSCH1 0x000FFFFF +#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) +/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH1 0x00003FFF #define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) -#define LEDC_HPOINT_LSCH1_V 0xFFFFF +#define LEDC_HPOINT_LSCH1_V 0x3FFF #define LEDC_HPOINT_LSCH1_S 0 -#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) -/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) +/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH1 0x0007FFFF #define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_V 0x7FFFF #define LEDC_DUTY_LSCH1_S 0 -#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) +#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) /* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 - has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH1 (BIT(31)) #define LEDC_DUTY_START_LSCH1_M (BIT(31)) #define LEDC_DUTY_START_LSCH1_V 0x1 #define LEDC_DUTY_START_LSCH1_S 31 /* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel1.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH1 (BIT(30)) #define LEDC_DUTY_INC_LSCH1_M (BIT(30)) #define LEDC_DUTY_INC_LSCH1_V 0x1 #define LEDC_DUTY_INC_LSCH1_S 30 /* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel1.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH1 0x000003FF #define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) #define LEDC_DUTY_NUM_LSCH1_V 0x3FF #define LEDC_DUTY_NUM_LSCH1_S 20 /* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch1 cycles for low speed channel1.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH1 0x000003FF #define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) #define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH1_S 10 /* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel1.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH1 0x000003FF #define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) #define LEDC_DUTY_SCALE_LSCH1_V 0x3FF #define LEDC_DUTY_SCALE_LSCH1_S 0 -#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) -/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel1.*/ -#define LEDC_DUTY_LSCH1 0x01FFFFFF +#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) +/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH1 0x0007FFFF #define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) -#define LEDC_DUTY_LSCH1_V 0x1FFFFFF +#define LEDC_DUTY_LSCH1_V 0x7FFFF #define LEDC_DUTY_LSCH1_S 0 -#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) +#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) +/* LEDC_OVF_CNT_RESET_ST_LSCH2 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH2 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH2_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH2_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH2_S 17 +/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH2_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH2_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH2_S 16 /* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH2 (BIT(15)) @@ -1023,98 +262,100 @@ extern "C" { #define LEDC_OVF_NUM_LSCH2_M ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S)) #define LEDC_OVF_NUM_LSCH2_V 0x3FF #define LEDC_OVF_NUM_LSCH2_S 5 -/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY - for low speed channel2.*/ +/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH2 (BIT(4)) #define LEDC_PARA_UP_LSCH2_M (BIT(4)) #define LEDC_PARA_UP_LSCH2_V 0x1 #define LEDC_PARA_UP_LSCH2_S 4 /* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel2 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH2 (BIT(3)) #define LEDC_IDLE_LV_LSCH2_M (BIT(3)) #define LEDC_IDLE_LV_LSCH2_V 0x1 #define LEDC_IDLE_LV_LSCH2_S 3 /* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel2.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH2_V 0x1 #define LEDC_SIG_OUT_EN_LSCH2_S 2 /* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH2 0x00000003 #define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) #define LEDC_TIMER_SEL_LSCH2_V 0x3 #define LEDC_TIMER_SEL_LSCH2_S 0 -#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) -/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ -#define LEDC_HPOINT_LSCH2 0x000FFFFF +#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) +/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH2 0x00003FFF #define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) -#define LEDC_HPOINT_LSCH2_V 0xFFFFF +#define LEDC_HPOINT_LSCH2_V 0x3FFF #define LEDC_HPOINT_LSCH2_S 0 -#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) -/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) +/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH2 0x0007FFFF #define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_V 0x7FFFF #define LEDC_DUTY_LSCH2_S 0 -#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) +#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) /* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 - has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH2 (BIT(31)) #define LEDC_DUTY_START_LSCH2_M (BIT(31)) #define LEDC_DUTY_START_LSCH2_V 0x1 #define LEDC_DUTY_START_LSCH2_S 31 /* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel2.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH2 (BIT(30)) #define LEDC_DUTY_INC_LSCH2_M (BIT(30)) #define LEDC_DUTY_INC_LSCH2_V 0x1 #define LEDC_DUTY_INC_LSCH2_S 30 /* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel2.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH2 0x000003FF #define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) #define LEDC_DUTY_NUM_LSCH2_V 0x3FF #define LEDC_DUTY_NUM_LSCH2_S 20 /* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch2 cycles for low speed channel2.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH2 0x000003FF #define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) #define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH2_S 10 /* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel2.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH2 0x000003FF #define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) #define LEDC_DUTY_SCALE_LSCH2_V 0x3FF #define LEDC_DUTY_SCALE_LSCH2_S 0 -#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) -/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel2.*/ -#define LEDC_DUTY_LSCH2 0x01FFFFFF +#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) +/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH2 0x0007FFFF #define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) -#define LEDC_DUTY_LSCH2_V 0x1FFFFFF +#define LEDC_DUTY_LSCH2_V 0x7FFFF #define LEDC_DUTY_LSCH2_S 0 -#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) +#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) +/* LEDC_OVF_CNT_RESET_ST_LSCH3 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH3 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH3_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH3_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH3_S 17 +/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH3_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH3_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH3_S 16 /* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH3 (BIT(15)) @@ -1127,98 +368,100 @@ extern "C" { #define LEDC_OVF_NUM_LSCH3_M ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S)) #define LEDC_OVF_NUM_LSCH3_V 0x3FF #define LEDC_OVF_NUM_LSCH3_S 5 -/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY - for low speed channel3.*/ +/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH3 (BIT(4)) #define LEDC_PARA_UP_LSCH3_M (BIT(4)) #define LEDC_PARA_UP_LSCH3_V 0x1 #define LEDC_PARA_UP_LSCH3_S 4 /* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel3 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH3 (BIT(3)) #define LEDC_IDLE_LV_LSCH3_M (BIT(3)) #define LEDC_IDLE_LV_LSCH3_V 0x1 #define LEDC_IDLE_LV_LSCH3_S 3 /* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel3.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH3_V 0x1 #define LEDC_SIG_OUT_EN_LSCH3_S 2 /* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH3 0x00000003 #define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) #define LEDC_TIMER_SEL_LSCH3_V 0x3 #define LEDC_TIMER_SEL_LSCH3_S 0 -#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) -/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ -#define LEDC_HPOINT_LSCH3 0x000FFFFF +#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) +/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH3 0x00003FFF #define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) -#define LEDC_HPOINT_LSCH3_V 0xFFFFF +#define LEDC_HPOINT_LSCH3_V 0x3FFF #define LEDC_HPOINT_LSCH3_S 0 -#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) -/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) +/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH3 0x0007FFFF #define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_V 0x7FFFF #define LEDC_DUTY_LSCH3_S 0 -#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) +#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) /* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 - has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH3 (BIT(31)) #define LEDC_DUTY_START_LSCH3_M (BIT(31)) #define LEDC_DUTY_START_LSCH3_V 0x1 #define LEDC_DUTY_START_LSCH3_S 31 /* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel3.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH3 (BIT(30)) #define LEDC_DUTY_INC_LSCH3_M (BIT(30)) #define LEDC_DUTY_INC_LSCH3_V 0x1 #define LEDC_DUTY_INC_LSCH3_S 30 /* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel3.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH3 0x000003FF #define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) #define LEDC_DUTY_NUM_LSCH3_V 0x3FF #define LEDC_DUTY_NUM_LSCH3_S 20 /* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch3 cycles for low speed channel3.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH3 0x000003FF #define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) #define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH3_S 10 /* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel3.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH3 0x000003FF #define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) #define LEDC_DUTY_SCALE_LSCH3_V 0x3FF #define LEDC_DUTY_SCALE_LSCH3_S 0 -#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) -/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel3.*/ -#define LEDC_DUTY_LSCH3 0x01FFFFFF +#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) +/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH3 0x0007FFFF #define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) -#define LEDC_DUTY_LSCH3_V 0x1FFFFFF +#define LEDC_DUTY_LSCH3_V 0x7FFFF #define LEDC_DUTY_LSCH3_S 0 -#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) +#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) +/* LEDC_OVF_CNT_RESET_ST_LSCH4 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH4 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH4_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH4_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH4_S 17 +/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH4_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH4_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH4_S 16 /* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH4 (BIT(15)) @@ -1231,98 +474,100 @@ extern "C" { #define LEDC_OVF_NUM_LSCH4_M ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S)) #define LEDC_OVF_NUM_LSCH4_V 0x3FF #define LEDC_OVF_NUM_LSCH4_S 5 -/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY - for low speed channel4.*/ +/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH4 (BIT(4)) #define LEDC_PARA_UP_LSCH4_M (BIT(4)) #define LEDC_PARA_UP_LSCH4_V 0x1 #define LEDC_PARA_UP_LSCH4_S 4 /* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel4 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH4 (BIT(3)) #define LEDC_IDLE_LV_LSCH4_M (BIT(3)) #define LEDC_IDLE_LV_LSCH4_V 0x1 #define LEDC_IDLE_LV_LSCH4_S 3 /* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel4.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH4_V 0x1 #define LEDC_SIG_OUT_EN_LSCH4_S 2 /* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH4 0x00000003 #define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) #define LEDC_TIMER_SEL_LSCH4_V 0x3 #define LEDC_TIMER_SEL_LSCH4_S 0 -#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) -/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ -#define LEDC_HPOINT_LSCH4 0x000FFFFF +#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) +/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH4 0x00003FFF #define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) -#define LEDC_HPOINT_LSCH4_V 0xFFFFF +#define LEDC_HPOINT_LSCH4_V 0x3FFF #define LEDC_HPOINT_LSCH4_S 0 -#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) -/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) +/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH4 0x0007FFFF #define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_V 0x7FFFF #define LEDC_DUTY_LSCH4_S 0 -#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) +#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) /* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH4 (BIT(31)) #define LEDC_DUTY_START_LSCH4_M (BIT(31)) #define LEDC_DUTY_START_LSCH4_V 0x1 #define LEDC_DUTY_START_LSCH4_S 31 /* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel4.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH4 (BIT(30)) #define LEDC_DUTY_INC_LSCH4_M (BIT(30)) #define LEDC_DUTY_INC_LSCH4_V 0x1 #define LEDC_DUTY_INC_LSCH4_S 30 /* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel4.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH4 0x000003FF #define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) #define LEDC_DUTY_NUM_LSCH4_V 0x3FF #define LEDC_DUTY_NUM_LSCH4_S 20 /* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch4 cycles for low speed channel4.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH4 0x000003FF #define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) #define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH4_S 10 /* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel4.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH4 0x000003FF #define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) #define LEDC_DUTY_SCALE_LSCH4_V 0x3FF #define LEDC_DUTY_SCALE_LSCH4_S 0 -#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) -/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel4.*/ -#define LEDC_DUTY_LSCH4 0x01FFFFFF +#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) +/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH4 0x0007FFFF #define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) -#define LEDC_DUTY_LSCH4_V 0x1FFFFFF +#define LEDC_DUTY_LSCH4_V 0x7FFFF #define LEDC_DUTY_LSCH4_S 0 -#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) +#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) +/* LEDC_OVF_CNT_RESET_ST_LSCH5 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH5 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH5_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH5_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH5_S 17 +/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH5_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH5_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH5_S 16 /* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH5 (BIT(15)) @@ -1335,98 +580,100 @@ extern "C" { #define LEDC_OVF_NUM_LSCH5_M ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S)) #define LEDC_OVF_NUM_LSCH5_V 0x3FF #define LEDC_OVF_NUM_LSCH5_S 5 -/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY - for low speed channel5.*/ +/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH5 (BIT(4)) #define LEDC_PARA_UP_LSCH5_M (BIT(4)) #define LEDC_PARA_UP_LSCH5_V 0x1 #define LEDC_PARA_UP_LSCH5_S 4 /* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel5 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH5 (BIT(3)) #define LEDC_IDLE_LV_LSCH5_M (BIT(3)) #define LEDC_IDLE_LV_LSCH5_V 0x1 #define LEDC_IDLE_LV_LSCH5_S 3 /* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel5.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH5_V 0x1 #define LEDC_SIG_OUT_EN_LSCH5_S 2 /* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH5 0x00000003 #define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) #define LEDC_TIMER_SEL_LSCH5_V 0x3 #define LEDC_TIMER_SEL_LSCH5_S 0 -#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) -/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ -#define LEDC_HPOINT_LSCH5 0x000FFFFF +#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) +/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH5 0x00003FFF #define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) -#define LEDC_HPOINT_LSCH5_V 0xFFFFF +#define LEDC_HPOINT_LSCH5_V 0x3FFF #define LEDC_HPOINT_LSCH5_S 0 -#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) -/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) +/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH5 0x0007FFFF #define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_V 0x7FFFF #define LEDC_DUTY_LSCH5_S 0 -#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) +#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) /* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH5 (BIT(31)) #define LEDC_DUTY_START_LSCH5_M (BIT(31)) #define LEDC_DUTY_START_LSCH5_V 0x1 #define LEDC_DUTY_START_LSCH5_S 31 /* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel5.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH5 (BIT(30)) #define LEDC_DUTY_INC_LSCH5_M (BIT(30)) #define LEDC_DUTY_INC_LSCH5_V 0x1 #define LEDC_DUTY_INC_LSCH5_S 30 /* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel5.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH5 0x000003FF #define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) #define LEDC_DUTY_NUM_LSCH5_V 0x3FF #define LEDC_DUTY_NUM_LSCH5_S 20 /* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch5 cycles for low speed channel4.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH5 0x000003FF #define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) #define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH5_S 10 /* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel5.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH5 0x000003FF #define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) #define LEDC_DUTY_SCALE_LSCH5_V 0x3FF #define LEDC_DUTY_SCALE_LSCH5_S 0 -#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) -/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel5.*/ -#define LEDC_DUTY_LSCH5 0x01FFFFFF +#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) +/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH5 0x0007FFFF #define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) -#define LEDC_DUTY_LSCH5_V 0x1FFFFFF +#define LEDC_DUTY_LSCH5_V 0x7FFFF #define LEDC_DUTY_LSCH5_S 0 -#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) +#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) +/* LEDC_OVF_CNT_RESET_ST_LSCH6 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH6 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH6_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH6_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH6_S 17 +/* LEDC_OVF_CNT_RESET_LSCH6 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH6 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH6_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH6_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH6_S 16 /* LEDC_OVF_CNT_EN_LSCH6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH6 (BIT(15)) @@ -1439,98 +686,100 @@ extern "C" { #define LEDC_OVF_NUM_LSCH6_M ((LEDC_OVF_NUM_LSCH6_V)<<(LEDC_OVF_NUM_LSCH6_S)) #define LEDC_OVF_NUM_LSCH6_V 0x3FF #define LEDC_OVF_NUM_LSCH6_S 5 -/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY - for low speed channel6.*/ +/* LEDC_PARA_UP_LSCH6 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH6 (BIT(4)) #define LEDC_PARA_UP_LSCH6_M (BIT(4)) #define LEDC_PARA_UP_LSCH6_V 0x1 #define LEDC_PARA_UP_LSCH6_S 4 /* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel6 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH6 (BIT(3)) #define LEDC_IDLE_LV_LSCH6_M (BIT(3)) #define LEDC_IDLE_LV_LSCH6_V 0x1 #define LEDC_IDLE_LV_LSCH6_S 3 /* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel6.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH6_V 0x1 #define LEDC_SIG_OUT_EN_LSCH6_S 2 /* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH6 0x00000003 #define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) #define LEDC_TIMER_SEL_LSCH6_V 0x3 #define LEDC_TIMER_SEL_LSCH6_S 0 -#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) -/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ -#define LEDC_HPOINT_LSCH6 0x000FFFFF +#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) +/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH6 0x00003FFF #define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) -#define LEDC_HPOINT_LSCH6_V 0xFFFFF +#define LEDC_HPOINT_LSCH6_V 0x3FFF #define LEDC_HPOINT_LSCH6_S 0 -#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) -/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) +/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH6 0x0007FFFF #define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) -#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_V 0x7FFFF #define LEDC_DUTY_LSCH6_S 0 -#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) +#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) /* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 - has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH6 (BIT(31)) #define LEDC_DUTY_START_LSCH6_M (BIT(31)) #define LEDC_DUTY_START_LSCH6_V 0x1 #define LEDC_DUTY_START_LSCH6_S 31 /* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel6.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH6 (BIT(30)) #define LEDC_DUTY_INC_LSCH6_M (BIT(30)) #define LEDC_DUTY_INC_LSCH6_V 0x1 #define LEDC_DUTY_INC_LSCH6_S 30 /* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel6.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH6 0x000003FF #define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) #define LEDC_DUTY_NUM_LSCH6_V 0x3FF #define LEDC_DUTY_NUM_LSCH6_S 20 /* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch6 cycles for low speed channel6.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH6 0x000003FF #define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) #define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH6_S 10 /* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel6.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH6 0x000003FF #define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) #define LEDC_DUTY_SCALE_LSCH6_V 0x3FF #define LEDC_DUTY_SCALE_LSCH6_S 0 -#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) -/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel6.*/ -#define LEDC_DUTY_LSCH6 0x01FFFFFF +#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) +/* LEDC_DUTY_LSCH6 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH6 0x0007FFFF #define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) -#define LEDC_DUTY_LSCH6_V 0x1FFFFFF +#define LEDC_DUTY_LSCH6_V 0x7FFFF #define LEDC_DUTY_LSCH6_S 0 -#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) +#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) +/* LEDC_OVF_CNT_RESET_ST_LSCH7 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH7 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH7_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH7_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH7_S 17 +/* LEDC_OVF_CNT_RESET_LSCH7 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH7 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH7_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH7_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH7_S 16 /* LEDC_OVF_CNT_EN_LSCH7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: */ #define LEDC_OVF_CNT_EN_LSCH7 (BIT(15)) @@ -1543,1047 +792,760 @@ extern "C" { #define LEDC_OVF_NUM_LSCH7_M ((LEDC_OVF_NUM_LSCH7_V)<<(LEDC_OVF_NUM_LSCH7_S)) #define LEDC_OVF_NUM_LSCH7_V 0x3FF #define LEDC_OVF_NUM_LSCH7_S 5 -/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY - for low speed channel7.*/ +/* LEDC_PARA_UP_LSCH7 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ #define LEDC_PARA_UP_LSCH7 (BIT(4)) #define LEDC_PARA_UP_LSCH7_M (BIT(4)) #define LEDC_PARA_UP_LSCH7_V 0x1 #define LEDC_PARA_UP_LSCH7_S 4 /* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This bit is used to control the output value when low speed channel7 is off.*/ +/*description: */ #define LEDC_IDLE_LV_LSCH7 (BIT(3)) #define LEDC_IDLE_LV_LSCH7_M (BIT(3)) #define LEDC_IDLE_LV_LSCH7_V 0x1 #define LEDC_IDLE_LV_LSCH7_S 3 /* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the output enable control bit for low speed channel7.*/ +/*description: */ #define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) #define LEDC_SIG_OUT_EN_LSCH7_V 0x1 #define LEDC_SIG_OUT_EN_LSCH7_S 2 /* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: There are four low speed timers the two bits are used to select - one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ +/*description: */ #define LEDC_TIMER_SEL_LSCH7 0x00000003 #define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) #define LEDC_TIMER_SEL_LSCH7_V 0x3 #define LEDC_TIMER_SEL_LSCH7_S 0 -#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) -/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: The output value changes to high when lstimerx(x=[0 3]) selected - by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ -#define LEDC_HPOINT_LSCH7 0x000FFFFF +#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) +/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH7 0x00003FFF #define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) -#define LEDC_HPOINT_LSCH7_V 0xFFFFF +#define LEDC_HPOINT_LSCH7_V 0x3FFF #define LEDC_HPOINT_LSCH7_S 0 -#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) -/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: The register is used to control output duty. When lstimerx(x=[0 - 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ -#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) +/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH7 0x0007FFFF #define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) -#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_V 0x7FFFF #define LEDC_DUTY_LSCH7_S 0 -#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) +#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) /* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 - has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ +/*description: */ #define LEDC_DUTY_START_LSCH7 (BIT(31)) #define LEDC_DUTY_START_LSCH7_M (BIT(31)) #define LEDC_DUTY_START_LSCH7_V 0x1 #define LEDC_DUTY_START_LSCH7_S 31 /* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: This register is used to increase the duty of output signal or - decrease the duty of output signal for low speed channel4.*/ +/*description: */ #define LEDC_DUTY_INC_LSCH7 (BIT(30)) #define LEDC_DUTY_INC_LSCH7_M (BIT(30)) #define LEDC_DUTY_INC_LSCH7_V 0x1 #define LEDC_DUTY_INC_LSCH7_S 30 /* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ -/*description: This register is used to control the num of increased or decreased - times for low speed channel4.*/ +/*description: */ #define LEDC_DUTY_NUM_LSCH7 0x000003FF #define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) #define LEDC_DUTY_NUM_LSCH7_V 0x3FF #define LEDC_DUTY_NUM_LSCH7_S 20 /* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ -/*description: This register is used to increase or decrease the duty every - reg_duty_cycle_lsch7 cycles for low speed channel7.*/ +/*description: */ #define LEDC_DUTY_CYCLE_LSCH7 0x000003FF #define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) #define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF #define LEDC_DUTY_CYCLE_LSCH7_S 10 /* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: This register controls the increase or decrease step scale for - low speed channel7.*/ +/*description: */ #define LEDC_DUTY_SCALE_LSCH7 0x000003FF #define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) #define LEDC_DUTY_SCALE_LSCH7_V 0x3FF #define LEDC_DUTY_SCALE_LSCH7_S 0 -#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) -/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ -/*description: This register represents the current duty of the output signal - for low speed channel7.*/ -#define LEDC_DUTY_LSCH7 0x01FFFFFF +#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) +/* LEDC_DUTY_LSCH7 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH7 0x0007FFFF #define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) -#define LEDC_DUTY_LSCH7_V 0x1FFFFFF +#define LEDC_DUTY_LSCH7_V 0x7FFFF #define LEDC_DUTY_LSCH7_S 0 -#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) -/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer0. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER0_V 0x1 -#define LEDC_TICK_SEL_HSTIMER0_S 25 -/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER0_RST (BIT(24)) -#define LEDC_HSTIMER0_RST_M (BIT(24)) -#define LEDC_HSTIMER0_RST_V 0x1 -#define LEDC_HSTIMER0_RST_S 24 -/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer0*/ -#define LEDC_HSTIMER0_PAUSE (BIT(23)) -#define LEDC_HSTIMER0_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER0_PAUSE_V 0x1 -#define LEDC_HSTIMER0_PAUSE_S 23 -/* LEDC_CLK_DIV_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x00a0) +/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ /*description: */ -#define LEDC_CLK_DIV_HSTIMER0 0x0003FFFF -#define LEDC_CLK_DIV_HSTIMER0_M ((LEDC_CLK_DIV_HSTIMER0_V)<<(LEDC_CLK_DIV_HSTIMER0_S)) -#define LEDC_CLK_DIV_HSTIMER0_V 0x3FFFF -#define LEDC_CLK_DIV_HSTIMER0_S 5 -/* LEDC_HSTIMER0_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: */ -#define LEDC_HSTIMER0_DUTY_RES 0x0000001F -#define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S)) -#define LEDC_HSTIMER0_DUTY_RES_V 0x1F -#define LEDC_HSTIMER0_DUTY_RES_S 0 - -#define LEDC_DIV_NUM_HSTIMER0 LEDC_CLK_DIV_HSTIMER0 -#define LEDC_DIV_NUM_HSTIMER0_M LEDC_CLK_DIV_HSTIMER0_M -#define LEDC_DIV_NUM_HSTIMER0_V LEDC_CLK_DIV_HSTIMER0_V -#define LEDC_DIV_NUM_HSTIMER0_S LEDC_CLK_DIV_HSTIMER0_S - -#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) -/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer0*/ -#define LEDC_HSTIMER0_CNT 0x000FFFFF -#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) -#define LEDC_HSTIMER0_CNT_V 0xFFFFF -#define LEDC_HSTIMER0_CNT_S 0 - -#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) -/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer1. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER1_V 0x1 -#define LEDC_TICK_SEL_HSTIMER1_S 25 -/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER1_RST (BIT(24)) -#define LEDC_HSTIMER1_RST_M (BIT(24)) -#define LEDC_HSTIMER1_RST_V 0x1 -#define LEDC_HSTIMER1_RST_S 24 -/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer1*/ -#define LEDC_HSTIMER1_PAUSE (BIT(23)) -#define LEDC_HSTIMER1_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER1_PAUSE_V 0x1 -#define LEDC_HSTIMER1_PAUSE_S 23 -/* LEDC_CLK_DIV_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: */ -#define LEDC_CLK_DIV_HSTIMER1 0x0003FFFF -#define LEDC_CLK_DIV_HSTIMER1_M ((LEDC_CLK_DIV_HSTIMER1_V)<<(LEDC_CLK_DIV_HSTIMER1_S)) -#define LEDC_CLK_DIV_HSTIMER1_V 0x3FFFF -#define LEDC_CLK_DIV_HSTIMER1_S 5 -/* LEDC_HSTIMER1_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: */ -#define LEDC_HSTIMER1_DUTY_RES 0x0000001F -#define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S)) -#define LEDC_HSTIMER1_DUTY_RES_V 0x1F -#define LEDC_HSTIMER1_DUTY_RES_S 0 - -#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) -/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer1.*/ -#define LEDC_HSTIMER1_CNT 0x000FFFFF -#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) -#define LEDC_HSTIMER1_CNT_V 0xFFFFF -#define LEDC_HSTIMER1_CNT_S 0 - -#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) -/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer2. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER2_V 0x1 -#define LEDC_TICK_SEL_HSTIMER2_S 25 -/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER2_RST (BIT(24)) -#define LEDC_HSTIMER2_RST_M (BIT(24)) -#define LEDC_HSTIMER2_RST_V 0x1 -#define LEDC_HSTIMER2_RST_S 24 -/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer2*/ -#define LEDC_HSTIMER2_PAUSE (BIT(23)) -#define LEDC_HSTIMER2_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER2_PAUSE_V 0x1 -#define LEDC_HSTIMER2_PAUSE_S 23 -/* LEDC_CLK_DIV_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: */ -#define LEDC_CLK_DIV_HSTIMER2 0x0003FFFF -#define LEDC_CLK_DIV_HSTIMER2_M ((LEDC_CLK_DIV_HSTIMER2_V)<<(LEDC_CLK_DIV_HSTIMER2_S)) -#define LEDC_CLK_DIV_HSTIMER2_V 0x3FFFF -#define LEDC_CLK_DIV_HSTIMER2_S 5 -/* LEDC_HSTIMER2_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: */ -#define LEDC_HSTIMER2_DUTY_RES 0x0000001F -#define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S)) -#define LEDC_HSTIMER2_DUTY_RES_V 0x1F -#define LEDC_HSTIMER2_DUTY_RES_S 0 - -#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) -/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer2*/ -#define LEDC_HSTIMER2_CNT 0x000FFFFF -#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) -#define LEDC_HSTIMER2_CNT_V 0xFFFFF -#define LEDC_HSTIMER2_CNT_S 0 - -#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) -/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose apb_clk or ref_tick for high speed - timer3. 1'b1:apb_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) -#define LEDC_TICK_SEL_HSTIMER3_V 0x1 -#define LEDC_TICK_SEL_HSTIMER3_S 25 -/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ -#define LEDC_HSTIMER3_RST (BIT(24)) -#define LEDC_HSTIMER3_RST_M (BIT(24)) -#define LEDC_HSTIMER3_RST_V 0x1 -#define LEDC_HSTIMER3_RST_S 24 -/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in high speed timer3*/ -#define LEDC_HSTIMER3_PAUSE (BIT(23)) -#define LEDC_HSTIMER3_PAUSE_M (BIT(23)) -#define LEDC_HSTIMER3_PAUSE_V 0x1 -#define LEDC_HSTIMER3_PAUSE_S 23 -/* LEDC_CLK_DIV_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ -/*description: */ -#define LEDC_CLK_DIV_HSTIMER3 0x0003FFFF -#define LEDC_CLK_DIV_HSTIMER3_M ((LEDC_CLK_DIV_HSTIMER3_V)<<(LEDC_CLK_DIV_HSTIMER3_S)) -#define LEDC_CLK_DIV_HSTIMER3_V 0x3FFFF -#define LEDC_CLK_DIV_HSTIMER3_S 5 -/* LEDC_HSTIMER3_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -/*description: */ -#define LEDC_HSTIMER3_DUTY_RES 0x0000001F -#define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S)) -#define LEDC_HSTIMER3_DUTY_RES_V 0x1F -#define LEDC_HSTIMER3_DUTY_RES_S 0 - -#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) -/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in high speed timer3*/ -#define LEDC_HSTIMER3_CNT 0x000FFFFF -#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) -#define LEDC_HSTIMER3_CNT_V 0xFFFFF -#define LEDC_HSTIMER3_CNT_S 0 - -#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) -/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ -#define LEDC_LSTIMER0_PARA_UP (BIT(26)) -#define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER0_PARA_UP (BIT(25)) +#define LEDC_LSTIMER0_PARA_UP_M (BIT(25)) #define LEDC_LSTIMER0_PARA_UP_V 0x1 -#define LEDC_LSTIMER0_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer0. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) +#define LEDC_LSTIMER0_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER0 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER0_M (BIT(24)) #define LEDC_TICK_SEL_LSTIMER0_V 0x1 -#define LEDC_TICK_SEL_LSTIMER0_S 25 -/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER0_RST (BIT(24)) -#define LEDC_LSTIMER0_RST_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER0_S 24 +/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER0_RST (BIT(23)) +#define LEDC_LSTIMER0_RST_M (BIT(23)) #define LEDC_LSTIMER0_RST_V 0x1 -#define LEDC_LSTIMER0_RST_S 24 -/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer0.*/ -#define LEDC_LSTIMER0_PAUSE (BIT(23)) -#define LEDC_LSTIMER0_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER0_RST_S 23 +/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_PAUSE (BIT(22)) +#define LEDC_LSTIMER0_PAUSE_M (BIT(22)) #define LEDC_LSTIMER0_PAUSE_V 0x1 -#define LEDC_LSTIMER0_PAUSE_S 23 -/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +#define LEDC_LSTIMER0_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ /*description: */ #define LEDC_CLK_DIV_LSTIMER0 0x0003FFFF #define LEDC_CLK_DIV_LSTIMER0_M ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S)) #define LEDC_CLK_DIV_LSTIMER0_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER0_S 5 -/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define LEDC_CLK_DIV_LSTIMER0_S 4 +/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ /*description: */ -#define LEDC_LSTIMER0_DUTY_RES 0x0000001F +#define LEDC_LSTIMER0_DUTY_RES 0x0000000F #define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S)) -#define LEDC_LSTIMER0_DUTY_RES_V 0x1F +#define LEDC_LSTIMER0_DUTY_RES_V 0xF #define LEDC_LSTIMER0_DUTY_RES_S 0 -#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) -/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer0.*/ -#define LEDC_LSTIMER0_CNT 0x000FFFFF +#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x00a4) +/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_CNT 0x00003FFF #define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) -#define LEDC_LSTIMER0_CNT_V 0xFFFFF +#define LEDC_LSTIMER0_CNT_V 0x3FFF #define LEDC_LSTIMER0_CNT_S 0 -#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) -/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ -#define LEDC_LSTIMER1_PARA_UP (BIT(26)) -#define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x00a8) +/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER1_PARA_UP (BIT(25)) +#define LEDC_LSTIMER1_PARA_UP_M (BIT(25)) #define LEDC_LSTIMER1_PARA_UP_V 0x1 -#define LEDC_LSTIMER1_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer1. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) +#define LEDC_LSTIMER1_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER1 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER1_M (BIT(24)) #define LEDC_TICK_SEL_LSTIMER1_V 0x1 -#define LEDC_TICK_SEL_LSTIMER1_S 25 -/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER1_RST (BIT(24)) -#define LEDC_LSTIMER1_RST_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER1_S 24 +/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER1_RST (BIT(23)) +#define LEDC_LSTIMER1_RST_M (BIT(23)) #define LEDC_LSTIMER1_RST_V 0x1 -#define LEDC_LSTIMER1_RST_S 24 -/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer1.*/ -#define LEDC_LSTIMER1_PAUSE (BIT(23)) -#define LEDC_LSTIMER1_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER1_RST_S 23 +/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_PAUSE (BIT(22)) +#define LEDC_LSTIMER1_PAUSE_M (BIT(22)) #define LEDC_LSTIMER1_PAUSE_V 0x1 -#define LEDC_LSTIMER1_PAUSE_S 23 -/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +#define LEDC_LSTIMER1_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ /*description: */ #define LEDC_CLK_DIV_LSTIMER1 0x0003FFFF #define LEDC_CLK_DIV_LSTIMER1_M ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S)) #define LEDC_CLK_DIV_LSTIMER1_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER1_S 5 -/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define LEDC_CLK_DIV_LSTIMER1_S 4 +/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ /*description: */ -#define LEDC_LSTIMER1_DUTY_RES 0x0000001F +#define LEDC_LSTIMER1_DUTY_RES 0x0000000F #define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S)) -#define LEDC_LSTIMER1_DUTY_RES_V 0x1F +#define LEDC_LSTIMER1_DUTY_RES_V 0xF #define LEDC_LSTIMER1_DUTY_RES_S 0 -#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) -/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer1.*/ -#define LEDC_LSTIMER1_CNT 0x000FFFFF +#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x00aC) +/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_CNT 0x00003FFF #define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) -#define LEDC_LSTIMER1_CNT_V 0xFFFFF +#define LEDC_LSTIMER1_CNT_V 0x3FFF #define LEDC_LSTIMER1_CNT_S 0 -#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) -/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ -#define LEDC_LSTIMER2_PARA_UP (BIT(26)) -#define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x00b0) +/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER2_PARA_UP (BIT(25)) +#define LEDC_LSTIMER2_PARA_UP_M (BIT(25)) #define LEDC_LSTIMER2_PARA_UP_V 0x1 -#define LEDC_LSTIMER2_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer2. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) +#define LEDC_LSTIMER2_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER2 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER2_M (BIT(24)) #define LEDC_TICK_SEL_LSTIMER2_V 0x1 -#define LEDC_TICK_SEL_LSTIMER2_S 25 -/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER2_RST (BIT(24)) -#define LEDC_LSTIMER2_RST_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER2_S 24 +/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER2_RST (BIT(23)) +#define LEDC_LSTIMER2_RST_M (BIT(23)) #define LEDC_LSTIMER2_RST_V 0x1 -#define LEDC_LSTIMER2_RST_S 24 -/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer2.*/ -#define LEDC_LSTIMER2_PAUSE (BIT(23)) -#define LEDC_LSTIMER2_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER2_RST_S 23 +/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_PAUSE (BIT(22)) +#define LEDC_LSTIMER2_PAUSE_M (BIT(22)) #define LEDC_LSTIMER2_PAUSE_V 0x1 -#define LEDC_LSTIMER2_PAUSE_S 23 -/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +#define LEDC_LSTIMER2_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ /*description: */ #define LEDC_CLK_DIV_LSTIMER2 0x0003FFFF #define LEDC_CLK_DIV_LSTIMER2_M ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S)) #define LEDC_CLK_DIV_LSTIMER2_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER2_S 5 -/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define LEDC_CLK_DIV_LSTIMER2_S 4 +/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ /*description: */ -#define LEDC_LSTIMER2_DUTY_RES 0x0000001F +#define LEDC_LSTIMER2_DUTY_RES 0x0000000F #define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S)) -#define LEDC_LSTIMER2_DUTY_RES_V 0x1F +#define LEDC_LSTIMER2_DUTY_RES_V 0xF #define LEDC_LSTIMER2_DUTY_RES_S 0 -#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) -/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer2.*/ -#define LEDC_LSTIMER2_CNT 0x000FFFFF +#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x00b4) +/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_CNT 0x00003FFF #define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) -#define LEDC_LSTIMER2_CNT_V 0xFFFFF +#define LEDC_LSTIMER2_CNT_V 0x3FFF #define LEDC_LSTIMER2_CNT_S 0 -#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) -/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ -/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ -#define LEDC_LSTIMER3_PARA_UP (BIT(26)) -#define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) +#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x00b8) +/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER3_PARA_UP (BIT(25)) +#define LEDC_LSTIMER3_PARA_UP_M (BIT(25)) #define LEDC_LSTIMER3_PARA_UP_V 0x1 -#define LEDC_LSTIMER3_PARA_UP_S 26 -/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to choose slow_clk or ref_tick for low speed - timer3. 1'b1:slow_clk 0:ref_tick*/ -#define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) -#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) +#define LEDC_LSTIMER3_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER3 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER3_M (BIT(24)) #define LEDC_TICK_SEL_LSTIMER3_V 0x1 -#define LEDC_TICK_SEL_LSTIMER3_S 25 -/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ -#define LEDC_LSTIMER3_RST (BIT(24)) -#define LEDC_LSTIMER3_RST_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER3_S 24 +/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER3_RST (BIT(23)) +#define LEDC_LSTIMER3_RST_M (BIT(23)) #define LEDC_LSTIMER3_RST_V 0x1 -#define LEDC_LSTIMER3_RST_S 24 -/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to pause the counter in low speed timer3.*/ -#define LEDC_LSTIMER3_PAUSE (BIT(23)) -#define LEDC_LSTIMER3_PAUSE_M (BIT(23)) +#define LEDC_LSTIMER3_RST_S 23 +/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_PAUSE (BIT(22)) +#define LEDC_LSTIMER3_PAUSE_M (BIT(22)) #define LEDC_LSTIMER3_PAUSE_V 0x1 -#define LEDC_LSTIMER3_PAUSE_S 23 -/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ +#define LEDC_LSTIMER3_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ /*description: */ #define LEDC_CLK_DIV_LSTIMER3 0x0003FFFF #define LEDC_CLK_DIV_LSTIMER3_M ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S)) #define LEDC_CLK_DIV_LSTIMER3_V 0x3FFFF -#define LEDC_CLK_DIV_LSTIMER3_S 5 -/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define LEDC_CLK_DIV_LSTIMER3_S 4 +/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ /*description: */ -#define LEDC_LSTIMER3_DUTY_RES 0x0000001F +#define LEDC_LSTIMER3_DUTY_RES 0x0000000F #define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S)) -#define LEDC_LSTIMER3_DUTY_RES_V 0x1F +#define LEDC_LSTIMER3_DUTY_RES_V 0xF #define LEDC_LSTIMER3_DUTY_RES_S 0 -#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) -/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: software can read this register to get the current counter value - in low speed timer3.*/ -#define LEDC_LSTIMER3_CNT 0x000FFFFF +#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x00bC) +/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_CNT 0x00003FFF #define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) -#define LEDC_LSTIMER3_CNT_V 0xFFFFF +#define LEDC_LSTIMER3_CNT_V 0x3FFF #define LEDC_LSTIMER3_CNT_S 0 -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 7 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x00c0) +/* LEDC_OVF_CNT_LSCH7_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_RAW (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_RAW_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_RAW_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_RAW (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_RAW_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_RAW_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_RAW_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_RAW_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_RAW_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_RAW_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_RAW_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_RAW_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_RAW_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_RAW_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_RAW_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_RAW_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_RAW_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_RAW_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(11)) #define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 6 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(10)) #define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 5 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(9)) #define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 4 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(8)) #define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 3 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(7)) #define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 2 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(6)) #define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 1 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(5)) #define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel 0 duty change done.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(4)) #define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 7 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 6 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 5 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 4 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 3 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 2 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 1 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel 0 duty change done.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 -/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel3 counter overflow.*/ -#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 4 +/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(3)) #define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_RAW_S 7 -/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel2 counter overflow.*/ -#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) +#define LEDC_LSTIMER3_OVF_INT_RAW_S 3 +/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(2)) #define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_RAW_S 6 -/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel1 counter overflow.*/ -#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) +#define LEDC_LSTIMER2_OVF_INT_RAW_S 2 +/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(1)) #define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_RAW_S 5 -/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for low speed channel0 counter overflow.*/ -#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) +#define LEDC_LSTIMER1_OVF_INT_RAW_S 1 +/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(0)) #define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_RAW_S 4 -/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel3 counter overflow.*/ -#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_RAW_S 3 -/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel2 counter overflow.*/ -#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_RAW_S 2 -/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel1 counter overflow.*/ -#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_RAW_S 1 -/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for high speed channel0 counter overflow.*/ -#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_RAW_S 0 +#define LEDC_LSTIMER0_OVF_INT_RAW_S 0 -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The interrupt status bit for low speed channel 7 duty change done event*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x00c4) +/* LEDC_OVF_CNT_LSCH7_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_ST (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ST_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_ST_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_ST (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ST_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_ST_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ST_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_ST_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ST_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_ST_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ST_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_ST_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ST_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_ST_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ST_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_ST_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ST_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_ST_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(11)) #define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 6 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(10)) #define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 5 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(9)) #define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 4 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(8)) #define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 3 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(7)) #define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 2 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(6)) #define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 1 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(5)) #define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel 0 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(4)) #define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 7 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 6 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 5 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 4 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 3 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 2 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 1 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel 0 duty change done event.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 -/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel3 counter overflow event.*/ -#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 4 +/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(3)) #define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ST_S 7 -/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel2 counter overflow event.*/ -#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) +#define LEDC_LSTIMER3_OVF_INT_ST_S 3 +/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(2)) #define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ST_S 6 -/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel1 counter overflow event.*/ -#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) +#define LEDC_LSTIMER2_OVF_INT_ST_S 2 +/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(1)) #define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ST_S 5 -/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt status bit for low speed channel0 counter overflow event.*/ -#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) +#define LEDC_LSTIMER1_OVF_INT_ST_S 1 +/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(0)) #define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ST_S 4 -/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel3 counter overflow event.*/ -#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_ST_S 3 -/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel2 counter overflow event.*/ -#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_ST_S 2 -/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel1 counter overflow event.*/ -#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_ST_S 1 -/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt status bit for high speed channel0 counter overflow event.*/ -#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_ST_S 0 +#define LEDC_LSTIMER0_OVF_INT_ST_S 0 -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ -/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x00c8) +/* LEDC_OVF_CNT_LSCH7_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_ENA (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ENA_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_ENA_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_ENA (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ENA_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_ENA_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ENA_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_ENA_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ENA_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_ENA_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ENA_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_ENA_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ENA_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_ENA_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ENA_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_ENA_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ENA_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_ENA_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(11)) #define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(10)) #define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(9)) #define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(8)) #define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(7)) #define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(6)) #define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(5)) #define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(4)) #define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 -/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ -#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 4 +/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(3)) #define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_ENA_S 7 -/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ -#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) +#define LEDC_LSTIMER3_OVF_INT_ENA_S 3 +/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(2)) #define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_ENA_S 6 -/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ -#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) +#define LEDC_LSTIMER2_OVF_INT_ENA_S 2 +/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(1)) #define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_ENA_S 5 -/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ -#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) +#define LEDC_LSTIMER1_OVF_INT_ENA_S 1 +/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(0)) #define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_ENA_S 4 -/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ -#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_ENA_S 3 -/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ -#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_ENA_S 2 -/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ -#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_ENA_S 1 -/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ -#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_ENA_S 0 +#define LEDC_LSTIMER0_OVF_INT_ENA_S 0 -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) -/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ -/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x00cC) +/* LEDC_OVF_CNT_LSCH7_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_CLR (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_CLR_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_CLR_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_CLR (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_CLR_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_CLR_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_CLR_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_CLR_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_CLR_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_CLR_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_CLR_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_CLR_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_CLR_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_CLR_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_CLR_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_CLR_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_CLR_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_CLR_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(11)) #define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 -/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(10)) #define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 -/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(9)) #define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 -/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(8)) #define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 -/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(7)) #define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 -/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(6)) #define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 -/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(5)) #define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 -/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(4)) #define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 -/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 -/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 -/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 -/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 -/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 -/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 -/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 -/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 -#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 -/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ -#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) -#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 4 +/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(3)) #define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER3_OVF_INT_CLR_S 7 -/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ -#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) -#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) +#define LEDC_LSTIMER3_OVF_INT_CLR_S 3 +/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(2)) #define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER2_OVF_INT_CLR_S 6 -/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ -#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) -#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) +#define LEDC_LSTIMER2_OVF_INT_CLR_S 2 +/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(1)) #define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER1_OVF_INT_CLR_S 5 -/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ -#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) -#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) +#define LEDC_LSTIMER1_OVF_INT_CLR_S 1 +/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(0)) #define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 -#define LEDC_LSTIMER0_OVF_INT_CLR_S 4 -/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ -#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) -#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER3_OVF_INT_CLR_S 3 -/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ -#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) -#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER2_OVF_INT_CLR_S 2 -/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ -#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) -#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER1_OVF_INT_CLR_S 1 -/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ -#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) -#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 -#define LEDC_HSTIMER0_OVF_INT_CLR_S 0 +#define LEDC_LSTIMER0_OVF_INT_CLR_S 0 -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0) /* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /*description: */ #define LEDC_APB_CLK_SEL 0x00000003 @@ -2591,400 +1553,8 @@ extern "C" { #define LEDC_APB_CLK_SEL_V 0x3 #define LEDC_APB_CLK_SEL_S 0 -#define LEDC_INT1_RAW_REG (DR_REG_LEDC_BASE + 0x0194) -/* LEDC_OVF_CNT_LSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH7_INT_RAW (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_RAW_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH7_INT_RAW_S 15 -/* LEDC_OVF_CNT_LSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH6_INT_RAW (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_RAW_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH6_INT_RAW_S 14 -/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_RAW (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_RAW_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_RAW_S 13 -/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_RAW (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_RAW_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_RAW_S 12 -/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_RAW (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_RAW_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_RAW_S 11 -/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_RAW (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_RAW_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_RAW_S 10 -/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_RAW (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_RAW_M (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_RAW_S 9 -/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_RAW (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_RAW_M (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_RAW_S 8 -/* LEDC_OVF_CNT_HSCH7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH7_INT_RAW (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_RAW_M (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH7_INT_RAW_S 7 -/* LEDC_OVF_CNT_HSCH6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH6_INT_RAW (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_RAW_M (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH6_INT_RAW_S 6 -/* LEDC_OVF_CNT_HSCH5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH5_INT_RAW (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_RAW_M (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH5_INT_RAW_S 5 -/* LEDC_OVF_CNT_HSCH4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH4_INT_RAW (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_RAW_M (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH4_INT_RAW_S 4 -/* LEDC_OVF_CNT_HSCH3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH3_INT_RAW (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_RAW_M (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH3_INT_RAW_S 3 -/* LEDC_OVF_CNT_HSCH2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH2_INT_RAW (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_RAW_M (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH2_INT_RAW_S 2 -/* LEDC_OVF_CNT_HSCH1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH1_INT_RAW (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_RAW_M (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH1_INT_RAW_S 1 -/* LEDC_OVF_CNT_HSCH0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH0_INT_RAW (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_RAW_M (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_RAW_V 0x1 -#define LEDC_OVF_CNT_HSCH0_INT_RAW_S 0 - -#define LEDC_INT1_ST_REG (DR_REG_LEDC_BASE + 0x0198) -/* LEDC_OVF_CNT_LSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH7_INT_ST (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_ST_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH7_INT_ST_S 15 -/* LEDC_OVF_CNT_LSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH6_INT_ST (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_ST_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH6_INT_ST_S 14 -/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_ST (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_ST_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_ST_S 13 -/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_ST (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_ST_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_ST_S 12 -/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_ST (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_ST_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_ST_S 11 -/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_ST (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_ST_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_ST_S 10 -/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_ST (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_ST_M (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_ST_S 9 -/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_ST (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_ST_M (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_ST_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_ST_S 8 -/* LEDC_OVF_CNT_HSCH7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH7_INT_ST (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_ST_M (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH7_INT_ST_S 7 -/* LEDC_OVF_CNT_HSCH6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH6_INT_ST (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_ST_M (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH6_INT_ST_S 6 -/* LEDC_OVF_CNT_HSCH5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH5_INT_ST (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_ST_M (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH5_INT_ST_S 5 -/* LEDC_OVF_CNT_HSCH4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH4_INT_ST (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_ST_M (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH4_INT_ST_S 4 -/* LEDC_OVF_CNT_HSCH3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH3_INT_ST (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_ST_M (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH3_INT_ST_S 3 -/* LEDC_OVF_CNT_HSCH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH2_INT_ST (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_ST_M (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH2_INT_ST_S 2 -/* LEDC_OVF_CNT_HSCH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH1_INT_ST (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_ST_M (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH1_INT_ST_S 1 -/* LEDC_OVF_CNT_HSCH0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH0_INT_ST (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_ST_M (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_ST_V 0x1 -#define LEDC_OVF_CNT_HSCH0_INT_ST_S 0 - -#define LEDC_INT1_ENA_REG (DR_REG_LEDC_BASE + 0x019c) -/* LEDC_OVF_CNT_LSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH7_INT_ENA (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_ENA_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH7_INT_ENA_S 15 -/* LEDC_OVF_CNT_LSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH6_INT_ENA (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_ENA_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH6_INT_ENA_S 14 -/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_ENA (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_ENA_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_ENA_S 13 -/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_ENA (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_ENA_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_ENA_S 12 -/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_ENA (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_ENA_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_ENA_S 11 -/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_ENA (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_ENA_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_ENA_S 10 -/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_ENA (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_ENA_M (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_ENA_S 9 -/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_ENA (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_ENA_M (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_ENA_S 8 -/* LEDC_OVF_CNT_HSCH7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH7_INT_ENA (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_ENA_M (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH7_INT_ENA_S 7 -/* LEDC_OVF_CNT_HSCH6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH6_INT_ENA (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_ENA_M (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH6_INT_ENA_S 6 -/* LEDC_OVF_CNT_HSCH5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH5_INT_ENA (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_ENA_M (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH5_INT_ENA_S 5 -/* LEDC_OVF_CNT_HSCH4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH4_INT_ENA (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_ENA_M (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH4_INT_ENA_S 4 -/* LEDC_OVF_CNT_HSCH3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH3_INT_ENA (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_ENA_M (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH3_INT_ENA_S 3 -/* LEDC_OVF_CNT_HSCH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH2_INT_ENA (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_ENA_M (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH2_INT_ENA_S 2 -/* LEDC_OVF_CNT_HSCH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH1_INT_ENA (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_ENA_M (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH1_INT_ENA_S 1 -/* LEDC_OVF_CNT_HSCH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH0_INT_ENA (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_ENA_M (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_ENA_V 0x1 -#define LEDC_OVF_CNT_HSCH0_INT_ENA_S 0 - -#define LEDC_INT1_CLR_REG (DR_REG_LEDC_BASE + 0x01a0) -/* LEDC_OVF_CNT_LSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH7_INT_CLR (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_CLR_M (BIT(15)) -#define LEDC_OVF_CNT_LSCH7_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH7_INT_CLR_S 15 -/* LEDC_OVF_CNT_LSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH6_INT_CLR (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_CLR_M (BIT(14)) -#define LEDC_OVF_CNT_LSCH6_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH6_INT_CLR_S 14 -/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH5_INT_CLR (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_CLR_M (BIT(13)) -#define LEDC_OVF_CNT_LSCH5_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH5_INT_CLR_S 13 -/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH4_INT_CLR (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_CLR_M (BIT(12)) -#define LEDC_OVF_CNT_LSCH4_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH4_INT_CLR_S 12 -/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH3_INT_CLR (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_CLR_M (BIT(11)) -#define LEDC_OVF_CNT_LSCH3_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH3_INT_CLR_S 11 -/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH2_INT_CLR (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_CLR_M (BIT(10)) -#define LEDC_OVF_CNT_LSCH2_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH2_INT_CLR_S 10 -/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH1_INT_CLR (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_CLR_M (BIT(9)) -#define LEDC_OVF_CNT_LSCH1_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH1_INT_CLR_S 9 -/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_LSCH0_INT_CLR (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_CLR_M (BIT(8)) -#define LEDC_OVF_CNT_LSCH0_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_LSCH0_INT_CLR_S 8 -/* LEDC_OVF_CNT_HSCH7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH7_INT_CLR (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_CLR_M (BIT(7)) -#define LEDC_OVF_CNT_HSCH7_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH7_INT_CLR_S 7 -/* LEDC_OVF_CNT_HSCH6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH6_INT_CLR (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_CLR_M (BIT(6)) -#define LEDC_OVF_CNT_HSCH6_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH6_INT_CLR_S 6 -/* LEDC_OVF_CNT_HSCH5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH5_INT_CLR (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_CLR_M (BIT(5)) -#define LEDC_OVF_CNT_HSCH5_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH5_INT_CLR_S 5 -/* LEDC_OVF_CNT_HSCH4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH4_INT_CLR (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_CLR_M (BIT(4)) -#define LEDC_OVF_CNT_HSCH4_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH4_INT_CLR_S 4 -/* LEDC_OVF_CNT_HSCH3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH3_INT_CLR (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_CLR_M (BIT(3)) -#define LEDC_OVF_CNT_HSCH3_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH3_INT_CLR_S 3 -/* LEDC_OVF_CNT_HSCH2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH2_INT_CLR (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_CLR_M (BIT(2)) -#define LEDC_OVF_CNT_HSCH2_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH2_INT_CLR_S 2 -/* LEDC_OVF_CNT_HSCH1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH1_INT_CLR (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_CLR_M (BIT(1)) -#define LEDC_OVF_CNT_HSCH1_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH1_INT_CLR_S 1 -/* LEDC_OVF_CNT_HSCH0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define LEDC_OVF_CNT_HSCH0_INT_CLR (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_CLR_M (BIT(0)) -#define LEDC_OVF_CNT_HSCH0_INT_CLR_V 0x1 -#define LEDC_OVF_CNT_HSCH0_INT_CLR_S 0 - -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) -/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18051200 ; */ +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC) +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072700 ; */ /*description: */ #define LEDC_DATE 0xFFFFFFFF #define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) @@ -2995,8 +1565,4 @@ extern "C" { } #endif - - -#endif /*_SOC_LEDC_REG_H_ */ - - +#endif /*_SOC_LEDC_REG_H_ */ \ No newline at end of file diff --git a/components/soc/esp32s2beta/include/soc/ledc_struct.h b/components/soc/esp32s2beta/include/soc/ledc_struct.h index 12e46cb861..aedaeefaf0 100644 --- a/components/soc/esp32s2beta/include/soc/ledc_struct.h +++ b/components/soc/esp32s2beta/include/soc/ledc_struct.h @@ -1,4 +1,4 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -22,43 +22,31 @@ typedef volatile struct { struct { struct { union { - struct { - uint32_t htimer_sel: 2; - uint32_t hsig_out_en: 1; - uint32_t hidle_lv: 1; - uint32_t hovf_num: 10; - uint32_t hovf_cnt_en: 1; - uint32_t reserved15: 16; - uint32_t clk_en: 1; - }; - struct { - uint32_t ltimer_sel: 2; - uint32_t lsig_out_en: 1; - uint32_t lidle_lv: 1; - uint32_t low_speed_update: 1; - uint32_t lovf_num: 10; - uint32_t lovf_cnt_en: 1; - uint32_t reserved16: 16; - }; struct { uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ - uint32_t reserved28: 28; + uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reserved for high speed timers*/ + uint32_t ovf_num: 10; + uint32_t ovf_cnt_en: 1; + uint32_t ovf_cnt_rst: 1; + uint32_t ovf_cnt_rst_st: 1; + uint32_t reserved18: 13; + uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ }; uint32_t val; } conf0; union { struct { - uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ - uint32_t reserved20: 12; + uint32_t hpoint: 14; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ + uint32_t reserved14: 16; }; uint32_t val; } hpoint; union { struct { - uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ - uint32_t reserved25: 7; + uint32_t duty: 19; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + uint32_t reserved19: 11; }; uint32_t val; } duty; @@ -74,54 +62,42 @@ typedef volatile struct { } conf1; union { struct { - uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ - uint32_t reserved25: 7; + uint32_t duty_read: 19; /*This register represents the current duty of the output signal for high speed channel.*/ + uint32_t reserved19: 11; }; uint32_t val; } duty_rd; } channel[8]; - } channel_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ + } channel_group[1]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ struct { struct { union { struct { - uint32_t duty_resolution: 5; - uint32_t clock_divider: 18; + uint32_t duty_resolution: 4; + uint32_t clock_divider: 18; uint32_t pause: 1; uint32_t rst: 1; uint32_t tick_sel: 1; uint32_t low_speed_update: 1; - uint32_t reserved27: 5; + uint32_t reserved26: 6; }; uint32_t val; } conf; union { struct { - uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ - uint32_t reserved20: 12; + uint32_t timer_cnt: 14; /*software can read this register to get the current counter value in high speed timer*/ + uint32_t reserved14: 16; }; uint32_t val; } value; } timer[4]; - } timer_group[2]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ + } timer_group[1]; /*two channel groups : 0: high-speed channels; 1: low-speed channels*/ union { struct { - uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ - uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ - uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ - uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ - uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ - uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ - uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ - uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ - uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ - uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ - uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ - uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ @@ -130,97 +106,93 @@ typedef volatile struct { uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ - uint32_t reserved24: 8; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_raw; union { struct { - uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ - uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ - uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ - uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ - uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ - uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ - uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ - uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ - uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done event.*/ - uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ - uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ - uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ - uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ - uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ - uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ - uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ - uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ - uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ - uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ - uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ - uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ - uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ - uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ - uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ - uint32_t reserved24: 8; + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_st; union { struct { - uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ - uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ - uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ - uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ - uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ - uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ - uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ - uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ - uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ - uint32_t reserved24: 8; + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_ena; union { struct { - uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ - uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ - uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ - uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ - uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ - uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ - uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ - uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ - uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ - uint32_t reserved24: 8; + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_clr; @@ -229,100 +201,8 @@ typedef volatile struct { uint32_t apb_clk_sel: 2; uint32_t reserved2: 30; }; - struct { - uint32_t slow_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz, (only used by LEDC low speed channels/timers)*/ - uint32_t reserved: 31; - }; uint32_t val; } conf; - union { - struct { - uint32_t ovf_cnt_hsch0: 1; - uint32_t ovf_cnt_hsch1: 1; - uint32_t ovf_cnt_hsch2: 1; - uint32_t ovf_cnt_hsch3: 1; - uint32_t ovf_cnt_hsch4: 1; - uint32_t ovf_cnt_hsch5: 1; - uint32_t ovf_cnt_hsch6: 1; - uint32_t ovf_cnt_hsch7: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int1_raw; - union { - struct { - uint32_t ovf_cnt_hsch0: 1; - uint32_t ovf_cnt_hsch1: 1; - uint32_t ovf_cnt_hsch2: 1; - uint32_t ovf_cnt_hsch3: 1; - uint32_t ovf_cnt_hsch4: 1; - uint32_t ovf_cnt_hsch5: 1; - uint32_t ovf_cnt_hsch6: 1; - uint32_t ovf_cnt_hsch7: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int1_st; - union { - struct { - uint32_t ovf_cnt_hsch0: 1; - uint32_t ovf_cnt_hsch1: 1; - uint32_t ovf_cnt_hsch2: 1; - uint32_t ovf_cnt_hsch3: 1; - uint32_t ovf_cnt_hsch4: 1; - uint32_t ovf_cnt_hsch5: 1; - uint32_t ovf_cnt_hsch6: 1; - uint32_t ovf_cnt_hsch7: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int1_ena; - union { - struct { - uint32_t ovf_cnt_hsch0: 1; - uint32_t ovf_cnt_hsch1: 1; - uint32_t ovf_cnt_hsch2: 1; - uint32_t ovf_cnt_hsch3: 1; - uint32_t ovf_cnt_hsch4: 1; - uint32_t ovf_cnt_hsch5: 1; - uint32_t ovf_cnt_hsch6: 1; - uint32_t ovf_cnt_hsch7: 1; - uint32_t ovf_cnt_lsch0: 1; - uint32_t ovf_cnt_lsch1: 1; - uint32_t ovf_cnt_lsch2: 1; - uint32_t ovf_cnt_lsch3: 1; - uint32_t ovf_cnt_lsch4: 1; - uint32_t ovf_cnt_lsch5: 1; - uint32_t ovf_cnt_lsch6: 1; - uint32_t ovf_cnt_lsch7: 1; - uint32_t reserved16: 16; - }; - uint32_t val; - } int1_clr; uint32_t reserved_1a4; uint32_t reserved_1a8; uint32_t reserved_1ac; diff --git a/components/soc/esp32s2beta/include/soc/pcnt_reg.h b/components/soc/esp32s2beta/include/soc/pcnt_reg.h index 38b1dd721c..f28fc40eac 100644 --- a/components/soc/esp32s2beta/include/soc/pcnt_reg.h +++ b/components/soc/esp32s2beta/include/soc/pcnt_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -21,100 +21,91 @@ extern "C" { #include "soc.h" #define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) /* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_LCTRL_MODE_U0 0x00000003 #define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S)) #define PCNT_CH1_LCTRL_MODE_U0_V 0x3 #define PCNT_CH1_LCTRL_MODE_U0_S 30 /* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_HCTRL_MODE_U0 0x00000003 #define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S)) #define PCNT_CH1_HCTRL_MODE_U0_V 0x3 #define PCNT_CH1_HCTRL_MODE_U0_S 28 /* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_POS_MODE_U0 0x00000003 #define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S)) #define PCNT_CH1_POS_MODE_U0_V 0x3 #define PCNT_CH1_POS_MODE_U0_S 26 /* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_NEG_MODE_U0 0x00000003 #define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S)) #define PCNT_CH1_NEG_MODE_U0_V 0x3 #define PCNT_CH1_NEG_MODE_U0_S 24 /* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_LCTRL_MODE_U0 0x00000003 #define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S)) #define PCNT_CH0_LCTRL_MODE_U0_V 0x3 #define PCNT_CH0_LCTRL_MODE_U0_S 22 /* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_HCTRL_MODE_U0 0x00000003 #define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S)) #define PCNT_CH0_HCTRL_MODE_U0_V 0x3 #define PCNT_CH0_HCTRL_MODE_U0_S 20 /* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_POS_MODE_U0 0x00000003 #define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S)) #define PCNT_CH0_POS_MODE_U0_V 0x3 #define PCNT_CH0_POS_MODE_U0_S 18 /* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_NEG_MODE_U0 0x00000003 #define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S)) #define PCNT_CH0_NEG_MODE_U0_V 0x3 #define PCNT_CH0_NEG_MODE_U0_S 16 /* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit0's count with thres1 value .*/ +/*description: */ #define PCNT_THR_THRES1_EN_U0 (BIT(15)) #define PCNT_THR_THRES1_EN_U0_M (BIT(15)) #define PCNT_THR_THRES1_EN_U0_V 0x1 #define PCNT_THR_THRES1_EN_U0_S 15 /* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit0's count with thres0 value.*/ +/*description: */ #define PCNT_THR_THRES0_EN_U0 (BIT(14)) #define PCNT_THR_THRES0_EN_U0_M (BIT(14)) #define PCNT_THR_THRES0_EN_U0_V 0x1 #define PCNT_THR_THRES0_EN_U0_S 14 /* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/ +/*description: */ #define PCNT_THR_L_LIM_EN_U0 (BIT(13)) #define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) #define PCNT_THR_L_LIM_EN_U0_V 0x1 #define PCNT_THR_L_LIM_EN_U0_S 13 /* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/ +/*description: */ #define PCNT_THR_H_LIM_EN_U0 (BIT(12)) #define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) #define PCNT_THR_H_LIM_EN_U0_V 0x1 #define PCNT_THR_H_LIM_EN_U0_S 12 /* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit0's count with 0 value.*/ +/*description: */ #define PCNT_THR_ZERO_EN_U0 (BIT(11)) #define PCNT_THR_ZERO_EN_U0_M (BIT(11)) #define PCNT_THR_ZERO_EN_U0_V 0x1 #define PCNT_THR_ZERO_EN_U0_S 11 /* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit0.*/ +/*description: */ #define PCNT_FILTER_EN_U0 (BIT(10)) #define PCNT_FILTER_EN_U0_M (BIT(10)) #define PCNT_FILTER_EN_U0_V 0x1 #define PCNT_FILTER_EN_U0_S 10 /* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit0.*/ +/*description: */ #define PCNT_FILTER_THRES_U0 0x000003FF #define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S)) #define PCNT_FILTER_THRES_U0_V 0x3FF @@ -122,13 +113,13 @@ extern "C" { #define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) /* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit0.*/ +/*description: */ #define PCNT_CNT_THRES1_U0 0x0000FFFF #define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S)) #define PCNT_CNT_THRES1_U0_V 0xFFFF #define PCNT_CNT_THRES1_U0_S 16 /* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit0.*/ +/*description: */ #define PCNT_CNT_THRES0_U0 0x0000FFFF #define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S)) #define PCNT_CNT_THRES0_U0_V 0xFFFF @@ -136,13 +127,13 @@ extern "C" { #define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) /* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit0.*/ +/*description: */ #define PCNT_CNT_L_LIM_U0 0x0000FFFF #define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S)) #define PCNT_CNT_L_LIM_U0_V 0xFFFF #define PCNT_CNT_L_LIM_U0_S 16 /* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit0.*/ +/*description: */ #define PCNT_CNT_H_LIM_U0 0x0000FFFF #define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S)) #define PCNT_CNT_H_LIM_U0_V 0xFFFF @@ -150,100 +141,91 @@ extern "C" { #define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) /* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_LCTRL_MODE_U1 0x00000003 #define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S)) #define PCNT_CH1_LCTRL_MODE_U1_V 0x3 #define PCNT_CH1_LCTRL_MODE_U1_S 30 /* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_HCTRL_MODE_U1 0x00000003 #define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S)) #define PCNT_CH1_HCTRL_MODE_U1_V 0x3 #define PCNT_CH1_HCTRL_MODE_U1_S 28 /* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_POS_MODE_U1 0x00000003 #define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S)) #define PCNT_CH1_POS_MODE_U1_V 0x3 #define PCNT_CH1_POS_MODE_U1_S 26 /* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_NEG_MODE_U1 0x00000003 #define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S)) #define PCNT_CH1_NEG_MODE_U1_V 0x3 #define PCNT_CH1_NEG_MODE_U1_S 24 /* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_LCTRL_MODE_U1 0x00000003 #define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S)) #define PCNT_CH0_LCTRL_MODE_U1_V 0x3 #define PCNT_CH0_LCTRL_MODE_U1_S 22 /* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_HCTRL_MODE_U1 0x00000003 #define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S)) #define PCNT_CH0_HCTRL_MODE_U1_V 0x3 #define PCNT_CH0_HCTRL_MODE_U1_S 20 /* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_POS_MODE_U1 0x00000003 #define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S)) #define PCNT_CH0_POS_MODE_U1_V 0x3 #define PCNT_CH0_POS_MODE_U1_S 18 /* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_NEG_MODE_U1 0x00000003 #define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S)) #define PCNT_CH0_NEG_MODE_U1_V 0x3 #define PCNT_CH0_NEG_MODE_U1_S 16 /* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit1's count with thres1 value .*/ +/*description: */ #define PCNT_THR_THRES1_EN_U1 (BIT(15)) #define PCNT_THR_THRES1_EN_U1_M (BIT(15)) #define PCNT_THR_THRES1_EN_U1_V 0x1 #define PCNT_THR_THRES1_EN_U1_S 15 /* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit1's count with thres0 value.*/ +/*description: */ #define PCNT_THR_THRES0_EN_U1 (BIT(14)) #define PCNT_THR_THRES0_EN_U1_M (BIT(14)) #define PCNT_THR_THRES0_EN_U1_V 0x1 #define PCNT_THR_THRES0_EN_U1_S 14 /* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/ +/*description: */ #define PCNT_THR_L_LIM_EN_U1 (BIT(13)) #define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) #define PCNT_THR_L_LIM_EN_U1_V 0x1 #define PCNT_THR_L_LIM_EN_U1_S 13 /* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/ +/*description: */ #define PCNT_THR_H_LIM_EN_U1 (BIT(12)) #define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) #define PCNT_THR_H_LIM_EN_U1_V 0x1 #define PCNT_THR_H_LIM_EN_U1_S 12 /* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit1's count with 0 value.*/ +/*description: */ #define PCNT_THR_ZERO_EN_U1 (BIT(11)) #define PCNT_THR_ZERO_EN_U1_M (BIT(11)) #define PCNT_THR_ZERO_EN_U1_V 0x1 #define PCNT_THR_ZERO_EN_U1_S 11 /* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit1.*/ +/*description: */ #define PCNT_FILTER_EN_U1 (BIT(10)) #define PCNT_FILTER_EN_U1_M (BIT(10)) #define PCNT_FILTER_EN_U1_V 0x1 #define PCNT_FILTER_EN_U1_S 10 /* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit1.*/ +/*description: */ #define PCNT_FILTER_THRES_U1 0x000003FF #define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S)) #define PCNT_FILTER_THRES_U1_V 0x3FF @@ -251,13 +233,13 @@ extern "C" { #define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) /* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit1.*/ +/*description: */ #define PCNT_CNT_THRES1_U1 0x0000FFFF #define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S)) #define PCNT_CNT_THRES1_U1_V 0xFFFF #define PCNT_CNT_THRES1_U1_S 16 /* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit1.*/ +/*description: */ #define PCNT_CNT_THRES0_U1 0x0000FFFF #define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S)) #define PCNT_CNT_THRES0_U1_V 0xFFFF @@ -265,13 +247,13 @@ extern "C" { #define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) /* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit1.*/ +/*description: */ #define PCNT_CNT_L_LIM_U1 0x0000FFFF #define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S)) #define PCNT_CNT_L_LIM_U1_V 0xFFFF #define PCNT_CNT_L_LIM_U1_S 16 /* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit1.*/ +/*description: */ #define PCNT_CNT_H_LIM_U1 0x0000FFFF #define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S)) #define PCNT_CNT_H_LIM_U1_V 0xFFFF @@ -279,100 +261,91 @@ extern "C" { #define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) /* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_LCTRL_MODE_U2 0x00000003 #define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S)) #define PCNT_CH1_LCTRL_MODE_U2_V 0x3 #define PCNT_CH1_LCTRL_MODE_U2_S 30 /* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_HCTRL_MODE_U2 0x00000003 #define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S)) #define PCNT_CH1_HCTRL_MODE_U2_V 0x3 #define PCNT_CH1_HCTRL_MODE_U2_S 28 /* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_POS_MODE_U2 0x00000003 #define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S)) #define PCNT_CH1_POS_MODE_U2_V 0x3 #define PCNT_CH1_POS_MODE_U2_S 26 /* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_NEG_MODE_U2 0x00000003 #define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S)) #define PCNT_CH1_NEG_MODE_U2_V 0x3 #define PCNT_CH1_NEG_MODE_U2_S 24 /* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_LCTRL_MODE_U2 0x00000003 #define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S)) #define PCNT_CH0_LCTRL_MODE_U2_V 0x3 #define PCNT_CH0_LCTRL_MODE_U2_S 22 /* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_HCTRL_MODE_U2 0x00000003 #define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S)) #define PCNT_CH0_HCTRL_MODE_U2_V 0x3 #define PCNT_CH0_HCTRL_MODE_U2_S 20 /* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_POS_MODE_U2 0x00000003 #define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S)) #define PCNT_CH0_POS_MODE_U2_V 0x3 #define PCNT_CH0_POS_MODE_U2_S 18 /* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_NEG_MODE_U2 0x00000003 #define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S)) #define PCNT_CH0_NEG_MODE_U2_V 0x3 #define PCNT_CH0_NEG_MODE_U2_S 16 /* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit2's count with thres1 value .*/ +/*description: */ #define PCNT_THR_THRES1_EN_U2 (BIT(15)) #define PCNT_THR_THRES1_EN_U2_M (BIT(15)) #define PCNT_THR_THRES1_EN_U2_V 0x1 #define PCNT_THR_THRES1_EN_U2_S 15 /* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit2's count with thres0 value.*/ +/*description: */ #define PCNT_THR_THRES0_EN_U2 (BIT(14)) #define PCNT_THR_THRES0_EN_U2_M (BIT(14)) #define PCNT_THR_THRES0_EN_U2_V 0x1 #define PCNT_THR_THRES0_EN_U2_S 14 /* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/ +/*description: */ #define PCNT_THR_L_LIM_EN_U2 (BIT(13)) #define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) #define PCNT_THR_L_LIM_EN_U2_V 0x1 #define PCNT_THR_L_LIM_EN_U2_S 13 /* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/ +/*description: */ #define PCNT_THR_H_LIM_EN_U2 (BIT(12)) #define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) #define PCNT_THR_H_LIM_EN_U2_V 0x1 #define PCNT_THR_H_LIM_EN_U2_S 12 /* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit2's count with 0 value.*/ +/*description: */ #define PCNT_THR_ZERO_EN_U2 (BIT(11)) #define PCNT_THR_ZERO_EN_U2_M (BIT(11)) #define PCNT_THR_ZERO_EN_U2_V 0x1 #define PCNT_THR_ZERO_EN_U2_S 11 /* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit2.*/ +/*description: */ #define PCNT_FILTER_EN_U2 (BIT(10)) #define PCNT_FILTER_EN_U2_M (BIT(10)) #define PCNT_FILTER_EN_U2_V 0x1 #define PCNT_FILTER_EN_U2_S 10 /* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit2.*/ +/*description: */ #define PCNT_FILTER_THRES_U2 0x000003FF #define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S)) #define PCNT_FILTER_THRES_U2_V 0x3FF @@ -380,13 +353,13 @@ extern "C" { #define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) /* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit2.*/ +/*description: */ #define PCNT_CNT_THRES1_U2 0x0000FFFF #define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S)) #define PCNT_CNT_THRES1_U2_V 0xFFFF #define PCNT_CNT_THRES1_U2_S 16 /* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit2.*/ +/*description: */ #define PCNT_CNT_THRES0_U2 0x0000FFFF #define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S)) #define PCNT_CNT_THRES0_U2_V 0xFFFF @@ -394,13 +367,13 @@ extern "C" { #define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) /* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit2.*/ +/*description: */ #define PCNT_CNT_L_LIM_U2 0x0000FFFF #define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S)) #define PCNT_CNT_L_LIM_U2_V 0xFFFF #define PCNT_CNT_L_LIM_U2_S 16 /* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit2.*/ +/*description: */ #define PCNT_CNT_H_LIM_U2 0x0000FFFF #define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S)) #define PCNT_CNT_H_LIM_U2_V 0xFFFF @@ -408,100 +381,91 @@ extern "C" { #define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) /* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_LCTRL_MODE_U3 0x00000003 #define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S)) #define PCNT_CH1_LCTRL_MODE_U3_V 0x3 #define PCNT_CH1_LCTRL_MODE_U3_S 30 /* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH1_HCTRL_MODE_U3 0x00000003 #define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S)) #define PCNT_CH1_HCTRL_MODE_U3_V 0x3 #define PCNT_CH1_HCTRL_MODE_U3_S 28 /* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_POS_MODE_U3 0x00000003 #define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S)) #define PCNT_CH1_POS_MODE_U3_V 0x3 #define PCNT_CH1_POS_MODE_U3_S 26 /* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH1_NEG_MODE_U3 0x00000003 #define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S)) #define PCNT_CH1_NEG_MODE_U3_V 0x3 #define PCNT_CH1_NEG_MODE_U3_S 24 /* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_LCTRL_MODE_U3 0x00000003 #define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S)) #define PCNT_CH0_LCTRL_MODE_U3_V 0x3 #define PCNT_CH0_LCTRL_MODE_U3_S 22 /* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ +/*description: */ #define PCNT_CH0_HCTRL_MODE_U3 0x00000003 #define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S)) #define PCNT_CH0_HCTRL_MODE_U3_V 0x3 #define PCNT_CH0_HCTRL_MODE_U3_S 20 /* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_POS_MODE_U3 0x00000003 #define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S)) #define PCNT_CH0_POS_MODE_U3_V 0x3 #define PCNT_CH0_POS_MODE_U3_S 18 /* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ +/*description: */ #define PCNT_CH0_NEG_MODE_U3 0x00000003 #define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S)) #define PCNT_CH0_NEG_MODE_U3_V 0x3 #define PCNT_CH0_NEG_MODE_U3_S 16 /* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit3's count with thres1 value .*/ +/*description: */ #define PCNT_THR_THRES1_EN_U3 (BIT(15)) #define PCNT_THR_THRES1_EN_U3_M (BIT(15)) #define PCNT_THR_THRES1_EN_U3_V 0x1 #define PCNT_THR_THRES1_EN_U3_S 15 /* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit3's count with thres0 value.*/ +/*description: */ #define PCNT_THR_THRES0_EN_U3 (BIT(14)) #define PCNT_THR_THRES0_EN_U3_M (BIT(14)) #define PCNT_THR_THRES0_EN_U3_V 0x1 #define PCNT_THR_THRES0_EN_U3_S 14 /* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/ +/*description: */ #define PCNT_THR_L_LIM_EN_U3 (BIT(13)) #define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) #define PCNT_THR_L_LIM_EN_U3_V 0x1 #define PCNT_THR_L_LIM_EN_U3_S 13 /* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/ +/*description: */ #define PCNT_THR_H_LIM_EN_U3 (BIT(12)) #define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) #define PCNT_THR_H_LIM_EN_U3_V 0x1 #define PCNT_THR_H_LIM_EN_U3_S 12 /* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit3's count with 0 value.*/ +/*description: */ #define PCNT_THR_ZERO_EN_U3 (BIT(11)) #define PCNT_THR_ZERO_EN_U3_M (BIT(11)) #define PCNT_THR_ZERO_EN_U3_V 0x1 #define PCNT_THR_ZERO_EN_U3_S 11 /* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit3.*/ +/*description: */ #define PCNT_FILTER_EN_U3 (BIT(10)) #define PCNT_FILTER_EN_U3_M (BIT(10)) #define PCNT_FILTER_EN_U3_V 0x1 #define PCNT_FILTER_EN_U3_S 10 /* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit3.*/ +/*description: */ #define PCNT_FILTER_THRES_U3 0x000003FF #define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S)) #define PCNT_FILTER_THRES_U3_V 0x3FF @@ -509,13 +473,13 @@ extern "C" { #define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) /* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit3.*/ +/*description: */ #define PCNT_CNT_THRES1_U3 0x0000FFFF #define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S)) #define PCNT_CNT_THRES1_U3_V 0xFFFF #define PCNT_CNT_THRES1_U3_S 16 /* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit3.*/ +/*description: */ #define PCNT_CNT_THRES0_U3 0x0000FFFF #define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S)) #define PCNT_CNT_THRES0_U3_V 0xFFFF @@ -523,535 +487,19 @@ extern "C" { #define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) /* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit3.*/ +/*description: */ #define PCNT_CNT_L_LIM_U3 0x0000FFFF #define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S)) #define PCNT_CNT_L_LIM_U3_V 0xFFFF #define PCNT_CNT_L_LIM_U3_S 16 /* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit3.*/ +/*description: */ #define PCNT_CNT_H_LIM_U3 0x0000FFFF #define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S)) #define PCNT_CNT_H_LIM_U3_V 0xFFFF #define PCNT_CNT_H_LIM_U3_S 0 -#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030) -/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U4 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S)) -#define PCNT_CH1_LCTRL_MODE_U4_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U4_S 30 -/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U4 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S)) -#define PCNT_CH1_HCTRL_MODE_U4_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U4_S 28 -/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U4 0x00000003 -#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S)) -#define PCNT_CH1_POS_MODE_U4_V 0x3 -#define PCNT_CH1_POS_MODE_U4_S 26 -/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U4 0x00000003 -#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S)) -#define PCNT_CH1_NEG_MODE_U4_V 0x3 -#define PCNT_CH1_NEG_MODE_U4_S 24 -/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U4 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S)) -#define PCNT_CH0_LCTRL_MODE_U4_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U4_S 22 -/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U4 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S)) -#define PCNT_CH0_HCTRL_MODE_U4_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U4_S 20 -/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U4 0x00000003 -#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S)) -#define PCNT_CH0_POS_MODE_U4_V 0x3 -#define PCNT_CH0_POS_MODE_U4_S 18 -/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U4 0x00000003 -#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S)) -#define PCNT_CH0_NEG_MODE_U4_V 0x3 -#define PCNT_CH0_NEG_MODE_U4_S 16 -/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit4's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U4 (BIT(15)) -#define PCNT_THR_THRES1_EN_U4_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U4_V 0x1 -#define PCNT_THR_THRES1_EN_U4_S 15 -/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit4's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U4 (BIT(14)) -#define PCNT_THR_THRES0_EN_U4_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U4_V 0x1 -#define PCNT_THR_THRES0_EN_U4_S 14 -/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U4 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U4_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U4_V 0x1 -#define PCNT_THR_L_LIM_EN_U4_S 13 -/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U4 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U4_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U4_V 0x1 -#define PCNT_THR_H_LIM_EN_U4_S 12 -/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit4's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U4 (BIT(11)) -#define PCNT_THR_ZERO_EN_U4_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U4_V 0x1 -#define PCNT_THR_ZERO_EN_U4_S 11 -/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit4.*/ -#define PCNT_FILTER_EN_U4 (BIT(10)) -#define PCNT_FILTER_EN_U4_M (BIT(10)) -#define PCNT_FILTER_EN_U4_V 0x1 -#define PCNT_FILTER_EN_U4_S 10 -/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit4.*/ -#define PCNT_FILTER_THRES_U4 0x000003FF -#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S)) -#define PCNT_FILTER_THRES_U4_V 0x3FF -#define PCNT_FILTER_THRES_U4_S 0 - -#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034) -/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit4.*/ -#define PCNT_CNT_THRES1_U4 0x0000FFFF -#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S)) -#define PCNT_CNT_THRES1_U4_V 0xFFFF -#define PCNT_CNT_THRES1_U4_S 16 -/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit4.*/ -#define PCNT_CNT_THRES0_U4 0x0000FFFF -#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S)) -#define PCNT_CNT_THRES0_U4_V 0xFFFF -#define PCNT_CNT_THRES0_U4_S 0 - -#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038) -/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit4.*/ -#define PCNT_CNT_L_LIM_U4 0x0000FFFF -#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S)) -#define PCNT_CNT_L_LIM_U4_V 0xFFFF -#define PCNT_CNT_L_LIM_U4_S 16 -/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit4.*/ -#define PCNT_CNT_H_LIM_U4 0x0000FFFF -#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S)) -#define PCNT_CNT_H_LIM_U4_V 0xFFFF -#define PCNT_CNT_H_LIM_U4_S 0 - -#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c) -/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U5 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S)) -#define PCNT_CH1_LCTRL_MODE_U5_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U5_S 30 -/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U5 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S)) -#define PCNT_CH1_HCTRL_MODE_U5_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U5_S 28 -/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U5 0x00000003 -#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S)) -#define PCNT_CH1_POS_MODE_U5_V 0x3 -#define PCNT_CH1_POS_MODE_U5_S 26 -/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U5 0x00000003 -#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S)) -#define PCNT_CH1_NEG_MODE_U5_V 0x3 -#define PCNT_CH1_NEG_MODE_U5_S 24 -/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U5 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S)) -#define PCNT_CH0_LCTRL_MODE_U5_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U5_S 22 -/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U5 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S)) -#define PCNT_CH0_HCTRL_MODE_U5_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U5_S 20 -/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U5 0x00000003 -#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S)) -#define PCNT_CH0_POS_MODE_U5_V 0x3 -#define PCNT_CH0_POS_MODE_U5_S 18 -/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U5 0x00000003 -#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S)) -#define PCNT_CH0_NEG_MODE_U5_V 0x3 -#define PCNT_CH0_NEG_MODE_U5_S 16 -/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit5's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U5 (BIT(15)) -#define PCNT_THR_THRES1_EN_U5_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U5_V 0x1 -#define PCNT_THR_THRES1_EN_U5_S 15 -/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit5's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U5 (BIT(14)) -#define PCNT_THR_THRES0_EN_U5_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U5_V 0x1 -#define PCNT_THR_THRES0_EN_U5_S 14 -/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U5 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U5_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U5_V 0x1 -#define PCNT_THR_L_LIM_EN_U5_S 13 -/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U5 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U5_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U5_V 0x1 -#define PCNT_THR_H_LIM_EN_U5_S 12 -/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit5's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U5 (BIT(11)) -#define PCNT_THR_ZERO_EN_U5_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U5_V 0x1 -#define PCNT_THR_ZERO_EN_U5_S 11 -/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit5.*/ -#define PCNT_FILTER_EN_U5 (BIT(10)) -#define PCNT_FILTER_EN_U5_M (BIT(10)) -#define PCNT_FILTER_EN_U5_V 0x1 -#define PCNT_FILTER_EN_U5_S 10 -/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit5.*/ -#define PCNT_FILTER_THRES_U5 0x000003FF -#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S)) -#define PCNT_FILTER_THRES_U5_V 0x3FF -#define PCNT_FILTER_THRES_U5_S 0 - -#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040) -/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit5.*/ -#define PCNT_CNT_THRES1_U5 0x0000FFFF -#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S)) -#define PCNT_CNT_THRES1_U5_V 0xFFFF -#define PCNT_CNT_THRES1_U5_S 16 -/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit5.*/ -#define PCNT_CNT_THRES0_U5 0x0000FFFF -#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S)) -#define PCNT_CNT_THRES0_U5_V 0xFFFF -#define PCNT_CNT_THRES0_U5_S 0 - -#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044) -/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit5.*/ -#define PCNT_CNT_L_LIM_U5 0x0000FFFF -#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S)) -#define PCNT_CNT_L_LIM_U5_V 0xFFFF -#define PCNT_CNT_L_LIM_U5_S 16 -/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit5.*/ -#define PCNT_CNT_H_LIM_U5 0x0000FFFF -#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S)) -#define PCNT_CNT_H_LIM_U5_V 0xFFFF -#define PCNT_CNT_H_LIM_U5_S 0 - -#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048) -/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U6 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S)) -#define PCNT_CH1_LCTRL_MODE_U6_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U6_S 30 -/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U6 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S)) -#define PCNT_CH1_HCTRL_MODE_U6_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U6_S 28 -/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U6 0x00000003 -#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S)) -#define PCNT_CH1_POS_MODE_U6_V 0x3 -#define PCNT_CH1_POS_MODE_U6_S 26 -/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U6 0x00000003 -#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S)) -#define PCNT_CH1_NEG_MODE_U6_V 0x3 -#define PCNT_CH1_NEG_MODE_U6_S 24 -/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U6 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S)) -#define PCNT_CH0_LCTRL_MODE_U6_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U6_S 22 -/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U6 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S)) -#define PCNT_CH0_HCTRL_MODE_U6_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U6_S 20 -/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U6 0x00000003 -#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S)) -#define PCNT_CH0_POS_MODE_U6_V 0x3 -#define PCNT_CH0_POS_MODE_U6_S 18 -/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U6 0x00000003 -#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S)) -#define PCNT_CH0_NEG_MODE_U6_V 0x3 -#define PCNT_CH0_NEG_MODE_U6_S 16 -/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit6's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U6 (BIT(15)) -#define PCNT_THR_THRES1_EN_U6_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U6_V 0x1 -#define PCNT_THR_THRES1_EN_U6_S 15 -/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit6's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U6 (BIT(14)) -#define PCNT_THR_THRES0_EN_U6_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U6_V 0x1 -#define PCNT_THR_THRES0_EN_U6_S 14 -/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U6 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U6_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U6_V 0x1 -#define PCNT_THR_L_LIM_EN_U6_S 13 -/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U6 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U6_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U6_V 0x1 -#define PCNT_THR_H_LIM_EN_U6_S 12 -/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit6's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U6 (BIT(11)) -#define PCNT_THR_ZERO_EN_U6_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U6_V 0x1 -#define PCNT_THR_ZERO_EN_U6_S 11 -/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit6.*/ -#define PCNT_FILTER_EN_U6 (BIT(10)) -#define PCNT_FILTER_EN_U6_M (BIT(10)) -#define PCNT_FILTER_EN_U6_V 0x1 -#define PCNT_FILTER_EN_U6_S 10 -/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit6.*/ -#define PCNT_FILTER_THRES_U6 0x000003FF -#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S)) -#define PCNT_FILTER_THRES_U6_V 0x3FF -#define PCNT_FILTER_THRES_U6_S 0 - -#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c) -/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit6.*/ -#define PCNT_CNT_THRES1_U6 0x0000FFFF -#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S)) -#define PCNT_CNT_THRES1_U6_V 0xFFFF -#define PCNT_CNT_THRES1_U6_S 16 -/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit6.*/ -#define PCNT_CNT_THRES0_U6 0x0000FFFF -#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S)) -#define PCNT_CNT_THRES0_U6_V 0xFFFF -#define PCNT_CNT_THRES0_U6_S 0 - -#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050) -/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit6.*/ -#define PCNT_CNT_L_LIM_U6 0x0000FFFF -#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S)) -#define PCNT_CNT_L_LIM_U6_V 0xFFFF -#define PCNT_CNT_L_LIM_U6_S 16 -/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit6.*/ -#define PCNT_CNT_H_LIM_U6 0x0000FFFF -#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S)) -#define PCNT_CNT_H_LIM_U6_V 0xFFFF -#define PCNT_CNT_H_LIM_U6_S 0 - -#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054) -/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's low control - signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_LCTRL_MODE_U7 0x00000003 -#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S)) -#define PCNT_CH1_LCTRL_MODE_U7_V 0x3 -#define PCNT_CH1_LCTRL_MODE_U7_S 30 -/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's high - control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH1_HCTRL_MODE_U7 0x00000003 -#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S)) -#define PCNT_CH1_HCTRL_MODE_U7_V 0x3 -#define PCNT_CH1_HCTRL_MODE_U7_S 28 -/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH1_POS_MODE_U7 0x00000003 -#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S)) -#define PCNT_CH1_POS_MODE_U7_V 0x3 -#define PCNT_CH1_POS_MODE_U7_S 26 -/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel1's input - negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH1_NEG_MODE_U7 0x00000003 -#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S)) -#define PCNT_CH1_NEG_MODE_U7_V 0x3 -#define PCNT_CH1_NEG_MODE_U7_S 24 -/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's low control - signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_LCTRL_MODE_U7 0x00000003 -#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S)) -#define PCNT_CH0_LCTRL_MODE_U7_V 0x3 -#define PCNT_CH0_LCTRL_MODE_U7_S 22 -/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's high - control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/ -#define PCNT_CH0_HCTRL_MODE_U7 0x00000003 -#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S)) -#define PCNT_CH0_HCTRL_MODE_U7_V 0x3 -#define PCNT_CH0_HCTRL_MODE_U7_S 20 -/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ -#define PCNT_CH0_POS_MODE_U7 0x00000003 -#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S)) -#define PCNT_CH0_POS_MODE_U7_V 0x3 -#define PCNT_CH0_POS_MODE_U7_S 18 -/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: This register is used to control the mode of channel0's input - negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ -#define PCNT_CH0_NEG_MODE_U7 0x00000003 -#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S)) -#define PCNT_CH0_NEG_MODE_U7_V 0x3 -#define PCNT_CH0_NEG_MODE_U7_S 16 -/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit7's count with thres1 value .*/ -#define PCNT_THR_THRES1_EN_U7 (BIT(15)) -#define PCNT_THR_THRES1_EN_U7_M (BIT(15)) -#define PCNT_THR_THRES1_EN_U7_V 0x1 -#define PCNT_THR_THRES1_EN_U7_S 15 -/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit for comparing unit7's count with thres0 value.*/ -#define PCNT_THR_THRES0_EN_U7 (BIT(14)) -#define PCNT_THR_THRES0_EN_U7_M (BIT(14)) -#define PCNT_THR_THRES0_EN_U7_V 0x1 -#define PCNT_THR_THRES0_EN_U7_S 14 -/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/ -#define PCNT_THR_L_LIM_EN_U7 (BIT(13)) -#define PCNT_THR_L_LIM_EN_U7_M (BIT(13)) -#define PCNT_THR_L_LIM_EN_U7_V 0x1 -#define PCNT_THR_L_LIM_EN_U7_S 13 -/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/ -#define PCNT_THR_H_LIM_EN_U7 (BIT(12)) -#define PCNT_THR_H_LIM_EN_U7_M (BIT(12)) -#define PCNT_THR_H_LIM_EN_U7_V 0x1 -#define PCNT_THR_H_LIM_EN_U7_S 12 -/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: This is the enable bit for comparing unit7's count with 0 value.*/ -#define PCNT_THR_ZERO_EN_U7 (BIT(11)) -#define PCNT_THR_ZERO_EN_U7_M (BIT(11)) -#define PCNT_THR_ZERO_EN_U7_V 0x1 -#define PCNT_THR_ZERO_EN_U7_S 11 -/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: This is the enable bit for filtering input signals for unit7.*/ -#define PCNT_FILTER_EN_U7 (BIT(10)) -#define PCNT_FILTER_EN_U7_M (BIT(10)) -#define PCNT_FILTER_EN_U7_V 0x1 -#define PCNT_FILTER_EN_U7_S 10 -/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ -/*description: This register is used to filter pluse whose width is smaller - than this value for unit7.*/ -#define PCNT_FILTER_THRES_U7 0x000003FF -#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S)) -#define PCNT_FILTER_THRES_U7_V 0x3FF -#define PCNT_FILTER_THRES_U7_S 0 - -#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058) -/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to configure thres1 value for unit7.*/ -#define PCNT_CNT_THRES1_U7 0x0000FFFF -#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S)) -#define PCNT_CNT_THRES1_U7_V 0xFFFF -#define PCNT_CNT_THRES1_U7_S 16 -/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thres0 value for unit7.*/ -#define PCNT_CNT_THRES0_U7 0x0000FFFF -#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S)) -#define PCNT_CNT_THRES0_U7_V 0xFFFF -#define PCNT_CNT_THRES0_U7_S 0 - -#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c) -/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ -/*description: This register is used to confiugre thr_l_lim value for unit7.*/ -#define PCNT_CNT_L_LIM_U7 0x0000FFFF -#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S)) -#define PCNT_CNT_L_LIM_U7_V 0xFFFF -#define PCNT_CNT_L_LIM_U7_S 16 -/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ -/*description: This register is used to configure thr_h_lim value for unit7.*/ -#define PCNT_CNT_H_LIM_U7 0x0000FFFF -#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S)) -#define PCNT_CNT_H_LIM_U7_V 0xFFFF -#define PCNT_CNT_H_LIM_U7_S 0 - -#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060) +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0030) /* PCNT_PULSE_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: */ #define PCNT_PULSE_CNT_U0 0x0000FFFF @@ -1059,7 +507,7 @@ extern "C" { #define PCNT_PULSE_CNT_U0_V 0xFFFF #define PCNT_PULSE_CNT_U0_S 0 -#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064) +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0034) /* PCNT_PULSE_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: */ #define PCNT_PULSE_CNT_U1 0x0000FFFF @@ -1067,7 +515,7 @@ extern "C" { #define PCNT_PULSE_CNT_U1_V 0xFFFF #define PCNT_PULSE_CNT_U1_S 0 -#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068) +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0038) /* PCNT_PULSE_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: */ #define PCNT_PULSE_CNT_U2 0x0000FFFF @@ -1075,7 +523,7 @@ extern "C" { #define PCNT_PULSE_CNT_U2_V 0xFFFF #define PCNT_PULSE_CNT_U2_S 0 -#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c) +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x003c) /* PCNT_PULSE_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: */ #define PCNT_PULSE_CNT_U3 0x0000FFFF @@ -1083,240 +531,112 @@ extern "C" { #define PCNT_PULSE_CNT_U3_V 0xFFFF #define PCNT_PULSE_CNT_U3_S 0 -#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070) -/* PCNT_PULSE_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U4 0x0000FFFF -#define PCNT_PULSE_CNT_U4_M ((PCNT_PULSE_CNT_U4_V)<<(PCNT_PULSE_CNT_U4_S)) -#define PCNT_PULSE_CNT_U4_V 0xFFFF -#define PCNT_PULSE_CNT_U4_S 0 - -#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074) -/* PCNT_PULSE_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U5 0x0000FFFF -#define PCNT_PULSE_CNT_U5_M ((PCNT_PULSE_CNT_U5_V)<<(PCNT_PULSE_CNT_U5_S)) -#define PCNT_PULSE_CNT_U5_V 0xFFFF -#define PCNT_PULSE_CNT_U5_S 0 - -#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078) -/* PCNT_PULSE_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U6 0x0000FFFF -#define PCNT_PULSE_CNT_U6_M ((PCNT_PULSE_CNT_U6_V)<<(PCNT_PULSE_CNT_U6_S)) -#define PCNT_PULSE_CNT_U6_V 0xFFFF -#define PCNT_PULSE_CNT_U6_S 0 - -#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c) -/* PCNT_PULSE_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: */ -#define PCNT_PULSE_CNT_U7 0x0000FFFF -#define PCNT_PULSE_CNT_U7_M ((PCNT_PULSE_CNT_U7_V)<<(PCNT_PULSE_CNT_U7_S)) -#define PCNT_PULSE_CNT_U7_V 0xFFFF -#define PCNT_PULSE_CNT_U7_S 0 - -#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080) -/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4 +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0040) /* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel3 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 #define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel2 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 #define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel1 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 #define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt raw bit for channel0 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 #define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 -#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084) -/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4 +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0044) /* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel3 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 #define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel2 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 #define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel1 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 #define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt status bit for channel0 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 #define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 -#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088) -/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel7 event.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel6 event.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel5 event.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel4 event.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4 +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0048) /* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel3 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 #define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel2 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 #define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel1 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 #define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This is the interrupt enable bit for channel0 event.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 #define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 -#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c) -/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel7 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7)) -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7 -/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel6 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6)) -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6 -/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel5 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5)) -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5 -/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel4 event interrupt.*/ -#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4)) -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1 -#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4 +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x004c) /* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel3 event interrupt.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) #define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 #define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 /* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel2 event interrupt.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) #define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 #define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 /* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel1 event interrupt.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) #define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 #define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 /* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear channel0 event interrupt.*/ +/*description: */ #define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) #define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 #define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 -#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090) -/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0050) +/* PCNT_CNT_THR_ZERO_LAT_U0 : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ #define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) #define PCNT_CNT_THR_ZERO_LAT_U0_M (BIT(6)) @@ -1353,7 +673,7 @@ extern "C" { #define PCNT_CNT_THR_ZERO_MODE_U0_V 0x3 #define PCNT_CNT_THR_ZERO_MODE_U0_S 0 -#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094) +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0054) /* PCNT_CNT_THR_ZERO_LAT_U1 : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ #define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) @@ -1391,7 +711,7 @@ extern "C" { #define PCNT_CNT_THR_ZERO_MODE_U1_V 0x3 #define PCNT_CNT_THR_ZERO_MODE_U1_S 0 -#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098) +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0058) /* PCNT_CNT_THR_ZERO_LAT_U2 : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ #define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) @@ -1429,7 +749,7 @@ extern "C" { #define PCNT_CNT_THR_ZERO_MODE_U2_V 0x3 #define PCNT_CNT_THR_ZERO_MODE_U2_S 0 -#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c) +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x005c) /* PCNT_CNT_THR_ZERO_LAT_U3 : RO ;bitpos:[6] ;default: 1'b0 ; */ /*description: */ #define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) @@ -1467,215 +787,15 @@ extern "C" { #define PCNT_CNT_THR_ZERO_MODE_U3_V 0x3 #define PCNT_CNT_THR_ZERO_MODE_U3_S 0 -#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0) -/* PCNT_CNT_THR_ZERO_LAT_U4 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U4 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U4_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U4_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U4_S 6 -/* PCNT_CNT_THR_H_LIM_LAT_U4 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U4 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U4_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U4_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U4_S 5 -/* PCNT_CNT_THR_L_LIM_LAT_U4 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U4 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U4_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U4_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U4_S 4 -/* PCNT_CNT_THR_THRES0_LAT_U4 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U4 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U4_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U4_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U4_S 3 -/* PCNT_CNT_THR_THRES1_LAT_U4 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U4 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U4_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U4_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U4_S 2 -/* PCNT_CNT_THR_ZERO_MODE_U4 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U4 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U4_M ((PCNT_CNT_THR_ZERO_MODE_U4_V)<<(PCNT_CNT_THR_ZERO_MODE_U4_S)) -#define PCNT_CNT_THR_ZERO_MODE_U4_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U4_S 0 - -#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4) -/* PCNT_CNT_THR_ZERO_LAT_U5 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U5 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U5_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U5_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U5_S 6 -/* PCNT_CNT_THR_H_LIM_LAT_U5 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U5 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U5_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U5_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U5_S 5 -/* PCNT_CNT_THR_L_LIM_LAT_U5 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U5 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U5_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U5_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U5_S 4 -/* PCNT_CNT_THR_THRES0_LAT_U5 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U5 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U5_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U5_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U5_S 3 -/* PCNT_CNT_THR_THRES1_LAT_U5 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U5 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U5_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U5_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U5_S 2 -/* PCNT_CNT_THR_ZERO_MODE_U5 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U5 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U5_M ((PCNT_CNT_THR_ZERO_MODE_U5_V)<<(PCNT_CNT_THR_ZERO_MODE_U5_S)) -#define PCNT_CNT_THR_ZERO_MODE_U5_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U5_S 0 - -#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8) -/* PCNT_CNT_THR_ZERO_LAT_U6 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U6 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U6_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U6_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U6_S 6 -/* PCNT_CNT_THR_H_LIM_LAT_U6 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U6 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U6_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U6_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U6_S 5 -/* PCNT_CNT_THR_L_LIM_LAT_U6 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U6 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U6_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U6_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U6_S 4 -/* PCNT_CNT_THR_THRES0_LAT_U6 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U6 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U6_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U6_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U6_S 3 -/* PCNT_CNT_THR_THRES1_LAT_U6 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U6 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U6_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U6_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U6_S 2 -/* PCNT_CNT_THR_ZERO_MODE_U6 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U6 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U6_M ((PCNT_CNT_THR_ZERO_MODE_U6_V)<<(PCNT_CNT_THR_ZERO_MODE_U6_S)) -#define PCNT_CNT_THR_ZERO_MODE_U6_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U6_S 0 - -#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac) -/* PCNT_CNT_THR_ZERO_LAT_U7 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_LAT_U7 (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U7_M (BIT(6)) -#define PCNT_CNT_THR_ZERO_LAT_U7_V 0x1 -#define PCNT_CNT_THR_ZERO_LAT_U7_S 6 -/* PCNT_CNT_THR_H_LIM_LAT_U7 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_H_LIM_LAT_U7 (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U7_M (BIT(5)) -#define PCNT_CNT_THR_H_LIM_LAT_U7_V 0x1 -#define PCNT_CNT_THR_H_LIM_LAT_U7_S 5 -/* PCNT_CNT_THR_L_LIM_LAT_U7 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_L_LIM_LAT_U7 (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U7_M (BIT(4)) -#define PCNT_CNT_THR_L_LIM_LAT_U7_V 0x1 -#define PCNT_CNT_THR_L_LIM_LAT_U7_S 4 -/* PCNT_CNT_THR_THRES0_LAT_U7 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES0_LAT_U7 (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U7_M (BIT(3)) -#define PCNT_CNT_THR_THRES0_LAT_U7_V 0x1 -#define PCNT_CNT_THR_THRES0_LAT_U7_S 3 -/* PCNT_CNT_THR_THRES1_LAT_U7 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_THRES1_LAT_U7 (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U7_M (BIT(2)) -#define PCNT_CNT_THR_THRES1_LAT_U7_V 0x1 -#define PCNT_CNT_THR_THRES1_LAT_U7_S 2 -/* PCNT_CNT_THR_ZERO_MODE_U7 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: */ -#define PCNT_CNT_THR_ZERO_MODE_U7 0x00000003 -#define PCNT_CNT_THR_ZERO_MODE_U7_M ((PCNT_CNT_THR_ZERO_MODE_U7_V)<<(PCNT_CNT_THR_ZERO_MODE_U7_S)) -#define PCNT_CNT_THR_ZERO_MODE_U7_V 0x3 -#define PCNT_CNT_THR_ZERO_MODE_U7_S 0 - -#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0) +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x0060) /* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ /*description: */ #define PCNT_CLK_EN (BIT(16)) #define PCNT_CLK_EN_M (BIT(16)) #define PCNT_CLK_EN_V 0x1 #define PCNT_CLK_EN_S 16 -/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit7's counter.*/ -#define PCNT_CNT_PAUSE_U7 (BIT(15)) -#define PCNT_CNT_PAUSE_U7_M (BIT(15)) -#define PCNT_CNT_PAUSE_U7_V 0x1 -#define PCNT_CNT_PAUSE_U7_S 15 -/* PCNT_PULSE_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U7 (BIT(14)) -#define PCNT_PULSE_CNT_RST_U7_M (BIT(14)) -#define PCNT_PULSE_CNT_RST_U7_V 0x1 -#define PCNT_PULSE_CNT_RST_U7_S 14 -/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit6's counter.*/ -#define PCNT_CNT_PAUSE_U6 (BIT(13)) -#define PCNT_CNT_PAUSE_U6_M (BIT(13)) -#define PCNT_CNT_PAUSE_U6_V 0x1 -#define PCNT_CNT_PAUSE_U6_S 13 -/* PCNT_PULSE_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U6 (BIT(12)) -#define PCNT_PULSE_CNT_RST_U6_M (BIT(12)) -#define PCNT_PULSE_CNT_RST_U6_V 0x1 -#define PCNT_PULSE_CNT_RST_U6_S 12 -/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit5's counter.*/ -#define PCNT_CNT_PAUSE_U5 (BIT(11)) -#define PCNT_CNT_PAUSE_U5_M (BIT(11)) -#define PCNT_CNT_PAUSE_U5_V 0x1 -#define PCNT_CNT_PAUSE_U5_S 11 -/* PCNT_PULSE_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U5 (BIT(10)) -#define PCNT_PULSE_CNT_RST_U5_M (BIT(10)) -#define PCNT_PULSE_CNT_RST_U5_V 0x1 -#define PCNT_PULSE_CNT_RST_U5_S 10 -/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit4's counter.*/ -#define PCNT_CNT_PAUSE_U4 (BIT(9)) -#define PCNT_CNT_PAUSE_U4_M (BIT(9)) -#define PCNT_CNT_PAUSE_U4_V 0x1 -#define PCNT_CNT_PAUSE_U4_S 9 -/* PCNT_PULSE_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define PCNT_PULSE_CNT_RST_U4 (BIT(8)) -#define PCNT_PULSE_CNT_RST_U4_M (BIT(8)) -#define PCNT_PULSE_CNT_RST_U4_V 0x1 -#define PCNT_PULSE_CNT_RST_U4_S 8 /* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit3's counter.*/ +/*description: */ #define PCNT_CNT_PAUSE_U3 (BIT(7)) #define PCNT_CNT_PAUSE_U3_M (BIT(7)) #define PCNT_CNT_PAUSE_U3_V 0x1 @@ -1687,7 +807,7 @@ extern "C" { #define PCNT_PULSE_CNT_RST_U3_V 0x1 #define PCNT_PULSE_CNT_RST_U3_S 6 /* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit2's counter.*/ +/*description: */ #define PCNT_CNT_PAUSE_U2 (BIT(5)) #define PCNT_CNT_PAUSE_U2_M (BIT(5)) #define PCNT_CNT_PAUSE_U2_V 0x1 @@ -1699,7 +819,7 @@ extern "C" { #define PCNT_PULSE_CNT_RST_U2_V 0x1 #define PCNT_PULSE_CNT_RST_U2_S 4 /* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit1's counter.*/ +/*description: */ #define PCNT_CNT_PAUSE_U1 (BIT(3)) #define PCNT_CNT_PAUSE_U1_M (BIT(3)) #define PCNT_CNT_PAUSE_U1_V 0x1 @@ -1711,7 +831,7 @@ extern "C" { #define PCNT_PULSE_CNT_RST_U1_V 0x1 #define PCNT_PULSE_CNT_RST_U1_S 2 /* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to pause unit0's counter.*/ +/*description: */ #define PCNT_CNT_PAUSE_U0 (BIT(1)) #define PCNT_CNT_PAUSE_U0_M (BIT(1)) #define PCNT_CNT_PAUSE_U0_V 0x1 @@ -1724,7 +844,7 @@ extern "C" { #define PCNT_PULSE_CNT_RST_U0_S 0 #define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) -/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */ +/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */ /*description: */ #define PCNT_DATE 0xFFFFFFFF #define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S)) diff --git a/components/soc/esp32s2beta/include/soc/pcnt_struct.h b/components/soc/esp32s2beta/include/soc/pcnt_struct.h index 3ed0e163cc..3b986cb1bd 100644 --- a/components/soc/esp32s2beta/include/soc/pcnt_struct.h +++ b/components/soc/esp32s2beta/include/soc/pcnt_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -53,25 +53,21 @@ typedef volatile struct { }; uint32_t val; } conf2; - } conf_unit[8]; + } conf_unit[4]; union { struct { uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ uint32_t reserved16: 16; }; uint32_t val; - } cnt_unit[8]; + } cnt_unit[4]; union { struct { uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/ uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/ uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/ uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/ - uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/ - uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/ - uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/ - uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/ - uint32_t reserved8: 24; + uint32_t reserved4: 28; }; uint32_t val; } int_raw; @@ -81,11 +77,7 @@ typedef volatile struct { uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/ uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/ uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/ - uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/ - uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/ - uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/ - uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/ - uint32_t reserved8: 24; + uint32_t reserved4: 28; }; uint32_t val; } int_st; @@ -95,11 +87,7 @@ typedef volatile struct { uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/ uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/ uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/ - uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/ - uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/ - uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/ - uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/ - uint32_t reserved8: 24; + uint32_t reserved4: 28; }; uint32_t val; } int_ena; @@ -109,11 +97,7 @@ typedef volatile struct { uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/ uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/ uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/ - uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/ - uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/ - uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/ - uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/ - uint32_t reserved8: 24; + uint32_t reserved4: 28; }; uint32_t val; } int_clr; @@ -128,7 +112,7 @@ typedef volatile struct { uint32_t reserved7:25; }; uint32_t val; - } status_unit[8]; + } status_unit[4]; union { struct { uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ @@ -139,16 +123,8 @@ typedef volatile struct { uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ - uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ - uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ - uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ - uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ - uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ - uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ - uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ - uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ uint32_t clk_en: 1; - uint32_t reserved17: 15; + uint32_t reserved9: 13; }; uint32_t val; } ctrl; diff --git a/components/soc/esp32s2beta/include/soc/timer_group_reg.h b/components/soc/esp32s2beta/include/soc/timer_group_reg.h index 7e4e437fd0..1f016a96ff 100644 --- a/components/soc/esp32s2beta/include/soc/timer_group_reg.h +++ b/components/soc/esp32s2beta/include/soc/timer_group_reg.h @@ -1,4 +1,4 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. diff --git a/components/soc/esp32s2beta/include/soc/timer_group_struct.h b/components/soc/esp32s2beta/include/soc/timer_group_struct.h index ab4cb84f99..4240d41cf3 100644 --- a/components/soc/esp32s2beta/include/soc/timer_group_struct.h +++ b/components/soc/esp32s2beta/include/soc/timer_group_struct.h @@ -1,4 +1,4 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. diff --git a/components/soc/esp32s2beta/ledc_periph.c b/components/soc/esp32s2beta/ledc_periph.c new file mode 100644 index 0000000000..ce1ad7ce41 --- /dev/null +++ b/components/soc/esp32s2beta/ledc_periph.c @@ -0,0 +1,25 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; \ No newline at end of file diff --git a/components/soc/esp32s2beta/sources.cmake b/components/soc/esp32s2beta/sources.cmake index a4b5e29357..d4c8e9d528 100644 --- a/components/soc/esp32s2beta/sources.cmake +++ b/components/soc/esp32s2beta/sources.cmake @@ -7,7 +7,8 @@ set(SOC_SRCS "cpu_util.c" "rtc_sleep.c" "rtc_time.c" "soc_memory_layout.c" - "spi_periph.c") + "spi_periph.c" + "ledc_periph.c") if(NOT CMAKE_BUILD_EARLY_EXPANSION) set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES diff --git a/components/soc/include/soc/ledc_periph.h b/components/soc/include/soc/ledc_periph.h index 342e542683..9ddd5f58a5 100644 --- a/components/soc/include/soc/ledc_periph.h +++ b/components/soc/include/soc/ledc_periph.h @@ -15,3 +15,16 @@ #pragma once #include "soc/ledc_reg.h" #include "soc/ledc_struct.h" + +/* + Stores a bunch of per-ledc-peripheral data. +*/ +typedef struct { + const uint8_t sig_out0_idx; +} ledc_signal_conn_t; + +#if CONFIG_IDF_TARGET_ESP32S2BETA +extern const ledc_signal_conn_t ledc_periph_signal[1]; +#elif defined CONFIG_IDF_TARGET_ESP32 +extern const ledc_signal_conn_t ledc_periph_signal[2]; +#endif \ No newline at end of file diff --git a/examples/mesh/internal_communication/main/mesh_light.c b/examples/mesh/internal_communication/main/mesh_light.c index 58a66e1527..490fd80e0f 100644 --- a/examples/mesh/internal_communication/main/mesh_light.c +++ b/examples/mesh/internal_communication/main/mesh_light.c @@ -41,7 +41,7 @@ esp_err_t mesh_light_init(void) ledc_timer_config_t ledc_timer = { .bit_num = LEDC_TIMER_13_BIT, .freq_hz = 5000, - .speed_mode = LEDC_HIGH_SPEED_MODE, + .speed_mode = LEDC_LOW_SPEED_MODE, .timer_num = LEDC_TIMER_0 }; ledc_timer_config(&ledc_timer); @@ -51,8 +51,9 @@ esp_err_t mesh_light_init(void) .duty = 100, .gpio_num = LEDC_IO_0, .intr_type = LEDC_INTR_FADE_END, - .speed_mode = LEDC_HIGH_SPEED_MODE, - .timer_sel = LEDC_TIMER_0 + .speed_mode = LEDC_LOW_SPEED_MODE, + .timer_sel = LEDC_TIMER_0, + .hpoint = 0, }; ledc_channel_config(&ledc_channel); ledc_channel.channel = LEDC_CHANNEL_1; @@ -75,56 +76,56 @@ esp_err_t mesh_light_set(int color) switch (color) { case MESH_LIGHT_RED: /* Red */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); break; case MESH_LIGHT_GREEN: /* Green */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); break; case MESH_LIGHT_BLUE: /* Blue */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; case MESH_LIGHT_YELLOW: /* Yellow */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); break; case MESH_LIGHT_PINK: /* Pink */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; case MESH_LIGHT_INIT: /* can't say */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; case MESH_LIGHT_WARNING: /* warning */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; default: /* off */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); } - ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0); - ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1); - ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2); + ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0); + ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1); + ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2); return ESP_OK; } diff --git a/examples/mesh/manual_networking/main/mesh_light.c b/examples/mesh/manual_networking/main/mesh_light.c index 4780503817..20d5ab3a21 100644 --- a/examples/mesh/manual_networking/main/mesh_light.c +++ b/examples/mesh/manual_networking/main/mesh_light.c @@ -41,7 +41,7 @@ esp_err_t mesh_light_init(void) ledc_timer_config_t ledc_timer = { .bit_num = LEDC_TIMER_13_BIT, .freq_hz = 5000, - .speed_mode = LEDC_HIGH_SPEED_MODE, + .speed_mode = LEDC_LOW_SPEED_MODE, .timer_num = LEDC_TIMER_0 }; ledc_timer_config(&ledc_timer); @@ -51,8 +51,9 @@ esp_err_t mesh_light_init(void) .duty = 100, .gpio_num = LEDC_IO_0, .intr_type = LEDC_INTR_FADE_END, - .speed_mode = LEDC_HIGH_SPEED_MODE, - .timer_sel = LEDC_TIMER_0 + .speed_mode = LEDC_LOW_SPEED_MODE, + .timer_sel = LEDC_TIMER_0, + .hpoint = 0, }; ledc_channel_config(&ledc_channel); ledc_channel.channel = LEDC_CHANNEL_1; @@ -75,56 +76,56 @@ esp_err_t mesh_light_set(int color) switch (color) { case MESH_LIGHT_RED: /* Red */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); break; case MESH_LIGHT_GREEN: /* Green */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); break; case MESH_LIGHT_BLUE: /* Blue */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; case MESH_LIGHT_YELLOW: /* Yellow */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); break; case MESH_LIGHT_PINK: /* Pink */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; case MESH_LIGHT_INIT: /* can't say */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; case MESH_LIGHT_WARNING: /* warning */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 3000); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 3000); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 3000); break; default: /* off */ - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1, 0); - ledc_set_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 0); + ledc_set_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2, 0); } - ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_0); - ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_1); - ledc_update_duty(LEDC_HIGH_SPEED_MODE, LEDC_CHANNEL_2); + ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_0); + ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1); + ledc_update_duty(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_2); return ESP_OK; } diff --git a/examples/peripherals/ledc/main/ledc_example_main.c b/examples/peripherals/ledc/main/ledc_example_main.c index d61e73fba6..13180db592 100644 --- a/examples/peripherals/ledc/main/ledc_example_main.c +++ b/examples/peripherals/ledc/main/ledc_example_main.c @@ -33,15 +33,22 @@ * GPIO4/5 are from low speed channel group. * */ +#ifdef CONFIG_IDF_TARGET_ESP32 #define LEDC_HS_TIMER LEDC_TIMER_0 #define LEDC_HS_MODE LEDC_HIGH_SPEED_MODE #define LEDC_HS_CH0_GPIO (18) #define LEDC_HS_CH0_CHANNEL LEDC_CHANNEL_0 #define LEDC_HS_CH1_GPIO (19) #define LEDC_HS_CH1_CHANNEL LEDC_CHANNEL_1 - +#endif #define LEDC_LS_TIMER LEDC_TIMER_1 #define LEDC_LS_MODE LEDC_LOW_SPEED_MODE +#ifdef CONFIG_IDF_TARGET_ESP32S2BETA +#define LEDC_LS_CH0_GPIO (18) +#define LEDC_LS_CH0_CHANNEL LEDC_CHANNEL_0 +#define LEDC_LS_CH1_GPIO (19) +#define LEDC_LS_CH1_CHANNEL LEDC_CHANNEL_1 +#endif #define LEDC_LS_CH2_GPIO (4) #define LEDC_LS_CH2_CHANNEL LEDC_CHANNEL_2 #define LEDC_LS_CH3_GPIO (5) @@ -62,17 +69,17 @@ void app_main() ledc_timer_config_t ledc_timer = { .duty_resolution = LEDC_TIMER_13_BIT, // resolution of PWM duty .freq_hz = 5000, // frequency of PWM signal - .speed_mode = LEDC_HS_MODE, // timer mode - .timer_num = LEDC_HS_TIMER // timer index + .speed_mode = LEDC_LS_MODE, // timer mode + .timer_num = LEDC_LS_TIMER // timer index }; // Set configuration of timer0 for high speed channels ledc_timer_config(&ledc_timer); - +#ifdef CONFIG_IDF_TARGET_ESP32 // Prepare and set configuration of timer1 for low speed channels - ledc_timer.speed_mode = LEDC_LS_MODE; - ledc_timer.timer_num = LEDC_LS_TIMER; + ledc_timer.speed_mode = LEDC_HS_MODE; + ledc_timer.timer_num = LEDC_HS_TIMER; ledc_timer_config(&ledc_timer); - +#endif /* * Prepare individual configuration * for each channel of LED Controller @@ -87,6 +94,7 @@ void app_main() * will be the same */ ledc_channel_config_t ledc_channel[LEDC_TEST_CH_NUM] = { +#ifdef CONFIG_IDF_TARGET_ESP32 { .channel = LEDC_HS_CH0_CHANNEL, .duty = 0, @@ -103,6 +111,24 @@ void app_main() .hpoint = 0, .timer_sel = LEDC_HS_TIMER }, +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + { + .channel = LEDC_LS_CH0_CHANNEL, + .duty = 0, + .gpio_num = LEDC_LS_CH0_GPIO, + .speed_mode = LEDC_LS_MODE, + .hpoint = 0, + .timer_sel = LEDC_LS_TIMER + }, + { + .channel = LEDC_LS_CH1_CHANNEL, + .duty = 0, + .gpio_num = LEDC_LS_CH1_GPIO, + .speed_mode = LEDC_LS_MODE, + .hpoint = 0, + .timer_sel = LEDC_LS_TIMER + }, +#endif { .channel = LEDC_LS_CH2_CHANNEL, .duty = 0, diff --git a/examples/peripherals/pcnt/main/pcnt_example_main.c b/examples/peripherals/pcnt/main/pcnt_example_main.c index f734501fcc..cafe6a1502 100644 --- a/examples/peripherals/pcnt/main/pcnt_example_main.c +++ b/examples/peripherals/pcnt/main/pcnt_example_main.c @@ -96,7 +96,7 @@ static void ledc_init(void) { // Prepare and then apply the LEDC PWM timer configuration ledc_timer_config_t ledc_timer; - ledc_timer.speed_mode = LEDC_HIGH_SPEED_MODE; + ledc_timer.speed_mode = LEDC_LOW_SPEED_MODE; ledc_timer.timer_num = LEDC_TIMER_1; ledc_timer.duty_resolution = LEDC_TIMER_10_BIT; ledc_timer.freq_hz = 1; // set output frequency at 1 Hz @@ -104,7 +104,7 @@ static void ledc_init(void) // Prepare and then apply the LEDC PWM channel configuration ledc_channel_config_t ledc_channel; - ledc_channel.speed_mode = LEDC_HIGH_SPEED_MODE; + ledc_channel.speed_mode = LEDC_LOW_SPEED_MODE; ledc_channel.channel = LEDC_CHANNEL_1; ledc_channel.timer_sel = LEDC_TIMER_1; ledc_channel.intr_type = LEDC_INTR_DISABLE; @@ -187,19 +187,19 @@ void app_main() if (res == pdTRUE) { pcnt_get_counter_value(PCNT_TEST_UNIT, &count); printf("Event PCNT unit[%d]; cnt: %d\n", evt.unit, count); - if (evt.status & PCNT_STATUS_THRES1_M) { + if (evt.status & PCNT_EVT_THRES_1) { printf("THRES1 EVT\n"); } - if (evt.status & PCNT_STATUS_THRES0_M) { + if (evt.status & PCNT_EVT_THRES_0) { printf("THRES0 EVT\n"); } - if (evt.status & PCNT_STATUS_L_LIM_M) { + if (evt.status & PCNT_EVT_L_LIM) { printf("L_LIM EVT\n"); } - if (evt.status & PCNT_STATUS_H_LIM_M) { + if (evt.status & PCNT_EVT_H_LIM) { printf("H_LIM EVT\n"); } - if (evt.status & PCNT_STATUS_ZERO_M) { + if (evt.status & PCNT_EVT_ZERO) { printf("ZERO EVT\n"); } } else { diff --git a/examples/peripherals/timer_group/main/timer_group_example_main.c b/examples/peripherals/timer_group/main/timer_group_example_main.c index 572e35e61d..9aadc00da5 100644 --- a/examples/peripherals/timer_group/main/timer_group_example_main.c +++ b/examples/peripherals/timer_group/main/timer_group_example_main.c @@ -6,7 +6,6 @@ software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */ - #include #include "esp_types.h" #include "freertos/FreeRTOS.h" @@ -60,8 +59,13 @@ void IRAM_ATTR timer_group0_isr(void *para) /* Retrieve the interrupt status and the counter value from the timer that reported the interrupt */ +#ifdef CONFIG_IDF_TARGET_ESP32 uint32_t intr_status = TIMERG0.int_st_timers.val; TIMERG0.hw_timer[timer_idx].update = 1; +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + uint32_t intr_status = TIMERG0.int_st.val; + TIMERG0.hw_timer[timer_idx].update.update = 1; +#endif uint64_t timer_counter_value = ((uint64_t) TIMERG0.hw_timer[timer_idx].cnt_high) << 32 | TIMERG0.hw_timer[timer_idx].cnt_low; @@ -77,13 +81,21 @@ void IRAM_ATTR timer_group0_isr(void *para) and update the alarm time for the timer with without reload */ if ((intr_status & BIT(timer_idx)) && timer_idx == TIMER_0) { evt.type = TEST_WITHOUT_RELOAD; +#ifdef CONFIG_IDF_TARGET_ESP32 TIMERG0.int_clr_timers.t0 = 1; +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + TIMERG0.int_clr.t0 = 1; +#endif timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE); TIMERG0.hw_timer[timer_idx].alarm_high = (uint32_t) (timer_counter_value >> 32); TIMERG0.hw_timer[timer_idx].alarm_low = (uint32_t) timer_counter_value; } else if ((intr_status & BIT(timer_idx)) && timer_idx == TIMER_1) { evt.type = TEST_WITH_RELOAD; +#ifdef CONFIG_IDF_TARGET_ESP32 TIMERG0.int_clr_timers.t1 = 1; +#elif defined CONFIG_IDF_TARGET_ESP32S2BETA + TIMERG0.int_clr.t1 = 1; +#endif } else { evt.type = -1; // not supported even type } @@ -114,6 +126,9 @@ static void example_tg0_timer_init(int timer_idx, config.alarm_en = TIMER_ALARM_EN; config.intr_type = TIMER_INTR_LEVEL; config.auto_reload = auto_reload; +#ifdef CONFIG_IDF_TARGET_ESP32S2BETA + config.clk_sel = TIMER_SRC_CLK_APB; +#endif timer_init(TIMER_GROUP_0, timer_idx, &config); /* Timer's counter will initially start from value below.