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esp_wifi: store PHY digital registers before disabling PHY and load

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them after enabling PHY
This commit is contained in:
Xia Xiaotian 2021-01-19 19:36:06 +08:00
parent e417960838
commit f53c0c5b87
7 changed files with 48 additions and 6 deletions
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14
components/esp_wifi/include/phy.h
View File

@ -21,10 +21,6 @@ extern "C" {
#define ESP_CAL_DATA_CHECK_FAIL 1
#if CONFIG_MAC_BB_PD
#define MAC_BB_PD_MEM_SIZE (192*4)
#endif
/**
* @file phy.h
* @brief Declarations for functions provided by libphy.a
@ -80,6 +76,16 @@ void phy_close_rf(void);
void phy_xpd_tsens(void);
#endif
/**
* @brief Store and load PHY digital registers.
*
* @param backup_en if backup_en is true, store PHY digital registers to memory. Otherwise load PHY digital registers from memory
* @param mem_addr Memory address to store and load PHY digital registers
*
* @return memory size
*/
uint8_t phy_dig_reg_backup(bool backup_en, uint32_t *mem_addr);
#if CONFIG_MAC_BB_PD
/**
* @brief Store and load baseband registers.

2
components/esp_wifi/lib

@ -1 +1 @@
Subproject commit e1efaabef1ec5ea1240e04fce5c0c359281ec096
Subproject commit ad41588ea4ecbdaa38a89f3c31229a3a66beb1a4

25
components/esp_wifi/src/phy_init.c
View File

@ -74,6 +74,9 @@ static int64_t s_phy_rf_en_ts = 0;
/* PHY spinlock for libphy.a */
static DRAM_ATTR portMUX_TYPE s_phy_int_mux = portMUX_INITIALIZER_UNLOCKED;
/* Memory to store PHY digital registers */
static uint32_t* s_phy_digital_regs_mem = NULL;
#if CONFIG_MAC_BB_PD
uint32_t* s_mac_bb_pd_mem = NULL;
#endif
@ -198,6 +201,24 @@ IRAM_ATTR void esp_phy_common_clock_disable(void)
wifi_bt_common_module_disable();
}
static inline void phy_digital_regs_store(void)
{
if (s_phy_digital_regs_mem == NULL) {
s_phy_digital_regs_mem = (uint32_t *)malloc(SOC_PHY_DIG_REGS_MEM_SIZE);
}
if (s_phy_digital_regs_mem != NULL) {
phy_dig_reg_backup(true, s_phy_digital_regs_mem);
}
}
static inline void phy_digital_regs_load(void)
{
if (s_phy_digital_regs_mem != NULL) {
phy_dig_reg_backup(false, s_phy_digital_regs_mem);
}
}
void esp_phy_enable(void)
{
_lock_acquire(&s_phy_access_lock);
@ -217,6 +238,7 @@ void esp_phy_enable(void)
}
else {
phy_wakeup_init();
phy_digital_regs_load();
}
#if CONFIG_IDF_TARGET_ESP32
@ -240,6 +262,7 @@ void esp_phy_disable(void)
s_phy_access_ref--;
if (s_phy_access_ref == 0) {
phy_digital_regs_store();
// Disable PHY and RF.
phy_close_rf();
#if CONFIG_IDF_TARGET_ESP32C3
@ -263,7 +286,7 @@ void esp_mac_bb_pd_mem_init(void)
_lock_acquire(&s_phy_access_lock);
if (s_mac_bb_pd_mem == NULL) {
s_mac_bb_pd_mem = (uint32_t *)heap_caps_malloc(MAC_BB_PD_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
s_mac_bb_pd_mem = (uint32_t *)heap_caps_malloc(SOC_MAC_BB_PD_MEM_SIZE, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
}
_lock_release(&s_phy_access_lock);

3
components/soc/esp32/include/soc/soc_caps.h
View File

@ -272,6 +272,9 @@
#define SOC_AES_SUPPORT_AES_192 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
/*-------------------------- Power Management CAPS ---------------------------*/
#define SOC_PM_SUPPORT_EXT_WAKEUP (1)

4
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -124,6 +124,10 @@
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)

3
components/soc/esp32s2/include/soc/soc_caps.h
View File

@ -300,6 +300,9 @@
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)

3
components/soc/esp32s3/include/soc/soc_caps.h
View File

@ -166,6 +166,9 @@
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)