mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
180 lines
7.7 KiB
C
180 lines
7.7 KiB
C
// The long term plan is to have a single soc_caps.h for all peripherals.
|
|
// During the refactoring and multichip support development process, we
|
|
// separate these information into periph_caps.h for each peripheral and
|
|
// include them here to avoid developing conflicts.
|
|
|
|
#pragma once
|
|
|
|
/*-------------------------- COMMON CAPS ---------------------------------------*/
|
|
#define SOC_PCNT_SUPPORTED 1
|
|
#define SOC_TWAI_SUPPORTED 1
|
|
#define SOC_GDMA_SUPPORTED 1
|
|
#define SOC_DEDICATED_GPIO_SUPPORTED 1
|
|
#define SOC_CPU_CORES_NUM 2
|
|
#define SOC_CACHE_SUPPORT_WRAP 1
|
|
#define SOC_ULP_SUPPORTED 1
|
|
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
|
|
#define SOC_CCOMP_TIMER_SUPPORTED 1
|
|
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
|
|
|
|
|
/*-------------------------- ADC CAPS ----------------------------------------*/
|
|
#include "adc_caps.h"
|
|
|
|
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
|
|
#include "brownout_caps.h"
|
|
|
|
/*-------------------------- CPU CAPS ----------------------------------------*/
|
|
#include "cpu_caps.h"
|
|
|
|
/*-------------------------- DAC CAPS ----------------------------------------*/
|
|
#include "dac_caps.h"
|
|
|
|
/*-------------------------- GDMA CAPS ---------------------------------------*/
|
|
#include "gdma_caps.h"
|
|
|
|
/*-------------------------- GPIO CAPS ---------------------------------------*/
|
|
#include "gpio_caps.h"
|
|
|
|
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
|
|
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (4) /*!< 4 outward channels on each CPU core */
|
|
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (4) /*!< 4 inward channels on each CPU core */
|
|
|
|
/*-------------------------- I2C CAPS ----------------------------------------*/
|
|
#include "i2c_caps.h"
|
|
|
|
/*-------------------------- I2S CAPS ----------------------------------------*/
|
|
#include "i2s_caps.h"
|
|
|
|
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
|
#include "ledc_caps.h"
|
|
|
|
/*-------------------------- MPU CAPS ----------------------------------------*/
|
|
#include "mpu_caps.h"
|
|
|
|
/*-------------------------- PCNT CAPS ---------------------------------------*/
|
|
#define SOC_PCNT_PORT_NUM (1)
|
|
#define SOC_PCNT_UNIT_NUM (4)
|
|
#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
|
|
|
|
/*-------------------------- RMT CAPS ----------------------------------------*/
|
|
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
|
|
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */
|
|
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */
|
|
#define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */
|
|
#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
|
|
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
|
|
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
|
|
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
|
|
#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */
|
|
#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */
|
|
|
|
/*-------------------------- RTCIO CAPS --------------------------------------*/
|
|
#include "rtc_io_caps.h"
|
|
|
|
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
|
|
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
|
|
#define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels
|
|
|
|
/*-------------------------- SPI CAPS ----------------------------------------*/
|
|
#include "spi_caps.h"
|
|
|
|
/*-------------------------- SPIRAM CAPS ----------------------------------------*/
|
|
#define SOC_SPIRAM_SUPPORTED 1
|
|
|
|
/*-------------------------- SYS TIMER CAPS ----------------------------------*/
|
|
#include "systimer_caps.h"
|
|
|
|
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
|
|
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
|
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
|
#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
|
|
#define SOC_TIMER_GROUPS (2)
|
|
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2)
|
|
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
|
|
#define SOC_TIMER_GROUP_LAYOUT {2,2}
|
|
|
|
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
|
#include "touch_sensor_caps.h"
|
|
|
|
/*-------------------------- TWAI CAPS ---------------------------------------*/
|
|
#include "twai_caps.h"
|
|
|
|
/*-------------------------- UART CAPS ---------------------------------------*/
|
|
#include "uart_caps.h"
|
|
|
|
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
|
|
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
|
|
|
|
/*--------------------------- SHA CAPS ---------------------------------------*/
|
|
/* Max amount of bytes in a single DMA operation is 4095,
|
|
for SHA this means that the biggest safe amount of bytes is
|
|
31 blocks of 128 bytes = 3968
|
|
*/
|
|
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
|
|
#define SOC_SHA_SUPPORT_DMA (1)
|
|
|
|
/* The SHA engine is able to resume hashing from a user supplied context */
|
|
#define SOC_SHA_SUPPORT_RESUME (1)
|
|
|
|
/* Has a centralized DMA, which is shared with all peripherals */
|
|
#define SOC_SHA_GDMA (1)
|
|
|
|
/* Supported HW algorithms */
|
|
#define SOC_SHA_SUPPORT_SHA1 (1)
|
|
#define SOC_SHA_SUPPORT_SHA224 (1)
|
|
#define SOC_SHA_SUPPORT_SHA256 (1)
|
|
#define SOC_SHA_SUPPORT_SHA384 (1)
|
|
#define SOC_SHA_SUPPORT_SHA256 (1)
|
|
#define SOC_SHA_SUPPORT_SHA512 (1)
|
|
#define SOC_SHA_SUPPORT_SHA512_224 (1)
|
|
#define SOC_SHA_SUPPORT_SHA512_256 (1)
|
|
#define SOC_SHA_SUPPORT_SHA512_T (1)
|
|
|
|
/* Supported HW algorithms */
|
|
#define SOC_SHA_SUPPORT_SHA1 (1)
|
|
#define SOC_SHA_SUPPORT_SHA256 (1)
|
|
#define SOC_SHA_SUPPORT_SHA384 (1)
|
|
#define SOC_SHA_SUPPORT_SHA512 (1)
|
|
|
|
|
|
/*--------------------------- RSA CAPS ---------------------------------------*/
|
|
#define SOC_RSA_MAX_BIT_LEN (4096)
|
|
|
|
|
|
/*-------------------------- AES CAPS -----------------------------------------*/
|
|
#define SOC_AES_SUPPORT_DMA (1)
|
|
|
|
/*-------------------------- Power Management CAPS ---------------------------*/
|
|
#define SOC_PM_SUPPORT_EXT_WAKEUP (1)
|
|
|
|
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
|
|
|
|
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
|
|
|
|
/* Has a centralized DMA, which is shared with all peripherals */
|
|
#define SOC_AES_GDMA (1)
|
|
|
|
#define SOC_AES_SUPPORT_AES_128 (1)
|
|
#define SOC_AES_SUPPORT_AES_256 (1)
|
|
|
|
// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
|
|
// Remove them when GDMA driver API is ready
|
|
#define SOC_GDMA_SHA_DMA_CHANNEL (3)
|
|
#define SOC_GDMA_AES_DMA_CHANNEL (4)
|
|
|
|
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
|
|
#define SOC_WIFI_HW_TSF (1)
|
|
|
|
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
|
|
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
|
|
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
|
|
|
|
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
|
|
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
|
|
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
|
|
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
|
|
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
|
|
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
|
|
#define SOC_COEX_HW_PTI (1)
|