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fast_gpio: fix wrong initial occupy mask

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This commit is contained in:
morris 2021-12-01 20:15:05 +08:00
parent 47ab8f8e63
commit e8c5f8656b
6 changed files with 18 additions and 14 deletions
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10
components/driver/CMakeLists.txt
View File

@ -34,6 +34,10 @@ if(CONFIG_SOC_GDMA_SUPPORTED)
list(APPEND srcs "gdma.c") list(APPEND srcs "gdma.c")
endif() endif()
if(CONFIG_SOC_DEDICATED_GPIO_SUPPORTED)
list(APPEND srcs "dedic_gpio.c")
endif()
if(${target} STREQUAL "esp32") if(${target} STREQUAL "esp32")
# SDMMC and MCPWM are in ESP32 only. # SDMMC and MCPWM are in ESP32 only.
list(APPEND srcs "dac_common.c" list(APPEND srcs "dac_common.c"
@ -53,7 +57,6 @@ endif()
if(IDF_TARGET STREQUAL "esp32s2") if(IDF_TARGET STREQUAL "esp32s2")
list(APPEND srcs "dac_common.c" list(APPEND srcs "dac_common.c"
"dedic_gpio.c"
"spi_slave_hd.c" "spi_slave_hd.c"
"touch_sensor_common.c" "touch_sensor_common.c"
"sigmadelta.c" "sigmadelta.c"
@ -69,8 +72,7 @@ if(IDF_TARGET STREQUAL "esp32s2")
endif() endif()
if(${target} STREQUAL "esp32s3") if(${target} STREQUAL "esp32s3")
list(APPEND srcs "dedic_gpio.c" list(APPEND srcs "sdmmc_host.c"
"sdmmc_host.c"
"sdmmc_transaction.c" "sdmmc_transaction.c"
"rmt.c" "rmt.c"
"sigmadelta.c" "sigmadelta.c"
@ -84,7 +86,6 @@ endif()
if(IDF_TARGET STREQUAL "esp32c3") if(IDF_TARGET STREQUAL "esp32c3")
list(APPEND srcs "spi_slave_hd.c" list(APPEND srcs "spi_slave_hd.c"
"dedic_gpio.c"
"usb_serial_jtag.c" "usb_serial_jtag.c"
"i2s.c" "i2s.c"
"rmt.c" "rmt.c"
@ -96,7 +97,6 @@ endif()
if(IDF_TARGET STREQUAL "esp32h2") if(IDF_TARGET STREQUAL "esp32h2")
list(APPEND srcs "spi_slave_hd.c" list(APPEND srcs "spi_slave_hd.c"
"dedic_gpio.c"
"i2s.c" "i2s.c"
"rmt.c" "rmt.c"
"sigmadelta.c" "sigmadelta.c"

14
components/driver/dedic_gpio.c
View File

@ -78,12 +78,15 @@ static esp_err_t dedic_gpio_build_platform(uint32_t core_id)
if (s_platform[core_id]) { if (s_platform[core_id]) {
// initialize platfrom members // initialize platfrom members
s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
// initial occupy_mask: 1111...100...0
s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1);
s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1);
#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS #if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
s_platform[core_id]->dev = &DEDIC_GPIO; s_platform[core_id]->dev = &DEDIC_GPIO;
#endif // SOC_DEDIC_GPIO_ALLOW_REG_ACCESS #endif // SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
#if !SOC_DEDIC_PERIPH_AUTO_ENABLE #if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
periph_module_enable(dedic_gpio_periph_signals.module); // enable APB clock to peripheral periph_module_enable(dedic_gpio_periph_signals.module); // enable APB clock to peripheral
#endif // !SOC_DEDIC_PERIPH_AUTO_ENABLE #endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
} }
} }
_lock_release(&s_platform_mutexlock[core_id]); _lock_release(&s_platform_mutexlock[core_id]);
@ -104,9 +107,9 @@ static void dedic_gpio_break_platform(uint32_t core_id)
if (s_platform[core_id]) { if (s_platform[core_id]) {
free(s_platform[core_id]); free(s_platform[core_id]);
s_platform[core_id] = NULL; s_platform[core_id] = NULL;
#if !SOC_DEDIC_PERIPH_AUTO_ENABLE #if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
periph_module_disable(dedic_gpio_periph_signals.module); // disable module if no GPIO channel is being used periph_module_disable(dedic_gpio_periph_signals.module); // disable module if no GPIO channel is being used
#endif // !SOC_DEDIC_PERIPH_AUTO_ENABLE #endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
} }
_lock_release(&s_platform_mutexlock[core_id]); _lock_release(&s_platform_mutexlock[core_id]);
} }
@ -309,7 +312,8 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
portENTER_CRITICAL(&s_platform[core_id]->spinlock); portENTER_CRITICAL(&s_platform[core_id]->spinlock);
s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask); s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask);
s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask); s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask);
if (!s_platform[core_id]->in_occupied_mask && !s_platform[core_id]->out_occupied_mask) { if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1)) &&
s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1))) {
recycle_all = true; recycle_all = true;
} }
portEXIT_CRITICAL(&s_platform[core_id]->spinlock); portEXIT_CRITICAL(&s_platform[core_id]->spinlock);

2
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -255,7 +255,7 @@ config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int int
default 8 default 8
config SOC_DEDIC_PERIPH_AUTO_ENABLE config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool bool
default y default y

2
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -136,7 +136,7 @@
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_AUTO_ENABLE (1) /*!< The dedicated GPIO peripheral is enabled automatically */ #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/ /*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C. // ESP32-C3 have 2 I2C.

2
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -239,7 +239,7 @@ config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int int
default 8 default 8
config SOC_DEDIC_PERIPH_AUTO_ENABLE config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool bool
default y default y

2
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -131,7 +131,7 @@
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_AUTO_ENABLE (1) /*!< The dedicated GPIO peripheral is enabled automatically */ #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/ /*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C. // ESP32-C3 have 2 I2C.