diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt
index 32ffd67b48..f47a54248b 100644
--- a/components/driver/CMakeLists.txt
+++ b/components/driver/CMakeLists.txt
@@ -34,6 +34,10 @@ if(CONFIG_SOC_GDMA_SUPPORTED)
     list(APPEND srcs "gdma.c")
 endif()
 
+if(CONFIG_SOC_DEDICATED_GPIO_SUPPORTED)
+    list(APPEND srcs "dedic_gpio.c")
+endif()
+
 if(${target} STREQUAL "esp32")
     # SDMMC and MCPWM are in ESP32 only.
     list(APPEND srcs "dac_common.c"
@@ -53,7 +57,6 @@ endif()
 
 if(IDF_TARGET STREQUAL "esp32s2")
     list(APPEND srcs "dac_common.c"
-                     "dedic_gpio.c"
                      "spi_slave_hd.c"
                      "touch_sensor_common.c"
                      "sigmadelta.c"
@@ -69,8 +72,7 @@ if(IDF_TARGET STREQUAL "esp32s2")
 endif()
 
 if(${target} STREQUAL "esp32s3")
-    list(APPEND srcs "dedic_gpio.c"
-                     "sdmmc_host.c"
+    list(APPEND srcs "sdmmc_host.c"
                      "sdmmc_transaction.c"
                      "rmt.c"
                      "sigmadelta.c"
@@ -84,7 +86,6 @@ endif()
 
 if(IDF_TARGET STREQUAL "esp32c3")
     list(APPEND srcs "spi_slave_hd.c"
-                     "dedic_gpio.c"
                      "usb_serial_jtag.c"
                      "i2s.c"
                      "rmt.c"
@@ -96,7 +97,6 @@ endif()
 
 if(IDF_TARGET STREQUAL "esp32h2")
     list(APPEND srcs "spi_slave_hd.c"
-                     "dedic_gpio.c"
                      "i2s.c"
                      "rmt.c"
                      "sigmadelta.c"
diff --git a/components/driver/dedic_gpio.c b/components/driver/dedic_gpio.c
index 8d3299ecd7..0b6ba6e434 100644
--- a/components/driver/dedic_gpio.c
+++ b/components/driver/dedic_gpio.c
@@ -78,12 +78,15 @@ static esp_err_t dedic_gpio_build_platform(uint32_t core_id)
             if (s_platform[core_id]) {
                 // initialize platfrom members
                 s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
+                // initial occupy_mask: 1111...100...0
+                s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1);
+                s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1);
 #if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
                 s_platform[core_id]->dev = &DEDIC_GPIO;
 #endif // SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
-#if !SOC_DEDIC_PERIPH_AUTO_ENABLE
+#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
                 periph_module_enable(dedic_gpio_periph_signals.module); // enable APB clock to peripheral
-#endif // !SOC_DEDIC_PERIPH_AUTO_ENABLE
+#endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
             }
         }
         _lock_release(&s_platform_mutexlock[core_id]);
@@ -104,9 +107,9 @@ static void dedic_gpio_break_platform(uint32_t core_id)
         if (s_platform[core_id]) {
             free(s_platform[core_id]);
             s_platform[core_id] = NULL;
-#if !SOC_DEDIC_PERIPH_AUTO_ENABLE
+#if !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
             periph_module_disable(dedic_gpio_periph_signals.module); // disable module if no GPIO channel is being used
-#endif // !SOC_DEDIC_PERIPH_AUTO_ENABLE
+#endif // !SOC_DEDIC_PERIPH_ALWAYS_ENABLE
         }
         _lock_release(&s_platform_mutexlock[core_id]);
     }
@@ -309,7 +312,8 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
     portENTER_CRITICAL(&s_platform[core_id]->spinlock);
     s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask);
     s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask);
-    if (!s_platform[core_id]->in_occupied_mask && !s_platform[core_id]->out_occupied_mask) {
+    if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1)) &&
+        s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1))) {
         recycle_all = true;
     }
     portEXIT_CRITICAL(&s_platform[core_id]->spinlock);
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index 9531d0f393..872eb97b5d 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -255,7 +255,7 @@ config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
     int
     default 8
 
-config SOC_DEDIC_PERIPH_AUTO_ENABLE
+config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
     bool
     default y
 
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 6a8665712e..710397f997 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -136,7 +136,7 @@
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_AUTO_ENABLE    (1) /*!< The dedicated GPIO peripheral is enabled automatically */
+#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32-C3 have 2 I2C.
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index 006767c1e1..5a83c2b0e9 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -239,7 +239,7 @@ config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
     int
     default 8
 
-config SOC_DEDIC_PERIPH_AUTO_ENABLE
+config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
     bool
     default y
 
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index 5e621a98ea..0f1861fa63 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -131,7 +131,7 @@
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-#define SOC_DEDIC_PERIPH_AUTO_ENABLE    (1) /*!< The dedicated GPIO peripheral is enabled automatically */
+#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32-C3 have 2 I2C.