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fix(ci): some actions taken to pass CI

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This commit is contained in:
Lou Tianhao 2024-09-13 20:22:11 +08:00 committed by BOT
parent d70f24e414
commit d9c15bb772
6 changed files with 8 additions and 7 deletions
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4
components/app_update/test_apps/test_app_update/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

2
components/esp_system/port/cpu_start.c
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@ -751,7 +751,7 @@ void IRAM_ATTR call_start_cpu0(void)
#endif #endif
#endif #endif
#if SOC_DEEP_SLEEP_SUPPORTED //TODO: IDF-9245 #if SOC_DEEP_SLEEP_SUPPORTED
// Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins // Need to unhold the IOs that were hold right before entering deep sleep, which are used as wakeup pins
if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) { if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
esp_deep_sleep_wakeup_io_reset(); esp_deep_sleep_wakeup_io_reset();

2
components/hal/esp32c61/modem_clock_hal.c
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@ -59,7 +59,7 @@ void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_conte
} }
} }
uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain) uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain)
{ {
HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
uint32_t bitmap = 0; uint32_t bitmap = 0;

2
components/soc/esp32c61/include/soc/soc_caps.h
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@ -180,7 +180,7 @@
#define SOC_GPIO_OUT_RANGE_MAX 21 #define SOC_GPIO_OUT_RANGE_MAX 21
// GPIO0~6 on ESP32C61 can support chip deep sleep wakeup // GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) //TODO: IDF-9245 #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6) #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7) #define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)

4
examples/system/.build-test-rules.yml
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@ -32,9 +32,9 @@ examples/system/deep_sleep:
examples/system/deep_sleep_wake_stub: examples/system/deep_sleep_wake_stub:
disable: disable:
- if: IDF_TARGET in ["esp32c2", "esp32p4", "esp32c61"] - if: ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB != 1
temporary: true temporary: true
reason: target(s) is not supported yet # TODO: [esp32c61] IDF-9245 reason: target(s) is not supported yet
examples/system/efuse: examples/system/efuse:
enable: enable:

1
examples/system/deep_sleep/pytest_deep_sleep.py
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@ -20,6 +20,7 @@ CONFIGS = [
pytest.mark.esp32c3, pytest.mark.esp32c3,
pytest.mark.esp32c5, pytest.mark.esp32c5,
pytest.mark.esp32c6, pytest.mark.esp32c6,
pytest.mark.esp32c61,
pytest.mark.esp32h2, pytest.mark.esp32h2,
pytest.mark.esp32p4, pytest.mark.esp32p4,
pytest.mark.esp32c2, pytest.mark.esp32c2,