glitch_filter: support derive clock source form IO MUX

This commit is contained in:
morris 2022-12-16 15:59:08 +08:00
parent cbe297e5a0
commit ca1b182b25
25 changed files with 335 additions and 36 deletions

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@ -13,6 +13,8 @@
#define FILTER_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
#define GLITCH_FILTER_PM_LOCK_NAME_LEN_MAX 16
#ifdef __cplusplus
extern "C" {
#endif

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@ -9,8 +9,10 @@
#include "esp_check.h"
#include "glitch_filter_priv.h"
#include "esp_private/esp_clk.h"
#include "esp_private/io_mux.h"
#include "soc/soc_caps.h"
#include "hal/gpio_glitch_filter_ll.h"
#include "esp_pm.h"
static const char *TAG = "gpio-filter";
@ -26,6 +28,10 @@ struct gpio_flex_glitch_filter_t {
gpio_glitch_filter_t base;
gpio_flex_glitch_filter_group_t *group;
uint32_t filter_id;
esp_pm_lock_handle_t pm_lock;
#if CONFIG_PM_ENABLE
char pm_lock_name[GLITCH_FILTER_PM_LOCK_NAME_LEN_MAX]; // pm lock name
#endif
};
static gpio_flex_glitch_filter_group_t s_gpio_glitch_filter_group = {
@ -66,6 +72,10 @@ static esp_err_t gpio_filter_destroy(gpio_flex_glitch_filter_t *filter)
portEXIT_CRITICAL(&group->spinlock);
}
if (filter->pm_lock) {
esp_pm_lock_delete(filter->pm_lock);
}
free(filter);
return ESP_OK;
}
@ -82,6 +92,11 @@ static esp_err_t gpio_flex_glitch_filter_enable(gpio_glitch_filter_t *filter)
ESP_RETURN_ON_FALSE(filter->fsm == GLITCH_FILTER_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "filter not in init state");
gpio_flex_glitch_filter_t *flex_filter = __containerof(filter, gpio_flex_glitch_filter_t, base);
// acquire pm lock
if (flex_filter->pm_lock) {
esp_pm_lock_acquire(flex_filter->pm_lock);
}
int filter_id = flex_filter->filter_id;
gpio_ll_glitch_filter_enable(s_gpio_glitch_filter_group.hw, filter_id, true);
filter->fsm = GLITCH_FILTER_FSM_ENABLE;
@ -95,6 +110,12 @@ static esp_err_t gpio_flex_glitch_filter_disable(gpio_glitch_filter_t *filter)
int filter_id = flex_filter->filter_id;
gpio_ll_glitch_filter_enable(s_gpio_glitch_filter_group.hw, filter_id, false);
// release pm lock
if (flex_filter->pm_lock) {
esp_pm_lock_release(flex_filter->pm_lock);
}
filter->fsm = GLITCH_FILTER_FSM_INIT;
return ESP_OK;
}
@ -105,19 +126,46 @@ esp_err_t gpio_new_flex_glitch_filter(const gpio_flex_glitch_filter_config_t *co
gpio_flex_glitch_filter_t *filter = NULL;
ESP_GOTO_ON_FALSE(config && ret_filter, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
ESP_GOTO_ON_FALSE(GPIO_IS_VALID_GPIO(config->gpio_num), ESP_ERR_INVALID_ARG, err, TAG, "invalid gpio number");
// Glitch filter's clock source is same to the IOMUX clock
// TODO: IDF-6345 task will make the IOMUX clock source configurable, and we should opt the glitch filter clock source accordingly
uint32_t clk_freq_mhz = esp_clk_xtal_freq() / 1000000;
// allocate driver object
filter = heap_caps_calloc(1, sizeof(gpio_flex_glitch_filter_t), FILTER_MEM_ALLOC_CAPS);
ESP_GOTO_ON_FALSE(filter, ESP_ERR_NO_MEM, err, TAG, "no memory for flex glitch filter");
// register the filter to the group
ESP_GOTO_ON_ERROR(gpio_filter_register_to_group(filter), err, TAG, "register filter to group failed");
int filter_id = filter->filter_id;
// set clock source
uint32_t clk_freq_mhz = 0;
switch (config->clk_src) {
#if SOC_GPIO_FILTER_CLK_SUPPORT_XTAL
case GLITCH_FILTER_CLK_SRC_XTAL:
clk_freq_mhz = esp_clk_xtal_freq() / 1000000;
break;
#endif // SOC_GPIO_FILTER_CLK_SUPPORT_XTAL
#if SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M
case GLITCH_FILTER_CLK_SRC_PLL_F80M:
clk_freq_mhz = 80;
#if CONFIG_PM_ENABLE
sprintf(filter->pm_lock_name, "filter_%d", filter_id); // e.g. filter_0
ret = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, filter->pm_lock_name, &filter->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create NO_LIGHT_SLEEP lock failed");
#endif
break;
#endif // SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid clock source");
break;
}
uint32_t window_thres_ticks = clk_freq_mhz * config->window_thres_ns / 1000;
uint32_t window_width_ticks = clk_freq_mhz * config->window_width_ns / 1000;
ESP_GOTO_ON_FALSE(window_thres_ticks && window_thres_ticks <= window_width_ticks && window_width_ticks <= GPIO_LL_GLITCH_FILTER_MAX_WINDOW,
ESP_ERR_INVALID_ARG, err, TAG, "invalid or out of range window width/threshold");
filter = heap_caps_calloc(1, sizeof(gpio_flex_glitch_filter_t), FILTER_MEM_ALLOC_CAPS);
ESP_GOTO_ON_FALSE(filter, ESP_ERR_NO_MEM, err, TAG, "no memory for flex glitch filter");
// register the filter to the group
ESP_GOTO_ON_ERROR(gpio_filter_register_to_group(filter), err, TAG, "register filter to group failed");
int filter_id = filter->filter_id;
// Glitch filter's clock source is same to the IOMUX clock
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(config->clk_src)), err, TAG, "set IO MUX clock source failed");
// make sure the filter is disabled
gpio_ll_glitch_filter_enable(s_gpio_glitch_filter_group.hw, filter_id, false);

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@ -7,8 +7,11 @@
#include <sys/cdefs.h>
#include "freertos/FreeRTOS.h"
#include "esp_check.h"
#include "esp_pm.h"
#include "glitch_filter_priv.h"
#include "hal/gpio_ll.h"
#include "esp_private/esp_clk.h"
#include "esp_private/io_mux.h"
static const char *TAG = "gpio-filter";
@ -17,19 +20,39 @@ static const char *TAG = "gpio-filter";
*/
typedef struct gpio_pin_glitch_filter_t {
gpio_glitch_filter_t base;
esp_pm_lock_handle_t pm_lock;
#if CONFIG_PM_ENABLE
char pm_lock_name[GLITCH_FILTER_PM_LOCK_NAME_LEN_MAX]; // pm lock name
#endif
} gpio_pin_glitch_filter_t;
static esp_err_t gpio_filter_destroy(gpio_pin_glitch_filter_t *filter)
{
if (filter->pm_lock) {
esp_pm_lock_delete(filter->pm_lock);
}
free(filter);
return ESP_OK;
}
static esp_err_t gpio_pin_glitch_filter_del(gpio_glitch_filter_t *filter)
{
ESP_RETURN_ON_FALSE(filter->fsm == GLITCH_FILTER_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "filter not in init state");
gpio_pin_glitch_filter_t *pin_filter = __containerof(filter, gpio_pin_glitch_filter_t, base);
free(pin_filter);
return ESP_OK;
return gpio_filter_destroy(pin_filter);
}
static esp_err_t gpio_pin_glitch_filter_enable(gpio_glitch_filter_t *filter)
{
ESP_RETURN_ON_FALSE(filter->fsm == GLITCH_FILTER_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "filter not in init state");
gpio_pin_glitch_filter_t *pin_filter = __containerof(filter, gpio_pin_glitch_filter_t, base);
// acquire pm lock
if (pin_filter->pm_lock) {
esp_pm_lock_acquire(pin_filter->pm_lock);
}
gpio_ll_pin_filter_enable(NULL, filter->gpio_num);
filter->fsm = GLITCH_FILTER_FSM_ENABLE;
return ESP_OK;
@ -38,7 +61,15 @@ static esp_err_t gpio_pin_glitch_filter_enable(gpio_glitch_filter_t *filter)
static esp_err_t gpio_pin_glitch_filter_disable(gpio_glitch_filter_t *filter)
{
ESP_RETURN_ON_FALSE(filter->fsm == GLITCH_FILTER_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "filter not in enable state");
gpio_pin_glitch_filter_t *pin_filter = __containerof(filter, gpio_pin_glitch_filter_t, base);
gpio_ll_pin_filter_disable(NULL, filter->gpio_num);
// release pm lock
if (pin_filter->pm_lock) {
esp_pm_lock_release(pin_filter->pm_lock);
}
filter->fsm = GLITCH_FILTER_FSM_INIT;
return ESP_OK;
}
@ -53,6 +84,40 @@ esp_err_t gpio_new_pin_glitch_filter(const gpio_pin_glitch_filter_config_t *conf
filter = heap_caps_calloc(1, sizeof(gpio_pin_glitch_filter_t), FILTER_MEM_ALLOC_CAPS);
ESP_GOTO_ON_FALSE(filter, ESP_ERR_NO_MEM, err, TAG, "no memory for pin glitch filter");
// set clock source
switch (config->clk_src) {
#if SOC_GPIO_FILTER_CLK_SUPPORT_XTAL
case GLITCH_FILTER_CLK_SRC_XTAL:
break;
#endif // SOC_GPIO_FILTER_CLK_SUPPORT_XTAL
#if SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M
case GLITCH_FILTER_CLK_SRC_PLL_F80M:
#if CONFIG_PM_ENABLE
sprintf(filter->pm_lock_name, "filter_io_%d", config->gpio_num); // e.g. filter_io_0
ret = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, filter->pm_lock_name, &filter->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create NO_LIGHT_SLEEP lock failed");
#endif
break;
#endif // SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M
#if SOC_GPIO_FILTER_CLK_SUPPORT_APB
case GLITCH_FILTER_CLK_SRC_APB:
#if CONFIG_PM_ENABLE
sprintf(filter->pm_lock_name, "filter_io_%d", config->gpio_num); // e.g. filter_io_0
ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, filter->pm_lock_name, &filter->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create APB_FREQ_MAX lock failed");
#endif
break;
#endif // SOC_GPIO_FILTER_CLK_SUPPORT_APB
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "invalid clock source");
break;
}
// Glitch filter's clock source is same to the IOMUX clock
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(config->clk_src)), err, TAG, "set IO MUX clock source failed");
filter->base.gpio_num = config->gpio_num;
filter->base.fsm = GLITCH_FILTER_FSM_INIT;
filter->base.del = gpio_pin_glitch_filter_del;
@ -63,7 +128,7 @@ esp_err_t gpio_new_pin_glitch_filter(const gpio_pin_glitch_filter_config_t *conf
return ESP_OK;
err:
if (filter) {
free(filter);
gpio_filter_destroy(filter);
}
return ret;
}

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@ -9,6 +9,7 @@
#include <stdbool.h>
#include <stdint.h>
#include "esp_err.h"
#include "hal/glitch_filter_types.h"
#include "driver/gpio.h"
#ifdef __cplusplus
@ -24,6 +25,7 @@ typedef struct gpio_glitch_filter_t *gpio_glitch_filter_handle_t;
* @brief Configuration of GPIO pin glitch filter
*/
typedef struct {
glitch_filter_clock_source_t clk_src; /*!< Clock source for the glitch filter */
gpio_num_t gpio_num; /*!< GPIO number */
} gpio_pin_glitch_filter_config_t;
@ -48,6 +50,7 @@ esp_err_t gpio_new_pin_glitch_filter(const gpio_pin_glitch_filter_config_t *conf
* @brief Configuration of GPIO flex glitch filter
*/
typedef struct {
glitch_filter_clock_source_t clk_src; /*!< Clock source for the glitch filter */
gpio_num_t gpio_num; /*!< GPIO number */
uint32_t window_width_ns; /*!< Sample window width (in ns) */
uint32_t window_thres_ns; /*!< Sample window threshold (in ns), during the `window_width_ns` sample window, any pulse whose width < window_thres_ns will be discarded. */

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@ -19,7 +19,9 @@
TEST_CASE("GPIO pin glitch filter life cycle", "[gpio_filter]")
{
gpio_glitch_filter_handle_t filter = NULL;
gpio_pin_glitch_filter_config_t config = {};
gpio_pin_glitch_filter_config_t config = {
.clk_src = GLITCH_FILTER_CLK_SRC_DEFAULT,
};
TEST_ESP_OK(gpio_new_pin_glitch_filter(&config, &filter));
TEST_ESP_OK(gpio_glitch_filter_enable(filter));
@ -38,7 +40,9 @@ TEST_CASE("GPIO pin glitch filter life cycle", "[gpio_filter]")
TEST_CASE("GPIO flex glitch filter life cycle", "[gpio_filter]")
{
gpio_glitch_filter_handle_t filters[SOC_GPIO_FLEX_GLITCH_FILTER_NUM];
gpio_flex_glitch_filter_config_t config = {};
gpio_flex_glitch_filter_config_t config = {
.clk_src = GLITCH_FILTER_CLK_SRC_DEFAULT,
};
// install filter with wrong parameters
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, gpio_new_flex_glitch_filter(&config, &filters[0]));
@ -82,6 +86,19 @@ static void test_gpio_intr_callback(void *args)
}
}
// put the simulation code in the IRAM to avoid cache miss
NOINLINE_ATTR IRAM_ATTR static void test_gpio_simulate_glitch_pulse(void)
{
// the following code is used to generate a short glitch pulse
// around 10ns @CPU160MHz
asm volatile(
"csrrsi zero, %0, 0x1\n"
"csrrsi zero, %0, 0x1\n"
"csrrci zero, %0, 0x1"
:: "i"(CSR_GPIO_OUT_USER)
);
}
TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]")
{
const gpio_num_t test_gpio = 0;
@ -109,9 +126,10 @@ TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]")
printf("apply glitch filter to the GPIO\r\n");
gpio_glitch_filter_handle_t filter;
gpio_flex_glitch_filter_config_t filter_cfg = {
.clk_src = GLITCH_FILTER_CLK_SRC_DEFAULT,
.gpio_num = test_gpio,
.window_thres_ns = 1500, // pulse whose width is shorter than 1500 will be filtered out
.window_width_ns = 1500,
.window_thres_ns = 500,
.window_width_ns = 500,
};
TEST_ESP_OK((gpio_new_flex_glitch_filter(&filter_cfg, &filter)));
TEST_ESP_OK(gpio_glitch_filter_enable(filter));
@ -122,12 +140,7 @@ TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]")
TEST_ESP_OK(gpio_isr_handler_add(test_gpio, test_gpio_intr_callback, sem));
printf("generate rising edge glitch signal\r\n");
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrci zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
test_gpio_simulate_glitch_pulse();
// should timeout, because the glitch is filtered out
TEST_ASSERT_EQUAL(pdFALSE, xSemaphoreTake(sem, pdMS_TO_TICKS(1000)));
@ -136,12 +149,7 @@ TEST_CASE("GPIO flex glitch filter enable/disable", "[gpio_filter]")
TEST_ESP_OK(gpio_glitch_filter_disable(filter));
printf("generate rising edge glitch signal again\r\n");
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrsi zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
asm volatile("csrrci zero, %0, 0x1" :: "i"(CSR_GPIO_OUT_USER));
test_gpio_simulate_glitch_pulse();
// this time we should see the GPIO interrupt fired up
TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(sem, pdMS_TO_TICKS(1000)));

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@ -0,0 +1,24 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER || (SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0)
typedef soc_periph_glitch_filter_clk_src_t glitch_filter_clock_source_t; // glitch filter clock source
#else
typedef int glitch_filter_clock_source_t; // glitch filter clock source, fallback to integer type
#endif // SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER || (SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0)
#ifdef __cplusplus
}
#endif

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@ -211,6 +211,10 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FILTER_CLK_SUPPORT_APB
bool
default y
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
bool
default y

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@ -102,6 +102,7 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_APB, /*!< APB_CLK is always 40MHz no matter it derives from XTAL or PLL */
SOC_MOD_CLK_PLL_F40M, /*!< PLL_F40M_CLK is derived from PLL, and has a fixed frequency of 40MHz */
SOC_MOD_CLK_PLL_F60M, /*!< PLL_F60M_CLK is derived from PLL, and has a fixed frequency of 60MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
@ -177,7 +178,7 @@ typedef enum {
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum {
UART_SCLK_PLL_F40M = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock is APB CLK */
UART_SCLK_PLL_F40M = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock is PLL_F40M CLK */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F40M, /*!< UART source clock default choice is PLL_F40M */
@ -215,6 +216,21 @@ typedef enum {
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
#ifdef __cplusplus
}
#endif

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@ -106,6 +106,7 @@
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 21
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C2, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.

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@ -303,6 +303,10 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FILTER_CLK_SUPPORT_APB
bool
default y
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
bool
default y

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@ -243,7 +243,7 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
@ -258,6 +258,22 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
/**

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@ -144,6 +144,7 @@
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 22
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.

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@ -307,6 +307,14 @@ config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
int
default 8
config SOC_GPIO_FILTER_CLK_SUPPORT_XTAL
bool
default y
config SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_GPIO_SUPPORT_ETM
bool
default y

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@ -123,7 +123,7 @@ typedef enum {
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
/**
* @brief Type of SYSTIMER clock source
@ -285,7 +285,7 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
@ -301,7 +301,24 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of TWAI

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@ -158,6 +158,8 @@
#define SOC_GPIO_PIN_COUNT 31
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_FILTER_CLK_SUPPORT_XTAL 1
#define SOC_GPIO_FILTER_CLK_SUPPORT_PLL_F80M 1
// GPIO peripheral has the ETM extension
#define SOC_GPIO_SUPPORT_ETM 1

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@ -308,7 +308,7 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
@ -323,6 +323,23 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
/**

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@ -283,6 +283,10 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FILTER_CLK_SUPPORT_APB
bool
default y
config SOC_GPIO_PIN_COUNT
int
default 41

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@ -248,7 +248,7 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
@ -263,6 +263,22 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
/**

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@ -142,6 +142,7 @@
// ESP32-H4 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
#if CONFIG_IDF_TARGET_ESP32H4_BETA_VERSION_1
#define SOC_GPIO_PIN_COUNT (41)

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@ -287,6 +287,10 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FILTER_CLK_SUPPORT_APB
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y

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@ -259,7 +259,7 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
@ -274,6 +274,22 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
////////////////////////////////////////////////////DAC/////////////////////////////////////////////////////////////////
/**

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@ -138,6 +138,7 @@
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 47
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.

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@ -351,6 +351,10 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FILTER_CLK_SUPPORT_APB
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y

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@ -288,7 +288,7 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
@ -303,6 +303,22 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
/**

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@ -146,6 +146,7 @@
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 49
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)