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sdm: support derive clock source from IO MUX

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This commit is contained in:
morris 2022-12-13 14:39:38 +08:00
parent 672ac58ad5
commit cbe297e5a0
17 changed files with 76 additions and 10 deletions
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21
components/driver/sdm.c
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@ -26,6 +26,7 @@
#include "hal/sdm_ll.h"
#include "soc/sdm_periph.h"
#include "esp_private/esp_clk.h"
#include "esp_private/io_mux.h"
#if CONFIG_SDM_CTRL_FUNC_IN_IRAM
#define SDM_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
@ -209,6 +210,7 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
ESP_GOTO_ON_FALSE(group->clk_src == 0 || group->clk_src == config->clk_src, ESP_ERR_INVALID_ARG, err, TAG, "clock source conflict");
uint32_t src_clk_hz = 0;
switch (config->clk_src) {
#if SOC_SDM_CLK_SUPPORT_APB
case SDM_CLK_SRC_APB:
src_clk_hz = esp_clk_apb_freq();
#if CONFIG_PM_ENABLE
@ -217,12 +219,31 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
ESP_RETURN_ON_ERROR(ret, TAG, "create APB_FREQ_MAX lock failed");
#endif
break;
#endif // SOC_SDM_CLK_SUPPORT_APB
#if SOC_SDM_CLK_SUPPORT_XTAL
case SDM_CLK_SRC_XTAL:
src_clk_hz = esp_clk_xtal_freq();
break;
#endif // SOC_SDM_CLK_SUPPORT_XTAL
#if SOC_SDM_CLK_SUPPORT_PLL_F80M
case SDM_CLK_SRC_PLL_F80M:
src_clk_hz = 80 * 1000 * 1000;
#if CONFIG_PM_ENABLE
sprintf(chan->pm_lock_name, "sdm_%d_%d", group->group_id, chan_id); // e.g. sdm_0_0
ret = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, chan->pm_lock_name, &chan->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create NO_LIGHT_SLEEP lock failed");
#endif
break;
#endif // SOC_SDM_CLK_SUPPORT_PLL_F80M
default:
ESP_GOTO_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, err, TAG, "clock source %d is not support", config->clk_src);
break;
}
group->clk_src = config->clk_src;
// SDM clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(group->clk_src)), err, TAG, "set IO MUX clock source failed");
// GPIO configuration
gpio_config_t gpio_conf = {
.intr_type = GPIO_INTR_DISABLE,

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@ -523,6 +523,10 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_HD_BOTH_INOUT_SUPPORTED
bool
default y

1
components/soc/esp32/include/soc/soc_caps.h
View File

@ -261,6 +261,7 @@
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@ -551,6 +551,10 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

1
components/soc/esp32c3/include/soc/soc_caps.h
View File

@ -262,6 +262,7 @@
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2

8
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -659,6 +659,14 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

10
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@ -101,7 +101,7 @@ typedef enum {
} soc_rtc_fast_clk_src_t;
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
// {[upstream]clock_name}: APB, (BB)PLL, etc.
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
/**
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
@ -115,7 +115,6 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */ // TODO: IDF-6343 This should be removed on ESP32C6! Impacts on all following peripheral drivers!
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL, and has a fixed frequency of 240MHz */
@ -291,14 +290,15 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of SDM
*/
#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Sigma Delta Modulator clock source
*/
typedef enum {
SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////

6
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -309,8 +309,10 @@
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
// TODO: IDF-5334 (Copy from esp32c3, need check)
/*-------------------------- SPI CAPS ----------------------------------------*/

8
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -511,6 +511,14 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

6
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -292,8 +292,10 @@
// TODO: IDF-6220
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
// TODO: IDF-6245 (Copy from esp32c6, need check)
/*-------------------------- SPI CAPS ----------------------------------------*/

4
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@ -531,6 +531,10 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

1
components/soc/esp32h4/include/soc/soc_caps.h
View File

@ -270,6 +270,7 @@
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@ -547,6 +547,10 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_HD_BOTH_INOUT_SUPPORTED
bool
default y

1
components/soc/esp32s2/include/soc/soc_caps.h
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@ -244,6 +244,7 @@
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@ -667,6 +667,10 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 3

1
components/soc/esp32s3/include/soc/soc_caps.h
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@ -275,6 +275,7 @@
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 3

2
tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c
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@ -33,11 +33,11 @@
#define REF_CLOCK_GPIO 0 // GPIO used to combine RMT out signal with PCNT input signal
#define REF_CLOCK_PRESCALER_MS 30 // PCNT high threshold interrupt fired every 30ms
// peripheral driver handles
static pcnt_unit_handle_t s_pcnt_unit;
static pcnt_channel_handle_t s_pcnt_chan;
static rmt_channel_handle_t s_rmt_chan;
static rmt_encoder_handle_t s_rmt_encoder;
static volatile uint32_t s_milliseconds;
void ref_clock_init(void)
{