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feat(gpio): add support for ESP32P4

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This commit is contained in:
Song Ruo Jing 2023-07-18 17:44:14 +08:00
parent 337aeb4b78
commit be9afeac86
52 changed files with 2499 additions and 6787 deletions
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8
components/driver/gpio/gpio.c
View File

@ -257,11 +257,13 @@ static esp_err_t gpio_hysteresis_disable(gpio_num_t gpio_num)
return ESP_OK;
}
#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
static esp_err_t gpio_hysteresis_by_efuse(gpio_num_t gpio_num)
{
gpio_hal_hysteresis_from_efuse(gpio_context.gpio_hal, gpio_num);
return ESP_OK;
}
#endif
#endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER
esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
@ -416,10 +418,14 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
gpio_hysteresis_enable(io_num);
} else if (pGPIOConfig->hys_ctrl_mode == GPIO_HYS_SOFT_DISABLE) {
gpio_hysteresis_disable(io_num);
} else {
}
#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
else {
gpio_hysteresis_by_efuse(io_num);
}
#endif
#endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER
/* By default, all the pins have to be configured as GPIO pins. */
gpio_hal_iomux_func_sel(io_reg, PIN_FUNC_GPIO);
}

52
components/driver/test_apps/gpio/main/test_gpio.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -791,21 +791,28 @@ TEST_CASE("GPIO_drive_capability_test", "[gpio][ignore]")
prompt_to_continue("If this test finishes");
}
#if SOC_USB_SERIAL_JTAG_SUPPORTED
#if SOC_USB_SERIAL_JTAG_SUPPORTED // TODO: replace with a more proper soc_caps (USB_PHY_INTERNAL_NUM > 0)
TEST_CASE("GPIO_input_and_output_of_USB_pins_test", "[gpio]")
{
const int test_pins[] = {USB_DP_GPIO_NUM, USB_DM_GPIO_NUM};
gpio_config_t io_conf = {
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_INPUT_OUTPUT,
.pin_bit_mask = (BIT64(test_pins[0]) | BIT64(test_pins[1])),
.pull_down_en = 0,
.pull_up_en = 0,
};
gpio_config(&io_conf);
const int test_pins[] = {USB_INT_PHY0_DP_GPIO_NUM,
USB_INT_PHY0_DM_GPIO_NUM,
#if CONFIG_IDF_TARGET_ESP32P4 // TODO: Use proper soc_caps macro
USB_INT_PHY1_DP_GPIO_NUM,
USB_INT_PHY1_DM_GPIO_NUM
#endif
};
for (int i = 0; i < sizeof(test_pins) / sizeof(int); i++) {
int pin = test_pins[i];
gpio_config_t io_conf = {
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_INPUT_OUTPUT,
.pin_bit_mask = BIT64(pin),
.pull_down_en = 0,
.pull_up_en = 0,
};
gpio_config(&io_conf);
// test pin
gpio_set_level(pin, 0);
esp_rom_delay_us(10);
@ -834,16 +841,26 @@ TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]")
// USB D+ pull-up value is default to 1 (USB_SERIAL_JTAG_DP_PULLUP)
// Therefore, when D+ pin's pull-up value is set to 0, it will also clear USB D+ pull-up value to allow
// its full functionality as a normal gpio pin
gpio_config_t input_io = test_init_io(USB_DP_GPIO_NUM);
input_io.mode = GPIO_MODE_INPUT;
input_io.pull_up_en = 0;
input_io.pull_down_en = 1;
gpio_config(&input_io);
const int test_pins[] = {USB_INT_PHY0_DP_GPIO_NUM,
#if CONFIG_IDF_TARGET_ESP32P4 // TODO: Use proper soc_caps macro
USB_INT_PHY1_DP_GPIO_NUM,
#endif
};
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(USB_DP_GPIO_NUM));
for (int i = 0; i < sizeof(test_pins) / sizeof(int); i++) {
int pin = test_pins[i];
gpio_config_t input_io = test_init_io(pin);
input_io.mode = GPIO_MODE_INPUT;
input_io.pull_up_en = 0;
input_io.pull_down_en = 1;
gpio_config(&input_io);
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(pin));
}
}
#endif //SOC_USB_SERIAL_JTAG_SUPPORTED
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO: IDF-7528 Remove when light sleep is supported on ESP32P4
// Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep
TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
{
@ -860,3 +877,4 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
printf("Waked up from light sleep\n");
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO);
}
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)

5
components/driver/test_apps/gpio/main/test_gpio.h
View File

@ -31,6 +31,11 @@ extern "C" {
#define TEST_GPIO_EXT_IN_IO (21)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC208_IDX)
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX)
#else
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)

37
components/esp_rom/include/esp32p4/rom/gpio.h
View File

@ -30,8 +30,8 @@ extern "C" {
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
#define GPIO_FUNC_IN_HIGH 0x38
#define GPIO_FUNC_IN_LOW 0x3C
#define GPIO_FUNC_IN_HIGH 0x3F
#define GPIO_FUNC_IN_LOW 0x3E
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
@ -85,7 +85,7 @@ void gpio_init(void);
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/**
* @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* @brief Change GPIO(32-56) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
@ -111,7 +111,7 @@ void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enabl
uint32_t gpio_input_get(void);
/**
* @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
* @brief Sample the value of GPIO input pins(32-56) and returns a bitmask.
*
* @param None
*
@ -173,7 +173,7 @@ void gpio_intr_ack(uint32_t ack_mask);
void gpio_intr_ack_high(uint32_t ack_mask);
/**
* @brief Set GPIO to wakeup the ESP32.
* @brief Set GPIO to wakeup the ESP32P4.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
@ -185,7 +185,7 @@ void gpio_intr_ack_high(uint32_t ack_mask);
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* @brief disable GPIOs to wakeup the ESP32P4.
* Please do not call this function in SDK.
*
* @param None
@ -197,10 +197,9 @@ void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~0x2f
* gpio == 0x3C, input 0 to signal
* gpio == 0x3A, input nothing to signal
* gpio == 0x38, input 1 to signal
* @param uint32_t gpio : gpio number, 0~56
* gpio == 0x3E, input 0 to signal
* gpio == 0x3F, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
@ -213,7 +212,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~0x2f
* @param uint32_t gpio : gpio number, 0~56
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
@ -229,7 +228,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @return None
*/
@ -238,7 +237,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @param uint32_t drv : 0-3
*
@ -249,7 +248,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @return None
*/
@ -258,7 +257,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @return None
*/
@ -267,7 +266,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @return None
*/
@ -276,7 +275,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @return None
*/
@ -285,7 +284,7 @@ void gpio_pad_hold(uint32_t gpio_num);
/**
* @brief enable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @return None
*/
@ -294,7 +293,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
/**
* @brief disable gpio pad input.
*
* @param uint32_t gpio_num : gpio number, 0~0x2f
* @param uint32_t gpio_num : gpio number, 0~56
*
* @return None
*/

2
components/hal/esp32/include/hal/gpio_ll.h
View File

@ -666,7 +666,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
gpio_ll_func_sel(hw, gpio_num, func);
}
#ifdef __cplusplus

2
components/hal/esp32c2/include/hal/gpio_ll.h
View File

@ -472,7 +472,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
gpio_ll_func_sel(hw, gpio_num, func);
}
/**

8
components/hal/esp32c3/include/hal/gpio_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -55,7 +55,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
if (gpio_num == USB_DP_GPIO_NUM) {
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
@ -276,7 +276,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
// Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) {
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
@ -488,7 +488,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
gpio_ll_func_sel(hw, gpio_num, func);
}
/**

4
components/hal/esp32c6/include/hal/gpio_etm_ll.h
View File

@ -35,7 +35,7 @@ extern "C" {
*/
static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
{
dev->event_chn_cfg[chan].etm_ch0_event_sel = gpio_num;
dev->event_chn_cfg[chan].etm_chn_event_sel = gpio_num;
}
/**
@ -47,7 +47,7 @@ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint3
*/
static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
{
dev->event_chn_cfg[chan].etm_ch0_event_en = enable;
dev->event_chn_cfg[chan].etm_chn_event_en = enable;
}
/**

11
components/hal/esp32c6/include/hal/gpio_ll.h
View File

@ -84,9 +84,9 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_DM_GPIO_NUM instead.
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_DP_GPIO_NUM) {
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
@ -248,6 +248,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
__attribute__((always_inline))
static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
@ -392,7 +393,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
{
return !!(LP_AON.gpio_hold0.gpio_hold0 & GPIO_HOLD_MASK[gpio_num]);
return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num));
}
/**
@ -435,7 +436,7 @@ __attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) {
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
@ -454,7 +455,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
gpio_ll_func_sel(hw, gpio_num, func);
}
/**

4
components/hal/esp32h2/include/hal/gpio_etm_ll.h
View File

@ -35,7 +35,7 @@ extern "C" {
*/
static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
{
dev->etm_event_chn_cfg[chan].etm_ch0_event_sel = gpio_num;
dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num;
}
/**
@ -47,7 +47,7 @@ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint3
*/
static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
{
dev->etm_event_chn_cfg[chan].etm_ch0_event_en = enable;
dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable;
}
/**

27
components/hal/esp32h2/include/hal/gpio_ll.h
View File

@ -83,9 +83,9 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32h2 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_DM_GPIO_NUM instead.
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
if (gpio_num == USB_DP_GPIO_NUM) {
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
@ -290,6 +290,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
__attribute__((always_inline))
static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
{
hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
@ -420,6 +421,24 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num];
}
/**
* @brief Get digital gpio pad hold status.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number, only support output GPIOs
*
* @note caller must ensure that gpio_num is a digital io pad
*
* @return
* - true digital gpio pad is held
* - false digital gpio pad is unheld
*/
__attribute__((always_inline))
static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
{
return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num));
}
/**
* @brief Set pad input to a peripheral signal through the IOMUX.
*
@ -460,7 +479,7 @@ __attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
// Disable USB Serial JTAG if pins 26 or pins 27 needs to select an IOMUX function
if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) {
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
@ -479,7 +498,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
gpio_ll_func_sel(hw, gpio_num, func);
}
/**

365
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -19,15 +19,18 @@
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/pmu_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/io_mux_struct.h"
#include "soc/hp_system_struct.h"
#include "soc/lp_iomux_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/pmu_struct.h"
#include "soc/usb_serial_jtag_struct.h"
#include "soc/usb_wrap_struct.h"
#include "soc/clk_tree_defs.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
//TODO: IDF-6509
#ifdef __cplusplus
extern "C" {
#endif
@ -35,8 +38,11 @@ extern "C" {
// Get GPIO hardware instance with giving gpio num
#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0))
#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_LL_INTR0_ENA (BIT(0))
// #define GPIO_LL_INTR1_ENA (BIT(1)) // TODO: IDF-7995
// #define GPIO_LL_INTR2_ENA (BIT(2))
// #define GPIO_LL_INTR3_ENA (BIT(3))
/**
* @brief Enable pull-up on GPIO.
*
@ -45,7 +51,7 @@ extern "C" {
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
IOMUX.gpio[gpio_num].fun_wpu = 1;
}
/**
@ -57,7 +63,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
IOMUX.gpio[gpio_num].fun_wpu = 0;
}
/**
@ -68,7 +74,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
IOMUX.gpio[gpio_num].fun_wpd = 1;
}
/**
@ -80,7 +86,22 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
abort();
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32p4 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
// One more noticable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately.
// We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
if (gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
} else if (gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) {
USB_WRAP.otg_conf.pad_pull_override = 1;
USB_WRAP.otg_conf.dp_pullup = 0;
}
IOMUX.gpio[gpio_num].fun_wpd = 0;
}
/**
@ -92,7 +113,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
{
// hw->pin[gpio_num].int_type = intr_type;
hw->pin[gpio_num].int_type = intr_type;
}
/**
@ -105,8 +126,8 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
// *status = hw->intr_0; // need to check
abort();
(void)core_id; // TODO: IDF-7995 There are 4 interrupt sources for GPIO on P4. New feature! Need to fix this function later.
*status = hw->intr_0.int_0;
}
/**
@ -119,7 +140,8 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
__attribute__((always_inline))
static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
*status = 0;
(void)core_id; // TODO: IDF-7995 There are 4 interrupt sources for GPIO on P4. New feature! Need to fix this function later.
*status = hw->intr1_0.int1_0;
}
/**
@ -131,7 +153,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
__attribute__((always_inline))
static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
{
// hw->status_w1tc = mask;
hw->status_w1tc.status_w1tc = mask;
}
/**
@ -143,7 +165,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
__attribute__((always_inline))
static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
{
// P4 needs check
hw->status1_w1tc.status1_w1tc = mask;
}
/**
@ -156,8 +178,8 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
__attribute__((always_inline))
static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num)
{
// HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
// GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr
(void)core_id;
hw->pin[gpio_num].int_ena = GPIO_LL_INTR0_ENA; //enable for GPIO_INTR0 interrupt signal TODO: IDF-7995
}
/**
@ -169,7 +191,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
__attribute__((always_inline))
static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// hw->pin[gpio_num].int_ena = 0; //disable GPIO intr
hw->pin[gpio_num].int_ena = 0; //disable GPIO intr
}
/**
@ -181,7 +203,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].fun_ie = 0;
}
/**
@ -192,7 +214,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].fun_ie = 1;
}
/**
@ -203,6 +225,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].filter_en = 1;
}
/**
@ -213,6 +236,55 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
IOMUX.gpio[gpio_num].filter_en = 0;
}
/**
* @brief Enable GPIO hysteresis
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO0-15
LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys |= bit_mask;
} else {
if (gpio_num < 32 + 16) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low |= (bit_mask >> 16);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high |= (bit_mask >> (32 + 16));
}
}
}
/**
* @brief Disable GPIO hysteresis
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO0-15
LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys &= ~bit_mask;
} else {
if (gpio_num < 32 + 16) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low &= ~(bit_mask >> 16);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high &= ~(bit_mask >> (32 + 16));
}
}
}
/**
@ -224,10 +296,13 @@ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// hw->enable_w1tc = (0x1 << gpio_num);
// // Ensure no other output signal is routed via GPIO matrix to this pin
// REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
// CORE_GPIO_OUT_PAD_OUT0_IDX);
if (gpio_num < 32) {
hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
} else {
hw->enable1_w1tc.enable1_w1tc = (0x1 << (gpio_num - 32));
}
// Ensure no other output signal is routed via GPIO matrix to this pin
hw->func_out_sel_cfg[gpio_num].out_sel = SIG_GPIO_OUT_IDX;
}
/**
@ -236,9 +311,14 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
__attribute__((always_inline))
static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// hw->enable_w1ts = (0x1 << gpio_num);
if (gpio_num < 32) {
hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
} else {
hw->enable1_w1ts.enable1_w1ts = (0x1 << (gpio_num - 32));
}
}
/**
@ -249,7 +329,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// hw->pin[gpio_num].pad_driver = 0;
hw->pin[gpio_num].pad_driver = 0;
}
/**
@ -260,7 +340,7 @@ static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// hw->pin[gpio_num].pad_driver = 1;
hw->pin[gpio_num].pad_driver = 1;
}
/**
@ -273,11 +353,19 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
{
// if (level) {
// hw->out_w1ts = (1 << gpio_num);
// } else {
// hw->out_w1tc = (1 << gpio_num);
// }
if (level) {
if (gpio_num < 32) {
hw->out_w1ts.out_w1ts = (1 << gpio_num);
} else {
hw->out1_w1ts.out1_w1ts = (1 << (gpio_num - 32));
}
} else {
if (gpio_num < 32) {
hw->out_w1tc.out_w1tc = (1 << gpio_num);
} else {
hw->out1_w1tc.out1_w1tc = (1 << (gpio_num - 32));
}
}
}
/**
@ -294,8 +382,11 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t
*/
static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
{
// return (hw->in >> gpio_num) & 0x1;
abort();
if (gpio_num < 32) {
return (hw->in.in_data_next >> gpio_num) & 0x1;
} else {
return (hw->in1.in1_data_next >> (gpio_num - 32)) & 0x1;
}
}
/**
@ -306,7 +397,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
// hw->pin[gpio_num].wakeup_enable = 0x1;
hw->pin[gpio_num].wakeup_enable = 1;
}
/**
@ -317,7 +408,7 @@ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
// hw->pin[gpio_num].wakeup_enable = 0;
hw->pin[gpio_num].wakeup_enable = 0;
}
/**
@ -329,7 +420,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
IOMUX.gpio[gpio_num].fun_drv = strength;
}
/**
@ -341,27 +432,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
}
/**
* @brief Enable all digital gpio pads hold function during Deep-sleep.
*
* @param hw Peripheral GPIO hardware instance address.
*/
static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
{
//SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
}
/**
* @brief Disable all digital gpio pads hold function during Deep-sleep.
*
* @param hw Peripheral GPIO hardware instance address.
*/
static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
{
//SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
*strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
}
/**
@ -372,6 +443,20 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
LP_IOMUX.lp_pad_hold.reg_lp_gpio_hold |= bit_mask;
} else {
if (gpio_num < 32 + 16) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low |= (bit_mask >> 16);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + 16));
}
}
}
/**
@ -382,6 +467,51 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
LP_IOMUX.lp_pad_hold.reg_lp_gpio_hold &= ~bit_mask;
} else {
if (gpio_num < 32 + 16) {
// GPIO 16-47
HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low &= ~(bit_mask >> 16);
} else {
// GPIO 48-56
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + 16));
}
}
}
/**
* @brief Get digital gpio pad hold status.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number, only support output GPIOs
*
* @note caller must ensure that gpio_num is a digital io pad
*
* @return
* - true digital gpio pad is held
* - false digital gpio pad is unheld
*/
__attribute__((always_inline))
static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
{
// TODO: IDF-7480 Fix magic number 16 with proper macro
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
abort();
} else {
if (gpio_num < 32 + 16) {
// GPIO 16-47
return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> 16));
} else {
// GPIO 48-56
return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + 16)));
}
}
}
/**
@ -394,8 +524,8 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
{
// hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
// PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4));
hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
IOMUX.gpio[gpio].fun_ie = 1;
}
/**
@ -406,8 +536,13 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
//CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE);
// Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function
// P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately.
// We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
} else if (pin_name == IO_MUX_GPIO26_REG || pin_name == IO_MUX_GPIO27_REG) {
USB_WRAP.otg_conf.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(pin_name, func);
}
@ -422,11 +557,15 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
__attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
// Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
if (gpio_num == 18 || gpio_num == 19) {
//CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE);
// Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function
// P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately.
// We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
if (gpio_num == USB_USJ_INT_PHY_DM_GPIO_NUM || gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
} else if (gpio_num == USB_OTG_INT_PHY_DM_GPIO_NUM || gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) {
USB_WRAP.otg_conf.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
IOMUX.gpio[gpio_num].mcu_sel = func;
}
/**
@ -440,9 +579,9 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
*/
static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
{
// hw->func_out_sel_cfg[gpio_num].oe_sel = 0;
// hw->func_out_sel_cfg[gpio_num].oe_inv_sel = oen_inv;
// gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_func_sel(hw, gpio_num, func);
}
/**
@ -452,6 +591,37 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
*/
static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
{
switch (src) {
case SOC_MOD_CLK_XTAL:
HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 0;
break;
case SOC_MOD_CLK_PLL_F80M:
HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 1;
break;
default:
// Unsupported IO_MUX clock source
HAL_ASSERT(false);
}
}
/**
* @brief Force hold digital io pad.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_hold_all(void)
{
// WT flag, it gets self-cleared after the configuration is done
PMU.imm_pad_hold_all.tie_high_hp_pad_hold_all = 1;
}
/**
* @brief Force unhold digital io pad.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_unhold_all(void)
{
// WT flag, it gets self-cleared after the configuration is done
PMU.imm_pad_hold_all.tie_low_hp_pad_hold_all = 1;
}
/**
@ -462,7 +632,7 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].slp_sel = 1;
}
/**
@ -474,7 +644,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].slp_sel = 0;
}
/**
@ -485,7 +655,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpu = 0;
}
/**
@ -496,7 +666,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpu = 1;
}
/**
@ -507,7 +677,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpd = 1;
}
/**
@ -518,7 +688,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_wpd = 0;
}
/**
@ -529,7 +699,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_ie = 0;
}
/**
@ -540,7 +710,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_ie = 1;
}
/**
@ -551,7 +721,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpio[gpio_num].mcu_oe = 0;
}
/**
@ -562,40 +732,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
}
/**
* @brief Enable GPIO deep-sleep wake-up function.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number.
* @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
*/
static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
{
}
/**
* @brief Disable GPIO deep-sleep wake-up function.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
*/
static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
}
/**
* @brief Get the status of whether an IO is used for deep-sleep wake-up.
*
* @param hw Peripheral GPIO hardware instance address.
* @param gpio_num GPIO number
* @return True if the pin is enabled to wake up from deep-sleep
*/
static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
{
return 0;
IOMUX.gpio[gpio_num].mcu_oe = 1;
}
#ifdef __cplusplus

2
components/hal/esp32s2/include/hal/gpio_ll.h
View File

@ -487,7 +487,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
gpio_ll_func_sel(hw, gpio_num, func);
}
/**

10
components/hal/esp32s3/include/hal/gpio_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -57,8 +57,8 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin
// which should be checked is USB_DM_GPIO_NUM instead.
if (gpio_num == USB_DP_GPIO_NUM) {
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
@ -291,7 +291,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) {
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
@ -506,7 +506,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
{
hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
gpio_ll_func_sel(hw, gpio_num, func);
}
/**

8
components/hal/esp32s3/include/hal/rtc_io_ll.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -63,7 +63,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
{
if (func == RTCIO_FUNC_RTC) {
// Disable USB Serial JTAG if pin 19 or pin 20 needs to select the rtc function
if (rtcio_num == rtc_io_num_map[USB_DM_GPIO_NUM] || rtcio_num == rtc_io_num_map[USB_DP_GPIO_NUM]) {
if (rtcio_num == rtc_io_num_map[USB_INT_PHY0_DM_GPIO_NUM] || rtcio_num == rtc_io_num_map[USB_INT_PHY0_DP_GPIO_NUM]) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
SENS.sar_peri_clk_gate_conf.iomux_clk_en = 1;
@ -202,8 +202,8 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num)
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin
// which should be checked is USB_DM_GPIO_NUM instead.
if (rtcio_num == USB_DP_GPIO_NUM) {
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
if (rtcio_num == USB_INT_PHY0_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}

8
components/hal/gpio_hal.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -33,11 +33,13 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num)
#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num, bool enable)
{
#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num);
#endif
if (enable) {
gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num);
gpio_ll_pin_input_hysteresis_enable(hal->dev, gpio_num);
} else {
gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num);
gpio_ll_pin_input_hysteresis_disable(hal->dev, gpio_num);
}
}

2
components/hal/include/hal/gpio_hal.h
View File

@ -497,6 +497,7 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, uint32_t gpio_n
*/
void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num, bool enable);
#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
/**
* @brief Set gpio hysteresis enable/disable by efuse.
*
@ -504,6 +505,7 @@ void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num,
* @param gpio_num GPIO number
*/
#define gpio_hal_hysteresis_from_efuse(hal, gpio_num) gpio_ll_pin_input_hysteresis_ctrl_sel_efuse((hal)->dev, gpio_num)
#endif
#endif // SOC_GPIO_SUPPORT_PIN_HYS_FILTER
#ifdef __cplusplus

16
components/hal/include/hal/gpio_types.h
View File

@ -68,6 +68,14 @@ typedef enum {
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
#define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG
#define GPIO_PIN_REG_48 IO_MUX_GPIO48_REG
#define GPIO_PIN_REG_49 IO_MUX_GPIO49_REG
#define GPIO_PIN_REG_50 IO_MUX_GPIO50_REG
#define GPIO_PIN_REG_51 IO_MUX_GPIO51_REG
#define GPIO_PIN_REG_52 IO_MUX_GPIO52_REG
#define GPIO_PIN_REG_53 IO_MUX_GPIO53_REG
#define GPIO_PIN_REG_54 IO_MUX_GPIO54_REG
#define GPIO_PIN_REG_55 IO_MUX_GPIO55_REG
#define GPIO_PIN_REG_56 IO_MUX_GPIO56_REG
typedef enum {
GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */
@ -121,14 +129,18 @@ typedef enum {
GPIO_DRIVE_CAP_MAX,
} gpio_drive_cap_t;
#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
/**
* @brief Available option for configuring hysteresis feature of GPIOs
*/
typedef enum {
#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
GPIO_HYS_CTRL_EFUSE = 0, /*!< Pad input hysteresis ctrl by efuse */
GPIO_HYS_SOFT_ENABLE = 1, /*!< Pad input hysteresis enable by software */
GPIO_HYS_SOFT_DISABLE = 2, /*!< Pad input hysteresis disable by software */
#endif
GPIO_HYS_SOFT_DISABLE, /*!< Pad input hysteresis disable by software */
GPIO_HYS_SOFT_ENABLE, /*!< Pad input hysteresis enable by software */
} gpio_hys_ctrl_mode_t;
#endif
#ifdef __cplusplus
}

4
components/soc/esp32c3/include/soc/io_mux_reg.h
View File

@ -137,8 +137,8 @@
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define USB_DM_GPIO_NUM 18
#define USB_DP_GPIO_NUM 19
#define USB_INT_PHY0_DM_GPIO_NUM 18
#define USB_INT_PHY0_DP_GPIO_NUM 19
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 21

10
components/soc/esp32c6/include/soc/gpio_ext_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -98,15 +98,15 @@ typedef union {
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0;
/** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:5;
uint32_t etm_chn_event_sel:5;
uint32_t reserved_5:2;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t etm_chn_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;

4
components/soc/esp32c6/include/soc/io_mux_reg.h
View File

@ -143,8 +143,8 @@
#define SD_DATA2_GPIO_NUM 22
#define SD_DATA3_GPIO_NUM 23
#define USB_DM_GPIO_NUM 12
#define USB_DP_GPIO_NUM 13
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define EXT_OSC_SLOW_GPIO_NUM 0

10
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@ -415,13 +415,17 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
default y
config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
int
default 8
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
int
default 8
config SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
bool
default y
config SOC_GPIO_SUPPORT_ETM
bool

8
components/soc/esp32h2/include/soc/gpio_ext_struct.h
View File

@ -140,15 +140,15 @@ typedef union {
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0;
/** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:5;
uint32_t etm_chn_event_sel:5;
uint32_t reserved_5:2;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t etm_chn_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;

4
components/soc/esp32h2/include/soc/io_mux_reg.h
View File

@ -155,8 +155,8 @@
#define SPI_D_GPIO_NUM 20
#define SPI_Q_GPIO_NUM 16
#define USB_DM_GPIO_NUM 26
#define USB_DP_GPIO_NUM 27
#define USB_INT_PHY0_DM_GPIO_NUM 26
#define USB_INT_PHY0_DP_GPIO_NUM 27
#define EXT_OSC_SLOW_GPIO_NUM 13

3
components/soc/esp32h2/include/soc/soc_caps.h
View File

@ -180,8 +180,9 @@
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 28
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
#define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse
// GPIO peripheral has the ETM extension
#define SOC_GPIO_SUPPORT_ETM 1

121
components/soc/esp32p4/gpio_periph.c
View File

@ -5,15 +5,128 @@
*/
#include "soc/gpio_periph.h"
#include "esp_assert.h"
const uint32_t GPIO_PIN_MUX_REG[] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
IO_MUX_GPIO2_REG,
IO_MUX_GPIO3_REG,
IO_MUX_GPIO4_REG,
IO_MUX_GPIO5_REG,
IO_MUX_GPIO6_REG,
IO_MUX_GPIO7_REG,
IO_MUX_GPIO8_REG,
IO_MUX_GPIO9_REG,
IO_MUX_GPIO10_REG,
IO_MUX_GPIO11_REG,
IO_MUX_GPIO12_REG,
IO_MUX_GPIO13_REG,
IO_MUX_GPIO14_REG,
IO_MUX_GPIO15_REG,
IO_MUX_GPIO16_REG,
IO_MUX_GPIO17_REG,
IO_MUX_GPIO18_REG,
IO_MUX_GPIO19_REG,
IO_MUX_GPIO20_REG,
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,
IO_MUX_GPIO24_REG,
IO_MUX_GPIO25_REG,
IO_MUX_GPIO26_REG,
IO_MUX_GPIO27_REG,
IO_MUX_GPIO28_REG,
IO_MUX_GPIO29_REG,
IO_MUX_GPIO30_REG,
IO_MUX_GPIO31_REG,
IO_MUX_GPIO32_REG,
IO_MUX_GPIO33_REG,
IO_MUX_GPIO34_REG,
IO_MUX_GPIO35_REG,
IO_MUX_GPIO36_REG,
IO_MUX_GPIO37_REG,
IO_MUX_GPIO38_REG,
IO_MUX_GPIO39_REG,
IO_MUX_GPIO40_REG,
IO_MUX_GPIO41_REG,
IO_MUX_GPIO42_REG,
IO_MUX_GPIO43_REG,
IO_MUX_GPIO44_REG,
IO_MUX_GPIO45_REG,
IO_MUX_GPIO46_REG,
IO_MUX_GPIO47_REG,
IO_MUX_GPIO48_REG,
IO_MUX_GPIO49_REG,
IO_MUX_GPIO50_REG,
IO_MUX_GPIO51_REG,
IO_MUX_GPIO52_REG,
IO_MUX_GPIO53_REG,
IO_MUX_GPIO54_REG,
IO_MUX_GPIO55_REG,
IO_MUX_GPIO56_REG,
};
// _Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
ESP_STATIC_ASSERT(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
const uint32_t GPIO_HOLD_MASK[] = {
BIT(0), //GPIO0 // LP_IOMUX_LP_PAD_HOLD_REG
BIT(1), //GPIO1
BIT(2), //GPIO2
BIT(3), //GPIO3
BIT(4), //GPIO4
BIT(5), //GPIO5
BIT(6), //GPIO6
BIT(7), //GPIO7
BIT(8), //GPIO8
BIT(9), //GPIO9
BIT(10), //GPIO10
BIT(11), //GPIO11
BIT(12), //GPIO12
BIT(13), //GPIO13
BIT(14), //GPIO14
BIT(15), //GPIO15
BIT(0), //GPIO16 // HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG
BIT(1), //GPIO17
BIT(2), //GPIO18
BIT(3), //GPIO19
BIT(4), //GPIO20
BIT(5), //GPIO21
BIT(6), //GPIO22
BIT(7), //GPIO23
BIT(8), //GPIO24
BIT(9), //GPIO25
BIT(10), //GPIO26
BIT(11), //GPIO27
BIT(12), //GPIO28
BIT(13), //GPIO29
BIT(14), //GPIO30
BIT(15), //GPIO31
BIT(16), //GPIO32
BIT(17), //GPIO33
BIT(18), //GPIO34
BIT(19), //GPIO35
BIT(20), //GPIO36
BIT(21), //GPIO37
BIT(22), //GPIO38
BIT(23), //GPIO39
BIT(24), //GPIO40
BIT(25), //GPIO41
BIT(26), //GPIO42
BIT(27), //GPIO43
BIT(28), //GPIO44
BIT(29), //GPIO45
BIT(30), //GPIO46
BIT(31), //GPIO47
BIT(0), //GPIO48 // HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG
BIT(1), //GPIO49
BIT(2), //GPIO50
BIT(3), //GPIO51
BIT(4), //GPIO52
BIT(5), //GPIO53
BIT(6), //GPIO54
BIT(7), //GPIO55
BIT(8), //GPIO56
};
// _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
ESP_STATIC_ASSERT(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

18
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@ -257,7 +257,11 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 64
default 57
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_ETM_EVENTS_PER_GROUP
int
@ -273,7 +277,7 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0xFFFFFFFFFFFFFFFF
default 0x01FFFFFFFFFFFFFF
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
@ -281,7 +285,15 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000007FFFFF00
default 0x01FFFFFFFFFF0000
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int

3
components/soc/esp32p4/include/soc/clkout_channel.h
View File

@ -1,9 +1,8 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//Copied from C6, please check. TODO: IDF-7526
// ESP32P4 CLKOUT signals has no corresponding iomux pins

1939
components/soc/esp32p4/include/soc/gpio_ext_reg.h
View File

File diff suppressed because it is too large Load Diff

136
components/soc/esp32p4/include/soc/gpio_ext_struct.h
View File

@ -16,18 +16,18 @@ extern "C" {
*/
typedef union {
struct {
/** sd0_in : R/W; bitpos: [7:0]; default: 0;
/** duty : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t sd0_in:8;
/** sd0_prescale : R/W; bitpos: [15:8]; default: 255;
uint32_t duty:8;
/** prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t sd0_prescale:8;
uint32_t prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpiosd_sigmadeltan_reg_t;
} gpio_sigmadelta_chn_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
@ -45,7 +45,7 @@ typedef union {
uint32_t spi_swap:1;
};
uint32_t val;
} gpiosd_sigmadelta_misc_reg_t;
} gpio_sigmadelta_misc_reg_t;
/** Group: Glitch filter Configure Registers */
@ -54,26 +54,26 @@ typedef union {
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
/** filter_chn_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
uint32_t filter_chn_en:1;
/** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
uint32_t filter_chn_input_io_num:6;
/** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
uint32_t filter_chn_window_thres:6;
/** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t filter_chn_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
} gpiosd_glitch_filter_chn_reg_t;
} gpio_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
@ -82,19 +82,19 @@ typedef union {
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
/** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:6;
uint32_t etm_chn_event_sel:6;
uint32_t reserved_6:1;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t etm_chn_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpiosd_etm_event_chn_cfg_reg_t;
} gpio_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -139,7 +139,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p0_cfg_reg_t;
} gpio_etm_task_p0_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -184,7 +184,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p1_cfg_reg_t;
} gpio_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -229,7 +229,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p2_cfg_reg_t;
} gpio_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -274,7 +274,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p3_cfg_reg_t;
} gpio_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -319,7 +319,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p4_cfg_reg_t;
} gpio_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -364,7 +364,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p5_cfg_reg_t;
} gpio_etm_task_p5_cfg_reg_t;
/** Type of etm_task_p6_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -409,7 +409,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p6_cfg_reg_t;
} gpio_etm_task_p6_cfg_reg_t;
/** Type of etm_task_p7_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -454,7 +454,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p7_cfg_reg_t;
} gpio_etm_task_p7_cfg_reg_t;
/** Type of etm_task_p8_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -499,7 +499,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p8_cfg_reg_t;
} gpio_etm_task_p8_cfg_reg_t;
/** Type of etm_task_p9_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -544,7 +544,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p9_cfg_reg_t;
} gpio_etm_task_p9_cfg_reg_t;
/** Type of etm_task_p10_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -589,7 +589,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p10_cfg_reg_t;
} gpio_etm_task_p10_cfg_reg_t;
/** Type of etm_task_p11_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -634,7 +634,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p11_cfg_reg_t;
} gpio_etm_task_p11_cfg_reg_t;
/** Type of etm_task_p12_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -679,7 +679,7 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p12_cfg_reg_t;
} gpio_etm_task_p12_cfg_reg_t;
/** Type of etm_task_p13_cfg register
* Etm Configure Register to decide which GPIO been chosen
@ -715,7 +715,7 @@ typedef union {
uint32_t reserved_20:12;
};
uint32_t val;
} gpiosd_etm_task_p13_cfg_reg_t;
} gpio_etm_task_p13_cfg_reg_t;
/** Group: Version Register */
@ -724,46 +724,62 @@ typedef union {
*/
typedef union {
struct {
/** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
/** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952;
* Version control register.
*/
uint32_t gpio_sd_date:28;
uint32_t gpio_ext_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_version_reg_t;
} gpio_ext_version_reg_t;
typedef struct gpio_sd_dev_t {
volatile gpio_sigmadelta_chn_reg_t channel[8];
uint32_t reserved_020;
volatile gpio_sigmadelta_misc_reg_t misc;
} gpio_sd_dev_t;
typedef struct gpio_glitch_filter_dev_t {
volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8];
} gpio_glitch_filter_dev_t;
typedef struct gpio_etm_dev_t {
volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpio_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpio_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpio_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpio_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpio_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpio_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpio_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
volatile gpio_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
volatile gpio_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
volatile gpio_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
volatile gpio_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
volatile gpio_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
volatile gpio_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
volatile gpio_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
} gpio_etm_dev_t;
typedef struct {
volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
uint32_t reserved_020;
volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
volatile gpio_sd_dev_t sigma_delta;
uint32_t reserved_028[2];
volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
volatile gpio_glitch_filter_dev_t glitch_filter;
uint32_t reserved_050[4];
volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
volatile gpio_etm_dev_t etm;
uint32_t reserved_0d8[9];
volatile gpiosd_version_reg_t version;
} gpiosd_dev_t;
volatile gpio_ext_version_reg_t version;
} gpio_ext_dev_t;
extern gpio_sd_dev_t SDM;
extern gpio_glitch_filter_dev_t GLITCH_FILTER;
extern gpio_etm_dev_t GPIO_ETM;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus
_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
#endif
#ifdef __cplusplus

63
components/soc/esp32p4/include/soc/gpio_num.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,9 +10,68 @@
extern "C" {
#endif
// TODO: IDF-6509
/**
* @brief GPIO number
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
GPIO_NUM_3 = 3, /*!< GPIO3, input and output */
GPIO_NUM_4 = 4, /*!< GPIO4, input and output */
GPIO_NUM_5 = 5, /*!< GPIO5, input and output */
GPIO_NUM_6 = 6, /*!< GPIO6, input and output */
GPIO_NUM_7 = 7, /*!< GPIO7, input and output */
GPIO_NUM_8 = 8, /*!< GPIO8, input and output */
GPIO_NUM_9 = 9, /*!< GPIO9, input and output */
GPIO_NUM_10 = 10, /*!< GPIO10, input and output */
GPIO_NUM_11 = 11, /*!< GPIO11, input and output */
GPIO_NUM_12 = 12, /*!< GPIO12, input and output */
GPIO_NUM_13 = 13, /*!< GPIO13, input and output */
GPIO_NUM_14 = 14, /*!< GPIO14, input and output */
GPIO_NUM_15 = 15, /*!< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
GPIO_NUM_28 = 28, /*!< GPIO28, input and output */
GPIO_NUM_29 = 29, /*!< GPIO29, input and output */
GPIO_NUM_30 = 30, /*!< GPIO30, input and output */
GPIO_NUM_31 = 31, /*!< GPIO31, input and output */
GPIO_NUM_32 = 32, /*!< GPIO32, input and output */
GPIO_NUM_33 = 33, /*!< GPIO33, input and output */
GPIO_NUM_34 = 34, /*!< GPIO34, input and output */
GPIO_NUM_35 = 35, /*!< GPIO35, input and output */
GPIO_NUM_36 = 36, /*!< GPIO36, input and output */
GPIO_NUM_37 = 37, /*!< GPIO37, input and output */
GPIO_NUM_38 = 38, /*!< GPIO38, input and output */
GPIO_NUM_39 = 39, /*!< GPIO39, input and output */
GPIO_NUM_40 = 40, /*!< GPIO40, input and output */
GPIO_NUM_41 = 41, /*!< GPIO41, input and output */
GPIO_NUM_42 = 42, /*!< GPIO42, input and output */
GPIO_NUM_43 = 43, /*!< GPIO43, input and output */
GPIO_NUM_44 = 44, /*!< GPIO44, input and output */
GPIO_NUM_45 = 45, /*!< GPIO45, input and output */
GPIO_NUM_46 = 46, /*!< GPIO46, input and output */
GPIO_NUM_47 = 47, /*!< GPIO47, input and output */
GPIO_NUM_48 = 48, /*!< GPIO48, input and output */
GPIO_NUM_49 = 49, /*!< GPIO49, input and output */
GPIO_NUM_50 = 50, /*!< GPIO50, input and output */
GPIO_NUM_51 = 51, /*!< GPIO51, input and output */
GPIO_NUM_52 = 52, /*!< GPIO52, input and output */
GPIO_NUM_53 = 53, /*!< GPIO53, input and output */
GPIO_NUM_54 = 54, /*!< GPIO54, input and output */
GPIO_NUM_55 = 55, /*!< GPIO55, input and output */
GPIO_NUM_56 = 56, /*!< GPIO56, input and output */
GPIO_NUM_MAX,
} gpio_num_t;

2
components/soc/esp32p4/include/soc/gpio_pins.h
View File

@ -11,6 +11,8 @@
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x3F)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3E)
#ifdef __cplusplus
}

27
components/soc/esp32p4/include/soc/gpio_reg.h
View File

@ -3710,33 +3710,6 @@ extern "C" {
#define GPIO_PIN56_INT_ENA_V 0x0000001FU
#define GPIO_PIN56_INT_ENA_S 13
/** GPIO_FUNC0_IN_SEL_CFG_REG register
* GPIO input function configuration register
*/
#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 63;
* set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
* high level. s=0x3E: set this port always low level.
*/
#define GPIO_FUNC0_IN_SEL 0x0000003FU
#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S)
#define GPIO_FUNC0_IN_SEL_V 0x0000003FU
#define GPIO_FUNC0_IN_SEL_S 0
/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
* set this bit to invert input signal. 1:invert. 0:not invert.
*/
#define GPIO_FUNC0_IN_INV_SEL (BIT(6))
#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S)
#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U
#define GPIO_FUNC0_IN_INV_SEL_S 6
/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0;
* set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
*/
#define GPIO_SIG0_IN_SEL (BIT(7))
#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S)
#define GPIO_SIG0_IN_SEL_V 0x00000001U
#define GPIO_SIG0_IN_SEL_S 7
/** GPIO_FUNC1_IN_SEL_CFG_REG register
* GPIO input function configuration register
*/

5440
components/soc/esp32p4/include/soc/gpio_struct.h
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File diff suppressed because it is too large Load Diff

3
components/soc/esp32p4/include/soc/hp_system_struct.h
View File

@ -1915,7 +1915,7 @@ typedef union {
} hp_system_gpio_o_hys_ctrl1_reg_t;
typedef struct {
typedef struct hp_system_dev_t {
volatile hp_system_ver_date_reg_t sys_ver_date;
volatile hp_system_clk_en_reg_t clk_en;
uint32_t reserved_008[2];
@ -2023,6 +2023,7 @@ typedef struct {
volatile hp_system_peri_mem_clk_force_on_reg_t peri_mem_clk_force_on;
} hp_system_dev_t;
extern hp_system_dev_t HP_SYSTEM;
#ifndef __cplusplus
_Static_assert(sizeof(hp_system_dev_t) == 0x1e4, "Invalid size of hp_system_dev_t structure");

84
components/soc/esp32p4/include/soc/io_mux_reg.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -63,6 +63,11 @@
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
#define FILTER_EN (BIT(15))
#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
#define FILTER_EN_V 1
#define FILTER_EN_S 15
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
@ -75,14 +80,16 @@
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_GPIO0
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_GPIO1
@ -142,13 +149,15 @@
#define IO_MUX_GPIO55_REG PERIPHS_IO_MUX_U_PAD_GPIO55
#define IO_MUX_GPIO56_REG PERIPHS_IO_MUX_U_PAD_GPIO56
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
// TODO: IDF-7499, IDF-7495
// Pins defined here are all wrong (Ln153-164). On P4, these pins are individual pins, don't use normal GPIO pins anymore.
// Please check iomux_mspi_pin_struct/reg.h
#define SPI_CS1_GPIO_NUM 26
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
@ -191,44 +200,37 @@
#define PSRAM_DP15_DEBUG_GPIO_NUM 46
#define PSRAM_DQS1_DEBUG_GPIO_NUM 47
#define SD_CLK_GPIO_NUM 12
#define SD_CMD_GPIO_NUM 11
#define SD_DATA0_GPIO_NUM 13
#define SD_DATA1_GPIO_NUM 14
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define SD_CLK_GPIO_NUM 43
#define SD_CMD_GPIO_NUM 44
#define SD_DATA0_GPIO_NUM 39
#define SD_DATA1_GPIO_NUM 40
#define SD_DATA2_GPIO_NUM 41
#define SD_DATA3_GPIO_NUM 42
#define SD_DATA4_GPIO_NUM 45
#define SD_DATA5_GPIO_NUM 46
#define SD_DATA6_GPIO_NUM 47
#define SD_DATA7_GPIO_NUM 48
#define MAX_RTC_GPIO_NUM 15
#define USB_INT_PHY0_DM_GPIO_NUM 24
#define USB_INT_PHY0_DP_GPIO_NUM 25
#define USB_INT_PHY1_DM_GPIO_NUM 26
#define USB_INT_PHY1_DP_GPIO_NUM 27
// We would fix the USB PHY usage on P4: PHY0 -> USJ, PHY1 -> USB_OTG
#define USB_USJ_INT_PHY_DM_GPIO_NUM USB_INT_PHY0_DM_GPIO_NUM
#define USB_USJ_INT_PHY_DP_GPIO_NUM USB_INT_PHY0_DP_GPIO_NUM
#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
// #define EXT_OSC_SLOW_GPIO_NUM 1 // TODO: IDF-7526
#define MAX_RTC_GPIO_NUM 16
#define MAX_PAD_GPIO_NUM 56
#define MAX_GPIO_NUM 56
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 IO_MUX_CLK_OUT3
#define CLK_OUT3_V IO_MUX_CLK_OUT3_V
#define CLK_OUT3_S IO_MUX_CLK_OUT3_S
#define CLK_OUT3_M IO_MUX_CLK_OUT3_M
#define CLK_OUT2 IO_MUX_CLK_OUT2
#define CLK_OUT2_V IO_MUX_CLK_OUT2_V
#define CLK_OUT2_S IO_MUX_CLK_OUT2_S
#define CLK_OUT2_M IO_MUX_CLK_OUT2_M
#define CLK_OUT1 IO_MUX_CLK_OUT1
#define CLK_OUT1_V IO_MUX_CLK_OUT1_V
#define CLK_OUT1_S IO_MUX_CLK_OUT1_S
#define CLK_OUT1_M IO_MUX_CLK_OUT1_M
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x4)

113
components/soc/esp32p4/include/soc/io_mux_struct.h
View File

@ -10,45 +10,92 @@
extern "C" {
#endif
/** Type of GPIO register
* IOMUX gpio configuration register
*/
typedef union {
struct {
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* output enable on sleep mode
*/
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* io sleep mode enable. set 1 to enable sleep mode.
*/
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* pull-down enable on sleep mode
*/
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* pull-up enable on sleep mode
*/
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* input enable on sleep mode
*/
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [5:6]; default: 0;
* select drive strenth on sleep mode
*/
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* pull-down enable
*/
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* pull-up enable
*/
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* input enable
*/
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [10:11]; default: 2;
* select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
*/
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [12:14]; default: 0;
* 0:select function0, 1:select function1 ...
*/
uint32_t mcu_sel:3;
/** filter_en : R/W; bitpos: [15]; default: 0;
* input filter enable
*/
uint32_t filter_en:1;
uint32_t reserved16 :16;
};
uint32_t val;
} iomux_gpio_reg_t;
typedef volatile struct iomux_dev_s {
/** Type of date register
* IOMUX version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 2101794;
* version register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} iomux_date_reg_t;
typedef struct iomux_dev_t {
uint32_t reserved_0;
union {
struct {
uint32_t mcu_oe : 1; /*output enable on sleep mode*/
uint32_t slp_sel : 1; /*io sleep mode enable. set 1 to enable sleep mode.*/
uint32_t mcu_wpd : 1; /*pull-down enable on sleep mode*/
uint32_t mcu_wpu : 1; /*pull-up enable on sleep mode*/
uint32_t mcu_ie : 1; /*input enable on sleep mode*/
uint32_t mcu_drv : 2; /*select drive strenth on sleep mode*/
uint32_t fun_wpd : 1; /*pull-down enable*/
uint32_t fun_wpu : 1; /*pull-up enable*/
uint32_t fun_ie : 1; /*input enable*/
uint32_t fun_drv : 2; /*select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA*/
uint32_t mcu_sel : 3; /*0:select function0, 1:select function1 ...*/
uint32_t filter_en : 1; /*input filter enable*/
uint32_t reserved16 : 16;
};
uint32_t val;
} gpio[57];
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
union {
struct {
uint32_t reg_date : 28; /*csv date*/
uint32_t reserved28 : 4;
};
uint32_t val;
} io_mux_date;
volatile iomux_gpio_reg_t gpio[57];
uint32_t reserved_e8[7];
volatile iomux_date_reg_t date;
} iomux_dev_t;
extern iomux_dev_t IOMUX;
#ifndef __cplusplus
_Static_assert(sizeof(iomux_dev_t) == 0x108, "Invalid size of iomux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

8
components/soc/esp32p4/include/soc/lp_gpio_sig_map.h
View File

@ -1,10 +1,9 @@
/*
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SOC_LP_GPIO_SIG_MAP_H_
#define _SOC_LP_GPIO_SIG_MAP_H_
#pragma once
#define LP_I2C_SCL_PAD_IN_IDX 0
#define LP_I2C_SCL_PAD_OUT_IDX 0
@ -51,5 +50,4 @@
#define LP_PROBE_TOP_OUT14_IDX 28
#define LP_PROBE_TOP_OUT15_IDX 29
#define PROBE_CHAIN_CLK_PAD_OUT_IDX 30
#define GPIO_MAP_DATE_IDX 0x230323
#endif /* _SOC_LP_GPIO_SIG_MAP_H_ */
#define LP_GPIO_MAP_DATE_IDX 0x230323

1
components/soc/esp32p4/include/soc/lp_iomux_struct.h
View File

@ -950,6 +950,7 @@ typedef struct lp_iomux_dev_t {
volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
} lp_iomux_dev_t;
extern lp_iomux_dev_t LP_IOMUX;
#ifndef __cplusplus
_Static_assert(sizeof(lp_iomux_dev_t) == 0x54, "Invalid size of lp_iomux_dev_t structure");

2
components/soc/esp32p4/include/soc/pmu_struct.h
View File

@ -3733,7 +3733,7 @@ typedef union {
} pmu_xtal_slp_reg_t;
typedef struct {
typedef struct pmu_dev_t {
volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power;
volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func;
volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb;

24
components/soc/esp32p4/include/soc/soc_caps.h
View File

@ -171,30 +171,36 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-P4 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 64
#define SOC_GPIO_PIN_COUNT 57
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: IDF-7481
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: IDF-7481
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
// #define SOC_GPIO_SUPPORT_ETM 1 //TODO: IDF-7841
#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
// Target has the full LP IO subsystem
// On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~7 on ESP32P4 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO0~15 on ESP32P4 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: IDF-7480
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFFFFF)
#define SOC_GPIO_VALID_GPIO_MASK (0x01FFFFFFFFFFFFFF)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_56)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x01FFFFFFFFFF0000ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
// #define SOC_RTCIO_PIN_COUNT 8 //TODO: IDF-7480
// #define SOC_RTCIO_PIN_COUNT 16 //TODO: IDF-7480
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 //TODO: IDF-7480
// #define SOC_RTCIO_HOLD_SUPPORTED 1 //TODO: IDF-7480
// #define SOC_RTCIO_WAKE_SUPPORTED 1 //TODO: IDF-7480

3
components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h
View File

@ -996,7 +996,7 @@ typedef union {
} usb_serial_jtag_date_reg_t;
typedef struct {
typedef struct usb_serial_jtag_dev_t {
volatile usb_serial_jtag_ep1_reg_t ep1;
volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
volatile usb_serial_jtag_int_raw_reg_t int_raw;
@ -1034,6 +1034,7 @@ typedef struct {
volatile usb_serial_jtag_date_reg_t date;
} usb_serial_jtag_dev_t;
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
#ifndef __cplusplus
_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure");

0
components/soc/esp32p4/include/soc/usbwrap_reg.h → components/soc/esp32p4/include/soc/usb_wrap_reg.h
View File

3
components/soc/esp32p4/include/soc/usbwrap_struct.h → components/soc/esp32p4/include/soc/usb_wrap_struct.h
View File

@ -122,12 +122,13 @@ typedef union {
} usb_wrap_date_reg_t;
typedef struct {
typedef struct usb_wrap_dev_t {
volatile usb_wrap_otg_conf_reg_t otg_conf;
uint32_t reserved_004[254];
volatile usb_wrap_date_reg_t date;
} usb_wrap_dev_t;
extern usb_wrap_dev_t USB_WRAP;
#ifndef __cplusplus
_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");

9
components/soc/esp32p4/ld/esp32p4.peripherals.ld
View File

@ -50,9 +50,12 @@ PROVIDE ( DS = 0x50094000 );
PROVIDE ( HMAC = 0x50095000 );
PROVIDE ( ECDSA = 0x50096000 );
PROVIDE ( IOMUX = 0x500e1000 );
PROVIDE ( GPIO = 0x500E0000 );
PROVIDE ( SIGMADELTA = 0x500E0F00 );
PROVIDE ( GPIO_EXT = 0x500E0F00 );
PROVIDE ( SDM = 0x500E0F00 );
PROVIDE ( GLITCH_FILTER = 0x500E0F30 );
PROVIDE ( GPIO_ETM = 0x500E0F60 );
PROVIDE ( IOMUX = 0x500E1000 );
PROVIDE ( HP_SYSTEM = 0x500E5000 );
PROVIDE ( HP_SYS_CLKRST = 0x500E6000 );
@ -92,3 +95,5 @@ PROVIDE ( I3C_SLV = 0x500DB000 );
PROVIDE ( PPA = 0x50087000 );
PROVIDE ( DMA2D = 0x50088000 );
PROVIDE ( JPEG = 0x50086000 );
PROVIDE ( USB_WRAP = 0x50080000 );

4
components/soc/esp32s3/include/soc/io_mux_reg.h
View File

@ -161,8 +161,8 @@
#define SD_DATA1_GPIO_NUM 14
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define USB_DM_GPIO_NUM 19
#define USB_DP_GPIO_NUM 20
#define USB_INT_PHY0_DM_GPIO_NUM 19
#define USB_INT_PHY0_DP_GPIO_NUM 20
#define XTAL32K_P_GPIO_NUM 15
#define XTAL32K_N_GPIO_NUM 16

14
docs/en/api-reference/peripherals/gpio.rst
View File

@ -56,13 +56,19 @@ GPIO Summary
GPIO Hysteresis Filter
----------------------
{IDF_TARGET_NAME} support the hardware hysteresis of the input pin, which can reduce the GPIO interrupt shoot by accident due to unstable sampling when the input voltage is near the critical of logic 0 and 1, especially when the input logic level conversion is slow or the voltage setup time is too long.
{IDF_TARGET_NAME} support the hardware hysteresis of the input pin, which can reduce the GPIO interrupt shoot by accident due to unstable sampling when the input voltage is near the criteria of logic 0 and 1, especially when the input logic level conversion is slow or the voltage setup time is too long.
Each pin can enable hysteresis function independently. By default, it controlled by eFuse and been closed, but it can also be enabled or disabled by software manually. You can select the hysteresis control mode by configuring :cpp:member:`gpio_config_t::hys_ctrl_mode`.
.. only:: SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
.. note::
Each pin can enable hysteresis function independently. By default, it controlled by eFuse and been closed, but it can also be enabled or disabled by software manually. You can select the hysteresis control mode by configuring :cpp:member:`gpio_config_t::hys_ctrl_mode`. Hysteresis control mode is set along with all the other GPIO configurations in :cpp:func:`gpio_config`.
When the hysteresis function is controlled by eFuse, this feature can still be controlled independently for each pin, you need to `burn the eFuse <https://docs.espressif.com/projects/esptool/en/latest/esp32/espefuse/index.html>`_ to enable the hysteresis function on specific GPIO additionally.
.. note::
When the hysteresis function is controlled by eFuse, this feature can still be controlled independently for each pin, you need to `burn the eFuse <https://docs.espressif.com/projects/esptool/en/latest/esp32/espefuse/index.html>`_ to enable the hysteresis function on specific GPIO additionally.
.. only:: not SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
Each pin can enable hysteresis function independently. By default, the function is not enabled. You can select the hysteresis control mode by configuring :cpp:member:`gpio_config_t::hys_ctrl_mode`. Hysteresis control mode is set along with all the other GPIO configurations in :cpp:func:`gpio_config`.
Application Example

5
docs/en/api-reference/peripherals/gpio/esp32h2.inc
View File

@ -62,11 +62,11 @@ The table below provides more information on pin usage, and please note the comm
- Strapping pin, RTC
* - GPIO10
- Analog comparator reference voltage
- ANA_CMPR_CH0 reference voltage
- RTC
* - GPIO11
- Analog comparator input (non-inverting)
- ANA_CMPR_CH0 input (non-inverting)
- RTC
* - GPIO12
@ -139,7 +139,6 @@ The table below provides more information on pin usage, and please note the comm
- SPI0/1: GPIO15-21 are usually used for SPI flash and not recommended for other uses.
- USB-Serial-JTAG: GPIO 26 and 27 are used by USB-Serial-JTAG by default. In order to use them as GPIOs, USB-Serial-JTAG will be disabled by the drivers.
- For chip variants with an SiP flash built in, GPIO15 ~ GPIO21 are dedicated to connecting the SiP flash and are not fan-out to the external pins. In addition, GPIO6 ~ GPIO7 are also not fan-out to the external pins. In conclusion, only GPIO0~ GPIO5, GPIO8~ GPIO14, GPIO22~ GPIO27 are available to users.
- For chip variant without SiP flash, apart from the flash IOs mentioned above, GPIO22 is not fan-out to the external pin, thus they're not available to users.
- RTC: GPIO7-14 can be used to wake up the chip from Deep-sleep mode. Other GPIOs can only wake up the chip from Light-sleep mode. For more information, please refer to Section :ref:`Wakeup Sources<api-reference-wakeup-source>`.
---

315
docs/en/api-reference/peripherals/gpio/esp32p4.inc Normal file
View File

@ -0,0 +1,315 @@
.. This file gets included from other .rst files in this folder.
.. It contains target-specific snippets.
.. Comments and '---' lines act as delimiters.
..
.. This is necessary mainly because RST doesn't support substitutions
.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
.. These code blocks can be moved back to the main .rst files, with target-specific
.. file names being replaced by substitutions.
.. gpio-summary
The {IDF_TARGET_NAME} chip features 57 physical GPIO pins (GPIO0 ~ GPIO56). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- Analog Function
- LP GPIO
- Comments
* - GPIO0
-
- LP_GPIO0
-
* - GPIO1
-
- LP_GPIO1
-
* - GPIO2
- TOUCH0
- LP_GPIO2
-
* - GPIO3
- TOUCH1
- LP_GPIO3
-
* - GPIO4
- TOUCH2
- LP_GPIO4
-
* - GPIO5
- TOUCH3
- LP_GPIO5
-
* - GPIO6
- TOUCH4
- LP_GPIO6
-
* - GPIO7
- TOUCH5
- LP_GPIO7
-
* - GPIO8
- TOUCH6
- LP_GPIO8
-
* - GPIO9
- TOUCH7
- LP_GPIO9
-
* - GPIO10
- TOUCH8
- LP_GPIO10
-
* - GPIO11
- TOUCH9
- LP_GPIO11
-
* - GPIO12
- TOUCH10
- LP_GPIO12
-
* - GPIO13
- TOUCH11
- LP_GPIO13
-
* - GPIO14
- TOUCH12
- LP_GPIO14
-
* - GPIO15
- TOUCH13
- LP_GPIO15
-
* - GPIO16
- ADC1_CH0
-
-
* - GPIO17
- ADC1_CH1
-
-
* - GPIO18
- ADC1_CH2
-
-
* - GPIO19
- ADC1_CH3
-
-
* - GPIO20
- ADC1_CH4
-
-
* - GPIO21
- ADC1_CH5
-
-
* - GPIO22
- ADC1_CH6
-
-
* - GPIO23
- ADC1_CH7
-
-
* - GPIO24
-
-
-
* - GPIO25
-
-
-
* - GPIO26
-
-
-
* - GPIO27
-
-
-
* - GPIO28
-
-
-
* - GPIO29
-
-
-
* - GPIO30
-
-
-
* - GPIO31
-
-
-
* - GPIO32
-
-
-
* - GPIO33
-
-
-
* - GPIO34
-
-
- Strapping pin
* - GPIO35
-
-
- Strapping pin
* - GPIO36
-
-
- Strapping pin
* - GPIO37
-
-
- Strapping pin
* - GPIO38
-
-
- Strapping pin
* - GPIO39
-
-
-
* - GPIO40
-
-
-
* - GPIO41
-
-
-
* - GPIO42
-
-
-
* - GPIO43
-
-
-
* - GPIO44
-
-
-
* - GPIO45
-
-
-
* - GPIO46
-
-
-
* - GPIO47
-
-
-
* - GPIO48
-
-
-
* - GPIO49
- ADC1_CH8
-
-
* - GPIO50
- ADC1_CH9
-
-
* - GPIO51
- ADC1_CH10, ANA_CMPR_CH0 reference voltage
-
-
* - GPIO52
- ADC1_CH11, ANA_CMPR_CH0 input (non-inverting)
-
-
* - GPIO53
- ADC1_CH12, ANA_CMPR_CH1 reference voltage
-
-
* - GPIO54
- ADC1_CH13, ANA_CMPR_CH1 input (non-inverting)
-
-
* - GPIO55
-
-
-
* - GPIO56
-
-
-
.. note::
- Strapping pin: GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 are strapping pins. For more infomation, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
- USB-JTAG: GPIO 24 and 25 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
---

13
docs/zh_CN/api-reference/peripherals/gpio.rst
View File

@ -58,11 +58,18 @@ GPIO 汇总
{IDF_TARGET_NAME} 支持输入引脚的硬件迟滞，这可以减少由于输入电压在逻辑 0、1 临界值附近时采样不稳定造成的 GPIO 中断误触，尤其是当输入逻辑电平转换较慢，电平建立时间较长时。
每个引脚可以独立启用迟滞功能。默认情况下，它由 eFuse 控制，且处于关闭状态，但也可以由软件控制启用或禁用。您可以通过配置 :cpp:member:`gpio_config_t::hys_ctrl_mode` 来选择迟滞控制模式。
.. only:: SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
.. note::
每个引脚可以独立启用迟滞功能。默认情况下，它由 eFuse 控制，且处于关闭状态，但也可以由软件控制启用或禁用。您可以通过配置 :cpp:member:`gpio_config_t::hys_ctrl_mode` 来选择迟滞控制模式。迟滞控制模式会和其余 GPIO 配置一起在 :cpp:func:`gpio_config` 中生效。
当迟滞功能由 eFuse 控制时，仍然可以独立的控制每个引脚的该功能，您需要 `烧断 eFuse <https://docs.espressif.com/projects/esptool/en/latest/esp32/espefuse/index.html>`_ ，以在特定 GPIO上 启用迟滞功能。
.. note::
当迟滞功能由 eFuse 控制时，仍然可以独立的控制每个引脚的该功能，您需要 `烧断 eFuse <https://docs.espressif.com/projects/esptool/en/latest/esp32/espefuse/index.html>`_ ，以在特定 GPIO上 启用迟滞功能。
.. only:: not SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE
每个引脚可以独立启用迟滞功能。默认情况下，它处于关闭状态。您可以通过配置 :cpp:member:`gpio_config_t::hys_ctrl_mode` 来选择启用与否。迟滞控制模式会和其余 GPIO 配置一起在 :cpp:func:`gpio_config` 中生效。
应用示例

5
docs/zh_CN/api-reference/peripherals/gpio/esp32h2.inc
View File

@ -64,11 +64,11 @@
- Strapping 管脚，RTC
* - GPIO10
- 模拟比较器外部参考电压
- ANA_CMPR_CH0 外部参考电压
- RTC
* - GPIO11
- 模拟比较器同相输入
- ANA_CMPR_CH0 同相输入
- RTC
* - GPIO12
@ -141,7 +141,6 @@
- SPI0/1: GPIO15-21 通常用于 SPI flash, 不推荐用于其他用途。
- USB-Serial-JTAG: GPIO26 和 GPIO27 默认用于 USB-Serial-JTAG。用做 GPIO 时驱动程序将禁用 USB-Serial-JTAG。
- 对于合封了 flash 的芯片型号， GPIO15 ~ GPIO21 专门用于连接该 flash, 并未引出至芯片管脚。且 GPIO6 ~ GPIO7 也未引出至芯片管脚，用户不可用。用户可配置使用其他剩余的 19 个 GPIO 管脚, 编号为: GPIO0 ~ GPIO5、GPIO8 ~ GPIO14、GPIO22 ~ GPIO27。
- 对于未合封 flash 的芯片型号， 除了以上提到的给 Flash 专用的 GPIO 以外, GPIO22 也并未引出至芯片管脚，用户不可用。
- RTC：GPIO7-14 可用于将芯片从 Deep-sleep 模式中唤醒，其他 GPIO 仅能将芯片从 Light-sleep 模式中唤醒。更多信息请参考 :ref:`唤醒源<api-reference-wakeup-source>` 章节。
---

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.. This file gets included from other .rst files in this folder.
.. It contains target-specific snippets.
.. Comments and '---' lines act as delimiters.
..
.. This is necessary mainly because RST doesn't support substitutions
.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
.. These code blocks can be moved back to the main .rst files, with target-specific
.. file names being replaced by substitutions.
.. gpio-summary
{IDF_TARGET_NAME} 芯片具有 57 个物理 GPIO 管脚（GPIO0 ~ GPIO56）。
每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- 模拟功能
- LP GPIO
- 注释
* - GPIO0
-
- LP_GPIO0
-
* - GPIO1
-
- LP_GPIO1
-
* - GPIO2
- TOUCH0
- LP_GPIO2
-
* - GPIO3
- TOUCH1
- LP_GPIO3
-
* - GPIO4
- TOUCH2
- LP_GPIO4
-
* - GPIO5
- TOUCH3
- LP_GPIO5
-
* - GPIO6
- TOUCH4
- LP_GPIO6
-
* - GPIO7
- TOUCH5
- LP_GPIO7
-
* - GPIO8
- TOUCH6
- LP_GPIO8
-
* - GPIO9
- TOUCH7
- LP_GPIO9
-
* - GPIO10
- TOUCH8
- LP_GPIO10
-
* - GPIO11
- TOUCH9
- LP_GPIO11
-
* - GPIO12
- TOUCH10
- LP_GPIO12
-
* - GPIO13
- TOUCH11
- LP_GPIO13
-
* - GPIO14
- TOUCH12
- LP_GPIO14
-
* - GPIO15
- TOUCH13
- LP_GPIO15
-
* - GPIO16
- ADC1_CH0
-
-
* - GPIO17
- ADC1_CH1
-
-
* - GPIO18
- ADC1_CH2
-
-
* - GPIO19
- ADC1_CH3
-
-
* - GPIO20
- ADC1_CH4
-
-
* - GPIO21
- ADC1_CH5
-
-
* - GPIO22
- ADC1_CH6
-
-
* - GPIO23
- ADC1_CH7
-
-
* - GPIO24
-
-
-
* - GPIO25
-
-
-
* - GPIO26
-
-
-
* - GPIO27
-
-
-
* - GPIO28
-
-
-
* - GPIO29
-
-
-
* - GPIO30
-
-
-
* - GPIO31
-
-
-
* - GPIO32
-
-
-
* - GPIO33
-
-
-
* - GPIO34
-
-
- Strapping 管脚
* - GPIO35
-
-
- Strapping 管脚
* - GPIO36
-
-
- Strapping 管脚
* - GPIO37
-
-
- Strapping 管脚
* - GPIO38
-
-
- Strapping 管脚
* - GPIO39
-
-
-
* - GPIO40
-
-
-
* - GPIO41
-
-
-
* - GPIO42
-
-
-
* - GPIO43
-
-
-
* - GPIO44
-
-
-
* - GPIO45
-
-
-
* - GPIO46
-
-
-
* - GPIO47
-
-
-
* - GPIO48
-
-
-
* - GPIO49
- ADC1_CH8
-
-
* - GPIO50
- ADC1_CH9
-
-
* - GPIO51
- ADC1_CH10，ANA_CMPR_CH0 外部参考电压
-
-
* - GPIO52
- ADC1_CH11，ANA_CMPR_CH0 同相输入
-
-
* - GPIO53
- ADC1_CH12，ANA_CMPR_CH1 外部参考电压
-
-
* - GPIO54
- ADC1_CH13，ANA_CMPR_CH1 同相输入
-
-
* - GPIO55
-
-
-
* - GPIO56
-
-
-
.. note::
- Strapping 管脚：GPIO34, GPIO35、GPIO36、GPIO37 和 GPIO38 是 Strapping 管脚。更多信息请参考 `ESP32-P4 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
- USB-JTAG：GPIO24 和 GPIO25 默认用于 USB-JTAG。用做 GPIO 时驱动程序将禁用 USB-JTAG。
---