From be9afeac86f5081c23044f8aa9e7492ad9d9a87a Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Tue, 18 Jul 2023 17:44:14 +0800 Subject: [PATCH] feat(gpio): add support for ESP32P4 --- components/driver/gpio/gpio.c | 8 +- .../driver/test_apps/gpio/main/test_gpio.c | 52 +- .../driver/test_apps/gpio/main/test_gpio.h | 5 + components/esp_rom/include/esp32p4/rom/gpio.h | 37 +- components/hal/esp32/include/hal/gpio_ll.h | 2 +- components/hal/esp32c2/include/hal/gpio_ll.h | 2 +- components/hal/esp32c3/include/hal/gpio_ll.h | 8 +- .../hal/esp32c6/include/hal/gpio_etm_ll.h | 4 +- components/hal/esp32c6/include/hal/gpio_ll.h | 11 +- .../hal/esp32h2/include/hal/gpio_etm_ll.h | 4 +- components/hal/esp32h2/include/hal/gpio_ll.h | 27 +- components/hal/esp32p4/include/hal/gpio_ll.h | 365 +- components/hal/esp32s2/include/hal/gpio_ll.h | 2 +- components/hal/esp32s3/include/hal/gpio_ll.h | 10 +- .../hal/esp32s3/include/hal/rtc_io_ll.h | 8 +- components/hal/gpio_hal.c | 8 +- components/hal/include/hal/gpio_hal.h | 2 + components/hal/include/hal/gpio_types.h | 16 +- .../soc/esp32c3/include/soc/io_mux_reg.h | 4 +- .../soc/esp32c6/include/soc/gpio_ext_struct.h | 10 +- .../soc/esp32c6/include/soc/io_mux_reg.h | 4 +- .../esp32h2/include/soc/Kconfig.soc_caps.in | 10 +- .../soc/esp32h2/include/soc/gpio_ext_struct.h | 8 +- .../soc/esp32h2/include/soc/io_mux_reg.h | 4 +- components/soc/esp32h2/include/soc/soc_caps.h | 3 +- components/soc/esp32p4/gpio_periph.c | 121 +- .../esp32p4/include/soc/Kconfig.soc_caps.in | 18 +- .../soc/esp32p4/include/soc/clkout_channel.h | 3 +- .../soc/esp32p4/include/soc/gpio_ext_reg.h | 1939 +++--- .../soc/esp32p4/include/soc/gpio_ext_struct.h | 136 +- components/soc/esp32p4/include/soc/gpio_num.h | 63 +- .../soc/esp32p4/include/soc/gpio_pins.h | 2 + components/soc/esp32p4/include/soc/gpio_reg.h | 27 - .../soc/esp32p4/include/soc/gpio_struct.h | 5440 +---------------- .../esp32p4/include/soc/hp_system_struct.h | 3 +- .../soc/esp32p4/include/soc/io_mux_reg.h | 84 +- .../soc/esp32p4/include/soc/io_mux_struct.h | 113 +- .../soc/esp32p4/include/soc/lp_gpio_sig_map.h | 8 +- .../soc/esp32p4/include/soc/lp_iomux_struct.h | 1 + .../soc/esp32p4/include/soc/pmu_struct.h | 2 +- components/soc/esp32p4/include/soc/soc_caps.h | 24 +- .../include/soc/usb_serial_jtag_struct.h | 3 +- .../soc/{usbwrap_reg.h => usb_wrap_reg.h} | 0 .../{usbwrap_struct.h => usb_wrap_struct.h} | 3 +- .../soc/esp32p4/ld/esp32p4.peripherals.ld | 9 +- .../soc/esp32s3/include/soc/io_mux_reg.h | 4 +- docs/en/api-reference/peripherals/gpio.rst | 14 +- .../peripherals/gpio/esp32h2.inc | 5 +- .../peripherals/gpio/esp32p4.inc | 315 + docs/zh_CN/api-reference/peripherals/gpio.rst | 13 +- .../peripherals/gpio/esp32h2.inc | 5 +- .../peripherals/gpio/esp32p4.inc | 317 + 52 files changed, 2499 insertions(+), 6787 deletions(-) rename components/soc/esp32p4/include/soc/{usbwrap_reg.h => usb_wrap_reg.h} (100%) rename components/soc/esp32p4/include/soc/{usbwrap_struct.h => usb_wrap_struct.h} (98%) create mode 100644 docs/en/api-reference/peripherals/gpio/esp32p4.inc create mode 100644 docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc diff --git a/components/driver/gpio/gpio.c b/components/driver/gpio/gpio.c index 762515c483..3cea507013 100644 --- a/components/driver/gpio/gpio.c +++ b/components/driver/gpio/gpio.c @@ -257,11 +257,13 @@ static esp_err_t gpio_hysteresis_disable(gpio_num_t gpio_num) return ESP_OK; } +#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE static esp_err_t gpio_hysteresis_by_efuse(gpio_num_t gpio_num) { gpio_hal_hysteresis_from_efuse(gpio_context.gpio_hal, gpio_num); return ESP_OK; } +#endif #endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) @@ -416,10 +418,14 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig) gpio_hysteresis_enable(io_num); } else if (pGPIOConfig->hys_ctrl_mode == GPIO_HYS_SOFT_DISABLE) { gpio_hysteresis_disable(io_num); - } else { + } +#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE + else { gpio_hysteresis_by_efuse(io_num); } +#endif #endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER + /* By default, all the pins have to be configured as GPIO pins. */ gpio_hal_iomux_func_sel(io_reg, PIN_FUNC_GPIO); } diff --git a/components/driver/test_apps/gpio/main/test_gpio.c b/components/driver/test_apps/gpio/main/test_gpio.c index b62b90c729..59a54bfd2d 100644 --- a/components/driver/test_apps/gpio/main/test_gpio.c +++ b/components/driver/test_apps/gpio/main/test_gpio.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -791,21 +791,28 @@ TEST_CASE("GPIO_drive_capability_test", "[gpio][ignore]") prompt_to_continue("If this test finishes"); } -#if SOC_USB_SERIAL_JTAG_SUPPORTED +#if SOC_USB_SERIAL_JTAG_SUPPORTED // TODO: replace with a more proper soc_caps (USB_PHY_INTERNAL_NUM > 0) TEST_CASE("GPIO_input_and_output_of_USB_pins_test", "[gpio]") { - const int test_pins[] = {USB_DP_GPIO_NUM, USB_DM_GPIO_NUM}; - gpio_config_t io_conf = { - .intr_type = GPIO_INTR_DISABLE, - .mode = GPIO_MODE_INPUT_OUTPUT, - .pin_bit_mask = (BIT64(test_pins[0]) | BIT64(test_pins[1])), - .pull_down_en = 0, - .pull_up_en = 0, - }; - gpio_config(&io_conf); + const int test_pins[] = {USB_INT_PHY0_DP_GPIO_NUM, + USB_INT_PHY0_DM_GPIO_NUM, +#if CONFIG_IDF_TARGET_ESP32P4 // TODO: Use proper soc_caps macro + USB_INT_PHY1_DP_GPIO_NUM, + USB_INT_PHY1_DM_GPIO_NUM +#endif + }; for (int i = 0; i < sizeof(test_pins) / sizeof(int); i++) { int pin = test_pins[i]; + gpio_config_t io_conf = { + .intr_type = GPIO_INTR_DISABLE, + .mode = GPIO_MODE_INPUT_OUTPUT, + .pin_bit_mask = BIT64(pin), + .pull_down_en = 0, + .pull_up_en = 0, + }; + gpio_config(&io_conf); + // test pin gpio_set_level(pin, 0); esp_rom_delay_us(10); @@ -834,16 +841,26 @@ TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]") // USB D+ pull-up value is default to 1 (USB_SERIAL_JTAG_DP_PULLUP) // Therefore, when D+ pin's pull-up value is set to 0, it will also clear USB D+ pull-up value to allow // its full functionality as a normal gpio pin - gpio_config_t input_io = test_init_io(USB_DP_GPIO_NUM); - input_io.mode = GPIO_MODE_INPUT; - input_io.pull_up_en = 0; - input_io.pull_down_en = 1; - gpio_config(&input_io); + const int test_pins[] = {USB_INT_PHY0_DP_GPIO_NUM, +#if CONFIG_IDF_TARGET_ESP32P4 // TODO: Use proper soc_caps macro + USB_INT_PHY1_DP_GPIO_NUM, +#endif + }; - TEST_ASSERT_EQUAL_INT(0, gpio_get_level(USB_DP_GPIO_NUM)); + for (int i = 0; i < sizeof(test_pins) / sizeof(int); i++) { + int pin = test_pins[i]; + gpio_config_t input_io = test_init_io(pin); + input_io.mode = GPIO_MODE_INPUT; + input_io.pull_up_en = 0; + input_io.pull_down_en = 1; + gpio_config(&input_io); + + TEST_ASSERT_EQUAL_INT(0, gpio_get_level(pin)); + } } #endif //SOC_USB_SERIAL_JTAG_SUPPORTED +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO: IDF-7528 Remove when light sleep is supported on ESP32P4 // Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]") { @@ -860,3 +877,4 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]") printf("Waked up from light sleep\n"); TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO); } +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...) diff --git a/components/driver/test_apps/gpio/main/test_gpio.h b/components/driver/test_apps/gpio/main/test_gpio.h index 47ce8330f4..971b3fb4c4 100644 --- a/components/driver/test_apps/gpio/main/test_gpio.h +++ b/components/driver/test_apps/gpio/main/test_gpio.h @@ -31,6 +31,11 @@ extern "C" { #define TEST_GPIO_EXT_IN_IO (21) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC208_IDX) +#elif CONFIG_IDF_TARGET_ESP32P4 +#define TEST_GPIO_EXT_OUT_IO (2) +#define TEST_GPIO_EXT_IN_IO (3) +#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) +#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX) #else #define TEST_GPIO_EXT_OUT_IO (2) #define TEST_GPIO_EXT_IN_IO (3) diff --git a/components/esp_rom/include/esp32p4/rom/gpio.h b/components/esp_rom/include/esp32p4/rom/gpio.h index 87fc43e0ca..c5439256eb 100644 --- a/components/esp_rom/include/esp32p4/rom/gpio.h +++ b/components/esp_rom/include/esp32p4/rom/gpio.h @@ -30,8 +30,8 @@ extern "C" { #define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) #define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) -#define GPIO_FUNC_IN_HIGH 0x38 -#define GPIO_FUNC_IN_LOW 0x3C +#define GPIO_FUNC_IN_HIGH 0x3F +#define GPIO_FUNC_IN_LOW 0x3E #define GPIO_ID_IS_PIN_REGISTER(reg_id) \ ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) @@ -85,7 +85,7 @@ void gpio_init(void); void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); /** - * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). + * @brief Change GPIO(32-56) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). * There is no particular ordering guaranteed; so if the order of writes is significant, * calling code should divide a single call into multiple calls. * @@ -111,7 +111,7 @@ void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enabl uint32_t gpio_input_get(void); /** - * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask. + * @brief Sample the value of GPIO input pins(32-56) and returns a bitmask. * * @param None * @@ -173,7 +173,7 @@ void gpio_intr_ack(uint32_t ack_mask); void gpio_intr_ack_high(uint32_t ack_mask); /** - * @brief Set GPIO to wakeup the ESP32. + * @brief Set GPIO to wakeup the ESP32P4. * Please do not call this function in SDK. * * @param uint32_t i: gpio number. @@ -185,7 +185,7 @@ void gpio_intr_ack_high(uint32_t ack_mask); void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); /** - * @brief disable GPIOs to wakeup the ESP32. + * @brief disable GPIOs to wakeup the ESP32P4. * Please do not call this function in SDK. * * @param None @@ -197,10 +197,9 @@ void gpio_pin_wakeup_disable(void); /** * @brief set gpio input to a signal, one gpio can input to several signals. * - * @param uint32_t gpio : gpio number, 0~0x2f - * gpio == 0x3C, input 0 to signal - * gpio == 0x3A, input nothing to signal - * gpio == 0x38, input 1 to signal + * @param uint32_t gpio : gpio number, 0~56 + * gpio == 0x3E, input 0 to signal + * gpio == 0x3F, input 1 to signal * * @param uint32_t signal_idx : signal index. * @@ -213,7 +212,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); /** * @brief set signal output to gpio, one signal can output to several gpios. * - * @param uint32_t gpio : gpio number, 0~0x2f + * @param uint32_t gpio : gpio number, 0~56 * * @param uint32_t signal_idx : signal index. * signal_idx == 0x100, cancel output put to the gpio @@ -229,7 +228,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_ /** * @brief Select pad as a gpio function from IOMUX. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @return None */ @@ -238,7 +237,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num); /** * @brief Set pad driver capability. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @param uint32_t drv : 0-3 * @@ -249,7 +248,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); /** * @brief Pull up the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @return None */ @@ -258,7 +257,7 @@ void gpio_pad_pullup(uint32_t gpio_num); /** * @brief Pull down the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @return None */ @@ -267,7 +266,7 @@ void gpio_pad_pulldown(uint32_t gpio_num); /** * @brief Unhold the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @return None */ @@ -276,7 +275,7 @@ void gpio_pad_unhold(uint32_t gpio_num); /** * @brief Hold the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @return None */ @@ -285,7 +284,7 @@ void gpio_pad_hold(uint32_t gpio_num); /** * @brief enable gpio pad input. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @return None */ @@ -294,7 +293,7 @@ void gpio_pad_input_enable(uint32_t gpio_num); /** * @brief disable gpio pad input. * - * @param uint32_t gpio_num : gpio number, 0~0x2f + * @param uint32_t gpio_num : gpio number, 0~56 * * @return None */ diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index b81842de75..6c15657aa2 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -666,7 +666,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_func_sel(hw, gpio_num, func); } #ifdef __cplusplus diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h index 9672ac9679..c38ce47241 100644 --- a/components/hal/esp32c2/include/hal/gpio_ll.h +++ b/components/hal/esp32c2/include/hal/gpio_ll.h @@ -472,7 +472,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_func_sel(hw, gpio_num, func); } /** diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index e14d5d4cc6..1bc8655ceb 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -55,7 +55,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value // USB DP pin is default to PU enabled - if (gpio_num == USB_DP_GPIO_NUM) { + if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); } @@ -276,7 +276,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function - if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { + if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); @@ -488,7 +488,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_func_sel(hw, gpio_num, func); } /** diff --git a/components/hal/esp32c6/include/hal/gpio_etm_ll.h b/components/hal/esp32c6/include/hal/gpio_etm_ll.h index 6d380b27ae..eb311e09dc 100644 --- a/components/hal/esp32c6/include/hal/gpio_etm_ll.h +++ b/components/hal/esp32c6/include/hal/gpio_etm_ll.h @@ -35,7 +35,7 @@ extern "C" { */ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) { - dev->event_chn_cfg[chan].etm_ch0_event_sel = gpio_num; + dev->event_chn_cfg[chan].etm_chn_event_sel = gpio_num; } /** @@ -47,7 +47,7 @@ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint3 */ static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) { - dev->event_chn_cfg[chan].etm_ch0_event_en = enable; + dev->event_chn_cfg[chan].etm_chn_event_en = enable; } /** diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h index e92c1bc332..827dc43aa2 100644 --- a/components/hal/esp32c6/include/hal/gpio_ll.h +++ b/components/hal/esp32c6/include/hal/gpio_ll.h @@ -84,9 +84,9 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value // USB DP pin is default to PU enabled // Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin - // which should be checked is USB_DM_GPIO_NUM instead. + // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. // TODO: read the specific efuse with efuse_ll.h - if (gpio_num == USB_DP_GPIO_NUM) { + if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); } @@ -248,6 +248,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num) { hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); @@ -392,7 +393,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) { - return !!(LP_AON.gpio_hold0.gpio_hold0 & GPIO_HOLD_MASK[gpio_num]); + return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num)); } /** @@ -435,7 +436,7 @@ __attribute__((always_inline)) static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function - if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { + if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); @@ -454,7 +455,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func); + gpio_ll_func_sel(hw, gpio_num, func); } /** diff --git a/components/hal/esp32h2/include/hal/gpio_etm_ll.h b/components/hal/esp32h2/include/hal/gpio_etm_ll.h index 49da6692ba..57101ba37f 100644 --- a/components/hal/esp32h2/include/hal/gpio_etm_ll.h +++ b/components/hal/esp32h2/include/hal/gpio_etm_ll.h @@ -35,7 +35,7 @@ extern "C" { */ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) { - dev->etm_event_chn_cfg[chan].etm_ch0_event_sel = gpio_num; + dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num; } /** @@ -47,7 +47,7 @@ static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint3 */ static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) { - dev->etm_event_chn_cfg[chan].etm_ch0_event_en = enable; + dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable; } /** diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h index e999d4e9f8..2aeb5ce22b 100644 --- a/components/hal/esp32h2/include/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/hal/gpio_ll.h @@ -83,9 +83,9 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num) // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value // USB DP pin is default to PU enabled // Note that esp32h2 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin - // which should be checked is USB_DM_GPIO_NUM instead. + // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. // TODO: read the specific efuse with efuse_ll.h - if (gpio_num == USB_DP_GPIO_NUM) { + if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); } @@ -290,6 +290,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num) { hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); @@ -420,6 +421,24 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num) LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num]; } +/** + * @brief Get digital gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + return !!(LP_AON.gpio_hold0.gpio_hold0 & BIT(gpio_num)); +} + /** * @brief Set pad input to a peripheral signal through the IOMUX. * @@ -460,7 +479,7 @@ __attribute__((always_inline)) static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { // Disable USB Serial JTAG if pins 26 or pins 27 needs to select an IOMUX function - if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { + if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); @@ -479,7 +498,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func); + gpio_ll_func_sel(hw, gpio_num, func); } /** diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index c4800c118a..7a9117d00f 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,15 +19,18 @@ #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/gpio_struct.h" -#include "soc/pmu_reg.h" -#include "soc/usb_serial_jtag_reg.h" +#include "soc/io_mux_struct.h" +#include "soc/hp_system_struct.h" +#include "soc/lp_iomux_struct.h" +#include "soc/hp_sys_clkrst_struct.h" +#include "soc/pmu_struct.h" +#include "soc/usb_serial_jtag_struct.h" +#include "soc/usb_wrap_struct.h" #include "soc/clk_tree_defs.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" -//TODO: IDF-6509 - #ifdef __cplusplus extern "C" { #endif @@ -35,8 +38,11 @@ extern "C" { // Get GPIO hardware instance with giving gpio num #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) -#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) -#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) +#define GPIO_LL_INTR0_ENA (BIT(0)) +// #define GPIO_LL_INTR1_ENA (BIT(1)) // TODO: IDF-7995 +// #define GPIO_LL_INTR2_ENA (BIT(2)) +// #define GPIO_LL_INTR3_ENA (BIT(3)) + /** * @brief Enable pull-up on GPIO. * @@ -45,7 +51,7 @@ extern "C" { */ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) { - REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); + IOMUX.gpio[gpio_num].fun_wpu = 1; } /** @@ -57,7 +63,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); + IOMUX.gpio[gpio_num].fun_wpu = 0; } /** @@ -68,7 +74,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) { - REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); + IOMUX.gpio[gpio_num].fun_wpd = 1; } /** @@ -80,7 +86,22 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - abort(); + // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value + // USB DP pin is default to PU enabled + // Note that esp32p4 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin + // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. + // TODO: read the specific efuse with efuse_ll.h + + // One more noticable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately. + // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG + if (gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) { + USB_SERIAL_JTAG.conf0.pad_pull_override = 1; + USB_SERIAL_JTAG.conf0.dp_pullup = 0; + } else if (gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) { + USB_WRAP.otg_conf.pad_pull_override = 1; + USB_WRAP.otg_conf.dp_pullup = 0; + } + IOMUX.gpio[gpio_num].fun_wpd = 0; } /** @@ -92,7 +113,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) { - // hw->pin[gpio_num].int_type = intr_type; + hw->pin[gpio_num].int_type = intr_type; } /** @@ -105,8 +126,8 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, uint32_t gpio_num, gpio __attribute__((always_inline)) static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) { - // *status = hw->intr_0; // need to check - abort(); + (void)core_id; // TODO: IDF-7995 There are 4 interrupt sources for GPIO on P4. New feature! Need to fix this function later. + *status = hw->intr_0.int_0; } /** @@ -119,7 +140,8 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin __attribute__((always_inline)) static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status) { - *status = 0; + (void)core_id; // TODO: IDF-7995 There are 4 interrupt sources for GPIO on P4. New feature! Need to fix this function later. + *status = hw->intr1_0.int1_0; } /** @@ -131,7 +153,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id __attribute__((always_inline)) static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) { - // hw->status_w1tc = mask; + hw->status_w1tc.status_w1tc = mask; } /** @@ -143,7 +165,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask) __attribute__((always_inline)) static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) { - // P4 needs check + hw->status1_w1tc.status1_w1tc = mask; } /** @@ -156,8 +178,8 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask) __attribute__((always_inline)) static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, uint32_t gpio_num) { - // HAL_ASSERT(core_id == 0 && "target SoC only has a single core"); - // GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr + (void)core_id; + hw->pin[gpio_num].int_ena = GPIO_LL_INTR0_ENA; //enable for GPIO_INTR0 interrupt signal TODO: IDF-7995 } /** @@ -169,7 +191,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, __attribute__((always_inline)) static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) { - // hw->pin[gpio_num].int_ena = 0; //disable GPIO intr + hw->pin[gpio_num].int_ena = 0; //disable GPIO intr } /** @@ -181,7 +203,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].fun_ie = 0; } /** @@ -192,7 +214,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].fun_ie = 1; } /** @@ -203,6 +225,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num) { + IOMUX.gpio[gpio_num].filter_en = 1; } /** @@ -213,6 +236,55 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num) { + IOMUX.gpio[gpio_num].filter_en = 0; +} + +/** + * @brief Enable GPIO hysteresis + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-7480 Fix magic number 16 with proper macro + uint64_t bit_mask = 1ULL << gpio_num; + if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { + // GPIO0-15 + LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys |= bit_mask; + } else { + if (gpio_num < 32 + 16) { + // GPIO 16-47 + HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low |= (bit_mask >> 16); + } else { + // GPIO 48-56 + HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high |= (bit_mask >> (32 + 16)); + } + } +} + +/** + * @brief Disable GPIO hysteresis + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + */ +static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-7480 Fix magic number 16 with proper macro + uint64_t bit_mask = 1ULL << gpio_num; + if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { + // GPIO0-15 + LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys &= ~bit_mask; + } else { + if (gpio_num < 32 + 16) { + // GPIO 16-47 + HP_SYSTEM.gpio_o_hys_ctrl0.reg_gpio_0_hys_low &= ~(bit_mask >> 16); + } else { + // GPIO 48-56 + HP_SYSTEM.gpio_o_hys_ctrl1.reg_gpio_0_hys_high &= ~(bit_mask >> (32 + 16)); + } + } } /** @@ -224,10 +296,13 @@ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { - // hw->enable_w1tc = (0x1 << gpio_num); - // // Ensure no other output signal is routed via GPIO matrix to this pin - // REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), - // CORE_GPIO_OUT_PAD_OUT0_IDX); + if (gpio_num < 32) { + hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); + } else { + hw->enable1_w1tc.enable1_w1tc = (0x1 << (gpio_num - 32)); + } + // Ensure no other output signal is routed via GPIO matrix to this pin + hw->func_out_sel_cfg[gpio_num].out_sel = SIG_GPIO_OUT_IDX; } /** @@ -236,9 +311,14 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num) { - // hw->enable_w1ts = (0x1 << gpio_num); + if (gpio_num < 32) { + hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num); + } else { + hw->enable1_w1ts.enable1_w1ts = (0x1 << (gpio_num - 32)); + } } /** @@ -249,7 +329,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num) { - // hw->pin[gpio_num].pad_driver = 0; + hw->pin[gpio_num].pad_driver = 0; } /** @@ -260,7 +340,7 @@ static inline void gpio_ll_od_disable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) { - // hw->pin[gpio_num].pad_driver = 1; + hw->pin[gpio_num].pad_driver = 1; } /** @@ -273,11 +353,19 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level) { - // if (level) { - // hw->out_w1ts = (1 << gpio_num); - // } else { - // hw->out_w1tc = (1 << gpio_num); - // } + if (level) { + if (gpio_num < 32) { + hw->out_w1ts.out_w1ts = (1 << gpio_num); + } else { + hw->out1_w1ts.out1_w1ts = (1 << (gpio_num - 32)); + } + } else { + if (gpio_num < 32) { + hw->out_w1tc.out_w1tc = (1 << gpio_num); + } else { + hw->out1_w1tc.out1_w1tc = (1 << (gpio_num - 32)); + } + } } /** @@ -294,8 +382,11 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t */ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num) { - // return (hw->in >> gpio_num) & 0x1; - abort(); + if (gpio_num < 32) { + return (hw->in.in_data_next >> gpio_num) & 0x1; + } else { + return (hw->in1.in1_data_next >> (gpio_num - 32)) & 0x1; + } } /** @@ -306,7 +397,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num) { - // hw->pin[gpio_num].wakeup_enable = 0x1; + hw->pin[gpio_num].wakeup_enable = 1; } /** @@ -317,7 +408,7 @@ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) { - // hw->pin[gpio_num].wakeup_enable = 0; + hw->pin[gpio_num].wakeup_enable = 0; } /** @@ -329,7 +420,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength) { - SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S); + IOMUX.gpio[gpio_num].fun_drv = strength; } /** @@ -341,27 +432,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength) { - *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S); -} - -/** - * @brief Enable all digital gpio pads hold function during Deep-sleep. - * - * @param hw Peripheral GPIO hardware instance address. - */ -static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) -{ - //SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M); -} - -/** - * @brief Disable all digital gpio pads hold function during Deep-sleep. - * - * @param hw Peripheral GPIO hardware instance address. - */ -static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) -{ - //SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD); + *strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv); } /** @@ -372,6 +443,20 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) */ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) { + // TODO: IDF-7480 Fix magic number 16 with proper macro + uint64_t bit_mask = 1ULL << gpio_num; + if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { + // GPIO 0-15 + LP_IOMUX.lp_pad_hold.reg_lp_gpio_hold |= bit_mask; + } else { + if (gpio_num < 32 + 16) { + // GPIO 16-47 + HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low |= (bit_mask >> 16); + } else { + // GPIO 48-56 + HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + 16)); + } + } } /** @@ -382,6 +467,51 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) { + // TODO: IDF-7480 Fix magic number 16 with proper macro + uint64_t bit_mask = 1ULL << gpio_num; + if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { + // GPIO 0-15 + LP_IOMUX.lp_pad_hold.reg_lp_gpio_hold &= ~bit_mask; + } else { + if (gpio_num < 32 + 16) { + // GPIO 16-47 + HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low &= ~(bit_mask >> 16); + } else { + // GPIO 48-56 + HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + 16)); + } + } +} + +/** + * @brief Get digital gpio pad hold status. + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number, only support output GPIOs + * + * @note caller must ensure that gpio_num is a digital io pad + * + * @return + * - true digital gpio pad is held + * - false digital gpio pad is unheld + */ +__attribute__((always_inline)) +static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) +{ + // TODO: IDF-7480 Fix magic number 16 with proper macro + uint64_t bit_mask = 1ULL << gpio_num; + if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { + // GPIO 0-15 + abort(); + } else { + if (gpio_num < 32 + 16) { + // GPIO 16-47 + return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> 16)); + } else { + // GPIO 48-56 + return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + 16))); + } + } } /** @@ -394,8 +524,8 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) { - // hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; - // PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); + hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; + IOMUX.gpio[gpio].fun_ie = 1; } /** @@ -406,8 +536,13 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign */ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) { - if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { - //CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE); + // Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function + // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately. + // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG + if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) { + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + } else if (pin_name == IO_MUX_GPIO26_REG || pin_name == IO_MUX_GPIO27_REG) { + USB_WRAP.otg_conf.usb_pad_enable = 0; } PIN_FUNC_SELECT(pin_name, func); } @@ -422,11 +557,15 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) __attribute__((always_inline)) static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { - // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function - if (gpio_num == 18 || gpio_num == 19) { - //CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE); + // Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function + // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately. + // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG + if (gpio_num == USB_USJ_INT_PHY_DM_GPIO_NUM || gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) { + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + } else if (gpio_num == USB_OTG_INT_PHY_DM_GPIO_NUM || gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) { + USB_WRAP.otg_conf.usb_pad_enable = 0; } - PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); + IOMUX.gpio[gpio_num].mcu_sel = func; } /** @@ -440,9 +579,9 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f */ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv) { - // hw->func_out_sel_cfg[gpio_num].oe_sel = 0; - // hw->func_out_sel_cfg[gpio_num].oe_inv_sel = oen_inv; - // gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func); + hw->func_out_sel_cfg[gpio_num].oen_sel = 0; + hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; + gpio_ll_func_sel(hw, gpio_num, func); } /** @@ -452,6 +591,37 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, */ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) { + switch (src) { + case SOC_MOD_CLK_XTAL: + HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 0; + break; + case SOC_MOD_CLK_PLL_F80M: + HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 1; + break; + default: + // Unsupported IO_MUX clock source + HAL_ASSERT(false); + } +} + +/** + * @brief Force hold digital io pad. + * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_hold_all(void) +{ + // WT flag, it gets self-cleared after the configuration is done + PMU.imm_pad_hold_all.tie_high_hp_pad_hold_all = 1; +} + +/** + * @brief Force unhold digital io pad. + * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. + */ +static inline void gpio_ll_force_unhold_all(void) +{ + // WT flag, it gets self-cleared after the configuration is done + PMU.imm_pad_hold_all.tie_low_hp_pad_hold_all = 1; } /** @@ -462,7 +632,7 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) */ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].slp_sel = 1; } /** @@ -474,7 +644,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].slp_sel = 0; } /** @@ -485,7 +655,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].mcu_wpu = 0; } /** @@ -496,7 +666,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].mcu_wpu = 1; } /** @@ -507,7 +677,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].mcu_wpd = 1; } /** @@ -518,7 +688,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].mcu_wpd = 0; } /** @@ -529,7 +699,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].mcu_ie = 0; } /** @@ -540,7 +710,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num */ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].mcu_ie = 1; } /** @@ -551,7 +721,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); + IOMUX.gpio[gpio_num].mcu_oe = 0; } /** @@ -562,40 +732,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); -} - -/** - * @brief Enable GPIO deep-sleep wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number. - * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used. - */ -static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) -{ -} - -/** - * @brief Disable GPIO deep-sleep wake-up function. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - */ -static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) -{ -} - -/** - * @brief Get the status of whether an IO is used for deep-sleep wake-up. - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - * @return True if the pin is enabled to wake up from deep-sleep - */ -static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num) -{ - return 0; + IOMUX.gpio[gpio_num].mcu_oe = 1; } #ifdef __cplusplus diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index bb8a381598..83bf6479f3 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -487,7 +487,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_func_sel(hw, gpio_num, func); } /** diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index 513d0829a9..1cdeb2db4c 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -57,8 +57,8 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value // USB DP pin is default to PU enabled // Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin - // which should be checked is USB_DM_GPIO_NUM instead. - if (gpio_num == USB_DP_GPIO_NUM) { + // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. + if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); } @@ -291,7 +291,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { - if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { + if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) { CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); @@ -506,7 +506,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_func_sel(hw, gpio_num, func); } /** diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h index 17546c2054..9d1aa0aee6 100644 --- a/components/hal/esp32s3/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,7 +63,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) { if (func == RTCIO_FUNC_RTC) { // Disable USB Serial JTAG if pin 19 or pin 20 needs to select the rtc function - if (rtcio_num == rtc_io_num_map[USB_DM_GPIO_NUM] || rtcio_num == rtc_io_num_map[USB_DP_GPIO_NUM]) { + if (rtcio_num == rtc_io_num_map[USB_INT_PHY0_DM_GPIO_NUM] || rtcio_num == rtc_io_num_map[USB_INT_PHY0_DP_GPIO_NUM]) { USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; } SENS.sar_peri_clk_gate_conf.iomux_clk_en = 1; @@ -202,8 +202,8 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value // USB DP pin is default to PU enabled // Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin - // which should be checked is USB_DM_GPIO_NUM instead. - if (rtcio_num == USB_DP_GPIO_NUM) { + // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. + if (rtcio_num == USB_INT_PHY0_DP_GPIO_NUM) { SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); } diff --git a/components/hal/gpio_hal.c b/components/hal/gpio_hal.c index e20aaa3ee3..50e5ebc103 100644 --- a/components/hal/gpio_hal.c +++ b/components/hal/gpio_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,11 +33,13 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num) #if SOC_GPIO_SUPPORT_PIN_HYS_FILTER void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num, bool enable) { +#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE + gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num); +#endif + if (enable) { - gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num); gpio_ll_pin_input_hysteresis_enable(hal->dev, gpio_num); } else { - gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num); gpio_ll_pin_input_hysteresis_disable(hal->dev, gpio_num); } } diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index 22fba943f7..3b624374e4 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -497,6 +497,7 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, uint32_t gpio_n */ void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num, bool enable); +#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE /** * @brief Set gpio hysteresis enable/disable by efuse. * @@ -504,6 +505,7 @@ void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num, * @param gpio_num GPIO number */ #define gpio_hal_hysteresis_from_efuse(hal, gpio_num) gpio_ll_pin_input_hysteresis_ctrl_sel_efuse((hal)->dev, gpio_num) +#endif #endif // SOC_GPIO_SUPPORT_PIN_HYS_FILTER #ifdef __cplusplus diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h index 2736cdb039..1f613e4bdb 100644 --- a/components/hal/include/hal/gpio_types.h +++ b/components/hal/include/hal/gpio_types.h @@ -68,6 +68,14 @@ typedef enum { #define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG #define GPIO_PIN_REG_47 IO_MUX_GPIO47_REG #define GPIO_PIN_REG_48 IO_MUX_GPIO48_REG +#define GPIO_PIN_REG_49 IO_MUX_GPIO49_REG +#define GPIO_PIN_REG_50 IO_MUX_GPIO50_REG +#define GPIO_PIN_REG_51 IO_MUX_GPIO51_REG +#define GPIO_PIN_REG_52 IO_MUX_GPIO52_REG +#define GPIO_PIN_REG_53 IO_MUX_GPIO53_REG +#define GPIO_PIN_REG_54 IO_MUX_GPIO54_REG +#define GPIO_PIN_REG_55 IO_MUX_GPIO55_REG +#define GPIO_PIN_REG_56 IO_MUX_GPIO56_REG typedef enum { GPIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */ @@ -121,14 +129,18 @@ typedef enum { GPIO_DRIVE_CAP_MAX, } gpio_drive_cap_t; +#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER /** * @brief Available option for configuring hysteresis feature of GPIOs */ typedef enum { +#if SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE GPIO_HYS_CTRL_EFUSE = 0, /*!< Pad input hysteresis ctrl by efuse */ - GPIO_HYS_SOFT_ENABLE = 1, /*!< Pad input hysteresis enable by software */ - GPIO_HYS_SOFT_DISABLE = 2, /*!< Pad input hysteresis disable by software */ +#endif + GPIO_HYS_SOFT_DISABLE, /*!< Pad input hysteresis disable by software */ + GPIO_HYS_SOFT_ENABLE, /*!< Pad input hysteresis enable by software */ } gpio_hys_ctrl_mode_t; +#endif #ifdef __cplusplus } diff --git a/components/soc/esp32c3/include/soc/io_mux_reg.h b/components/soc/esp32c3/include/soc/io_mux_reg.h index c814bdd956..f5abe8ee5e 100644 --- a/components/soc/esp32c3/include/soc/io_mux_reg.h +++ b/components/soc/esp32c3/include/soc/io_mux_reg.h @@ -137,8 +137,8 @@ #define SD_DATA2_GPIO_NUM 9 #define SD_DATA3_GPIO_NUM 10 -#define USB_DM_GPIO_NUM 18 -#define USB_DP_GPIO_NUM 19 +#define USB_INT_PHY0_DM_GPIO_NUM 18 +#define USB_INT_PHY0_DP_GPIO_NUM 19 #define MAX_RTC_GPIO_NUM 5 #define MAX_PAD_GPIO_NUM 21 diff --git a/components/soc/esp32c6/include/soc/gpio_ext_struct.h b/components/soc/esp32c6/include/soc/gpio_ext_struct.h index 1468d5ef2a..8dc5652cdc 100644 --- a/components/soc/esp32c6/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32c6/include/soc/gpio_ext_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -98,15 +98,15 @@ typedef union { */ typedef union { struct { - /** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0; + /** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0; * Etm event channel select gpio. */ - uint32_t etm_ch0_event_sel:5; + uint32_t etm_chn_event_sel:5; uint32_t reserved_5:2; - /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; + /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ - uint32_t etm_ch0_event_en:1; + uint32_t etm_chn_event_en:1; uint32_t reserved_8:24; }; uint32_t val; diff --git a/components/soc/esp32c6/include/soc/io_mux_reg.h b/components/soc/esp32c6/include/soc/io_mux_reg.h index 304ed1c383..aa95643237 100644 --- a/components/soc/esp32c6/include/soc/io_mux_reg.h +++ b/components/soc/esp32c6/include/soc/io_mux_reg.h @@ -143,8 +143,8 @@ #define SD_DATA2_GPIO_NUM 22 #define SD_DATA3_GPIO_NUM 23 -#define USB_DM_GPIO_NUM 12 -#define USB_DP_GPIO_NUM 13 +#define USB_INT_PHY0_DM_GPIO_NUM 12 +#define USB_INT_PHY0_DP_GPIO_NUM 13 #define EXT_OSC_SLOW_GPIO_NUM 0 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index b9453dc3f4..475b4e0889 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -415,13 +415,17 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool default y +config SOC_GPIO_FLEX_GLITCH_FILTER_NUM + int + default 8 + config SOC_GPIO_SUPPORT_PIN_HYS_FILTER bool default y -config SOC_GPIO_FLEX_GLITCH_FILTER_NUM - int - default 8 +config SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE + bool + default y config SOC_GPIO_SUPPORT_ETM bool diff --git a/components/soc/esp32h2/include/soc/gpio_ext_struct.h b/components/soc/esp32h2/include/soc/gpio_ext_struct.h index 1c9e6f3985..9b211852e1 100644 --- a/components/soc/esp32h2/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32h2/include/soc/gpio_ext_struct.h @@ -140,15 +140,15 @@ typedef union { */ typedef union { struct { - /** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0; + /** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0; * Etm event channel select gpio. */ - uint32_t etm_ch0_event_sel:5; + uint32_t etm_chn_event_sel:5; uint32_t reserved_5:2; - /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; + /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ - uint32_t etm_ch0_event_en:1; + uint32_t etm_chn_event_en:1; uint32_t reserved_8:24; }; uint32_t val; diff --git a/components/soc/esp32h2/include/soc/io_mux_reg.h b/components/soc/esp32h2/include/soc/io_mux_reg.h index 514f7e1de7..5db79e1673 100644 --- a/components/soc/esp32h2/include/soc/io_mux_reg.h +++ b/components/soc/esp32h2/include/soc/io_mux_reg.h @@ -155,8 +155,8 @@ #define SPI_D_GPIO_NUM 20 #define SPI_Q_GPIO_NUM 16 -#define USB_DM_GPIO_NUM 26 -#define USB_DP_GPIO_NUM 27 +#define USB_INT_PHY0_DM_GPIO_NUM 26 +#define USB_INT_PHY0_DP_GPIO_NUM 27 #define EXT_OSC_SLOW_GPIO_NUM 13 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 666a03606c..1912728c85 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -180,8 +180,9 @@ #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 28 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 -#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 +#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 +#define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse // GPIO peripheral has the ETM extension #define SOC_GPIO_SUPPORT_ETM 1 diff --git a/components/soc/esp32p4/gpio_periph.c b/components/soc/esp32p4/gpio_periph.c index c23436882a..12a5bdc0bf 100644 --- a/components/soc/esp32p4/gpio_periph.c +++ b/components/soc/esp32p4/gpio_periph.c @@ -5,15 +5,128 @@ */ #include "soc/gpio_periph.h" +#include "esp_assert.h" const uint32_t GPIO_PIN_MUX_REG[] = { - + IO_MUX_GPIO0_REG, + IO_MUX_GPIO1_REG, + IO_MUX_GPIO2_REG, + IO_MUX_GPIO3_REG, + IO_MUX_GPIO4_REG, + IO_MUX_GPIO5_REG, + IO_MUX_GPIO6_REG, + IO_MUX_GPIO7_REG, + IO_MUX_GPIO8_REG, + IO_MUX_GPIO9_REG, + IO_MUX_GPIO10_REG, + IO_MUX_GPIO11_REG, + IO_MUX_GPIO12_REG, + IO_MUX_GPIO13_REG, + IO_MUX_GPIO14_REG, + IO_MUX_GPIO15_REG, + IO_MUX_GPIO16_REG, + IO_MUX_GPIO17_REG, + IO_MUX_GPIO18_REG, + IO_MUX_GPIO19_REG, + IO_MUX_GPIO20_REG, + IO_MUX_GPIO21_REG, + IO_MUX_GPIO22_REG, + IO_MUX_GPIO23_REG, + IO_MUX_GPIO24_REG, + IO_MUX_GPIO25_REG, + IO_MUX_GPIO26_REG, + IO_MUX_GPIO27_REG, + IO_MUX_GPIO28_REG, + IO_MUX_GPIO29_REG, + IO_MUX_GPIO30_REG, + IO_MUX_GPIO31_REG, + IO_MUX_GPIO32_REG, + IO_MUX_GPIO33_REG, + IO_MUX_GPIO34_REG, + IO_MUX_GPIO35_REG, + IO_MUX_GPIO36_REG, + IO_MUX_GPIO37_REG, + IO_MUX_GPIO38_REG, + IO_MUX_GPIO39_REG, + IO_MUX_GPIO40_REG, + IO_MUX_GPIO41_REG, + IO_MUX_GPIO42_REG, + IO_MUX_GPIO43_REG, + IO_MUX_GPIO44_REG, + IO_MUX_GPIO45_REG, + IO_MUX_GPIO46_REG, + IO_MUX_GPIO47_REG, + IO_MUX_GPIO48_REG, + IO_MUX_GPIO49_REG, + IO_MUX_GPIO50_REG, + IO_MUX_GPIO51_REG, + IO_MUX_GPIO52_REG, + IO_MUX_GPIO53_REG, + IO_MUX_GPIO54_REG, + IO_MUX_GPIO55_REG, + IO_MUX_GPIO56_REG, }; -// _Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); +ESP_STATIC_ASSERT(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG"); const uint32_t GPIO_HOLD_MASK[] = { - + BIT(0), //GPIO0 // LP_IOMUX_LP_PAD_HOLD_REG + BIT(1), //GPIO1 + BIT(2), //GPIO2 + BIT(3), //GPIO3 + BIT(4), //GPIO4 + BIT(5), //GPIO5 + BIT(6), //GPIO6 + BIT(7), //GPIO7 + BIT(8), //GPIO8 + BIT(9), //GPIO9 + BIT(10), //GPIO10 + BIT(11), //GPIO11 + BIT(12), //GPIO12 + BIT(13), //GPIO13 + BIT(14), //GPIO14 + BIT(15), //GPIO15 + BIT(0), //GPIO16 // HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG + BIT(1), //GPIO17 + BIT(2), //GPIO18 + BIT(3), //GPIO19 + BIT(4), //GPIO20 + BIT(5), //GPIO21 + BIT(6), //GPIO22 + BIT(7), //GPIO23 + BIT(8), //GPIO24 + BIT(9), //GPIO25 + BIT(10), //GPIO26 + BIT(11), //GPIO27 + BIT(12), //GPIO28 + BIT(13), //GPIO29 + BIT(14), //GPIO30 + BIT(15), //GPIO31 + BIT(16), //GPIO32 + BIT(17), //GPIO33 + BIT(18), //GPIO34 + BIT(19), //GPIO35 + BIT(20), //GPIO36 + BIT(21), //GPIO37 + BIT(22), //GPIO38 + BIT(23), //GPIO39 + BIT(24), //GPIO40 + BIT(25), //GPIO41 + BIT(26), //GPIO42 + BIT(27), //GPIO43 + BIT(28), //GPIO44 + BIT(29), //GPIO45 + BIT(30), //GPIO46 + BIT(31), //GPIO47 + BIT(0), //GPIO48 // HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG + BIT(1), //GPIO49 + BIT(2), //GPIO50 + BIT(3), //GPIO51 + BIT(4), //GPIO52 + BIT(5), //GPIO53 + BIT(6), //GPIO54 + BIT(7), //GPIO55 + BIT(8), //GPIO56 }; -// _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); +ESP_STATIC_ASSERT(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 2ecefecf05..23e1657625 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -257,7 +257,11 @@ config SOC_GPIO_PORT config SOC_GPIO_PIN_COUNT int - default 64 + default 57 + +config SOC_GPIO_SUPPORT_PIN_HYS_FILTER + bool + default y config SOC_GPIO_ETM_EVENTS_PER_GROUP int @@ -273,7 +277,7 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT config SOC_GPIO_VALID_GPIO_MASK hex - default 0xFFFFFFFFFFFFFFFF + default 0x01FFFFFFFFFFFFFF config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int @@ -281,7 +285,15 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex - default 0x000000007FFFFF00 + default 0x01FFFFFFFFFF0000 + +config SOC_GPIO_SUPPORT_FORCE_HOLD + bool + default y + +config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + bool + default y config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h index d3ba233faa..4064eaf8d2 100644 --- a/components/soc/esp32p4/include/soc/clkout_channel.h +++ b/components/soc/esp32p4/include/soc/clkout_channel.h @@ -1,9 +1,8 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -//Copied from C6, please check. TODO: IDF-7526 // ESP32P4 CLKOUT signals has no corresponding iomux pins diff --git a/components/soc/esp32p4/include/soc/gpio_ext_reg.h b/components/soc/esp32p4/include/soc/gpio_ext_reg.h index 157a4c9e0a..7f0b5a8921 100644 --- a/components/soc/esp32p4/include/soc/gpio_ext_reg.h +++ b/components/soc/esp32p4/include/soc/gpio_ext_reg.h @@ -11,1453 +11,1444 @@ extern "C" { #endif -/** - * TODO: IDF-6509, GPIO - * TODO: IDF-7481, GPIO Glitch Filter - * Please note, some xxx_CHn_xx registers, their fields are still named with xx_CH0_xx - * e.g. GPIOSD_GLITCH_FILTER_CH1_REG and GPIOSD_FILTER_CH0_EN - */ - -#define GPIOSD_FILTER_CH0_EN (BIT(0)) - -/** GPIOSD_SIGMADELTA0_REG register +/** GPIO_EXT_SIGMADELTA0_REG register * Duty Cycle Configure Register of SDM0 */ -#define GPIOSD_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0) +/** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD0_IN 0x000000FFU +#define GPIO_EXT_SD0_IN_M (GPIO_EXT_SD0_IN_V << GPIO_EXT_SD0_IN_S) +#define GPIO_EXT_SD0_IN_V 0x000000FFU +#define GPIO_EXT_SD0_IN_S 0 +/** GPIO_EXT_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD0_PRESCALE 0x000000FFU +#define GPIO_EXT_SD0_PRESCALE_M (GPIO_EXT_SD0_PRESCALE_V << GPIO_EXT_SD0_PRESCALE_S) +#define GPIO_EXT_SD0_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD0_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA1_REG register +/** GPIO_EXT_SIGMADELTA1_REG register * Duty Cycle Configure Register of SDM1 */ -#define GPIOSD_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4) +/** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD1_IN 0x000000FFU +#define GPIO_EXT_SD1_IN_M (GPIO_EXT_SD1_IN_V << GPIO_EXT_SD1_IN_S) +#define GPIO_EXT_SD1_IN_V 0x000000FFU +#define GPIO_EXT_SD1_IN_S 0 +/** GPIO_EXT_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD1_PRESCALE 0x000000FFU +#define GPIO_EXT_SD1_PRESCALE_M (GPIO_EXT_SD1_PRESCALE_V << GPIO_EXT_SD1_PRESCALE_S) +#define GPIO_EXT_SD1_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD1_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA2_REG register +/** GPIO_EXT_SIGMADELTA2_REG register * Duty Cycle Configure Register of SDM2 */ -#define GPIOSD_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8) +/** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD2_IN 0x000000FFU +#define GPIO_EXT_SD2_IN_M (GPIO_EXT_SD2_IN_V << GPIO_EXT_SD2_IN_S) +#define GPIO_EXT_SD2_IN_V 0x000000FFU +#define GPIO_EXT_SD2_IN_S 0 +/** GPIO_EXT_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD2_PRESCALE 0x000000FFU +#define GPIO_EXT_SD2_PRESCALE_M (GPIO_EXT_SD2_PRESCALE_V << GPIO_EXT_SD2_PRESCALE_S) +#define GPIO_EXT_SD2_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD2_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA3_REG register +/** GPIO_EXT_SIGMADELTA3_REG register * Duty Cycle Configure Register of SDM3 */ -#define GPIOSD_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc) +/** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD3_IN 0x000000FFU +#define GPIO_EXT_SD3_IN_M (GPIO_EXT_SD3_IN_V << GPIO_EXT_SD3_IN_S) +#define GPIO_EXT_SD3_IN_V 0x000000FFU +#define GPIO_EXT_SD3_IN_S 0 +/** GPIO_EXT_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD3_PRESCALE 0x000000FFU +#define GPIO_EXT_SD3_PRESCALE_M (GPIO_EXT_SD3_PRESCALE_V << GPIO_EXT_SD3_PRESCALE_S) +#define GPIO_EXT_SD3_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD3_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA4_REG register +/** GPIO_EXT_SIGMADELTA4_REG register * Duty Cycle Configure Register of SDM4 */ -#define GPIOSD_SIGMADELTA4_REG (DR_REG_GPIO_EXT_BASE + 0x10) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA4_REG (DR_REG_GPIO_EXT_BASE + 0x10) +/** GPIO_EXT_SD4_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD4_IN 0x000000FFU +#define GPIO_EXT_SD4_IN_M (GPIO_EXT_SD4_IN_V << GPIO_EXT_SD4_IN_S) +#define GPIO_EXT_SD4_IN_V 0x000000FFU +#define GPIO_EXT_SD4_IN_S 0 +/** GPIO_EXT_SD4_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD4_PRESCALE 0x000000FFU +#define GPIO_EXT_SD4_PRESCALE_M (GPIO_EXT_SD4_PRESCALE_V << GPIO_EXT_SD4_PRESCALE_S) +#define GPIO_EXT_SD4_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD4_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA5_REG register +/** GPIO_EXT_SIGMADELTA5_REG register * Duty Cycle Configure Register of SDM5 */ -#define GPIOSD_SIGMADELTA5_REG (DR_REG_GPIO_EXT_BASE + 0x14) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA5_REG (DR_REG_GPIO_EXT_BASE + 0x14) +/** GPIO_EXT_SD5_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD5_IN 0x000000FFU +#define GPIO_EXT_SD5_IN_M (GPIO_EXT_SD5_IN_V << GPIO_EXT_SD5_IN_S) +#define GPIO_EXT_SD5_IN_V 0x000000FFU +#define GPIO_EXT_SD5_IN_S 0 +/** GPIO_EXT_SD5_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD5_PRESCALE 0x000000FFU +#define GPIO_EXT_SD5_PRESCALE_M (GPIO_EXT_SD5_PRESCALE_V << GPIO_EXT_SD5_PRESCALE_S) +#define GPIO_EXT_SD5_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD5_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA6_REG register +/** GPIO_EXT_SIGMADELTA6_REG register * Duty Cycle Configure Register of SDM6 */ -#define GPIOSD_SIGMADELTA6_REG (DR_REG_GPIO_EXT_BASE + 0x18) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA6_REG (DR_REG_GPIO_EXT_BASE + 0x18) +/** GPIO_EXT_SD6_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD6_IN 0x000000FFU +#define GPIO_EXT_SD6_IN_M (GPIO_EXT_SD6_IN_V << GPIO_EXT_SD6_IN_S) +#define GPIO_EXT_SD6_IN_V 0x000000FFU +#define GPIO_EXT_SD6_IN_S 0 +/** GPIO_EXT_SD6_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD6_PRESCALE 0x000000FFU +#define GPIO_EXT_SD6_PRESCALE_M (GPIO_EXT_SD6_PRESCALE_V << GPIO_EXT_SD6_PRESCALE_S) +#define GPIO_EXT_SD6_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD6_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA7_REG register +/** GPIO_EXT_SIGMADELTA7_REG register * Duty Cycle Configure Register of SDM7 */ -#define GPIOSD_SIGMADELTA7_REG (DR_REG_GPIO_EXT_BASE + 0x1c) -/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0; +#define GPIO_EXT_SIGMADELTA7_REG (DR_REG_GPIO_EXT_BASE + 0x1c) +/** GPIO_EXT_SD7_IN : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ -#define GPIOSD_SD0_IN 0x000000FFU -#define GPIOSD_SD0_IN_M (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S) -#define GPIOSD_SD0_IN_V 0x000000FFU -#define GPIOSD_SD0_IN_S 0 -/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255; +#define GPIO_EXT_SD7_IN 0x000000FFU +#define GPIO_EXT_SD7_IN_M (GPIO_EXT_SD7_IN_V << GPIO_EXT_SD7_IN_S) +#define GPIO_EXT_SD7_IN_V 0x000000FFU +#define GPIO_EXT_SD7_IN_S 0 +/** GPIO_EXT_SD7_PRESCALE : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ -#define GPIOSD_SD0_PRESCALE 0x000000FFU -#define GPIOSD_SD0_PRESCALE_M (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S) -#define GPIOSD_SD0_PRESCALE_V 0x000000FFU -#define GPIOSD_SD0_PRESCALE_S 8 +#define GPIO_EXT_SD7_PRESCALE 0x000000FFU +#define GPIO_EXT_SD7_PRESCALE_M (GPIO_EXT_SD7_PRESCALE_V << GPIO_EXT_SD7_PRESCALE_S) +#define GPIO_EXT_SD7_PRESCALE_V 0x000000FFU +#define GPIO_EXT_SD7_PRESCALE_S 8 -/** GPIOSD_SIGMADELTA_MISC_REG register +/** GPIO_EXT_SIGMADELTA_MISC_REG register * MISC Register */ -#define GPIOSD_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) -/** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; +#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24) +/** GPIO_EXT_SD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0; * Clock enable bit of sigma delta modulation. */ -#define GPIOSD_FUNCTION_CLK_EN (BIT(30)) -#define GPIOSD_FUNCTION_CLK_EN_M (GPIOSD_FUNCTION_CLK_EN_V << GPIOSD_FUNCTION_CLK_EN_S) -#define GPIOSD_FUNCTION_CLK_EN_V 0x00000001U -#define GPIOSD_FUNCTION_CLK_EN_S 30 -/** GPIOSD_SPI_SWAP : R/W; bitpos: [31]; default: 0; +#define GPIO_EXT_SD_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_EXT_SD_FUNCTION_CLK_EN_M (GPIO_EXT_SD_FUNCTION_CLK_EN_V << GPIO_EXT_SD_FUNCTION_CLK_EN_S) +#define GPIO_EXT_SD_FUNCTION_CLK_EN_V 0x00000001U +#define GPIO_EXT_SD_FUNCTION_CLK_EN_S 30 +/** GPIO_EXT_SD_SPI_SWAP : R/W; bitpos: [31]; default: 0; * Reserved. */ -#define GPIOSD_SPI_SWAP (BIT(31)) -#define GPIOSD_SPI_SWAP_M (GPIOSD_SPI_SWAP_V << GPIOSD_SPI_SWAP_S) -#define GPIOSD_SPI_SWAP_V 0x00000001U -#define GPIOSD_SPI_SWAP_S 31 +#define GPIO_EXT_SD_SPI_SWAP (BIT(31)) +#define GPIO_EXT_SD_SPI_SWAP_M (GPIO_EXT_SD_SPI_SWAP_V << GPIO_EXT_SD_SPI_SWAP_S) +#define GPIO_EXT_SD_SPI_SWAP_V 0x00000001U +#define GPIO_EXT_SD_SPI_SWAP_S 31 -/** GPIOSD_GLITCH_FILTER_CH0_REG register +/** GPIO_EXT_GLITCH_FILTER_CH0_REG register * Glitch Filter Configure Register of Channel0 */ -#define GPIOSD_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30) +/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH0_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH0_EN_M (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S) +#define GPIO_EXT_FILTER_CH0_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH0_EN_S 0 +/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S 13 -/** GPIOSD_GLITCH_FILTER_CH1_REG register +/** GPIO_EXT_GLITCH_FILTER_CH1_REG register * Glitch Filter Configure Register of Channel1 */ -#define GPIOSD_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34) +/** GPIO_EXT_FILTER_CH1_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH1_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH1_EN_M (GPIO_EXT_FILTER_CH1_EN_V << GPIO_EXT_FILTER_CH1_EN_S) +#define GPIO_EXT_FILTER_CH1_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH1_EN_S 0 +/** GPIO_EXT_FILTER_CH1_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH1_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH1_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES_M (GPIO_EXT_FILTER_CH1_WINDOW_THRES_V << GPIO_EXT_FILTER_CH1_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH1_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH1_WINDOW_WIDTH_S 13 -/** GPIOSD_GLITCH_FILTER_CH2_REG register +/** GPIO_EXT_GLITCH_FILTER_CH2_REG register * Glitch Filter Configure Register of Channel2 */ -#define GPIOSD_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38) +/** GPIO_EXT_FILTER_CH2_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH2_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH2_EN_M (GPIO_EXT_FILTER_CH2_EN_V << GPIO_EXT_FILTER_CH2_EN_S) +#define GPIO_EXT_FILTER_CH2_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH2_EN_S 0 +/** GPIO_EXT_FILTER_CH2_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH2_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH2_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES_M (GPIO_EXT_FILTER_CH2_WINDOW_THRES_V << GPIO_EXT_FILTER_CH2_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH2_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH2_WINDOW_WIDTH_S 13 -/** GPIOSD_GLITCH_FILTER_CH3_REG register +/** GPIO_EXT_GLITCH_FILTER_CH3_REG register * Glitch Filter Configure Register of Channel3 */ -#define GPIOSD_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c) +/** GPIO_EXT_FILTER_CH3_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH3_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH3_EN_M (GPIO_EXT_FILTER_CH3_EN_V << GPIO_EXT_FILTER_CH3_EN_S) +#define GPIO_EXT_FILTER_CH3_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH3_EN_S 0 +/** GPIO_EXT_FILTER_CH3_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH3_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH3_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES_M (GPIO_EXT_FILTER_CH3_WINDOW_THRES_V << GPIO_EXT_FILTER_CH3_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH3_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH3_WINDOW_WIDTH_S 13 -/** GPIOSD_GLITCH_FILTER_CH4_REG register +/** GPIO_EXT_GLITCH_FILTER_CH4_REG register * Glitch Filter Configure Register of Channel4 */ -#define GPIOSD_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40) +/** GPIO_EXT_FILTER_CH4_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH4_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH4_EN_M (GPIO_EXT_FILTER_CH4_EN_V << GPIO_EXT_FILTER_CH4_EN_S) +#define GPIO_EXT_FILTER_CH4_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH4_EN_S 0 +/** GPIO_EXT_FILTER_CH4_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH4_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH4_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES_M (GPIO_EXT_FILTER_CH4_WINDOW_THRES_V << GPIO_EXT_FILTER_CH4_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH4_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH4_WINDOW_WIDTH_S 13 -/** GPIOSD_GLITCH_FILTER_CH5_REG register +/** GPIO_EXT_GLITCH_FILTER_CH5_REG register * Glitch Filter Configure Register of Channel5 */ -#define GPIOSD_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44) +/** GPIO_EXT_FILTER_CH5_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH5_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH5_EN_M (GPIO_EXT_FILTER_CH5_EN_V << GPIO_EXT_FILTER_CH5_EN_S) +#define GPIO_EXT_FILTER_CH5_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH5_EN_S 0 +/** GPIO_EXT_FILTER_CH5_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH5_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH5_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES_M (GPIO_EXT_FILTER_CH5_WINDOW_THRES_V << GPIO_EXT_FILTER_CH5_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH5_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH5_WINDOW_WIDTH_S 13 -/** GPIOSD_GLITCH_FILTER_CH6_REG register +/** GPIO_EXT_GLITCH_FILTER_CH6_REG register * Glitch Filter Configure Register of Channel6 */ -#define GPIOSD_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48) +/** GPIO_EXT_FILTER_CH6_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH6_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH6_EN_M (GPIO_EXT_FILTER_CH6_EN_V << GPIO_EXT_FILTER_CH6_EN_S) +#define GPIO_EXT_FILTER_CH6_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH6_EN_S 0 +/** GPIO_EXT_FILTER_CH6_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH6_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH6_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES_M (GPIO_EXT_FILTER_CH6_WINDOW_THRES_V << GPIO_EXT_FILTER_CH6_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH6_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH6_WINDOW_WIDTH_S 13 -/** GPIOSD_GLITCH_FILTER_CH7_REG register +/** GPIO_EXT_GLITCH_FILTER_CH7_REG register * Glitch Filter Configure Register of Channel7 */ -#define GPIOSD_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) -/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c) +/** GPIO_EXT_FILTER_CH7_EN : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ -#define GPIOSD_FILTER_CH0_EN (BIT(0)) -#define GPIOSD_FILTER_CH0_EN_M (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S) -#define GPIOSD_FILTER_CH0_EN_V 0x00000001U -#define GPIOSD_FILTER_CH0_EN_S 0 -/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; +#define GPIO_EXT_FILTER_CH7_EN (BIT(0)) +#define GPIO_EXT_FILTER_CH7_EN_M (GPIO_EXT_FILTER_CH7_EN_V << GPIO_EXT_FILTER_CH7_EN_S) +#define GPIO_EXT_FILTER_CH7_EN_V 0x00000001U +#define GPIO_EXT_FILTER_CH7_EN_S 0 +/** GPIO_EXT_FILTER_CH7_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_M (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S) -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_V 0x0000003FU -#define GPIOSD_FILTER_CH0_INPUT_IO_NUM_S 1 -/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM 0x0000003FU +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_M (GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_S) +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_V 0x0000003FU +#define GPIO_EXT_FILTER_CH7_INPUT_IO_NUM_S 1 +/** GPIO_EXT_FILTER_CH7_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ -#define GPIOSD_FILTER_CH0_WINDOW_THRES 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_M (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S) -#define GPIOSD_FILTER_CH0_WINDOW_THRES_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_THRES_S 7 -/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES_M (GPIO_EXT_FILTER_CH7_WINDOW_THRES_V << GPIO_EXT_FILTER_CH7_WINDOW_THRES_S) +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES_V 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_THRES_S 7 +/** GPIO_EXT_FILTER_CH7_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_M (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S) -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_V 0x0000003FU -#define GPIOSD_FILTER_CH0_WINDOW_WIDTH_S 13 +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_M (GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_S) +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_V 0x0000003FU +#define GPIO_EXT_FILTER_CH7_WINDOW_WIDTH_S 13 -/** GPIOSD_ETM_EVENT_CH0_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register * Etm Config register of Channel0 */ -#define GPIOSD_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 -/** GPIOSD_ETM_EVENT_CH1_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register * Etm Config register of Channel1 */ -#define GPIOSD_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64) +/** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH1_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH1_EVENT_SEL_M (GPIO_EXT_ETM_CH1_EVENT_SEL_V << GPIO_EXT_ETM_CH1_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH1_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH1_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH1_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH1_EVENT_EN_M (GPIO_EXT_ETM_CH1_EVENT_EN_V << GPIO_EXT_ETM_CH1_EVENT_EN_S) +#define GPIO_EXT_ETM_CH1_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH1_EVENT_EN_S 7 -/** GPIOSD_ETM_EVENT_CH2_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register * Etm Config register of Channel2 */ -#define GPIOSD_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68) +/** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH2_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH2_EVENT_SEL_M (GPIO_EXT_ETM_CH2_EVENT_SEL_V << GPIO_EXT_ETM_CH2_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH2_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH2_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH2_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH2_EVENT_EN_M (GPIO_EXT_ETM_CH2_EVENT_EN_V << GPIO_EXT_ETM_CH2_EVENT_EN_S) +#define GPIO_EXT_ETM_CH2_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH2_EVENT_EN_S 7 -/** GPIOSD_ETM_EVENT_CH3_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register * Etm Config register of Channel3 */ -#define GPIOSD_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c) +/** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH3_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH3_EVENT_SEL_M (GPIO_EXT_ETM_CH3_EVENT_SEL_V << GPIO_EXT_ETM_CH3_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH3_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH3_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH3_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH3_EVENT_EN_M (GPIO_EXT_ETM_CH3_EVENT_EN_V << GPIO_EXT_ETM_CH3_EVENT_EN_S) +#define GPIO_EXT_ETM_CH3_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH3_EVENT_EN_S 7 -/** GPIOSD_ETM_EVENT_CH4_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register * Etm Config register of Channel4 */ -#define GPIOSD_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70) +/** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH4_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH4_EVENT_SEL_M (GPIO_EXT_ETM_CH4_EVENT_SEL_V << GPIO_EXT_ETM_CH4_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH4_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH4_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH4_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH4_EVENT_EN_M (GPIO_EXT_ETM_CH4_EVENT_EN_V << GPIO_EXT_ETM_CH4_EVENT_EN_S) +#define GPIO_EXT_ETM_CH4_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH4_EVENT_EN_S 7 -/** GPIOSD_ETM_EVENT_CH5_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register * Etm Config register of Channel5 */ -#define GPIOSD_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74) +/** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH5_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH5_EVENT_SEL_M (GPIO_EXT_ETM_CH5_EVENT_SEL_V << GPIO_EXT_ETM_CH5_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH5_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH5_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH5_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH5_EVENT_EN_M (GPIO_EXT_ETM_CH5_EVENT_EN_V << GPIO_EXT_ETM_CH5_EVENT_EN_S) +#define GPIO_EXT_ETM_CH5_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH5_EVENT_EN_S 7 -/** GPIOSD_ETM_EVENT_CH6_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register * Etm Config register of Channel6 */ -#define GPIOSD_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78) +/** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH6_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH6_EVENT_SEL_M (GPIO_EXT_ETM_CH6_EVENT_SEL_V << GPIO_EXT_ETM_CH6_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH6_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH6_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH6_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH6_EVENT_EN_M (GPIO_EXT_ETM_CH6_EVENT_EN_V << GPIO_EXT_ETM_CH6_EVENT_EN_S) +#define GPIO_EXT_ETM_CH6_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH6_EVENT_EN_S 7 -/** GPIOSD_ETM_EVENT_CH7_CFG_REG register +/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register * Etm Config register of Channel7 */ -#define GPIOSD_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) -/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; +#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c) +/** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ -#define GPIOSD_ETM_CH0_EVENT_SEL 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_M (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S) -#define GPIOSD_ETM_CH0_EVENT_SEL_V 0x0000003FU -#define GPIOSD_ETM_CH0_EVENT_SEL_S 0 -/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; +#define GPIO_EXT_ETM_CH7_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH7_EVENT_SEL_M (GPIO_EXT_ETM_CH7_EVENT_SEL_V << GPIO_EXT_ETM_CH7_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH7_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH7_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ -#define GPIOSD_ETM_CH0_EVENT_EN (BIT(7)) -#define GPIOSD_ETM_CH0_EVENT_EN_M (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S) -#define GPIOSD_ETM_CH0_EVENT_EN_V 0x00000001U -#define GPIOSD_ETM_CH0_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH7_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH7_EVENT_EN_M (GPIO_EXT_ETM_CH7_EVENT_EN_V << GPIO_EXT_ETM_CH7_EVENT_EN_S) +#define GPIO_EXT_ETM_CH7_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH7_EVENT_EN_S 7 -/** GPIOSD_ETM_TASK_P0_CFG_REG register +/** GPIO_EXT_ETM_TASK_P0_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) -/** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0) +/** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO0_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO0_EN_M (GPIOSD_ETM_TASK_GPIO0_EN_V << GPIOSD_ETM_TASK_GPIO0_EN_S) -#define GPIOSD_ETM_TASK_GPIO0_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO0_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO0_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO0_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO0_SEL_M (GPIOSD_ETM_TASK_GPIO0_SEL_V << GPIOSD_ETM_TASK_GPIO0_SEL_S) -#define GPIOSD_ETM_TASK_GPIO0_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO0_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO1_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO1_EN_M (GPIOSD_ETM_TASK_GPIO1_EN_V << GPIOSD_ETM_TASK_GPIO1_EN_S) -#define GPIOSD_ETM_TASK_GPIO1_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO1_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO1_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO1_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO1_SEL_M (GPIOSD_ETM_TASK_GPIO1_SEL_V << GPIOSD_ETM_TASK_GPIO1_SEL_S) -#define GPIOSD_ETM_TASK_GPIO1_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO1_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO2_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO2_EN_M (GPIOSD_ETM_TASK_GPIO2_EN_V << GPIOSD_ETM_TASK_GPIO2_EN_S) -#define GPIOSD_ETM_TASK_GPIO2_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO2_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO2_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO2_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO2_SEL_M (GPIOSD_ETM_TASK_GPIO2_SEL_V << GPIOSD_ETM_TASK_GPIO2_SEL_S) -#define GPIOSD_ETM_TASK_GPIO2_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO2_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO3_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO3_EN_M (GPIOSD_ETM_TASK_GPIO3_EN_V << GPIOSD_ETM_TASK_GPIO3_EN_S) -#define GPIOSD_ETM_TASK_GPIO3_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO3_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO3_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO3_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO3_SEL_M (GPIOSD_ETM_TASK_GPIO3_SEL_V << GPIOSD_ETM_TASK_GPIO3_SEL_S) -#define GPIOSD_ETM_TASK_GPIO3_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO3_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 25 -/** GPIOSD_ETM_TASK_P1_CFG_REG register +/** GPIO_EXT_ETM_TASK_P1_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) -/** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4) +/** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO4_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO4_EN_M (GPIOSD_ETM_TASK_GPIO4_EN_V << GPIOSD_ETM_TASK_GPIO4_EN_S) -#define GPIOSD_ETM_TASK_GPIO4_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO4_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO4_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO4_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO4_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO4_SEL_M (GPIOSD_ETM_TASK_GPIO4_SEL_V << GPIOSD_ETM_TASK_GPIO4_SEL_S) -#define GPIOSD_ETM_TASK_GPIO4_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO4_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO5_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO5_EN_M (GPIOSD_ETM_TASK_GPIO5_EN_V << GPIOSD_ETM_TASK_GPIO5_EN_S) -#define GPIOSD_ETM_TASK_GPIO5_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO5_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO5_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO5_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO5_SEL_M (GPIOSD_ETM_TASK_GPIO5_SEL_V << GPIOSD_ETM_TASK_GPIO5_SEL_S) -#define GPIOSD_ETM_TASK_GPIO5_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO5_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO6_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO6_EN_M (GPIOSD_ETM_TASK_GPIO6_EN_V << GPIOSD_ETM_TASK_GPIO6_EN_S) -#define GPIOSD_ETM_TASK_GPIO6_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO6_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO6_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO6_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO6_SEL_M (GPIOSD_ETM_TASK_GPIO6_SEL_V << GPIOSD_ETM_TASK_GPIO6_SEL_S) -#define GPIOSD_ETM_TASK_GPIO6_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO6_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO7_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO7_EN_M (GPIOSD_ETM_TASK_GPIO7_EN_V << GPIOSD_ETM_TASK_GPIO7_EN_S) -#define GPIOSD_ETM_TASK_GPIO7_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO7_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO7_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO7_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO7_SEL_M (GPIOSD_ETM_TASK_GPIO7_SEL_V << GPIOSD_ETM_TASK_GPIO7_SEL_S) -#define GPIOSD_ETM_TASK_GPIO7_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO7_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 25 -/** GPIOSD_ETM_TASK_P2_CFG_REG register +/** GPIO_EXT_ETM_TASK_P2_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) -/** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8) +/** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO8_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO8_EN_M (GPIOSD_ETM_TASK_GPIO8_EN_V << GPIOSD_ETM_TASK_GPIO8_EN_S) -#define GPIOSD_ETM_TASK_GPIO8_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO8_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO8_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO8_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO8_SEL_M (GPIOSD_ETM_TASK_GPIO8_SEL_V << GPIOSD_ETM_TASK_GPIO8_SEL_S) -#define GPIOSD_ETM_TASK_GPIO8_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO8_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO9_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO9_EN_M (GPIOSD_ETM_TASK_GPIO9_EN_V << GPIOSD_ETM_TASK_GPIO9_EN_S) -#define GPIOSD_ETM_TASK_GPIO9_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO9_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO9_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO9_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO9_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO9_SEL_M (GPIOSD_ETM_TASK_GPIO9_SEL_V << GPIOSD_ETM_TASK_GPIO9_SEL_S) -#define GPIOSD_ETM_TASK_GPIO9_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO9_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO10_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO10_EN_M (GPIOSD_ETM_TASK_GPIO10_EN_V << GPIOSD_ETM_TASK_GPIO10_EN_S) -#define GPIOSD_ETM_TASK_GPIO10_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO10_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO10_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO10_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO10_SEL_M (GPIOSD_ETM_TASK_GPIO10_SEL_V << GPIOSD_ETM_TASK_GPIO10_SEL_S) -#define GPIOSD_ETM_TASK_GPIO10_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO10_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO11_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO11_EN_M (GPIOSD_ETM_TASK_GPIO11_EN_V << GPIOSD_ETM_TASK_GPIO11_EN_S) -#define GPIOSD_ETM_TASK_GPIO11_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO11_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO11_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO11_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO11_SEL_M (GPIOSD_ETM_TASK_GPIO11_SEL_V << GPIOSD_ETM_TASK_GPIO11_SEL_S) -#define GPIOSD_ETM_TASK_GPIO11_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO11_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 25 -/** GPIOSD_ETM_TASK_P3_CFG_REG register +/** GPIO_EXT_ETM_TASK_P3_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) -/** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac) +/** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO12_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO12_EN_M (GPIOSD_ETM_TASK_GPIO12_EN_V << GPIOSD_ETM_TASK_GPIO12_EN_S) -#define GPIOSD_ETM_TASK_GPIO12_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO12_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO12_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO12_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO12_SEL_M (GPIOSD_ETM_TASK_GPIO12_SEL_V << GPIOSD_ETM_TASK_GPIO12_SEL_S) -#define GPIOSD_ETM_TASK_GPIO12_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO12_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO13_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO13_EN_M (GPIOSD_ETM_TASK_GPIO13_EN_V << GPIOSD_ETM_TASK_GPIO13_EN_S) -#define GPIOSD_ETM_TASK_GPIO13_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO13_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO13_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO13_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO13_SEL_M (GPIOSD_ETM_TASK_GPIO13_SEL_V << GPIOSD_ETM_TASK_GPIO13_SEL_S) -#define GPIOSD_ETM_TASK_GPIO13_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO13_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO14_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO14_EN_M (GPIOSD_ETM_TASK_GPIO14_EN_V << GPIOSD_ETM_TASK_GPIO14_EN_S) -#define GPIOSD_ETM_TASK_GPIO14_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO14_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO14_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO14_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO14_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO14_SEL_M (GPIOSD_ETM_TASK_GPIO14_SEL_V << GPIOSD_ETM_TASK_GPIO14_SEL_S) -#define GPIOSD_ETM_TASK_GPIO14_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO14_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO15_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO15_EN_M (GPIOSD_ETM_TASK_GPIO15_EN_V << GPIOSD_ETM_TASK_GPIO15_EN_S) -#define GPIOSD_ETM_TASK_GPIO15_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO15_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO15_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO15_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO15_SEL_M (GPIOSD_ETM_TASK_GPIO15_SEL_V << GPIOSD_ETM_TASK_GPIO15_SEL_S) -#define GPIOSD_ETM_TASK_GPIO15_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO15_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 25 -/** GPIOSD_ETM_TASK_P4_CFG_REG register +/** GPIO_EXT_ETM_TASK_P4_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) -/** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0) +/** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO16_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO16_EN_M (GPIOSD_ETM_TASK_GPIO16_EN_V << GPIOSD_ETM_TASK_GPIO16_EN_S) -#define GPIOSD_ETM_TASK_GPIO16_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO16_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO16_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO16_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO16_SEL_M (GPIOSD_ETM_TASK_GPIO16_SEL_V << GPIOSD_ETM_TASK_GPIO16_SEL_S) -#define GPIOSD_ETM_TASK_GPIO16_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO16_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO17_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO17_EN_M (GPIOSD_ETM_TASK_GPIO17_EN_V << GPIOSD_ETM_TASK_GPIO17_EN_S) -#define GPIOSD_ETM_TASK_GPIO17_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO17_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO17_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO17_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO17_SEL_M (GPIOSD_ETM_TASK_GPIO17_SEL_V << GPIOSD_ETM_TASK_GPIO17_SEL_S) -#define GPIOSD_ETM_TASK_GPIO17_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO17_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO18_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO18_EN_M (GPIOSD_ETM_TASK_GPIO18_EN_V << GPIOSD_ETM_TASK_GPIO18_EN_S) -#define GPIOSD_ETM_TASK_GPIO18_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO18_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO18_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO18_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO18_SEL_M (GPIOSD_ETM_TASK_GPIO18_SEL_V << GPIOSD_ETM_TASK_GPIO18_SEL_S) -#define GPIOSD_ETM_TASK_GPIO18_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO18_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO19_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO19_EN_M (GPIOSD_ETM_TASK_GPIO19_EN_V << GPIOSD_ETM_TASK_GPIO19_EN_S) -#define GPIOSD_ETM_TASK_GPIO19_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO19_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO19_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO19_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO19_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO19_SEL_M (GPIOSD_ETM_TASK_GPIO19_SEL_V << GPIOSD_ETM_TASK_GPIO19_SEL_S) -#define GPIOSD_ETM_TASK_GPIO19_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO19_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 25 -/** GPIOSD_ETM_TASK_P5_CFG_REG register +/** GPIO_EXT_ETM_TASK_P5_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) -/** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4) +/** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO20_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO20_EN_M (GPIOSD_ETM_TASK_GPIO20_EN_V << GPIOSD_ETM_TASK_GPIO20_EN_S) -#define GPIOSD_ETM_TASK_GPIO20_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO20_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO20_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO20_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO20_SEL_M (GPIOSD_ETM_TASK_GPIO20_SEL_V << GPIOSD_ETM_TASK_GPIO20_SEL_S) -#define GPIOSD_ETM_TASK_GPIO20_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO20_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO21_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO21_EN_M (GPIOSD_ETM_TASK_GPIO21_EN_V << GPIOSD_ETM_TASK_GPIO21_EN_S) -#define GPIOSD_ETM_TASK_GPIO21_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO21_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO21_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO21_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO21_SEL_M (GPIOSD_ETM_TASK_GPIO21_SEL_V << GPIOSD_ETM_TASK_GPIO21_SEL_S) -#define GPIOSD_ETM_TASK_GPIO21_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO21_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO22_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO22_EN_M (GPIOSD_ETM_TASK_GPIO22_EN_V << GPIOSD_ETM_TASK_GPIO22_EN_S) -#define GPIOSD_ETM_TASK_GPIO22_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO22_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO22_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO22_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO22_SEL_M (GPIOSD_ETM_TASK_GPIO22_SEL_V << GPIOSD_ETM_TASK_GPIO22_SEL_S) -#define GPIOSD_ETM_TASK_GPIO22_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO22_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO23_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO23_EN_M (GPIOSD_ETM_TASK_GPIO23_EN_V << GPIOSD_ETM_TASK_GPIO23_EN_S) -#define GPIOSD_ETM_TASK_GPIO23_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO23_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO23_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO23_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO23_SEL_M (GPIOSD_ETM_TASK_GPIO23_SEL_V << GPIOSD_ETM_TASK_GPIO23_SEL_S) -#define GPIOSD_ETM_TASK_GPIO23_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO23_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 25 -/** GPIOSD_ETM_TASK_P6_CFG_REG register +/** GPIO_EXT_ETM_TASK_P6_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) -/** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8) +/** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO24_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO24_EN_M (GPIOSD_ETM_TASK_GPIO24_EN_V << GPIOSD_ETM_TASK_GPIO24_EN_S) -#define GPIOSD_ETM_TASK_GPIO24_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO24_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO24_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO24_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO24_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO24_SEL_M (GPIOSD_ETM_TASK_GPIO24_SEL_V << GPIOSD_ETM_TASK_GPIO24_SEL_S) -#define GPIOSD_ETM_TASK_GPIO24_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO24_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO25_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO25_EN_M (GPIOSD_ETM_TASK_GPIO25_EN_V << GPIOSD_ETM_TASK_GPIO25_EN_S) -#define GPIOSD_ETM_TASK_GPIO25_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO25_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO25_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_M (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO25_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO25_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO25_SEL_M (GPIOSD_ETM_TASK_GPIO25_SEL_V << GPIOSD_ETM_TASK_GPIO25_SEL_S) -#define GPIOSD_ETM_TASK_GPIO25_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO25_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO25_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO26_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO26_EN_M (GPIOSD_ETM_TASK_GPIO26_EN_V << GPIOSD_ETM_TASK_GPIO26_EN_S) -#define GPIOSD_ETM_TASK_GPIO26_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO26_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO26_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_M (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO26_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO26_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO26_SEL_M (GPIOSD_ETM_TASK_GPIO26_SEL_V << GPIOSD_ETM_TASK_GPIO26_SEL_S) -#define GPIOSD_ETM_TASK_GPIO26_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO26_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO26_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO27_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO27_EN_M (GPIOSD_ETM_TASK_GPIO27_EN_V << GPIOSD_ETM_TASK_GPIO27_EN_S) -#define GPIOSD_ETM_TASK_GPIO27_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO27_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO27_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO27_EN_M (GPIO_EXT_ETM_TASK_GPIO27_EN_V << GPIO_EXT_ETM_TASK_GPIO27_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO27_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO27_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO27_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO27_SEL_M (GPIOSD_ETM_TASK_GPIO27_SEL_V << GPIOSD_ETM_TASK_GPIO27_SEL_S) -#define GPIOSD_ETM_TASK_GPIO27_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO27_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO27_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_M (GPIO_EXT_ETM_TASK_GPIO27_SEL_V << GPIO_EXT_ETM_TASK_GPIO27_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_S 25 -/** GPIOSD_ETM_TASK_P7_CFG_REG register +/** GPIO_EXT_ETM_TASK_P7_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xbc) -/** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xbc) +/** GPIO_EXT_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO28_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO28_EN_M (GPIOSD_ETM_TASK_GPIO28_EN_V << GPIOSD_ETM_TASK_GPIO28_EN_S) -#define GPIOSD_ETM_TASK_GPIO28_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO28_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO28_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO28_EN_M (GPIO_EXT_ETM_TASK_GPIO28_EN_V << GPIO_EXT_ETM_TASK_GPIO28_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO28_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO28_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO28_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO28_SEL_M (GPIOSD_ETM_TASK_GPIO28_SEL_V << GPIOSD_ETM_TASK_GPIO28_SEL_S) -#define GPIOSD_ETM_TASK_GPIO28_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO28_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO28_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_M (GPIO_EXT_ETM_TASK_GPIO28_SEL_V << GPIO_EXT_ETM_TASK_GPIO28_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO29_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO29_EN_M (GPIOSD_ETM_TASK_GPIO29_EN_V << GPIOSD_ETM_TASK_GPIO29_EN_S) -#define GPIOSD_ETM_TASK_GPIO29_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO29_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO29_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO29_EN_M (GPIO_EXT_ETM_TASK_GPIO29_EN_V << GPIO_EXT_ETM_TASK_GPIO29_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO29_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO29_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO29_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO29_SEL_M (GPIOSD_ETM_TASK_GPIO29_SEL_V << GPIOSD_ETM_TASK_GPIO29_SEL_S) -#define GPIOSD_ETM_TASK_GPIO29_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO29_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO29_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_M (GPIO_EXT_ETM_TASK_GPIO29_SEL_V << GPIO_EXT_ETM_TASK_GPIO29_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO30_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO30_EN_M (GPIOSD_ETM_TASK_GPIO30_EN_V << GPIOSD_ETM_TASK_GPIO30_EN_S) -#define GPIOSD_ETM_TASK_GPIO30_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO30_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO30_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO30_EN_M (GPIO_EXT_ETM_TASK_GPIO30_EN_V << GPIO_EXT_ETM_TASK_GPIO30_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO30_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO30_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO30_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO30_SEL_M (GPIOSD_ETM_TASK_GPIO30_SEL_V << GPIOSD_ETM_TASK_GPIO30_SEL_S) -#define GPIOSD_ETM_TASK_GPIO30_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO30_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO31_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO30_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO30_SEL_M (GPIO_EXT_ETM_TASK_GPIO30_SEL_V << GPIO_EXT_ETM_TASK_GPIO30_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO30_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO30_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO31_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO31_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO31_EN_M (GPIOSD_ETM_TASK_GPIO31_EN_V << GPIOSD_ETM_TASK_GPIO31_EN_S) -#define GPIOSD_ETM_TASK_GPIO31_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO31_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO31_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO31_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO31_EN_M (GPIO_EXT_ETM_TASK_GPIO31_EN_V << GPIO_EXT_ETM_TASK_GPIO31_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO31_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO31_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO31_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO31_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO31_SEL_M (GPIOSD_ETM_TASK_GPIO31_SEL_V << GPIOSD_ETM_TASK_GPIO31_SEL_S) -#define GPIOSD_ETM_TASK_GPIO31_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO31_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO31_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO31_SEL_M (GPIO_EXT_ETM_TASK_GPIO31_SEL_V << GPIO_EXT_ETM_TASK_GPIO31_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO31_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO31_SEL_S 25 -/** GPIOSD_ETM_TASK_P8_CFG_REG register +/** GPIO_EXT_ETM_TASK_P8_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P8_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc0) -/** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P8_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc0) +/** GPIO_EXT_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO32_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO32_EN_M (GPIOSD_ETM_TASK_GPIO32_EN_V << GPIOSD_ETM_TASK_GPIO32_EN_S) -#define GPIOSD_ETM_TASK_GPIO32_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO32_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO32_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO32_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO32_EN_M (GPIO_EXT_ETM_TASK_GPIO32_EN_V << GPIO_EXT_ETM_TASK_GPIO32_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO32_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO32_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO32_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO32_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO32_SEL_M (GPIOSD_ETM_TASK_GPIO32_SEL_V << GPIOSD_ETM_TASK_GPIO32_SEL_S) -#define GPIOSD_ETM_TASK_GPIO32_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO32_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO33_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO32_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO32_SEL_M (GPIO_EXT_ETM_TASK_GPIO32_SEL_V << GPIO_EXT_ETM_TASK_GPIO32_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO32_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO32_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO33_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO33_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO33_EN_M (GPIOSD_ETM_TASK_GPIO33_EN_V << GPIOSD_ETM_TASK_GPIO33_EN_S) -#define GPIOSD_ETM_TASK_GPIO33_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO33_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO33_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO33_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO33_EN_M (GPIO_EXT_ETM_TASK_GPIO33_EN_V << GPIO_EXT_ETM_TASK_GPIO33_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO33_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO33_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO33_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO33_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO33_SEL_M (GPIOSD_ETM_TASK_GPIO33_SEL_V << GPIOSD_ETM_TASK_GPIO33_SEL_S) -#define GPIOSD_ETM_TASK_GPIO33_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO33_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO34_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO33_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO33_SEL_M (GPIO_EXT_ETM_TASK_GPIO33_SEL_V << GPIO_EXT_ETM_TASK_GPIO33_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO33_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO33_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO34_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO34_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO34_EN_M (GPIOSD_ETM_TASK_GPIO34_EN_V << GPIOSD_ETM_TASK_GPIO34_EN_S) -#define GPIOSD_ETM_TASK_GPIO34_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO34_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO34_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO34_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO34_EN_M (GPIO_EXT_ETM_TASK_GPIO34_EN_V << GPIO_EXT_ETM_TASK_GPIO34_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO34_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO34_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO34_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO34_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO34_SEL_M (GPIOSD_ETM_TASK_GPIO34_SEL_V << GPIOSD_ETM_TASK_GPIO34_SEL_S) -#define GPIOSD_ETM_TASK_GPIO34_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO34_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO35_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO34_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO34_SEL_M (GPIO_EXT_ETM_TASK_GPIO34_SEL_V << GPIO_EXT_ETM_TASK_GPIO34_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO34_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO34_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO35_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO35_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO35_EN_M (GPIOSD_ETM_TASK_GPIO35_EN_V << GPIOSD_ETM_TASK_GPIO35_EN_S) -#define GPIOSD_ETM_TASK_GPIO35_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO35_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO35_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO35_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO35_EN_M (GPIO_EXT_ETM_TASK_GPIO35_EN_V << GPIO_EXT_ETM_TASK_GPIO35_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO35_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO35_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO35_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO35_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO35_SEL_M (GPIOSD_ETM_TASK_GPIO35_SEL_V << GPIOSD_ETM_TASK_GPIO35_SEL_S) -#define GPIOSD_ETM_TASK_GPIO35_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO35_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO35_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO35_SEL_M (GPIO_EXT_ETM_TASK_GPIO35_SEL_V << GPIO_EXT_ETM_TASK_GPIO35_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO35_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO35_SEL_S 25 -/** GPIOSD_ETM_TASK_P9_CFG_REG register +/** GPIO_EXT_ETM_TASK_P9_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P9_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc4) -/** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P9_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc4) +/** GPIO_EXT_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO36_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO36_EN_M (GPIOSD_ETM_TASK_GPIO36_EN_V << GPIOSD_ETM_TASK_GPIO36_EN_S) -#define GPIOSD_ETM_TASK_GPIO36_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO36_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO36_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO36_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO36_EN_M (GPIO_EXT_ETM_TASK_GPIO36_EN_V << GPIO_EXT_ETM_TASK_GPIO36_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO36_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO36_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO36_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO36_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO36_SEL_M (GPIOSD_ETM_TASK_GPIO36_SEL_V << GPIOSD_ETM_TASK_GPIO36_SEL_S) -#define GPIOSD_ETM_TASK_GPIO36_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO36_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO37_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO36_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO36_SEL_M (GPIO_EXT_ETM_TASK_GPIO36_SEL_V << GPIO_EXT_ETM_TASK_GPIO36_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO36_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO36_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO37_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO37_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO37_EN_M (GPIOSD_ETM_TASK_GPIO37_EN_V << GPIOSD_ETM_TASK_GPIO37_EN_S) -#define GPIOSD_ETM_TASK_GPIO37_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO37_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO37_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO37_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO37_EN_M (GPIO_EXT_ETM_TASK_GPIO37_EN_V << GPIO_EXT_ETM_TASK_GPIO37_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO37_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO37_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO37_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO37_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO37_SEL_M (GPIOSD_ETM_TASK_GPIO37_SEL_V << GPIOSD_ETM_TASK_GPIO37_SEL_S) -#define GPIOSD_ETM_TASK_GPIO37_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO37_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO38_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO37_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO37_SEL_M (GPIO_EXT_ETM_TASK_GPIO37_SEL_V << GPIO_EXT_ETM_TASK_GPIO37_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO37_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO37_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO38_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO38_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO38_EN_M (GPIOSD_ETM_TASK_GPIO38_EN_V << GPIOSD_ETM_TASK_GPIO38_EN_S) -#define GPIOSD_ETM_TASK_GPIO38_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO38_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO38_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO38_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO38_EN_M (GPIO_EXT_ETM_TASK_GPIO38_EN_V << GPIO_EXT_ETM_TASK_GPIO38_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO38_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO38_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO38_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO38_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO38_SEL_M (GPIOSD_ETM_TASK_GPIO38_SEL_V << GPIOSD_ETM_TASK_GPIO38_SEL_S) -#define GPIOSD_ETM_TASK_GPIO38_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO38_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO39_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO38_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO38_SEL_M (GPIO_EXT_ETM_TASK_GPIO38_SEL_V << GPIO_EXT_ETM_TASK_GPIO38_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO38_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO38_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO39_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO39_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO39_EN_M (GPIOSD_ETM_TASK_GPIO39_EN_V << GPIOSD_ETM_TASK_GPIO39_EN_S) -#define GPIOSD_ETM_TASK_GPIO39_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO39_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO39_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO39_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO39_EN_M (GPIO_EXT_ETM_TASK_GPIO39_EN_V << GPIO_EXT_ETM_TASK_GPIO39_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO39_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO39_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO39_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO39_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO39_SEL_M (GPIOSD_ETM_TASK_GPIO39_SEL_V << GPIOSD_ETM_TASK_GPIO39_SEL_S) -#define GPIOSD_ETM_TASK_GPIO39_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO39_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO39_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO39_SEL_M (GPIO_EXT_ETM_TASK_GPIO39_SEL_V << GPIO_EXT_ETM_TASK_GPIO39_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO39_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO39_SEL_S 25 -/** GPIOSD_ETM_TASK_P10_CFG_REG register +/** GPIO_EXT_ETM_TASK_P10_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P10_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc8) -/** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P10_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xc8) +/** GPIO_EXT_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO40_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO40_EN_M (GPIOSD_ETM_TASK_GPIO40_EN_V << GPIOSD_ETM_TASK_GPIO40_EN_S) -#define GPIOSD_ETM_TASK_GPIO40_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO40_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO40_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO40_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO40_EN_M (GPIO_EXT_ETM_TASK_GPIO40_EN_V << GPIO_EXT_ETM_TASK_GPIO40_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO40_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO40_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO40_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO40_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO40_SEL_M (GPIOSD_ETM_TASK_GPIO40_SEL_V << GPIOSD_ETM_TASK_GPIO40_SEL_S) -#define GPIOSD_ETM_TASK_GPIO40_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO40_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO41_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO40_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO40_SEL_M (GPIO_EXT_ETM_TASK_GPIO40_SEL_V << GPIO_EXT_ETM_TASK_GPIO40_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO40_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO40_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO41_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO41_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO41_EN_M (GPIOSD_ETM_TASK_GPIO41_EN_V << GPIOSD_ETM_TASK_GPIO41_EN_S) -#define GPIOSD_ETM_TASK_GPIO41_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO41_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO41_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO41_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO41_EN_M (GPIO_EXT_ETM_TASK_GPIO41_EN_V << GPIO_EXT_ETM_TASK_GPIO41_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO41_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO41_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO41_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO41_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO41_SEL_M (GPIOSD_ETM_TASK_GPIO41_SEL_V << GPIOSD_ETM_TASK_GPIO41_SEL_S) -#define GPIOSD_ETM_TASK_GPIO41_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO41_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO42_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO41_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO41_SEL_M (GPIO_EXT_ETM_TASK_GPIO41_SEL_V << GPIO_EXT_ETM_TASK_GPIO41_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO41_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO41_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO42_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO42_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO42_EN_M (GPIOSD_ETM_TASK_GPIO42_EN_V << GPIOSD_ETM_TASK_GPIO42_EN_S) -#define GPIOSD_ETM_TASK_GPIO42_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO42_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO42_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO42_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO42_EN_M (GPIO_EXT_ETM_TASK_GPIO42_EN_V << GPIO_EXT_ETM_TASK_GPIO42_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO42_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO42_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO42_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO42_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO42_SEL_M (GPIOSD_ETM_TASK_GPIO42_SEL_V << GPIOSD_ETM_TASK_GPIO42_SEL_S) -#define GPIOSD_ETM_TASK_GPIO42_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO42_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO43_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO42_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO42_SEL_M (GPIO_EXT_ETM_TASK_GPIO42_SEL_V << GPIO_EXT_ETM_TASK_GPIO42_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO42_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO42_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO43_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO43_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO43_EN_M (GPIOSD_ETM_TASK_GPIO43_EN_V << GPIOSD_ETM_TASK_GPIO43_EN_S) -#define GPIOSD_ETM_TASK_GPIO43_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO43_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO43_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO43_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO43_EN_M (GPIO_EXT_ETM_TASK_GPIO43_EN_V << GPIO_EXT_ETM_TASK_GPIO43_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO43_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO43_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO43_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO43_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO43_SEL_M (GPIOSD_ETM_TASK_GPIO43_SEL_V << GPIOSD_ETM_TASK_GPIO43_SEL_S) -#define GPIOSD_ETM_TASK_GPIO43_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO43_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO43_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO43_SEL_M (GPIO_EXT_ETM_TASK_GPIO43_SEL_V << GPIO_EXT_ETM_TASK_GPIO43_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO43_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO43_SEL_S 25 -/** GPIOSD_ETM_TASK_P11_CFG_REG register +/** GPIO_EXT_ETM_TASK_P11_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P11_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xcc) -/** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P11_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xcc) +/** GPIO_EXT_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO44_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO44_EN_M (GPIOSD_ETM_TASK_GPIO44_EN_V << GPIOSD_ETM_TASK_GPIO44_EN_S) -#define GPIOSD_ETM_TASK_GPIO44_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO44_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO44_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO44_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO44_EN_M (GPIO_EXT_ETM_TASK_GPIO44_EN_V << GPIO_EXT_ETM_TASK_GPIO44_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO44_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO44_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO44_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO44_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO44_SEL_M (GPIOSD_ETM_TASK_GPIO44_SEL_V << GPIOSD_ETM_TASK_GPIO44_SEL_S) -#define GPIOSD_ETM_TASK_GPIO44_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO44_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO45_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO44_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO44_SEL_M (GPIO_EXT_ETM_TASK_GPIO44_SEL_V << GPIO_EXT_ETM_TASK_GPIO44_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO44_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO44_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO45_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO45_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO45_EN_M (GPIOSD_ETM_TASK_GPIO45_EN_V << GPIOSD_ETM_TASK_GPIO45_EN_S) -#define GPIOSD_ETM_TASK_GPIO45_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO45_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO45_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO45_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO45_EN_M (GPIO_EXT_ETM_TASK_GPIO45_EN_V << GPIO_EXT_ETM_TASK_GPIO45_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO45_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO45_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO45_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO45_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO45_SEL_M (GPIOSD_ETM_TASK_GPIO45_SEL_V << GPIOSD_ETM_TASK_GPIO45_SEL_S) -#define GPIOSD_ETM_TASK_GPIO45_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO45_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO46_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO45_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO45_SEL_M (GPIO_EXT_ETM_TASK_GPIO45_SEL_V << GPIO_EXT_ETM_TASK_GPIO45_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO45_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO45_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO46_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO46_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO46_EN_M (GPIOSD_ETM_TASK_GPIO46_EN_V << GPIOSD_ETM_TASK_GPIO46_EN_S) -#define GPIOSD_ETM_TASK_GPIO46_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO46_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO46_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO46_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO46_EN_M (GPIO_EXT_ETM_TASK_GPIO46_EN_V << GPIO_EXT_ETM_TASK_GPIO46_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO46_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO46_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO46_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO46_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO46_SEL_M (GPIOSD_ETM_TASK_GPIO46_SEL_V << GPIOSD_ETM_TASK_GPIO46_SEL_S) -#define GPIOSD_ETM_TASK_GPIO46_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO46_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO47_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO46_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO46_SEL_M (GPIO_EXT_ETM_TASK_GPIO46_SEL_V << GPIO_EXT_ETM_TASK_GPIO46_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO46_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO46_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO47_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO47_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO47_EN_M (GPIOSD_ETM_TASK_GPIO47_EN_V << GPIOSD_ETM_TASK_GPIO47_EN_S) -#define GPIOSD_ETM_TASK_GPIO47_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO47_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO47_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO47_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO47_EN_M (GPIO_EXT_ETM_TASK_GPIO47_EN_V << GPIO_EXT_ETM_TASK_GPIO47_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO47_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO47_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO47_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO47_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO47_SEL_M (GPIOSD_ETM_TASK_GPIO47_SEL_V << GPIOSD_ETM_TASK_GPIO47_SEL_S) -#define GPIOSD_ETM_TASK_GPIO47_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO47_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO47_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO47_SEL_M (GPIO_EXT_ETM_TASK_GPIO47_SEL_V << GPIO_EXT_ETM_TASK_GPIO47_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO47_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO47_SEL_S 25 -/** GPIOSD_ETM_TASK_P12_CFG_REG register +/** GPIO_EXT_ETM_TASK_P12_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P12_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd0) -/** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P12_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd0) +/** GPIO_EXT_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO48_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO48_EN_M (GPIOSD_ETM_TASK_GPIO48_EN_V << GPIOSD_ETM_TASK_GPIO48_EN_S) -#define GPIOSD_ETM_TASK_GPIO48_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO48_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO48_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO48_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO48_EN_M (GPIO_EXT_ETM_TASK_GPIO48_EN_V << GPIO_EXT_ETM_TASK_GPIO48_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO48_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO48_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO48_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO48_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO48_SEL_M (GPIOSD_ETM_TASK_GPIO48_SEL_V << GPIOSD_ETM_TASK_GPIO48_SEL_S) -#define GPIOSD_ETM_TASK_GPIO48_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO48_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO49_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO48_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO48_SEL_M (GPIO_EXT_ETM_TASK_GPIO48_SEL_V << GPIO_EXT_ETM_TASK_GPIO48_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO48_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO48_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO49_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO49_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO49_EN_M (GPIOSD_ETM_TASK_GPIO49_EN_V << GPIOSD_ETM_TASK_GPIO49_EN_S) -#define GPIOSD_ETM_TASK_GPIO49_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO49_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO49_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO49_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO49_EN_M (GPIO_EXT_ETM_TASK_GPIO49_EN_V << GPIO_EXT_ETM_TASK_GPIO49_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO49_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO49_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO49_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO49_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO49_SEL_M (GPIOSD_ETM_TASK_GPIO49_SEL_V << GPIOSD_ETM_TASK_GPIO49_SEL_S) -#define GPIOSD_ETM_TASK_GPIO49_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO49_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO50_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO49_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO49_SEL_M (GPIO_EXT_ETM_TASK_GPIO49_SEL_V << GPIO_EXT_ETM_TASK_GPIO49_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO49_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO49_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO50_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO50_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO50_EN_M (GPIOSD_ETM_TASK_GPIO50_EN_V << GPIOSD_ETM_TASK_GPIO50_EN_S) -#define GPIOSD_ETM_TASK_GPIO50_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO50_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO50_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO50_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO50_EN_M (GPIO_EXT_ETM_TASK_GPIO50_EN_V << GPIO_EXT_ETM_TASK_GPIO50_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO50_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO50_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO50_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO50_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO50_SEL_M (GPIOSD_ETM_TASK_GPIO50_SEL_V << GPIOSD_ETM_TASK_GPIO50_SEL_S) -#define GPIOSD_ETM_TASK_GPIO50_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO50_SEL_S 17 -/** GPIOSD_ETM_TASK_GPIO51_EN : R/W; bitpos: [24]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO50_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO50_SEL_M (GPIO_EXT_ETM_TASK_GPIO50_SEL_V << GPIO_EXT_ETM_TASK_GPIO50_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO50_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO50_SEL_S 17 +/** GPIO_EXT_ETM_TASK_GPIO51_EN : R/W; bitpos: [24]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO51_EN (BIT(24)) -#define GPIOSD_ETM_TASK_GPIO51_EN_M (GPIOSD_ETM_TASK_GPIO51_EN_V << GPIOSD_ETM_TASK_GPIO51_EN_S) -#define GPIOSD_ETM_TASK_GPIO51_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO51_EN_S 24 -/** GPIOSD_ETM_TASK_GPIO51_SEL : R/W; bitpos: [27:25]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO51_EN (BIT(24)) +#define GPIO_EXT_ETM_TASK_GPIO51_EN_M (GPIO_EXT_ETM_TASK_GPIO51_EN_V << GPIO_EXT_ETM_TASK_GPIO51_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO51_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO51_EN_S 24 +/** GPIO_EXT_ETM_TASK_GPIO51_SEL : R/W; bitpos: [27:25]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO51_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO51_SEL_M (GPIOSD_ETM_TASK_GPIO51_SEL_V << GPIOSD_ETM_TASK_GPIO51_SEL_S) -#define GPIOSD_ETM_TASK_GPIO51_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO51_SEL_S 25 +#define GPIO_EXT_ETM_TASK_GPIO51_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO51_SEL_M (GPIO_EXT_ETM_TASK_GPIO51_SEL_V << GPIO_EXT_ETM_TASK_GPIO51_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO51_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO51_SEL_S 25 -/** GPIOSD_ETM_TASK_P13_CFG_REG register +/** GPIO_EXT_ETM_TASK_P13_CFG_REG register * Etm Configure Register to decide which GPIO been chosen */ -#define GPIOSD_ETM_TASK_P13_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd4) -/** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0; +#define GPIO_EXT_ETM_TASK_P13_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xd4) +/** GPIO_EXT_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO52_EN (BIT(0)) -#define GPIOSD_ETM_TASK_GPIO52_EN_M (GPIOSD_ETM_TASK_GPIO52_EN_V << GPIOSD_ETM_TASK_GPIO52_EN_S) -#define GPIOSD_ETM_TASK_GPIO52_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO52_EN_S 0 -/** GPIOSD_ETM_TASK_GPIO52_SEL : R/W; bitpos: [3:1]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO52_EN (BIT(0)) +#define GPIO_EXT_ETM_TASK_GPIO52_EN_M (GPIO_EXT_ETM_TASK_GPIO52_EN_V << GPIO_EXT_ETM_TASK_GPIO52_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO52_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO52_EN_S 0 +/** GPIO_EXT_ETM_TASK_GPIO52_SEL : R/W; bitpos: [3:1]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO52_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO52_SEL_M (GPIOSD_ETM_TASK_GPIO52_SEL_V << GPIOSD_ETM_TASK_GPIO52_SEL_S) -#define GPIOSD_ETM_TASK_GPIO52_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO52_SEL_S 1 -/** GPIOSD_ETM_TASK_GPIO53_EN : R/W; bitpos: [8]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO52_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO52_SEL_M (GPIO_EXT_ETM_TASK_GPIO52_SEL_V << GPIO_EXT_ETM_TASK_GPIO52_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO52_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO52_SEL_S 1 +/** GPIO_EXT_ETM_TASK_GPIO53_EN : R/W; bitpos: [8]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO53_EN (BIT(8)) -#define GPIOSD_ETM_TASK_GPIO53_EN_M (GPIOSD_ETM_TASK_GPIO53_EN_V << GPIOSD_ETM_TASK_GPIO53_EN_S) -#define GPIOSD_ETM_TASK_GPIO53_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO53_EN_S 8 -/** GPIOSD_ETM_TASK_GPIO53_SEL : R/W; bitpos: [11:9]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO53_EN (BIT(8)) +#define GPIO_EXT_ETM_TASK_GPIO53_EN_M (GPIO_EXT_ETM_TASK_GPIO53_EN_V << GPIO_EXT_ETM_TASK_GPIO53_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO53_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO53_EN_S 8 +/** GPIO_EXT_ETM_TASK_GPIO53_SEL : R/W; bitpos: [11:9]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO53_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO53_SEL_M (GPIOSD_ETM_TASK_GPIO53_SEL_V << GPIOSD_ETM_TASK_GPIO53_SEL_S) -#define GPIOSD_ETM_TASK_GPIO53_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO53_SEL_S 9 -/** GPIOSD_ETM_TASK_GPIO54_EN : R/W; bitpos: [16]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO53_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO53_SEL_M (GPIO_EXT_ETM_TASK_GPIO53_SEL_V << GPIO_EXT_ETM_TASK_GPIO53_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO53_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO53_SEL_S 9 +/** GPIO_EXT_ETM_TASK_GPIO54_EN : R/W; bitpos: [16]; default: 0; * Enable bit of GPIO response etm task. */ -#define GPIOSD_ETM_TASK_GPIO54_EN (BIT(16)) -#define GPIOSD_ETM_TASK_GPIO54_EN_M (GPIOSD_ETM_TASK_GPIO54_EN_V << GPIOSD_ETM_TASK_GPIO54_EN_S) -#define GPIOSD_ETM_TASK_GPIO54_EN_V 0x00000001U -#define GPIOSD_ETM_TASK_GPIO54_EN_S 16 -/** GPIOSD_ETM_TASK_GPIO54_SEL : R/W; bitpos: [19:17]; default: 0; +#define GPIO_EXT_ETM_TASK_GPIO54_EN (BIT(16)) +#define GPIO_EXT_ETM_TASK_GPIO54_EN_M (GPIO_EXT_ETM_TASK_GPIO54_EN_V << GPIO_EXT_ETM_TASK_GPIO54_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO54_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO54_EN_S 16 +/** GPIO_EXT_ETM_TASK_GPIO54_SEL : R/W; bitpos: [19:17]; default: 0; * GPIO choose a etm task channel. */ -#define GPIOSD_ETM_TASK_GPIO54_SEL 0x00000007U -#define GPIOSD_ETM_TASK_GPIO54_SEL_M (GPIOSD_ETM_TASK_GPIO54_SEL_V << GPIOSD_ETM_TASK_GPIO54_SEL_S) -#define GPIOSD_ETM_TASK_GPIO54_SEL_V 0x00000007U -#define GPIOSD_ETM_TASK_GPIO54_SEL_S 17 +#define GPIO_EXT_ETM_TASK_GPIO54_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO54_SEL_M (GPIO_EXT_ETM_TASK_GPIO54_SEL_V << GPIO_EXT_ETM_TASK_GPIO54_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO54_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO54_SEL_S 17 -/** GPIOSD_VERSION_REG register +/** GPIO_EXT_VERSION_REG register * Version Control Register */ -#define GPIOSD_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) -/** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952; +#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc) +/** GPIO_EXT_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952; * Version control register. */ -#define GPIOSD_GPIO_SD_DATE 0x0FFFFFFFU -#define GPIOSD_GPIO_SD_DATE_M (GPIOSD_GPIO_SD_DATE_V << GPIOSD_GPIO_SD_DATE_S) -#define GPIOSD_GPIO_SD_DATE_V 0x0FFFFFFFU -#define GPIOSD_GPIO_SD_DATE_S 0 +#define GPIO_EXT_DATE 0x0FFFFFFFU +#define GPIO_EXT_DATE_M (GPIO_EXT_DATE_V << GPIO_EXT_DATE_S) +#define GPIO_EXT_DATE_V 0x0FFFFFFFU +#define GPIO_EXT_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/gpio_ext_struct.h b/components/soc/esp32p4/include/soc/gpio_ext_struct.h index 54e9030a97..c4ea00e07a 100644 --- a/components/soc/esp32p4/include/soc/gpio_ext_struct.h +++ b/components/soc/esp32p4/include/soc/gpio_ext_struct.h @@ -16,18 +16,18 @@ extern "C" { */ typedef union { struct { - /** sd0_in : R/W; bitpos: [7:0]; default: 0; + /** duty : R/W; bitpos: [7:0]; default: 0; * This field is used to configure the duty cycle of sigma delta modulation output. */ - uint32_t sd0_in:8; - /** sd0_prescale : R/W; bitpos: [15:8]; default: 255; + uint32_t duty:8; + /** prescale : R/W; bitpos: [15:8]; default: 255; * This field is used to set a divider value to divide APB clock. */ - uint32_t sd0_prescale:8; + uint32_t prescale:8; uint32_t reserved_16:16; }; uint32_t val; -} gpiosd_sigmadeltan_reg_t; +} gpio_sigmadelta_chn_reg_t; /** Type of sigmadelta_misc register * MISC Register @@ -45,7 +45,7 @@ typedef union { uint32_t spi_swap:1; }; uint32_t val; -} gpiosd_sigmadelta_misc_reg_t; +} gpio_sigmadelta_misc_reg_t; /** Group: Glitch filter Configure Registers */ @@ -54,26 +54,26 @@ typedef union { */ typedef union { struct { - /** filter_ch0_en : R/W; bitpos: [0]; default: 0; + /** filter_chn_en : R/W; bitpos: [0]; default: 0; * Glitch Filter channel enable bit. */ - uint32_t filter_ch0_en:1; - /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; + uint32_t filter_chn_en:1; + /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0; * Glitch Filter input io number. */ - uint32_t filter_ch0_input_io_num:6; - /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; + uint32_t filter_chn_input_io_num:6; + /** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0; * Glitch Filter window threshold. */ - uint32_t filter_ch0_window_thres:6; - /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; + uint32_t filter_chn_window_thres:6; + /** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0; * Glitch Filter window width. */ - uint32_t filter_ch0_window_width:6; + uint32_t filter_chn_window_width:6; uint32_t reserved_19:13; }; uint32_t val; -} gpiosd_glitch_filter_chn_reg_t; +} gpio_glitch_filter_chn_reg_t; /** Group: Etm Configure Registers */ @@ -82,19 +82,19 @@ typedef union { */ typedef union { struct { - /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0; + /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0; * Etm event channel select gpio. */ - uint32_t etm_ch0_event_sel:6; + uint32_t etm_chn_event_sel:6; uint32_t reserved_6:1; - /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; + /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; * Etm event send enable bit. */ - uint32_t etm_ch0_event_en:1; + uint32_t etm_chn_event_en:1; uint32_t reserved_8:24; }; uint32_t val; -} gpiosd_etm_event_chn_cfg_reg_t; +} gpio_etm_event_chn_cfg_reg_t; /** Type of etm_task_p0_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -139,7 +139,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p0_cfg_reg_t; +} gpio_etm_task_p0_cfg_reg_t; /** Type of etm_task_p1_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -184,7 +184,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p1_cfg_reg_t; +} gpio_etm_task_p1_cfg_reg_t; /** Type of etm_task_p2_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -229,7 +229,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p2_cfg_reg_t; +} gpio_etm_task_p2_cfg_reg_t; /** Type of etm_task_p3_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -274,7 +274,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p3_cfg_reg_t; +} gpio_etm_task_p3_cfg_reg_t; /** Type of etm_task_p4_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -319,7 +319,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p4_cfg_reg_t; +} gpio_etm_task_p4_cfg_reg_t; /** Type of etm_task_p5_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -364,7 +364,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p5_cfg_reg_t; +} gpio_etm_task_p5_cfg_reg_t; /** Type of etm_task_p6_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -409,7 +409,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p6_cfg_reg_t; +} gpio_etm_task_p6_cfg_reg_t; /** Type of etm_task_p7_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -454,7 +454,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p7_cfg_reg_t; +} gpio_etm_task_p7_cfg_reg_t; /** Type of etm_task_p8_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -499,7 +499,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p8_cfg_reg_t; +} gpio_etm_task_p8_cfg_reg_t; /** Type of etm_task_p9_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -544,7 +544,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p9_cfg_reg_t; +} gpio_etm_task_p9_cfg_reg_t; /** Type of etm_task_p10_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -589,7 +589,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p10_cfg_reg_t; +} gpio_etm_task_p10_cfg_reg_t; /** Type of etm_task_p11_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -634,7 +634,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p11_cfg_reg_t; +} gpio_etm_task_p11_cfg_reg_t; /** Type of etm_task_p12_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -679,7 +679,7 @@ typedef union { uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_etm_task_p12_cfg_reg_t; +} gpio_etm_task_p12_cfg_reg_t; /** Type of etm_task_p13_cfg register * Etm Configure Register to decide which GPIO been chosen @@ -715,7 +715,7 @@ typedef union { uint32_t reserved_20:12; }; uint32_t val; -} gpiosd_etm_task_p13_cfg_reg_t; +} gpio_etm_task_p13_cfg_reg_t; /** Group: Version Register */ @@ -724,46 +724,62 @@ typedef union { */ typedef union { struct { - /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952; + /** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952; * Version control register. */ - uint32_t gpio_sd_date:28; + uint32_t gpio_ext_date:28; uint32_t reserved_28:4; }; uint32_t val; -} gpiosd_version_reg_t; +} gpio_ext_version_reg_t; +typedef struct gpio_sd_dev_t { + volatile gpio_sigmadelta_chn_reg_t channel[8]; + uint32_t reserved_020; + volatile gpio_sigmadelta_misc_reg_t misc; +} gpio_sd_dev_t; + +typedef struct gpio_glitch_filter_dev_t { + volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8]; +} gpio_glitch_filter_dev_t; + +typedef struct gpio_etm_dev_t { + volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; + uint32_t reserved_080[8]; + volatile gpio_etm_task_p0_cfg_reg_t etm_task_p0_cfg; + volatile gpio_etm_task_p1_cfg_reg_t etm_task_p1_cfg; + volatile gpio_etm_task_p2_cfg_reg_t etm_task_p2_cfg; + volatile gpio_etm_task_p3_cfg_reg_t etm_task_p3_cfg; + volatile gpio_etm_task_p4_cfg_reg_t etm_task_p4_cfg; + volatile gpio_etm_task_p5_cfg_reg_t etm_task_p5_cfg; + volatile gpio_etm_task_p6_cfg_reg_t etm_task_p6_cfg; + volatile gpio_etm_task_p7_cfg_reg_t etm_task_p7_cfg; + volatile gpio_etm_task_p8_cfg_reg_t etm_task_p8_cfg; + volatile gpio_etm_task_p9_cfg_reg_t etm_task_p9_cfg; + volatile gpio_etm_task_p10_cfg_reg_t etm_task_p10_cfg; + volatile gpio_etm_task_p11_cfg_reg_t etm_task_p11_cfg; + volatile gpio_etm_task_p12_cfg_reg_t etm_task_p12_cfg; + volatile gpio_etm_task_p13_cfg_reg_t etm_task_p13_cfg; +} gpio_etm_dev_t; + typedef struct { - volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8]; - uint32_t reserved_020; - volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc; + volatile gpio_sd_dev_t sigma_delta; uint32_t reserved_028[2]; - volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8]; + volatile gpio_glitch_filter_dev_t glitch_filter; uint32_t reserved_050[4]; - volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_080[8]; - volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg; - volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg; - volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg; - volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg; - volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg; - volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg; - volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg; - volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg; - volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg; - volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg; + volatile gpio_etm_dev_t etm; uint32_t reserved_0d8[9]; - volatile gpiosd_version_reg_t version; -} gpiosd_dev_t; + volatile gpio_ext_version_reg_t version; +} gpio_ext_dev_t; +extern gpio_sd_dev_t SDM; +extern gpio_glitch_filter_dev_t GLITCH_FILTER; +extern gpio_etm_dev_t GPIO_ETM; +extern gpio_ext_dev_t GPIO_EXT; #ifndef __cplusplus -_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure"); +_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/gpio_num.h b/components/soc/esp32p4/include/soc/gpio_num.h index df655b3f27..f191f8e0f5 100644 --- a/components/soc/esp32p4/include/soc/gpio_num.h +++ b/components/soc/esp32p4/include/soc/gpio_num.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,9 +10,68 @@ extern "C" { #endif -// TODO: IDF-6509 +/** + * @brief GPIO number + */ typedef enum { GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ + GPIO_NUM_30 = 30, /*!< GPIO30, input and output */ + GPIO_NUM_31 = 31, /*!< GPIO31, input and output */ + GPIO_NUM_32 = 32, /*!< GPIO32, input and output */ + GPIO_NUM_33 = 33, /*!< GPIO33, input and output */ + GPIO_NUM_34 = 34, /*!< GPIO34, input and output */ + GPIO_NUM_35 = 35, /*!< GPIO35, input and output */ + GPIO_NUM_36 = 36, /*!< GPIO36, input and output */ + GPIO_NUM_37 = 37, /*!< GPIO37, input and output */ + GPIO_NUM_38 = 38, /*!< GPIO38, input and output */ + GPIO_NUM_39 = 39, /*!< GPIO39, input and output */ + GPIO_NUM_40 = 40, /*!< GPIO40, input and output */ + GPIO_NUM_41 = 41, /*!< GPIO41, input and output */ + GPIO_NUM_42 = 42, /*!< GPIO42, input and output */ + GPIO_NUM_43 = 43, /*!< GPIO43, input and output */ + GPIO_NUM_44 = 44, /*!< GPIO44, input and output */ + GPIO_NUM_45 = 45, /*!< GPIO45, input and output */ + GPIO_NUM_46 = 46, /*!< GPIO46, input and output */ + GPIO_NUM_47 = 47, /*!< GPIO47, input and output */ + GPIO_NUM_48 = 48, /*!< GPIO48, input and output */ + GPIO_NUM_49 = 49, /*!< GPIO49, input and output */ + GPIO_NUM_50 = 50, /*!< GPIO50, input and output */ + GPIO_NUM_51 = 51, /*!< GPIO51, input and output */ + GPIO_NUM_52 = 52, /*!< GPIO52, input and output */ + GPIO_NUM_53 = 53, /*!< GPIO53, input and output */ + GPIO_NUM_54 = 54, /*!< GPIO54, input and output */ + GPIO_NUM_55 = 55, /*!< GPIO55, input and output */ + GPIO_NUM_56 = 56, /*!< GPIO56, input and output */ GPIO_NUM_MAX, } gpio_num_t; diff --git a/components/soc/esp32p4/include/soc/gpio_pins.h b/components/soc/esp32p4/include/soc/gpio_pins.h index 6238eeffbb..baaf358edf 100644 --- a/components/soc/esp32p4/include/soc/gpio_pins.h +++ b/components/soc/esp32p4/include/soc/gpio_pins.h @@ -11,6 +11,8 @@ extern "C" { #endif +#define GPIO_MATRIX_CONST_ONE_INPUT (0x3F) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3E) #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/gpio_reg.h b/components/soc/esp32p4/include/soc/gpio_reg.h index 42a7c7fff9..014c375394 100644 --- a/components/soc/esp32p4/include/soc/gpio_reg.h +++ b/components/soc/esp32p4/include/soc/gpio_reg.h @@ -3710,33 +3710,6 @@ extern "C" { #define GPIO_PIN56_INT_ENA_V 0x0000001FU #define GPIO_PIN56_INT_ENA_S 13 -/** GPIO_FUNC0_IN_SEL_CFG_REG register - * GPIO input function configuration register - */ -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) -/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ -#define GPIO_FUNC0_IN_SEL 0x0000003FU -#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) -#define GPIO_FUNC0_IN_SEL_V 0x0000003FU -#define GPIO_FUNC0_IN_SEL_S 0 -/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) -#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) -#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_IN_INV_SEL_S 6 -/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ -#define GPIO_SIG0_IN_SEL (BIT(7)) -#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) -#define GPIO_SIG0_IN_SEL_V 0x00000001U -#define GPIO_SIG0_IN_SEL_S 7 - /** GPIO_FUNC1_IN_SEL_CFG_REG register * GPIO input function configuration register */ diff --git a/components/soc/esp32p4/include/soc/gpio_struct.h b/components/soc/esp32p4/include/soc/gpio_struct.h index eb487495eb..7aaade2883 100644 --- a/components/soc/esp32p4/include/soc/gpio_struct.h +++ b/components/soc/esp32p4/include/soc/gpio_struct.h @@ -389,5230 +389,101 @@ typedef union { uint32_t val; } gpio_status_next1_reg_t; -/** Type of pinn register +/** Type of pin register * GPIO pin configuration register */ typedef union { struct { - /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + /** sync2_bypass : R/W; bitpos: [1:0]; default: 0; * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at * posedge. */ - uint32_t pinn_sync2_bypass:2; - /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; + uint32_t sync2_bypass:2; + /** pad_driver : R/W; bitpos: [2]; default: 0; * set this bit to select pad driver. 1:open-drain. 0:normal. */ - uint32_t pinn_pad_driver:1; - /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + uint32_t pad_driver:1; + /** sync1_bypass : R/W; bitpos: [4:3]; default: 0; * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at * posedge. */ - uint32_t pinn_sync1_bypass:2; + uint32_t sync1_bypass:2; uint32_t reserved_5:2; - /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; + /** int_type : R/W; bitpos: [9:7]; default: 0; * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid * at high level */ - uint32_t pinn_int_type:3; - /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + uint32_t int_type:3; + /** wakeup_enable : R/W; bitpos: [10]; default: 0; * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ - uint32_t pinn_wakeup_enable:1; - /** pinn_config : R/W; bitpos: [12:11]; default: 0; + uint32_t wakeup_enable:1; + /** config : R/W; bitpos: [12:11]; default: 0; * reserved */ - uint32_t pinn_config:2; - /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; + uint32_t config:2; + /** int_ena : R/W; bitpos: [17:13]; default: 0; * set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) * interrupt. */ - uint32_t pinn_int_ena:5; + uint32_t int_ena:5; uint32_t reserved_18:14; }; uint32_t val; -} gpio_pinn_reg_t; +} gpio_pin_reg_t; -/** Type of func1_in_sel_cfg register +/** Type of func_in_sel_cfg register * GPIO input function configuration register */ typedef union { struct { - /** func1_in_sel : R/W; bitpos: [5:0]; default: 63; + /** in_sel : R/W; bitpos: [5:0]; default: 63; * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always * high level. s=0x3E: set this port always low level. */ - uint32_t func1_in_sel:6; - /** func1_in_inv_sel : R/W; bitpos: [6]; default: 0; + uint32_t in_sel:6; + /** in_inv_sel : R/W; bitpos: [6]; default: 0; * set this bit to invert input signal. 1:invert. 0:not invert. */ - uint32_t func1_in_inv_sel:1; - /** sig1_in_sel : R/W; bitpos: [7]; default: 0; + uint32_t in_inv_sel:1; + /** sig_in_sel : R/W; bitpos: [7]; default: 0; * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ - uint32_t sig1_in_sel:1; + uint32_t sig_in_sel:1; uint32_t reserved_8:24; }; uint32_t val; -} gpio_func1_in_sel_cfg_reg_t; +} gpio_func_in_sel_cfg_reg_t; -/** Type of func2_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func2_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func2_in_sel:6; - /** func2_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func2_in_inv_sel:1; - /** sig2_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig2_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func2_in_sel_cfg_reg_t; - -/** Type of func3_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func3_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func3_in_sel:6; - /** func3_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func3_in_inv_sel:1; - /** sig3_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig3_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func3_in_sel_cfg_reg_t; - -/** Type of func4_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func4_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func4_in_sel:6; - /** func4_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func4_in_inv_sel:1; - /** sig4_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig4_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func4_in_sel_cfg_reg_t; - -/** Type of func5_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func5_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func5_in_sel:6; - /** func5_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func5_in_inv_sel:1; - /** sig5_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig5_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func5_in_sel_cfg_reg_t; - -/** Type of func6_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func6_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func6_in_sel:6; - /** func6_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func6_in_inv_sel:1; - /** sig6_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig6_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func6_in_sel_cfg_reg_t; - -/** Type of func7_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func7_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func7_in_sel:6; - /** func7_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func7_in_inv_sel:1; - /** sig7_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig7_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func7_in_sel_cfg_reg_t; - -/** Type of func8_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func8_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func8_in_sel:6; - /** func8_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func8_in_inv_sel:1; - /** sig8_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig8_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func8_in_sel_cfg_reg_t; - -/** Type of func9_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func9_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func9_in_sel:6; - /** func9_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func9_in_inv_sel:1; - /** sig9_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig9_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func9_in_sel_cfg_reg_t; - -/** Type of func10_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func10_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func10_in_sel:6; - /** func10_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func10_in_inv_sel:1; - /** sig10_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig10_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func10_in_sel_cfg_reg_t; - -/** Type of func11_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func11_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func11_in_sel:6; - /** func11_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func11_in_inv_sel:1; - /** sig11_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig11_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func11_in_sel_cfg_reg_t; - -/** Type of func12_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func12_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func12_in_sel:6; - /** func12_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func12_in_inv_sel:1; - /** sig12_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig12_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func12_in_sel_cfg_reg_t; - -/** Type of func13_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func13_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func13_in_sel:6; - /** func13_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func13_in_inv_sel:1; - /** sig13_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig13_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func13_in_sel_cfg_reg_t; - -/** Type of func14_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func14_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func14_in_sel:6; - /** func14_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func14_in_inv_sel:1; - /** sig14_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig14_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func14_in_sel_cfg_reg_t; - -/** Type of func15_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func15_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func15_in_sel:6; - /** func15_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func15_in_inv_sel:1; - /** sig15_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig15_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func15_in_sel_cfg_reg_t; - -/** Type of func16_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func16_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func16_in_sel:6; - /** func16_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func16_in_inv_sel:1; - /** sig16_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig16_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func16_in_sel_cfg_reg_t; - -/** Type of func17_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func17_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func17_in_sel:6; - /** func17_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func17_in_inv_sel:1; - /** sig17_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig17_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func17_in_sel_cfg_reg_t; - -/** Type of func18_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func18_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func18_in_sel:6; - /** func18_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func18_in_inv_sel:1; - /** sig18_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig18_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func18_in_sel_cfg_reg_t; - -/** Type of func19_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func19_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func19_in_sel:6; - /** func19_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func19_in_inv_sel:1; - /** sig19_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig19_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func19_in_sel_cfg_reg_t; - -/** Type of func20_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func20_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func20_in_sel:6; - /** func20_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func20_in_inv_sel:1; - /** sig20_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig20_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func20_in_sel_cfg_reg_t; - -/** Type of func21_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func21_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func21_in_sel:6; - /** func21_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func21_in_inv_sel:1; - /** sig21_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig21_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func21_in_sel_cfg_reg_t; - -/** Type of func22_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func22_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func22_in_sel:6; - /** func22_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func22_in_inv_sel:1; - /** sig22_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig22_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func22_in_sel_cfg_reg_t; - -/** Type of func23_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func23_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func23_in_sel:6; - /** func23_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func23_in_inv_sel:1; - /** sig23_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig23_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func23_in_sel_cfg_reg_t; - -/** Type of func24_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func24_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func24_in_sel:6; - /** func24_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func24_in_inv_sel:1; - /** sig24_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig24_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func24_in_sel_cfg_reg_t; - -/** Type of func25_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func25_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func25_in_sel:6; - /** func25_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func25_in_inv_sel:1; - /** sig25_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig25_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func25_in_sel_cfg_reg_t; - -/** Type of func26_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func26_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func26_in_sel:6; - /** func26_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func26_in_inv_sel:1; - /** sig26_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig26_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func26_in_sel_cfg_reg_t; - -/** Type of func27_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func27_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func27_in_sel:6; - /** func27_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func27_in_inv_sel:1; - /** sig27_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig27_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func27_in_sel_cfg_reg_t; - -/** Type of func28_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func28_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func28_in_sel:6; - /** func28_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func28_in_inv_sel:1; - /** sig28_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig28_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func28_in_sel_cfg_reg_t; - -/** Type of func29_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func29_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func29_in_sel:6; - /** func29_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func29_in_inv_sel:1; - /** sig29_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig29_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func29_in_sel_cfg_reg_t; - -/** Type of func30_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func30_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func30_in_sel:6; - /** func30_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func30_in_inv_sel:1; - /** sig30_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig30_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func30_in_sel_cfg_reg_t; - -/** Type of func31_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func31_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func31_in_sel:6; - /** func31_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func31_in_inv_sel:1; - /** sig31_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig31_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func31_in_sel_cfg_reg_t; - -/** Type of func32_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func32_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func32_in_sel:6; - /** func32_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func32_in_inv_sel:1; - /** sig32_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig32_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func32_in_sel_cfg_reg_t; - -/** Type of func33_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func33_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func33_in_sel:6; - /** func33_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func33_in_inv_sel:1; - /** sig33_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig33_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func33_in_sel_cfg_reg_t; - -/** Type of func34_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func34_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func34_in_sel:6; - /** func34_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func34_in_inv_sel:1; - /** sig34_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig34_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func34_in_sel_cfg_reg_t; - -/** Type of func35_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func35_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func35_in_sel:6; - /** func35_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func35_in_inv_sel:1; - /** sig35_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig35_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func35_in_sel_cfg_reg_t; - -/** Type of func36_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func36_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func36_in_sel:6; - /** func36_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func36_in_inv_sel:1; - /** sig36_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig36_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func36_in_sel_cfg_reg_t; - -/** Type of func37_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func37_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func37_in_sel:6; - /** func37_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func37_in_inv_sel:1; - /** sig37_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig37_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func37_in_sel_cfg_reg_t; - -/** Type of func38_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func38_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func38_in_sel:6; - /** func38_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func38_in_inv_sel:1; - /** sig38_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig38_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func38_in_sel_cfg_reg_t; - -/** Type of func39_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func39_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func39_in_sel:6; - /** func39_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func39_in_inv_sel:1; - /** sig39_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig39_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func39_in_sel_cfg_reg_t; - -/** Type of func40_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func40_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func40_in_sel:6; - /** func40_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func40_in_inv_sel:1; - /** sig40_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig40_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func40_in_sel_cfg_reg_t; - -/** Type of func41_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func41_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func41_in_sel:6; - /** func41_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func41_in_inv_sel:1; - /** sig41_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig41_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func41_in_sel_cfg_reg_t; - -/** Type of func42_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func42_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func42_in_sel:6; - /** func42_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func42_in_inv_sel:1; - /** sig42_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig42_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func42_in_sel_cfg_reg_t; - -/** Type of func43_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func43_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func43_in_sel:6; - /** func43_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func43_in_inv_sel:1; - /** sig43_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig43_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func43_in_sel_cfg_reg_t; - -/** Type of func44_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func44_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func44_in_sel:6; - /** func44_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func44_in_inv_sel:1; - /** sig44_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig44_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func44_in_sel_cfg_reg_t; - -/** Type of func45_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func45_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func45_in_sel:6; - /** func45_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func45_in_inv_sel:1; - /** sig45_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig45_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func45_in_sel_cfg_reg_t; - -/** Type of func47_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func47_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func47_in_sel:6; - /** func47_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func47_in_inv_sel:1; - /** sig47_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig47_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func47_in_sel_cfg_reg_t; - -/** Type of func48_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func48_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func48_in_sel:6; - /** func48_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func48_in_inv_sel:1; - /** sig48_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig48_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func48_in_sel_cfg_reg_t; - -/** Type of func49_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func49_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func49_in_sel:6; - /** func49_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func49_in_inv_sel:1; - /** sig49_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig49_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func49_in_sel_cfg_reg_t; - -/** Type of func50_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func50_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func50_in_sel:6; - /** func50_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func50_in_inv_sel:1; - /** sig50_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig50_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func50_in_sel_cfg_reg_t; - -/** Type of func51_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func51_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func51_in_sel:6; - /** func51_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func51_in_inv_sel:1; - /** sig51_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig51_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func51_in_sel_cfg_reg_t; - -/** Type of func52_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func52_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func52_in_sel:6; - /** func52_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func52_in_inv_sel:1; - /** sig52_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig52_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func52_in_sel_cfg_reg_t; - -/** Type of func53_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func53_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func53_in_sel:6; - /** func53_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func53_in_inv_sel:1; - /** sig53_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig53_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func53_in_sel_cfg_reg_t; - -/** Type of func54_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func54_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func54_in_sel:6; - /** func54_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func54_in_inv_sel:1; - /** sig54_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig54_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func54_in_sel_cfg_reg_t; - -/** Type of func55_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func55_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func55_in_sel:6; - /** func55_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func55_in_inv_sel:1; - /** sig55_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig55_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func55_in_sel_cfg_reg_t; - -/** Type of func56_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func56_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func56_in_sel:6; - /** func56_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func56_in_inv_sel:1; - /** sig56_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig56_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func56_in_sel_cfg_reg_t; - -/** Type of func57_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func57_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func57_in_sel:6; - /** func57_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func57_in_inv_sel:1; - /** sig57_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig57_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func57_in_sel_cfg_reg_t; - -/** Type of func58_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func58_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func58_in_sel:6; - /** func58_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func58_in_inv_sel:1; - /** sig58_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig58_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func58_in_sel_cfg_reg_t; - -/** Type of func59_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func59_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func59_in_sel:6; - /** func59_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func59_in_inv_sel:1; - /** sig59_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig59_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func59_in_sel_cfg_reg_t; - -/** Type of func60_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func60_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func60_in_sel:6; - /** func60_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func60_in_inv_sel:1; - /** sig60_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig60_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func60_in_sel_cfg_reg_t; - -/** Type of func61_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func61_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func61_in_sel:6; - /** func61_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func61_in_inv_sel:1; - /** sig61_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig61_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func61_in_sel_cfg_reg_t; - -/** Type of func62_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func62_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func62_in_sel:6; - /** func62_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func62_in_inv_sel:1; - /** sig62_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig62_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func62_in_sel_cfg_reg_t; - -/** Type of func63_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func63_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func63_in_sel:6; - /** func63_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func63_in_inv_sel:1; - /** sig63_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig63_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func63_in_sel_cfg_reg_t; - -/** Type of func64_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func64_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func64_in_sel:6; - /** func64_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func64_in_inv_sel:1; - /** sig64_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig64_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func64_in_sel_cfg_reg_t; - -/** Type of func65_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func65_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func65_in_sel:6; - /** func65_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func65_in_inv_sel:1; - /** sig65_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig65_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func65_in_sel_cfg_reg_t; - -/** Type of func66_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func66_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func66_in_sel:6; - /** func66_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func66_in_inv_sel:1; - /** sig66_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig66_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func66_in_sel_cfg_reg_t; - -/** Type of func68_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func68_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func68_in_sel:6; - /** func68_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func68_in_inv_sel:1; - /** sig68_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig68_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func68_in_sel_cfg_reg_t; - -/** Type of func69_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func69_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func69_in_sel:6; - /** func69_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func69_in_inv_sel:1; - /** sig69_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig69_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func69_in_sel_cfg_reg_t; - -/** Type of func70_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func70_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func70_in_sel:6; - /** func70_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func70_in_inv_sel:1; - /** sig70_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig70_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func70_in_sel_cfg_reg_t; - -/** Type of func71_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func71_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func71_in_sel:6; - /** func71_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func71_in_inv_sel:1; - /** sig71_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig71_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func71_in_sel_cfg_reg_t; - -/** Type of func74_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func74_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func74_in_sel:6; - /** func74_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func74_in_inv_sel:1; - /** sig74_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig74_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func74_in_sel_cfg_reg_t; - -/** Type of func75_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func75_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func75_in_sel:6; - /** func75_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func75_in_inv_sel:1; - /** sig75_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig75_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func75_in_sel_cfg_reg_t; - -/** Type of func76_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func76_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func76_in_sel:6; - /** func76_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func76_in_inv_sel:1; - /** sig76_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig76_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func76_in_sel_cfg_reg_t; - -/** Type of func77_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func77_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func77_in_sel:6; - /** func77_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func77_in_inv_sel:1; - /** sig77_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig77_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func77_in_sel_cfg_reg_t; - -/** Type of func78_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func78_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func78_in_sel:6; - /** func78_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func78_in_inv_sel:1; - /** sig78_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig78_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func78_in_sel_cfg_reg_t; - -/** Type of func80_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func80_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func80_in_sel:6; - /** func80_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func80_in_inv_sel:1; - /** sig80_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig80_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func80_in_sel_cfg_reg_t; - -/** Type of func83_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func83_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func83_in_sel:6; - /** func83_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func83_in_inv_sel:1; - /** sig83_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig83_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func83_in_sel_cfg_reg_t; - -/** Type of func86_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func86_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func86_in_sel:6; - /** func86_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func86_in_inv_sel:1; - /** sig86_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig86_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func86_in_sel_cfg_reg_t; - -/** Type of func89_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func89_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func89_in_sel:6; - /** func89_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func89_in_inv_sel:1; - /** sig89_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig89_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func89_in_sel_cfg_reg_t; - -/** Type of func90_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func90_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func90_in_sel:6; - /** func90_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func90_in_inv_sel:1; - /** sig90_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig90_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func90_in_sel_cfg_reg_t; - -/** Type of func91_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func91_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func91_in_sel:6; - /** func91_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func91_in_inv_sel:1; - /** sig91_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig91_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func91_in_sel_cfg_reg_t; - -/** Type of func92_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func92_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func92_in_sel:6; - /** func92_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func92_in_inv_sel:1; - /** sig92_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig92_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func92_in_sel_cfg_reg_t; - -/** Type of func93_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func93_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func93_in_sel:6; - /** func93_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func93_in_inv_sel:1; - /** sig93_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig93_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func93_in_sel_cfg_reg_t; - -/** Type of func94_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func94_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func94_in_sel:6; - /** func94_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func94_in_inv_sel:1; - /** sig94_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig94_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func94_in_sel_cfg_reg_t; - -/** Type of func95_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func95_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func95_in_sel:6; - /** func95_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func95_in_inv_sel:1; - /** sig95_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig95_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func95_in_sel_cfg_reg_t; - -/** Type of func96_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func96_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func96_in_sel:6; - /** func96_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func96_in_inv_sel:1; - /** sig96_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig96_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func96_in_sel_cfg_reg_t; - -/** Type of func97_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func97_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func97_in_sel:6; - /** func97_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func97_in_inv_sel:1; - /** sig97_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig97_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func97_in_sel_cfg_reg_t; - -/** Type of func98_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func98_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func98_in_sel:6; - /** func98_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func98_in_inv_sel:1; - /** sig98_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig98_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func98_in_sel_cfg_reg_t; - -/** Type of func99_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func99_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func99_in_sel:6; - /** func99_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func99_in_inv_sel:1; - /** sig99_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig99_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func99_in_sel_cfg_reg_t; - -/** Type of func100_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func100_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func100_in_sel:6; - /** func100_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func100_in_inv_sel:1; - /** sig100_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig100_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func100_in_sel_cfg_reg_t; - -/** Type of func101_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func101_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func101_in_sel:6; - /** func101_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func101_in_inv_sel:1; - /** sig101_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig101_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func101_in_sel_cfg_reg_t; - -/** Type of func102_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func102_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func102_in_sel:6; - /** func102_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func102_in_inv_sel:1; - /** sig102_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig102_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func102_in_sel_cfg_reg_t; - -/** Type of func103_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func103_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func103_in_sel:6; - /** func103_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func103_in_inv_sel:1; - /** sig103_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig103_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func103_in_sel_cfg_reg_t; - -/** Type of func104_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func104_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func104_in_sel:6; - /** func104_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func104_in_inv_sel:1; - /** sig104_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig104_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func104_in_sel_cfg_reg_t; - -/** Type of func105_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func105_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func105_in_sel:6; - /** func105_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func105_in_inv_sel:1; - /** sig105_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig105_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func105_in_sel_cfg_reg_t; - -/** Type of func106_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func106_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func106_in_sel:6; - /** func106_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func106_in_inv_sel:1; - /** sig106_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig106_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func106_in_sel_cfg_reg_t; - -/** Type of func107_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func107_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func107_in_sel:6; - /** func107_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func107_in_inv_sel:1; - /** sig107_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig107_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func107_in_sel_cfg_reg_t; - -/** Type of func108_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func108_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func108_in_sel:6; - /** func108_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func108_in_inv_sel:1; - /** sig108_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig108_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func108_in_sel_cfg_reg_t; - -/** Type of func109_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func109_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func109_in_sel:6; - /** func109_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func109_in_inv_sel:1; - /** sig109_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig109_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func109_in_sel_cfg_reg_t; - -/** Type of func110_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func110_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func110_in_sel:6; - /** func110_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func110_in_inv_sel:1; - /** sig110_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig110_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func110_in_sel_cfg_reg_t; - -/** Type of func111_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func111_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func111_in_sel:6; - /** func111_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func111_in_inv_sel:1; - /** sig111_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig111_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func111_in_sel_cfg_reg_t; - -/** Type of func112_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func112_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func112_in_sel:6; - /** func112_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func112_in_inv_sel:1; - /** sig112_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig112_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func112_in_sel_cfg_reg_t; - -/** Type of func113_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func113_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func113_in_sel:6; - /** func113_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func113_in_inv_sel:1; - /** sig113_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig113_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func113_in_sel_cfg_reg_t; - -/** Type of func114_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func114_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func114_in_sel:6; - /** func114_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func114_in_inv_sel:1; - /** sig114_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig114_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func114_in_sel_cfg_reg_t; - -/** Type of func117_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func117_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func117_in_sel:6; - /** func117_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func117_in_inv_sel:1; - /** sig117_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig117_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func117_in_sel_cfg_reg_t; - -/** Type of func118_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func118_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func118_in_sel:6; - /** func118_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func118_in_inv_sel:1; - /** sig118_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig118_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func118_in_sel_cfg_reg_t; - -/** Type of func126_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func126_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func126_in_sel:6; - /** func126_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func126_in_inv_sel:1; - /** sig126_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig126_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func126_in_sel_cfg_reg_t; - -/** Type of func127_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func127_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func127_in_sel:6; - /** func127_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func127_in_inv_sel:1; - /** sig127_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig127_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func127_in_sel_cfg_reg_t; - -/** Type of func128_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func128_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func128_in_sel:6; - /** func128_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func128_in_inv_sel:1; - /** sig128_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig128_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func128_in_sel_cfg_reg_t; - -/** Type of func129_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func129_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func129_in_sel:6; - /** func129_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func129_in_inv_sel:1; - /** sig129_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig129_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func129_in_sel_cfg_reg_t; - -/** Type of func130_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func130_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func130_in_sel:6; - /** func130_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func130_in_inv_sel:1; - /** sig130_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig130_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func130_in_sel_cfg_reg_t; - -/** Type of func131_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func131_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func131_in_sel:6; - /** func131_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func131_in_inv_sel:1; - /** sig131_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig131_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func131_in_sel_cfg_reg_t; - -/** Type of func132_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func132_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func132_in_sel:6; - /** func132_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func132_in_inv_sel:1; - /** sig132_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig132_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func132_in_sel_cfg_reg_t; - -/** Type of func133_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func133_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func133_in_sel:6; - /** func133_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func133_in_inv_sel:1; - /** sig133_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig133_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func133_in_sel_cfg_reg_t; - -/** Type of func134_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func134_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func134_in_sel:6; - /** func134_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func134_in_inv_sel:1; - /** sig134_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig134_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func134_in_sel_cfg_reg_t; - -/** Type of func135_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func135_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func135_in_sel:6; - /** func135_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func135_in_inv_sel:1; - /** sig135_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig135_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func135_in_sel_cfg_reg_t; - -/** Type of func136_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func136_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func136_in_sel:6; - /** func136_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func136_in_inv_sel:1; - /** sig136_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig136_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func136_in_sel_cfg_reg_t; - -/** Type of func137_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func137_in_sel : R/W; bitpos: [5:0]; default: 63; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func137_in_sel:6; - /** func137_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func137_in_inv_sel:1; - /** sig137_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig137_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func137_in_sel_cfg_reg_t; - -/** Type of func138_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func138_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func138_in_sel:6; - /** func138_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func138_in_inv_sel:1; - /** sig138_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig138_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func138_in_sel_cfg_reg_t; - -/** Type of func139_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func139_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func139_in_sel:6; - /** func139_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func139_in_inv_sel:1; - /** sig139_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig139_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func139_in_sel_cfg_reg_t; - -/** Type of func140_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func140_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func140_in_sel:6; - /** func140_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func140_in_inv_sel:1; - /** sig140_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig140_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func140_in_sel_cfg_reg_t; - -/** Type of func141_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func141_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func141_in_sel:6; - /** func141_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func141_in_inv_sel:1; - /** sig141_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig141_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func141_in_sel_cfg_reg_t; - -/** Type of func142_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func142_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func142_in_sel:6; - /** func142_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func142_in_inv_sel:1; - /** sig142_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig142_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func142_in_sel_cfg_reg_t; - -/** Type of func143_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func143_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func143_in_sel:6; - /** func143_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func143_in_inv_sel:1; - /** sig143_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig143_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func143_in_sel_cfg_reg_t; - -/** Type of func144_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func144_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func144_in_sel:6; - /** func144_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func144_in_inv_sel:1; - /** sig144_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig144_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func144_in_sel_cfg_reg_t; - -/** Type of func145_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func145_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func145_in_sel:6; - /** func145_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func145_in_inv_sel:1; - /** sig145_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig145_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func145_in_sel_cfg_reg_t; - -/** Type of func146_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func146_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func146_in_sel:6; - /** func146_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func146_in_inv_sel:1; - /** sig146_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig146_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func146_in_sel_cfg_reg_t; - -/** Type of func147_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func147_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func147_in_sel:6; - /** func147_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func147_in_inv_sel:1; - /** sig147_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig147_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func147_in_sel_cfg_reg_t; - -/** Type of func148_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func148_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func148_in_sel:6; - /** func148_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func148_in_inv_sel:1; - /** sig148_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig148_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func148_in_sel_cfg_reg_t; - -/** Type of func149_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func149_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func149_in_sel:6; - /** func149_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func149_in_inv_sel:1; - /** sig149_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig149_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func149_in_sel_cfg_reg_t; - -/** Type of func150_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func150_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func150_in_sel:6; - /** func150_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func150_in_inv_sel:1; - /** sig150_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig150_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func150_in_sel_cfg_reg_t; - -/** Type of func151_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func151_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func151_in_sel:6; - /** func151_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func151_in_inv_sel:1; - /** sig151_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig151_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func151_in_sel_cfg_reg_t; - -/** Type of func152_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func152_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func152_in_sel:6; - /** func152_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func152_in_inv_sel:1; - /** sig152_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig152_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func152_in_sel_cfg_reg_t; - -/** Type of func153_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func153_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func153_in_sel:6; - /** func153_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func153_in_inv_sel:1; - /** sig153_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig153_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func153_in_sel_cfg_reg_t; - -/** Type of func154_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func154_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func154_in_sel:6; - /** func154_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func154_in_inv_sel:1; - /** sig154_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig154_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func154_in_sel_cfg_reg_t; - -/** Type of func155_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func155_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func155_in_sel:6; - /** func155_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func155_in_inv_sel:1; - /** sig155_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig155_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func155_in_sel_cfg_reg_t; - -/** Type of func156_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func156_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func156_in_sel:6; - /** func156_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func156_in_inv_sel:1; - /** sig156_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig156_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func156_in_sel_cfg_reg_t; - -/** Type of func158_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func158_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func158_in_sel:6; - /** func158_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func158_in_inv_sel:1; - /** sig158_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig158_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func158_in_sel_cfg_reg_t; - -/** Type of func159_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func159_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func159_in_sel:6; - /** func159_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func159_in_inv_sel:1; - /** sig159_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig159_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func159_in_sel_cfg_reg_t; - -/** Type of func160_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func160_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func160_in_sel:6; - /** func160_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func160_in_inv_sel:1; - /** sig160_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig160_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func160_in_sel_cfg_reg_t; - -/** Type of func161_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func161_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func161_in_sel:6; - /** func161_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func161_in_inv_sel:1; - /** sig161_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig161_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func161_in_sel_cfg_reg_t; - -/** Type of func162_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func162_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func162_in_sel:6; - /** func162_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func162_in_inv_sel:1; - /** sig162_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig162_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func162_in_sel_cfg_reg_t; - -/** Type of func163_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func163_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func163_in_sel:6; - /** func163_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func163_in_inv_sel:1; - /** sig163_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig163_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func163_in_sel_cfg_reg_t; - -/** Type of func164_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func164_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func164_in_sel:6; - /** func164_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func164_in_inv_sel:1; - /** sig164_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig164_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func164_in_sel_cfg_reg_t; - -/** Type of func165_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func165_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func165_in_sel:6; - /** func165_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func165_in_inv_sel:1; - /** sig165_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig165_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func165_in_sel_cfg_reg_t; - -/** Type of func166_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func166_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func166_in_sel:6; - /** func166_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func166_in_inv_sel:1; - /** sig166_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig166_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func166_in_sel_cfg_reg_t; - -/** Type of func167_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func167_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func167_in_sel:6; - /** func167_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func167_in_inv_sel:1; - /** sig167_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig167_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func167_in_sel_cfg_reg_t; - -/** Type of func168_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func168_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func168_in_sel:6; - /** func168_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func168_in_inv_sel:1; - /** sig168_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig168_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func168_in_sel_cfg_reg_t; - -/** Type of func169_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func169_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func169_in_sel:6; - /** func169_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func169_in_inv_sel:1; - /** sig169_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig169_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func169_in_sel_cfg_reg_t; - -/** Type of func170_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func170_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func170_in_sel:6; - /** func170_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func170_in_inv_sel:1; - /** sig170_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig170_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func170_in_sel_cfg_reg_t; - -/** Type of func171_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func171_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func171_in_sel:6; - /** func171_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func171_in_inv_sel:1; - /** sig171_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig171_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func171_in_sel_cfg_reg_t; - -/** Type of func172_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func172_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func172_in_sel:6; - /** func172_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func172_in_inv_sel:1; - /** sig172_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig172_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func172_in_sel_cfg_reg_t; - -/** Type of func173_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func173_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func173_in_sel:6; - /** func173_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func173_in_inv_sel:1; - /** sig173_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig173_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func173_in_sel_cfg_reg_t; - -/** Type of func174_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func174_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func174_in_sel:6; - /** func174_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func174_in_inv_sel:1; - /** sig174_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig174_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func174_in_sel_cfg_reg_t; - -/** Type of func175_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func175_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func175_in_sel:6; - /** func175_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func175_in_inv_sel:1; - /** sig175_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig175_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func175_in_sel_cfg_reg_t; - -/** Type of func176_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func176_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func176_in_sel:6; - /** func176_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func176_in_inv_sel:1; - /** sig176_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig176_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func176_in_sel_cfg_reg_t; - -/** Type of func177_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func177_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func177_in_sel:6; - /** func177_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func177_in_inv_sel:1; - /** sig177_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig177_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func177_in_sel_cfg_reg_t; - -/** Type of func178_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func178_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func178_in_sel:6; - /** func178_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func178_in_inv_sel:1; - /** sig178_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig178_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func178_in_sel_cfg_reg_t; - -/** Type of func179_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func179_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func179_in_sel:6; - /** func179_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func179_in_inv_sel:1; - /** sig179_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig179_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func179_in_sel_cfg_reg_t; - -/** Type of func180_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func180_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func180_in_sel:6; - /** func180_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func180_in_inv_sel:1; - /** sig180_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig180_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func180_in_sel_cfg_reg_t; - -/** Type of func181_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func181_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func181_in_sel:6; - /** func181_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func181_in_inv_sel:1; - /** sig181_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig181_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func181_in_sel_cfg_reg_t; - -/** Type of func182_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func182_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func182_in_sel:6; - /** func182_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func182_in_inv_sel:1; - /** sig182_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig182_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func182_in_sel_cfg_reg_t; - -/** Type of func183_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func183_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func183_in_sel:6; - /** func183_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func183_in_inv_sel:1; - /** sig183_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig183_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func183_in_sel_cfg_reg_t; - -/** Type of func184_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func184_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func184_in_sel:6; - /** func184_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func184_in_inv_sel:1; - /** sig184_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig184_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func184_in_sel_cfg_reg_t; - -/** Type of func185_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func185_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func185_in_sel:6; - /** func185_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func185_in_inv_sel:1; - /** sig185_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig185_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func185_in_sel_cfg_reg_t; - -/** Type of func186_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func186_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func186_in_sel:6; - /** func186_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func186_in_inv_sel:1; - /** sig186_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig186_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func186_in_sel_cfg_reg_t; - -/** Type of func187_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func187_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func187_in_sel:6; - /** func187_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func187_in_inv_sel:1; - /** sig187_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig187_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func187_in_sel_cfg_reg_t; - -/** Type of func188_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func188_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func188_in_sel:6; - /** func188_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func188_in_inv_sel:1; - /** sig188_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig188_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func188_in_sel_cfg_reg_t; - -/** Type of func189_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func189_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func189_in_sel:6; - /** func189_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func189_in_inv_sel:1; - /** sig189_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig189_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func189_in_sel_cfg_reg_t; - -/** Type of func190_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func190_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func190_in_sel:6; - /** func190_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func190_in_inv_sel:1; - /** sig190_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig190_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func190_in_sel_cfg_reg_t; - -/** Type of func191_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func191_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func191_in_sel:6; - /** func191_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func191_in_inv_sel:1; - /** sig191_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig191_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func191_in_sel_cfg_reg_t; - -/** Type of func192_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func192_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func192_in_sel:6; - /** func192_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func192_in_inv_sel:1; - /** sig192_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig192_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func192_in_sel_cfg_reg_t; - -/** Type of func193_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func193_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func193_in_sel:6; - /** func193_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func193_in_inv_sel:1; - /** sig193_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig193_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func193_in_sel_cfg_reg_t; - -/** Type of func194_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func194_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func194_in_sel:6; - /** func194_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func194_in_inv_sel:1; - /** sig194_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig194_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func194_in_sel_cfg_reg_t; - -/** Type of func195_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func195_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func195_in_sel:6; - /** func195_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func195_in_inv_sel:1; - /** sig195_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig195_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func195_in_sel_cfg_reg_t; - -/** Type of func196_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func196_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func196_in_sel:6; - /** func196_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func196_in_inv_sel:1; - /** sig196_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig196_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func196_in_sel_cfg_reg_t; - -/** Type of func197_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func197_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func197_in_sel:6; - /** func197_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func197_in_inv_sel:1; - /** sig197_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig197_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func197_in_sel_cfg_reg_t; - -/** Type of func198_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func198_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func198_in_sel:6; - /** func198_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func198_in_inv_sel:1; - /** sig198_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig198_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func198_in_sel_cfg_reg_t; - -/** Type of func199_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func199_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func199_in_sel:6; - /** func199_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func199_in_inv_sel:1; - /** sig199_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig199_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func199_in_sel_cfg_reg_t; - -/** Type of func200_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func200_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func200_in_sel:6; - /** func200_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func200_in_inv_sel:1; - /** sig200_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig200_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func200_in_sel_cfg_reg_t; - -/** Type of func201_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func201_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func201_in_sel:6; - /** func201_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func201_in_inv_sel:1; - /** sig201_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig201_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func201_in_sel_cfg_reg_t; - -/** Type of func202_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func202_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func202_in_sel:6; - /** func202_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func202_in_inv_sel:1; - /** sig202_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig202_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func202_in_sel_cfg_reg_t; - -/** Type of func203_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func203_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func203_in_sel:6; - /** func203_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func203_in_inv_sel:1; - /** sig203_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig203_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func203_in_sel_cfg_reg_t; - -/** Type of func214_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func214_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func214_in_sel:6; - /** func214_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func214_in_inv_sel:1; - /** sig214_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig214_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func214_in_sel_cfg_reg_t; - -/** Type of func215_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func215_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func215_in_sel:6; - /** func215_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func215_in_inv_sel:1; - /** sig215_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig215_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func215_in_sel_cfg_reg_t; - -/** Type of func216_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func216_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func216_in_sel:6; - /** func216_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func216_in_inv_sel:1; - /** sig216_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig216_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func216_in_sel_cfg_reg_t; - -/** Type of func217_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func217_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func217_in_sel:6; - /** func217_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func217_in_inv_sel:1; - /** sig217_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig217_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func217_in_sel_cfg_reg_t; - -/** Type of func218_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func218_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func218_in_sel:6; - /** func218_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func218_in_inv_sel:1; - /** sig218_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig218_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func218_in_sel_cfg_reg_t; - -/** Type of func219_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func219_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func219_in_sel:6; - /** func219_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func219_in_inv_sel:1; - /** sig219_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig219_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func219_in_sel_cfg_reg_t; - -/** Type of func220_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func220_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func220_in_sel:6; - /** func220_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func220_in_inv_sel:1; - /** sig220_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig220_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func220_in_sel_cfg_reg_t; - -/** Type of func221_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func221_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func221_in_sel:6; - /** func221_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func221_in_inv_sel:1; - /** sig221_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig221_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func221_in_sel_cfg_reg_t; - -/** Type of func222_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func222_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func222_in_sel:6; - /** func222_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func222_in_inv_sel:1; - /** sig222_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig222_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func222_in_sel_cfg_reg_t; - -/** Type of func223_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func223_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func223_in_sel:6; - /** func223_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func223_in_inv_sel:1; - /** sig223_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig223_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func223_in_sel_cfg_reg_t; - -/** Type of func224_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func224_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func224_in_sel:6; - /** func224_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func224_in_inv_sel:1; - /** sig224_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig224_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func224_in_sel_cfg_reg_t; - -/** Type of func225_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func225_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func225_in_sel:6; - /** func225_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func225_in_inv_sel:1; - /** sig225_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig225_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func225_in_sel_cfg_reg_t; - -/** Type of func226_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func226_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func226_in_sel:6; - /** func226_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func226_in_inv_sel:1; - /** sig226_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig226_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func226_in_sel_cfg_reg_t; - -/** Type of func227_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func227_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func227_in_sel:6; - /** func227_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func227_in_inv_sel:1; - /** sig227_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig227_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func227_in_sel_cfg_reg_t; - -/** Type of func228_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func228_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func228_in_sel:6; - /** func228_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func228_in_inv_sel:1; - /** sig228_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig228_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func228_in_sel_cfg_reg_t; - -/** Type of func229_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func229_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func229_in_sel:6; - /** func229_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func229_in_inv_sel:1; - /** sig229_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig229_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func229_in_sel_cfg_reg_t; - -/** Type of func230_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func230_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func230_in_sel:6; - /** func230_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func230_in_inv_sel:1; - /** sig230_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig230_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func230_in_sel_cfg_reg_t; - -/** Type of func231_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func231_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func231_in_sel:6; - /** func231_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func231_in_inv_sel:1; - /** sig231_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig231_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func231_in_sel_cfg_reg_t; - -/** Type of func232_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func232_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func232_in_sel:6; - /** func232_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func232_in_inv_sel:1; - /** sig232_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig232_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func232_in_sel_cfg_reg_t; - -/** Type of func233_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func233_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func233_in_sel:6; - /** func233_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func233_in_inv_sel:1; - /** sig233_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig233_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func233_in_sel_cfg_reg_t; - -/** Type of func234_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func234_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func234_in_sel:6; - /** func234_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func234_in_inv_sel:1; - /** sig234_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig234_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func234_in_sel_cfg_reg_t; - -/** Type of func235_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func235_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func235_in_sel:6; - /** func235_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func235_in_inv_sel:1; - /** sig235_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig235_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func235_in_sel_cfg_reg_t; - -/** Type of func236_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func236_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func236_in_sel:6; - /** func236_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func236_in_inv_sel:1; - /** sig236_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig236_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func236_in_sel_cfg_reg_t; - -/** Type of func237_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func237_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func237_in_sel:6; - /** func237_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func237_in_inv_sel:1; - /** sig237_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig237_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func237_in_sel_cfg_reg_t; - -/** Type of func238_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func238_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func238_in_sel:6; - /** func238_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func238_in_inv_sel:1; - /** sig238_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig238_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func238_in_sel_cfg_reg_t; - -/** Type of func239_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func239_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func239_in_sel:6; - /** func239_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func239_in_inv_sel:1; - /** sig239_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig239_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func239_in_sel_cfg_reg_t; - -/** Type of func240_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func240_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func240_in_sel:6; - /** func240_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func240_in_inv_sel:1; - /** sig240_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig240_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func240_in_sel_cfg_reg_t; - -/** Type of func241_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func241_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func241_in_sel:6; - /** func241_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func241_in_inv_sel:1; - /** sig241_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig241_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func241_in_sel_cfg_reg_t; - -/** Type of func242_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func242_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func242_in_sel:6; - /** func242_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func242_in_inv_sel:1; - /** sig242_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig242_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func242_in_sel_cfg_reg_t; - -/** Type of func243_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func243_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func243_in_sel:6; - /** func243_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func243_in_inv_sel:1; - /** sig243_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig243_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func243_in_sel_cfg_reg_t; - -/** Type of func244_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func244_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func244_in_sel:6; - /** func244_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func244_in_inv_sel:1; - /** sig244_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig244_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func244_in_sel_cfg_reg_t; - -/** Type of func245_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func245_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func245_in_sel:6; - /** func245_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func245_in_inv_sel:1; - /** sig245_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig245_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func245_in_sel_cfg_reg_t; - -/** Type of func246_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func246_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func246_in_sel:6; - /** func246_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func246_in_inv_sel:1; - /** sig246_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig246_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func246_in_sel_cfg_reg_t; - -/** Type of func247_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func247_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func247_in_sel:6; - /** func247_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func247_in_inv_sel:1; - /** sig247_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig247_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func247_in_sel_cfg_reg_t; - -/** Type of func248_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func248_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func248_in_sel:6; - /** func248_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func248_in_inv_sel:1; - /** sig248_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig248_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func248_in_sel_cfg_reg_t; - -/** Type of func249_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func249_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func249_in_sel:6; - /** func249_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func249_in_inv_sel:1; - /** sig249_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig249_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func249_in_sel_cfg_reg_t; - -/** Type of func250_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func250_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func250_in_sel:6; - /** func250_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func250_in_inv_sel:1; - /** sig250_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig250_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func250_in_sel_cfg_reg_t; - -/** Type of func251_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func251_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func251_in_sel:6; - /** func251_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func251_in_inv_sel:1; - /** sig251_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig251_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func251_in_sel_cfg_reg_t; - -/** Type of func252_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func252_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func252_in_sel:6; - /** func252_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func252_in_inv_sel:1; - /** sig252_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig252_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func252_in_sel_cfg_reg_t; - -/** Type of func253_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func253_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func253_in_sel:6; - /** func253_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func253_in_inv_sel:1; - /** sig253_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig253_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func253_in_sel_cfg_reg_t; - -/** Type of func254_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func254_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func254_in_sel:6; - /** func254_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func254_in_inv_sel:1; - /** sig254_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig254_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func254_in_sel_cfg_reg_t; - -/** Type of func255_in_sel_cfg register - * GPIO input function configuration register - */ -typedef union { - struct { - /** func255_in_sel : R/W; bitpos: [5:0]; default: 62; - * set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always - * high level. s=0x3E: set this port always low level. - */ - uint32_t func255_in_sel:6; - /** func255_in_inv_sel : R/W; bitpos: [6]; default: 0; - * set this bit to invert input signal. 1:invert. 0:not invert. - */ - uint32_t func255_in_inv_sel:1; - /** sig255_in_sel : R/W; bitpos: [7]; default: 0; - * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. - */ - uint32_t sig255_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_func255_in_sel_cfg_reg_t; - -/** Type of funcn_out_sel_cfg register +/** Type of func_out_sel_cfg register * GPIO output function select register */ typedef union { struct { - /** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256; + /** out_sel : R/W/SC; bitpos: [8:0]; default: 256; * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: * output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals * GPIO_OUT_REG[n]. */ - uint32_t funcn_out_sel:9; - /** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; + uint32_t out_sel:9; + /** out_inv_sel : R/W/SC; bitpos: [9]; default: 0; * set this bit to invert output signal.1:invert.0:not invert. */ - uint32_t funcn_out_inv_sel:1; - /** funcn_oen_sel : R/W; bitpos: [10]; default: 0; + uint32_t out_inv_sel:1; + /** oen_sel : R/W; bitpos: [10]; default: 0; * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output * enable signal.0:use peripheral output enable signal. */ - uint32_t funcn_oen_sel:1; - /** funcn_oen_inv_sel : R/W; bitpos: [11]; default: 0; + uint32_t oen_sel:1; + /** oen_inv_sel : R/W; bitpos: [11]; default: 0; * set this bit to invert output enable signal.1:invert.0:not invert. */ - uint32_t funcn_oen_inv_sel:1; + uint32_t oen_inv_sel:1; uint32_t reserved_12:20; }; uint32_t val; -} gpio_funcn_out_sel_cfg_reg_t; +} gpio_func_out_sel_cfg_reg_t; /** Type of intr_2 register * GPIO interrupt 2 status register for GPIO0-31 @@ -5957,7 +828,7 @@ typedef union { } gpio_int_clr_reg_t; -typedef struct { +typedef struct gpio_dev_t { volatile gpio_bt_select_reg_t bt_select; volatile gpio_out_reg_t out; volatile gpio_out_w1ts_reg_t out_w1ts; @@ -5987,244 +858,9 @@ typedef struct { volatile gpio_intr1_1_reg_t intr1_1; volatile gpio_status_next_reg_t status_next; volatile gpio_status_next1_reg_t status_next1; - volatile gpio_pinn_reg_t pinn[57]; - uint32_t reserved_158; - volatile gpio_func1_in_sel_cfg_reg_t func1_in_sel_cfg; - volatile gpio_func2_in_sel_cfg_reg_t func2_in_sel_cfg; - volatile gpio_func3_in_sel_cfg_reg_t func3_in_sel_cfg; - volatile gpio_func4_in_sel_cfg_reg_t func4_in_sel_cfg; - volatile gpio_func5_in_sel_cfg_reg_t func5_in_sel_cfg; - volatile gpio_func6_in_sel_cfg_reg_t func6_in_sel_cfg; - volatile gpio_func7_in_sel_cfg_reg_t func7_in_sel_cfg; - volatile gpio_func8_in_sel_cfg_reg_t func8_in_sel_cfg; - volatile gpio_func9_in_sel_cfg_reg_t func9_in_sel_cfg; - volatile gpio_func10_in_sel_cfg_reg_t func10_in_sel_cfg; - volatile gpio_func11_in_sel_cfg_reg_t func11_in_sel_cfg; - volatile gpio_func12_in_sel_cfg_reg_t func12_in_sel_cfg; - volatile gpio_func13_in_sel_cfg_reg_t func13_in_sel_cfg; - volatile gpio_func14_in_sel_cfg_reg_t func14_in_sel_cfg; - volatile gpio_func15_in_sel_cfg_reg_t func15_in_sel_cfg; - volatile gpio_func16_in_sel_cfg_reg_t func16_in_sel_cfg; - volatile gpio_func17_in_sel_cfg_reg_t func17_in_sel_cfg; - volatile gpio_func18_in_sel_cfg_reg_t func18_in_sel_cfg; - volatile gpio_func19_in_sel_cfg_reg_t func19_in_sel_cfg; - volatile gpio_func20_in_sel_cfg_reg_t func20_in_sel_cfg; - volatile gpio_func21_in_sel_cfg_reg_t func21_in_sel_cfg; - volatile gpio_func22_in_sel_cfg_reg_t func22_in_sel_cfg; - volatile gpio_func23_in_sel_cfg_reg_t func23_in_sel_cfg; - volatile gpio_func24_in_sel_cfg_reg_t func24_in_sel_cfg; - volatile gpio_func25_in_sel_cfg_reg_t func25_in_sel_cfg; - volatile gpio_func26_in_sel_cfg_reg_t func26_in_sel_cfg; - volatile gpio_func27_in_sel_cfg_reg_t func27_in_sel_cfg; - volatile gpio_func28_in_sel_cfg_reg_t func28_in_sel_cfg; - volatile gpio_func29_in_sel_cfg_reg_t func29_in_sel_cfg; - volatile gpio_func30_in_sel_cfg_reg_t func30_in_sel_cfg; - volatile gpio_func31_in_sel_cfg_reg_t func31_in_sel_cfg; - volatile gpio_func32_in_sel_cfg_reg_t func32_in_sel_cfg; - volatile gpio_func33_in_sel_cfg_reg_t func33_in_sel_cfg; - volatile gpio_func34_in_sel_cfg_reg_t func34_in_sel_cfg; - volatile gpio_func35_in_sel_cfg_reg_t func35_in_sel_cfg; - volatile gpio_func36_in_sel_cfg_reg_t func36_in_sel_cfg; - volatile gpio_func37_in_sel_cfg_reg_t func37_in_sel_cfg; - volatile gpio_func38_in_sel_cfg_reg_t func38_in_sel_cfg; - volatile gpio_func39_in_sel_cfg_reg_t func39_in_sel_cfg; - volatile gpio_func40_in_sel_cfg_reg_t func40_in_sel_cfg; - volatile gpio_func41_in_sel_cfg_reg_t func41_in_sel_cfg; - volatile gpio_func42_in_sel_cfg_reg_t func42_in_sel_cfg; - volatile gpio_func43_in_sel_cfg_reg_t func43_in_sel_cfg; - volatile gpio_func44_in_sel_cfg_reg_t func44_in_sel_cfg; - volatile gpio_func45_in_sel_cfg_reg_t func45_in_sel_cfg; - uint32_t reserved_210; - volatile gpio_func47_in_sel_cfg_reg_t func47_in_sel_cfg; - volatile gpio_func48_in_sel_cfg_reg_t func48_in_sel_cfg; - volatile gpio_func49_in_sel_cfg_reg_t func49_in_sel_cfg; - volatile gpio_func50_in_sel_cfg_reg_t func50_in_sel_cfg; - volatile gpio_func51_in_sel_cfg_reg_t func51_in_sel_cfg; - volatile gpio_func52_in_sel_cfg_reg_t func52_in_sel_cfg; - volatile gpio_func53_in_sel_cfg_reg_t func53_in_sel_cfg; - volatile gpio_func54_in_sel_cfg_reg_t func54_in_sel_cfg; - volatile gpio_func55_in_sel_cfg_reg_t func55_in_sel_cfg; - volatile gpio_func56_in_sel_cfg_reg_t func56_in_sel_cfg; - volatile gpio_func57_in_sel_cfg_reg_t func57_in_sel_cfg; - volatile gpio_func58_in_sel_cfg_reg_t func58_in_sel_cfg; - volatile gpio_func59_in_sel_cfg_reg_t func59_in_sel_cfg; - volatile gpio_func60_in_sel_cfg_reg_t func60_in_sel_cfg; - volatile gpio_func61_in_sel_cfg_reg_t func61_in_sel_cfg; - volatile gpio_func62_in_sel_cfg_reg_t func62_in_sel_cfg; - volatile gpio_func63_in_sel_cfg_reg_t func63_in_sel_cfg; - volatile gpio_func64_in_sel_cfg_reg_t func64_in_sel_cfg; - volatile gpio_func65_in_sel_cfg_reg_t func65_in_sel_cfg; - volatile gpio_func66_in_sel_cfg_reg_t func66_in_sel_cfg; - uint32_t reserved_264; - volatile gpio_func68_in_sel_cfg_reg_t func68_in_sel_cfg; - volatile gpio_func69_in_sel_cfg_reg_t func69_in_sel_cfg; - volatile gpio_func70_in_sel_cfg_reg_t func70_in_sel_cfg; - volatile gpio_func71_in_sel_cfg_reg_t func71_in_sel_cfg; - uint32_t reserved_278[2]; - volatile gpio_func74_in_sel_cfg_reg_t func74_in_sel_cfg; - volatile gpio_func75_in_sel_cfg_reg_t func75_in_sel_cfg; - volatile gpio_func76_in_sel_cfg_reg_t func76_in_sel_cfg; - volatile gpio_func77_in_sel_cfg_reg_t func77_in_sel_cfg; - volatile gpio_func78_in_sel_cfg_reg_t func78_in_sel_cfg; - uint32_t reserved_294; - volatile gpio_func80_in_sel_cfg_reg_t func80_in_sel_cfg; - uint32_t reserved_29c[2]; - volatile gpio_func83_in_sel_cfg_reg_t func83_in_sel_cfg; - uint32_t reserved_2a8[2]; - volatile gpio_func86_in_sel_cfg_reg_t func86_in_sel_cfg; - uint32_t reserved_2b4[2]; - volatile gpio_func89_in_sel_cfg_reg_t func89_in_sel_cfg; - volatile gpio_func90_in_sel_cfg_reg_t func90_in_sel_cfg; - volatile gpio_func91_in_sel_cfg_reg_t func91_in_sel_cfg; - volatile gpio_func92_in_sel_cfg_reg_t func92_in_sel_cfg; - volatile gpio_func93_in_sel_cfg_reg_t func93_in_sel_cfg; - volatile gpio_func94_in_sel_cfg_reg_t func94_in_sel_cfg; - volatile gpio_func95_in_sel_cfg_reg_t func95_in_sel_cfg; - volatile gpio_func96_in_sel_cfg_reg_t func96_in_sel_cfg; - volatile gpio_func97_in_sel_cfg_reg_t func97_in_sel_cfg; - volatile gpio_func98_in_sel_cfg_reg_t func98_in_sel_cfg; - volatile gpio_func99_in_sel_cfg_reg_t func99_in_sel_cfg; - volatile gpio_func100_in_sel_cfg_reg_t func100_in_sel_cfg; - volatile gpio_func101_in_sel_cfg_reg_t func101_in_sel_cfg; - volatile gpio_func102_in_sel_cfg_reg_t func102_in_sel_cfg; - volatile gpio_func103_in_sel_cfg_reg_t func103_in_sel_cfg; - volatile gpio_func104_in_sel_cfg_reg_t func104_in_sel_cfg; - volatile gpio_func105_in_sel_cfg_reg_t func105_in_sel_cfg; - volatile gpio_func106_in_sel_cfg_reg_t func106_in_sel_cfg; - volatile gpio_func107_in_sel_cfg_reg_t func107_in_sel_cfg; - volatile gpio_func108_in_sel_cfg_reg_t func108_in_sel_cfg; - volatile gpio_func109_in_sel_cfg_reg_t func109_in_sel_cfg; - volatile gpio_func110_in_sel_cfg_reg_t func110_in_sel_cfg; - volatile gpio_func111_in_sel_cfg_reg_t func111_in_sel_cfg; - volatile gpio_func112_in_sel_cfg_reg_t func112_in_sel_cfg; - volatile gpio_func113_in_sel_cfg_reg_t func113_in_sel_cfg; - volatile gpio_func114_in_sel_cfg_reg_t func114_in_sel_cfg; - uint32_t reserved_324[2]; - volatile gpio_func117_in_sel_cfg_reg_t func117_in_sel_cfg; - volatile gpio_func118_in_sel_cfg_reg_t func118_in_sel_cfg; - uint32_t reserved_334[7]; - volatile gpio_func126_in_sel_cfg_reg_t func126_in_sel_cfg; - volatile gpio_func127_in_sel_cfg_reg_t func127_in_sel_cfg; - volatile gpio_func128_in_sel_cfg_reg_t func128_in_sel_cfg; - volatile gpio_func129_in_sel_cfg_reg_t func129_in_sel_cfg; - volatile gpio_func130_in_sel_cfg_reg_t func130_in_sel_cfg; - volatile gpio_func131_in_sel_cfg_reg_t func131_in_sel_cfg; - volatile gpio_func132_in_sel_cfg_reg_t func132_in_sel_cfg; - volatile gpio_func133_in_sel_cfg_reg_t func133_in_sel_cfg; - volatile gpio_func134_in_sel_cfg_reg_t func134_in_sel_cfg; - volatile gpio_func135_in_sel_cfg_reg_t func135_in_sel_cfg; - volatile gpio_func136_in_sel_cfg_reg_t func136_in_sel_cfg; - volatile gpio_func137_in_sel_cfg_reg_t func137_in_sel_cfg; - volatile gpio_func138_in_sel_cfg_reg_t func138_in_sel_cfg; - volatile gpio_func139_in_sel_cfg_reg_t func139_in_sel_cfg; - volatile gpio_func140_in_sel_cfg_reg_t func140_in_sel_cfg; - volatile gpio_func141_in_sel_cfg_reg_t func141_in_sel_cfg; - volatile gpio_func142_in_sel_cfg_reg_t func142_in_sel_cfg; - volatile gpio_func143_in_sel_cfg_reg_t func143_in_sel_cfg; - volatile gpio_func144_in_sel_cfg_reg_t func144_in_sel_cfg; - volatile gpio_func145_in_sel_cfg_reg_t func145_in_sel_cfg; - volatile gpio_func146_in_sel_cfg_reg_t func146_in_sel_cfg; - volatile gpio_func147_in_sel_cfg_reg_t func147_in_sel_cfg; - volatile gpio_func148_in_sel_cfg_reg_t func148_in_sel_cfg; - volatile gpio_func149_in_sel_cfg_reg_t func149_in_sel_cfg; - volatile gpio_func150_in_sel_cfg_reg_t func150_in_sel_cfg; - volatile gpio_func151_in_sel_cfg_reg_t func151_in_sel_cfg; - volatile gpio_func152_in_sel_cfg_reg_t func152_in_sel_cfg; - volatile gpio_func153_in_sel_cfg_reg_t func153_in_sel_cfg; - volatile gpio_func154_in_sel_cfg_reg_t func154_in_sel_cfg; - volatile gpio_func155_in_sel_cfg_reg_t func155_in_sel_cfg; - volatile gpio_func156_in_sel_cfg_reg_t func156_in_sel_cfg; - uint32_t reserved_3cc; - volatile gpio_func158_in_sel_cfg_reg_t func158_in_sel_cfg; - volatile gpio_func159_in_sel_cfg_reg_t func159_in_sel_cfg; - volatile gpio_func160_in_sel_cfg_reg_t func160_in_sel_cfg; - volatile gpio_func161_in_sel_cfg_reg_t func161_in_sel_cfg; - volatile gpio_func162_in_sel_cfg_reg_t func162_in_sel_cfg; - volatile gpio_func163_in_sel_cfg_reg_t func163_in_sel_cfg; - volatile gpio_func164_in_sel_cfg_reg_t func164_in_sel_cfg; - volatile gpio_func165_in_sel_cfg_reg_t func165_in_sel_cfg; - volatile gpio_func166_in_sel_cfg_reg_t func166_in_sel_cfg; - volatile gpio_func167_in_sel_cfg_reg_t func167_in_sel_cfg; - volatile gpio_func168_in_sel_cfg_reg_t func168_in_sel_cfg; - volatile gpio_func169_in_sel_cfg_reg_t func169_in_sel_cfg; - volatile gpio_func170_in_sel_cfg_reg_t func170_in_sel_cfg; - volatile gpio_func171_in_sel_cfg_reg_t func171_in_sel_cfg; - volatile gpio_func172_in_sel_cfg_reg_t func172_in_sel_cfg; - volatile gpio_func173_in_sel_cfg_reg_t func173_in_sel_cfg; - volatile gpio_func174_in_sel_cfg_reg_t func174_in_sel_cfg; - volatile gpio_func175_in_sel_cfg_reg_t func175_in_sel_cfg; - volatile gpio_func176_in_sel_cfg_reg_t func176_in_sel_cfg; - volatile gpio_func177_in_sel_cfg_reg_t func177_in_sel_cfg; - volatile gpio_func178_in_sel_cfg_reg_t func178_in_sel_cfg; - volatile gpio_func179_in_sel_cfg_reg_t func179_in_sel_cfg; - volatile gpio_func180_in_sel_cfg_reg_t func180_in_sel_cfg; - volatile gpio_func181_in_sel_cfg_reg_t func181_in_sel_cfg; - volatile gpio_func182_in_sel_cfg_reg_t func182_in_sel_cfg; - volatile gpio_func183_in_sel_cfg_reg_t func183_in_sel_cfg; - volatile gpio_func184_in_sel_cfg_reg_t func184_in_sel_cfg; - volatile gpio_func185_in_sel_cfg_reg_t func185_in_sel_cfg; - volatile gpio_func186_in_sel_cfg_reg_t func186_in_sel_cfg; - volatile gpio_func187_in_sel_cfg_reg_t func187_in_sel_cfg; - volatile gpio_func188_in_sel_cfg_reg_t func188_in_sel_cfg; - volatile gpio_func189_in_sel_cfg_reg_t func189_in_sel_cfg; - volatile gpio_func190_in_sel_cfg_reg_t func190_in_sel_cfg; - volatile gpio_func191_in_sel_cfg_reg_t func191_in_sel_cfg; - volatile gpio_func192_in_sel_cfg_reg_t func192_in_sel_cfg; - volatile gpio_func193_in_sel_cfg_reg_t func193_in_sel_cfg; - volatile gpio_func194_in_sel_cfg_reg_t func194_in_sel_cfg; - volatile gpio_func195_in_sel_cfg_reg_t func195_in_sel_cfg; - volatile gpio_func196_in_sel_cfg_reg_t func196_in_sel_cfg; - volatile gpio_func197_in_sel_cfg_reg_t func197_in_sel_cfg; - volatile gpio_func198_in_sel_cfg_reg_t func198_in_sel_cfg; - volatile gpio_func199_in_sel_cfg_reg_t func199_in_sel_cfg; - volatile gpio_func200_in_sel_cfg_reg_t func200_in_sel_cfg; - volatile gpio_func201_in_sel_cfg_reg_t func201_in_sel_cfg; - volatile gpio_func202_in_sel_cfg_reg_t func202_in_sel_cfg; - volatile gpio_func203_in_sel_cfg_reg_t func203_in_sel_cfg; - uint32_t reserved_488[10]; - volatile gpio_func214_in_sel_cfg_reg_t func214_in_sel_cfg; - volatile gpio_func215_in_sel_cfg_reg_t func215_in_sel_cfg; - volatile gpio_func216_in_sel_cfg_reg_t func216_in_sel_cfg; - volatile gpio_func217_in_sel_cfg_reg_t func217_in_sel_cfg; - volatile gpio_func218_in_sel_cfg_reg_t func218_in_sel_cfg; - volatile gpio_func219_in_sel_cfg_reg_t func219_in_sel_cfg; - volatile gpio_func220_in_sel_cfg_reg_t func220_in_sel_cfg; - volatile gpio_func221_in_sel_cfg_reg_t func221_in_sel_cfg; - volatile gpio_func222_in_sel_cfg_reg_t func222_in_sel_cfg; - volatile gpio_func223_in_sel_cfg_reg_t func223_in_sel_cfg; - volatile gpio_func224_in_sel_cfg_reg_t func224_in_sel_cfg; - volatile gpio_func225_in_sel_cfg_reg_t func225_in_sel_cfg; - volatile gpio_func226_in_sel_cfg_reg_t func226_in_sel_cfg; - volatile gpio_func227_in_sel_cfg_reg_t func227_in_sel_cfg; - volatile gpio_func228_in_sel_cfg_reg_t func228_in_sel_cfg; - volatile gpio_func229_in_sel_cfg_reg_t func229_in_sel_cfg; - volatile gpio_func230_in_sel_cfg_reg_t func230_in_sel_cfg; - volatile gpio_func231_in_sel_cfg_reg_t func231_in_sel_cfg; - volatile gpio_func232_in_sel_cfg_reg_t func232_in_sel_cfg; - volatile gpio_func233_in_sel_cfg_reg_t func233_in_sel_cfg; - volatile gpio_func234_in_sel_cfg_reg_t func234_in_sel_cfg; - volatile gpio_func235_in_sel_cfg_reg_t func235_in_sel_cfg; - volatile gpio_func236_in_sel_cfg_reg_t func236_in_sel_cfg; - volatile gpio_func237_in_sel_cfg_reg_t func237_in_sel_cfg; - volatile gpio_func238_in_sel_cfg_reg_t func238_in_sel_cfg; - volatile gpio_func239_in_sel_cfg_reg_t func239_in_sel_cfg; - volatile gpio_func240_in_sel_cfg_reg_t func240_in_sel_cfg; - volatile gpio_func241_in_sel_cfg_reg_t func241_in_sel_cfg; - volatile gpio_func242_in_sel_cfg_reg_t func242_in_sel_cfg; - volatile gpio_func243_in_sel_cfg_reg_t func243_in_sel_cfg; - volatile gpio_func244_in_sel_cfg_reg_t func244_in_sel_cfg; - volatile gpio_func245_in_sel_cfg_reg_t func245_in_sel_cfg; - volatile gpio_func246_in_sel_cfg_reg_t func246_in_sel_cfg; - volatile gpio_func247_in_sel_cfg_reg_t func247_in_sel_cfg; - volatile gpio_func248_in_sel_cfg_reg_t func248_in_sel_cfg; - volatile gpio_func249_in_sel_cfg_reg_t func249_in_sel_cfg; - volatile gpio_func250_in_sel_cfg_reg_t func250_in_sel_cfg; - volatile gpio_func251_in_sel_cfg_reg_t func251_in_sel_cfg; - volatile gpio_func252_in_sel_cfg_reg_t func252_in_sel_cfg; - volatile gpio_func253_in_sel_cfg_reg_t func253_in_sel_cfg; - volatile gpio_func254_in_sel_cfg_reg_t func254_in_sel_cfg; - volatile gpio_func255_in_sel_cfg_reg_t func255_in_sel_cfg; - volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[57]; + volatile gpio_pin_reg_t pin[57]; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* func0-func255: reserved for func0, 46, 67, 72, 73, 79, 81, 82, 84, 85, 87, 88, 115, 116, 119-125, 157, 204-213 */ + volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[57]; volatile gpio_intr_2_reg_t intr_2; volatile gpio_intr1_2_reg_t intr1_2; volatile gpio_intr_3_reg_t intr_3; diff --git a/components/soc/esp32p4/include/soc/hp_system_struct.h b/components/soc/esp32p4/include/soc/hp_system_struct.h index e2a34bc7ee..628ef31ef4 100644 --- a/components/soc/esp32p4/include/soc/hp_system_struct.h +++ b/components/soc/esp32p4/include/soc/hp_system_struct.h @@ -1915,7 +1915,7 @@ typedef union { } hp_system_gpio_o_hys_ctrl1_reg_t; -typedef struct { +typedef struct hp_system_dev_t { volatile hp_system_ver_date_reg_t sys_ver_date; volatile hp_system_clk_en_reg_t clk_en; uint32_t reserved_008[2]; @@ -2023,6 +2023,7 @@ typedef struct { volatile hp_system_peri_mem_clk_force_on_reg_t peri_mem_clk_force_on; } hp_system_dev_t; +extern hp_system_dev_t HP_SYSTEM; #ifndef __cplusplus _Static_assert(sizeof(hp_system_dev_t) == 0x1e4, "Invalid size of hp_system_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/io_mux_reg.h b/components/soc/esp32p4/include/soc/io_mux_reg.h index 475aa25bd1..c58352ba1d 100644 --- a/components/soc/esp32p4/include/soc/io_mux_reg.h +++ b/components/soc/esp32p4/include/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,6 +63,11 @@ #define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) #define MCU_SEL_V 0x7 #define MCU_SEL_S 12 +/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ +#define FILTER_EN (BIT(15)) +#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) +#define FILTER_EN_V 1 +#define FILTER_EN_S 15 #define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) #define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) @@ -75,14 +80,16 @@ #define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) #define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) -#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); -#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) -#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) -#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) +#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_GPIO0 #define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_GPIO1 @@ -142,13 +149,15 @@ #define IO_MUX_GPIO55_REG PERIPHS_IO_MUX_U_PAD_GPIO55 #define IO_MUX_GPIO56_REG PERIPHS_IO_MUX_U_PAD_GPIO56 -#define FUNC_GPIO_GPIO 1 #define PIN_FUNC_GPIO 1 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) +// TODO: IDF-7499, IDF-7495 +// Pins defined here are all wrong (Ln153-164). On P4, these pins are individual pins, don't use normal GPIO pins anymore. +// Please check iomux_mspi_pin_struct/reg.h #define SPI_CS1_GPIO_NUM 26 #define SPI_HD_GPIO_NUM 27 #define SPI_WP_GPIO_NUM 28 @@ -191,44 +200,37 @@ #define PSRAM_DP15_DEBUG_GPIO_NUM 46 #define PSRAM_DQS1_DEBUG_GPIO_NUM 47 -#define SD_CLK_GPIO_NUM 12 -#define SD_CMD_GPIO_NUM 11 -#define SD_DATA0_GPIO_NUM 13 -#define SD_DATA1_GPIO_NUM 14 -#define SD_DATA2_GPIO_NUM 9 -#define SD_DATA3_GPIO_NUM 10 +#define SD_CLK_GPIO_NUM 43 +#define SD_CMD_GPIO_NUM 44 +#define SD_DATA0_GPIO_NUM 39 +#define SD_DATA1_GPIO_NUM 40 +#define SD_DATA2_GPIO_NUM 41 +#define SD_DATA3_GPIO_NUM 42 +#define SD_DATA4_GPIO_NUM 45 +#define SD_DATA5_GPIO_NUM 46 +#define SD_DATA6_GPIO_NUM 47 +#define SD_DATA7_GPIO_NUM 48 -#define MAX_RTC_GPIO_NUM 15 +#define USB_INT_PHY0_DM_GPIO_NUM 24 +#define USB_INT_PHY0_DP_GPIO_NUM 25 +#define USB_INT_PHY1_DM_GPIO_NUM 26 +#define USB_INT_PHY1_DP_GPIO_NUM 27 + +// We would fix the USB PHY usage on P4: PHY0 -> USJ, PHY1 -> USB_OTG +#define USB_USJ_INT_PHY_DM_GPIO_NUM USB_INT_PHY0_DM_GPIO_NUM +#define USB_USJ_INT_PHY_DP_GPIO_NUM USB_INT_PHY0_DP_GPIO_NUM +#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM +#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM + +// #define EXT_OSC_SLOW_GPIO_NUM 1 // TODO: IDF-7526 + +#define MAX_RTC_GPIO_NUM 16 #define MAX_PAD_GPIO_NUM 56 #define MAX_GPIO_NUM 56 #define HIGH_IO_HOLD_BIT_SHIFT 32 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE -#define PIN_CTRL (REG_IO_MUX_BASE +0x00) -#define PAD_POWER_SEL BIT(15) -#define PAD_POWER_SEL_V 0x1 -#define PAD_POWER_SEL_M BIT(15) -#define PAD_POWER_SEL_S 15 - -#define PAD_POWER_SWITCH_DELAY 0x7 -#define PAD_POWER_SWITCH_DELAY_V 0x7 -#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) -#define PAD_POWER_SWITCH_DELAY_S 12 - -#define CLK_OUT3 IO_MUX_CLK_OUT3 -#define CLK_OUT3_V IO_MUX_CLK_OUT3_V -#define CLK_OUT3_S IO_MUX_CLK_OUT3_S -#define CLK_OUT3_M IO_MUX_CLK_OUT3_M -#define CLK_OUT2 IO_MUX_CLK_OUT2 -#define CLK_OUT2_V IO_MUX_CLK_OUT2_V -#define CLK_OUT2_S IO_MUX_CLK_OUT2_S -#define CLK_OUT2_M IO_MUX_CLK_OUT2_M -#define CLK_OUT1 IO_MUX_CLK_OUT1 -#define CLK_OUT1_V IO_MUX_CLK_OUT1_V -#define CLK_OUT1_S IO_MUX_CLK_OUT1_S -#define CLK_OUT1_M IO_MUX_CLK_OUT1_M -// definitions above are inherited from previous version of code, should double check // definitions below are generated from pin_txt.csv #define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x4) diff --git a/components/soc/esp32p4/include/soc/io_mux_struct.h b/components/soc/esp32p4/include/soc/io_mux_struct.h index 1b93d7c821..5ddbc746b9 100644 --- a/components/soc/esp32p4/include/soc/io_mux_struct.h +++ b/components/soc/esp32p4/include/soc/io_mux_struct.h @@ -10,45 +10,92 @@ extern "C" { #endif +/** Type of GPIO register + * IOMUX gpio configuration register + */ +typedef union { + struct { + /** mcu_oe : R/W; bitpos: [0]; default: 0; + * output enable on sleep mode + */ + uint32_t mcu_oe:1; + /** slp_sel : R/W; bitpos: [1]; default: 0; + * io sleep mode enable. set 1 to enable sleep mode. + */ + uint32_t slp_sel:1; + /** mcu_wpd : R/W; bitpos: [2]; default: 0; + * pull-down enable on sleep mode + */ + uint32_t mcu_wpd:1; + /** mcu_wpu : R/W; bitpos: [3]; default: 0; + * pull-up enable on sleep mode + */ + uint32_t mcu_wpu:1; + /** mcu_ie : R/W; bitpos: [4]; default: 0; + * input enable on sleep mode + */ + uint32_t mcu_ie:1; + /** mcu_drv : R/W; bitpos: [5:6]; default: 0; + * select drive strenth on sleep mode + */ + uint32_t mcu_drv:2; + /** fun_wpd : R/W; bitpos: [7]; default: 0; + * pull-down enable + */ + uint32_t fun_wpd:1; + /** fun_wpu : R/W; bitpos: [8]; default: 0; + * pull-up enable + */ + uint32_t fun_wpu:1; + /** fun_ie : R/W; bitpos: [9]; default: 0; + * input enable + */ + uint32_t fun_ie:1; + /** fun_drv : R/W; bitpos: [10:11]; default: 2; + * select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + */ + uint32_t fun_drv:2; + /** mcu_sel : R/W; bitpos: [12:14]; default: 0; + * 0:select function0, 1:select function1 ... + */ + uint32_t mcu_sel:3; + /** filter_en : R/W; bitpos: [15]; default: 0; + * input filter enable + */ + uint32_t filter_en:1; + uint32_t reserved16 :16; + }; + uint32_t val; +} iomux_gpio_reg_t; -typedef volatile struct iomux_dev_s { +/** Type of date register + * IOMUX version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 2101794; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} iomux_date_reg_t; + + +typedef struct iomux_dev_t { uint32_t reserved_0; - union { - struct { - uint32_t mcu_oe : 1; /*output enable on sleep mode*/ - uint32_t slp_sel : 1; /*io sleep mode enable. set 1 to enable sleep mode.*/ - uint32_t mcu_wpd : 1; /*pull-down enable on sleep mode*/ - uint32_t mcu_wpu : 1; /*pull-up enable on sleep mode*/ - uint32_t mcu_ie : 1; /*input enable on sleep mode*/ - uint32_t mcu_drv : 2; /*select drive strenth on sleep mode*/ - uint32_t fun_wpd : 1; /*pull-down enable*/ - uint32_t fun_wpu : 1; /*pull-up enable*/ - uint32_t fun_ie : 1; /*input enable*/ - uint32_t fun_drv : 2; /*select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA*/ - uint32_t mcu_sel : 3; /*0:select function0, 1:select function1 ...*/ - uint32_t filter_en : 1; /*input filter enable*/ - uint32_t reserved16 : 16; - }; - uint32_t val; - } gpio[57]; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - union { - struct { - uint32_t reg_date : 28; /*csv date*/ - uint32_t reserved28 : 4; - }; - uint32_t val; - } io_mux_date; + volatile iomux_gpio_reg_t gpio[57]; + uint32_t reserved_e8[7]; + volatile iomux_date_reg_t date; } iomux_dev_t; extern iomux_dev_t IOMUX; +#ifndef __cplusplus +_Static_assert(sizeof(iomux_dev_t) == 0x108, "Invalid size of iomux_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h index 5bfb2830d2..d9649fa9a2 100644 --- a/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h +++ b/components/soc/esp32p4/include/soc/lp_gpio_sig_map.h @@ -1,10 +1,9 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _SOC_LP_GPIO_SIG_MAP_H_ -#define _SOC_LP_GPIO_SIG_MAP_H_ +#pragma once #define LP_I2C_SCL_PAD_IN_IDX 0 #define LP_I2C_SCL_PAD_OUT_IDX 0 @@ -51,5 +50,4 @@ #define LP_PROBE_TOP_OUT14_IDX 28 #define LP_PROBE_TOP_OUT15_IDX 29 #define PROBE_CHAIN_CLK_PAD_OUT_IDX 30 -#define GPIO_MAP_DATE_IDX 0x230323 -#endif /* _SOC_LP_GPIO_SIG_MAP_H_ */ +#define LP_GPIO_MAP_DATE_IDX 0x230323 diff --git a/components/soc/esp32p4/include/soc/lp_iomux_struct.h b/components/soc/esp32p4/include/soc/lp_iomux_struct.h index c389b7e4fa..1a7e96dda4 100644 --- a/components/soc/esp32p4/include/soc/lp_iomux_struct.h +++ b/components/soc/esp32p4/include/soc/lp_iomux_struct.h @@ -950,6 +950,7 @@ typedef struct lp_iomux_dev_t { volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys; } lp_iomux_dev_t; +extern lp_iomux_dev_t LP_IOMUX; #ifndef __cplusplus _Static_assert(sizeof(lp_iomux_dev_t) == 0x54, "Invalid size of lp_iomux_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/pmu_struct.h b/components/soc/esp32p4/include/soc/pmu_struct.h index 520d8dc922..47b9cdb3cb 100644 --- a/components/soc/esp32p4/include/soc/pmu_struct.h +++ b/components/soc/esp32p4/include/soc/pmu_struct.h @@ -3733,7 +3733,7 @@ typedef union { } pmu_xtal_slp_reg_t; -typedef struct { +typedef struct pmu_dev_t { volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 4a89111c7e..d4f325386f 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -171,30 +171,36 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-P4 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U -#define SOC_GPIO_PIN_COUNT 64 +#define SOC_GPIO_PIN_COUNT 57 // #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: IDF-7481 // #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: IDF-7481 +#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 // GPIO peripheral has the ETM extension -// #define SOC_GPIO_SUPPORT_ETM 1 +// #define SOC_GPIO_SUPPORT_ETM 1 //TODO: IDF-7841 #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // Target has the full LP IO subsystem // On ESP32-P4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) -// GPIO0~7 on ESP32P4 can support chip deep sleep wakeup -// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) +// GPIO0~15 on ESP32P4 can support chip deep sleep wakeup +// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: IDF-7480 -#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFFFFF) +#define SOC_GPIO_VALID_GPIO_MASK (0x01FFFFFFFFFFFFFF) #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK -#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) +#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF) -// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30) -#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_56) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x01FFFFFFFFFF0000ULL + +// Support to force hold all IOs +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// Support to hold a single digital I/O when the digital domain is powered off +#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) /*-------------------------- RTCIO CAPS --------------------------------------*/ -// #define SOC_RTCIO_PIN_COUNT 8 //TODO: IDF-7480 +// #define SOC_RTCIO_PIN_COUNT 16 //TODO: IDF-7480 // #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 //TODO: IDF-7480 // #define SOC_RTCIO_HOLD_SUPPORTED 1 //TODO: IDF-7480 // #define SOC_RTCIO_WAKE_SUPPORTED 1 //TODO: IDF-7480 diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h index ed400ae548..11e17067a2 100644 --- a/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h @@ -996,7 +996,7 @@ typedef union { } usb_serial_jtag_date_reg_t; -typedef struct { +typedef struct usb_serial_jtag_dev_t { volatile usb_serial_jtag_ep1_reg_t ep1; volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf; volatile usb_serial_jtag_int_raw_reg_t int_raw; @@ -1034,6 +1034,7 @@ typedef struct { volatile usb_serial_jtag_date_reg_t date; } usb_serial_jtag_dev_t; +extern usb_serial_jtag_dev_t USB_SERIAL_JTAG; #ifndef __cplusplus _Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x8c, "Invalid size of usb_serial_jtag_dev_t structure"); diff --git a/components/soc/esp32p4/include/soc/usbwrap_reg.h b/components/soc/esp32p4/include/soc/usb_wrap_reg.h similarity index 100% rename from components/soc/esp32p4/include/soc/usbwrap_reg.h rename to components/soc/esp32p4/include/soc/usb_wrap_reg.h diff --git a/components/soc/esp32p4/include/soc/usbwrap_struct.h b/components/soc/esp32p4/include/soc/usb_wrap_struct.h similarity index 98% rename from components/soc/esp32p4/include/soc/usbwrap_struct.h rename to components/soc/esp32p4/include/soc/usb_wrap_struct.h index d99347df55..98ec41832b 100644 --- a/components/soc/esp32p4/include/soc/usbwrap_struct.h +++ b/components/soc/esp32p4/include/soc/usb_wrap_struct.h @@ -122,12 +122,13 @@ typedef union { } usb_wrap_date_reg_t; -typedef struct { +typedef struct usb_wrap_dev_t { volatile usb_wrap_otg_conf_reg_t otg_conf; uint32_t reserved_004[254]; volatile usb_wrap_date_reg_t date; } usb_wrap_dev_t; +extern usb_wrap_dev_t USB_WRAP; #ifndef __cplusplus _Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure"); diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index f35009c86d..4f8f7bf9f4 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -50,9 +50,12 @@ PROVIDE ( DS = 0x50094000 ); PROVIDE ( HMAC = 0x50095000 ); PROVIDE ( ECDSA = 0x50096000 ); -PROVIDE ( IOMUX = 0x500e1000 ); PROVIDE ( GPIO = 0x500E0000 ); -PROVIDE ( SIGMADELTA = 0x500E0F00 ); +PROVIDE ( GPIO_EXT = 0x500E0F00 ); +PROVIDE ( SDM = 0x500E0F00 ); +PROVIDE ( GLITCH_FILTER = 0x500E0F30 ); +PROVIDE ( GPIO_ETM = 0x500E0F60 ); +PROVIDE ( IOMUX = 0x500E1000 ); PROVIDE ( HP_SYSTEM = 0x500E5000 ); PROVIDE ( HP_SYS_CLKRST = 0x500E6000 ); @@ -92,3 +95,5 @@ PROVIDE ( I3C_SLV = 0x500DB000 ); PROVIDE ( PPA = 0x50087000 ); PROVIDE ( DMA2D = 0x50088000 ); PROVIDE ( JPEG = 0x50086000 ); + +PROVIDE ( USB_WRAP = 0x50080000 ); diff --git a/components/soc/esp32s3/include/soc/io_mux_reg.h b/components/soc/esp32s3/include/soc/io_mux_reg.h index b2dfe9eb64..3ca2cd0498 100644 --- a/components/soc/esp32s3/include/soc/io_mux_reg.h +++ b/components/soc/esp32s3/include/soc/io_mux_reg.h @@ -161,8 +161,8 @@ #define SD_DATA1_GPIO_NUM 14 #define SD_DATA2_GPIO_NUM 9 #define SD_DATA3_GPIO_NUM 10 -#define USB_DM_GPIO_NUM 19 -#define USB_DP_GPIO_NUM 20 +#define USB_INT_PHY0_DM_GPIO_NUM 19 +#define USB_INT_PHY0_DP_GPIO_NUM 20 #define XTAL32K_P_GPIO_NUM 15 #define XTAL32K_N_GPIO_NUM 16 diff --git a/docs/en/api-reference/peripherals/gpio.rst b/docs/en/api-reference/peripherals/gpio.rst index c2cb49e67f..31ccee47a3 100644 --- a/docs/en/api-reference/peripherals/gpio.rst +++ b/docs/en/api-reference/peripherals/gpio.rst @@ -56,13 +56,19 @@ GPIO Summary GPIO Hysteresis Filter ---------------------- - {IDF_TARGET_NAME} support the hardware hysteresis of the input pin, which can reduce the GPIO interrupt shoot by accident due to unstable sampling when the input voltage is near the critical of logic 0 and 1, especially when the input logic level conversion is slow or the voltage setup time is too long. + {IDF_TARGET_NAME} support the hardware hysteresis of the input pin, which can reduce the GPIO interrupt shoot by accident due to unstable sampling when the input voltage is near the criteria of logic 0 and 1, especially when the input logic level conversion is slow or the voltage setup time is too long. - Each pin can enable hysteresis function independently. By default, it controlled by eFuse and been closed, but it can also be enabled or disabled by software manually. You can select the hysteresis control mode by configuring :cpp:member:`gpio_config_t::hys_ctrl_mode`. + .. only:: SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE - .. note:: + Each pin can enable hysteresis function independently. By default, it controlled by eFuse and been closed, but it can also be enabled or disabled by software manually. You can select the hysteresis control mode by configuring :cpp:member:`gpio_config_t::hys_ctrl_mode`. Hysteresis control mode is set along with all the other GPIO configurations in :cpp:func:`gpio_config`. - When the hysteresis function is controlled by eFuse, this feature can still be controlled independently for each pin, you need to `burn the eFuse `_ to enable the hysteresis function on specific GPIO additionally. + .. note:: + + When the hysteresis function is controlled by eFuse, this feature can still be controlled independently for each pin, you need to `burn the eFuse `_ to enable the hysteresis function on specific GPIO additionally. + + .. only:: not SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE + + Each pin can enable hysteresis function independently. By default, the function is not enabled. You can select the hysteresis control mode by configuring :cpp:member:`gpio_config_t::hys_ctrl_mode`. Hysteresis control mode is set along with all the other GPIO configurations in :cpp:func:`gpio_config`. Application Example diff --git a/docs/en/api-reference/peripherals/gpio/esp32h2.inc b/docs/en/api-reference/peripherals/gpio/esp32h2.inc index 8e8a91d342..99f8d2327b 100644 --- a/docs/en/api-reference/peripherals/gpio/esp32h2.inc +++ b/docs/en/api-reference/peripherals/gpio/esp32h2.inc @@ -62,11 +62,11 @@ The table below provides more information on pin usage, and please note the comm - Strapping pin, RTC * - GPIO10 - - Analog comparator reference voltage + - ANA_CMPR_CH0 reference voltage - RTC * - GPIO11 - - Analog comparator input (non-inverting) + - ANA_CMPR_CH0 input (non-inverting) - RTC * - GPIO12 @@ -139,7 +139,6 @@ The table below provides more information on pin usage, and please note the comm - SPI0/1: GPIO15-21 are usually used for SPI flash and not recommended for other uses. - USB-Serial-JTAG: GPIO 26 and 27 are used by USB-Serial-JTAG by default. In order to use them as GPIOs, USB-Serial-JTAG will be disabled by the drivers. - For chip variants with an SiP flash built in, GPIO15 ~ GPIO21 are dedicated to connecting the SiP flash and are not fan-out to the external pins. In addition, GPIO6 ~ GPIO7 are also not fan-out to the external pins. In conclusion, only GPIO0~ GPIO5, GPIO8~ GPIO14, GPIO22~ GPIO27 are available to users. - - For chip variant without SiP flash, apart from the flash IOs mentioned above, GPIO22 is not fan-out to the external pin, thus they're not available to users. - RTC: GPIO7-14 can be used to wake up the chip from Deep-sleep mode. Other GPIOs can only wake up the chip from Light-sleep mode. For more information, please refer to Section :ref:`Wakeup Sources`. --- diff --git a/docs/en/api-reference/peripherals/gpio/esp32p4.inc b/docs/en/api-reference/peripherals/gpio/esp32p4.inc new file mode 100644 index 0000000000..027104fe3c --- /dev/null +++ b/docs/en/api-reference/peripherals/gpio/esp32p4.inc @@ -0,0 +1,315 @@ +.. This file gets included from other .rst files in this folder. +.. It contains target-specific snippets. +.. Comments and '---' lines act as delimiters. +.. +.. This is necessary mainly because RST doesn't support substitutions +.. (defined in RST, not in Python) inside code blocks. If that is ever implemented, +.. These code blocks can be moved back to the main .rst files, with target-specific +.. file names being replaced by substitutions. + +.. gpio-summary + +The {IDF_TARGET_NAME} chip features 57 physical GPIO pins (GPIO0 ~ GPIO56). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. + +The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions. + +.. list-table:: + :header-rows: 1 + :widths: 8 12 12 20 + + * - GPIO + - Analog Function + - LP GPIO + - Comments + + * - GPIO0 + - + - LP_GPIO0 + - + + * - GPIO1 + - + - LP_GPIO1 + - + + * - GPIO2 + - TOUCH0 + - LP_GPIO2 + - + + * - GPIO3 + - TOUCH1 + - LP_GPIO3 + - + + * - GPIO4 + - TOUCH2 + - LP_GPIO4 + - + + * - GPIO5 + - TOUCH3 + - LP_GPIO5 + - + + * - GPIO6 + - TOUCH4 + - LP_GPIO6 + - + + * - GPIO7 + - TOUCH5 + - LP_GPIO7 + - + + * - GPIO8 + - TOUCH6 + - LP_GPIO8 + - + + * - GPIO9 + - TOUCH7 + - LP_GPIO9 + - + + * - GPIO10 + - TOUCH8 + - LP_GPIO10 + - + + * - GPIO11 + - TOUCH9 + - LP_GPIO11 + - + + * - GPIO12 + - TOUCH10 + - LP_GPIO12 + - + + * - GPIO13 + - TOUCH11 + - LP_GPIO13 + - + + * - GPIO14 + - TOUCH12 + - LP_GPIO14 + - + + * - GPIO15 + - TOUCH13 + - LP_GPIO15 + - + + * - GPIO16 + - ADC1_CH0 + - + - + + * - GPIO17 + - ADC1_CH1 + - + - + + * - GPIO18 + - ADC1_CH2 + - + - + + * - GPIO19 + - ADC1_CH3 + - + - + + * - GPIO20 + - ADC1_CH4 + - + - + + * - GPIO21 + - ADC1_CH5 + - + - + + * - GPIO22 + - ADC1_CH6 + - + - + + * - GPIO23 + - ADC1_CH7 + - + - + + * - GPIO24 + - + - + - + + * - GPIO25 + - + - + - + + * - GPIO26 + - + - + - + + * - GPIO27 + - + - + - + + * - GPIO28 + - + - + - + + * - GPIO29 + - + - + - + + * - GPIO30 + - + - + - + + * - GPIO31 + - + - + - + + * - GPIO32 + - + - + - + + * - GPIO33 + - + - + - + + * - GPIO34 + - + - + - Strapping pin + + * - GPIO35 + - + - + - Strapping pin + + * - GPIO36 + - + - + - Strapping pin + + * - GPIO37 + - + - + - Strapping pin + + * - GPIO38 + - + - + - Strapping pin + + * - GPIO39 + - + - + - + + * - GPIO40 + - + - + - + + * - GPIO41 + - + - + - + + * - GPIO42 + - + - + - + + * - GPIO43 + - + - + - + + * - GPIO44 + - + - + - + + * - GPIO45 + - + - + - + + * - GPIO46 + - + - + - + + * - GPIO47 + - + - + - + + * - GPIO48 + - + - + - + + * - GPIO49 + - ADC1_CH8 + - + - + + * - GPIO50 + - ADC1_CH9 + - + - + + * - GPIO51 + - ADC1_CH10, ANA_CMPR_CH0 reference voltage + - + - + + * - GPIO52 + - ADC1_CH11, ANA_CMPR_CH0 input (non-inverting) + - + - + + * - GPIO53 + - ADC1_CH12, ANA_CMPR_CH1 reference voltage + - + - + + * - GPIO54 + - ADC1_CH13, ANA_CMPR_CH1 input (non-inverting) + - + - + + * - GPIO55 + - + - + - + + * - GPIO56 + - + - + - + +.. note:: + + - Strapping pin: GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 are strapping pins. For more infomation, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__. + - USB-JTAG: GPIO 24 and 25 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers. + +--- diff --git a/docs/zh_CN/api-reference/peripherals/gpio.rst b/docs/zh_CN/api-reference/peripherals/gpio.rst index cc1f66111b..65507172b1 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/gpio.rst @@ -58,11 +58,18 @@ GPIO 汇总 {IDF_TARGET_NAME} 支持输入引脚的硬件迟滞，这可以减少由于输入电压在逻辑 0、1 临界值附近时采样不稳定造成的 GPIO 中断误触，尤其是当输入逻辑电平转换较慢，电平建立时间较长时。 - 每个引脚可以独立启用迟滞功能。默认情况下，它由 eFuse 控制，且处于关闭状态，但也可以由软件控制启用或禁用。您可以通过配置 :cpp:member:`gpio_config_t::hys_ctrl_mode` 来选择迟滞控制模式。 + .. only:: SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE - .. note:: + 每个引脚可以独立启用迟滞功能。默认情况下，它由 eFuse 控制，且处于关闭状态，但也可以由软件控制启用或禁用。您可以通过配置 :cpp:member:`gpio_config_t::hys_ctrl_mode` 来选择迟滞控制模式。迟滞控制模式会和其余 GPIO 配置一起在 :cpp:func:`gpio_config` 中生效。 - 当迟滞功能由 eFuse 控制时，仍然可以独立的控制每个引脚的该功能，您需要 `烧断 eFuse `_ ，以在特定 GPIO上 启用迟滞功能。 + + .. note:: + + 当迟滞功能由 eFuse 控制时，仍然可以独立的控制每个引脚的该功能，您需要 `烧断 eFuse `_ ，以在特定 GPIO上 启用迟滞功能。 + + .. only:: not SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE + + 每个引脚可以独立启用迟滞功能。默认情况下，它处于关闭状态。您可以通过配置 :cpp:member:`gpio_config_t::hys_ctrl_mode` 来选择启用与否。迟滞控制模式会和其余 GPIO 配置一起在 :cpp:func:`gpio_config` 中生效。 应用示例 diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32h2.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32h2.inc index 62d6b7a0d3..b642377b61 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio/esp32h2.inc +++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32h2.inc @@ -64,11 +64,11 @@ - Strapping 管脚，RTC * - GPIO10 - - 模拟比较器外部参考电压 + - ANA_CMPR_CH0 外部参考电压 - RTC * - GPIO11 - - 模拟比较器同相输入 + - ANA_CMPR_CH0 同相输入 - RTC * - GPIO12 @@ -141,7 +141,6 @@ - SPI0/1: GPIO15-21 通常用于 SPI flash, 不推荐用于其他用途。 - USB-Serial-JTAG: GPIO26 和 GPIO27 默认用于 USB-Serial-JTAG。用做 GPIO 时驱动程序将禁用 USB-Serial-JTAG。 - 对于合封了 flash 的芯片型号， GPIO15 ~ GPIO21 专门用于连接该 flash, 并未引出至芯片管脚。且 GPIO6 ~ GPIO7 也未引出至芯片管脚，用户不可用。用户可配置使用其他剩余的 19 个 GPIO 管脚, 编号为: GPIO0 ~ GPIO5、GPIO8 ~ GPIO14、GPIO22 ~ GPIO27。 - - 对于未合封 flash 的芯片型号， 除了以上提到的给 Flash 专用的 GPIO 以外, GPIO22 也并未引出至芯片管脚，用户不可用。 - RTC：GPIO7-14 可用于将芯片从 Deep-sleep 模式中唤醒，其他 GPIO 仅能将芯片从 Light-sleep 模式中唤醒。更多信息请参考 :ref:`唤醒源` 章节。 --- diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc new file mode 100644 index 0000000000..6864ecf35e --- /dev/null +++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32p4.inc @@ -0,0 +1,317 @@ +.. This file gets included from other .rst files in this folder. +.. It contains target-specific snippets. +.. Comments and '---' lines act as delimiters. +.. +.. This is necessary mainly because RST doesn't support substitutions +.. (defined in RST, not in Python) inside code blocks. If that is ever implemented, +.. These code blocks can be moved back to the main .rst files, with target-specific +.. file names being replaced by substitutions. + +.. gpio-summary + +{IDF_TARGET_NAME} 芯片具有 57 个物理 GPIO 管脚（GPIO0 ~ GPIO56）。 + +每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。 + +下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。 + +.. list-table:: + :header-rows: 1 + :widths: 8 12 12 20 + + * - GPIO + - 模拟功能 + - LP GPIO + - 注释 + + * - GPIO0 + - + - LP_GPIO0 + - + + * - GPIO1 + - + - LP_GPIO1 + - + + * - GPIO2 + - TOUCH0 + - LP_GPIO2 + - + + * - GPIO3 + - TOUCH1 + - LP_GPIO3 + - + + * - GPIO4 + - TOUCH2 + - LP_GPIO4 + - + + * - GPIO5 + - TOUCH3 + - LP_GPIO5 + - + + * - GPIO6 + - TOUCH4 + - LP_GPIO6 + - + + * - GPIO7 + - TOUCH5 + - LP_GPIO7 + - + + * - GPIO8 + - TOUCH6 + - LP_GPIO8 + - + + * - GPIO9 + - TOUCH7 + - LP_GPIO9 + - + + * - GPIO10 + - TOUCH8 + - LP_GPIO10 + - + + * - GPIO11 + - TOUCH9 + - LP_GPIO11 + - + + * - GPIO12 + - TOUCH10 + - LP_GPIO12 + - + + * - GPIO13 + - TOUCH11 + - LP_GPIO13 + - + + * - GPIO14 + - TOUCH12 + - LP_GPIO14 + - + + * - GPIO15 + - TOUCH13 + - LP_GPIO15 + - + + * - GPIO16 + - ADC1_CH0 + - + - + + * - GPIO17 + - ADC1_CH1 + - + - + + * - GPIO18 + - ADC1_CH2 + - + - + + * - GPIO19 + - ADC1_CH3 + - + - + + * - GPIO20 + - ADC1_CH4 + - + - + + * - GPIO21 + - ADC1_CH5 + - + - + + * - GPIO22 + - ADC1_CH6 + - + - + + * - GPIO23 + - ADC1_CH7 + - + - + + * - GPIO24 + - + - + - + + * - GPIO25 + - + - + - + + * - GPIO26 + - + - + - + + * - GPIO27 + - + - + - + + * - GPIO28 + - + - + - + + * - GPIO29 + - + - + - + + * - GPIO30 + - + - + - + + * - GPIO31 + - + - + - + + * - GPIO32 + - + - + - + + * - GPIO33 + - + - + - + + * - GPIO34 + - + - + - Strapping 管脚 + + * - GPIO35 + - + - + - Strapping 管脚 + + * - GPIO36 + - + - + - Strapping 管脚 + + * - GPIO37 + - + - + - Strapping 管脚 + + * - GPIO38 + - + - + - Strapping 管脚 + + * - GPIO39 + - + - + - + + * - GPIO40 + - + - + - + + * - GPIO41 + - + - + - + + * - GPIO42 + - + - + - + + * - GPIO43 + - + - + - + + * - GPIO44 + - + - + - + + * - GPIO45 + - + - + - + + * - GPIO46 + - + - + - + + * - GPIO47 + - + - + - + + * - GPIO48 + - + - + - + + * - GPIO49 + - ADC1_CH8 + - + - + + * - GPIO50 + - ADC1_CH9 + - + - + + * - GPIO51 + - ADC1_CH10，ANA_CMPR_CH0 外部参考电压 + - + - + + * - GPIO52 + - ADC1_CH11，ANA_CMPR_CH0 同相输入 + - + - + + * - GPIO53 + - ADC1_CH12，ANA_CMPR_CH1 外部参考电压 + - + - + + * - GPIO54 + - ADC1_CH13，ANA_CMPR_CH1 同相输入 + - + - + + * - GPIO55 + - + - + - + + * - GPIO56 + - + - + - + +.. note:: + + - Strapping 管脚：GPIO34, GPIO35、GPIO36、GPIO37 和 GPIO38 是 Strapping 管脚。更多信息请参考 `ESP32-P4 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。 + - USB-JTAG：GPIO24 和 GPIO25 默认用于 USB-JTAG。用做 GPIO 时驱动程序将禁用 USB-JTAG。 + +---