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Merge branch 'feature/esp32s2beta_update_uart_driver' into 'feature/esp32s2beta'

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feat(uart): update uart driver for esp32s2beta

See merge request espressif/esp-idf!5257
This commit is contained in:
Angus Gratton 2019-07-30 18:05:54 +08:00
commit aea5561941
18 changed files with 752 additions and 558 deletions
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69
components/driver/include/driver/uart.h
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@ -1,9 +1,9 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -12,15 +12,14 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_UART_H_
#define _DRIVER_UART_H_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/uart_periph.h"
#include "soc/uart_caps.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "driver/periph_ctrl.h"
@ -82,7 +81,9 @@ typedef enum {
typedef enum {
UART_NUM_0 = 0x0, /*!< UART base address 0x3ff40000*/
UART_NUM_1 = 0x1, /*!< UART base address 0x3ff50000*/
#if SOC_UART_NUM > 2
UART_NUM_2 = 0x2, /*!< UART base address 0x3ff6e000*/
#endif
UART_NUM_MAX,
} uart_port_t;
@ -257,7 +258,7 @@ esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate);
*
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param inverse_mask Choose the wires that need to be inverted.
* Inverse_mask should be chosen from
* Inverse_mask should be chosen from
* UART_INVERSE_RXD / UART_INVERSE_TXD / UART_INVERSE_RTS / UART_INVERSE_CTS,
* combined with OR operation.
*
@ -401,7 +402,7 @@ esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh);
* @param fn Interrupt handler function.
* @param arg parameter for handler function
* @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
* ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
* ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
* @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will
* be returned here.
*
@ -429,7 +430,7 @@ esp_err_t uart_isr_free(uart_port_t uart_num);
* @note Internal signal can be output to multiple GPIO pads.
* Only one GPIO pad can connect with input signal.
*
* @note Instead of GPIO number a macro 'UART_PIN_NO_CHANGE' may be provided
* @note Instead of GPIO number a macro 'UART_PIN_NO_CHANGE' may be provided
to keep the currently allocated pin.
*
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
@ -556,7 +557,7 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait);
/**
* @brief Send data to the UART port from a given buffer and length.
*
*
* This function will not wait for enough space in TX FIFO. It will just fill the available TX FIFO and return when the FIFO is full.
* @note This function should only be used when UART TX buffer is not enabled.
*
@ -674,26 +675,51 @@ esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size);
*/
esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num);
#if CONFIG_IDF_TARGET_ESP32
/**
* @brief UART enable pattern detect function.
* Designed for applications like 'AT commands'.
* When the hardware detect a series of one same character, the interrupt will be triggered.
* @note This function only works for esp32. And this function is deprecated, please use
* uart_enable_pattern_det_baud_intr instead.
*
* @param uart_num UART port number.
* @param pattern_chr character of the pattern.
* @param chr_num number of the character, 8bit value.
* @param chr_tout timeout of the interval between each pattern characters, 24bit value, unit is APB (80Mhz) clock cycle.
* When the duration is less than this value, it will not take this data as at_cmd char.
* @param post_idle idle time after the last pattern character, 24bit value, unit is APB (80Mhz) clock cycle.
* When the duration is less than this value, it will not take the previous data as the last at_cmd char
* @param pre_idle idle time before the first pattern character, 24bit value, unit is APB (80Mhz) clock cycle.
* When the duration is less than this value, it will not take this data as the first at_cmd char.
*
* @return
* - ESP_OK Success
* - ESP_FAIL Parameter error
*/
esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle) __attribute__((deprecated));
#endif
/**
* @brief UART enable pattern detect function.
* Designed for applications like 'AT commands'.
* When the hardware detect a series of one same character, the interrupt will be triggered.
*
* @param uart_num UART port number.
* @param pattern_chr character of the pattern
* @param pattern_chr character of the pattern.
* @param chr_num number of the character, 8bit value.
* @param chr_tout timeout of the interval between each pattern characters, 24bit value, unit is APB (80Mhz) clock cycle.
* When the duration is less than this value, it will not take this data as at_cmd char
* @param post_idle idle time after the last pattern character, 24bit value, unit is APB (80Mhz) clock cycle.
* @param chr_tout timeout of the interval between each pattern characters, 16bit value, unit is the baud-rate cycle you configured.
* When the duration is more than this value, it will not take this data as at_cmd char.
* @param post_idle idle time after the last pattern character, 16bit value, unit is the baud-rate cycle you configured.
* When the duration is less than this value, it will not take the previous data as the last at_cmd char
* @param pre_idle idle time before the first pattern character, 24bit value, unit is APB (80Mhz) clock cycle.
* When the duration is less than this value, it will not take this data as the first at_cmd char
* @param pre_idle idle time before the first pattern character, 16bit value, unit is the baud-rate cycle you configured.
* When the duration is less than this value, it will not take this data as the first at_cmd char.
*
* @return
* - ESP_OK Success
* - ESP_FAIL Parameter error
*/
esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle);
esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle);
/**
* @brief Return the nearest detected pattern position in buffer.
@ -748,10 +774,10 @@ int uart_pattern_get_pos(uart_port_t uart_num);
esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length);
/**
* @brief UART set communication mode
* @brief UART set communication mode
* @note This function must be executed after uart_driver_install(), when the driver object is initialized.
* @param uart_num Uart number to configure
* @param mode UART UART mode to set
* @param mode UART UART mode to set
*
* @return
* - ESP_OK Success
@ -763,8 +789,8 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode);
* @brief UART set threshold timeout for TOUT feature
*
* @param uart_num Uart number to configure
* @param tout_thresh This parameter defines timeout threshold in uart symbol periods. The maximum value of threshold is 126.
* tout_thresh = 1, defines TOUT interrupt timeout equal to transmission time of one symbol (~11 bit) on current baudrate.
* @param tout_thresh This parameter defines timeout threshold in uart symbol periods. The maximum value of threshold is 126.
* tout_thresh = 1, defines TOUT interrupt timeout equal to transmission time of one symbol (~11 bit) on current baudrate.
* If the time is expired the UART_RXFIFO_TOUT_INT interrupt is triggered. If tout_thresh == 0,
* the TOUT feature is disabled.
*
@ -785,7 +811,7 @@ esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh);
* @param collision_flag Pointer to variable of type bool to return collision flag.
*
* @return
* - ESP_OK Success
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag);
@ -844,4 +870,3 @@ esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_thresh
}
#endif
#endif /*_DRIVER_UART_H_*/

555
components/driver/uart.c
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File diff suppressed because it is too large Load Diff

8
components/freemodbus/common/include/esp_modbus_common.h
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@ -22,10 +22,10 @@
#define MB_CONTROLLER_PRIORITY (CONFIG_FMB_SERIAL_TASK_PRIO - 1) // priority of MB controller task
// Default port defines
#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus
#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined
#define MB_UART_PORT (UART_NUM_2) // Default UART port number
#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info
#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus
#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined
#define MB_UART_PORT (UART_NUM_MAX - 1) // Default UART port number
#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info
#define MB_PARITY_NONE (UART_PARITY_DISABLE)
// The Macros below handle the endianness while transfer N byte data into buffer

2
components/freemodbus/port/portserial.c
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@ -78,7 +78,7 @@ static TaskHandle_t xMbTaskHandle;
static const CHAR *TAG = "MB_SERIAL";
// The UART hardware port number
static UCHAR ucUartNumber = UART_NUM_2;
static UCHAR ucUartNumber = UART_NUM_MAX - 1;
static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag
static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag

2
components/freemodbus/port/portserial_m.c
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@ -73,7 +73,7 @@ static QueueHandle_t xMbUartQueue;
static TaskHandle_t xMbTaskHandle;
// The UART hardware port number
static UCHAR ucUartNumber = UART_NUM_2;
static UCHAR ucUartNumber = UART_NUM_MAX - 1;
static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag
static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag

2
components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c
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@ -83,7 +83,7 @@ static esp_err_t mbc_serial_master_setup(void* comm_info)
MB_MASTER_CHECK(((comm_info_ptr->mode == MB_MODE_RTU) || (comm_info_ptr->mode == MB_MODE_ASCII)),
ESP_ERR_INVALID_ARG, "mb incorrect mode = (0x%x).",
(uint32_t)comm_info_ptr->mode);
MB_MASTER_CHECK((comm_info_ptr->port <= UART_NUM_2), ESP_ERR_INVALID_ARG,
MB_MASTER_CHECK((comm_info_ptr->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG,
"mb wrong port to set = (0x%x).", (uint32_t)comm_info_ptr->port);
MB_MASTER_CHECK((comm_info_ptr->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG,
"mb wrong parity option = (0x%x).", (uint32_t)comm_info_ptr->parity);

2
components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c
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@ -69,7 +69,7 @@ static esp_err_t mbc_serial_slave_setup(void* comm_info)
MB_SLAVE_CHECK((comm_settings->slave_addr <= MB_ADDRESS_MAX),
ESP_ERR_INVALID_ARG, "mb wrong slave address = (0x%x).",
(uint32_t)comm_settings->slave_addr);
MB_SLAVE_CHECK((comm_settings->port <= UART_NUM_2), ESP_ERR_INVALID_ARG,
MB_SLAVE_CHECK((comm_settings->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG,
"mb wrong port to set = (0x%x).", (uint32_t)comm_settings->port);
MB_SLAVE_CHECK((comm_settings->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG,
"mb wrong parity option = (0x%x).", (uint32_t)comm_settings->parity);

25
components/soc/esp32/include/soc/uart_caps.h Normal file
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@ -0,0 +1,25 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_NUM 3
#ifdef __cplusplus
}
#endif

25
components/soc/esp32s2beta/include/soc/uart_caps.h Normal file
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@ -0,0 +1,25 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_NUM 2
#ifdef __cplusplus
}
#endif

389
components/soc/esp32s2beta/include/soc/uart_struct.h
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@ -20,354 +20,353 @@ extern "C" {
typedef volatile struct {
union {
struct {
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
uint8_t rw_byte;
uint8_t reserved[3];
};
uint32_t val;
} ahb_fifo;
union {
struct {
uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/
uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/
uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
uint32_t reserved19: 13;
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t reserved19: 13;
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/
uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/
uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/
uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/
uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/
uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/
uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/
uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/
uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
uint32_t reserved19: 13;
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
uint32_t reserved19: 13;
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/
uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/
uint32_t div_int: 20;
uint32_t div_frag: 4;
uint32_t reserved24: 8;
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/
uint32_t en: 1;
uint32_t reserved1: 7;
uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
uint32_t glitch_filt: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} auto_baud;
union {
struct {
uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/
uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/
uint32_t reserved12: 1;
uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/
uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/
uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/
uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/
uint32_t reserved28: 1;
uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/
uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/
uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/
uint32_t rxfifo_cnt:10;
uint32_t reserved10: 3;
uint32_t dsrn: 1;
uint32_t ctsn: 1;
uint32_t rxd: 1;
uint32_t txfifo_cnt:10;
uint32_t reserved26: 3;
uint32_t dtrn: 1;
uint32_t rtsn: 1;
uint32_t txd: 1;
};
uint32_t val;
} status;
union {
struct {
uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/
uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/
uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/
uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/
uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/
uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/
uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/
uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/
uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/
uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/
uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/
uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/
uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/
uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/
uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/
uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/
uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/
uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/
uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/
uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/
uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/
uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/
uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/
uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/
uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/
uint32_t parity: 1;
uint32_t parity_en: 1;
uint32_t bit_num: 2;
uint32_t stop_bit_num: 2;
uint32_t sw_rts: 1;
uint32_t sw_dtr: 1;
uint32_t txd_brk: 1;
uint32_t irda_dplx: 1;
uint32_t irda_tx_en: 1;
uint32_t irda_wctl: 1;
uint32_t irda_tx_inv: 1;
uint32_t irda_rx_inv: 1;
uint32_t loopback: 1;
uint32_t tx_flow_en: 1;
uint32_t irda_en: 1;
uint32_t rxfifo_rst: 1;
uint32_t txfifo_rst: 1;
uint32_t rxd_inv: 1;
uint32_t cts_inv: 1;
uint32_t dsr_inv: 1;
uint32_t txd_inv: 1;
uint32_t rts_inv: 1;
uint32_t dtr_inv: 1;
uint32_t clk_en: 1;
uint32_t err_wr_mask: 1;
uint32_t tick_ref_always_on: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd: 7;
uint32_t reserved7: 1;
uint32_t txfifo_empty_thrhd: 7;
uint32_t rxfifo_full_thrhd: 9;
uint32_t txfifo_empty_thrhd: 9;
uint32_t reserved18: 11;
uint32_t rx_tout_flow_dis: 1;
uint32_t rx_flow_thrhd: 7;
uint32_t rx_flow_en: 1;
uint32_t rx_tout_thrhd: 7;
uint32_t rx_tout_en: 1;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} lowpulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
uint32_t edge_cnt: 10;
uint32_t reserved10: 22;
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/
uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/
uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/
uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/
uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/
uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/
uint32_t sw_flow_con_en: 1;
uint32_t xonoff_del: 1;
uint32_t force_xon: 1;
uint32_t force_xoff: 1;
uint32_t send_xon: 1;
uint32_t send_xoff: 1;
uint32_t reserved6: 26;
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/
uint32_t active_threshold:10;
uint32_t reserved10: 22;
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/
uint32_t xon_char: 8; /*This register stores the xon flow control char.*/
uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/
uint32_t xoff_threshold: 9;
uint32_t xoff_char: 8;
uint32_t reserved17: 15;
};
uint32_t val;
} swfc_conf;
} swfc_conf0;
union {
struct {
uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/
uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/
uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/
uint32_t xon_threshold: 9;
uint32_t xon_char: 8;
uint32_t reserved17: 15;
};
uint32_t val;
} swfc_conf1;
union {
struct {
uint32_t rx_idle_thrhd:10;
uint32_t tx_idle_num: 10;
uint32_t tx_brk_num: 8;
uint32_t reserved28: 4;
};
uint32_t val;
} idle_conf;
union {
struct {
uint32_t en: 1; /*Set this bit to choose rs485 mode.*/
uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/
uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/
uint32_t en: 1;
uint32_t dl0_en: 1;
uint32_t dl1_en: 1;
uint32_t tx_rx_en: 1;
uint32_t rx_busy_tx_en: 1;
uint32_t rx_dly_num: 1;
uint32_t tx_dly_num: 4;
uint32_t reserved10: 22;
};
uint32_t val;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
uint32_t reserved24: 8;
uint32_t pre_idle_num:16;
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/
uint32_t reserved24: 8;
uint32_t post_idle_num:16;
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
uint32_t reserved24: 8;
uint32_t rx_gap_tout:16;
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_gaptout;
union {
struct {
uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/
uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
uint32_t data: 8;
uint32_t char_num: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/
uint32_t reserved1: 1;
uint32_t reserved2: 1;
uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/
uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/
uint32_t reserved11: 4;
uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/
uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/
uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/
uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/
uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/
uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/
uint32_t reserved31: 1;
uint32_t mem_pd: 1;
uint32_t rx_size: 3;
uint32_t tx_size: 3;
uint32_t rx_flow_thrhd: 9;
uint32_t rx_tout_thrhd:10;
uint32_t reserved26: 6;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t apb_tx_waddr:11;
uint32_t tx_raddr: 11;
uint32_t reserved22: 10;
uint32_t apb_tx_waddr:10;
uint32_t reserved10: 1;
uint32_t tx_raddr: 10;
uint32_t reserved21: 11;
};
uint32_t val;
} mem_tx_status;
union {
struct {
uint32_t apb_rx_raddr:11;
uint32_t rx_waddr: 11;
uint32_t reserved22: 10;
uint32_t apb_rx_raddr:10;
uint32_t reserved10: 1;
uint32_t rx_waddr: 10;
uint32_t reserved21: 11;
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/
uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/
uint32_t reserved6: 26;
uint32_t st_urx_out: 4;
uint32_t st_utx_out: 4;
uint32_t reserved8: 24;
};
uint32_t val;
} mem_cnt_status;
} fsm_status;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} pospulse;
union {
struct {
uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
uint32_t reserved20: 12;
uint32_t min_cnt: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} negpulse;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t date; /**/
uint32_t id; /**/
uint32_t date; /**/
uint32_t id; /**/
} uart_dev_t;
extern uart_dev_t UART0;
extern uart_dev_t UART1;
extern uart_dev_t UART2;
#ifdef __cplusplus
}
#endif

2
components/soc/include/soc/uart_periph.h
View File

@ -13,6 +13,8 @@
// limitations under the License.
#pragma once
#include "soc/uart_caps.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/uart_channel.h"

12
components/vfs/test/test_vfs_access.c
View File

@ -27,11 +27,19 @@ static wl_handle_t test_wl_handle;
TEST_CASE("Can use access() for UART", "[vfs]")
{
const char *uarts[] = {"/dev/uart/0", "/dev/uart/1", "/dev/uart/2"};
const char *uarts[] = {
"/dev/uart/0",
"/dev/uart/1",
#if SOC_UART_NUM > 2
"/dev/uart/2"
#endif
};
uart_driver_install(UART_NUM_0, 256, 0, 0, NULL, 0);
uart_driver_install(UART_NUM_1, 256, 0, 0, NULL, 0);
#if SOC_UART_NUM > 2
uart_driver_install(UART_NUM_2, 256, 0, 0, NULL, 0);
#endif
for (int i = 0; i < sizeof(uarts)/sizeof(uarts[0]); ++i) {
TEST_ASSERT_EQUAL_MESSAGE(access(uarts[i], F_OK), 0, uarts[i]);
@ -55,7 +63,9 @@ TEST_CASE("Can use access() for UART", "[vfs]")
uart_driver_delete(UART_NUM_0);
uart_driver_delete(UART_NUM_1);
#if SOC_UART_NUM > 2
uart_driver_delete(UART_NUM_2);
#endif
}
static inline void test_spi_flash_setup()

195
components/vfs/vfs_uart.c
View File

@ -32,11 +32,27 @@
#endif
// TODO: make the number of UARTs chip dependent
#define UART_NUM 3
#define UART_NUM SOC_UART_NUM
// Token signifying that no character is available
#define NONE -1
#if CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CR
#else
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_LF
#endif
#if CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDIN_LINE_ENDING_CR
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CR
#else
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_LF
#endif
// UART write bytes function type
typedef void (*tx_func_t)(int, int);
// UART read bytes function type
@ -50,17 +66,54 @@ static int uart_rx_char(int fd);
static void uart_tx_char_via_driver(int fd, int c);
static int uart_rx_char_via_driver(int fd);
// Pointers to UART peripherals
static uart_dev_t* s_uarts[UART_NUM] = {&UART0, &UART1, &UART2};
// per-UART locks, lazily initialized
static _lock_t s_uart_read_locks[UART_NUM];
static _lock_t s_uart_write_locks[UART_NUM];
// One-character buffer used for newline conversion code, per UART
static int s_peek_char[UART_NUM] = { NONE, NONE, NONE };
// Per-UART non-blocking flag. Note: default implementation does not honor this
// flag, all reads are non-blocking. This option becomes effective if UART
// driver is used.
static bool s_non_blocking[UART_NUM];
typedef struct {
// Pointers to UART peripherals
uart_dev_t* uart;
// One-character buffer used for newline conversion code, per UART
int peek_char;
// per-UART locks, lazily initialized
_lock_t read_lock;
_lock_t write_lock;
// Per-UART non-blocking flag. Note: default implementation does not honor this
// flag, all reads are non-blocking. This option becomes effective if UART
// driver is used.
bool non_blocking;
// Newline conversion mode when transmitting
esp_line_endings_t tx_mode;
// Newline conversion mode when receiving
esp_line_endings_t rx_mode;
// Functions used to write bytes to UART. Default to "basic" functions.
tx_func_t tx_func;
// Functions used to read bytes from UART. Default to "basic" functions.
rx_func_t rx_func;
} vfs_uart_context_t;
#define VFS_CTX_DEFAULT_VAL(uart_dev) (vfs_uart_context_t) {\
.uart = (uart_dev),\
.peek_char = NONE,\
.tx_mode = DEFAULT_TX_MODE,\
.rx_mode = DEFAULT_RX_MODE,\
.tx_func = uart_tx_char,\
.rx_func = uart_rx_char,\
}
//If the context should be dynamically initialized, remove this structure
//and point s_ctx to allocated data.
static vfs_uart_context_t s_context[UART_NUM] = {
VFS_CTX_DEFAULT_VAL(&UART0),
VFS_CTX_DEFAULT_VAL(&UART1),
#if UART_NUM > 2
VFS_CTX_DEFAULT_VAL(&UART2),
#endif
};
static vfs_uart_context_t* s_ctx[UART_NUM] = {
&s_context[0],
&s_context[1],
#if UART_NUM > 2
&s_context[2],
#endif
};
/* Lock ensuring that uart_select is used from only one task at the time */
static _lock_t s_one_select_lock;
@ -73,39 +126,9 @@ static fd_set *_readfds_orig = NULL;
static fd_set *_writefds_orig = NULL;
static fd_set *_errorfds_orig = NULL;
// Newline conversion mode when transmitting
static esp_line_endings_t s_tx_mode =
#if CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF
ESP_LINE_ENDINGS_CRLF;
#elif CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR
ESP_LINE_ENDINGS_CR;
#else
ESP_LINE_ENDINGS_LF;
#endif
// Newline conversion mode when receiving
static esp_line_endings_t s_rx_mode[UART_NUM] = { [0 ... UART_NUM-1] =
#if CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF
ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDIN_LINE_ENDING_CR
ESP_LINE_ENDINGS_CR
#else
ESP_LINE_ENDINGS_LF
#endif
};
static void uart_end_select();
// Functions used to write bytes to UART. Default to "basic" functions.
static tx_func_t s_uart_tx_func[UART_NUM] = {
&uart_tx_char, &uart_tx_char, &uart_tx_char
};
// Functions used to read bytes from UART. Default to "basic" functions.
static rx_func_t s_uart_rx_func[UART_NUM] = {
&uart_rx_char, &uart_rx_char, &uart_rx_char
};
static int uart_open(const char * path, int flags, int mode)
{
@ -124,14 +147,14 @@ static int uart_open(const char * path, int flags, int mode)
return fd;
}
s_non_blocking[fd] = ((flags & O_NONBLOCK) == O_NONBLOCK);
s_ctx[fd]->non_blocking = ((flags & O_NONBLOCK) == O_NONBLOCK);
return fd;
}
static void uart_tx_char(int fd, int c)
{
uart_dev_t* uart = s_uarts[fd];
uart_dev_t* uart = s_ctx[fd]->uart;
while (uart->status.txfifo_cnt >= 127) {
;
}
@ -150,7 +173,7 @@ static void uart_tx_char_via_driver(int fd, int c)
static int uart_rx_char(int fd)
{
uart_dev_t* uart = s_uarts[fd];
uart_dev_t* uart = s_ctx[fd]->uart;
if (uart->status.rxfifo_cnt == 0) {
return NONE;
}
@ -164,7 +187,7 @@ static int uart_rx_char(int fd)
static int uart_rx_char_via_driver(int fd)
{
uint8_t c;
int timeout = s_non_blocking[fd] ? 0 : portMAX_DELAY;
int timeout = s_ctx[fd]->non_blocking ? 0 : portMAX_DELAY;
int n = uart_read_bytes(fd, &c, 1, timeout);
if (n <= 0) {
return NONE;
@ -180,18 +203,18 @@ static ssize_t uart_write(int fd, const void * data, size_t size)
* a dedicated UART lock if two streams (stdout and stderr) point to the
* same UART.
*/
_lock_acquire_recursive(&s_uart_write_locks[fd]);
_lock_acquire_recursive(&s_ctx[fd]->write_lock);
for (size_t i = 0; i < size; i++) {
int c = data_c[i];
if (c == '\n' && s_tx_mode != ESP_LINE_ENDINGS_LF) {
s_uart_tx_func[fd](fd, '\r');
if (s_tx_mode == ESP_LINE_ENDINGS_CR) {
if (c == '\n' && s_ctx[fd]->tx_mode != ESP_LINE_ENDINGS_LF) {
s_ctx[fd]->tx_func(fd, '\r');
if (s_ctx[fd]->tx_mode == ESP_LINE_ENDINGS_CR) {
continue;
}
}
s_uart_tx_func[fd](fd, c);
s_ctx[fd]->tx_func(fd, c);
}
_lock_release_recursive(&s_uart_write_locks[fd]);
_lock_release_recursive(&s_ctx[fd]->write_lock);
return size;
}
@ -202,19 +225,19 @@ static ssize_t uart_write(int fd, const void * data, size_t size)
static int uart_read_char(int fd)
{
/* return character from peek buffer, if it is there */
if (s_peek_char[fd] != NONE) {
int c = s_peek_char[fd];
s_peek_char[fd] = NONE;
if (s_ctx[fd]->peek_char != NONE) {
int c = s_ctx[fd]->peek_char;
s_ctx[fd]->peek_char = NONE;
return c;
}
return s_uart_rx_func[fd](fd);
return s_ctx[fd]->rx_func(fd);
}
/* Push back a character; it will be returned by next call to uart_read_char */
static void uart_return_char(int fd, int c)
{
assert(s_peek_char[fd] == NONE);
s_peek_char[fd] = c;
assert(s_ctx[fd]->peek_char == NONE);
s_ctx[fd]->peek_char = c;
}
static ssize_t uart_read(int fd, void* data, size_t size)
@ -222,13 +245,13 @@ static ssize_t uart_read(int fd, void* data, size_t size)
assert(fd >=0 && fd < 3);
char *data_c = (char *) data;
size_t received = 0;
_lock_acquire_recursive(&s_uart_read_locks[fd]);
_lock_acquire_recursive(&s_ctx[fd]->read_lock);
while (received < size) {
int c = uart_read_char(fd);
if (c == '\r') {
if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CR) {
if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) {
c = '\n';
} else if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CRLF) {
} else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) {
/* look ahead */
int c2 = uart_read_char(fd);
if (c2 == NONE) {
@ -255,7 +278,7 @@ static ssize_t uart_read(int fd, void* data, size_t size)
break;
}
}
_lock_release_recursive(&s_uart_read_locks[fd]);
_lock_release_recursive(&s_ctx[fd]->read_lock);
if (received > 0) {
return received;
}
@ -281,11 +304,11 @@ static int uart_fcntl(int fd, int cmd, int arg)
assert(fd >=0 && fd < 3);
int result = 0;
if (cmd == F_GETFL) {
if (s_non_blocking[fd]) {
if (s_ctx[fd]->non_blocking) {
result |= O_NONBLOCK;
}
} else if (cmd == F_SETFL) {
s_non_blocking[fd] = (arg & O_NONBLOCK) != 0;
s_ctx[fd]->non_blocking = (arg & O_NONBLOCK) != 0;
} else {
// unsupported operation
result = -1;
@ -318,9 +341,9 @@ static int uart_access(const char *path, int amode)
static int uart_fsync(int fd)
{
assert(fd >= 0 && fd < 3);
_lock_acquire_recursive(&s_uart_write_locks[fd]);
_lock_acquire_recursive(&s_ctx[fd]->write_lock);
uart_tx_wait_idle((uint8_t) fd);
_lock_release_recursive(&s_uart_write_locks[fd]);
_lock_release_recursive(&s_ctx[fd]->write_lock);
return 0;
}
@ -489,11 +512,11 @@ static int uart_tcsetattr(int fd, int optional_actions, const struct termios *p)
}
if (p->c_iflag & IGNCR) {
s_rx_mode[fd] = ESP_LINE_ENDINGS_CRLF;
s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_CRLF;
} else if (p->c_iflag & ICRNL) {
s_rx_mode[fd] = ESP_LINE_ENDINGS_CR;
s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_CR;
} else {
s_rx_mode[fd] = ESP_LINE_ENDINGS_LF;
s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_LF;
}
// output line endings are not supported because there is no alternative in termios for converting LF to CR
@ -672,9 +695,9 @@ static int uart_tcgetattr(int fd, struct termios *p)
memset(p, 0, sizeof(struct termios));
if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CRLF) {
if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) {
p->c_iflag |= IGNCR;
} else if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CR) {
} else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) {
p->c_iflag |= ICRNL;
}
@ -931,31 +954,33 @@ void esp_vfs_dev_uart_register()
void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode)
{
for (int i = 0; i < UART_NUM; ++i) {
s_rx_mode[i] = mode;
s_ctx[i]->rx_mode = mode;
}
}
void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode)
{
s_tx_mode = mode;
for (int i = 0; i < UART_NUM; ++i) {
s_ctx[i]->tx_mode = mode;
}
}
void esp_vfs_dev_uart_use_nonblocking(int uart_num)
{
_lock_acquire_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_uart_write_locks[uart_num]);
s_uart_tx_func[uart_num] = uart_tx_char;
s_uart_rx_func[uart_num] = uart_rx_char;
_lock_release_recursive(&s_uart_write_locks[uart_num]);
_lock_release_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_ctx[uart_num]->read_lock);
_lock_acquire_recursive(&s_ctx[uart_num]->write_lock);
s_ctx[uart_num]->tx_func = uart_tx_char;
s_ctx[uart_num]->rx_func = uart_rx_char;
_lock_release_recursive(&s_ctx[uart_num]->write_lock);
_lock_release_recursive(&s_ctx[uart_num]->read_lock);
}
void esp_vfs_dev_uart_use_driver(int uart_num)
{
_lock_acquire_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_uart_write_locks[uart_num]);
s_uart_tx_func[uart_num] = uart_tx_char_via_driver;
s_uart_rx_func[uart_num] = uart_rx_char_via_driver;
_lock_release_recursive(&s_uart_write_locks[uart_num]);
_lock_release_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_ctx[uart_num]->read_lock);
_lock_acquire_recursive(&s_ctx[uart_num]->write_lock);
s_ctx[uart_num]->tx_func = uart_tx_char_via_driver;
s_ctx[uart_num]->rx_func = uart_rx_char_via_driver;
_lock_release_recursive(&s_ctx[uart_num]->write_lock);
_lock_release_recursive(&s_ctx[uart_num]->read_lock);
}

2
docs/en/api-reference/peripherals/uart.rst
View File

@ -169,7 +169,7 @@ The API provides a convenient way to handle specific interrupts discussed above
* **FIFO space threshold or transmission timeout reached** - the interrupts on TX or Rx FIFO buffer being filled with specific number of characters or on a timeout of sending or receiving data. To use these interrupts, first configure respective threshold values of the buffer length and the timeout by entering them in :cpp:type:`uart_intr_config_t` structure and calling :cpp:func:`uart_intr_config`. Then enable interrupts with functions :cpp:func:`uart_enable_rx_intr` and :cpp:func:`uart_enable_tx_intr`. To disable these interrupts there are corresponding functions :cpp:func:`uart_disable_rx_intr` or :cpp:func:`uart_disable_tx_intr`.
* **Pattern detection** - an interrupt triggered on detecting a 'pattern' of the same character being sent number of times. The functions that allow to configure, enable and disable this interrupt are :cpp:func:`uart_enable_pattern_det_intr` and cpp:func:`uart_disable_pattern_det_intr`.
* **Pattern detection** - an interrupt triggered on detecting a 'pattern' of the same character being sent number of times. The functions that allow to configure, enable and disable this interrupt are :cpp:func:`uart_enable_pattern_det_baud_intr` and cpp:func:`uart_disable_pattern_det_intr`.
Macros
^^^^^^

2
examples/peripherals/uart/nmea0183_parser/main/nmea_parser.c
View File

@ -699,7 +699,7 @@ nmea_parser_handle_t nmea_parser_init(const nmea_parser_config_t *config)
goto err_uart_install;
}
/* Set pattern interrupt, used to detect the end of a line */
uart_enable_pattern_det_intr(esp_gps->uart_port, '\n', 1, 10000, 10, 10);
uart_enable_pattern_det_baud_intr(esp_gps->uart_port, '\n', 1, 9, 0, 0);
/* Set pattern queue size */
uart_pattern_queue_reset(esp_gps->uart_port, config->uart.event_queue_size);
uart_flush(esp_gps->uart_port);

2
examples/peripherals/uart/uart_echo_rs485/main/rs485_example.c
View File

@ -47,7 +47,7 @@
#define PACKET_READ_TICS (100 / portTICK_RATE_MS)
#define ECHO_TASK_STACK_SIZE (2048)
#define ECHO_TASK_PRIO (10)
#define ECHO_UART_PORT (UART_NUM_2)
#define ECHO_UART_PORT (UART_NUM_MAX - 1)
static const char *TAG = "RS485_ECHO_APP";

2
examples/peripherals/uart/uart_events/main/uart_events_example_main.c
View File

@ -140,7 +140,7 @@ void app_main()
uart_driver_install(EX_UART_NUM, BUF_SIZE * 2, BUF_SIZE * 2, 20, &uart0_queue, 0);
//Set uart pattern detect function.
uart_enable_pattern_det_intr(EX_UART_NUM, '+', PATTERN_CHR_NUM, 10000, 10, 10);
uart_enable_pattern_det_baud_intr(EX_UART_NUM, '+', PATTERN_CHR_NUM, 9, 0, 0);
//Reset the pattern queue length to record at most 20 pattern positions.
uart_pattern_queue_reset(EX_UART_NUM, 20);

14
examples/protocols/pppos_client/components/modem/src/esp_modem.c
View File

@ -28,9 +28,9 @@
#define ESP_MODEM_LINE_BUFFER_SIZE (CONFIG_EXAMPLE_UART_RX_BUFFER_SIZE / 2)
#define ESP_MODEM_EVENT_QUEUE_SIZE (16)
#define MIN_PATTERN_INTERVAL (10000)
#define MIN_POST_IDLE (10)
#define MIN_PRE_IDLE (10)
#define MIN_PATTERN_INTERVAL (9)
#define MIN_POST_IDLE (0)
#define MIN_PRE_IDLE (0)
/**
* @brief Macro defined for error checking
@ -264,12 +264,12 @@ static esp_err_t esp_modem_dte_send_wait(modem_dte_t *dte, const char *data, uin
MODEM_CHECK(res >= len, "wait prompt [%s] timeout", err, prompt);
MODEM_CHECK(!strncmp(prompt, (const char *)buffer, len), "get wrong prompt: %s", err, buffer);
free(buffer);
uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
return ESP_OK;
err:
free(buffer);
err_write:
uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
err_param:
return ESP_FAIL;
}
@ -298,7 +298,7 @@ static esp_err_t esp_modem_dte_change_mode(modem_dte_t *dte, modem_mode_t new_mo
case MODEM_COMMAND_MODE:
uart_disable_rx_intr(esp_dte->uart_port);
uart_flush(esp_dte->uart_port);
uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
uart_pattern_queue_reset(esp_dte->uart_port, CONFIG_EXAMPLE_UART_PATTERN_QUEUE_SIZE);
MODEM_CHECK(dce->set_working_mode(dce, new_mode) == ESP_OK, "set new working mode:%d failed", err, new_mode);
break;
@ -392,7 +392,7 @@ modem_dte_t *esp_modem_dte_init(const esp_modem_dte_config_t *config)
CONFIG_EXAMPLE_UART_EVENT_QUEUE_SIZE, &(esp_dte->event_queue), 0);
MODEM_CHECK(res == ESP_OK, "install uart driver failed", err_uart_config);
/* Set pattern interrupt, used to detect the end of a line. */
res = uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
res = uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE);
/* Set pattern queue size */
res |= uart_pattern_queue_reset(esp_dte->uart_port, CONFIG_EXAMPLE_UART_PATTERN_QUEUE_SIZE);
MODEM_CHECK(res == ESP_OK, "config uart pattern failed", err_uart_pattern);