diff --git a/components/driver/include/driver/uart.h b/components/driver/include/driver/uart.h index 4f0c8c1ca1..ac43dda8b8 100644 --- a/components/driver/include/driver/uart.h +++ b/components/driver/include/driver/uart.h @@ -1,9 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -12,15 +12,14 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _DRIVER_UART_H_ -#define _DRIVER_UART_H_ - +#pragma once #ifdef __cplusplus extern "C" { #endif #include "soc/uart_periph.h" +#include "soc/uart_caps.h" #include "esp_err.h" #include "esp_intr_alloc.h" #include "driver/periph_ctrl.h" @@ -82,7 +81,9 @@ typedef enum { typedef enum { UART_NUM_0 = 0x0, /*!< UART base address 0x3ff40000*/ UART_NUM_1 = 0x1, /*!< UART base address 0x3ff50000*/ +#if SOC_UART_NUM > 2 UART_NUM_2 = 0x2, /*!< UART base address 0x3ff6e000*/ +#endif UART_NUM_MAX, } uart_port_t; @@ -257,7 +258,7 @@ esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate); * * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2 * @param inverse_mask Choose the wires that need to be inverted. - * Inverse_mask should be chosen from + * Inverse_mask should be chosen from * UART_INVERSE_RXD / UART_INVERSE_TXD / UART_INVERSE_RTS / UART_INVERSE_CTS, * combined with OR operation. * @@ -401,7 +402,7 @@ esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh); * @param fn Interrupt handler function. * @param arg parameter for handler function * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred) - * ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. + * ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. * @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will * be returned here. * @@ -429,7 +430,7 @@ esp_err_t uart_isr_free(uart_port_t uart_num); * @note Internal signal can be output to multiple GPIO pads. * Only one GPIO pad can connect with input signal. * - * @note Instead of GPIO number a macro 'UART_PIN_NO_CHANGE' may be provided + * @note Instead of GPIO number a macro 'UART_PIN_NO_CHANGE' may be provided to keep the currently allocated pin. * * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2 @@ -556,7 +557,7 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait); /** * @brief Send data to the UART port from a given buffer and length. - * + * * This function will not wait for enough space in TX FIFO. It will just fill the available TX FIFO and return when the FIFO is full. * @note This function should only be used when UART TX buffer is not enabled. * @@ -674,26 +675,51 @@ esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size); */ esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num); +#if CONFIG_IDF_TARGET_ESP32 +/** + * @brief UART enable pattern detect function. + * Designed for applications like 'AT commands'. + * When the hardware detect a series of one same character, the interrupt will be triggered. + * @note This function only works for esp32. And this function is deprecated, please use + * uart_enable_pattern_det_baud_intr instead. + * + * @param uart_num UART port number. + * @param pattern_chr character of the pattern. + * @param chr_num number of the character, 8bit value. + * @param chr_tout timeout of the interval between each pattern characters, 24bit value, unit is APB (80Mhz) clock cycle. + * When the duration is less than this value, it will not take this data as at_cmd char. + * @param post_idle idle time after the last pattern character, 24bit value, unit is APB (80Mhz) clock cycle. + * When the duration is less than this value, it will not take the previous data as the last at_cmd char + * @param pre_idle idle time before the first pattern character, 24bit value, unit is APB (80Mhz) clock cycle. + * When the duration is less than this value, it will not take this data as the first at_cmd char. + * + * @return + * - ESP_OK Success + * - ESP_FAIL Parameter error + */ +esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle) __attribute__((deprecated)); +#endif + /** * @brief UART enable pattern detect function. * Designed for applications like 'AT commands'. * When the hardware detect a series of one same character, the interrupt will be triggered. * * @param uart_num UART port number. - * @param pattern_chr character of the pattern + * @param pattern_chr character of the pattern. * @param chr_num number of the character, 8bit value. - * @param chr_tout timeout of the interval between each pattern characters, 24bit value, unit is APB (80Mhz) clock cycle. - * When the duration is less than this value, it will not take this data as at_cmd char - * @param post_idle idle time after the last pattern character, 24bit value, unit is APB (80Mhz) clock cycle. + * @param chr_tout timeout of the interval between each pattern characters, 16bit value, unit is the baud-rate cycle you configured. + * When the duration is more than this value, it will not take this data as at_cmd char. + * @param post_idle idle time after the last pattern character, 16bit value, unit is the baud-rate cycle you configured. * When the duration is less than this value, it will not take the previous data as the last at_cmd char - * @param pre_idle idle time before the first pattern character, 24bit value, unit is APB (80Mhz) clock cycle. - * When the duration is less than this value, it will not take this data as the first at_cmd char + * @param pre_idle idle time before the first pattern character, 16bit value, unit is the baud-rate cycle you configured. + * When the duration is less than this value, it will not take this data as the first at_cmd char. * * @return * - ESP_OK Success * - ESP_FAIL Parameter error */ -esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle); +esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle); /** * @brief Return the nearest detected pattern position in buffer. @@ -748,10 +774,10 @@ int uart_pattern_get_pos(uart_port_t uart_num); esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length); /** - * @brief UART set communication mode + * @brief UART set communication mode * @note This function must be executed after uart_driver_install(), when the driver object is initialized. * @param uart_num Uart number to configure - * @param mode UART UART mode to set + * @param mode UART UART mode to set * * @return * - ESP_OK Success @@ -763,8 +789,8 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode); * @brief UART set threshold timeout for TOUT feature * * @param uart_num Uart number to configure - * @param tout_thresh This parameter defines timeout threshold in uart symbol periods. The maximum value of threshold is 126. - * tout_thresh = 1, defines TOUT interrupt timeout equal to transmission time of one symbol (~11 bit) on current baudrate. + * @param tout_thresh This parameter defines timeout threshold in uart symbol periods. The maximum value of threshold is 126. + * tout_thresh = 1, defines TOUT interrupt timeout equal to transmission time of one symbol (~11 bit) on current baudrate. * If the time is expired the UART_RXFIFO_TOUT_INT interrupt is triggered. If tout_thresh == 0, * the TOUT feature is disabled. * @@ -785,7 +811,7 @@ esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh); * @param collision_flag Pointer to variable of type bool to return collision flag. * * @return - * - ESP_OK Success + * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error */ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag); @@ -844,4 +870,3 @@ esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_thresh } #endif -#endif /*_DRIVER_UART_H_*/ diff --git a/components/driver/uart.c b/components/driver/uart.c index 37925e54df..ed6bfb660c 100644 --- a/components/driver/uart.c +++ b/components/driver/uart.c @@ -34,10 +34,12 @@ #include "esp32s2beta/clk.h" #endif +#define UART_NUM SOC_UART_NUM + #define XOFF (char)0x13 #define XON (char)0x11 -static const char* UART_TAG = "uart"; +static const char *UART_TAG = "uart"; #define UART_CHECK(a, str, ret_val) \ if (!(a)) { \ ESP_LOGE(UART_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \ @@ -74,7 +76,7 @@ typedef struct { int wr; int rd; int len; - int* data; + int *data; } uart_pat_rb_t; typedef struct { @@ -92,8 +94,8 @@ typedef struct { RingbufHandle_t rx_ring_buf; /*!< RX ring buffer handler*/ bool rx_buffer_full_flg; /*!< RX ring buffer full flag. */ int rx_cur_remain; /*!< Data number that waiting to be read out in ring buffer item*/ - uint8_t* rx_ptr; /*!< pointer to the current data in ring buffer*/ - uint8_t* rx_head_ptr; /*!< pointer to the head of RX item*/ + uint8_t *rx_ptr; /*!< pointer to the current data in ring buffer*/ + uint8_t *rx_head_ptr; /*!< pointer to the head of RX item*/ uint8_t rx_data_buf[UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/ uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */ uart_pat_rb_t rx_pattern_pos; @@ -106,8 +108,8 @@ typedef struct { int tx_buf_size; /*!< TX ring buffer size */ RingbufHandle_t tx_ring_buf; /*!< TX ring buffer handler*/ bool tx_waiting_fifo; /*!< this flag indicates that some task is waiting for FIFO empty interrupt, used to send all data without any data buffer*/ - uint8_t* tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/ - uart_tx_data_t* tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/ + uint8_t *tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/ + uart_tx_data_t *tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/ uint32_t tx_len_tot; /*!< Total length of current item in ring buffer*/ uint32_t tx_len_cur; uint8_t tx_brk_flg; /*!< Flag to indicate to send a break signal in the end of the item sending procedure */ @@ -118,8 +120,20 @@ typedef struct { static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0}; /* DRAM_ATTR is required to avoid UART array placed in flash, due to accessed from ISR */ -static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = {&UART0, &UART1, &UART2}; -static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED}; +static DRAM_ATTR uart_dev_t *const UART[UART_NUM_MAX] = { + &UART0, + &UART1, +#if UART_NUM > 2 + &UART2 +#endif +}; +static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = { + portMUX_INITIALIZER_UNLOCKED, + portMUX_INITIALIZER_UNLOCKED, +#if UART_NUM > 2 + portMUX_INITIALIZER_UNLOCKED +#endif +}; static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED; esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit) @@ -132,7 +146,7 @@ esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit return ESP_OK; } -esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t* data_bit) +esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t *data_bit) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); *(data_bit) = UART[uart_num]->conf0.bit_num; @@ -157,15 +171,19 @@ esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit) return ESP_OK; } -esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t* stop_bit) +esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t *stop_bit) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); +#if CONFIG_IDF_TARGET_ESP32 //workaround for hardware bug, when uart stop bit set as 2-bit mode. if (UART[uart_num]->rs485_conf.dl1_en == 1 && UART[uart_num]->conf0.stop_bit_num == UART_STOP_BITS_1) { (*stop_bit) = UART_STOP_BITS_2; } else { (*stop_bit) = UART[uart_num]->conf0.stop_bit_num; } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + (*stop_bit) = UART[uart_num]->conf0.stop_bit_num; +#endif return ESP_OK; } @@ -179,12 +197,12 @@ esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode) return ESP_OK; } -esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode) +esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t *parity_mode) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); int val = UART[uart_num]->conf0.val; - if(val & UART_PARITY_EN_M) { - if(val & UART_PARITY_M) { + if (val & UART_PARITY_EN_M) { + if (val & UART_PARITY_M) { (*parity_mode) = UART_PARITY_ODD; } else { (*parity_mode) = UART_PARITY_EVEN; @@ -219,14 +237,14 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate) return ret; } -esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate) +esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t *baudrate) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); uint32_t clk_div = (UART[uart_num]->clk_div.div_int << 4) | UART[uart_num]->clk_div.div_frag; UART_EXIT_CRITICAL(&uart_spinlock[uart_num]); uint32_t uart_clk_freq = esp_clk_apb_freq(); - if(UART[uart_num]->conf0.tick_ref_always_on == 0) { + if (UART[uart_num]->conf0.tick_ref_always_on == 0) { uart_clk_freq = REF_CLK_FREQ; } (*baudrate) = ((uart_clk_freq) << 4) / clk_div; @@ -250,12 +268,19 @@ esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_t UART_CHECK((rx_thresh_xon < UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL); UART_CHECK((rx_thresh_xoff < UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - UART[uart_num]->flow_conf.sw_flow_con_en = enable? 1:0; - UART[uart_num]->flow_conf.xonoff_del = enable?1:0; + UART[uart_num]->flow_conf.sw_flow_con_en = enable ? 1 : 0; + UART[uart_num]->flow_conf.xonoff_del = enable ? 1 : 0; +#if CONFIG_IDF_TARGET_ESP32 UART[uart_num]->swfc_conf.xon_threshold = rx_thresh_xon; UART[uart_num]->swfc_conf.xoff_threshold = rx_thresh_xoff; UART[uart_num]->swfc_conf.xon_char = XON; UART[uart_num]->swfc_conf.xoff_char = XOFF; +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->swfc_conf1.xon_threshold = rx_thresh_xon; + UART[uart_num]->swfc_conf0.xoff_threshold = rx_thresh_xoff; + UART[uart_num]->swfc_conf1.xon_char = XON; + UART[uart_num]->swfc_conf0.xoff_char = XOFF; +#endif UART_EXIT_CRITICAL(&uart_spinlock[uart_num]); return ESP_OK; } @@ -267,13 +292,17 @@ esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow UART_CHECK((rx_thresh < UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL); UART_CHECK((flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - if(flow_ctrl & UART_HW_FLOWCTRL_RTS) { + if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { +#if CONFIG_IDF_TARGET_ESP32 UART[uart_num]->conf1.rx_flow_thrhd = rx_thresh; +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->mem_conf.rx_flow_thrhd = rx_thresh; +#endif UART[uart_num]->conf1.rx_flow_en = 1; } else { UART[uart_num]->conf1.rx_flow_en = 0; } - if(flow_ctrl & UART_HW_FLOWCTRL_CTS) { + if (flow_ctrl & UART_HW_FLOWCTRL_CTS) { UART[uart_num]->conf0.tx_flow_en = 1; } else { UART[uart_num]->conf0.tx_flow_en = 0; @@ -282,14 +311,14 @@ esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow return ESP_OK; } -esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flow_ctrl) +esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t *flow_ctrl) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); uart_hw_flowcontrol_t val = UART_HW_FLOWCTRL_DISABLE; - if(UART[uart_num]->conf1.rx_flow_en) { + if (UART[uart_num]->conf1.rx_flow_en) { val |= UART_HW_FLOWCTRL_RTS; } - if(UART[uart_num]->conf0.tx_flow_en) { + if (UART[uart_num]->conf0.tx_flow_en) { val |= UART_HW_FLOWCTRL_CTS; } (*flow_ctrl) = val; @@ -299,12 +328,12 @@ esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flo static esp_err_t uart_reset_rx_fifo(uart_port_t uart_num) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); +#if CONFIG_IDF_TARGET_ESP32 //Due to hardware issue, we can not use fifo_rst to reset uart fifo. //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <> v2.6 or later. // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`. -#if CONFIG_IDF_TARGET_ESP32 - while(UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.wr_addr != UART[uart_num]->mem_rx_status.rd_addr)) { + while (UART[uart_num]->status.rxfifo_cnt != 0 || (UART[uart_num]->mem_rx_status.wr_addr != UART[uart_num]->mem_rx_status.rd_addr)) { READ_PERI_REG(UART_FIFO_REG(uart_num)); } #elif CONFIG_IDF_TARGET_ESP32S2BETA @@ -360,7 +389,7 @@ static esp_err_t uart_pattern_link_free(uart_port_t uart_num) { UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL); if (p_uart_obj[uart_num]->rx_pattern_pos.data != NULL) { - int* pdata = p_uart_obj[uart_num]->rx_pattern_pos.data; + int *pdata = p_uart_obj[uart_num]->rx_pattern_pos.data; UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); p_uart_obj[uart_num]->rx_pattern_pos.data = NULL; p_uart_obj[uart_num]->rx_pattern_pos.wr = 0; @@ -376,7 +405,7 @@ static esp_err_t uart_pattern_enqueue(uart_port_t uart_num, int pos) UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL); esp_err_t ret = ESP_OK; UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos; + uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos; int next = p_pos->wr + 1; if (next >= p_pos->len) { next = 0; @@ -396,12 +425,12 @@ static esp_err_t uart_pattern_enqueue(uart_port_t uart_num, int pos) static esp_err_t uart_pattern_dequeue(uart_port_t uart_num) { UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL); - if(p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) { + if (p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) { return ESP_ERR_INVALID_STATE; } else { esp_err_t ret = ESP_OK; UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos; + uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos; if (p_pos->rd == p_pos->wr) { ret = ESP_FAIL; } else { @@ -419,9 +448,9 @@ static esp_err_t uart_pattern_queue_update(uart_port_t uart_num, int diff_len) { UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos; + uart_pat_rb_t *p_pos = &p_uart_obj[uart_num]->rx_pattern_pos; int rd = p_pos->rd; - while(rd != p_pos->wr) { + while (rd != p_pos->wr) { p_pos->data[rd] -= diff_len; int rd_rec = rd; rd ++; @@ -440,7 +469,7 @@ int uart_pattern_pop_pos(uart_port_t uart_num) { UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1)); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos; + uart_pat_rb_t *pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos; int pos = -1; if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) { pos = pat_pos->data[pat_pos->rd]; @@ -454,7 +483,7 @@ int uart_pattern_get_pos(uart_port_t uart_num) { UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1)); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos; + uart_pat_rb_t *pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos; int pos = -1; if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) { pos = pat_pos->data[pat_pos->rd]; @@ -468,12 +497,12 @@ esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length) UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE); - int* pdata = (int*) malloc(queue_length * sizeof(int)); - if(pdata == NULL) { + int *pdata = (int *) malloc(queue_length * sizeof(int)); + if (pdata == NULL) { return ESP_ERR_NO_MEM; } UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - int* ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data; + int *ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data; p_uart_obj[uart_num]->rx_pattern_pos.data = pdata; p_uart_obj[uart_num]->rx_pattern_pos.len = queue_length; p_uart_obj[uart_num]->rx_pattern_pos.rd = 0; @@ -483,8 +512,10 @@ esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length) return ESP_OK; } +#if CONFIG_IDF_TARGET_ESP32 esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle) { + //This function is deprecated, please use uart_enable_pattern_det_baud_intr instead. UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); UART_CHECK(chr_tout >= 0 && chr_tout <= UART_RX_GAP_TOUT_V, "uart pattern set error\n", ESP_FAIL); UART_CHECK(post_idle >= 0 && post_idle <= UART_POST_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL); @@ -496,6 +527,37 @@ esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, u UART[uart_num]->at_cmd_precnt.pre_idle_num = pre_idle; return uart_enable_intr_mask(uart_num, UART_AT_CMD_CHAR_DET_INT_ENA_M); } +#endif + +esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle) +{ + UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); + UART_CHECK(chr_tout >= 0 && chr_tout <= UART_RX_GAP_TOUT_V, "uart pattern set error\n", ESP_FAIL); + UART_CHECK(post_idle >= 0 && post_idle <= UART_POST_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL); + UART_CHECK(pre_idle >= 0 && pre_idle <= UART_PRE_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL); + UART[uart_num]->at_cmd_char.data = pattern_chr; + UART[uart_num]->at_cmd_char.char_num = chr_num; + +#if CONFIG_IDF_TARGET_ESP32 + int apb_clk_freq = 0; + uint32_t uart_baud = 0; + uint32_t uart_div = 0; + + uart_get_baudrate(uart_num, &uart_baud); + apb_clk_freq = esp_clk_apb_freq(); + uart_div = apb_clk_freq / uart_baud; + + UART[uart_num]->at_cmd_gaptout.rx_gap_tout = chr_tout * uart_div; + UART[uart_num]->at_cmd_postcnt.post_idle_num = post_idle * uart_div; + UART[uart_num]->at_cmd_precnt.pre_idle_num = pre_idle * uart_div; +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->at_cmd_gaptout.rx_gap_tout = chr_tout; + UART[uart_num]->at_cmd_postcnt.post_idle_num = post_idle; + UART[uart_num]->at_cmd_precnt.pre_idle_num = pre_idle; +#endif + + return uart_enable_intr_mask(uart_num, UART_AT_CMD_CHAR_DET_INT_ENA_M); +} esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num) { @@ -504,12 +566,12 @@ esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num) esp_err_t uart_enable_rx_intr(uart_port_t uart_num) { - return uart_enable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA); + return uart_enable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); } esp_err_t uart_disable_rx_intr(uart_port_t uart_num) { - return uart_disable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA); + return uart_disable_intr_mask(uart_num, UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); } esp_err_t uart_disable_tx_intr(uart_port_t uart_num) @@ -529,22 +591,24 @@ esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh) return ESP_OK; } -esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg, int intr_alloc_flags, uart_isr_handle_t *handle) +esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void *), void *arg, int intr_alloc_flags, uart_isr_handle_t *handle) { int ret; UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - switch(uart_num) { - case UART_NUM_1: - ret=esp_intr_alloc(ETS_UART1_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); - break; - case UART_NUM_2: - ret=esp_intr_alloc(ETS_UART2_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); - break; - case UART_NUM_0: - default: - ret=esp_intr_alloc(ETS_UART0_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); - break; + switch (uart_num) { + case UART_NUM_1: + ret = esp_intr_alloc(ETS_UART1_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); + break; +#if UART_NUM > 2 + case UART_NUM_2: + ret = esp_intr_alloc(ETS_UART2_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); + break; +#endif + case UART_NUM_0: + default: + ret = esp_intr_alloc(ETS_UART0_INTR_SOURCE, intr_alloc_flags, fn, arg, handle); + break; } UART_EXIT_CRITICAL(&uart_spinlock[uart_num]); return ret; @@ -555,10 +619,12 @@ esp_err_t uart_isr_free(uart_port_t uart_num) { esp_err_t ret; UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); - if (p_uart_obj[uart_num]->intr_handle==NULL) return ESP_ERR_INVALID_ARG; + if (p_uart_obj[uart_num]->intr_handle == NULL) { + return ESP_ERR_INVALID_ARG; + } UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); - ret=esp_intr_free(p_uart_obj[uart_num]->intr_handle); - p_uart_obj[uart_num]->intr_handle=NULL; + ret = esp_intr_free(p_uart_obj[uart_num]->intr_handle); + p_uart_obj[uart_num]->intr_handle = NULL; UART_EXIT_CRITICAL(&uart_spinlock[uart_num]); return ret; } @@ -574,53 +640,53 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r UART_CHECK((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), "cts_io_num error", ESP_FAIL); int tx_sig, rx_sig, rts_sig, cts_sig; - switch(uart_num) { - case UART_NUM_0: - tx_sig = U0TXD_OUT_IDX; - rx_sig = U0RXD_IN_IDX; - rts_sig = U0RTS_OUT_IDX; - cts_sig = U0CTS_IN_IDX; - break; - case UART_NUM_1: - tx_sig = U1TXD_OUT_IDX; - rx_sig = U1RXD_IN_IDX; - rts_sig = U1RTS_OUT_IDX; - cts_sig = U1CTS_IN_IDX; - break; -#if CONFIG_IDF_TARGET_ESP32 - case UART_NUM_2: - tx_sig = U2TXD_OUT_IDX; - rx_sig = U2RXD_IN_IDX; - rts_sig = U2RTS_OUT_IDX; - cts_sig = U2CTS_IN_IDX; - break; + switch (uart_num) { + case UART_NUM_0: + tx_sig = U0TXD_OUT_IDX; + rx_sig = U0RXD_IN_IDX; + rts_sig = U0RTS_OUT_IDX; + cts_sig = U0CTS_IN_IDX; + break; + case UART_NUM_1: + tx_sig = U1TXD_OUT_IDX; + rx_sig = U1RXD_IN_IDX; + rts_sig = U1RTS_OUT_IDX; + cts_sig = U1CTS_IN_IDX; + break; +#if UART_NUM > 2 + case UART_NUM_2: + tx_sig = U2TXD_OUT_IDX; + rx_sig = U2RXD_IN_IDX; + rts_sig = U2RTS_OUT_IDX; + cts_sig = U2CTS_IN_IDX; + break; #endif - case UART_NUM_MAX: - default: - tx_sig = U0TXD_OUT_IDX; - rx_sig = U0RXD_IN_IDX; - rts_sig = U0RTS_OUT_IDX; - cts_sig = U0CTS_IN_IDX; - break; + case UART_NUM_MAX: + default: + tx_sig = U0TXD_OUT_IDX; + rx_sig = U0RXD_IN_IDX; + rts_sig = U0RTS_OUT_IDX; + cts_sig = U0CTS_IN_IDX; + break; } - if(tx_io_num >= 0) { + if (tx_io_num >= 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO); gpio_set_level(tx_io_num, 1); gpio_matrix_out(tx_io_num, tx_sig, 0, 0); } - if(rx_io_num >= 0) { + if (rx_io_num >= 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO); gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY); gpio_set_direction(rx_io_num, GPIO_MODE_INPUT); gpio_matrix_in(rx_io_num, rx_sig, 0); } - if(rts_io_num >= 0) { + if (rts_io_num >= 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO); gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT); gpio_matrix_out(rts_io_num, rts_sig, 0, 0); } - if(cts_io_num >= 0) { + if (cts_io_num >= 0) { PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO); gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY); gpio_set_direction(cts_io_num, GPIO_MODE_INPUT); @@ -664,30 +730,34 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf esp_err_t r; UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); UART_CHECK((uart_config), "param null", ESP_FAIL); - if(uart_num == UART_NUM_0) { + if (uart_num == UART_NUM_0) { periph_module_enable(PERIPH_UART0_MODULE); - } else if(uart_num == UART_NUM_1) { + } else if (uart_num == UART_NUM_1) { periph_module_enable(PERIPH_UART1_MODULE); - } else if(uart_num == UART_NUM_2) { -#if CONFIG_IDF_TARGET_ESP32 +#if UART_NUM > 2 + } else if (uart_num == UART_NUM_2) { periph_module_enable(PERIPH_UART2_MODULE); -#else - return ESP_FAIL; #endif } r = uart_set_hw_flow_ctrl(uart_num, uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh); - if (r != ESP_OK) return r; + if (r != ESP_OK) { + return r; + } UART[uart_num]->conf0.val = - (uart_config->parity << UART_PARITY_S) + (uart_config->parity << UART_PARITY_S) | (uart_config->data_bits << UART_BIT_NUM_S) | ((uart_config->flow_ctrl & UART_HW_FLOWCTRL_CTS) ? UART_TX_FLOW_EN : 0x0) | (uart_config->use_ref_tick ? 0 : UART_TICK_REF_ALWAYS_ON_M); r = uart_set_baudrate(uart_num, uart_config->baud_rate); - if (r != ESP_OK) return r; + if (r != ESP_OK) { + return r; + } r = uart_set_tx_idle_num(uart_num, UART_TX_IDLE_NUM_DEFAULT); - if (r != ESP_OK) return r; + if (r != ESP_OK) { + return r; + } r = uart_set_stop_bits(uart_num, uart_config->stop_bits); //A hardware reset does not reset the fifo, //so we need to reset the fifo manually. @@ -701,22 +771,26 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_ UART_CHECK((intr_conf), "param null", ESP_FAIL); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); UART[uart_num]->int_clr.val = UART_INTR_MASK; - if(intr_conf->intr_enable_mask & UART_RXFIFO_TOUT_INT_ENA_M) { + if (intr_conf->intr_enable_mask & UART_RXFIFO_TOUT_INT_ENA_M) { +#if CONFIG_IDF_TARGET_ESP32 //Hardware issue workaround: when using ref_tick, the rx timeout threshold needs increase to 10 times. //T_ref = T_apb * APB_CLK/(REF_TICK << CLKDIV_FRAG_BIT_WIDTH) - if(UART[uart_num]->conf0.tick_ref_always_on == 0) { + if (UART[uart_num]->conf0.tick_ref_always_on == 0) { UART[uart_num]->conf1.rx_tout_thrhd = ((intr_conf->rx_timeout_thresh * UART_TOUT_REF_FACTOR_DEFAULT) & UART_RX_TOUT_THRHD_V); } else { UART[uart_num]->conf1.rx_tout_thrhd = ((intr_conf->rx_timeout_thresh) & UART_RX_TOUT_THRHD_V); } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->mem_conf.rx_tout_thrhd = ((intr_conf->rx_timeout_thresh) & UART_RX_TOUT_THRHD_V); +#endif UART[uart_num]->conf1.rx_tout_en = 1; } else { UART[uart_num]->conf1.rx_tout_en = 0; } - if(intr_conf->intr_enable_mask & UART_RXFIFO_FULL_INT_ENA_M) { + if (intr_conf->intr_enable_mask & UART_RXFIFO_FULL_INT_ENA_M) { UART[uart_num]->conf1.rxfifo_full_thrhd = intr_conf->rxfifo_full_thresh; } - if(intr_conf->intr_enable_mask & UART_TXFIFO_EMPTY_INT_ENA_M) { + if (intr_conf->intr_enable_mask & UART_TXFIFO_EMPTY_INT_ENA_M) { UART[uart_num]->conf1.txfifo_empty_thrhd = intr_conf->txfifo_empty_intr_thresh; } UART[uart_num]->int_ena.val = intr_conf->intr_enable_mask; @@ -724,7 +798,7 @@ esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_ return ESP_OK; } -static int uart_find_pattern_from_last(uint8_t* buf, int length, uint8_t pat_chr, int pat_num) +static int uart_find_pattern_from_last(uint8_t *buf, int length, uint8_t pat_chr, int pat_num) { int cnt = 0; int len = length; @@ -745,34 +819,34 @@ static int uart_find_pattern_from_last(uint8_t* buf, int length, uint8_t pat_chr //internal isr handler for default driver code. static void uart_rx_intr_handler_default(void *param) { - uart_obj_t *p_uart = (uart_obj_t*) param; + uart_obj_t *p_uart = (uart_obj_t *) param; uint8_t uart_num = p_uart->uart_num; - uart_dev_t* uart_reg = UART[uart_num]; + uart_dev_t *uart_reg = UART[uart_num]; int rx_fifo_len = uart_reg->status.rxfifo_cnt; uint8_t buf_idx = 0; uint32_t uart_intr_status = UART[uart_num]->int_st.val; uart_event_t uart_event; portBASE_TYPE HPTaskAwoken = 0; static uint8_t pat_flg = 0; - while(uart_intr_status != 0x0) { + while (uart_intr_status != 0x0) { buf_idx = 0; uart_event.type = UART_EVENT_MAX; - if(uart_intr_status & UART_TXFIFO_EMPTY_INT_ST_M) { + if (uart_intr_status & UART_TXFIFO_EMPTY_INT_ST_M) { uart_clear_intr_status(uart_num, UART_TXFIFO_EMPTY_INT_CLR_M); uart_disable_intr_mask_from_isr(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M); - if(p_uart->tx_waiting_brk) { + if (p_uart->tx_waiting_brk) { continue; } //TX semaphore will only be used when tx_buf_size is zero. - if(p_uart->tx_waiting_fifo == true && p_uart->tx_buf_size == 0) { + if (p_uart->tx_waiting_fifo == true && p_uart->tx_buf_size == 0) { p_uart->tx_waiting_fifo = false; xSemaphoreGiveFromISR(p_uart->tx_fifo_sem, &HPTaskAwoken); - if(HPTaskAwoken == pdTRUE) { + if (HPTaskAwoken == pdTRUE) { portYIELD_FROM_ISR(); } } else { //We don't use TX ring buffer, because the size is zero. - if(p_uart->tx_buf_size == 0) { + if (p_uart->tx_buf_size == 0) { continue; } int tx_fifo_rem = UART_FIFO_LEN - UART[uart_num]->status.txfifo_cnt; @@ -780,33 +854,32 @@ static void uart_rx_intr_handler_default(void *param) //We need to put a loop here, in case all the buffer items are very short. //That would cause a watch_dog reset because empty interrupt happens so often. //Although this is a loop in ISR, this loop will execute at most 128 turns. - while(tx_fifo_rem) { - if(p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) { + while (tx_fifo_rem) { + if (p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) { size_t size; - p_uart->tx_head = (uart_tx_data_t*) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size); - if(p_uart->tx_head) { + p_uart->tx_head = (uart_tx_data_t *) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size); + if (p_uart->tx_head) { //The first item is the data description //Get the first item to get the data information - if(p_uart->tx_len_tot == 0) { + if (p_uart->tx_len_tot == 0) { p_uart->tx_ptr = NULL; p_uart->tx_len_tot = p_uart->tx_head->tx_data.size; - if(p_uart->tx_head->type == UART_DATA_BREAK) { + if (p_uart->tx_head->type == UART_DATA_BREAK) { p_uart->tx_brk_flg = 1; p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len; } //We have saved the data description from the 1st item, return buffer. vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken); - if(HPTaskAwoken == pdTRUE) { + if (HPTaskAwoken == pdTRUE) { portYIELD_FROM_ISR(); } - }else if(p_uart->tx_ptr == NULL) { + } else if (p_uart->tx_ptr == NULL) { //Update the TX item pointer, we will need this to return item to buffer. - p_uart->tx_ptr = (uint8_t*) p_uart->tx_head; + p_uart->tx_ptr = (uint8_t *) p_uart->tx_head; en_tx_flg = true; p_uart->tx_len_cur = size; } - } - else { + } else { //Can not get data from ring buffer, return; break; } @@ -823,7 +896,7 @@ static void uart_rx_intr_handler_default(void *param) } for (buf_idx = 0; buf_idx < send_len; buf_idx++) { WRITE_PERI_REG(UART_FIFO_AHB_REG(uart_num), - *(p_uart->tx_ptr++) & 0xff); + *(p_uart->tx_ptr++) & 0xff); } p_uart->tx_len_tot -= send_len; p_uart->tx_len_cur -= send_len; @@ -831,14 +904,14 @@ static void uart_rx_intr_handler_default(void *param) if (p_uart->tx_len_cur == 0) { //Return item to ring buffer. vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken); - if(HPTaskAwoken == pdTRUE) { + if (HPTaskAwoken == pdTRUE) { portYIELD_FROM_ISR(); } p_uart->tx_head = NULL; p_uart->tx_ptr = NULL; //Sending item done, now we need to send break if there is a record. //Set TX break signal after FIFO is empty - if(p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) { + if (p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) { UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]); uart_reg->int_ena.tx_brk_done = 0; uart_reg->idle_conf.tx_brk_num = p_uart->tx_brk_len; @@ -864,13 +937,12 @@ static void uart_rx_intr_handler_default(void *param) uart_enable_intr_mask_from_isr(uart_num, UART_TXFIFO_EMPTY_INT_ENA_M); } } - } - else if ((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M) - || (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M) - || (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) - ) { + } else if ((uart_intr_status & UART_RXFIFO_TOUT_INT_ST_M) + || (uart_intr_status & UART_RXFIFO_FULL_INT_ST_M) + || (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) + ) { rx_fifo_len = uart_reg->status.rxfifo_cnt; - if(pat_flg == 1) { + if (pat_flg == 1) { uart_intr_status |= UART_AT_CMD_CHAR_DET_INT_ST_M; pat_flg = 0; } @@ -907,7 +979,7 @@ static void uart_rx_intr_handler_default(void *param) p_uart->rx_stash_len = rx_fifo_len; //If we fail to push data to ring buffer, we will have to stash the data, and send next time. //Mainly for applications that uses flow control or small ring buffer. - if(pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) { + if (pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) { p_uart->rx_buffer_full_flg = true; uart_disable_intr_mask_from_isr(uart_num, UART_RXFIFO_TOUT_INT_ENA_M | UART_RXFIFO_FULL_INT_ENA_M); if (uart_event.type == UART_PATTERN_DET) { @@ -916,11 +988,11 @@ static void uart_rx_intr_handler_default(void *param) uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len)); } else { uart_pattern_enqueue(uart_num, - pat_idx <= -1 ? - //can not find the pattern in buffer, - p_uart->rx_buffered_len + p_uart->rx_stash_len : - // find the pattern in buffer - p_uart->rx_buffered_len + pat_idx); + pat_idx <= -1 ? + //can not find the pattern in buffer, + p_uart->rx_buffered_len + p_uart->rx_stash_len : + // find the pattern in buffer + p_uart->rx_buffered_len + pat_idx); } if ((p_uart->xQueueUart != NULL) && (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken))) { ESP_EARLY_LOGV(UART_TAG, "UART event queue full"); @@ -933,7 +1005,7 @@ static void uart_rx_intr_handler_default(void *param) if (rx_fifo_len < pat_num) { //some of the characters are read out in last interrupt uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len)); - } else if(pat_idx >= 0) { + } else if (pat_idx >= 0) { // find pattern in statsh buffer. uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len + pat_idx); } @@ -941,20 +1013,20 @@ static void uart_rx_intr_handler_default(void *param) p_uart->rx_buffered_len += p_uart->rx_stash_len; UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]); } - if(HPTaskAwoken == pdTRUE) { + if (HPTaskAwoken == pdTRUE) { portYIELD_FROM_ISR(); } } else { uart_disable_intr_mask_from_isr(uart_num, UART_RXFIFO_FULL_INT_ENA_M | UART_RXFIFO_TOUT_INT_ENA_M); uart_clear_intr_status(uart_num, UART_RXFIFO_FULL_INT_CLR_M | UART_RXFIFO_TOUT_INT_CLR_M); - if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) { + if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) { uart_reg->int_clr.at_cmd_char_det = 1; uart_event.type = UART_PATTERN_DET; uart_event.size = rx_fifo_len; pat_flg = 1; } } - } else if(uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) { + } else if (uart_intr_status & UART_RXFIFO_OVF_INT_ST_M) { // When fifo overflows, we reset the fifo. UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]); uart_reset_rx_fifo(uart_num); @@ -966,10 +1038,10 @@ static void uart_rx_intr_handler_default(void *param) p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken); } UART_EXIT_CRITICAL_ISR(&uart_selectlock); - } else if(uart_intr_status & UART_BRK_DET_INT_ST_M) { + } else if (uart_intr_status & UART_BRK_DET_INT_ST_M) { uart_reg->int_clr.brk_det = 1; uart_event.type = UART_BREAK; - } else if(uart_intr_status & UART_FRM_ERR_INT_ST_M) { + } else if (uart_intr_status & UART_FRM_ERR_INT_ST_M) { uart_reg->int_clr.frm_err = 1; uart_event.type = UART_FRAME_ERR; UART_ENTER_CRITICAL_ISR(&uart_selectlock); @@ -977,7 +1049,7 @@ static void uart_rx_intr_handler_default(void *param) p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken); } UART_EXIT_CRITICAL_ISR(&uart_selectlock); - } else if(uart_intr_status & UART_PARITY_ERR_INT_ST_M) { + } else if (uart_intr_status & UART_PARITY_ERR_INT_ST_M) { uart_reg->int_clr.parity_err = 1; uart_event.type = UART_PARITY_ERR; UART_ENTER_CRITICAL_ISR(&uart_selectlock); @@ -985,33 +1057,33 @@ static void uart_rx_intr_handler_default(void *param) p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken); } UART_EXIT_CRITICAL_ISR(&uart_selectlock); - } else if(uart_intr_status & UART_TX_BRK_DONE_INT_ST_M) { + } else if (uart_intr_status & UART_TX_BRK_DONE_INT_ST_M) { UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]); uart_reg->conf0.txd_brk = 0; uart_reg->int_ena.tx_brk_done = 0; uart_reg->int_clr.tx_brk_done = 1; - if(p_uart->tx_brk_flg == 1) { + if (p_uart->tx_brk_flg == 1) { uart_reg->int_ena.txfifo_empty = 1; } UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]); - if(p_uart->tx_brk_flg == 1) { + if (p_uart->tx_brk_flg == 1) { p_uart->tx_brk_flg = 0; p_uart->tx_waiting_brk = 0; } else { xSemaphoreGiveFromISR(p_uart->tx_brk_sem, &HPTaskAwoken); - if(HPTaskAwoken == pdTRUE) { + if (HPTaskAwoken == pdTRUE) { portYIELD_FROM_ISR(); } } - } else if(uart_intr_status & UART_TX_BRK_IDLE_DONE_INT_ST_M) { + } else if (uart_intr_status & UART_TX_BRK_IDLE_DONE_INT_ST_M) { uart_disable_intr_mask_from_isr(uart_num, UART_TX_BRK_IDLE_DONE_INT_ENA_M); uart_clear_intr_status(uart_num, UART_TX_BRK_IDLE_DONE_INT_CLR_M); - } else if(uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) { + } else if (uart_intr_status & UART_AT_CMD_CHAR_DET_INT_ST_M) { uart_reg->int_clr.at_cmd_char_det = 1; uart_event.type = UART_PATTERN_DET; } else if ((uart_intr_status & UART_RS485_CLASH_INT_ST_M) - || (uart_intr_status & UART_RS485_FRM_ERR_INT_ENA) - || (uart_intr_status & UART_RS485_PARITY_ERR_INT_ENA)) { + || (uart_intr_status & UART_RS485_FRM_ERR_INT_ENA) + || (uart_intr_status & UART_RS485_PARITY_ERR_INT_ENA)) { // RS485 collision or frame error interrupt triggered uart_clear_intr_status(uart_num, UART_RS485_CLASH_INT_CLR_M); UART_ENTER_CRITICAL_ISR(&uart_spinlock[uart_num]); @@ -1020,7 +1092,7 @@ static void uart_rx_intr_handler_default(void *param) p_uart_obj[uart_num]->coll_det_flg = true; UART_EXIT_CRITICAL_ISR(&uart_spinlock[uart_num]); uart_event.type = UART_EVENT_MAX; - } else if(uart_intr_status & UART_TX_DONE_INT_ST_M) { + } else if (uart_intr_status & UART_TX_DONE_INT_ST_M) { uart_disable_intr_mask_from_isr(uart_num, UART_TX_DONE_INT_ENA_M); uart_clear_intr_status(uart_num, UART_TX_DONE_INT_CLR_M); // If RS485 half duplex mode is enable then reset FIFO and @@ -1040,11 +1112,11 @@ static void uart_rx_intr_handler_default(void *param) uart_event.type = UART_EVENT_MAX; } - if(uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) { + if (uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) { if (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken)) { ESP_EARLY_LOGV(UART_TAG, "UART event queue full"); } - if(HPTaskAwoken == pdTRUE) { + if (HPTaskAwoken == pdTRUE) { portYIELD_FROM_ISR(); } } @@ -1061,11 +1133,11 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait) portTickType ticks_start = xTaskGetTickCount(); //Take tx_mux res = xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)ticks_to_wait); - if(res == pdFALSE) { + if (res == pdFALSE) { return ESP_ERR_TIMEOUT; } xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, 0); - if(UART[uart_num]->status.txfifo_cnt == 0) { + if (UART[uart_num]->status.txfifo_cnt == 0) { xSemaphoreGive(p_uart_obj[uart_num]->tx_mux); return ESP_OK; } @@ -1079,7 +1151,7 @@ esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait) } //take 2nd tx_done_sem, wait given from ISR res = xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, (portTickType)ticks_to_wait); - if(res == pdFALSE) { + if (res == pdFALSE) { uart_disable_intr_mask(uart_num, UART_TX_DONE_INT_ENA_M); xSemaphoreGive(p_uart_obj[uart_num]->tx_mux); return ESP_ERR_TIMEOUT; @@ -1101,7 +1173,7 @@ static esp_err_t uart_set_break(uart_port_t uart_num, int break_num) //Fill UART tx_fifo and return a number, //This function by itself is not thread-safe, always call from within a muxed section. -static int uart_fill_fifo(uart_port_t uart_num, const char* buffer, uint32_t len) +static int uart_fill_fifo(uart_port_t uart_num, const char *buffer, uint32_t len) { uint8_t i = 0; uint8_t tx_fifo_cnt = UART[uart_num]->status.txfifo_cnt; @@ -1118,23 +1190,23 @@ static int uart_fill_fifo(uart_port_t uart_num, const char* buffer, uint32_t len return copy_cnt; } -int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len) +int uart_tx_chars(uart_port_t uart_num, const char *buffer, uint32_t len) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1)); UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1)); UART_CHECK(buffer, "buffer null", (-1)); - if(len == 0) { + if (len == 0) { return 0; } xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY); - int tx_len = uart_fill_fifo(uart_num, (const char*) buffer, len); + int tx_len = uart_fill_fifo(uart_num, (const char *) buffer, len); xSemaphoreGive(p_uart_obj[uart_num]->tx_mux); return tx_len; } -static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool brk_en, int brk_len) +static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool brk_en, int brk_len) { - if(size == 0) { + if (size == 0) { return 0; } size_t original_size = size; @@ -1142,31 +1214,31 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool //lock for uart_tx xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY); p_uart_obj[uart_num]->coll_det_flg = false; - if(p_uart_obj[uart_num]->tx_buf_size > 0) { + if (p_uart_obj[uart_num]->tx_buf_size > 0) { int max_size = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf); int offset = 0; uart_tx_data_t evt; evt.tx_data.size = size; evt.tx_data.brk_len = brk_len; - if(brk_en) { + if (brk_en) { evt.type = UART_DATA_BREAK; } else { evt.type = UART_DATA; } - xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) &evt, sizeof(uart_tx_data_t), portMAX_DELAY); - while(size > 0) { + xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) &evt, sizeof(uart_tx_data_t), portMAX_DELAY); + while (size > 0) { int send_size = size > max_size / 2 ? max_size / 2 : size; - xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) (src + offset), send_size, portMAX_DELAY); + xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) (src + offset), send_size, portMAX_DELAY); size -= send_size; offset += send_size; uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT); } } else { - while(size) { + while (size) { //semaphore for tx_fifo available - if(pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) { - size_t sent = uart_fill_fifo(uart_num, (char*) src, size); - if(sent < size) { + if (pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) { + size_t sent = uart_fill_fifo(uart_num, (char *) src, size); + if (sent < size) { p_uart_obj[uart_num]->tx_waiting_fifo = true; uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT); } @@ -1174,7 +1246,7 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool src += sent; } } - if(brk_en) { + if (brk_en) { uart_set_break(uart_num, brk_len); xSemaphoreTake(p_uart_obj[uart_num]->tx_brk_sem, (portTickType)portMAX_DELAY); } @@ -1184,7 +1256,7 @@ static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool return original_size; } -int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size) +int uart_write_bytes(uart_port_t uart_num, const char *src, size_t size) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1)); UART_CHECK((p_uart_obj[uart_num] != NULL), "uart driver error", (-1)); @@ -1192,7 +1264,7 @@ int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size) return uart_tx_all(uart_num, src, size, 0, 0); } -int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len) +int uart_write_bytes_with_break(uart_port_t uart_num, const char *src, size_t size, int brk_len) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1)); UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1)); @@ -1204,9 +1276,9 @@ int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t si static bool uart_check_buf_full(uart_port_t uart_num) { - if(p_uart_obj[uart_num]->rx_buffer_full_flg) { + if (p_uart_obj[uart_num]->rx_buffer_full_flg) { BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1); - if(res == pdTRUE) { + if (res == pdTRUE) { UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len; p_uart_obj[uart_num]->rx_buffer_full_flg = false; @@ -1218,22 +1290,22 @@ static bool uart_check_buf_full(uart_port_t uart_num) return false; } -int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait) +int uart_read_bytes(uart_port_t uart_num, uint8_t *buf, uint32_t length, TickType_t ticks_to_wait) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1)); UART_CHECK((buf), "uart data null", (-1)); UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1)); - uint8_t* data = NULL; + uint8_t *data = NULL; size_t size; size_t copy_len = 0; int len_tmp; - if(xSemaphoreTake(p_uart_obj[uart_num]->rx_mux,(portTickType)ticks_to_wait) != pdTRUE) { + if (xSemaphoreTake(p_uart_obj[uart_num]->rx_mux, (portTickType)ticks_to_wait) != pdTRUE) { return -1; } - while(length) { - if(p_uart_obj[uart_num]->rx_cur_remain == 0) { - data = (uint8_t*) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (portTickType) ticks_to_wait); - if(data) { + while (length) { + if (p_uart_obj[uart_num]->rx_cur_remain == 0) { + data = (uint8_t *) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (portTickType) ticks_to_wait); + if (data) { p_uart_obj[uart_num]->rx_head_ptr = data; p_uart_obj[uart_num]->rx_ptr = data; p_uart_obj[uart_num]->rx_cur_remain = size; @@ -1241,7 +1313,7 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp //When using dual cores, `rx_buffer_full_flg` may read and write on different cores at same time, //which may lose synchronization. So we also need to call `uart_check_buf_full` once when ringbuffer is empty //to solve the possible asynchronous issues. - if(uart_check_buf_full(uart_num)) { + if (uart_check_buf_full(uart_num)) { //This condition will never be true if `uart_read_bytes` //and `uart_rx_intr_handler_default` are scheduled on the same core. continue; @@ -1251,7 +1323,7 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp } } } - if(p_uart_obj[uart_num]->rx_cur_remain > length) { + if (p_uart_obj[uart_num]->rx_cur_remain > length) { len_tmp = length; } else { len_tmp = p_uart_obj[uart_num]->rx_cur_remain; @@ -1265,7 +1337,7 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp p_uart_obj[uart_num]->rx_cur_remain -= len_tmp; copy_len += len_tmp; length -= len_tmp; - if(p_uart_obj[uart_num]->rx_cur_remain == 0) { + if (p_uart_obj[uart_num]->rx_cur_remain == 0) { vRingbufferReturnItem(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_head_ptr); p_uart_obj[uart_num]->rx_head_ptr = NULL; p_uart_obj[uart_num]->rx_ptr = NULL; @@ -1277,7 +1349,7 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp return copy_len; } -esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size) +esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t *size) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL); @@ -1291,15 +1363,15 @@ esp_err_t uart_flush_input(uart_port_t uart_num) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL); - uart_obj_t* p_uart = p_uart_obj[uart_num]; - uint8_t* data; + uart_obj_t *p_uart = p_uart_obj[uart_num]; + uint8_t *data; size_t size; //rx sem protect the ring buffer read related functions xSemaphoreTake(p_uart->rx_mux, (portTickType)portMAX_DELAY); uart_disable_rx_intr(p_uart_obj[uart_num]->uart_num); - while(true) { - if(p_uart->rx_head_ptr) { + while (true) { + if (p_uart->rx_head_ptr) { vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr); UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain; @@ -1309,9 +1381,9 @@ esp_err_t uart_flush_input(uart_port_t uart_num) p_uart->rx_cur_remain = 0; p_uart->rx_head_ptr = NULL; } - data = (uint8_t*) xRingbufferReceive(p_uart->rx_ring_buf, &size, (portTickType) 0); - if(data == NULL) { - if( p_uart_obj[uart_num]->rx_buffered_len != 0 ) { + data = (uint8_t *) xRingbufferReceive(p_uart->rx_ring_buf, &size, (portTickType) 0); + if (data == NULL) { + if ( p_uart_obj[uart_num]->rx_buffered_len != 0 ) { ESP_LOGE(UART_TAG, "rx_buffered_len error"); p_uart_obj[uart_num]->rx_buffered_len = 0; } @@ -1326,9 +1398,9 @@ esp_err_t uart_flush_input(uart_port_t uart_num) uart_pattern_queue_update(uart_num, size); UART_EXIT_CRITICAL(&uart_spinlock[uart_num]); vRingbufferReturnItem(p_uart->rx_ring_buf, data); - if(p_uart_obj[uart_num]->rx_buffer_full_flg) { + if (p_uart_obj[uart_num]->rx_buffer_full_flg) { BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1); - if(res == pdTRUE) { + if (res == pdTRUE) { UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len; p_uart_obj[uart_num]->rx_buffer_full_flg = false; @@ -1353,9 +1425,9 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b UART_CHECK((tx_buffer_size > UART_FIFO_LEN) || (tx_buffer_size == 0), "uart tx buffer length error(>128 or 0)", ESP_FAIL); UART_CHECK((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM set in intr_alloc_flags", ESP_FAIL); /* uart_rx_intr_handler_default is not in IRAM */ - if(p_uart_obj[uart_num] == NULL) { - p_uart_obj[uart_num] = (uart_obj_t*) calloc(1, sizeof(uart_obj_t)); - if(p_uart_obj[uart_num] == NULL) { + if (p_uart_obj[uart_num] == NULL) { + p_uart_obj[uart_num] = (uart_obj_t *) calloc(1, sizeof(uart_obj_t)); + if (p_uart_obj[uart_num] == NULL) { ESP_LOGE(UART_TAG, "UART driver malloc error"); return ESP_FAIL; } @@ -1378,7 +1450,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b p_uart_obj[uart_num]->rx_buffered_len = 0; uart_pattern_queue_reset(uart_num, UART_PATTERN_DET_QLEN_DEFAULT); - if(uart_queue) { + if (uart_queue) { p_uart_obj[uart_num]->xQueueUart = xQueueCreate(queue_size, sizeof(uart_event_t)); *uart_queue = p_uart_obj[uart_num]->xQueueUart; ESP_LOGI(UART_TAG, "queue free spaces: %d", uxQueueSpacesAvailable(p_uart_obj[uart_num]->xQueueUart)); @@ -1391,7 +1463,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b p_uart_obj[uart_num]->rx_cur_remain = 0; p_uart_obj[uart_num]->rx_head_ptr = NULL; p_uart_obj[uart_num]->rx_ring_buf = xRingbufferCreate(rx_buffer_size, RINGBUF_TYPE_BYTEBUF); - if(tx_buffer_size > 0) { + if (tx_buffer_size > 0) { p_uart_obj[uart_num]->tx_ring_buf = xRingbufferCreate(tx_buffer_size, RINGBUF_TYPE_NOSPLIT); p_uart_obj[uart_num]->tx_buf_size = tx_buffer_size; } else { @@ -1404,21 +1476,25 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b return ESP_FAIL; } - r=uart_isr_register(uart_num, uart_rx_intr_handler_default, p_uart_obj[uart_num], intr_alloc_flags, &p_uart_obj[uart_num]->intr_handle); - if (r!=ESP_OK) goto err; + r = uart_isr_register(uart_num, uart_rx_intr_handler_default, p_uart_obj[uart_num], intr_alloc_flags, &p_uart_obj[uart_num]->intr_handle); + if (r != ESP_OK) { + goto err; + } uart_intr_config_t uart_intr = { .intr_enable_mask = UART_RXFIFO_FULL_INT_ENA_M - | UART_RXFIFO_TOUT_INT_ENA_M - | UART_FRM_ERR_INT_ENA_M - | UART_RXFIFO_OVF_INT_ENA_M - | UART_BRK_DET_INT_ENA_M - | UART_PARITY_ERR_INT_ENA_M, + | UART_RXFIFO_TOUT_INT_ENA_M + | UART_FRM_ERR_INT_ENA_M + | UART_RXFIFO_OVF_INT_ENA_M + | UART_BRK_DET_INT_ENA_M + | UART_PARITY_ERR_INT_ENA_M, .rxfifo_full_thresh = UART_FULL_THRESH_DEFAULT, .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT, .txfifo_empty_intr_thresh = UART_EMPTY_THRESH_DEFAULT }; - r=uart_intr_config(uart_num, &uart_intr); - if (r!=ESP_OK) goto err; + r = uart_intr_config(uart_num, &uart_intr); + if (r != ESP_OK) { + goto err; + } return r; err: @@ -1430,7 +1506,7 @@ err: esp_err_t uart_driver_delete(uart_port_t uart_num) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL); - if(p_uart_obj[uart_num] == NULL) { + if (p_uart_obj[uart_num] == NULL) { ESP_LOGI(UART_TAG, "ALREADY NULL"); return ESP_OK; } @@ -1439,35 +1515,35 @@ esp_err_t uart_driver_delete(uart_port_t uart_num) uart_disable_tx_intr(uart_num); uart_pattern_link_free(uart_num); - if(p_uart_obj[uart_num]->tx_fifo_sem) { + if (p_uart_obj[uart_num]->tx_fifo_sem) { vSemaphoreDelete(p_uart_obj[uart_num]->tx_fifo_sem); p_uart_obj[uart_num]->tx_fifo_sem = NULL; } - if(p_uart_obj[uart_num]->tx_done_sem) { + if (p_uart_obj[uart_num]->tx_done_sem) { vSemaphoreDelete(p_uart_obj[uart_num]->tx_done_sem); p_uart_obj[uart_num]->tx_done_sem = NULL; } - if(p_uart_obj[uart_num]->tx_brk_sem) { + if (p_uart_obj[uart_num]->tx_brk_sem) { vSemaphoreDelete(p_uart_obj[uart_num]->tx_brk_sem); p_uart_obj[uart_num]->tx_brk_sem = NULL; } - if(p_uart_obj[uart_num]->tx_mux) { + if (p_uart_obj[uart_num]->tx_mux) { vSemaphoreDelete(p_uart_obj[uart_num]->tx_mux); p_uart_obj[uart_num]->tx_mux = NULL; } - if(p_uart_obj[uart_num]->rx_mux) { + if (p_uart_obj[uart_num]->rx_mux) { vSemaphoreDelete(p_uart_obj[uart_num]->rx_mux); p_uart_obj[uart_num]->rx_mux = NULL; } - if(p_uart_obj[uart_num]->xQueueUart) { + if (p_uart_obj[uart_num]->xQueueUart) { vQueueDelete(p_uart_obj[uart_num]->xQueueUart); p_uart_obj[uart_num]->xQueueUart = NULL; } - if(p_uart_obj[uart_num]->rx_ring_buf) { + if (p_uart_obj[uart_num]->rx_ring_buf) { vRingbufferDelete(p_uart_obj[uart_num]->rx_ring_buf); p_uart_obj[uart_num]->rx_ring_buf = NULL; } - if(p_uart_obj[uart_num]->tx_ring_buf) { + if (p_uart_obj[uart_num]->tx_ring_buf) { vRingbufferDelete(p_uart_obj[uart_num]->tx_ring_buf); p_uart_obj[uart_num]->tx_ring_buf = NULL; } @@ -1476,17 +1552,15 @@ esp_err_t uart_driver_delete(uart_port_t uart_num) p_uart_obj[uart_num] = NULL; if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM ) { - if(uart_num == UART_NUM_0) { - periph_module_disable(PERIPH_UART0_MODULE); - } else if(uart_num == UART_NUM_1) { - periph_module_disable(PERIPH_UART1_MODULE); - } else if(uart_num == UART_NUM_2) { -#if CONFIG_IDF_TARGET_ESP32 + if (uart_num == UART_NUM_0) { + periph_module_disable(PERIPH_UART0_MODULE); + } else if (uart_num == UART_NUM_1) { + periph_module_disable(PERIPH_UART1_MODULE); +#if UART_NUM > 2 + } else if (uart_num == UART_NUM_2) { periph_module_disable(PERIPH_UART2_MODULE); -#else - return ESP_FAIL; #endif - } + } } return ESP_OK; } @@ -1502,6 +1576,7 @@ portMUX_TYPE *uart_get_selectlock() { return &uart_selectlock; } + // Set UART mode esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode) { @@ -1510,7 +1585,7 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode) if ((mode == UART_MODE_RS485_COLLISION_DETECT) || (mode == UART_MODE_RS485_APP_CTRL) || (mode == UART_MODE_RS485_HALF_DUPLEX)) { UART_CHECK((UART[uart_num]->conf1.rx_flow_en != 1), - "disable hw flowctrl before using RS485 mode", ESP_ERR_INVALID_ARG); + "disable hw flowctrl before using RS485 mode", ESP_ERR_INVALID_ARG); } UART_ENTER_CRITICAL(&uart_spinlock[uart_num]); UART[uart_num]->rs485_conf.en = 0; @@ -1531,10 +1606,10 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode) UART[uart_num]->rs485_conf.en = 1; // Enable collision detection interrupts uart_enable_intr_mask(uart_num, UART_RXFIFO_TOUT_INT_ENA - | UART_RXFIFO_FULL_INT_ENA - | UART_RS485_CLASH_INT_ENA - | UART_RS485_FRM_ERR_INT_ENA - | UART_RS485_PARITY_ERR_INT_ENA); + | UART_RXFIFO_FULL_INT_ENA + | UART_RS485_CLASH_INT_ENA + | UART_RS485_FRM_ERR_INT_ENA + | UART_RS485_PARITY_ERR_INT_ENA); break; case UART_MODE_RS485_APP_CTRL: // Application software control, remove echo @@ -1570,7 +1645,15 @@ esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh) // The tout_thresh = 1, defines TOUT interrupt timeout equal to // transmission time of one symbol (~11 bit) on current baudrate if (tout_thresh > 0) { - UART[uart_num]->conf1.rx_tout_thrhd = (tout_thresh & UART_RX_TOUT_THRHD_V); +#if CONFIG_IDF_TARGET_ESP32 + if (UART[uart_num]->conf0.tick_ref_always_on == 0) { + UART[uart_num]->conf1.rx_tout_thrhd = ((tout_thresh * UART_TOUT_REF_FACTOR_DEFAULT) & UART_RX_TOUT_THRHD_V); + } else { + UART[uart_num]->conf1.rx_tout_thrhd = ((tout_thresh) & UART_RX_TOUT_THRHD_V); + } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + UART[uart_num]->mem_conf.rx_tout_thrhd = ((tout_thresh) & UART_RX_TOUT_THRHD_V); +#endif UART[uart_num]->conf1.rx_tout_en = 1; } else { UART[uart_num]->conf1.rx_tout_en = 0; @@ -1579,13 +1662,13 @@ esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh) return ESP_OK; } -esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag) +esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool *collision_flag) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG); UART_CHECK((collision_flag != NULL), "wrong parameter pointer", ESP_ERR_INVALID_ARG); UART_CHECK((UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX) - || UART_IS_MODE_SET(uart_num, UART_MODE_RS485_COLLISION_DETECT)), - "wrong mode", ESP_ERR_INVALID_ARG); + || UART_IS_MODE_SET(uart_num, UART_MODE_RS485_COLLISION_DETECT)), + "wrong mode", ESP_ERR_INVALID_ARG); *collision_flag = p_uart_obj[uart_num]->coll_det_flg; return ESP_OK; } @@ -1595,13 +1678,13 @@ esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold) UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG); UART_CHECK((wakeup_threshold <= UART_ACTIVE_THRESHOLD_V && wakeup_threshold > UART_MIN_WAKEUP_THRESH), - "wakeup_threshold out of bounds", ESP_ERR_INVALID_ARG); + "wakeup_threshold out of bounds", ESP_ERR_INVALID_ARG); UART[uart_num]->sleep_conf.active_threshold = wakeup_threshold - UART_MIN_WAKEUP_THRESH; return ESP_OK; } -esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_threshold) +esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int *out_wakeup_threshold) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG); UART_CHECK((out_wakeup_threshold != NULL), "argument is NULL", ESP_ERR_INVALID_ARG); diff --git a/components/freemodbus/common/include/esp_modbus_common.h b/components/freemodbus/common/include/esp_modbus_common.h index 7bec02476a..34810cf366 100644 --- a/components/freemodbus/common/include/esp_modbus_common.h +++ b/components/freemodbus/common/include/esp_modbus_common.h @@ -22,10 +22,10 @@ #define MB_CONTROLLER_PRIORITY (CONFIG_FMB_SERIAL_TASK_PRIO - 1) // priority of MB controller task // Default port defines -#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus -#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined -#define MB_UART_PORT (UART_NUM_2) // Default UART port number -#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info +#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus +#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined +#define MB_UART_PORT (UART_NUM_MAX - 1) // Default UART port number +#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info #define MB_PARITY_NONE (UART_PARITY_DISABLE) // The Macros below handle the endianness while transfer N byte data into buffer diff --git a/components/freemodbus/port/portserial.c b/components/freemodbus/port/portserial.c index 54bbe8318b..10967af7ab 100644 --- a/components/freemodbus/port/portserial.c +++ b/components/freemodbus/port/portserial.c @@ -78,7 +78,7 @@ static TaskHandle_t xMbTaskHandle; static const CHAR *TAG = "MB_SERIAL"; // The UART hardware port number -static UCHAR ucUartNumber = UART_NUM_2; +static UCHAR ucUartNumber = UART_NUM_MAX - 1; static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag diff --git a/components/freemodbus/port/portserial_m.c b/components/freemodbus/port/portserial_m.c index 74a4a1be04..330269101a 100644 --- a/components/freemodbus/port/portserial_m.c +++ b/components/freemodbus/port/portserial_m.c @@ -73,7 +73,7 @@ static QueueHandle_t xMbUartQueue; static TaskHandle_t xMbTaskHandle; // The UART hardware port number -static UCHAR ucUartNumber = UART_NUM_2; +static UCHAR ucUartNumber = UART_NUM_MAX - 1; static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag diff --git a/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c b/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c index 8db15aea41..30aae200fc 100644 --- a/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c +++ b/components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c @@ -83,7 +83,7 @@ static esp_err_t mbc_serial_master_setup(void* comm_info) MB_MASTER_CHECK(((comm_info_ptr->mode == MB_MODE_RTU) || (comm_info_ptr->mode == MB_MODE_ASCII)), ESP_ERR_INVALID_ARG, "mb incorrect mode = (0x%x).", (uint32_t)comm_info_ptr->mode); - MB_MASTER_CHECK((comm_info_ptr->port <= UART_NUM_2), ESP_ERR_INVALID_ARG, + MB_MASTER_CHECK((comm_info_ptr->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG, "mb wrong port to set = (0x%x).", (uint32_t)comm_info_ptr->port); MB_MASTER_CHECK((comm_info_ptr->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG, "mb wrong parity option = (0x%x).", (uint32_t)comm_info_ptr->parity); diff --git a/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c b/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c index 86e9616d02..72d753e520 100644 --- a/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c +++ b/components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c @@ -69,7 +69,7 @@ static esp_err_t mbc_serial_slave_setup(void* comm_info) MB_SLAVE_CHECK((comm_settings->slave_addr <= MB_ADDRESS_MAX), ESP_ERR_INVALID_ARG, "mb wrong slave address = (0x%x).", (uint32_t)comm_settings->slave_addr); - MB_SLAVE_CHECK((comm_settings->port <= UART_NUM_2), ESP_ERR_INVALID_ARG, + MB_SLAVE_CHECK((comm_settings->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG, "mb wrong port to set = (0x%x).", (uint32_t)comm_settings->port); MB_SLAVE_CHECK((comm_settings->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG, "mb wrong parity option = (0x%x).", (uint32_t)comm_settings->parity); diff --git a/components/soc/esp32/include/soc/uart_caps.h b/components/soc/esp32/include/soc/uart_caps.h new file mode 100644 index 0000000000..21af9f4d85 --- /dev/null +++ b/components/soc/esp32/include/soc/uart_caps.h @@ -0,0 +1,25 @@ +// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_UART_NUM 3 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s2beta/include/soc/uart_caps.h b/components/soc/esp32s2beta/include/soc/uart_caps.h new file mode 100644 index 0000000000..1981f7ebf1 --- /dev/null +++ b/components/soc/esp32s2beta/include/soc/uart_caps.h @@ -0,0 +1,25 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_UART_NUM 2 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s2beta/include/soc/uart_struct.h b/components/soc/esp32s2beta/include/soc/uart_struct.h index c4096d5f97..07f27e905b 100644 --- a/components/soc/esp32s2beta/include/soc/uart_struct.h +++ b/components/soc/esp32s2beta/include/soc/uart_struct.h @@ -20,354 +20,353 @@ extern "C" { typedef volatile struct { union { struct { - uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/ + uint8_t rw_byte; uint8_t reserved[3]; }; uint32_t val; } ahb_fifo; union { struct { - uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ - uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ - uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ - uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ - uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ - uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ - uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ - uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ - uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ - uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ - uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ - uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ - uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ - uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ - uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ - uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ - uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ - uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_raw; union { struct { - uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ - uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ - uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ - uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ - uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ - uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ - uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ - uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ - uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ - uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ - uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ - uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ - uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ - uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ - uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ - uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ - uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ - uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_st; union { struct { - uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ - uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ - uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ - uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ - uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ - uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ - uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ - uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ - uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ - uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ - uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ - uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ - uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ - uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ - uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_ena; union { struct { - uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ - uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ - uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ - uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ - uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ - uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ - uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ - uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ - uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ - uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ - uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ - uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ - uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ - uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ - uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ - uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ - uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; }; uint32_t val; } int_clr; union { struct { - uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/ - uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + uint32_t div_int: 20; + uint32_t div_frag: 4; uint32_t reserved24: 8; }; uint32_t val; } clk_div; union { struct { - uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t en: 1; uint32_t reserved1: 7; - uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ + uint32_t glitch_filt: 8; uint32_t reserved16: 16; }; uint32_t val; } auto_baud; union { struct { - uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ - uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ - uint32_t reserved12: 1; - uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ - uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ - uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ - uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ - uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ - uint32_t reserved28: 1; - uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ - uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ - uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + uint32_t rxfifo_cnt:10; + uint32_t reserved10: 3; + uint32_t dsrn: 1; + uint32_t ctsn: 1; + uint32_t rxd: 1; + uint32_t txfifo_cnt:10; + uint32_t reserved26: 3; + uint32_t dtrn: 1; + uint32_t rtsn: 1; + uint32_t txd: 1; }; uint32_t val; } status; union { struct { - uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ - uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ - uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ - uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ - uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ - uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ - uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ - uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/ - uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ - uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ - uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ - uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ - uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ - uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ - uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ - uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ - uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ - uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ - uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ - uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ - uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ - uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ - uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ - uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ - uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ - uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ + uint32_t parity: 1; + uint32_t parity_en: 1; + uint32_t bit_num: 2; + uint32_t stop_bit_num: 2; + uint32_t sw_rts: 1; + uint32_t sw_dtr: 1; + uint32_t txd_brk: 1; + uint32_t irda_dplx: 1; + uint32_t irda_tx_en: 1; + uint32_t irda_wctl: 1; + uint32_t irda_tx_inv: 1; + uint32_t irda_rx_inv: 1; + uint32_t loopback: 1; + uint32_t tx_flow_en: 1; + uint32_t irda_en: 1; + uint32_t rxfifo_rst: 1; + uint32_t txfifo_rst: 1; + uint32_t rxd_inv: 1; + uint32_t cts_inv: 1; + uint32_t dsr_inv: 1; + uint32_t txd_inv: 1; + uint32_t rts_inv: 1; + uint32_t dtr_inv: 1; + uint32_t clk_en: 1; + uint32_t err_wr_mask: 1; + uint32_t tick_ref_always_on: 1; uint32_t reserved28: 4; }; uint32_t val; } conf0; union { struct { - uint32_t rxfifo_full_thrhd: 7; - uint32_t reserved7: 1; - uint32_t txfifo_empty_thrhd: 7; + uint32_t rxfifo_full_thrhd: 9; + uint32_t txfifo_empty_thrhd: 9; + uint32_t reserved18: 11; uint32_t rx_tout_flow_dis: 1; - uint32_t rx_flow_thrhd: 7; uint32_t rx_flow_en: 1; - uint32_t rx_tout_thrhd: 7; uint32_t rx_tout_en: 1; }; uint32_t val; } conf1; union { struct { - uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } lowpulse; union { struct { - uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } highpulse; union { struct { - uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + uint32_t edge_cnt: 10; uint32_t reserved10: 22; }; uint32_t val; } rxd_cnt; union { struct { - uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ - uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ - uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ - uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ - uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ - uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ + uint32_t sw_flow_con_en: 1; + uint32_t xonoff_del: 1; + uint32_t force_xon: 1; + uint32_t force_xoff: 1; + uint32_t send_xon: 1; + uint32_t send_xoff: 1; uint32_t reserved6: 26; }; uint32_t val; } flow_conf; union { struct { - uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ + uint32_t active_threshold:10; uint32_t reserved10: 22; }; uint32_t val; } sleep_conf; union { struct { - uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ - uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ - uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ - uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ + uint32_t xoff_threshold: 9; + uint32_t xoff_char: 8; + uint32_t reserved17: 15; }; uint32_t val; - } swfc_conf; + } swfc_conf0; union { struct { - uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ - uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ - uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ + uint32_t xon_threshold: 9; + uint32_t xon_char: 8; + uint32_t reserved17: 15; + }; + uint32_t val; + } swfc_conf1; + union { + struct { + uint32_t rx_idle_thrhd:10; + uint32_t tx_idle_num: 10; + uint32_t tx_brk_num: 8; uint32_t reserved28: 4; }; uint32_t val; } idle_conf; union { struct { - uint32_t en: 1; /*Set this bit to choose rs485 mode.*/ - uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ - uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ - uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ - uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t en: 1; + uint32_t dl0_en: 1; + uint32_t dl1_en: 1; + uint32_t tx_rx_en: 1; + uint32_t rx_busy_tx_en: 1; + uint32_t rx_dly_num: 1; + uint32_t tx_dly_num: 4; uint32_t reserved10: 22; }; uint32_t val; } rs485_conf; union { struct { - uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ - uint32_t reserved24: 8; + uint32_t pre_idle_num:16; + uint32_t reserved16: 16; }; uint32_t val; } at_cmd_precnt; union { struct { - uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ - uint32_t reserved24: 8; + uint32_t post_idle_num:16; + uint32_t reserved16: 16; }; uint32_t val; } at_cmd_postcnt; union { struct { - uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ - uint32_t reserved24: 8; + uint32_t rx_gap_tout:16; + uint32_t reserved16: 16; }; uint32_t val; } at_cmd_gaptout; union { struct { - uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ - uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ + uint32_t data: 8; + uint32_t char_num: 8; uint32_t reserved16: 16; }; uint32_t val; } at_cmd_char; union { struct { - uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ - uint32_t reserved1: 1; - uint32_t reserved2: 1; - uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ - uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ - uint32_t reserved11: 4; - uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ - uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ - uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ - uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ - uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ - uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ - uint32_t reserved31: 1; + uint32_t mem_pd: 1; + uint32_t rx_size: 3; + uint32_t tx_size: 3; + uint32_t rx_flow_thrhd: 9; + uint32_t rx_tout_thrhd:10; + uint32_t reserved26: 6; }; uint32_t val; } mem_conf; union { struct { - uint32_t apb_tx_waddr:11; - uint32_t tx_raddr: 11; - uint32_t reserved22: 10; + uint32_t apb_tx_waddr:10; + uint32_t reserved10: 1; + uint32_t tx_raddr: 10; + uint32_t reserved21: 11; }; uint32_t val; } mem_tx_status; union { struct { - uint32_t apb_rx_raddr:11; - uint32_t rx_waddr: 11; - uint32_t reserved22: 10; + uint32_t apb_rx_raddr:10; + uint32_t reserved10: 1; + uint32_t rx_waddr: 10; + uint32_t reserved21: 11; }; uint32_t val; } mem_rx_status; union { struct { - uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/ - uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/ - uint32_t reserved6: 26; + uint32_t st_urx_out: 4; + uint32_t st_utx_out: 4; + uint32_t reserved8: 24; }; uint32_t val; - } mem_cnt_status; + } fsm_status; union { struct { - uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } pospulse; union { struct { - uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; + uint32_t reserved20: 12; }; uint32_t val; } negpulse; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t date; /**/ - uint32_t id; /**/ + uint32_t date; /**/ + uint32_t id; /**/ } uart_dev_t; extern uart_dev_t UART0; extern uart_dev_t UART1; -extern uart_dev_t UART2; #ifdef __cplusplus } #endif diff --git a/components/soc/include/soc/uart_periph.h b/components/soc/include/soc/uart_periph.h index d149048aa1..27324cd1d5 100644 --- a/components/soc/include/soc/uart_periph.h +++ b/components/soc/include/soc/uart_periph.h @@ -13,6 +13,8 @@ // limitations under the License. #pragma once + +#include "soc/uart_caps.h" #include "soc/uart_reg.h" #include "soc/uart_struct.h" #include "soc/uart_channel.h" diff --git a/components/vfs/test/test_vfs_access.c b/components/vfs/test/test_vfs_access.c index 02e7d56f82..4f3988842a 100644 --- a/components/vfs/test/test_vfs_access.c +++ b/components/vfs/test/test_vfs_access.c @@ -27,11 +27,19 @@ static wl_handle_t test_wl_handle; TEST_CASE("Can use access() for UART", "[vfs]") { - const char *uarts[] = {"/dev/uart/0", "/dev/uart/1", "/dev/uart/2"}; + const char *uarts[] = { + "/dev/uart/0", + "/dev/uart/1", +#if SOC_UART_NUM > 2 + "/dev/uart/2" +#endif + }; uart_driver_install(UART_NUM_0, 256, 0, 0, NULL, 0); uart_driver_install(UART_NUM_1, 256, 0, 0, NULL, 0); +#if SOC_UART_NUM > 2 uart_driver_install(UART_NUM_2, 256, 0, 0, NULL, 0); +#endif for (int i = 0; i < sizeof(uarts)/sizeof(uarts[0]); ++i) { TEST_ASSERT_EQUAL_MESSAGE(access(uarts[i], F_OK), 0, uarts[i]); @@ -55,7 +63,9 @@ TEST_CASE("Can use access() for UART", "[vfs]") uart_driver_delete(UART_NUM_0); uart_driver_delete(UART_NUM_1); +#if SOC_UART_NUM > 2 uart_driver_delete(UART_NUM_2); +#endif } static inline void test_spi_flash_setup() diff --git a/components/vfs/vfs_uart.c b/components/vfs/vfs_uart.c index 2bb365a605..36fade118a 100644 --- a/components/vfs/vfs_uart.c +++ b/components/vfs/vfs_uart.c @@ -32,11 +32,27 @@ #endif // TODO: make the number of UARTs chip dependent -#define UART_NUM 3 +#define UART_NUM SOC_UART_NUM // Token signifying that no character is available #define NONE -1 +#if CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF +# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CRLF +#elif CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR +# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CR +#else +# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_LF +#endif + +#if CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF +# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CRLF +#elif CONFIG_NEWLIB_STDIN_LINE_ENDING_CR +# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CR +#else +# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_LF +#endif + // UART write bytes function type typedef void (*tx_func_t)(int, int); // UART read bytes function type @@ -50,17 +66,54 @@ static int uart_rx_char(int fd); static void uart_tx_char_via_driver(int fd, int c); static int uart_rx_char_via_driver(int fd); -// Pointers to UART peripherals -static uart_dev_t* s_uarts[UART_NUM] = {&UART0, &UART1, &UART2}; -// per-UART locks, lazily initialized -static _lock_t s_uart_read_locks[UART_NUM]; -static _lock_t s_uart_write_locks[UART_NUM]; -// One-character buffer used for newline conversion code, per UART -static int s_peek_char[UART_NUM] = { NONE, NONE, NONE }; -// Per-UART non-blocking flag. Note: default implementation does not honor this -// flag, all reads are non-blocking. This option becomes effective if UART -// driver is used. -static bool s_non_blocking[UART_NUM]; +typedef struct { + // Pointers to UART peripherals + uart_dev_t* uart; + // One-character buffer used for newline conversion code, per UART + int peek_char; + // per-UART locks, lazily initialized + _lock_t read_lock; + _lock_t write_lock; + // Per-UART non-blocking flag. Note: default implementation does not honor this + // flag, all reads are non-blocking. This option becomes effective if UART + // driver is used. + bool non_blocking; + // Newline conversion mode when transmitting + esp_line_endings_t tx_mode; + // Newline conversion mode when receiving + esp_line_endings_t rx_mode; + // Functions used to write bytes to UART. Default to "basic" functions. + tx_func_t tx_func; + // Functions used to read bytes from UART. Default to "basic" functions. + rx_func_t rx_func; +} vfs_uart_context_t; + +#define VFS_CTX_DEFAULT_VAL(uart_dev) (vfs_uart_context_t) {\ + .uart = (uart_dev),\ + .peek_char = NONE,\ + .tx_mode = DEFAULT_TX_MODE,\ + .rx_mode = DEFAULT_RX_MODE,\ + .tx_func = uart_tx_char,\ + .rx_func = uart_rx_char,\ +} + +//If the context should be dynamically initialized, remove this structure +//and point s_ctx to allocated data. +static vfs_uart_context_t s_context[UART_NUM] = { + VFS_CTX_DEFAULT_VAL(&UART0), + VFS_CTX_DEFAULT_VAL(&UART1), +#if UART_NUM > 2 + VFS_CTX_DEFAULT_VAL(&UART2), +#endif +}; + +static vfs_uart_context_t* s_ctx[UART_NUM] = { + &s_context[0], + &s_context[1], +#if UART_NUM > 2 + &s_context[2], +#endif +}; /* Lock ensuring that uart_select is used from only one task at the time */ static _lock_t s_one_select_lock; @@ -73,39 +126,9 @@ static fd_set *_readfds_orig = NULL; static fd_set *_writefds_orig = NULL; static fd_set *_errorfds_orig = NULL; -// Newline conversion mode when transmitting -static esp_line_endings_t s_tx_mode = -#if CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF - ESP_LINE_ENDINGS_CRLF; -#elif CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR - ESP_LINE_ENDINGS_CR; -#else - ESP_LINE_ENDINGS_LF; -#endif - -// Newline conversion mode when receiving -static esp_line_endings_t s_rx_mode[UART_NUM] = { [0 ... UART_NUM-1] = -#if CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF - ESP_LINE_ENDINGS_CRLF -#elif CONFIG_NEWLIB_STDIN_LINE_ENDING_CR - ESP_LINE_ENDINGS_CR -#else - ESP_LINE_ENDINGS_LF -#endif -}; static void uart_end_select(); -// Functions used to write bytes to UART. Default to "basic" functions. -static tx_func_t s_uart_tx_func[UART_NUM] = { - &uart_tx_char, &uart_tx_char, &uart_tx_char -}; - -// Functions used to read bytes from UART. Default to "basic" functions. -static rx_func_t s_uart_rx_func[UART_NUM] = { - &uart_rx_char, &uart_rx_char, &uart_rx_char -}; - static int uart_open(const char * path, int flags, int mode) { @@ -124,14 +147,14 @@ static int uart_open(const char * path, int flags, int mode) return fd; } - s_non_blocking[fd] = ((flags & O_NONBLOCK) == O_NONBLOCK); + s_ctx[fd]->non_blocking = ((flags & O_NONBLOCK) == O_NONBLOCK); return fd; } static void uart_tx_char(int fd, int c) { - uart_dev_t* uart = s_uarts[fd]; + uart_dev_t* uart = s_ctx[fd]->uart; while (uart->status.txfifo_cnt >= 127) { ; } @@ -150,7 +173,7 @@ static void uart_tx_char_via_driver(int fd, int c) static int uart_rx_char(int fd) { - uart_dev_t* uart = s_uarts[fd]; + uart_dev_t* uart = s_ctx[fd]->uart; if (uart->status.rxfifo_cnt == 0) { return NONE; } @@ -164,7 +187,7 @@ static int uart_rx_char(int fd) static int uart_rx_char_via_driver(int fd) { uint8_t c; - int timeout = s_non_blocking[fd] ? 0 : portMAX_DELAY; + int timeout = s_ctx[fd]->non_blocking ? 0 : portMAX_DELAY; int n = uart_read_bytes(fd, &c, 1, timeout); if (n <= 0) { return NONE; @@ -180,18 +203,18 @@ static ssize_t uart_write(int fd, const void * data, size_t size) * a dedicated UART lock if two streams (stdout and stderr) point to the * same UART. */ - _lock_acquire_recursive(&s_uart_write_locks[fd]); + _lock_acquire_recursive(&s_ctx[fd]->write_lock); for (size_t i = 0; i < size; i++) { int c = data_c[i]; - if (c == '\n' && s_tx_mode != ESP_LINE_ENDINGS_LF) { - s_uart_tx_func[fd](fd, '\r'); - if (s_tx_mode == ESP_LINE_ENDINGS_CR) { + if (c == '\n' && s_ctx[fd]->tx_mode != ESP_LINE_ENDINGS_LF) { + s_ctx[fd]->tx_func(fd, '\r'); + if (s_ctx[fd]->tx_mode == ESP_LINE_ENDINGS_CR) { continue; } } - s_uart_tx_func[fd](fd, c); + s_ctx[fd]->tx_func(fd, c); } - _lock_release_recursive(&s_uart_write_locks[fd]); + _lock_release_recursive(&s_ctx[fd]->write_lock); return size; } @@ -202,19 +225,19 @@ static ssize_t uart_write(int fd, const void * data, size_t size) static int uart_read_char(int fd) { /* return character from peek buffer, if it is there */ - if (s_peek_char[fd] != NONE) { - int c = s_peek_char[fd]; - s_peek_char[fd] = NONE; + if (s_ctx[fd]->peek_char != NONE) { + int c = s_ctx[fd]->peek_char; + s_ctx[fd]->peek_char = NONE; return c; } - return s_uart_rx_func[fd](fd); + return s_ctx[fd]->rx_func(fd); } /* Push back a character; it will be returned by next call to uart_read_char */ static void uart_return_char(int fd, int c) { - assert(s_peek_char[fd] == NONE); - s_peek_char[fd] = c; + assert(s_ctx[fd]->peek_char == NONE); + s_ctx[fd]->peek_char = c; } static ssize_t uart_read(int fd, void* data, size_t size) @@ -222,13 +245,13 @@ static ssize_t uart_read(int fd, void* data, size_t size) assert(fd >=0 && fd < 3); char *data_c = (char *) data; size_t received = 0; - _lock_acquire_recursive(&s_uart_read_locks[fd]); + _lock_acquire_recursive(&s_ctx[fd]->read_lock); while (received < size) { int c = uart_read_char(fd); if (c == '\r') { - if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CR) { + if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) { c = '\n'; - } else if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CRLF) { + } else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) { /* look ahead */ int c2 = uart_read_char(fd); if (c2 == NONE) { @@ -255,7 +278,7 @@ static ssize_t uart_read(int fd, void* data, size_t size) break; } } - _lock_release_recursive(&s_uart_read_locks[fd]); + _lock_release_recursive(&s_ctx[fd]->read_lock); if (received > 0) { return received; } @@ -281,11 +304,11 @@ static int uart_fcntl(int fd, int cmd, int arg) assert(fd >=0 && fd < 3); int result = 0; if (cmd == F_GETFL) { - if (s_non_blocking[fd]) { + if (s_ctx[fd]->non_blocking) { result |= O_NONBLOCK; } } else if (cmd == F_SETFL) { - s_non_blocking[fd] = (arg & O_NONBLOCK) != 0; + s_ctx[fd]->non_blocking = (arg & O_NONBLOCK) != 0; } else { // unsupported operation result = -1; @@ -318,9 +341,9 @@ static int uart_access(const char *path, int amode) static int uart_fsync(int fd) { assert(fd >= 0 && fd < 3); - _lock_acquire_recursive(&s_uart_write_locks[fd]); + _lock_acquire_recursive(&s_ctx[fd]->write_lock); uart_tx_wait_idle((uint8_t) fd); - _lock_release_recursive(&s_uart_write_locks[fd]); + _lock_release_recursive(&s_ctx[fd]->write_lock); return 0; } @@ -489,11 +512,11 @@ static int uart_tcsetattr(int fd, int optional_actions, const struct termios *p) } if (p->c_iflag & IGNCR) { - s_rx_mode[fd] = ESP_LINE_ENDINGS_CRLF; + s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_CRLF; } else if (p->c_iflag & ICRNL) { - s_rx_mode[fd] = ESP_LINE_ENDINGS_CR; + s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_CR; } else { - s_rx_mode[fd] = ESP_LINE_ENDINGS_LF; + s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_LF; } // output line endings are not supported because there is no alternative in termios for converting LF to CR @@ -672,9 +695,9 @@ static int uart_tcgetattr(int fd, struct termios *p) memset(p, 0, sizeof(struct termios)); - if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CRLF) { + if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) { p->c_iflag |= IGNCR; - } else if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CR) { + } else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) { p->c_iflag |= ICRNL; } @@ -931,31 +954,33 @@ void esp_vfs_dev_uart_register() void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) { for (int i = 0; i < UART_NUM; ++i) { - s_rx_mode[i] = mode; + s_ctx[i]->rx_mode = mode; } } void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) { - s_tx_mode = mode; + for (int i = 0; i < UART_NUM; ++i) { + s_ctx[i]->tx_mode = mode; + } } void esp_vfs_dev_uart_use_nonblocking(int uart_num) { - _lock_acquire_recursive(&s_uart_read_locks[uart_num]); - _lock_acquire_recursive(&s_uart_write_locks[uart_num]); - s_uart_tx_func[uart_num] = uart_tx_char; - s_uart_rx_func[uart_num] = uart_rx_char; - _lock_release_recursive(&s_uart_write_locks[uart_num]); - _lock_release_recursive(&s_uart_read_locks[uart_num]); + _lock_acquire_recursive(&s_ctx[uart_num]->read_lock); + _lock_acquire_recursive(&s_ctx[uart_num]->write_lock); + s_ctx[uart_num]->tx_func = uart_tx_char; + s_ctx[uart_num]->rx_func = uart_rx_char; + _lock_release_recursive(&s_ctx[uart_num]->write_lock); + _lock_release_recursive(&s_ctx[uart_num]->read_lock); } void esp_vfs_dev_uart_use_driver(int uart_num) { - _lock_acquire_recursive(&s_uart_read_locks[uart_num]); - _lock_acquire_recursive(&s_uart_write_locks[uart_num]); - s_uart_tx_func[uart_num] = uart_tx_char_via_driver; - s_uart_rx_func[uart_num] = uart_rx_char_via_driver; - _lock_release_recursive(&s_uart_write_locks[uart_num]); - _lock_release_recursive(&s_uart_read_locks[uart_num]); + _lock_acquire_recursive(&s_ctx[uart_num]->read_lock); + _lock_acquire_recursive(&s_ctx[uart_num]->write_lock); + s_ctx[uart_num]->tx_func = uart_tx_char_via_driver; + s_ctx[uart_num]->rx_func = uart_rx_char_via_driver; + _lock_release_recursive(&s_ctx[uart_num]->write_lock); + _lock_release_recursive(&s_ctx[uart_num]->read_lock); } diff --git a/docs/en/api-reference/peripherals/uart.rst b/docs/en/api-reference/peripherals/uart.rst index cf704bf194..4805ceda7c 100644 --- a/docs/en/api-reference/peripherals/uart.rst +++ b/docs/en/api-reference/peripherals/uart.rst @@ -169,7 +169,7 @@ The API provides a convenient way to handle specific interrupts discussed above * **FIFO space threshold or transmission timeout reached** - the interrupts on TX or Rx FIFO buffer being filled with specific number of characters or on a timeout of sending or receiving data. To use these interrupts, first configure respective threshold values of the buffer length and the timeout by entering them in :cpp:type:`uart_intr_config_t` structure and calling :cpp:func:`uart_intr_config`. Then enable interrupts with functions :cpp:func:`uart_enable_rx_intr` and :cpp:func:`uart_enable_tx_intr`. To disable these interrupts there are corresponding functions :cpp:func:`uart_disable_rx_intr` or :cpp:func:`uart_disable_tx_intr`. -* **Pattern detection** - an interrupt triggered on detecting a 'pattern' of the same character being sent number of times. The functions that allow to configure, enable and disable this interrupt are :cpp:func:`uart_enable_pattern_det_intr` and cpp:func:`uart_disable_pattern_det_intr`. +* **Pattern detection** - an interrupt triggered on detecting a 'pattern' of the same character being sent number of times. The functions that allow to configure, enable and disable this interrupt are :cpp:func:`uart_enable_pattern_det_baud_intr` and cpp:func:`uart_disable_pattern_det_intr`. Macros ^^^^^^ diff --git a/examples/peripherals/uart/nmea0183_parser/main/nmea_parser.c b/examples/peripherals/uart/nmea0183_parser/main/nmea_parser.c index 0dc244afe2..89457e4921 100644 --- a/examples/peripherals/uart/nmea0183_parser/main/nmea_parser.c +++ b/examples/peripherals/uart/nmea0183_parser/main/nmea_parser.c @@ -699,7 +699,7 @@ nmea_parser_handle_t nmea_parser_init(const nmea_parser_config_t *config) goto err_uart_install; } /* Set pattern interrupt, used to detect the end of a line */ - uart_enable_pattern_det_intr(esp_gps->uart_port, '\n', 1, 10000, 10, 10); + uart_enable_pattern_det_baud_intr(esp_gps->uart_port, '\n', 1, 9, 0, 0); /* Set pattern queue size */ uart_pattern_queue_reset(esp_gps->uart_port, config->uart.event_queue_size); uart_flush(esp_gps->uart_port); diff --git a/examples/peripherals/uart/uart_echo_rs485/main/rs485_example.c b/examples/peripherals/uart/uart_echo_rs485/main/rs485_example.c index 22204b73fe..7860966072 100644 --- a/examples/peripherals/uart/uart_echo_rs485/main/rs485_example.c +++ b/examples/peripherals/uart/uart_echo_rs485/main/rs485_example.c @@ -47,7 +47,7 @@ #define PACKET_READ_TICS (100 / portTICK_RATE_MS) #define ECHO_TASK_STACK_SIZE (2048) #define ECHO_TASK_PRIO (10) -#define ECHO_UART_PORT (UART_NUM_2) +#define ECHO_UART_PORT (UART_NUM_MAX - 1) static const char *TAG = "RS485_ECHO_APP"; diff --git a/examples/peripherals/uart/uart_events/main/uart_events_example_main.c b/examples/peripherals/uart/uart_events/main/uart_events_example_main.c index 8c9f545cb1..ea851006b1 100644 --- a/examples/peripherals/uart/uart_events/main/uart_events_example_main.c +++ b/examples/peripherals/uart/uart_events/main/uart_events_example_main.c @@ -140,7 +140,7 @@ void app_main() uart_driver_install(EX_UART_NUM, BUF_SIZE * 2, BUF_SIZE * 2, 20, &uart0_queue, 0); //Set uart pattern detect function. - uart_enable_pattern_det_intr(EX_UART_NUM, '+', PATTERN_CHR_NUM, 10000, 10, 10); + uart_enable_pattern_det_baud_intr(EX_UART_NUM, '+', PATTERN_CHR_NUM, 9, 0, 0); //Reset the pattern queue length to record at most 20 pattern positions. uart_pattern_queue_reset(EX_UART_NUM, 20); diff --git a/examples/protocols/pppos_client/components/modem/src/esp_modem.c b/examples/protocols/pppos_client/components/modem/src/esp_modem.c index 148d67473c..a75fa95865 100644 --- a/examples/protocols/pppos_client/components/modem/src/esp_modem.c +++ b/examples/protocols/pppos_client/components/modem/src/esp_modem.c @@ -28,9 +28,9 @@ #define ESP_MODEM_LINE_BUFFER_SIZE (CONFIG_EXAMPLE_UART_RX_BUFFER_SIZE / 2) #define ESP_MODEM_EVENT_QUEUE_SIZE (16) -#define MIN_PATTERN_INTERVAL (10000) -#define MIN_POST_IDLE (10) -#define MIN_PRE_IDLE (10) +#define MIN_PATTERN_INTERVAL (9) +#define MIN_POST_IDLE (0) +#define MIN_PRE_IDLE (0) /** * @brief Macro defined for error checking @@ -264,12 +264,12 @@ static esp_err_t esp_modem_dte_send_wait(modem_dte_t *dte, const char *data, uin MODEM_CHECK(res >= len, "wait prompt [%s] timeout", err, prompt); MODEM_CHECK(!strncmp(prompt, (const char *)buffer, len), "get wrong prompt: %s", err, buffer); free(buffer); - uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); + uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); return ESP_OK; err: free(buffer); err_write: - uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); + uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); err_param: return ESP_FAIL; } @@ -298,7 +298,7 @@ static esp_err_t esp_modem_dte_change_mode(modem_dte_t *dte, modem_mode_t new_mo case MODEM_COMMAND_MODE: uart_disable_rx_intr(esp_dte->uart_port); uart_flush(esp_dte->uart_port); - uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); + uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); uart_pattern_queue_reset(esp_dte->uart_port, CONFIG_EXAMPLE_UART_PATTERN_QUEUE_SIZE); MODEM_CHECK(dce->set_working_mode(dce, new_mode) == ESP_OK, "set new working mode:%d failed", err, new_mode); break; @@ -392,7 +392,7 @@ modem_dte_t *esp_modem_dte_init(const esp_modem_dte_config_t *config) CONFIG_EXAMPLE_UART_EVENT_QUEUE_SIZE, &(esp_dte->event_queue), 0); MODEM_CHECK(res == ESP_OK, "install uart driver failed", err_uart_config); /* Set pattern interrupt, used to detect the end of a line. */ - res = uart_enable_pattern_det_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); + res = uart_enable_pattern_det_baud_intr(esp_dte->uart_port, '\n', 1, MIN_PATTERN_INTERVAL, MIN_POST_IDLE, MIN_PRE_IDLE); /* Set pattern queue size */ res |= uart_pattern_queue_reset(esp_dte->uart_port, CONFIG_EXAMPLE_UART_PATTERN_QUEUE_SIZE); MODEM_CHECK(res == ESP_OK, "config uart pattern failed", err_uart_pattern);