mirror of
https://github.com/espressif/esp-idf.git
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esp32c6: add soc/ no-gdvs reg files
This commit is contained in:
songruojing
Song Ruo Jing
parent
a00f217341
commit
95c31a7074
160
components/soc/esp32c6/include/soc/clint_reg.h
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160
components/soc/esp32c6/include/soc/clint_reg.h
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*CLINT MINT*/
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#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
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/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_SIP 0xFFFFFFFF
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#define CLINT_CPU_MINT_SIP_M ((CLINT_CPU_MINT_SIP_V)<<(CLINT_CPU_MINT_SIP_S))
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#define CLINT_CPU_MINT_SIP_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_SIP_S 0
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#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4)
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/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
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/*description: .*/
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#define CLINT_MINT_SAMPLING_MODE 0x00000003
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#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
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#define CLINT_MINT_SAMPLING_MODE_V 0x3
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#define CLINT_MINT_SAMPLING_MODE_S 4
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/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3))
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#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3))
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#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1
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#define CLINT_MINT_COUNTER_OVERFLOW_S 3
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/* CLINT_MINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_MINT_TIMERINT_PENDING (BIT(2))
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#define CLINT_MINT_TIMERINT_PENDING_M (BIT(2))
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#define CLINT_MINT_TIMERINT_PENDING_V 0x1
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#define CLINT_MINT_TIMERINT_PENDING_S 2
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/* CLINT_MINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_MINT_TIMERINT_EN (BIT(1))
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#define CLINT_MINT_TIMERINT_EN_M (BIT(1))
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#define CLINT_MINT_TIMERINT_EN_V 0x1
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#define CLINT_MINT_TIMERINT_EN_S 1
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/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_MINT_COUNTER_EN (BIT(0))
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#define CLINT_MINT_COUNTER_EN_M (BIT(0))
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#define CLINT_MINT_COUNTER_EN_V 0x1
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#define CLINT_MINT_COUNTER_EN_S 0
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#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0x8)
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/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
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#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_L_S 0
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#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xC)
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/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
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#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_H_S 0
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#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x10)
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/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
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#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_L_S 0
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#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x14)
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/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
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#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_H_S 0
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/*CLINT UINT*/
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#define CLINT_UINT_SIP_REG (DR_REG_CLINT_U_BASE + 0x0)
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/* CLINT_CPU_UINT_SIP : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: .*/
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#define CLINT_CPU_UINT_SIP 0xFFFFFFFF
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#define CLINT_CPU_UINT_SIP_M ((CLINT_CPU_UINT_SIP_V)<<(CLINT_CPU_UINT_SIP_S))
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#define CLINT_CPU_UINT_SIP_V 0xFFFFFFFF
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#define CLINT_CPU_UINT_SIP_S 0
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#define CLINT_UINT_TIMECTL_REG (DR_REG_CLINT_U_BASE + 0x4)
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/* CLINT_UINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
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/*description: .*/
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#define CLINT_UINT_SAMPLING_MODE 0x00000003
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#define CLINT_UINT_SAMPLING_MODE_M ((CLINT_CPU_UINT_TIMECTL_V)<<(CLINT_CPU_UINT_TIMECTL_S))
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#define CLINT_UINT_SAMPLING_MODE_V 0x3
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#define CLINT_UINT_SAMPLING_MODE_S 4
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/* CLINT_UINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_UINT_COUNTER_OVERFLOW (BIT(3))
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#define CLINT_UINT_COUNTER_OVERFLOW_M (BIT(3))
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#define CLINT_UINT_COUNTER_OVERFLOW_V 0x1
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#define CLINT_UINT_COUNTER_OVERFLOW_S 3
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/* CLINT_UINT_TIMERINT_PENDING : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_UINT_TIMERINT_PENDING (BIT(2))
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#define CLINT_UINT_TIMERINT_PENDING_M (BIT(2))
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#define CLINT_UINT_TIMERINT_PENDING_V 0x1
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#define CLINT_UINT_TIMERINT_PENDING_S 2
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/* CLINT_UINT_TIMERINT_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_UINT_TIMERINT_EN (BIT(1))
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#define CLINT_UINT_TIMERINT_EN_M (BIT(1))
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#define CLINT_UINT_TIMERINT_EN_V 0x1
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#define CLINT_UINT_TIMERINT_EN_S 1
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/* CLINT_UINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_UINT_COUNTER_EN (BIT(0))
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#define CLINT_UINT_COUNTER_EN_M (BIT(0))
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#define CLINT_UINT_COUNTER_EN_V 0x1
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#define CLINT_UINT_COUNTER_EN_S 0
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#define CLINT_UINT_UTIME_L_REG (DR_REG_CLINT_U_BASE + 0x8)
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/* CLINT_CPU_UINT_UTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_UINT_UTIME_L 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIME_L_M ((CLINT_CPU_UINT_UTIME_L_V)<<(CLINT_CPU_UINT_UTIME_L_S))
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#define CLINT_CPU_UINT_UTIME_L_V 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIME_L_S 0
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#define CLINT_UINT_UTIME_H_REG (DR_REG_CLINT_U_BASE + 0xC)
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/* CLINT_CPU_UINT_UTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_UINT_UTIME_H 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIME_H_M ((CLINT_CPU_UINT_UTIME_H_V)<<(CLINT_CPU_UINT_UTIME_H_S))
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#define CLINT_CPU_UINT_UTIME_H_V 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIME_H_S 0
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#define CLINT_UINT_UTIMECMP_L_REG (DR_REG_CLINT_U_BASE + 0x10)
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/* CLINT_CPU_UINT_UTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_UINT_UTIMECMP_L 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIMECMP_L_M ((CLINT_CPU_UINT_UTIMECMP_L_V)<<(CLINT_CPU_UINT_UTIMECMP_L_S))
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#define CLINT_CPU_UINT_UTIMECMP_L_V 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIMECMP_L_S 0
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#define CLINT_UINT_UTIMECMP_H_REG (DR_REG_CLINT_U_BASE + 0x14)
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/* CLINT_CPU_UINT_UTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_UINT_UTIMECMP_H 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIMECMP_H_M ((CLINT_CPU_UINT_UTIMECMP_H_V)<<(CLINT_CPU_UINT_UTIMECMP_H_S))
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#define CLINT_CPU_UINT_UTIMECMP_H_V 0xFFFFFFFF
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#define CLINT_CPU_UINT_UTIMECMP_H_S 0
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#ifdef __cplusplus
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}
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#endif
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632
components/soc/esp32c6/include/soc/plic_reg.h
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632
components/soc/esp32c6/include/soc/plic_reg.h
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DR_REG_PLIC_MX_BASE ( 0x20001000 )
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#define DR_REG_PLIC_UX_BASE ( 0x20001400 )
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#define PLIC_MXINT_CONF_REG ( 0x200013FC )
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#define PLIC_UXINT_CONF_REG ( 0x200017FC )
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#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
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#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4)
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/*PLIC MX*/
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#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0)
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/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF
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#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S))
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#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF
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#define PLIC_CPU_MXINT_ENABLE_S 0
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#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4)
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/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF
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#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S))
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#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF
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#define PLIC_CPU_MXINT_TYPE_S 0
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#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8)
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/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF
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#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S))
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#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF
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#define PLIC_CPU_MXINT_CLEAR_S 0
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#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC)
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/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
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#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
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#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
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#define PLIC_CPU_EIP_STATUS_S 0
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#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10)
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/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT0_PRI 0x0000000F
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#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S))
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#define PLIC_CPU_MXINT0_PRI_V 0xF
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#define PLIC_CPU_MXINT0_PRI_S 0
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#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14)
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/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT1_PRI 0x0000000F
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#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S))
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#define PLIC_CPU_MXINT1_PRI_V 0xF
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#define PLIC_CPU_MXINT1_PRI_S 0
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#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18)
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/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT2_PRI 0x0000000F
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#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S))
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#define PLIC_CPU_MXINT2_PRI_V 0xF
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#define PLIC_CPU_MXINT2_PRI_S 0
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#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C)
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/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT3_PRI 0x0000000F
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#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S))
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#define PLIC_CPU_MXINT3_PRI_V 0xF
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#define PLIC_CPU_MXINT3_PRI_S 0
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#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20)
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/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT4_PRI 0x0000000F
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#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S))
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#define PLIC_CPU_MXINT4_PRI_V 0xF
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#define PLIC_CPU_MXINT4_PRI_S 0
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#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24)
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/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT5_PRI 0x0000000F
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#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S))
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#define PLIC_CPU_MXINT5_PRI_V 0xF
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#define PLIC_CPU_MXINT5_PRI_S 0
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#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28)
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/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT6_PRI 0x0000000F
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#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S))
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#define PLIC_CPU_MXINT6_PRI_V 0xF
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#define PLIC_CPU_MXINT6_PRI_S 0
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#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C)
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/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT7_PRI 0x0000000F
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#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S))
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#define PLIC_CPU_MXINT7_PRI_V 0xF
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#define PLIC_CPU_MXINT7_PRI_S 0
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#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30)
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/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT8_PRI 0x0000000F
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#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S))
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#define PLIC_CPU_MXINT8_PRI_V 0xF
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#define PLIC_CPU_MXINT8_PRI_S 0
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#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34)
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/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
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/*description: .*/
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#define PLIC_CPU_MXINT9_PRI 0x0000000F
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#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S))
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#define PLIC_CPU_MXINT9_PRI_V 0xF
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#define PLIC_CPU_MXINT9_PRI_S 0
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|
||||
#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38)
|
||||
/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT10_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S))
|
||||
#define PLIC_CPU_MXINT10_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT10_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C)
|
||||
/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT11_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S))
|
||||
#define PLIC_CPU_MXINT11_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT11_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40)
|
||||
/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT12_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S))
|
||||
#define PLIC_CPU_MXINT12_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT12_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44)
|
||||
/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT13_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S))
|
||||
#define PLIC_CPU_MXINT13_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT13_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48)
|
||||
/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT14_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S))
|
||||
#define PLIC_CPU_MXINT14_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT14_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C)
|
||||
/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT15_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S))
|
||||
#define PLIC_CPU_MXINT15_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT15_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50)
|
||||
/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT16_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S))
|
||||
#define PLIC_CPU_MXINT16_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT16_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54)
|
||||
/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT17_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S))
|
||||
#define PLIC_CPU_MXINT17_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT17_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58)
|
||||
/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT18_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S))
|
||||
#define PLIC_CPU_MXINT18_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT18_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C)
|
||||
/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT19_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S))
|
||||
#define PLIC_CPU_MXINT19_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT19_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60)
|
||||
/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT20_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S))
|
||||
#define PLIC_CPU_MXINT20_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT20_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64)
|
||||
/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT21_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S))
|
||||
#define PLIC_CPU_MXINT21_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT21_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68)
|
||||
/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT22_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S))
|
||||
#define PLIC_CPU_MXINT22_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT22_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C)
|
||||
/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT23_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S))
|
||||
#define PLIC_CPU_MXINT23_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT23_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70)
|
||||
/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT24_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S))
|
||||
#define PLIC_CPU_MXINT24_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT24_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74)
|
||||
/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT25_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S))
|
||||
#define PLIC_CPU_MXINT25_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT25_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78)
|
||||
/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT26_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S))
|
||||
#define PLIC_CPU_MXINT26_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT26_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C)
|
||||
/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT27_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S))
|
||||
#define PLIC_CPU_MXINT27_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT27_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80)
|
||||
/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT28_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S))
|
||||
#define PLIC_CPU_MXINT28_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT28_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84)
|
||||
/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT29_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S))
|
||||
#define PLIC_CPU_MXINT29_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT29_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88)
|
||||
/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT30_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S))
|
||||
#define PLIC_CPU_MXINT30_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT30_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C)
|
||||
/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT31_PRI 0x0000000F
|
||||
#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S))
|
||||
#define PLIC_CPU_MXINT31_PRI_V 0xF
|
||||
#define PLIC_CPU_MXINT31_PRI_S 0
|
||||
|
||||
#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90)
|
||||
/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_MXINT_THRESH 0x000000FF
|
||||
#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S))
|
||||
#define PLIC_CPU_MXINT_THRESH_V 0xFF
|
||||
#define PLIC_CPU_MXINT_THRESH_S 0
|
||||
|
||||
#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94)
|
||||
/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/
|
||||
#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF
|
||||
#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S))
|
||||
#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF
|
||||
#define PLIC_CPU_MXINT_CLAIM_S 0
|
||||
|
||||
/*PLIC UX*/
|
||||
#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0)
|
||||
/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S))
|
||||
#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_ENABLE_S 0
|
||||
|
||||
#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4)
|
||||
/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S))
|
||||
#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_TYPE_S 0
|
||||
|
||||
#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8)
|
||||
/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S))
|
||||
#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_CLEAR_S 0
|
||||
|
||||
#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC)
|
||||
/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF
|
||||
#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S))
|
||||
#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF
|
||||
#define PLIC_CPU_EIP_STATUS_S 0
|
||||
|
||||
#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10)
|
||||
/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT0_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S))
|
||||
#define PLIC_CPU_UXINT0_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT0_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14)
|
||||
/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT1_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S))
|
||||
#define PLIC_CPU_UXINT1_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT1_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18)
|
||||
/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT2_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S))
|
||||
#define PLIC_CPU_UXINT2_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT2_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C)
|
||||
/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT3_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S))
|
||||
#define PLIC_CPU_UXINT3_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT3_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20)
|
||||
/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT4_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S))
|
||||
#define PLIC_CPU_UXINT4_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT4_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24)
|
||||
/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT5_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S))
|
||||
#define PLIC_CPU_UXINT5_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT5_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28)
|
||||
/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT6_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S))
|
||||
#define PLIC_CPU_UXINT6_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT6_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C)
|
||||
/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT7_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S))
|
||||
#define PLIC_CPU_UXINT7_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT7_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30)
|
||||
/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT8_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S))
|
||||
#define PLIC_CPU_UXINT8_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT8_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34)
|
||||
/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT9_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S))
|
||||
#define PLIC_CPU_UXINT9_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT9_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38)
|
||||
/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT10_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S))
|
||||
#define PLIC_CPU_UXINT10_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT10_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C)
|
||||
/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT11_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S))
|
||||
#define PLIC_CPU_UXINT11_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT11_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40)
|
||||
/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT12_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S))
|
||||
#define PLIC_CPU_UXINT12_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT12_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44)
|
||||
/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT13_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S))
|
||||
#define PLIC_CPU_UXINT13_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT13_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48)
|
||||
/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT14_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S))
|
||||
#define PLIC_CPU_UXINT14_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT14_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C)
|
||||
/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT15_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S))
|
||||
#define PLIC_CPU_UXINT15_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT15_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50)
|
||||
/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT16_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S))
|
||||
#define PLIC_CPU_UXINT16_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT16_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54)
|
||||
/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT17_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S))
|
||||
#define PLIC_CPU_UXINT17_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT17_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58)
|
||||
/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT18_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S))
|
||||
#define PLIC_CPU_UXINT18_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT18_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C)
|
||||
/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT19_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S))
|
||||
#define PLIC_CPU_UXINT19_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT19_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60)
|
||||
/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT20_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S))
|
||||
#define PLIC_CPU_UXINT20_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT20_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64)
|
||||
/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT21_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S))
|
||||
#define PLIC_CPU_UXINT21_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT21_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68)
|
||||
/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT22_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S))
|
||||
#define PLIC_CPU_UXINT22_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT22_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C)
|
||||
/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT23_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S))
|
||||
#define PLIC_CPU_UXINT23_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT23_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70)
|
||||
/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT24_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S))
|
||||
#define PLIC_CPU_UXINT24_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT24_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74)
|
||||
/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT25_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S))
|
||||
#define PLIC_CPU_UXINT25_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT25_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78)
|
||||
/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT26_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S))
|
||||
#define PLIC_CPU_UXINT26_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT26_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C)
|
||||
/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT27_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S))
|
||||
#define PLIC_CPU_UXINT27_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT27_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80)
|
||||
/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT28_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S))
|
||||
#define PLIC_CPU_UXINT28_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT28_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84)
|
||||
/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT29_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S))
|
||||
#define PLIC_CPU_UXINT29_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT29_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88)
|
||||
/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT30_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S))
|
||||
#define PLIC_CPU_UXINT30_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT30_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C)
|
||||
/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT31_PRI 0x0000000F
|
||||
#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S))
|
||||
#define PLIC_CPU_UXINT31_PRI_V 0xF
|
||||
#define PLIC_CPU_UXINT31_PRI_S 0
|
||||
|
||||
#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90)
|
||||
/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT_THRESH 0x000000FF
|
||||
#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S))
|
||||
#define PLIC_CPU_UXINT_THRESH_V 0xFF
|
||||
#define PLIC_CPU_UXINT_THRESH_S 0
|
||||
|
||||
#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94)
|
||||
/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: .*/
|
||||
#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S))
|
||||
#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF
|
||||
#define PLIC_CPU_UXINT_CLAIM_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
175
components/soc/esp32c6/include/soc/regi2c_bbpll.h
Normal file
175
components/soc/esp32c6/include/soc/regi2c_bbpll.h
Normal file
@ -0,0 +1,175 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_bbpll.h
|
||||
* @brief Register definitions for digital PLL (BBPLL)
|
||||
*
|
||||
* This file lists register fields of BBPLL, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* rtc_clk_cpu_freq_set function in rtc_clk.c.
|
||||
*/
|
||||
|
||||
#define I2C_BBPLL 0x66
|
||||
#define I2C_BBPLL_HOSTID 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_DELAY 0
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV 0
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_RSTB 1
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_START 1
|
||||
#define I2C_BBPLL_IR_CAL_START_MSB 6
|
||||
#define I2C_BBPLL_IR_CAL_START_LSB 6
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP 1
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_REF_DIV 2
|
||||
#define I2C_BBPLL_OC_REF_DIV_MSB 3
|
||||
#define I2C_BBPLL_OC_REF_DIV_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DCHGP 2
|
||||
#define I2C_BBPLL_OC_DCHGP_MSB 6
|
||||
#define I2C_BBPLL_OC_DCHGP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_FCAL 2
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DIV_7_0 3
|
||||
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
|
||||
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
|
||||
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC 4
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
|
||||
|
||||
#define I2C_BBPLL_MODE_HF 4
|
||||
#define I2C_BBPLL_MODE_HF_MSB 1
|
||||
#define I2C_BBPLL_MODE_HF_LSB 1
|
||||
|
||||
#define I2C_BBPLL_DIV_ADC 4
|
||||
#define I2C_BBPLL_DIV_ADC_MSB 3
|
||||
#define I2C_BBPLL_DIV_ADC_LSB 2
|
||||
|
||||
#define I2C_BBPLL_DIV_DAC 4
|
||||
#define I2C_BBPLL_DIV_DAC_MSB 4
|
||||
#define I2C_BBPLL_DIV_DAC_LSB 4
|
||||
|
||||
#define I2C_BBPLL_DIV_CPU 4
|
||||
#define I2C_BBPLL_DIV_CPU_MSB 5
|
||||
#define I2C_BBPLL_DIV_CPU_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_VCON 4
|
||||
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
|
||||
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OC_TSCHGP 4
|
||||
#define I2C_BBPLL_OC_TSCHGP_MSB 7
|
||||
#define I2C_BBPLL_OC_TSCHGP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DR1 5
|
||||
#define I2C_BBPLL_OC_DR1_MSB 2
|
||||
#define I2C_BBPLL_OC_DR1_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DR3 5
|
||||
#define I2C_BBPLL_OC_DR3_MSB 6
|
||||
#define I2C_BBPLL_OC_DR3_LSB 4
|
||||
|
||||
#define I2C_BBPLL_EN_USB 5
|
||||
#define I2C_BBPLL_EN_USB_MSB 7
|
||||
#define I2C_BBPLL_EN_USB_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DCUR 6
|
||||
#define I2C_BBPLL_OC_DCUR_MSB 2
|
||||
#define I2C_BBPLL_OC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_INC_CUR 6
|
||||
#define I2C_BBPLL_INC_CUR_MSB 3
|
||||
#define I2C_BBPLL_INC_CUR_LSB 3
|
||||
|
||||
#define I2C_BBPLL_OC_DHREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_DLREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_CAP 8
|
||||
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
|
||||
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_UDF 8
|
||||
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
|
||||
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_OVF 8
|
||||
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
|
||||
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_END 8
|
||||
#define I2C_BBPLL_OR_CAL_END_MSB 6
|
||||
#define I2C_BBPLL_OR_CAL_END_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_LOCK 8
|
||||
#define I2C_BBPLL_OR_LOCK_MSB 7
|
||||
#define I2C_BBPLL_OR_LOCK_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS 9
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_DELAY2 9
|
||||
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
|
||||
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
|
||||
|
||||
#define I2C_BBPLL_BBADC_DVDD 9
|
||||
#define I2C_BBPLL_BBADC_DVDD_MSB 5
|
||||
#define I2C_BBPLL_BBADC_DVDD_LSB 4
|
||||
|
||||
#define I2C_BBPLL_BBADC_DREF 9
|
||||
#define I2C_BBPLL_BBADC_DREF_MSB 7
|
||||
#define I2C_BBPLL_BBADC_DREF_LSB 6
|
||||
|
||||
#define I2C_BBPLL_BBADC_DCUR 10
|
||||
#define I2C_BBPLL_BBADC_DCUR_MSB 1
|
||||
#define I2C_BBPLL_BBADC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
|
||||
|
||||
#define I2C_BBPLL_ENT_PLL 10
|
||||
#define I2C_BBPLL_ENT_PLL_MSB 3
|
||||
#define I2C_BBPLL_ENT_PLL_LSB 3
|
||||
|
||||
#define I2C_BBPLL_DTEST 10
|
||||
#define I2C_BBPLL_DTEST_MSB 5
|
||||
#define I2C_BBPLL_DTEST_LSB 4
|
||||
|
||||
#define I2C_BBPLL_ENT_ADC 10
|
||||
#define I2C_BBPLL_ENT_ADC_MSB 7
|
||||
#define I2C_BBPLL_ENT_ADC_LSB 6
|
||||
22
components/soc/esp32c6/include/soc/regi2c_bias.h
Normal file
22
components/soc/esp32c6/include/soc/regi2c_bias.h
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_bias.h
|
||||
* @brief Register definitions for bias
|
||||
*
|
||||
* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* bootloader_hardware_init function in bootloader_esp32c3.c.
|
||||
*/
|
||||
|
||||
#define I2C_BIAS 0X6A
|
||||
#define I2C_BIAS_HOSTID 0
|
||||
|
||||
#define I2C_BIAS_DREG_1P1_PVT 1
|
||||
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
|
||||
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
|
||||
22
components/soc/esp32c6/include/soc/regi2c_brownout.h
Normal file
22
components/soc/esp32c6/include/soc/regi2c_brownout.h
Normal file
@ -0,0 +1,22 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_brownout.h
|
||||
* @brief Register definitions for brownout detector
|
||||
*
|
||||
* This file lists register fields of the brownout detector, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h.
|
||||
*/
|
||||
|
||||
#define I2C_BOD 0x61
|
||||
#define I2C_BOD_HOSTID 0
|
||||
|
||||
#define I2C_BOD_THRESHOLD 0x5
|
||||
#define I2C_BOD_THRESHOLD_MSB 2
|
||||
#define I2C_BOD_THRESHOLD_LSB 0
|
||||
34
components/soc/esp32c6/include/soc/regi2c_defs.h
Normal file
34
components/soc/esp32c6/include/soc/regi2c_defs.h
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
/* Analog function control register */
|
||||
#define I2C_MST_ANA_CONF0_REG 0x6000E040
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
|
||||
|
||||
#define ANA_CONFIG_REG 0x6000E044
|
||||
#define ANA_CONFIG_S (8)
|
||||
#define ANA_CONFIG_M (0x3FF)
|
||||
|
||||
#define ANA_I2C_SAR_FORCE_PD BIT(18)
|
||||
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
|
||||
|
||||
|
||||
#define ANA_CONFIG2_REG 0x6000E048
|
||||
#define ANA_CONFIG2_M BIT(18)
|
||||
|
||||
#define ANA_I2C_SAR_FORCE_PU BIT(16)
|
||||
|
||||
/**
|
||||
* Restore regi2c analog calibration related configuration registers.
|
||||
* This is a workaround, and is fixed on later chips
|
||||
*/
|
||||
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
|
||||
#define REGI2C_ANA_CALI_BYTE_NUM 8
|
||||
55
components/soc/esp32c6/include/soc/regi2c_lp_bias.h
Normal file
55
components/soc/esp32c6/include/soc/regi2c_lp_bias.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_lp_bias.h
|
||||
* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
|
||||
*
|
||||
* This file lists register fields of low power dbais, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* rtc_init function in rtc_init.c.
|
||||
*/
|
||||
|
||||
#define I2C_ULP 0x61
|
||||
#define I2C_ULP_HOSTID 0
|
||||
|
||||
#define I2C_ULP_IR_RESETB 0
|
||||
#define I2C_ULP_IR_RESETB_MSB 0
|
||||
#define I2C_ULP_IR_RESETB_LSB 0
|
||||
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK 0
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
|
||||
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH 0
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
|
||||
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
|
||||
|
||||
#define I2C_ULP_O_DONE_FLAG 3
|
||||
#define I2C_ULP_O_DONE_FLAG_MSB 0
|
||||
#define I2C_ULP_O_DONE_FLAG_LSB 0
|
||||
|
||||
#define I2C_ULP_BG_O_DONE_FLAG 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
|
||||
|
||||
#define I2C_ULP_OCODE 4
|
||||
#define I2C_ULP_OCODE_MSB 7
|
||||
#define I2C_ULP_OCODE_LSB 0
|
||||
|
||||
#define I2C_ULP_IR_FORCE_CODE 5
|
||||
#define I2C_ULP_IR_FORCE_CODE_MSB 6
|
||||
#define I2C_ULP_IR_FORCE_CODE_LSB 6
|
||||
|
||||
#define I2C_ULP_EXT_CODE 6
|
||||
#define I2C_ULP_EXT_CODE_MSB 7
|
||||
#define I2C_ULP_EXT_CODE_LSB 0
|
||||
79
components/soc/esp32c6/include/soc/regi2c_saradc.h
Normal file
79
components/soc/esp32c6/include/soc/regi2c_saradc.h
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_saradc.h
|
||||
* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
|
||||
*
|
||||
* This file lists register fields of SAR, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* function in adc_ll.h.
|
||||
*/
|
||||
|
||||
#define I2C_SAR_ADC 0X69
|
||||
#define I2C_SAR_ADC_HOSTID 0
|
||||
|
||||
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
|
||||
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
|
||||
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
|
||||
|
||||
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
|
||||
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
|
||||
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
|
||||
|
||||
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
|
||||
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
|
||||
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR1_DREF_ADDR 0x2
|
||||
#define ADC_SAR1_DREF_ADDR_MSB 0x6
|
||||
#define ADC_SAR1_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_SAR2_DREF_ADDR 0x5
|
||||
#define ADC_SAR2_DREF_ADDR_MSB 0x6
|
||||
#define ADC_SAR2_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR 0x7
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
|
||||
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR 0x7
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
|
||||
|
||||
#define ADC_SARADC_ENT_RTC_ADDR 0x7
|
||||
#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
|
||||
#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
|
||||
|
||||
#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
|
||||
#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
|
||||
#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
|
||||
|
||||
#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
|
||||
#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
|
||||
#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
|
||||
|
||||
#define I2C_SARADC_TSENS_DAC 0x6
|
||||
#define I2C_SARADC_TSENS_DAC_MSB 3
|
||||
#define I2C_SARADC_TSENS_DAC_LSB 0
|
||||
Loading…
Reference in New Issue
Block a user