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ethernet: add kconfig help for GPIO0 output mode

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1. add kconfig help for GPIO0 output mode
2. fix wrong LAN8720 register index
This commit is contained in:
suda-morris 2019-09-17 11:45:13 +08:00 committed by bot
parent 1c89a6c4db
commit 89d71691d6
3 changed files with 15 additions and 10 deletions
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14
components/ethernet/eth_phy/phy_lan8720.c
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@ -140,11 +140,11 @@ void phy_lan8720_dump_registers()
ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4)); ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4));
ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5)); ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5));
ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6)); ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6));
ESP_LOGD(TAG, "MCSR 0x%04x", esp_eth_smi_read(0x17)); ESP_LOGD(TAG, "MCSR 0x%04x", esp_eth_smi_read(0x11));
ESP_LOGD(TAG, "SM 0x%04x", esp_eth_smi_read(0x18)); ESP_LOGD(TAG, "SM 0x%04x", esp_eth_smi_read(0x12));
ESP_LOGD(TAG, "SECR 0x%04x", esp_eth_smi_read(0x26)); ESP_LOGD(TAG, "SECR 0x%04x", esp_eth_smi_read(0x1A));
ESP_LOGD(TAG, "CSIR 0x%04x", esp_eth_smi_read(0x27)); ESP_LOGD(TAG, "CSIR 0x%04x", esp_eth_smi_read(0x1B));
ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x29)); ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x1D));
ESP_LOGD(TAG, "IMR 0x%04x", esp_eth_smi_read(0x30)); ESP_LOGD(TAG, "IMR 0x%04x", esp_eth_smi_read(0x1E));
ESP_LOGD(TAG, "PSCSR 0x%04x", esp_eth_smi_read(0x31)); ESP_LOGD(TAG, "PSCSR 0x%04x", esp_eth_smi_read(0x1F));
} }

10
examples/ethernet/ethernet/main/Kconfig.projbuild
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@ -42,9 +42,15 @@ config PHY_CLOCK_GPIO0_IN
Input of 50MHz refclock on GPIO0 Input of 50MHz refclock on GPIO0
config PHY_CLOCK_GPIO0_OUT config PHY_CLOCK_GPIO0_OUT
bool "GPIO0 output" bool "GPIO0 Output(READ HELP)"
help help
Output the internal 50MHz APLL clock on GPIO0 GPIO0 can be set to output a pre-divided PLL clock (test only!).
Enabling this option will configure GPIO0 to output a 50MHz clock.
In fact this clock doesn't have directly relationship with EMAC peripheral.
Sometimes this clock won't work well with your PHY chip. You might need to
add some extra devices after GPIO0 (e.g. inverter).
Note that outputting RMII clock on GPIO0 is an experimental practice.
If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
config PHY_CLOCK_GPIO16_OUT config PHY_CLOCK_GPIO16_OUT
bool "GPIO16 output" bool "GPIO16 output"

1
examples/ethernet/ethernet/sdkconfig.defaults
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@ -1 +0,0 @@