From 89d71691d6e8efcaa518cc7048f38dd78715b960 Mon Sep 17 00:00:00 2001 From: suda-morris <362953310@qq.com> Date: Tue, 17 Sep 2019 11:45:13 +0800 Subject: [PATCH] ethernet: add kconfig help for GPIO0 output mode 1. add kconfig help for GPIO0 output mode 2. fix wrong LAN8720 register index --- components/ethernet/eth_phy/phy_lan8720.c | 14 +++++++------- examples/ethernet/ethernet/main/Kconfig.projbuild | 10 ++++++++-- examples/ethernet/ethernet/sdkconfig.defaults | 1 - 3 files changed, 15 insertions(+), 10 deletions(-) delete mode 100644 examples/ethernet/ethernet/sdkconfig.defaults diff --git a/components/ethernet/eth_phy/phy_lan8720.c b/components/ethernet/eth_phy/phy_lan8720.c index 0914ce1dc7..9af0cd9df1 100644 --- a/components/ethernet/eth_phy/phy_lan8720.c +++ b/components/ethernet/eth_phy/phy_lan8720.c @@ -140,11 +140,11 @@ void phy_lan8720_dump_registers() ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4)); ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5)); ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6)); - ESP_LOGD(TAG, "MCSR 0x%04x", esp_eth_smi_read(0x17)); - ESP_LOGD(TAG, "SM 0x%04x", esp_eth_smi_read(0x18)); - ESP_LOGD(TAG, "SECR 0x%04x", esp_eth_smi_read(0x26)); - ESP_LOGD(TAG, "CSIR 0x%04x", esp_eth_smi_read(0x27)); - ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x29)); - ESP_LOGD(TAG, "IMR 0x%04x", esp_eth_smi_read(0x30)); - ESP_LOGD(TAG, "PSCSR 0x%04x", esp_eth_smi_read(0x31)); + ESP_LOGD(TAG, "MCSR 0x%04x", esp_eth_smi_read(0x11)); + ESP_LOGD(TAG, "SM 0x%04x", esp_eth_smi_read(0x12)); + ESP_LOGD(TAG, "SECR 0x%04x", esp_eth_smi_read(0x1A)); + ESP_LOGD(TAG, "CSIR 0x%04x", esp_eth_smi_read(0x1B)); + ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x1D)); + ESP_LOGD(TAG, "IMR 0x%04x", esp_eth_smi_read(0x1E)); + ESP_LOGD(TAG, "PSCSR 0x%04x", esp_eth_smi_read(0x1F)); } diff --git a/examples/ethernet/ethernet/main/Kconfig.projbuild b/examples/ethernet/ethernet/main/Kconfig.projbuild index b762dc54ac..cb8876d6ec 100644 --- a/examples/ethernet/ethernet/main/Kconfig.projbuild +++ b/examples/ethernet/ethernet/main/Kconfig.projbuild @@ -42,9 +42,15 @@ config PHY_CLOCK_GPIO0_IN Input of 50MHz refclock on GPIO0 config PHY_CLOCK_GPIO0_OUT - bool "GPIO0 output" + bool "GPIO0 Output(READ HELP)" help - Output the internal 50MHz APLL clock on GPIO0 + GPIO0 can be set to output a pre-divided PLL clock (test only!). + Enabling this option will configure GPIO0 to output a 50MHz clock. + In fact this clock doesn't have directly relationship with EMAC peripheral. + Sometimes this clock won't work well with your PHY chip. You might need to + add some extra devices after GPIO0 (e.g. inverter). + Note that outputting RMII clock on GPIO0 is an experimental practice. + If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability. config PHY_CLOCK_GPIO16_OUT bool "GPIO16 output" diff --git a/examples/ethernet/ethernet/sdkconfig.defaults b/examples/ethernet/ethernet/sdkconfig.defaults deleted file mode 100644 index 8b13789179..0000000000 --- a/examples/ethernet/ethernet/sdkconfig.defaults +++ /dev/null @@ -1 +0,0 @@ -