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Merge branch 'feature/enable_aes_sha_support_for_c5_mp' into 'master'

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feat: enabled aes and sha support for esp32c5 mp version

Closes IDF-8627 and IDF-8624

See merge request espressif/esp-idf!30741
This commit is contained in:
Aditya Patwardhan 2024-05-27 18:56:56 +08:00
commit 8541242860
2 changed files with 65 additions and 13 deletions
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52
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
View File

@ -67,10 +67,18 @@ config SOC_SYSTIMER_SUPPORTED
bool
default y
config SOC_AES_SUPPORTED
bool
default y
config SOC_MPI_SUPPORTED
bool
default y
config SOC_SHA_SUPPORTED
bool
default y
config SOC_RSA_SUPPORTED
bool
default y
@ -99,6 +107,22 @@ config SOC_XTAL_SUPPORT_48M
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
@ -411,6 +435,34 @@ config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

26
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@ -45,9 +45,9 @@
#define SOC_LEDC_SUPPORTED 1
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627
#define SOC_AES_SUPPORTED 1
#define SOC_MPI_SUPPORTED 1
// #define SOC_SHA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8624
#define SOC_SHA_SUPPORTED 1
#define SOC_RSA_SUPPORTED 1
// #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616
// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619
@ -80,13 +80,13 @@
#define SOC_XTAL_SUPPORT_48M 1
/*-------------------------- AES CAPS -----------------------------------------*/
// #define SOC_AES_SUPPORT_DMA (1)
#define SOC_AES_SUPPORT_DMA (1)
/* Has a centralized DMA, which is shared with all peripherals */
// #define SOC_AES_GDMA (1)
#define SOC_AES_GDMA (1)
// #define SOC_AES_SUPPORT_AES_128 (1)
// #define SOC_AES_SUPPORT_AES_256 (1)
#define SOC_AES_SUPPORT_AES_128 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
@ -361,19 +361,19 @@
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
// #define SOC_SHA_SUPPORT_DMA (1)
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
// #define SOC_SHA_SUPPORT_RESUME (1)
#define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
// #define SOC_SHA_GDMA (1)
#define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
// #define SOC_SHA_SUPPORT_SHA1 (1)
// #define SOC_SHA_SUPPORT_SHA224 (1)
// #define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*--------------------------- ECDSA CAPS ---------------------------------------*/
// #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)