Merge branch 'feature/esp32c5_ledc_support' into 'master'

feat(ledc): support ledc on esp32c5

Closes IDF-8684

See merge request espressif/esp-idf!30836

components/esp_driver_ledc/src/ledc.c

@@ -571,8 +571,10 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
         ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk);
 
         /* keep ESP_PD_DOMAIN_RC_FAST on during light sleep */
+#if SOC_LIGHT_SLEEP_SUPPORTED
         extern void esp_sleep_periph_use_8m(bool use_or_not);
         esp_sleep_periph_use_8m(glb_clk == LEDC_SLOW_CLK_RC_FAST);
+#endif
     }
 
     /* The divisor is correct, we can write in the hardware. */
@@ -672,7 +674,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
     if (!new_speed_mode_ctx_created && !p_ledc_obj[speed_mode]) {
         return ESP_ERR_NO_MEM;
     }
-#if !(CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4)
+#if !(CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5)
     // On such targets, the default ledc core(global) clock does not connect to any clock source
     // Set channel configurations and update bits before core clock is on could lead to error
     // Therefore, we should connect the core clock to a real clock source to make it on before any ledc register operation

components/hal/esp32c5/include/hal/ledc_ll.h

@@ -0,0 +1,552 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for LEDC register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include "hal/assert.h"
+#include "hal/ledc_types.h"
+#include "soc/ledc_struct.h"
+#include "soc/ledc_reg.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LEDC_LL_GET_HW()           &LEDC
+
+#define LEDC_LL_DUTY_NUM_MAX       (LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)
+#define LEDC_LL_DUTY_CYCLE_MAX     (LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)
+#define LEDC_LL_DUTY_SCALE_MAX     (LEDC_CH0_GAMMA_RANGE0_SCALE_V)
+#define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_CH0_V)
+#define LEDC_LL_FRACTIONAL_BITS    (8)
+#define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
+#define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+
+/**
+ * @brief Enable peripheral register clock
+ *
+ * @param enable    Enable/Disable
+ */
+static inline void ledc_ll_enable_bus_clock(bool enable) {
+    PCR.ledc_conf.ledc_clk_en = enable;
+}
+
+/**
+ * @brief Reset whole peripheral register to init value defined by HW design
+ */
+static inline void ledc_ll_enable_reset_reg(bool enable) {
+    PCR.ledc_conf.ledc_rst_en = enable;
+}
+
+/**
+ * @brief Enable LEDC function clock
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param en True to enable, false to disable
+ *
+ * @return None
+ */
+static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
+    (void)hw;
+    PCR.ledc_sclk_conf.ledc_sclk_en = en;
+}
+
+/**
+ * @brief Set LEDC low speed timer clock
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param slow_clk_sel LEDC low speed timer clock source
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel)
+{
+    (void) hw;
+    uint32_t clk_sel_val = 3;
+    switch (slow_clk_sel)
+    {
+    case LEDC_SLOW_CLK_XTAL:
+        clk_sel_val = 0;
+        break;
+    case LEDC_SLOW_CLK_RC_FAST:
+        clk_sel_val = 1;
+        break;
+    case LEDC_SLOW_CLK_PLL_DIV:
+        clk_sel_val = 2;
+        break;
+    default:
+        abort();
+    }
+
+    PCR.ledc_sclk_conf.ledc_sclk_sel = clk_sel_val;
+}
+
+/**
+ * @brief Get LEDC low speed timer clock
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param slow_clk_sel LEDC low speed timer clock source
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t *slow_clk_sel)
+{
+    (void) hw;
+    switch (PCR.ledc_sclk_conf.ledc_sclk_sel)
+    {
+    case 0:
+        *slow_clk_sel = LEDC_SLOW_CLK_XTAL;
+        break;
+    case 1:
+        *slow_clk_sel = LEDC_SLOW_CLK_RC_FAST;
+        break;
+    case 2:
+        *slow_clk_sel = LEDC_SLOW_CLK_PLL_DIV;
+        break;
+    default:
+        abort();
+    }
+}
+
+/**
+ * @brief Update LEDC low speed timer
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ *
+ * @return None
+ */
+static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
+{
+    hw->timer_group[speed_mode].timer[timer_sel].conf.para_up = 1;
+    // Here, we don't wait for the bit gets cleared since it can take quite long depends on the pwm frequency
+}
+
+/**
+ * @brief Reset LEDC timer
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ *
+ * @return None
+ */
+static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
+{
+    hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1;
+    hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0;
+}
+
+/**
+ * @brief Pause LEDC timer
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ *
+ * @return None
+ */
+static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
+{
+    hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1;
+}
+
+/**
+ * @brief Resume LEDC timer
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ *
+ * @return None
+ */
+static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel)
+{
+    hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 0;
+}
+
+/**
+ * @brief Set LEDC timer clock divider
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider)
+{
+    hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div = clock_divider;
+}
+
+/**
+ * @brief Get LEDC timer clock divider
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider)
+{
+    *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div;
+}
+
+/**
+ * @brief Get LEDC timer clock source
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ * @param clk_src Pointer to accept the timer clock source
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
+{
+    // The target has no timer-specific clock source option
+    HAL_ASSERT(hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 0);
+    *clk_src = LEDC_SCLK;
+}
+
+/**
+ * @brief Set LEDC duty resolution
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ * @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)]
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution)
+{
+    hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution;
+}
+
+/**
+ * @brief Get LEDC duty resolution
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ * @param duty_resolution Pointer to accept the resolution of duty setting in number of bits.
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution)
+{
+    *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res;
+}
+
+/**
+ * @brief Get LEDC max duty
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ * @param max_duty Pointer to accept the max duty
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *max_duty)
+{
+    *max_duty = (1 << (hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res));
+}
+
+/**
+ * @brief Update channel configure when select low speed mode
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ *
+ * @return None
+ */
+static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
+{
+    hw->channel_group[speed_mode].channel[channel_num].conf0.para_up = 1;
+}
+
+/**
+ * @brief Set LEDC hpoint value
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param hpoint_val LEDC hpoint value(max: 0xfffff)
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t hpoint_val)
+{
+    hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val;
+}
+
+/**
+ * @brief Get LEDC hpoint value
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff)
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val)
+{
+    *hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint;
+}
+
+/**
+ * @brief Set LEDC the integer part of duty value
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)]
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val)
+{
+    hw->channel_group[speed_mode].channel[channel_num].duty_init.duty = duty_val << 4;
+}
+
+/**
+ * @brief Get LEDC duty value
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param duty_val Pointer to accept the LEDC duty value
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val)
+{
+    *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty >> 4);
+}
+
+/**
+ * @brief Function to set fade parameters all-in-one
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param range Gamma fade range index, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
+ * @param dir LEDC duty change direction, increase or decrease
+ * @param cycle The duty cycles
+ * @param scale The step scale
+ * @param step The number of increased or decreased times
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step)
+{
+    ledc_channel_gamma_fade_param_t range_param = {
+        .duty_inc = dir,
+        .duty_cycle = cycle,
+        .scale = scale,
+        .duty_num = step,
+    };
+    LEDC_GAMMA_RAM.channel[channel_num].entry[range].val = range_param.val;
+}
+
+/**
+ * @brief Set the total number of ranges in one fading
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param range_num Total number of ranges (1 - SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX) of the fading configured
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num)
+{
+    hw->channel_gamma_conf_group[speed_mode].gamma_conf[channel_num].gamma_entry_num = range_num;
+}
+
+/**
+ * @brief Get the total number of ranges in one fading
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param range_num Pointer to accept fade range number
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num)
+{
+    *range_num = hw->channel_gamma_conf_group[speed_mode].gamma_conf[channel_num].gamma_entry_num;
+}
+
+/**
+ * @brief Get fade configurations in gamma_rd register
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param range Gamma fade range index to get, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
+ * @param dir Pointer to accept fade direction value
+ * @param cycle Pointer to accept fade cycle value
+ * @param scale Pointer to accept fade scale value
+ * @param step Pointer to accept fade step value
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
+{
+    ledc_channel_gamma_fade_param_t range_param = {
+        .val = LEDC_GAMMA_RAM.channel[channel_num].entry[range].val,
+    };
+
+    *dir = range_param.duty_inc;
+    *cycle = range_param.duty_cycle;
+    *scale = range_param.scale;
+    *step = range_param.duty_num;
+}
+
+/**
+ * @brief Set the output enable
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param sig_out_en The output enable status
+ *
+ * @return None
+ */
+__attribute__((always_inline))
+static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en)
+{
+    hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en;
+}
+
+/**
+ * @brief Set the duty start
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param duty_start The duty start
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool duty_start)
+{
+    hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start;
+}
+
+/**
+ * @brief Set output idle level
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param idle_level The output idle level
+ *
+ * @return None
+ */
+__attribute__((always_inline))
+static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t idle_level)
+{
+    hw->channel_group[speed_mode].channel[channel_num].conf0.idle_lv = idle_level & 0x1;
+}
+
+/**
+ * @brief Set fade end interrupt enable
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param fade_end_intr_en The fade end interrupt enable status
+ *
+ * @return None
+ */
+static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool fade_end_intr_en)
+{
+    uint32_t value = hw->int_ena.val;
+    uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
+    hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num))));
+}
+
+/**
+ * @brief Get fade end interrupt status
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param intr_status The fade end interrupt status
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status)
+{
+    uint32_t value = hw->int_st.val;
+    uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
+    *intr_status = (value >> int_en_base) & 0xff;
+}
+
+/**
+ * @brief Clear fade end interrupt status
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ *
+ * @return None
+ */
+static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num)
+{
+    uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S;
+    hw->int_clr.val = BIT(int_en_base + channel_num);
+}
+
+/**
+ * @brief Set timer index of the specified channel
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
+ *
+ * @return None
+ */
+static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t timer_sel)
+{
+    hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel = timer_sel;
+}
+
+/**
+ * @brief Get timer index of the specified channel
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param speed_mode LEDC speed_mode, low-speed mode only
+ * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
+ * @param timer_sel Pointer to accept the LEDC timer index
+ *
+ * @return None
+ */
+static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel)
+{
+    *timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in

@@ -59,6 +59,10 @@ config SOC_GPSPI_SUPPORTED
     bool
     default y
 
+config SOC_LEDC_SUPPORTED
+    bool
+    default y
+
 config SOC_SYSTIMER_SUPPORTED
     bool
     default y
@@ -287,6 +291,26 @@ config SOC_LEDC_CHANNEL_NUM
     int
     default 6
 
+config SOC_LEDC_TIMER_BIT_WIDTH
+    int
+    default 20
+
+config SOC_LEDC_SUPPORT_FADE_STOP
+    bool
+    default y
+
+config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
+    bool
+    default y
+
+config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
+    int
+    default 16
+
+config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
+    int
+    default 10
+
 config SOC_MMU_PERIPH_NUM
     int
     default 1
@@ -571,10 +595,6 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
     bool
     default y
 
-config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
-    bool
-    default y
-
 config SOC_MODEM_CLOCK_IS_INDEPENDENT
     bool
     default y

components/soc/esp32c5/mp/include/soc/clk_tree_defs.h

@@ -473,7 +473,7 @@ typedef enum {  // TODO: [ESP32C5] IDF-8650 (inherit from C6)
 /**
  * @brief Type of LEDC clock source, reserved for the legacy LEDC driver
  */
-typedef enum {  // TODO: [ESP32C5] IDF-8684 (inherit from C6)
+typedef enum {
     LEDC_AUTO_CLK = 0,                              /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
     LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M clock as the source clock */
     LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */

components/soc/esp32c5/mp/include/soc/ledc_struct.h

@@ -20,38 +20,38 @@ typedef union {
          *  Configures which timer is channel n selected.\\0: Select timer0\\1: Select
          *  timer1\\2: Select timer2\\3: Select timer3
          */
-        uint32_t timer_sel_chn:2;
+        uint32_t timer_sel:2;
         /** sig_out_en_chn : R/W; bitpos: [2]; default: 0;
          *  Configures whether or not to enable signal output on channel n.\\0: Signal output
          *  disable\\1: Signal output enable
          */
-        uint32_t sig_out_en_chn:1;
+        uint32_t sig_out_en:1;
         /** idle_lv_chn : R/W; bitpos: [3]; default: 0;
          *  Configures the output value when channel n is inactive. Valid only when
          *  LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high
          */
-        uint32_t idle_lv_chn:1;
+        uint32_t idle_lv:1;
         /** para_up_chn : WT; bitpos: [4]; default: 0;
          *  Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
          *  LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_OVF_CNT_EN_CHn fields and duty cycle
          *  range configuration for channel n, and will be automatically cleared by
          *  hardware.\\0: Invalid. No effect\\1: Update
          */
-        uint32_t para_up_chn:1;
+        uint32_t para_up:1;
         /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0;
          *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt
          *  will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times.
          */
-        uint32_t ovf_num_chn:10;
+        uint32_t ovf_num:10;
         /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0;
          *  Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable
          */
-        uint32_t ovf_cnt_en_chn:1;
+        uint32_t ovf_cnt_en:1;
         /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0;
          *  Configures whether or not to reset the  ovf_cnt of channel n.\\0: Invalid. No
          *  effect\\1: Reset the ovf_cnt
          */
-        uint32_t ovf_cnt_reset_chn:1;
+        uint32_t ovf_cnt_reset:1;
         uint32_t reserved_17:15;
     };
     uint32_t val;
@@ -66,7 +66,7 @@ typedef union {
          *  Configures high point of signal output on channel n. The output value changes to
          *  high when the selected timers has reached the value specified by this register.
          */
-        uint32_t hpoint_chn:20;
+        uint32_t hpoint:20;
         uint32_t reserved_20:12;
     };
     uint32_t val;
@@ -80,7 +80,7 @@ typedef union {
         /** duty_chn : R/W; bitpos: [24:0]; default: 0;
          *  Configures the duty of signal output on channel n.
          */
-        uint32_t duty_chn:25;
+        uint32_t duty:25;
         uint32_t reserved_25:7;
     };
     uint32_t val;
@@ -96,7 +96,7 @@ typedef union {
          *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
          *  effect\\1: Take effect
          */
-        uint32_t duty_start_chn:1;
+        uint32_t duty_start:1;
     };
     uint32_t val;
 } ledc_chn_conf1_reg_t;
@@ -109,30 +109,30 @@ typedef union {
         /** timern_duty_res : R/W; bitpos: [4:0]; default: 0;
          *  Configures the bit width of the counter in timer n. Valid values are 1 to 20.
          */
-        uint32_t timern_duty_res:5;
+        uint32_t duty_res:5;
         /** clk_div_timern : R/W; bitpos: [22:5]; default: 0;
          *  Configures the divisor for the divider in timer n.The least significant eight bits
          *  represent the fractional part.
          */
-        uint32_t clk_div_timern:18;
+        uint32_t clk_div:18;
         /** timern_pause : R/W; bitpos: [23]; default: 0;
          *  Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause
          */
-        uint32_t timern_pause:1;
+        uint32_t pause:1;
         /** timern_rst : R/W; bitpos: [24]; default: 1;
          *  Configures whether or not to reset timer n. The counter will show 0 after
          *  reset.\\0: Not reset\\1: Reset
          */
-        uint32_t timern_rst:1;
+        uint32_t rst:1;
         /** tick_sel_timern : R/W; bitpos: [25]; default: 0;
          *  Configures which clock is timer n selected. Unused.
          */
-        uint32_t tick_sel_timern:1;
+        uint32_t tick_sel:1;
         /** timern_para_up : WT; bitpos: [26]; default: 0;
          *  Configures whether or not to update LEDC_CLK_DIV_TIMERn and
          *  LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update
          */
-        uint32_t timern_para_up:1;
+        uint32_t para_up:1;
         uint32_t reserved_27:5;
     };
     uint32_t val;
@@ -146,17 +146,17 @@ typedef union {
         /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
          *  Configures the number of duty cycle fading rages for LEDC chn.
          */
-        uint32_t chn_gamma_entry_num:5;
+        uint32_t gamma_entry_num:5;
         /** chn_gamma_pause : WT; bitpos: [5]; default: 0;
          *  Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No
          *  effect\\1: Pause
          */
-        uint32_t chn_gamma_pause:1;
+        uint32_t gamma_pause:1;
         /** chn_gamma_resume : WT; bitpos: [6]; default: 0;
          *  Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No
          *  effect\\1: Resume
          */
-        uint32_t chn_gamma_resume:1;
+        uint32_t gamma_resume:1;
         uint32_t reserved_7:25;
     };
     uint32_t val;
@@ -633,7 +633,7 @@ typedef union {
         /** duty_chn_r : RO; bitpos: [24:0]; default: 0;
          *  Represents the current duty of output signal on channel n.
          */
-        uint32_t duty_chn_r:25;
+        uint32_t duty:25;
         uint32_t reserved_25:7;
     };
     uint32_t val;
@@ -1020,9 +1020,9 @@ typedef union {
 typedef struct {
     volatile ledc_chn_conf0_reg_t conf0;
     volatile ledc_chn_hpoint_reg_t hpoint;
-    volatile ledc_chn_duty_reg_t duty;
+    volatile ledc_chn_duty_reg_t duty_init;
     volatile ledc_chn_conf1_reg_t conf1;
-    volatile ledc_chn_duty_r_reg_t duty_rd;
+    volatile ledc_chn_duty_r_reg_t duty_r;
 } ledc_chn_reg_t;
 
 typedef struct {
@@ -1072,10 +1072,36 @@ typedef struct {
     volatile ledc_date_reg_t date;
 } ledc_dev_t;
 
+
+/**
+ * Gamma fade param group ram type
+ */
+typedef union {
+    struct {
+        uint32_t duty_inc       :1;
+        uint32_t duty_cycle     :10;
+        uint32_t scale          :10;
+        uint32_t duty_num       :10;
+        uint32_t reserved       :1;
+    };
+    uint32_t val;
+} ledc_channel_gamma_fade_param_t;
+
+typedef struct {
+    volatile ledc_channel_gamma_fade_param_t entry[16];
+} ledc_gamma_channel_t;
+
+typedef struct {
+    volatile ledc_gamma_channel_t channel[6];
+} ledc_gamma_ram_t;
+
+
 extern ledc_dev_t LEDC;
+extern ledc_gamma_ram_t LEDC_GAMMA_RAM;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure");
+_Static_assert(sizeof(ledc_gamma_ram_t) == 0x180, "Invalid size of ledc_gamma_ram_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32c5/mp/include/soc/soc_caps.h

@@ -42,7 +42,7 @@
 #define SOC_RMT_SUPPORTED               1
 // #define SOC_SDM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8687
 #define SOC_GPSPI_SUPPORTED             1
-// #define SOC_LEDC_SUPPORTED              1  // TODO: [ESP32C5] IDF-8684
+#define SOC_LEDC_SUPPORTED              1
 // #define SOC_I2C_SUPPORTED               1  // TODO: [ESP32C5] IDF-8694, IDF-8696
 #define SOC_SYSTIMER_SUPPORTED          1     // TODO: [ESP32C5] IDF-8707
 // #define SOC_AES_SUPPORTED               1  // TODO: [ESP32C5] IDF-8627
@@ -274,15 +274,14 @@
 #define SOC_I2S_TDM_FULL_DATA_WIDTH (1)  /*!< No limitation to data bit width when using multiple slots */
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
-// TODO: [ESP32C5] 8684
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
 #define SOC_LEDC_CHANNEL_NUM                (6)
-// #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
-// #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
-// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
-// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
-// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_TIMER_BIT_WIDTH            (20)
+#define SOC_LEDC_SUPPORT_FADE_STOP          (1)
+#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
+#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
+#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
 
 /*-------------------------- MMU CAPS ----------------------------------------*/
 // TODO: [ESP32C5] IDF-8658
@@ -540,7 +539,7 @@
 // #define SOC_PM_PAU_LINK_NUM             (4)
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
-#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
+// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1) // TODO: IDF-8642
 #define SOC_MODEM_CLOCK_IS_INDEPENDENT            (1)
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */

components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld

@@ -13,6 +13,7 @@ PROVIDE ( UHCI                = 0x60005000 );
 PROVIDE ( RMT                 = 0x60006000 );
 PROVIDE ( RMTMEM              = 0x60006400 );
 PROVIDE ( LEDC                = 0x60007000 );
+PROVIDE ( LEDC_GAMMA_RAM      = 0x60007400 );
 PROVIDE ( TIMERG0             = 0x60008000 );
 PROVIDE ( TIMERG1             = 0x60009000 );
 PROVIDE ( SYSTIMER            = 0x6000A000 );

components/soc/esp32c5/mp/ledc_periph.c

@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/ledc_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every LEDC peripheral: GPIO signals
+*/
+const ledc_signal_conn_t ledc_periph_signal[1] = {
+    {
+        .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
+    }
+};

components/soc/esp32p4/include/soc/ledc_struct.h

@@ -1237,7 +1237,7 @@ typedef union {
 } ledc_channel_gamma_fade_param_t;
 
 typedef struct {
-    ledc_channel_gamma_fade_param_t entry[16];
+    volatile ledc_channel_gamma_fade_param_t entry[16];
 } ledc_gamma_channel_t;
 
 typedef struct {

docs/docs_not_updated/esp32c5.txt

@@ -116,7 +116,6 @@ api-reference/peripherals/touch_element.rst
 api-reference/peripherals/lcd.rst
 api-reference/peripherals/mcpwm.rst
 api-reference/peripherals/ana_cmpr.rst
-api-reference/peripherals/ledc.rst
 api-reference/peripherals/temp_sensor.rst
 api-reference/peripherals/spi_features.rst
 api-reference/peripherals/clk_tree.rst

docs/en/api-reference/peripherals/ledc.rst

@@ -1,7 +1,7 @@
 LED Control (LEDC)
 ==================
 
-{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16"}
+{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16", esp32c5="16"}
 
 :link_to_translation:`zh_CN:[中文]`
 
@@ -147,7 +147,26 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - ~ 20 MHz
          - Dynamic Frequency Scaling compatible, Light sleep compatible
        * - XTAL_CLK
-         - 40 MHz
+         - 40/26 MHz
+         - Dynamic Frequency Scaling compatible
+
+.. only:: esp32c5
+
+    .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks
+       :widths: 15 15 30
+       :header-rows: 1
+
+       * - Clock name
+         - Clock freq
+         - Clock capabilities
+       * - PLL_80M_CLK
+         - 80 MHz
+         - /
+       * - RC_FAST_CLK
+         - ~ 17.5 MHz
+         - Dynamic Frequency Scaling compatible, Light sleep compatible
+       * - XTAL_CLK
+         - 48/40 MHz
          - Dynamic Frequency Scaling compatible
 
 .. only:: esp32c6

docs/zh_CN/api-reference/peripherals/ledc.rst

@@ -1,7 +1,7 @@
 LED PWM 控制器
 ==============
 
-{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16"}
+{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16", esp32c5="16"}
 
 :link_to_translation:`en:[English]`
 
@@ -147,7 +147,26 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实
          - ~ 20 MHz
          - 支持动态调频 (DFS) 功能，支持 Light-sleep 模式
        * - XTAL_CLK
-         - 40 MHz
+         - 40/26 MHz
+         - 支持动态调频 (DFS) 功能
+
+.. only:: esp32c5
+
+    .. list-table:: {IDF_TARGET_NAME} LEDC 时钟源特性
+       :widths: 10 10 30
+       :header-rows: 1
+
+       * - 时钟名称
+         - 时钟频率
+         - 时钟功能
+       * - PLL_80M_CLK
+         - 80 MHz
+         - /
+       * - RC_FAST_CLK
+         - ~ 17.5 MHz
+         - 支持动态调频 (DFS) 功能，支持 Light-sleep 模式
+       * - XTAL_CLK
+         - 48/40 MHz
          - 支持动态调频 (DFS) 功能
 
 .. only:: esp32c6