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refactor(cache): improved cache test with set cache dirty first
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@ -57,6 +57,12 @@ TEST_CASE("test cache msync short enough to be in an ISR", "[cache]")
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uint32_t sync_time_us = 200;
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RECORD_TIME_PREPARE();
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#if CONFIG_SPIRAM
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//prepare the cache
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TEST_ESP_OK(test_set_buffer_dirty(TEST_SYNC_START, TEST_SYNC_SIZE));
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#endif
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//do once to record time
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RECORD_TIME_START();
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TEST_ESP_OK(esp_cache_msync((void *)TEST_SYNC_START, TEST_SYNC_SIZE, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE | ESP_CACHE_MSYNC_FLAG_UNALIGNED));
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RECORD_TIME_END(sync_time);
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@ -72,11 +78,17 @@ TEST_CASE("test cache msync short enough to be in an ISR", "[cache]")
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};
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TEST_ESP_OK(esp_timer_create(&oneshot_timer_args, &timer));
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#if CONFIG_SPIRAM
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//prepare the cache
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TEST_ESP_OK(test_set_buffer_dirty(TEST_SYNC_START, TEST_SYNC_SIZE));
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#endif
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//start timer
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uint32_t period = sync_time_us * 2;
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TEST_ESP_OK(esp_timer_start_periodic(timer, period));
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//1ms
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esp_rom_delay_us(1000);
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//10ms
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esp_rom_delay_us(10 * 1000);
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TEST_ESP_OK(esp_timer_stop(timer));
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ESP_LOGI(TAG, "Finish");
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@ -100,6 +112,10 @@ TEST_CASE("test cache msync work with Flash operation when XIP from PSRAM", "[ca
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uint32_t sync_time = 0;
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RECORD_TIME_PREPARE();
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//prepare the cache
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TEST_ESP_OK(test_set_buffer_dirty(TEST_SYNC_START, TEST_SYNC_SIZE));
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//do once to record time
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RECORD_TIME_START();
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TEST_ESP_OK(esp_cache_msync((void *)TEST_SYNC_START, TEST_SYNC_SIZE, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_INVALIDATE));
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RECORD_TIME_END(sync_time);
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@ -121,9 +137,14 @@ TEST_CASE("test cache msync work with Flash operation when XIP from PSRAM", "[ca
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};
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TEST_ESP_OK(esp_timer_create(&oneshot_timer_args, &timer));
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//prepare the cache
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TEST_ESP_OK(test_set_buffer_dirty(TEST_SYNC_START, TEST_SYNC_SIZE));
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//start timer
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uint32_t period = sync_time_us * 2;
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TEST_ESP_OK(esp_timer_start_periodic(timer, period));
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//erase
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ESP_ERROR_CHECK(esp_flash_erase_region(part->flash_chip, part->address, part->size));
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TEST_ESP_OK(esp_timer_stop(timer));
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