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bugfix: fix esp32s3 psram access failed when dfs is enabled
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@ -550,8 +550,10 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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rtc_clk_cpu_freq_set_config(&cpu_freq_config);
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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if (cpu_freq_config.source == RTC_CPU_FREQ_SRC_PLL) {
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// Restore mspi clock freq
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spi_timing_change_speed_mode_cache_safe(false);
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}
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#endif
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if (!deep_sleep) {
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@ -1,4 +1,4 @@
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idf_component_register(SRCS "pm_locks.c" "pm_trace.c" "pm_impl.c"
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INCLUDE_DIRS include
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PRIV_REQUIRES esp_system driver
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PRIV_REQUIRES esp_system driver spi_flash
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LDFRAGMENTS linker.lf)
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@ -17,6 +17,7 @@
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#include "esp_private/crosscore_int.h"
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#include "soc/rtc.h"
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#include "soc/soc_caps.h"
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#include "hal/cpu_hal.h"
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#include "hal/uart_ll.h"
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#include "hal/uart_types.h"
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@ -32,6 +33,10 @@
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#include "esp_private/pm_trace.h"
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#include "esp_private/esp_timer_private.h"
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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#include "esp_private/spi_flash_os.h"
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#endif
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#include "esp_sleep.h"
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#include "sdkconfig.h"
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@ -501,7 +506,19 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
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if (switch_down) {
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on_freq_update(old_ticks_per_us, new_ticks_per_us);
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}
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if (new_config.source == RTC_CPU_FREQ_SRC_PLL) {
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rtc_clk_cpu_freq_set_config_fast(&new_config);
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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spi_timing_change_speed_mode_cache_safe(false);
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#endif
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} else {
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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spi_timing_change_speed_mode_cache_safe(true);
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#endif
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rtc_clk_cpu_freq_set_config_fast(&new_config);
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}
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if (!switch_down) {
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on_freq_update(old_ticks_per_us, new_ticks_per_us);
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}
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@ -470,8 +470,8 @@ void spi_timing_enter_mspi_high_speed_mode(bool control_spi1)
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void spi_timing_change_speed_mode_cache_safe(bool switch_down)
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{
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Cache_Freeze_ICache_Enable(1);
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Cache_Freeze_DCache_Enable(1);
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Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
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Cache_Freeze_DCache_Enable(CACHE_FREEZE_ACK_BUSY);
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if (switch_down) {
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//enter MSPI low speed mode, extra delays should be removed
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spi_timing_enter_mspi_low_speed_mode(false);
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