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bugfix: fix esp32s3 psram access failed when dfs is enabled

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This commit is contained in:
wuzhenghui 2023-06-05 21:17:40 +08:00
parent fd5e03b221
commit 82bcd4dc7f
4 changed files with 25 additions and 6 deletions
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2
components/esp_hw_support/sleep_modes.c
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@ -550,8 +550,10 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
rtc_clk_cpu_freq_set_config(&cpu_freq_config); rtc_clk_cpu_freq_set_config(&cpu_freq_config);
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
if (cpu_freq_config.source == RTC_CPU_FREQ_SRC_PLL) {
// Restore mspi clock freq // Restore mspi clock freq
spi_timing_change_speed_mode_cache_safe(false); spi_timing_change_speed_mode_cache_safe(false);
}
#endif #endif
if (!deep_sleep) { if (!deep_sleep) {

2
components/esp_pm/CMakeLists.txt
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@ -1,4 +1,4 @@
idf_component_register(SRCS "pm_locks.c" "pm_trace.c" "pm_impl.c" idf_component_register(SRCS "pm_locks.c" "pm_trace.c" "pm_impl.c"
INCLUDE_DIRS include INCLUDE_DIRS include
PRIV_REQUIRES esp_system driver PRIV_REQUIRES esp_system driver spi_flash
LDFRAGMENTS linker.lf) LDFRAGMENTS linker.lf)

17
components/esp_pm/pm_impl.c
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@ -17,6 +17,7 @@
#include "esp_private/crosscore_int.h" #include "esp_private/crosscore_int.h"
#include "soc/rtc.h" #include "soc/rtc.h"
#include "soc/soc_caps.h"
#include "hal/cpu_hal.h" #include "hal/cpu_hal.h"
#include "hal/uart_ll.h" #include "hal/uart_ll.h"
#include "hal/uart_types.h" #include "hal/uart_types.h"
@ -32,6 +33,10 @@
#include "esp_private/pm_trace.h" #include "esp_private/pm_trace.h"
#include "esp_private/esp_timer_private.h" #include "esp_private/esp_timer_private.h"
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
#include "esp_private/spi_flash_os.h"
#endif
#include "esp_sleep.h" #include "esp_sleep.h"
#include "sdkconfig.h" #include "sdkconfig.h"
@ -501,7 +506,19 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
if (switch_down) { if (switch_down) {
on_freq_update(old_ticks_per_us, new_ticks_per_us); on_freq_update(old_ticks_per_us, new_ticks_per_us);
} }
if (new_config.source == RTC_CPU_FREQ_SRC_PLL) {
rtc_clk_cpu_freq_set_config_fast(&new_config); rtc_clk_cpu_freq_set_config_fast(&new_config);
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
spi_timing_change_speed_mode_cache_safe(false);
#endif
} else {
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
spi_timing_change_speed_mode_cache_safe(true);
#endif
rtc_clk_cpu_freq_set_config_fast(&new_config);
}
if (!switch_down) { if (!switch_down) {
on_freq_update(old_ticks_per_us, new_ticks_per_us); on_freq_update(old_ticks_per_us, new_ticks_per_us);
} }

4
components/spi_flash/spi_flash_timing_tuning.c
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@ -470,8 +470,8 @@ void spi_timing_enter_mspi_high_speed_mode(bool control_spi1)
void spi_timing_change_speed_mode_cache_safe(bool switch_down) void spi_timing_change_speed_mode_cache_safe(bool switch_down)
{ {
Cache_Freeze_ICache_Enable(1); Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
Cache_Freeze_DCache_Enable(1); Cache_Freeze_DCache_Enable(CACHE_FREEZE_ACK_BUSY);
if (switch_down) { if (switch_down) {
//enter MSPI low speed mode, extra delays should be removed //enter MSPI low speed mode, extra delays should be removed
spi_timing_enter_mspi_low_speed_mode(false); spi_timing_enter_mspi_low_speed_mode(false);