From 717a2ccf150aff93baa33294d272953d3828b7dd Mon Sep 17 00:00:00 2001
From: laokaiyao <laokaiyao@espressif.com>
Date: Tue, 11 Jun 2024 15:23:36 +0800
Subject: [PATCH] remove(c5beta3): remove c5 beta3 soc files

---
 .codespellrc                                  |    2 +-
 components/soc/CMakeLists.txt                 |    8 +-
 components/soc/esp32c5/beta3/gdma_periph.c    |  121 -
 components/soc/esp32c5/beta3/gpio_periph.c    |   41 -
 components/soc/esp32c5/beta3/i2c_periph.c     |   22 -
 .../soc/esp32c5/beta3/ieee802154_periph.c     |   12 -
 .../beta3/include/modem/modem_syscon_struct.h |  164 -
 .../esp32c5/beta3/include/modem/reg_base.h    |    9 -
 .../beta3/include/soc/Kconfig.soc_caps.in     |  872 ---
 .../soc/esp32c5/beta3/include/soc/aes_reg.h   |  368 -
 .../esp32c5/beta3/include/soc/aes_struct.h    |  438 --
 .../beta3/include/soc/apb_saradc_reg.h        |  813 --
 .../beta3/include/soc/apb_saradc_struct.h     |  696 --
 .../beta3/include/soc/assist_debug_reg.h      |  582 --
 .../beta3/include/soc/assist_debug_struct.h   |  549 --
 .../beta3/include/soc/bitscrambler_reg.h      |  481 --
 .../beta3/include/soc/bitscrambler_struct.h   |  437 --
 .../soc/esp32c5/beta3/include/soc/cache_reg.h | 1289 ----
 .../esp32c5/beta3/include/soc/cache_struct.h  | 1410 ----
 .../soc/esp32c5/beta3/include/soc/clic_reg.h  |  108 -
 .../soc/esp32c5/beta3/include/soc/clint_reg.h |   77 -
 .../esp32c5/beta3/include/soc/clk_tree_defs.h |  524 --
 .../esp32c5/beta3/include/soc/dport_access.h  |  108 -
 .../soc/esp32c5/beta3/include/soc/ds_reg.h    |  149 -
 .../soc/esp32c5/beta3/include/soc/ds_struct.h |  149 -
 .../esp32c5/beta3/include/soc/ecc_mult_reg.h  |  185 -
 .../beta3/include/soc/ecc_mult_struct.h       |  164 -
 .../soc/esp32c5/beta3/include/soc/ecdsa_reg.h |  318 -
 .../esp32c5/beta3/include/soc/ecdsa_struct.h  |  324 -
 .../soc/esp32c5/beta3/include/soc/efuse_reg.h | 2556 ------
 .../esp32c5/beta3/include/soc/efuse_struct.h  | 2390 ------
 .../esp32c5/beta3/include/soc/ext_mem_defs.h  |  132 -
 .../esp32c5/beta3/include/soc/gdma_channel.h  |   30 -
 .../soc/esp32c5/beta3/include/soc/gdma_reg.h  | 3213 --------
 .../esp32c5/beta3/include/soc/gdma_struct.h   | 1044 ---
 .../esp32c5/beta3/include/soc/gpio_ext_reg.h  | 1102 ---
 .../beta3/include/soc/gpio_ext_struct.h       |  340 -
 .../soc/esp32c5/beta3/include/soc/gpio_num.h  |   50 -
 .../soc/esp32c5/beta3/include/soc/gpio_pins.h |   19 -
 .../soc/esp32c5/beta3/include/soc/gpio_reg.h  | 5727 --------------
 .../esp32c5/beta3/include/soc/gpio_sig_map.h  |  232 -
 .../esp32c5/beta3/include/soc/gpio_struct.h   |  419 -
 .../beta3/include/soc/hardware_lock_reg.h     |   76 -
 .../beta3/include/soc/hardware_lock_struct.h  |   98 -
 .../soc/esp32c5/beta3/include/soc/hmac_reg.h  |  232 -
 .../esp32c5/beta3/include/soc/hmac_struct.h   |  292 -
 .../esp32c5/beta3/include/soc/hp_apm_reg.h    | 1950 -----
 .../esp32c5/beta3/include/soc/hp_apm_struct.h | 1734 -----
 .../esp32c5/beta3/include/soc/hp_system_reg.h |  784 --
 .../beta3/include/soc/hp_system_struct.h      |  760 --
 .../soc/esp32c5/beta3/include/soc/huk_reg.h   |  222 -
 .../esp32c5/beta3/include/soc/huk_struct.h    |  242 -
 .../soc/esp32c5/beta3/include/soc/i2c_reg.h   | 1521 ----
 .../esp32c5/beta3/include/soc/i2c_struct.h    | 1122 ---
 .../soc/esp32c5/beta3/include/soc/i2s_reg.h   | 1268 ---
 .../esp32c5/beta3/include/soc/i2s_struct.h    | 1007 ---
 .../beta3/include/soc/ieee802154_reg.h        |  545 --
 .../beta3/include/soc/ieee802154_struct.h     |  480 --
 .../beta3/include/soc/interrupt_matrix_reg.h  | 1044 ---
 .../include/soc/interrupt_matrix_struct.h     | 1385 ----
 .../esp32c5/beta3/include/soc/interrupts.h    |  110 -
 .../esp32c5/beta3/include/soc/intpri_reg.h    |   88 -
 .../esp32c5/beta3/include/soc/intpri_struct.h |  121 -
 .../esp32c5/beta3/include/soc/io_mux_reg.h    |  344 -
 .../esp32c5/beta3/include/soc/io_mux_struct.h |  143 -
 .../esp32c5/beta3/include/soc/keymng_reg.h    |  337 -
 .../esp32c5/beta3/include/soc/keymng_struct.h |  340 -
 .../soc/esp32c5/beta3/include/soc/ledc_reg.h  | 2334 ------
 .../esp32c5/beta3/include/soc/ledc_struct.h   | 1080 ---
 .../beta3/include/soc/lp_analog_peri_reg.h    |  228 -
 .../beta3/include/soc/lp_analog_peri_struct.h |  252 -
 .../esp32c5/beta3/include/soc/lp_aon_reg.h    |  466 --
 .../esp32c5/beta3/include/soc/lp_aon_struct.h |  365 -
 .../esp32c5/beta3/include/soc/lp_apm0_reg.h   |  534 --
 .../beta3/include/soc/lp_apm0_struct.h        |  515 --
 .../esp32c5/beta3/include/soc/lp_apm_reg.h    |  610 --
 .../esp32c5/beta3/include/soc/lp_apm_struct.h |  599 --
 .../esp32c5/beta3/include/soc/lp_clkrst_reg.h |  404 -
 .../beta3/include/soc/lp_clkrst_struct.h      |  354 -
 .../beta3/include/soc/lp_i2c_ana_mst_reg.h    |  135 -
 .../beta3/include/soc/lp_i2c_ana_mst_struct.h |  150 -
 .../esp32c5/beta3/include/soc/lp_i2c_reg.h    | 1285 ---
 .../esp32c5/beta3/include/soc/lp_i2c_struct.h |  963 ---
 .../soc/esp32c5/beta3/include/soc/lp_io_reg.h | 1263 ---
 .../esp32c5/beta3/include/soc/lp_io_struct.h  |  740 --
 .../esp32c5/beta3/include/soc/lp_tee_reg.h    |   72 -
 .../esp32c5/beta3/include/soc/lp_tee_struct.h |   99 -
 .../esp32c5/beta3/include/soc/lp_timer_reg.h  |  342 -
 .../beta3/include/soc/lp_timer_struct.h       |  335 -
 .../esp32c5/beta3/include/soc/lp_uart_reg.h   | 1381 ----
 .../beta3/include/soc/lp_uart_struct.h        | 1128 ---
 .../esp32c5/beta3/include/soc/lp_wdt_reg.h    |  324 -
 .../esp32c5/beta3/include/soc/lp_wdt_struct.h |  317 -
 .../esp32c5/beta3/include/soc/lpperi_reg.h    |  317 -
 .../esp32c5/beta3/include/soc/lpperi_struct.h |  289 -
 .../soc/esp32c5/beta3/include/soc/mcpwm_reg.h | 4514 -----------
 .../esp32c5/beta3/include/soc/mcpwm_struct.h  | 2031 -----
 .../beta3/include/soc/mem_monitor_reg.h       |  184 -
 .../beta3/include/soc/mem_monitor_struct.h    |  220 -
 .../esp32c5/beta3/include/soc/otp_debug_reg.h | 1600 ----
 .../beta3/include/soc/otp_debug_struct.h      | 2137 -----
 .../esp32c5/beta3/include/soc/parl_io_reg.h   |  480 --
 .../beta3/include/soc/parl_io_struct.h        |  509 --
 .../soc/esp32c5/beta3/include/soc/pau_reg.h   |  332 -
 .../esp32c5/beta3/include/soc/pau_struct.h    |  339 -
 .../soc/esp32c5/beta3/include/soc/pcnt_reg.h  | 1346 ----
 .../esp32c5/beta3/include/soc/pcnt_struct.h   |  442 --
 .../soc/esp32c5/beta3/include/soc/pcr_reg.h   | 2551 ------
 .../esp32c5/beta3/include/soc/pcr_struct.h    | 2239 ------
 .../esp32c5/beta3/include/soc/periph_defs.h   |   88 -
 .../beta3/include/soc/pmu_icg_mapping.h       |   68 -
 .../soc/esp32c5/beta3/include/soc/pmu_reg.h   | 3359 --------
 .../esp32c5/beta3/include/soc/pmu_struct.h    |  758 --
 .../soc/esp32c5/beta3/include/soc/reg_base.h  |  105 -
 .../esp32c5/beta3/include/soc/regi2c_bbpll.h  |   86 -
 .../esp32c5/beta3/include/soc/regi2c_defs.h   |   30 -
 .../beta3/include/soc/regi2c_dig_reg.h        |   64 -
 .../esp32c5/beta3/include/soc/reset_reasons.h |   56 -
 .../beta3/include/soc/retention_periph_defs.h |   92 -
 .../soc/esp32c5/beta3/include/soc/rmt_reg.h   | 1491 ----
 .../esp32c5/beta3/include/soc/rmt_struct.h    |  802 --
 .../soc/esp32c5/beta3/include/soc/rsa_reg.h   |  233 -
 .../esp32c5/beta3/include/soc/rsa_struct.h    |  273 -
 .../beta3/include/soc/rtc_io_channel.h        |   33 -
 .../soc/esp32c5/beta3/include/soc/sha_reg.h   |  148 -
 .../esp32c5/beta3/include/soc/sha_struct.h    |  188 -
 .../soc/esp32c5/beta3/include/soc/soc.h       |  240 -
 .../soc/esp32c5/beta3/include/soc/soc_caps.h  |  582 --
 .../esp32c5/beta3/include/soc/soc_etm_reg.h   | 6867 -----------------
 .../beta3/include/soc/soc_etm_source.h        |  300 -
 .../beta3/include/soc/soc_etm_struct.h        | 3649 ---------
 .../soc/esp32c5/beta3/include/soc/soc_pins.h  |   16 -
 .../esp32c5/beta3/include/soc/spi1_mem_reg.h  | 1232 ---
 .../beta3/include/soc/spi1_mem_struct.h       | 1081 ---
 .../esp32c5/beta3/include/soc/spi_mem_reg.h   | 2737 -------
 .../beta3/include/soc/spi_mem_struct.h        | 1081 ---
 .../soc/esp32c5/beta3/include/soc/spi_pins.h  |   18 -
 .../soc/esp32c5/beta3/include/soc/spi_reg.h   | 2116 -----
 .../esp32c5/beta3/include/soc/spi_struct.h    | 1405 ----
 .../include/soc/system_periph_retention.h     |   94 -
 .../esp32c5/beta3/include/soc/system_reg.h    |   12 -
 .../esp32c5/beta3/include/soc/systimer_reg.h  |  630 --
 .../beta3/include/soc/systimer_struct.h       |  379 -
 .../soc/esp32c5/beta3/include/soc/tee_reg.h   |  680 --
 .../esp32c5/beta3/include/soc/tee_struct.h    |  701 --
 .../beta3/include/soc/timer_group_reg.h       |  538 --
 .../beta3/include/soc/timer_group_struct.h    |  556 --
 .../soc/esp32c5/beta3/include/soc/trace_reg.h |  463 --
 .../esp32c5/beta3/include/soc/trace_struct.h  |  462 --
 .../soc/esp32c5/beta3/include/soc/twai_reg.h  |  791 --
 .../esp32c5/beta3/include/soc/twai_struct.h   |  614 --
 .../esp32c5/beta3/include/soc/uart_channel.h  |   18 -
 .../soc/esp32c5/beta3/include/soc/uart_pins.h |   46 -
 .../soc/esp32c5/beta3/include/soc/uart_reg.h  | 1579 ----
 .../esp32c5/beta3/include/soc/uart_struct.h   | 1294 ----
 .../soc/esp32c5/beta3/include/soc/uhci_reg.h  |  966 ---
 .../esp32c5/beta3/include/soc/uhci_struct.h   |  666 --
 .../beta3/include/soc/usb_serial_jtag_reg.h   | 1188 ---
 .../include/soc/usb_serial_jtag_struct.h      |  941 ---
 .../soc/esp32c5/beta3/include/soc/wdev_reg.h  |   13 -
 components/soc/esp32c5/beta3/interrupts.c     |   95 -
 .../esp32c5/beta3/ld/esp32c5.peripherals.ld   |   85 -
 components/soc/esp32c5/beta3/spi_periph.c     |   64 -
 .../esp32c5/beta3/system_retention_periph.c   |  114 -
 components/soc/esp32c5/beta3/uart_periph.c    |  151 -
 components/soc/esp32c5/{mp => }/gdma_periph.c |    0
 components/soc/esp32c5/{mp => }/gpio_periph.c |    0
 components/soc/esp32c5/{mp => }/i2s_periph.c  |    0
 .../include/modem/modem_lpcon_reg.h           |  179 +-
 .../include/modem/modem_lpcon_struct.h        |  122 +-
 .../include/modem/modem_syscon_reg.h          |   99 +-
 .../include/modem/modem_syscon_struct.h       |  174 +
 .../soc/esp32c5/include/modem/reg_base.h      |    9 +
 .../esp32c5/include/soc/Kconfig.soc_caps.in   |  776 +-
 .../{beta3 => }/include/soc/adc_channel.h     |    3 +-
 .../esp32c5/{mp => }/include/soc/aes_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/aes_struct.h |    0
 .../{mp => }/include/soc/ahb_dma_reg.h        |    0
 .../{mp => }/include/soc/ahb_dma_struct.h     |    0
 .../{mp => }/include/soc/apb_saradc_reg.h     |    0
 .../{mp => }/include/soc/apb_saradc_struct.h  |    0
 .../{mp => }/include/soc/assist_debug_reg.h   |    4 +-
 .../include/soc/assist_debug_struct.h         |   10 +-
 .../{mp => }/include/soc/bitscrambler_reg.h   |    4 +-
 .../include/soc/bitscrambler_struct.h         |    4 +-
 .../esp32c5/{mp => }/include/soc/cache_reg.h  |    8 +-
 .../{mp => }/include/soc/cache_struct.h       |    8 +-
 .../esp32c5/{mp => }/include/soc/clic_reg.h   |    0
 .../esp32c5/{mp => }/include/soc/clint_reg.h  |    0
 .../{mp => }/include/soc/clk_tree_defs.h      |    0
 .../{beta3 => }/include/soc/clkout_channel.h  |    0
 .../{mp => }/include/soc/dport_access.h       |    0
 .../soc/esp32c5/{mp => }/include/soc/ds_reg.h |    0
 .../esp32c5/{mp => }/include/soc/ds_struct.h  |    0
 .../{mp => }/include/soc/ecc_mult_reg.h       |    0
 .../{mp => }/include/soc/ecc_mult_struct.h    |    0
 .../esp32c5/{mp => }/include/soc/ecdsa_reg.h  |    6 +-
 .../{mp => }/include/soc/ecdsa_struct.h       |    6 +-
 .../{beta3 => }/include/soc/efuse_defs.h      |    0
 .../esp32c5/{mp => }/include/soc/efuse_reg.h  |    6 +-
 .../{mp => }/include/soc/efuse_struct.h       |    8 +-
 .../{mp => }/include/soc/ext_mem_defs.h       |    0
 .../{mp => }/include/soc/gdma_channel.h       |    0
 .../{mp => }/include/soc/gpio_ext_reg.h       |    2 +-
 .../{mp => }/include/soc/gpio_ext_struct.h    |    2 +-
 .../esp32c5/{mp => }/include/soc/gpio_num.h   |    0
 .../esp32c5/{mp => }/include/soc/gpio_pins.h  |    0
 .../esp32c5/{mp => }/include/soc/gpio_reg.h   |    0
 .../soc/esp32c5/include/soc/gpio_sig_map.h    |  247 +-
 .../{mp => }/include/soc/gpio_struct.h        |    0
 .../esp32c5/{mp => }/include/soc/hmac_reg.h   |    0
 .../{mp => }/include/soc/hmac_struct.h        |    0
 .../esp32c5/{mp => }/include/soc/hp_apm_reg.h |    0
 .../{mp => }/include/soc/hp_apm_struct.h      |    0
 .../{mp => }/include/soc/hp_system_reg.h      |    0
 .../{mp => }/include/soc/hp_system_struct.h   |    0
 .../esp32c5/{mp => }/include/soc/huk_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/huk_struct.h |    0
 .../{beta3 => }/include/soc/hwcrypto_reg.h    |    0
 .../{beta3 => }/include/soc/i2c_ana_mst_reg.h |    0
 .../esp32c5/{mp => }/include/soc/i2c_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/i2c_struct.h |    0
 .../esp32c5/{mp => }/include/soc/i2s_reg.h    |    2 +-
 .../esp32c5/{mp => }/include/soc/i2s_struct.h |    0
 .../include/soc/interrupt_matrix_reg.h        |    0
 .../include/soc/interrupt_matrix_struct.h     |    0
 .../{beta3 => }/include/soc/interrupt_reg.h   |    0
 .../esp32c5/{mp => }/include/soc/interrupts.h |    0
 .../esp32c5/{mp => }/include/soc/intpri_reg.h |    0
 .../{mp => }/include/soc/intpri_struct.h      |    0
 .../esp32c5/{mp => }/include/soc/io_mux_reg.h |    0
 .../{mp => }/include/soc/io_mux_struct.h      |    0
 .../esp32c5/{mp => }/include/soc/keymng_reg.h |    0
 .../{mp => }/include/soc/keymng_struct.h      |    0
 .../esp32c5/{mp => }/include/soc/ledc_reg.h   |    0
 .../{mp => }/include/soc/ledc_struct.h        |    0
 .../{mp => }/include/soc/lp_analog_peri_reg.h |    0
 .../include/soc/lp_analog_peri_struct.h       |    0
 .../esp32c5/{mp => }/include/soc/lp_aon_reg.h |    2 +-
 .../{mp => }/include/soc/lp_aon_struct.h      |    2 +-
 .../{mp => }/include/soc/lp_apm0_reg.h        |    0
 .../{mp => }/include/soc/lp_apm0_struct.h     |    0
 .../esp32c5/{mp => }/include/soc/lp_apm_reg.h |    0
 .../{mp => }/include/soc/lp_apm_struct.h      |    0
 .../{mp => }/include/soc/lp_clkrst_reg.h      |    2 +-
 .../{mp => }/include/soc/lp_clkrst_struct.h   |    2 +-
 .../{mp => }/include/soc/lp_gpio_reg.h        |    0
 .../{mp => }/include/soc/lp_gpio_struct.h     |    0
 .../{mp => }/include/soc/lp_i2c_ana_mst_reg.h |    0
 .../include/soc/lp_i2c_ana_mst_struct.h       |    0
 .../esp32c5/{mp => }/include/soc/lp_i2c_reg.h |    0
 .../{mp => }/include/soc/lp_i2c_struct.h      |    0
 .../{mp => }/include/soc/lp_iomux_reg.h       |    0
 .../{mp => }/include/soc/lp_iomux_struct.h    |    0
 .../esp32c5/{mp => }/include/soc/lp_tee_reg.h |    0
 .../{mp => }/include/soc/lp_tee_struct.h      |    0
 .../{mp => }/include/soc/lp_timer_reg.h       |    0
 .../{mp => }/include/soc/lp_timer_struct.h    |    0
 .../{mp => }/include/soc/lp_uart_reg.h        |    0
 .../{mp => }/include/soc/lp_uart_struct.h     |    0
 .../esp32c5/{mp => }/include/soc/lp_wdt_reg.h |    0
 .../{mp => }/include/soc/lp_wdt_struct.h      |    0
 .../esp32c5/{mp => }/include/soc/lpperi_reg.h |    0
 .../{mp => }/include/soc/lpperi_struct.h      |    0
 .../esp32c5/{mp => }/include/soc/mcpwm_reg.h  |    0
 .../{mp => }/include/soc/mcpwm_struct.h       |    0
 .../{mp => }/include/soc/mem_monitor_reg.h    |    0
 .../{mp => }/include/soc/mem_monitor_struct.h |    0
 .../{mp => }/include/soc/parl_io_reg.h        |    8 +-
 .../{mp => }/include/soc/parl_io_struct.h     |    8 +-
 .../esp32c5/{mp => }/include/soc/pau_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/pau_struct.h |    0
 .../esp32c5/{mp => }/include/soc/pcnt_reg.h   |    0
 .../{mp => }/include/soc/pcnt_struct.h        |    0
 .../esp32c5/{mp => }/include/soc/pcr_reg.h    |   50 +-
 .../esp32c5/{mp => }/include/soc/pcr_struct.h |   50 +-
 .../{mp => }/include/soc/periph_defs.h        |    0
 .../{mp => }/include/soc/pmu_icg_mapping.h    |    0
 .../esp32c5/{mp => }/include/soc/pmu_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/pmu_struct.h |    0
 .../esp32c5/{mp => }/include/soc/pvt_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/pvt_struct.h |    0
 .../esp32c5/{mp => }/include/soc/reg_base.h   |    0
 .../{mp => }/include/soc/regi2c_bbpll.h       |    0
 .../{mp => }/include/soc/regi2c_defs.h        |    0
 .../{mp => }/include/soc/regi2c_dig_reg.h     |    0
 .../{mp => }/include/soc/reset_reasons.h      |    2 +-
 .../include/soc/retention_periph_defs.h       |    0
 .../esp32c5/{mp => }/include/soc/rmt_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/rmt_struct.h |    0
 .../esp32c5/{mp => }/include/soc/rsa_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/rsa_struct.h |    0
 .../esp32c5/{mp => }/include/soc/rtc_io_reg.h |    0
 .../{mp => }/include/soc/rtc_io_struct.h      |    0
 .../esp32c5/{mp => }/include/soc/sha_reg.h    |    2 +-
 .../esp32c5/{mp => }/include/soc/sha_struct.h |    0
 .../soc/esp32c5/{mp => }/include/soc/soc.h    |    0
 components/soc/esp32c5/include/soc/soc_caps.h |  580 +-
 .../{mp => }/include/soc/soc_etm_reg.h        |    0
 .../{mp => }/include/soc/soc_etm_source.h     |    0
 .../{mp => }/include/soc/soc_etm_struct.h     |    0
 .../esp32c5/{mp => }/include/soc/soc_pins.h   |    0
 .../{mp => }/include/soc/spi1_mem_reg.h       |    6 +-
 .../{mp => }/include/soc/spi1_mem_struct.h    |    6 +-
 .../{mp => }/include/soc/spi_mem_reg.h        |   16 +-
 .../{mp => }/include/soc/spi_mem_struct.h     |    8 +-
 .../esp32c5/{mp => }/include/soc/spi_pins.h   |    0
 .../esp32c5/{mp => }/include/soc/spi_reg.h    |    2 +-
 .../esp32c5/{mp => }/include/soc/spi_struct.h |    0
 .../esp32c5/{mp => }/include/soc/system_reg.h |    0
 .../{mp => }/include/soc/systimer_reg.h       |    0
 .../{mp => }/include/soc/systimer_struct.h    |    0
 .../esp32c5/{mp => }/include/soc/tee_reg.h    |    0
 .../esp32c5/{mp => }/include/soc/tee_struct.h |    0
 .../{mp => }/include/soc/timer_group_reg.h    |    0
 .../{mp => }/include/soc/timer_group_struct.h |    0
 .../esp32c5/{mp => }/include/soc/trace_reg.h  |   10 +-
 .../{mp => }/include/soc/trace_struct.h       |   10 +-
 .../esp32c5/{mp => }/include/soc/twaifd_reg.h |    8 +-
 .../{mp => }/include/soc/twaifd_struct.h      |    8 +-
 .../{mp => }/include/soc/uart_channel.h       |    0
 .../esp32c5/{mp => }/include/soc/uart_pins.h  |    0
 .../esp32c5/{mp => }/include/soc/uart_reg.h   |    0
 .../{mp => }/include/soc/uart_struct.h        |    0
 .../esp32c5/{mp => }/include/soc/uhci_reg.h   |    0
 .../{mp => }/include/soc/uhci_struct.h        |    0
 .../include/soc/usb_serial_jtag_reg.h         |    4 +-
 .../include/soc/usb_serial_jtag_struct.h      |    4 +-
 .../esp32c5/{mp => }/include/soc/wdev_reg.h   |    0
 components/soc/esp32c5/{mp => }/interrupts.c  |    0
 .../{mp => }/ld/esp32c5.peripherals.ld        |    0
 components/soc/esp32c5/{mp => }/ledc_periph.c |    0
 .../soc/esp32c5/{mp => }/mcpwm_periph.c       |    0
 .../mp/include/soc/Kconfig.soc_caps.in        |  800 --
 .../esp32c5/mp/include/soc/clkout_channel.h   |   42 -
 .../soc/esp32c5/mp/include/soc/efuse_defs.h   |   17 -
 .../soc/esp32c5/mp/include/soc/gpio_sig_map.h |  246 -
 .../soc/esp32c5/mp/include/soc/hwcrypto_reg.h |   12 -
 .../esp32c5/mp/include/soc/i2c_ana_mst_reg.h  |  220 -
 .../esp32c5/mp/include/soc/interrupt_reg.h    |   25 -
 .../soc/esp32c5/mp/include/soc/soc_caps.h     |  583 --
 components/soc/esp32c5/mp/mpi_periph.c        |   21 -
 components/soc/esp32c5/mp/pcnt_periph.c       |   70 -
 components/soc/esp32c5/mp/rmt_periph.c        |   34 -
 components/soc/esp32c5/mp/timer_periph.c      |   92 -
 .../soc/esp32c5/{beta3 => }/mpi_periph.c      |    0
 .../soc/esp32c5/{beta3 => }/pcnt_periph.c     |    0
 .../soc/esp32c5/{beta3 => }/rmt_periph.c      |    0
 components/soc/esp32c5/{mp => }/spi_periph.c  |    0
 .../soc/esp32c5/{beta3 => }/timer_periph.c    |    0
 components/soc/esp32c5/{mp => }/uart_periph.c |    0
 .../soc/esp32c61/include/soc/adc_channel.h    |   29 +
 components/soc/include/soc/rtc_cntl_periph.h  |    4 +-
 353 files changed, 2185 insertions(+), 124541 deletions(-)
 delete mode 100644 components/soc/esp32c5/beta3/gdma_periph.c
 delete mode 100644 components/soc/esp32c5/beta3/gpio_periph.c
 delete mode 100644 components/soc/esp32c5/beta3/i2c_periph.c
 delete mode 100644 components/soc/esp32c5/beta3/ieee802154_periph.c
 delete mode 100644 components/soc/esp32c5/beta3/include/modem/modem_syscon_struct.h
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 delete mode 100644 components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
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 delete mode 100644 components/soc/esp32c5/beta3/include/soc/aes_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/apb_saradc_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/apb_saradc_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/assist_debug_reg.h
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 delete mode 100644 components/soc/esp32c5/beta3/include/soc/bitscrambler_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/bitscrambler_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/cache_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/cache_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/clic_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/clint_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/dport_access.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ds_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ds_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ecc_mult_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ecc_mult_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ecdsa_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ecdsa_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/efuse_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/efuse_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ext_mem_defs.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gdma_channel.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gdma_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gdma_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gpio_ext_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gpio_ext_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gpio_num.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gpio_pins.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gpio_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gpio_sig_map.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/gpio_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hardware_lock_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hardware_lock_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hmac_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hmac_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hp_apm_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hp_apm_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hp_system_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/hp_system_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/huk_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/huk_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/i2c_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/i2c_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/i2s_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/i2s_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ieee802154_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ieee802154_struct.h
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 delete mode 100644 components/soc/esp32c5/beta3/include/soc/interrupts.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/intpri_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/intpri_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/io_mux_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/keymng_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/keymng_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ledc_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/ledc_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_analog_peri_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_analog_peri_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_aon_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_aon_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_apm0_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_apm0_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_apm_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_apm_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_clkrst_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_clkrst_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_i2c_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_i2c_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_io_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_io_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_tee_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_tee_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_timer_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_timer_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_uart_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_uart_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_wdt_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lp_wdt_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lpperi_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/lpperi_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/mcpwm_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/mcpwm_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/mem_monitor_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/mem_monitor_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/otp_debug_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/otp_debug_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/parl_io_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/parl_io_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pau_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pau_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pcnt_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pcnt_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pcr_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pcr_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/periph_defs.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pmu_icg_mapping.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pmu_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/pmu_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/reg_base.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/regi2c_bbpll.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/regi2c_defs.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/regi2c_dig_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/reset_reasons.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/retention_periph_defs.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/rmt_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/rmt_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/rsa_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/rsa_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/rtc_io_channel.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/sha_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/sha_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/soc.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/soc_caps.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/soc_etm_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/soc_etm_source.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/soc_etm_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/soc_pins.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/spi1_mem_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/spi1_mem_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/spi_mem_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/spi_mem_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/spi_pins.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/spi_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/spi_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/system_periph_retention.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/system_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/systimer_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/systimer_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/tee_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/tee_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/timer_group_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/timer_group_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/trace_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/trace_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/twai_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/twai_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/uart_channel.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/uart_pins.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/uart_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/uart_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/uhci_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/uhci_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_struct.h
 delete mode 100644 components/soc/esp32c5/beta3/include/soc/wdev_reg.h
 delete mode 100644 components/soc/esp32c5/beta3/interrupts.c
 delete mode 100644 components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
 delete mode 100644 components/soc/esp32c5/beta3/spi_periph.c
 delete mode 100644 components/soc/esp32c5/beta3/system_retention_periph.c
 delete mode 100644 components/soc/esp32c5/beta3/uart_periph.c
 rename components/soc/esp32c5/{mp => }/gdma_periph.c (100%)
 rename components/soc/esp32c5/{mp => }/gpio_periph.c (100%)
 rename components/soc/esp32c5/{mp => }/i2s_periph.c (100%)
 rename components/soc/esp32c5/{beta3 => }/include/modem/modem_lpcon_reg.h (72%)
 rename components/soc/esp32c5/{beta3 => }/include/modem/modem_lpcon_struct.h (67%)
 rename components/soc/esp32c5/{beta3 => }/include/modem/modem_syscon_reg.h (84%)
 create mode 100644 components/soc/esp32c5/include/modem/modem_syscon_struct.h
 create mode 100644 components/soc/esp32c5/include/modem/reg_base.h
 rename components/soc/esp32c5/{beta3 => }/include/soc/adc_channel.h (82%)
 rename components/soc/esp32c5/{mp => }/include/soc/aes_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/aes_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ahb_dma_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ahb_dma_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/apb_saradc_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/apb_saradc_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/assist_debug_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/assist_debug_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/bitscrambler_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/bitscrambler_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/cache_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/cache_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/clic_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/clint_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/clk_tree_defs.h (100%)
 rename components/soc/esp32c5/{beta3 => }/include/soc/clkout_channel.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/dport_access.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ds_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ds_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ecc_mult_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ecc_mult_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ecdsa_reg.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/ecdsa_struct.h (97%)
 rename components/soc/esp32c5/{beta3 => }/include/soc/efuse_defs.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/efuse_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/efuse_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/ext_mem_defs.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/gdma_channel.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/gpio_ext_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/gpio_ext_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/gpio_num.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/gpio_pins.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/gpio_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/gpio_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/hmac_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/hmac_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/hp_apm_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/hp_apm_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/hp_system_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/hp_system_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/huk_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/huk_struct.h (100%)
 rename components/soc/esp32c5/{beta3 => }/include/soc/hwcrypto_reg.h (100%)
 rename components/soc/esp32c5/{beta3 => }/include/soc/i2c_ana_mst_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/i2c_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/i2c_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/i2s_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/i2s_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/interrupt_matrix_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/interrupt_matrix_struct.h (100%)
 rename components/soc/esp32c5/{beta3 => }/include/soc/interrupt_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/interrupts.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/intpri_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/intpri_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/io_mux_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/io_mux_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/keymng_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/keymng_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ledc_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/ledc_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_analog_peri_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_analog_peri_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_aon_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_aon_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_apm0_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_apm0_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_apm_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_apm_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_clkrst_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_clkrst_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_gpio_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_gpio_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_i2c_ana_mst_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_i2c_ana_mst_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_i2c_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_i2c_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_iomux_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_iomux_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_tee_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_tee_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_timer_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_timer_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_uart_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_uart_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_wdt_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lp_wdt_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lpperi_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/lpperi_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/mcpwm_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/mcpwm_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/mem_monitor_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/mem_monitor_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/parl_io_reg.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/parl_io_struct.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/pau_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pau_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pcnt_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pcnt_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pcr_reg.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/pcr_struct.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/periph_defs.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pmu_icg_mapping.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pmu_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pmu_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pvt_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/pvt_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/reg_base.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/regi2c_bbpll.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/regi2c_defs.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/regi2c_dig_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/reset_reasons.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/retention_periph_defs.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/rmt_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/rmt_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/rsa_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/rsa_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/rtc_io_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/rtc_io_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/sha_reg.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/sha_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/soc.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/soc_etm_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/soc_etm_source.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/soc_etm_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/soc_pins.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/spi1_mem_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/spi1_mem_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/spi_mem_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/spi_mem_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/spi_pins.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/spi_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/spi_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/system_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/systimer_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/systimer_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/tee_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/tee_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/timer_group_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/timer_group_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/trace_reg.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/trace_struct.h (98%)
 rename components/soc/esp32c5/{mp => }/include/soc/twaifd_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/twaifd_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/uart_channel.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/uart_pins.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/uart_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/uart_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/uhci_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/uhci_struct.h (100%)
 rename components/soc/esp32c5/{mp => }/include/soc/usb_serial_jtag_reg.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/usb_serial_jtag_struct.h (99%)
 rename components/soc/esp32c5/{mp => }/include/soc/wdev_reg.h (100%)
 rename components/soc/esp32c5/{mp => }/interrupts.c (100%)
 rename components/soc/esp32c5/{mp => }/ld/esp32c5.peripherals.ld (100%)
 rename components/soc/esp32c5/{mp => }/ledc_periph.c (100%)
 rename components/soc/esp32c5/{mp => }/mcpwm_periph.c (100%)
 delete mode 100644 components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
 delete mode 100644 components/soc/esp32c5/mp/include/soc/clkout_channel.h
 delete mode 100644 components/soc/esp32c5/mp/include/soc/efuse_defs.h
 delete mode 100644 components/soc/esp32c5/mp/include/soc/gpio_sig_map.h
 delete mode 100644 components/soc/esp32c5/mp/include/soc/hwcrypto_reg.h
 delete mode 100644 components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h
 delete mode 100644 components/soc/esp32c5/mp/include/soc/interrupt_reg.h
 delete mode 100644 components/soc/esp32c5/mp/include/soc/soc_caps.h
 delete mode 100644 components/soc/esp32c5/mp/mpi_periph.c
 delete mode 100644 components/soc/esp32c5/mp/pcnt_periph.c
 delete mode 100644 components/soc/esp32c5/mp/rmt_periph.c
 delete mode 100644 components/soc/esp32c5/mp/timer_periph.c
 rename components/soc/esp32c5/{beta3 => }/mpi_periph.c (100%)
 rename components/soc/esp32c5/{beta3 => }/pcnt_periph.c (100%)
 rename components/soc/esp32c5/{beta3 => }/rmt_periph.c (100%)
 rename components/soc/esp32c5/{mp => }/spi_periph.c (100%)
 rename components/soc/esp32c5/{beta3 => }/timer_periph.c (100%)
 rename components/soc/esp32c5/{mp => }/uart_periph.c (100%)
 create mode 100644 components/soc/esp32c61/include/soc/adc_channel.h

diff --git a/.codespellrc b/.codespellrc
index ff26c69e4c..b79ebe6b0a 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -1,4 +1,4 @@
 [codespell]
 skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*
-ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane
 write-changes = true
diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt
index b3a53fb779..54b293aeea 100644
--- a/components/soc/CMakeLists.txt
+++ b/components/soc/CMakeLists.txt
@@ -1,12 +1,6 @@
 idf_build_get_property(target IDF_TARGET)
 
-if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
-    set(target_folder "esp32c5/beta3")
-elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
-    set(target_folder "esp32c5/mp")
-else()
-    set(target_folder "${target}")
-endif()
+set(target_folder "${target}")
 
 # On Linux the soc component is a simple wrapper, without much functionality
 if(NOT ${target} STREQUAL "linux")
diff --git a/components/soc/esp32c5/beta3/gdma_periph.c b/components/soc/esp32c5/beta3/gdma_periph.c
deleted file mode 100644
index 4900618201..0000000000
--- a/components/soc/esp32c5/beta3/gdma_periph.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/gdma_periph.h"
-#include "soc/gdma_reg.h"
-
-const gdma_signal_conn_t gdma_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_GDMA_MODULE,
-            .pairs = {
-                [0]  = {
-                    .rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
-                    .tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
-                },
-                [1]  = {
-                    .rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
-                    .tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
-                },
-                [2]  = {
-                    .rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
-                    .tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
-                }
-            }
-        }
-    }
-};
-
-#if SOC_GDMA_SUPPORT_SLEEP_RETENTION
-/* GDMA Channel (Group0, Pair0) Registers Context
-   Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
-            GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
-            GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
-            GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
-*/
-#define G0P0_RETENTION_REGS_CNT_0  13
-#define G0P0_RETENTION_MAP_BASE_0  GDMA_IN_INT_ENA_CH0_REG
-#define G0P0_RETENTION_REGS_CNT_1  2
-#define G0P0_RETENTION_MAP_BASE_1  GDMA_BT_TX_SEL_REG
-static const uint32_t g0p0_regs_map0[4] = {0x4C801001, 0x604C0060, 0, 0};
-static const uint32_t g0p0_regs_map1[4] = {0x3, 0, 0, 0};
-static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
-    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
-                                                G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
-                                                G0P0_RETENTION_REGS_CNT_0, 0, 0, \
-                                                g0p0_regs_map0[0], g0p0_regs_map0[1],   \
-                                                g0p0_regs_map0[2], g0p0_regs_map0[3]),  \
-                                                .owner = ENTRY(0) | ENTRY(2) },
-    [1]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
-                                                G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
-                                                G0P0_RETENTION_REGS_CNT_1, 0, 0, \
-                                                g0p0_regs_map1[0], g0p0_regs_map1[1],   \
-                                                g0p0_regs_map1[2], g0p0_regs_map1[3]),  \
-                                                .owner = ENTRY(0) | ENTRY(2) },
-};
-
-/* GDMA Channel (Group0, Pair1) Registers Context
-   Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
-            GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
-            GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
-            GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
-*/
-#define G0P1_RETENTION_REGS_CNT_0  13
-#define G0P1_RETENTION_MAP_BASE_0  GDMA_IN_INT_ENA_CH1_REG
-#define G0P1_RETENTION_REGS_CNT_1  2
-#define G0P1_RETENTION_MAP_BASE_1  GDMA_BT_TX_SEL_REG
-static const uint32_t g0p1_regs_map0[4] = {0x81001, 0, 0xC00604C0, 0x604};
-static const uint32_t g0p1_regs_map1[4] = {0x3, 0, 0, 0};
-static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
-    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
-                                                G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
-                                                G0P1_RETENTION_REGS_CNT_0, 0, 0, \
-                                                g0p1_regs_map0[0], g0p1_regs_map0[1],   \
-                                                g0p1_regs_map0[2], g0p1_regs_map0[3]),  \
-                                                .owner = ENTRY(0) | ENTRY(2) },
-    [1]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
-                                                G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
-                                                G0P1_RETENTION_REGS_CNT_1, 0, 0, \
-                                                g0p1_regs_map1[0], g0p1_regs_map1[1],   \
-                                                g0p1_regs_map1[2], g0p1_regs_map1[3]),  \
-                                                .owner = ENTRY(0) | ENTRY(2) },
-};
-
-/* GDMA Channel (Group0, Pair2) Registers Context
-   Include: GDMA_MISC_CONF_REG / GDMA_BT_TX_SEL_REG / GDMA_BT_RX_SEL_REG
-            GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
-            GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
-            GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
-*/
-#define G0P2_RETENTION_REGS_CNT_0  6
-#define G0P2_RETENTION_MAP_BASE_0  GDMA_IN_INT_ENA_CH2_REG
-#define G0P2_RETENTION_REGS_CNT_1  9
-#define G0P2_RETENTION_MAP_BASE_1  GDMA_IN_PRI_CH2_REG
-static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
-static const uint32_t g0p2_regs_map1[4] = {0xf026003, 0, 0, 0};
-static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
-    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
-                                                G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
-                                                G0P2_RETENTION_REGS_CNT_0, 0, 0, \
-                                                g0p2_regs_map0[0], g0p2_regs_map0[1],   \
-                                                g0p2_regs_map0[2], g0p2_regs_map0[3]),  \
-                                                .owner = ENTRY(0) | ENTRY(2) },
-    [1]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \
-                                                G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
-                                                G0P2_RETENTION_REGS_CNT_1, 0, 0, \
-                                                g0p2_regs_map1[0], g0p2_regs_map1[1],   \
-                                                g0p2_regs_map1[2], g0p2_regs_map1[3]),  \
-                                                .owner = ENTRY(0) | ENTRY(2) },
-};
-
-const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
-    [0] = {
-        [0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
-        [1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
-        [2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)}
-    }
-};
-#endif
diff --git a/components/soc/esp32c5/beta3/gpio_periph.c b/components/soc/esp32c5/beta3/gpio_periph.c
deleted file mode 100644
index 00d0ebeaa9..0000000000
--- a/components/soc/esp32c5/beta3/gpio_periph.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/gpio_periph.h"
-
-_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
-
-const uint32_t GPIO_HOLD_MASK[] = {
-    BIT(0),          //GPIO0   // LP_AON_GPIO_HOLD0_REG
-    BIT(1),          //GPIO1
-    BIT(2),          //GPIO2
-    BIT(3),          //GPIO3
-    BIT(4),          //GPIO4
-    BIT(5),          //GPIO5
-    BIT(6),          //GPIO6
-    BIT(7),          //GPIO7
-    BIT(8),          //GPIO8
-    BIT(9),          //GPIO9
-    BIT(10),         //GPIO10
-    BIT(11),         //GPIO11
-    BIT(12),         //GPIO12
-    BIT(13),         //GPIO13
-    BIT(14),         //GPIO14
-    BIT(15),         //GPIO15
-    BIT(16),         //GPIO16
-    BIT(17),         //GPIO17
-    BIT(18),         //GPIO18
-    BIT(19),         //GPIO19
-    BIT(20),         //GPIO20
-    BIT(21),         //GPIO21
-    BIT(22),         //GPIO22
-    BIT(23),         //GPIO23
-    BIT(24),         //GPIO24
-    BIT(25),         //GPIO25
-    BIT(26),         //GPIO26
-};
-
-_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
diff --git a/components/soc/esp32c5/beta3/i2c_periph.c b/components/soc/esp32c5/beta3/i2c_periph.c
deleted file mode 100644
index 4e87d0c44f..0000000000
--- a/components/soc/esp32c5/beta3/i2c_periph.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/i2c_periph.h"
-#include "soc/gpio_sig_map.h"
-
-/*
- Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
-*/
-const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
-    {
-        .sda_out_sig = I2CEXT0_SDA_OUT_IDX,
-        .sda_in_sig = I2CEXT0_SDA_IN_IDX,
-        .scl_out_sig = I2CEXT0_SCL_OUT_IDX,
-        .scl_in_sig = I2CEXT0_SCL_IN_IDX,
-        .irq = ETS_I2C_EXT0_INTR_SOURCE,
-        .module = PERIPH_I2C0_MODULE,
-    },
-};
diff --git a/components/soc/esp32c5/beta3/ieee802154_periph.c b/components/soc/esp32c5/beta3/ieee802154_periph.c
deleted file mode 100644
index 76724c95f5..0000000000
--- a/components/soc/esp32c5/beta3/ieee802154_periph.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/ieee802154_periph.h"
-
-const ieee802154_conn_t ieee802154_periph = {
-            .module = PERIPH_IEEE802154_MODULE,
-            .irq_id = ETS_ZB_MAC_INTR_SOURCE,
-};
diff --git a/components/soc/esp32c5/beta3/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/beta3/include/modem/modem_syscon_struct.h
deleted file mode 100644
index ff9ff72f25..0000000000
--- a/components/soc/esp32c5/beta3/include/modem/modem_syscon_struct.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t clk_en                    :    1;
-            uint32_t modem_ant_force_sel_bt    :    1;
-            uint32_t modem_ant_force_sel_wifi  :    1;
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } test_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    21;
-            uint32_t clk_data_dump_mux         :    1;
-            uint32_t clk_etm_en                :    1;
-            uint32_t clk_zb_apb_en             :    1;
-            uint32_t clk_zbmac_en              :    1;
-            uint32_t clk_modem_sec_ecb_en      :    1;
-            uint32_t clk_modem_sec_ccm_en      :    1;
-            uint32_t clk_modem_sec_bah_en      :    1;
-            uint32_t clk_modem_sec_apb_en      :    1;
-            uint32_t clk_modem_sec_en          :    1;
-            uint32_t clk_ble_timer_en          :    1;
-            uint32_t clk_data_dump_en          :    1;
-        };
-        uint32_t val;
-    } clk_conf;
-    union {
-        struct {
-            uint32_t clk_wifibb_fo             :    1;
-            uint32_t clk_wifimac_fo            :    1;
-            uint32_t clk_wifi_apb_fo           :    1;
-            uint32_t clk_fe_fo                 :    1;
-            uint32_t clk_fe_apb_fo             :    1;
-            uint32_t clk_btbb_fo               :    1;
-            uint32_t clk_btmac_fo              :    1;
-            uint32_t clk_bt_apb_fo             :    1;
-            uint32_t clk_zbmac_fo              :    1;
-            uint32_t clk_zbmac_apb_fo          :    1;
-            uint32_t reserved10                    :    13;
-            uint32_t reserved23                    :    1;
-            uint32_t reserved24                    :    1;
-            uint32_t reserved25                    :    1;
-            uint32_t reserved26                    :    1;
-            uint32_t reserved27                    :    1;
-            uint32_t clk_etm_fo                :    1;
-            uint32_t clk_modem_sec_fo          :    1;
-            uint32_t clk_ble_timer_fo          :    1;
-            uint32_t clk_data_dump_fo          :    1;
-        };
-        uint32_t val;
-    } clk_conf_force_on;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;
-            uint32_t clk_zb_st_map             :    4;
-            uint32_t clk_fe_st_map             :    4;
-            uint32_t clk_bt_st_map             :    4;
-            uint32_t clk_wifi_st_map           :    4;
-            uint32_t clk_modem_peri_st_map     :    4;
-            uint32_t clk_modem_apb_st_map      :    4;
-        };
-        uint32_t val;
-    } clk_conf_power_st;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;
-            uint32_t reserved1                     :    1;
-            uint32_t reserved2                     :    1;
-            uint32_t reserved3                     :    1;
-            uint32_t reserved4                     :    1;
-            uint32_t reserved5                     :    1;
-            uint32_t reserved6                     :    1;
-            uint32_t reserved7                     :    1;
-            uint32_t rst_wifibb                :    1;
-            uint32_t rst_wifimac               :    1;
-            uint32_t rst_fe_pwdet_adc          :    1;
-            uint32_t rst_fe_dac                :    1;
-            uint32_t rst_fe_adc                :    1;
-            uint32_t rst_fe_ahb                :    1;
-            uint32_t rst_fe                    :    1;
-            uint32_t rst_btmac_apb             :    1;
-            uint32_t rst_btmac                 :    1;
-            uint32_t rst_btbb_apb              :    1;
-            uint32_t rst_btbb                  :    1;
-            uint32_t reserved19                    :    3;
-            uint32_t rst_etm                   :    1;
-            uint32_t reserved23                    :    1;
-            uint32_t rst_zbmac                 :    1;
-            uint32_t rst_modem_ecb             :    1;
-            uint32_t rst_modem_ccm             :    1;
-            uint32_t rst_modem_bah             :    1;
-            uint32_t reserved28                    :    1;
-            uint32_t rst_modem_sec             :    1;
-            uint32_t rst_ble_timer             :    1;
-            uint32_t rst_data_dump             :    1;
-        };
-        uint32_t val;
-    } modem_rst_conf;
-    union {
-        struct {
-            uint32_t clk_wifibb_22m_en         :    1;
-            uint32_t clk_wifibb_40m_en         :    1;
-            uint32_t clk_wifibb_44m_en         :    1;
-            uint32_t clk_wifibb_80m_en         :    1;
-            uint32_t clk_wifibb_40x_en         :    1;
-            uint32_t clk_wifibb_80x_en         :    1;
-            uint32_t clk_wifibb_40x1_en        :    1;
-            uint32_t clk_wifibb_80x1_en        :    1;
-            uint32_t clk_wifibb_160x1_en       :    1;
-            uint32_t clk_wifimac_en            :    1;
-            uint32_t clk_wifi_apb_en           :    1;
-            uint32_t clk_fe_20m_en             :    1;
-            uint32_t clk_fe_40m_en             :    1;
-            uint32_t clk_fe_80m_en             :    1;
-            uint32_t clk_fe_160m_en            :    1;
-            uint32_t clk_fe_apb_en             :    1;
-            uint32_t clk_bt_apb_en             :    1;
-            uint32_t clk_btbb_en               :    1;
-            uint32_t clk_btmac_en              :    1;
-            uint32_t clk_fe_pwdet_adc_en       :    1;
-            uint32_t clk_fe_adc_en             :    1;
-            uint32_t clk_fe_dac_en             :    1;
-            uint32_t reserved22                :    1;
-            uint32_t reserved23                :    1;
-            uint32_t reserved24                :    8;
-        };
-        uint32_t val;
-    } clk_conf1;
-    uint32_t wifi_bb_cfg;
-    uint32_t mem_rf1_conf;
-    uint32_t mem_rf2_conf;
-    union {
-        struct {
-            uint32_t date                      :    28;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } date;
-} modem_syscon_dev_t;
-
-extern modem_syscon_dev_t MODEM_SYSCON;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/modem/reg_base.h b/components/soc/esp32c5/beta3/include/modem/reg_base.h
deleted file mode 100644
index 7a0254eac0..0000000000
--- a/components/soc/esp32c5/beta3/include/modem/reg_base.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-#define DR_REG_MODEM_SYSCON_BASE  0x600A9800
-#define DR_REG_MODEM_LPCON_BASE   0x600AF000
diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
deleted file mode 100644
index 0ecb474523..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
+++ /dev/null
@@ -1,872 +0,0 @@
-#####################################################
-# This file is auto-generated from SoC caps
-# using gen_soc_caps_kconfig.py, do not edit manually
-#####################################################
-
-config SOC_UART_SUPPORTED
-    bool
-    default y
-
-config SOC_GDMA_SUPPORTED
-    bool
-    default y
-
-config SOC_AHB_GDMA_SUPPORTED
-    bool
-    default y
-
-config SOC_GPTIMER_SUPPORTED
-    bool
-    default y
-
-config SOC_PCNT_SUPPORTED
-    bool
-    default y
-
-config SOC_ASYNC_MEMCPY_SUPPORTED
-    bool
-    default y
-
-config SOC_PHY_SUPPORTED
-    bool
-    default y
-
-config SOC_WIFI_SUPPORTED
-    bool
-    default y
-
-config SOC_SUPPORTS_SECURE_DL_MODE
-    bool
-    default y
-
-config SOC_EFUSE_KEY_PURPOSE_FIELD
-    bool
-    default y
-
-config SOC_EFUSE_SUPPORTED
-    bool
-    default y
-
-config SOC_RTC_FAST_MEM_SUPPORTED
-    bool
-    default y
-
-config SOC_RTC_MEM_SUPPORTED
-    bool
-    default y
-
-config SOC_IEEE802154_SUPPORTED
-    bool
-    default y
-
-config SOC_RMT_SUPPORTED
-    bool
-    default y
-
-config SOC_GPSPI_SUPPORTED
-    bool
-    default y
-
-config SOC_I2C_SUPPORTED
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORTED
-    bool
-    default y
-
-config SOC_AES_SUPPORTED
-    bool
-    default y
-
-config SOC_MPI_SUPPORTED
-    bool
-    default y
-
-config SOC_SHA_SUPPORTED
-    bool
-    default y
-
-config SOC_RSA_SUPPORTED
-    bool
-    default y
-
-config SOC_HMAC_SUPPORTED
-    bool
-    default y
-
-config SOC_DIG_SIGN_SUPPORTED
-    bool
-    default y
-
-config SOC_ECC_SUPPORTED
-    bool
-    default y
-
-config SOC_ECC_EXTENDED_MODES_SUPPORTED
-    bool
-    default y
-
-config SOC_FLASH_ENC_SUPPORTED
-    bool
-    default y
-
-config SOC_SECURE_BOOT_SUPPORTED
-    bool
-    default y
-
-config SOC_PMU_SUPPORTED
-    bool
-    default y
-
-config SOC_PAU_SUPPORTED
-    bool
-    default y
-
-config SOC_LP_TIMER_SUPPORTED
-    bool
-    default y
-
-config SOC_LP_AON_SUPPORTED
-    bool
-    default y
-
-config SOC_LP_PERIPHERALS_SUPPORTED
-    bool
-    default y
-
-config SOC_ULP_SUPPORTED
-    bool
-    default y
-
-config SOC_LP_CORE_SUPPORTED
-    bool
-    default y
-
-config SOC_SPI_FLASH_SUPPORTED
-    bool
-    default y
-
-config SOC_ECDSA_SUPPORTED
-    bool
-    default y
-
-config SOC_LIGHT_SLEEP_SUPPORTED
-    bool
-    default y
-
-config SOC_MODEM_CLOCK_SUPPORTED
-    bool
-    default y
-
-config SOC_BT_SUPPORTED
-    bool
-    default y
-
-config SOC_PM_SUPPORTED
-    bool
-    default y
-
-config SOC_XTAL_SUPPORT_40M
-    bool
-    default y
-
-config SOC_XTAL_SUPPORT_48M
-    bool
-    default y
-
-config SOC_AES_SUPPORT_DMA
-    bool
-    default y
-
-config SOC_AES_GDMA
-    bool
-    default y
-
-config SOC_AES_SUPPORT_AES_128
-    bool
-    default y
-
-config SOC_AES_SUPPORT_AES_256
-    bool
-    default y
-
-config SOC_ADC_PERIPH_NUM
-    int
-    default 1
-
-config SOC_ADC_MAX_CHANNEL_NUM
-    int
-    default 7
-
-config SOC_SHARED_IDCACHE_SUPPORTED
-    bool
-    default y
-
-config SOC_CACHE_FREEZE_SUPPORTED
-    bool
-    default y
-
-config SOC_CPU_CORES_NUM
-    int
-    default 1
-
-config SOC_CPU_INTR_NUM
-    int
-    default 32
-
-config SOC_CPU_HAS_FLEXIBLE_INTC
-    bool
-    default y
-
-config SOC_INT_CLIC_SUPPORTED
-    bool
-    default y
-
-config SOC_INT_HW_NESTED_SUPPORTED
-    bool
-    default y
-
-config SOC_BRANCH_PREDICTOR_SUPPORTED
-    bool
-    default y
-
-config SOC_CPU_BREAKPOINTS_NUM
-    int
-    default 4
-
-config SOC_CPU_WATCHPOINTS_NUM
-    int
-    default 4
-
-config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
-    hex
-    default 0x100
-
-config SOC_CPU_HAS_PMA
-    bool
-    default y
-
-config SOC_CPU_IDRAM_SPLIT_USING_PMP
-    bool
-    default y
-
-config SOC_DS_SIGNATURE_MAX_BIT_LEN
-    int
-    default 3072
-
-config SOC_DS_KEY_PARAM_MD_IV_LENGTH
-    int
-    default 16
-
-config SOC_DS_KEY_CHECK_MAX_WAIT_US
-    int
-    default 1100
-
-config SOC_AHB_GDMA_VERSION
-    int
-    default 1
-
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
-config SOC_GPIO_PORT
-    int
-    default 1
-
-config SOC_GPIO_PIN_COUNT
-    int
-    default 27
-
-config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
-    bool
-    default y
-
-config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
-    bool
-    default y
-
-config SOC_GPIO_IN_RANGE_MAX
-    int
-    default 26
-
-config SOC_GPIO_OUT_RANGE_MAX
-    int
-    default 26
-
-config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
-    int
-    default 0
-
-config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
-    hex
-    default 0x0000000007FFFF00
-
-config SOC_GPIO_SUPPORT_FORCE_HOLD
-    bool
-    default y
-
-config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
-    bool
-    default y
-
-config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
-    int
-    default 3
-
-config SOC_RTCIO_PIN_COUNT
-    int
-    default 0
-
-config SOC_I2C_NUM
-    int
-    default 1
-
-config SOC_HP_I2C_NUM
-    int
-    default 1
-
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_10BIT_ADDR
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_BROADCAST
-    bool
-    default y
-
-config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-    bool
-    default y
-
-config SOC_LEDC_SUPPORT_XTAL_CLOCK
-    bool
-    default y
-
-config SOC_LEDC_CHANNEL_NUM
-    int
-    default 6
-
-config SOC_MMU_PERIPH_NUM
-    int
-    default 1
-
-config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
-    int
-    default 1
-
-config SOC_MMU_DI_VADDR_SHARED
-    bool
-    default y
-
-config SOC_PCNT_GROUPS
-    int
-    default 1
-
-config SOC_PCNT_UNITS_PER_GROUP
-    int
-    default 4
-
-config SOC_PCNT_CHANNELS_PER_UNIT
-    int
-    default 2
-
-config SOC_PCNT_THRES_POINT_PER_UNIT
-    int
-    default 2
-
-config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
-    bool
-    default y
-
-config SOC_PCNT_SUPPORT_CLEAR_SIGNAL
-    bool
-    default y
-
-config SOC_RMT_GROUPS
-    int
-    default 1
-
-config SOC_RMT_TX_CANDIDATES_PER_GROUP
-    int
-    default 2
-
-config SOC_RMT_RX_CANDIDATES_PER_GROUP
-    int
-    default 2
-
-config SOC_RMT_CHANNELS_PER_GROUP
-    int
-    default 4
-
-config SOC_RMT_MEM_WORDS_PER_CHANNEL
-    int
-    default 48
-
-config SOC_RMT_SUPPORT_RX_PINGPONG
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_RX_DEMODULATION
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_ASYNC_STOP
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_LOOP_COUNT
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_SYNCHRO
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_MPI_MEM_BLOCKS_NUM
-    int
-    default 4
-
-config SOC_MPI_OPERATIONS_NUM
-    int
-    default 3
-
-config SOC_RSA_MAX_BIT_LEN
-    int
-    default 3072
-
-config SOC_SHA_DMA_MAX_BUFFER_SIZE
-    int
-    default 3968
-
-config SOC_SHA_SUPPORT_DMA
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_RESUME
-    bool
-    default y
-
-config SOC_SHA_GDMA
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_SHA1
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_SHA224
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_SHA256
-    bool
-    default y
-
-config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
-    bool
-    default y
-
-config SOC_SPI_PERIPH_NUM
-    int
-    default 2
-
-config SOC_SPI_MAX_CS_NUM
-    int
-    default 6
-
-config SOC_SPI_MAXIMUM_BUFFER_SIZE
-    int
-    default 64
-
-config SOC_SPI_SUPPORT_DDRCLK
-    bool
-    default y
-
-config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_CD_SIG
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_SLAVE_HD_VER2
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_CLK_XTAL
-    bool
-    default y
-
-config SOC_MEMSPI_IS_INDEPENDENT
-    bool
-    default y
-
-config SOC_SPI_MAX_PRE_DIVIDER
-    int
-    default 256
-
-config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
-    bool
-    default y
-
-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
-config SOC_LP_TIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_LP_TIMER_BIT_WIDTH_HI
-    int
-    default 16
-
-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
-config SOC_EFUSE_ECDSA_KEY
-    bool
-    default y
-
-config SOC_SECURE_BOOT_V2_RSA
-    bool
-    default y
-
-config SOC_SECURE_BOOT_V2_ECC
-    bool
-    default y
-
-config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
-    int
-    default 3
-
-config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
-    bool
-    default y
-
-config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
-    bool
-    default y
-
-config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
-    int
-    default 64
-
-config SOC_FLASH_ENCRYPTION_XTS_AES
-    bool
-    default y
-
-config SOC_FLASH_ENCRYPTION_XTS_AES_128
-    bool
-    default y
-
-config SOC_UART_NUM
-    int
-    default 3
-
-config SOC_UART_HP_NUM
-    int
-    default 2
-
-config SOC_UART_LP_NUM
-    int
-    default 1
-
-config SOC_UART_FIFO_LEN
-    int
-    default 128
-
-config SOC_LP_UART_FIFO_LEN
-    int
-    default 16
-
-config SOC_UART_BITRATE_MAX
-    int
-    default 5000000
-
-config SOC_UART_SUPPORT_PLL_F80M_CLK
-    bool
-    default y
-
-config SOC_UART_SUPPORT_XTAL_CLK
-    bool
-    default y
-
-config SOC_UART_SUPPORT_WAKEUP_INT
-    bool
-    default y
-
-config SOC_UART_HAS_LP_UART
-    bool
-    default y
-
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
-config SOC_UART_SUPPORT_SLEEP_RETENTION
-    bool
-    default y
-
-config SOC_COEX_HW_PTI
-    bool
-    default y
-
-config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
-    int
-    default 12
-
-config SOC_PM_SUPPORT_CPU_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_MODEM_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_XTAL32K_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_RC32K_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_RC_FAST_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_VDDSDIO_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_TOP_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_HP_AON_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_RTC_PERIPH_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_PMU_MODEM_STATE
-    bool
-    default n
-
-config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
-    bool
-    default y
-
-config SOC_PM_CPU_RETENTION_BY_SW
-    bool
-    default y
-
-config SOC_PM_MODEM_RETENTION_BY_REGDMA
-    bool
-    default y
-
-config SOC_PM_PAU_LINK_NUM
-    int
-    default 4
-
-config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
-    bool
-    default y
-
-config SOC_MODEM_CLOCK_IS_INDEPENDENT
-    bool
-    default y
-
-config SOC_CLK_XTAL32K_SUPPORTED
-    bool
-    default y
-
-config SOC_CLK_OSC_SLOW_SUPPORTED
-    bool
-    default y
-
-config SOC_CLK_RC32K_SUPPORTED
-    bool
-    default y
-
-config SOC_RCC_IS_INDEPENDENT
-    bool
-    default y
-
-config SOC_WIFI_HW_TSF
-    bool
-    default y
-
-config SOC_WIFI_FTM_SUPPORT
-    bool
-    default n
-
-config SOC_WIFI_GCMP_SUPPORT
-    bool
-    default y
-
-config SOC_WIFI_WAPI_SUPPORT
-    bool
-    default y
-
-config SOC_WIFI_CSI_SUPPORT
-    bool
-    default y
-
-config SOC_WIFI_MESH_SUPPORT
-    bool
-    default y
-
-config SOC_WIFI_HE_SUPPORT
-    bool
-    default y
-
-config SOC_WIFI_HE_SUPPORT_5G
-    bool
-    default y
-
-config SOC_BLE_SUPPORTED
-    bool
-    default y
-
-config SOC_BLE_MESH_SUPPORTED
-    bool
-    default y
-
-config SOC_ESP_NIMBLE_CONTROLLER
-    bool
-    default y
-
-config SOC_BLE_50_SUPPORTED
-    bool
-    default y
-
-config SOC_BLE_DEVICE_PRIVACY_SUPPORTED
-    bool
-    default y
-
-config SOC_BLE_POWER_CONTROL_SUPPORTED
-    bool
-    default y
-
-config SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED
-    bool
-    default y
-
-config SOC_BLUFI_SUPPORTED
-    bool
-    default y
-
-config SOC_BLE_MULTI_CONN_OPTIMIZATION
-    bool
-    default y
diff --git a/components/soc/esp32c5/beta3/include/soc/aes_reg.h b/components/soc/esp32c5/beta3/include/soc/aes_reg.h
deleted file mode 100644
index fbf892dae7..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/aes_reg.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** AES_KEY_0_REG register
- *  Key material key_0 configure register
- */
-#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
-/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_0 that is a part of key material.
- */
-#define AES_KEY_0    0xFFFFFFFFU
-#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
-#define AES_KEY_0_V  0xFFFFFFFFU
-#define AES_KEY_0_S  0
-
-/** AES_KEY_1_REG register
- *  Key material key_1 configure register
- */
-#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
-/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_1 that is a part of key material.
- */
-#define AES_KEY_1    0xFFFFFFFFU
-#define AES_KEY_1_M  (AES_KEY_1_V << AES_KEY_1_S)
-#define AES_KEY_1_V  0xFFFFFFFFU
-#define AES_KEY_1_S  0
-
-/** AES_KEY_2_REG register
- *  Key material key_2 configure register
- */
-#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
-/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_2 that is a part of key material.
- */
-#define AES_KEY_2    0xFFFFFFFFU
-#define AES_KEY_2_M  (AES_KEY_2_V << AES_KEY_2_S)
-#define AES_KEY_2_V  0xFFFFFFFFU
-#define AES_KEY_2_S  0
-
-/** AES_KEY_3_REG register
- *  Key material key_3 configure register
- */
-#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
-/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_3 that is a part of key material.
- */
-#define AES_KEY_3    0xFFFFFFFFU
-#define AES_KEY_3_M  (AES_KEY_3_V << AES_KEY_3_S)
-#define AES_KEY_3_V  0xFFFFFFFFU
-#define AES_KEY_3_S  0
-
-/** AES_KEY_4_REG register
- *  Key material key_4 configure register
- */
-#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
-/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_4 that is a part of key material.
- */
-#define AES_KEY_4    0xFFFFFFFFU
-#define AES_KEY_4_M  (AES_KEY_4_V << AES_KEY_4_S)
-#define AES_KEY_4_V  0xFFFFFFFFU
-#define AES_KEY_4_S  0
-
-/** AES_KEY_5_REG register
- *  Key material key_5 configure register
- */
-#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
-/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_5 that is a part of key material.
- */
-#define AES_KEY_5    0xFFFFFFFFU
-#define AES_KEY_5_M  (AES_KEY_5_V << AES_KEY_5_S)
-#define AES_KEY_5_V  0xFFFFFFFFU
-#define AES_KEY_5_S  0
-
-/** AES_KEY_6_REG register
- *  Key material key_6 configure register
- */
-#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
-/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_6 that is a part of key material.
- */
-#define AES_KEY_6    0xFFFFFFFFU
-#define AES_KEY_6_M  (AES_KEY_6_V << AES_KEY_6_S)
-#define AES_KEY_6_V  0xFFFFFFFFU
-#define AES_KEY_6_S  0
-
-/** AES_KEY_7_REG register
- *  Key material key_7 configure register
- */
-#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
-/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores key_7 that is a part of key material.
- */
-#define AES_KEY_7    0xFFFFFFFFU
-#define AES_KEY_7_M  (AES_KEY_7_V << AES_KEY_7_S)
-#define AES_KEY_7_V  0xFFFFFFFFU
-#define AES_KEY_7_S  0
-
-/** AES_TEXT_IN_0_REG register
- *  source text material text_in_0 configure register
- */
-#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
-/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_in_0 that is a part of source text material.
- */
-#define AES_TEXT_IN_0    0xFFFFFFFFU
-#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
-#define AES_TEXT_IN_0_V  0xFFFFFFFFU
-#define AES_TEXT_IN_0_S  0
-
-/** AES_TEXT_IN_1_REG register
- *  source text material text_in_1 configure register
- */
-#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
-/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_in_1 that is a part of source text material.
- */
-#define AES_TEXT_IN_1    0xFFFFFFFFU
-#define AES_TEXT_IN_1_M  (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
-#define AES_TEXT_IN_1_V  0xFFFFFFFFU
-#define AES_TEXT_IN_1_S  0
-
-/** AES_TEXT_IN_2_REG register
- *  source text material text_in_2 configure register
- */
-#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
-/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_in_2 that is a part of source text material.
- */
-#define AES_TEXT_IN_2    0xFFFFFFFFU
-#define AES_TEXT_IN_2_M  (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
-#define AES_TEXT_IN_2_V  0xFFFFFFFFU
-#define AES_TEXT_IN_2_S  0
-
-/** AES_TEXT_IN_3_REG register
- *  source text material text_in_3 configure register
- */
-#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
-/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_in_3 that is a part of source text material.
- */
-#define AES_TEXT_IN_3    0xFFFFFFFFU
-#define AES_TEXT_IN_3_M  (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
-#define AES_TEXT_IN_3_V  0xFFFFFFFFU
-#define AES_TEXT_IN_3_S  0
-
-/** AES_TEXT_OUT_0_REG register
- *  result text material text_out_0 configure register
- */
-#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
-/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_out_0 that is a part of result text material.
- */
-#define AES_TEXT_OUT_0    0xFFFFFFFFU
-#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
-#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
-#define AES_TEXT_OUT_0_S  0
-
-/** AES_TEXT_OUT_1_REG register
- *  result text material text_out_1 configure register
- */
-#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
-/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_out_1 that is a part of result text material.
- */
-#define AES_TEXT_OUT_1    0xFFFFFFFFU
-#define AES_TEXT_OUT_1_M  (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
-#define AES_TEXT_OUT_1_V  0xFFFFFFFFU
-#define AES_TEXT_OUT_1_S  0
-
-/** AES_TEXT_OUT_2_REG register
- *  result text material text_out_2 configure register
- */
-#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
-/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_out_2 that is a part of result text material.
- */
-#define AES_TEXT_OUT_2    0xFFFFFFFFU
-#define AES_TEXT_OUT_2_M  (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
-#define AES_TEXT_OUT_2_V  0xFFFFFFFFU
-#define AES_TEXT_OUT_2_S  0
-
-/** AES_TEXT_OUT_3_REG register
- *  result text material text_out_3 configure register
- */
-#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
-/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
- *  This bits stores text_out_3 that is a part of result text material.
- */
-#define AES_TEXT_OUT_3    0xFFFFFFFFU
-#define AES_TEXT_OUT_3_M  (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
-#define AES_TEXT_OUT_3_V  0xFFFFFFFFU
-#define AES_TEXT_OUT_3_S  0
-
-/** AES_MODE_REG register
- *  AES Mode register
- */
-#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
-/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
- *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
- *  AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
- */
-#define AES_MODE    0x00000007U
-#define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
-#define AES_MODE_V  0x00000007U
-#define AES_MODE_S  0
-
-/** AES_TRIGGER_REG register
- *  AES trigger register
- */
-#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
-/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
- *  Set this bit to start AES calculation.
- */
-#define AES_TRIGGER    (BIT(0))
-#define AES_TRIGGER_M  (AES_TRIGGER_V << AES_TRIGGER_S)
-#define AES_TRIGGER_V  0x00000001U
-#define AES_TRIGGER_S  0
-
-/** AES_STATE_REG register
- *  AES state register
- */
-#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
-/** AES_STATE : RO; bitpos: [1:0]; default: 0;
- *  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
- *  idle, 1: busy, 2: calculation_done.
- */
-#define AES_STATE    0x00000003U
-#define AES_STATE_M  (AES_STATE_V << AES_STATE_S)
-#define AES_STATE_V  0x00000003U
-#define AES_STATE_S  0
-
-/** AES_IV_MEM register
- *  The memory that stores initialization vector
- */
-#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
-#define AES_IV_MEM_SIZE_BYTES 16
-
-/** AES_H_MEM register
- *  The memory that stores GCM hash subkey
- */
-#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
-#define AES_H_MEM_SIZE_BYTES 16
-
-/** AES_J0_MEM register
- *  The memory that stores J0
- */
-#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
-#define AES_J0_MEM_SIZE_BYTES 16
-
-/** AES_T0_MEM register
- *  The memory that stores T0
- */
-#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
-#define AES_T0_MEM_SIZE_BYTES 16
-
-/** AES_DMA_ENABLE_REG register
- *  DMA-AES working mode register
- */
-#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
-/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
- *  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
- */
-#define AES_DMA_ENABLE    (BIT(0))
-#define AES_DMA_ENABLE_M  (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
-#define AES_DMA_ENABLE_V  0x00000001U
-#define AES_DMA_ENABLE_S  0
-
-/** AES_BLOCK_MODE_REG register
- *  AES cipher block mode register
- */
-#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
-/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
- *  0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
- */
-#define AES_BLOCK_MODE    0x00000007U
-#define AES_BLOCK_MODE_M  (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
-#define AES_BLOCK_MODE_V  0x00000007U
-#define AES_BLOCK_MODE_S  0
-
-/** AES_BLOCK_NUM_REG register
- *  AES block number register
- */
-#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
-/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
- *  Those bits stores the number of Plaintext/ciphertext block.
- */
-#define AES_BLOCK_NUM    0xFFFFFFFFU
-#define AES_BLOCK_NUM_M  (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
-#define AES_BLOCK_NUM_V  0xFFFFFFFFU
-#define AES_BLOCK_NUM_S  0
-
-/** AES_INC_SEL_REG register
- *  Standard incrementing function configure register
- */
-#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
-/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
- *  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
- */
-#define AES_INC_SEL    (BIT(0))
-#define AES_INC_SEL_M  (AES_INC_SEL_V << AES_INC_SEL_S)
-#define AES_INC_SEL_V  0x00000001U
-#define AES_INC_SEL_S  0
-
-/** AES_INT_CLEAR_REG register
- *  AES Interrupt clear register
- */
-#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
-/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the AES interrupt.
- */
-#define AES_INT_CLEAR    (BIT(0))
-#define AES_INT_CLEAR_M  (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
-#define AES_INT_CLEAR_V  0x00000001U
-#define AES_INT_CLEAR_S  0
-
-/** AES_INT_ENA_REG register
- *  AES Interrupt enable register
- */
-#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
-/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
- */
-#define AES_INT_ENA    (BIT(0))
-#define AES_INT_ENA_M  (AES_INT_ENA_V << AES_INT_ENA_S)
-#define AES_INT_ENA_V  0x00000001U
-#define AES_INT_ENA_S  0
-
-/** AES_DATE_REG register
- *  AES version control register
- */
-#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
-/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
- *  This bits stores the version information of AES.
- */
-#define AES_DATE    0x3FFFFFFFU
-#define AES_DATE_M  (AES_DATE_V << AES_DATE_S)
-#define AES_DATE_V  0x3FFFFFFFU
-#define AES_DATE_S  0
-
-/** AES_DMA_EXIT_REG register
- *  AES-DMA exit config
- */
-#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
-/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
- *  Set this register to leave calculation done stage. Recommend to use it after
- *  software finishes reading DMA's output buffer.
- */
-#define AES_DMA_EXIT    (BIT(0))
-#define AES_DMA_EXIT_M  (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
-#define AES_DMA_EXIT_V  0x00000001U
-#define AES_DMA_EXIT_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/aes_struct.h b/components/soc/esp32c5/beta3/include/soc/aes_struct.h
deleted file mode 100644
index c337d9ceec..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/aes_struct.h
+++ /dev/null
@@ -1,438 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: key register */
-/** Type of key_0 register
- *  Key material key_0 configure register
- */
-typedef union {
-    struct {
-        /** key_0 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_0 that is a part of key material.
-         */
-        uint32_t key_0:32;
-    };
-    uint32_t val;
-} aes_key_0_reg_t;
-
-/** Type of key_1 register
- *  Key material key_1 configure register
- */
-typedef union {
-    struct {
-        /** key_1 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_1 that is a part of key material.
-         */
-        uint32_t key_1:32;
-    };
-    uint32_t val;
-} aes_key_1_reg_t;
-
-/** Type of key_2 register
- *  Key material key_2 configure register
- */
-typedef union {
-    struct {
-        /** key_2 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_2 that is a part of key material.
-         */
-        uint32_t key_2:32;
-    };
-    uint32_t val;
-} aes_key_2_reg_t;
-
-/** Type of key_3 register
- *  Key material key_3 configure register
- */
-typedef union {
-    struct {
-        /** key_3 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_3 that is a part of key material.
-         */
-        uint32_t key_3:32;
-    };
-    uint32_t val;
-} aes_key_3_reg_t;
-
-/** Type of key_4 register
- *  Key material key_4 configure register
- */
-typedef union {
-    struct {
-        /** key_4 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_4 that is a part of key material.
-         */
-        uint32_t key_4:32;
-    };
-    uint32_t val;
-} aes_key_4_reg_t;
-
-/** Type of key_5 register
- *  Key material key_5 configure register
- */
-typedef union {
-    struct {
-        /** key_5 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_5 that is a part of key material.
-         */
-        uint32_t key_5:32;
-    };
-    uint32_t val;
-} aes_key_5_reg_t;
-
-/** Type of key_6 register
- *  Key material key_6 configure register
- */
-typedef union {
-    struct {
-        /** key_6 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_6 that is a part of key material.
-         */
-        uint32_t key_6:32;
-    };
-    uint32_t val;
-} aes_key_6_reg_t;
-
-/** Type of key_7 register
- *  Key material key_7 configure register
- */
-typedef union {
-    struct {
-        /** key_7 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores key_7 that is a part of key material.
-         */
-        uint32_t key_7:32;
-    };
-    uint32_t val;
-} aes_key_7_reg_t;
-
-
-/** Group: text in register */
-/** Type of text_in_0 register
- *  source text material text_in_0 configure register
- */
-typedef union {
-    struct {
-        /** text_in_0 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_in_0 that is a part of source text material.
-         */
-        uint32_t text_in_0:32;
-    };
-    uint32_t val;
-} aes_text_in_0_reg_t;
-
-/** Type of text_in_1 register
- *  source text material text_in_1 configure register
- */
-typedef union {
-    struct {
-        /** text_in_1 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_in_1 that is a part of source text material.
-         */
-        uint32_t text_in_1:32;
-    };
-    uint32_t val;
-} aes_text_in_1_reg_t;
-
-/** Type of text_in_2 register
- *  source text material text_in_2 configure register
- */
-typedef union {
-    struct {
-        /** text_in_2 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_in_2 that is a part of source text material.
-         */
-        uint32_t text_in_2:32;
-    };
-    uint32_t val;
-} aes_text_in_2_reg_t;
-
-/** Type of text_in_3 register
- *  source text material text_in_3 configure register
- */
-typedef union {
-    struct {
-        /** text_in_3 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_in_3 that is a part of source text material.
-         */
-        uint32_t text_in_3:32;
-    };
-    uint32_t val;
-} aes_text_in_3_reg_t;
-
-
-/** Group: text out register */
-/** Type of text_out_0 register
- *  result text material text_out_0 configure register
- */
-typedef union {
-    struct {
-        /** text_out_0 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_out_0 that is a part of result text material.
-         */
-        uint32_t text_out_0:32;
-    };
-    uint32_t val;
-} aes_text_out_0_reg_t;
-
-/** Type of text_out_1 register
- *  result text material text_out_1 configure register
- */
-typedef union {
-    struct {
-        /** text_out_1 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_out_1 that is a part of result text material.
-         */
-        uint32_t text_out_1:32;
-    };
-    uint32_t val;
-} aes_text_out_1_reg_t;
-
-/** Type of text_out_2 register
- *  result text material text_out_2 configure register
- */
-typedef union {
-    struct {
-        /** text_out_2 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_out_2 that is a part of result text material.
-         */
-        uint32_t text_out_2:32;
-    };
-    uint32_t val;
-} aes_text_out_2_reg_t;
-
-/** Type of text_out_3 register
- *  result text material text_out_3 configure register
- */
-typedef union {
-    struct {
-        /** text_out_3 : R/W; bitpos: [31:0]; default: 0;
-         *  This bits stores text_out_3 that is a part of result text material.
-         */
-        uint32_t text_out_3:32;
-    };
-    uint32_t val;
-} aes_text_out_3_reg_t;
-
-
-/** Group: Configuration register */
-/** Type of mode register
- *  AES Mode register
- */
-typedef union {
-    struct {
-        /** mode : R/W; bitpos: [2:0]; default: 0;
-         *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
-         *  AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
-         */
-        uint32_t mode:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} aes_mode_reg_t;
-
-/** Type of block_mode register
- *  AES cipher block mode register
- */
-typedef union {
-    struct {
-        /** block_mode : R/W; bitpos: [2:0]; default: 0;
-         *  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
-         *  0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
-         */
-        uint32_t block_mode:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} aes_block_mode_reg_t;
-
-/** Type of block_num register
- *  AES block number register
- */
-typedef union {
-    struct {
-        /** block_num : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits stores the number of Plaintext/ciphertext block.
-         */
-        uint32_t block_num:32;
-    };
-    uint32_t val;
-} aes_block_num_reg_t;
-
-/** Type of inc_sel register
- *  Standard incrementing function configure register
- */
-typedef union {
-    struct {
-        /** inc_sel : R/W; bitpos: [0]; default: 0;
-         *  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
-         */
-        uint32_t inc_sel:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} aes_inc_sel_reg_t;
-
-
-/** Group: Control/Status register */
-/** Type of trigger register
- *  AES trigger register
- */
-typedef union {
-    struct {
-        /** trigger : WT; bitpos: [0]; default: 0;
-         *  Set this bit to start AES calculation.
-         */
-        uint32_t trigger:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} aes_trigger_reg_t;
-
-/** Type of state register
- *  AES state register
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [1:0]; default: 0;
-         *  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
-         *  idle, 1: busy, 2: calculation_done.
-         */
-        uint32_t state:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} aes_state_reg_t;
-
-/** Type of dma_enable register
- *  DMA-AES working mode register
- */
-typedef union {
-    struct {
-        /** dma_enable : R/W; bitpos: [0]; default: 0;
-         *  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
-         */
-        uint32_t dma_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} aes_dma_enable_reg_t;
-
-/** Type of dma_exit register
- *  AES-DMA exit config
- */
-typedef union {
-    struct {
-        /** dma_exit : WT; bitpos: [0]; default: 0;
-         *  Set this register to leave calculation done stage. Recommend to use it after
-         *  software finishes reading DMA's output buffer.
-         */
-        uint32_t dma_exit:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} aes_dma_exit_reg_t;
-
-
-/** Group: memory type */
-
-/** Group: interrupt register */
-/** Type of int_clear register
- *  AES Interrupt clear register
- */
-typedef union {
-    struct {
-        /** int_clear : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the AES interrupt.
-         */
-        uint32_t int_clear:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} aes_int_clear_reg_t;
-
-/** Type of int_ena register
- *  AES Interrupt enable register
- */
-typedef union {
-    struct {
-        /** int_ena : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
-         */
-        uint32_t int_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} aes_int_ena_reg_t;
-
-
-/** Group: Version control register */
-/** Type of date register
- *  AES version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [29:0]; default: 538513936;
-         *  This bits stores the version information of AES.
-         */
-        uint32_t date:30;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} aes_date_reg_t;
-
-
-typedef struct aes_dev_t {
-    volatile aes_key_0_reg_t key_0;
-    volatile aes_key_1_reg_t key_1;
-    volatile aes_key_2_reg_t key_2;
-    volatile aes_key_3_reg_t key_3;
-    volatile aes_key_4_reg_t key_4;
-    volatile aes_key_5_reg_t key_5;
-    volatile aes_key_6_reg_t key_6;
-    volatile aes_key_7_reg_t key_7;
-    volatile aes_text_in_0_reg_t text_in_0;
-    volatile aes_text_in_1_reg_t text_in_1;
-    volatile aes_text_in_2_reg_t text_in_2;
-    volatile aes_text_in_3_reg_t text_in_3;
-    volatile aes_text_out_0_reg_t text_out_0;
-    volatile aes_text_out_1_reg_t text_out_1;
-    volatile aes_text_out_2_reg_t text_out_2;
-    volatile aes_text_out_3_reg_t text_out_3;
-    volatile aes_mode_reg_t mode;
-    uint32_t reserved_044;
-    volatile aes_trigger_reg_t trigger;
-    volatile aes_state_reg_t state;
-    volatile uint32_t iv[4];
-    volatile uint32_t h[4];
-    volatile uint32_t j0[4];
-    volatile uint32_t t0[4];
-    volatile aes_dma_enable_reg_t dma_enable;
-    volatile aes_block_mode_reg_t block_mode;
-    volatile aes_block_num_reg_t block_num;
-    volatile aes_inc_sel_reg_t inc_sel;
-    uint32_t reserved_0a0[3];
-    volatile aes_int_clear_reg_t int_clear;
-    volatile aes_int_ena_reg_t int_ena;
-    volatile aes_date_reg_t date;
-    volatile aes_dma_exit_reg_t dma_exit;
-} aes_dev_t;
-
-extern aes_dev_t AES;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(aes_dev_t) == 0xbc, "Invalid size of aes_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/beta3/include/soc/apb_saradc_reg.h
deleted file mode 100644
index 179fe6a7d6..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/apb_saradc_reg.h
+++ /dev/null
@@ -1,813 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** APB_SARADC_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
-/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
- *  select software enable saradc sample
- */
-#define APB_SARADC_SARADC_START_FORCE    (BIT(0))
-#define APB_SARADC_SARADC_START_FORCE_M  (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S)
-#define APB_SARADC_SARADC_START_FORCE_V  0x00000001U
-#define APB_SARADC_SARADC_START_FORCE_S  0
-/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0;
- *  software enable saradc sample
- */
-#define APB_SARADC_SARADC_START    (BIT(1))
-#define APB_SARADC_SARADC_START_M  (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S)
-#define APB_SARADC_SARADC_START_V  0x00000001U
-#define APB_SARADC_SARADC_START_S  1
-/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
- *  SAR clock gated
- */
-#define APB_SARADC_SARADC_SAR_CLK_GATED    (BIT(6))
-#define APB_SARADC_SARADC_SAR_CLK_GATED_M  (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S)
-#define APB_SARADC_SARADC_SAR_CLK_GATED_V  0x00000001U
-#define APB_SARADC_SARADC_SAR_CLK_GATED_S  6
-/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
- *  SAR clock divider
- */
-#define APB_SARADC_SARADC_SAR_CLK_DIV    0x000000FFU
-#define APB_SARADC_SARADC_SAR_CLK_DIV_M  (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S)
-#define APB_SARADC_SARADC_SAR_CLK_DIV_V  0x000000FFU
-#define APB_SARADC_SARADC_SAR_CLK_DIV_S  7
-/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
- *  0 ~ 15 means length 1 ~ 16
- */
-#define APB_SARADC_SARADC_SAR_PATT_LEN    0x00000007U
-#define APB_SARADC_SARADC_SAR_PATT_LEN_M  (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S)
-#define APB_SARADC_SARADC_SAR_PATT_LEN_V  0x00000007U
-#define APB_SARADC_SARADC_SAR_PATT_LEN_S  15
-/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
- *  clear the pointer of pattern table for DIG ADC1 CTRL
- */
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR    (BIT(23))
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M  (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S)
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V  0x00000001U
-#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S  23
-/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
- *  force option to xpd sar blocks
- */
-#define APB_SARADC_SARADC_XPD_SAR_FORCE    0x00000003U
-#define APB_SARADC_SARADC_XPD_SAR_FORCE_M  (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S)
-#define APB_SARADC_SARADC_XPD_SAR_FORCE_V  0x00000003U
-#define APB_SARADC_SARADC_XPD_SAR_FORCE_S  27
-/** APB_SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
- *  enable saradc2 power detect driven func.
- */
-#define APB_SARADC_SARADC2_PWDET_DRV    (BIT(29))
-#define APB_SARADC_SARADC2_PWDET_DRV_M  (APB_SARADC_SARADC2_PWDET_DRV_V << APB_SARADC_SARADC2_PWDET_DRV_S)
-#define APB_SARADC_SARADC2_PWDET_DRV_V  0x00000001U
-#define APB_SARADC_SARADC2_PWDET_DRV_S  29
-/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
- *  wait arbit signal stable after sar_done
- */
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE    0x00000003U
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M  (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S)
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V  0x00000003U
-#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S  30
-
-/** APB_SARADC_CTRL2_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
-/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
- *  enable max meas num
- */
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT    (BIT(0))
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M  (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S)
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V  0x00000001U
-#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S  0
-/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
- *  max conversion number
- */
-#define APB_SARADC_SARADC_MAX_MEAS_NUM    0x000000FFU
-#define APB_SARADC_SARADC_MAX_MEAS_NUM_M  (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S)
-#define APB_SARADC_SARADC_MAX_MEAS_NUM_V  0x000000FFU
-#define APB_SARADC_SARADC_MAX_MEAS_NUM_S  1
-/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
- *  1: data to DIG ADC1 CTRL is inverted, otherwise not
- */
-#define APB_SARADC_SARADC_SAR1_INV    (BIT(9))
-#define APB_SARADC_SARADC_SAR1_INV_M  (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S)
-#define APB_SARADC_SARADC_SAR1_INV_V  0x00000001U
-#define APB_SARADC_SARADC_SAR1_INV_S  9
-/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
- *  1: data to DIG ADC2 CTRL is inverted, otherwise not
- */
-#define APB_SARADC_SARADC_SAR2_INV    (BIT(10))
-#define APB_SARADC_SARADC_SAR2_INV_M  (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S)
-#define APB_SARADC_SARADC_SAR2_INV_V  0x00000001U
-#define APB_SARADC_SARADC_SAR2_INV_S  10
-/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
- *  to set saradc timer target
- */
-#define APB_SARADC_SARADC_TIMER_TARGET    0x00000FFFU
-#define APB_SARADC_SARADC_TIMER_TARGET_M  (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S)
-#define APB_SARADC_SARADC_TIMER_TARGET_V  0x00000FFFU
-#define APB_SARADC_SARADC_TIMER_TARGET_S  12
-/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
- *  to enable saradc timer trigger
- */
-#define APB_SARADC_SARADC_TIMER_EN    (BIT(24))
-#define APB_SARADC_SARADC_TIMER_EN_M  (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S)
-#define APB_SARADC_SARADC_TIMER_EN_V  0x00000001U
-#define APB_SARADC_SARADC_TIMER_EN_S  24
-
-/** APB_SARADC_FILTER_CTRL1_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
-/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
- *  Factor of saradc filter1
- */
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1    0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_M  (APB_SARADC_APB_SARADC_FILTER_FACTOR1_V << APB_SARADC_APB_SARADC_FILTER_FACTOR1_S)
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_V  0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR1_S  26
-/** APB_SARADC_APB_SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
- *  Factor of saradc filter0
- */
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0    0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_M  (APB_SARADC_APB_SARADC_FILTER_FACTOR0_V << APB_SARADC_APB_SARADC_FILTER_FACTOR0_S)
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_V  0x00000007U
-#define APB_SARADC_APB_SARADC_FILTER_FACTOR0_S  29
-
-/** APB_SARADC_SAR_PATT_TAB1_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
-/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
- *  item 0 ~ 3 for pattern table 1 (each item one byte)
- */
-#define APB_SARADC_SARADC_SAR_PATT_TAB1    0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB1_M  (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S)
-#define APB_SARADC_SARADC_SAR_PATT_TAB1_V  0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB1_S  0
-
-/** APB_SARADC_SAR_PATT_TAB2_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
-/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
- *  Item 4 ~ 7 for pattern table 1 (each item one byte)
- */
-#define APB_SARADC_SARADC_SAR_PATT_TAB2    0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB2_M  (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S)
-#define APB_SARADC_SARADC_SAR_PATT_TAB2_V  0x00FFFFFFU
-#define APB_SARADC_SARADC_SAR_PATT_TAB2_S  0
-
-/** APB_SARADC_ONETIME_SAMPLE_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
-/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
- *  configure onetime atten
- */
-#define APB_SARADC_SARADC_ONETIME_ATTEN    0x00000003U
-#define APB_SARADC_SARADC_ONETIME_ATTEN_M  (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S)
-#define APB_SARADC_SARADC_ONETIME_ATTEN_V  0x00000003U
-#define APB_SARADC_SARADC_ONETIME_ATTEN_S  23
-/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
- *  configure onetime channel
- */
-#define APB_SARADC_SARADC_ONETIME_CHANNEL    0x0000000FU
-#define APB_SARADC_SARADC_ONETIME_CHANNEL_M  (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S)
-#define APB_SARADC_SARADC_ONETIME_CHANNEL_V  0x0000000FU
-#define APB_SARADC_SARADC_ONETIME_CHANNEL_S  25
-/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
- *  trigger adc onetime sample
- */
-#define APB_SARADC_SARADC_ONETIME_START    (BIT(29))
-#define APB_SARADC_SARADC_ONETIME_START_M  (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S)
-#define APB_SARADC_SARADC_ONETIME_START_V  0x00000001U
-#define APB_SARADC_SARADC_ONETIME_START_S  29
-/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
- *  enable adc2 onetime sample
- */
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE    (BIT(30))
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M  (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S)
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V  0x00000001U
-#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S  30
-/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
- *  enable adc1 onetime sample
- */
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE    (BIT(31))
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M  (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S)
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V  0x00000001U
-#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S  31
-
-/** APB_SARADC_ARB_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
-/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
- *  adc2 arbiter force to enableapb controller
- */
-#define APB_SARADC_ADC_ARB_APB_FORCE    (BIT(2))
-#define APB_SARADC_ADC_ARB_APB_FORCE_M  (APB_SARADC_ADC_ARB_APB_FORCE_V << APB_SARADC_ADC_ARB_APB_FORCE_S)
-#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
-/** APB_SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
- *  adc2 arbiter force to enable rtc controller
- */
-#define APB_SARADC_ADC_ARB_RTC_FORCE    (BIT(3))
-#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (APB_SARADC_ADC_ARB_RTC_FORCE_V << APB_SARADC_ADC_ARB_RTC_FORCE_S)
-#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
-/** APB_SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
- *  adc2 arbiter force to enable wifi controller
- */
-#define APB_SARADC_ADC_ARB_WIFI_FORCE    (BIT(4))
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (APB_SARADC_ADC_ARB_WIFI_FORCE_V << APB_SARADC_ADC_ARB_WIFI_FORCE_S)
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
-/** APB_SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
- *  adc2 arbiter force grant
- */
-#define APB_SARADC_ADC_ARB_GRANT_FORCE    (BIT(5))
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (APB_SARADC_ADC_ARB_GRANT_FORCE_V << APB_SARADC_ADC_ARB_GRANT_FORCE_S)
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x00000001U
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
-/** APB_SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
- *  Set adc2 arbiterapb priority
- */
-#define APB_SARADC_ADC_ARB_APB_PRIORITY    0x00000003U
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  (APB_SARADC_ADC_ARB_APB_PRIORITY_V << APB_SARADC_ADC_ARB_APB_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x00000003U
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
-/** APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
- *  Set adc2 arbiter rtc priority
- */
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY    0x00000003U
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  (APB_SARADC_ADC_ARB_RTC_PRIORITY_V << APB_SARADC_ADC_ARB_RTC_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x00000003U
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
-/** APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
- *  Set adc2 arbiter wifi priority
- */
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY    0x00000003U
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  (APB_SARADC_ADC_ARB_WIFI_PRIORITY_V << APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x00000003U
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
-/** APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
- *  adc2 arbiter uses fixed priority
- */
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY    (BIT(12))
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (APB_SARADC_ADC_ARB_FIX_PRIORITY_V << APB_SARADC_ADC_ARB_FIX_PRIORITY_S)
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x00000001U
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
-
-/** APB_SARADC_FILTER_CTRL0_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
-/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
- *  configure filter1 to adc channel
- */
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1    0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_M  (APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S)
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL1_S  18
-/** APB_SARADC_APB_SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
- *  configure filter0 to adc channel
- */
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0    0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_M  (APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V << APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S)
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_FILTER_CHANNEL0_S  22
-/** APB_SARADC_APB_SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
- *  enable apb_adc1_filter
- */
-#define APB_SARADC_APB_SARADC_FILTER_RESET    (BIT(31))
-#define APB_SARADC_APB_SARADC_FILTER_RESET_M  (APB_SARADC_APB_SARADC_FILTER_RESET_V << APB_SARADC_APB_SARADC_FILTER_RESET_S)
-#define APB_SARADC_APB_SARADC_FILTER_RESET_V  0x00000001U
-#define APB_SARADC_APB_SARADC_FILTER_RESET_S  31
-
-/** APB_SARADC_SAR1DATA_STATUS_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
-/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
- *  saradc1 data
- */
-#define APB_SARADC_APB_SARADC1_DATA    0x0001FFFFU
-#define APB_SARADC_APB_SARADC1_DATA_M  (APB_SARADC_APB_SARADC1_DATA_V << APB_SARADC_APB_SARADC1_DATA_S)
-#define APB_SARADC_APB_SARADC1_DATA_V  0x0001FFFFU
-#define APB_SARADC_APB_SARADC1_DATA_S  0
-
-/** APB_SARADC_SAR2DATA_STATUS_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
-/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
- *  saradc2 data
- */
-#define APB_SARADC_APB_SARADC2_DATA    0x0001FFFFU
-#define APB_SARADC_APB_SARADC2_DATA_M  (APB_SARADC_APB_SARADC2_DATA_V << APB_SARADC_APB_SARADC2_DATA_S)
-#define APB_SARADC_APB_SARADC2_DATA_V  0x0001FFFFU
-#define APB_SARADC_APB_SARADC2_DATA_S  0
-
-/** APB_SARADC_THRES0_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
-/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
- *  configure thres0 to adc channel
- */
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL    0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_M  (APB_SARADC_APB_SARADC_THRES0_CHANNEL_V << APB_SARADC_APB_SARADC_THRES0_CHANNEL_S)
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES0_CHANNEL_S  0
-/** APB_SARADC_APB_SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
- *  saradc thres0 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_V << APB_SARADC_APB_SARADC_THRES0_HIGH_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_S  5
-/** APB_SARADC_APB_SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
- *  saradc thres0 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_LOW_M  (APB_SARADC_APB_SARADC_THRES0_LOW_V << APB_SARADC_APB_SARADC_THRES0_LOW_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES0_LOW_S  18
-
-/** APB_SARADC_THRES1_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
-/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
- *  configure thres1 to adc channel
- */
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL    0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_M  (APB_SARADC_APB_SARADC_THRES1_CHANNEL_V << APB_SARADC_APB_SARADC_THRES1_CHANNEL_S)
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_V  0x0000000FU
-#define APB_SARADC_APB_SARADC_THRES1_CHANNEL_S  0
-/** APB_SARADC_APB_SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
- *  saradc thres1 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_V << APB_SARADC_APB_SARADC_THRES1_HIGH_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_S  5
-/** APB_SARADC_APB_SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
- *  saradc thres1 monitor thres
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW    0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_LOW_M  (APB_SARADC_APB_SARADC_THRES1_LOW_V << APB_SARADC_APB_SARADC_THRES1_LOW_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_V  0x00001FFFU
-#define APB_SARADC_APB_SARADC_THRES1_LOW_S  18
-
-/** APB_SARADC_THRES_CTRL_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
-/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
- *  enable thres to all channel
- */
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN_M  (APB_SARADC_APB_SARADC_THRES_ALL_EN_V << APB_SARADC_APB_SARADC_THRES_ALL_EN_S)
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES_ALL_EN_S  27
-/** APB_SARADC_APB_SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
- *  enable thres1
- */
-#define APB_SARADC_APB_SARADC_THRES1_EN    (BIT(30))
-#define APB_SARADC_APB_SARADC_THRES1_EN_M  (APB_SARADC_APB_SARADC_THRES1_EN_V << APB_SARADC_APB_SARADC_THRES1_EN_S)
-#define APB_SARADC_APB_SARADC_THRES1_EN_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_EN_S  30
-/** APB_SARADC_APB_SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
- *  enable thres0
- */
-#define APB_SARADC_APB_SARADC_THRES0_EN    (BIT(31))
-#define APB_SARADC_APB_SARADC_THRES0_EN_M  (APB_SARADC_APB_SARADC_THRES0_EN_V << APB_SARADC_APB_SARADC_THRES0_EN_S)
-#define APB_SARADC_APB_SARADC_THRES0_EN_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_EN_S  31
-
-/** APB_SARADC_INT_ENA_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
-/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  tsens low  interrupt enable
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_M  (APB_SARADC_APB_SARADC_TSENS_INT_ENA_V << APB_SARADC_APB_SARADC_TSENS_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_ENA_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ENA_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ENA_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ENA_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt enable
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ENA_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  saradc2 done interrupt enable
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_M  (APB_SARADC_APB_SARADC2_DONE_INT_ENA_V << APB_SARADC_APB_SARADC2_DONE_INT_ENA_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_ENA_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  saradc1 done interrupt enable
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_M  (APB_SARADC_APB_SARADC1_DONE_INT_ENA_V << APB_SARADC_APB_SARADC1_DONE_INT_ENA_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_ENA_S  31
-
-/** APB_SARADC_INT_RAW_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
-/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  saradc tsens  interrupt raw
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_M  (APB_SARADC_APB_SARADC_TSENS_INT_RAW_V << APB_SARADC_APB_SARADC_TSENS_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_RAW_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_RAW_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_RAW_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_RAW_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt raw
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_RAW_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  saradc2 done interrupt raw
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_M  (APB_SARADC_APB_SARADC2_DONE_INT_RAW_V << APB_SARADC_APB_SARADC2_DONE_INT_RAW_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_RAW_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  saradc1 done interrupt raw
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_M  (APB_SARADC_APB_SARADC1_DONE_INT_RAW_V << APB_SARADC_APB_SARADC1_DONE_INT_RAW_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_RAW_S  31
-
-/** APB_SARADC_INT_ST_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
-/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
- *  saradc tsens  interrupt state
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST_M  (APB_SARADC_APB_SARADC_TSENS_INT_ST_V << APB_SARADC_APB_SARADC_TSENS_INT_ST_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_ST_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_ST_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_ST_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_ST_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt state
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_ST_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
- *  saradc2 done interrupt state
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST_M  (APB_SARADC_APB_SARADC2_DONE_INT_ST_V << APB_SARADC_APB_SARADC2_DONE_INT_ST_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_ST_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
- *  saradc1 done interrupt state
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST_M  (APB_SARADC_APB_SARADC1_DONE_INT_ST_V << APB_SARADC_APB_SARADC1_DONE_INT_ST_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_ST_S  31
-
-/** APB_SARADC_INT_CLR_REG register
- *  digital saradc int register
- */
-#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
-/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
- *  saradc tsens  interrupt clear
- */
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR    (BIT(25))
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_M  (APB_SARADC_APB_SARADC_TSENS_INT_CLR_V << APB_SARADC_APB_SARADC_TSENS_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_TSENS_INT_CLR_S  25
-/** APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
- *  saradc thres1 low  interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR    (BIT(26))
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_LOW_INT_CLR_S  26
-/** APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
- *  saradc thres0 low interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR    (BIT(27))
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_LOW_INT_CLR_S  27
-/** APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
- *  saradc thres1 high interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR    (BIT(28))
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES1_HIGH_INT_CLR_S  28
-/** APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
- *  saradc thres0 high interrupt clear
- */
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR    (BIT(29))
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_M  (APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V << APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S)
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC_THRES0_HIGH_INT_CLR_S  29
-/** APB_SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
- *  saradc2 done interrupt clear
- */
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR    (BIT(30))
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_M  (APB_SARADC_APB_SARADC2_DONE_INT_CLR_V << APB_SARADC_APB_SARADC2_DONE_INT_CLR_S)
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC2_DONE_INT_CLR_S  30
-/** APB_SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
- *  saradc1 done interrupt clear
- */
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR    (BIT(31))
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_M  (APB_SARADC_APB_SARADC1_DONE_INT_CLR_V << APB_SARADC_APB_SARADC1_DONE_INT_CLR_S)
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_V  0x00000001U
-#define APB_SARADC_APB_SARADC1_DONE_INT_CLR_S  31
-
-/** APB_SARADC_DMA_CONF_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
-/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
- *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
- */
-#define APB_SARADC_APB_ADC_EOF_NUM    0x0000FFFFU
-#define APB_SARADC_APB_ADC_EOF_NUM_M  (APB_SARADC_APB_ADC_EOF_NUM_V << APB_SARADC_APB_ADC_EOF_NUM_S)
-#define APB_SARADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
-#define APB_SARADC_APB_ADC_EOF_NUM_S  0
-/** APB_SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
- *  reset_apb_adc_state
- */
-#define APB_SARADC_APB_ADC_RESET_FSM    (BIT(30))
-#define APB_SARADC_APB_ADC_RESET_FSM_M  (APB_SARADC_APB_ADC_RESET_FSM_V << APB_SARADC_APB_ADC_RESET_FSM_S)
-#define APB_SARADC_APB_ADC_RESET_FSM_V  0x00000001U
-#define APB_SARADC_APB_ADC_RESET_FSM_S  30
-/** APB_SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
- *  enable apb_adc use spi_dma
- */
-#define APB_SARADC_APB_ADC_TRANS    (BIT(31))
-#define APB_SARADC_APB_ADC_TRANS_M  (APB_SARADC_APB_ADC_TRANS_V << APB_SARADC_APB_ADC_TRANS_S)
-#define APB_SARADC_APB_ADC_TRANS_V  0x00000001U
-#define APB_SARADC_APB_ADC_TRANS_S  31
-
-/** APB_SARADC_CLKM_CONF_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
-/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
- *  Integral I2S clock divider value
- */
-#define APB_SARADC_CLKM_DIV_NUM    0x000000FFU
-#define APB_SARADC_CLKM_DIV_NUM_M  (APB_SARADC_CLKM_DIV_NUM_V << APB_SARADC_CLKM_DIV_NUM_S)
-#define APB_SARADC_CLKM_DIV_NUM_V  0x000000FFU
-#define APB_SARADC_CLKM_DIV_NUM_S  0
-/** APB_SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
- *  Fractional clock divider numerator value
- */
-#define APB_SARADC_CLKM_DIV_B    0x0000003FU
-#define APB_SARADC_CLKM_DIV_B_M  (APB_SARADC_CLKM_DIV_B_V << APB_SARADC_CLKM_DIV_B_S)
-#define APB_SARADC_CLKM_DIV_B_V  0x0000003FU
-#define APB_SARADC_CLKM_DIV_B_S  8
-/** APB_SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
- *  Fractional clock divider denominator value
- */
-#define APB_SARADC_CLKM_DIV_A    0x0000003FU
-#define APB_SARADC_CLKM_DIV_A_M  (APB_SARADC_CLKM_DIV_A_V << APB_SARADC_CLKM_DIV_A_S)
-#define APB_SARADC_CLKM_DIV_A_V  0x0000003FU
-#define APB_SARADC_CLKM_DIV_A_S  14
-/** APB_SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
- *  reg clk en
- */
-#define APB_SARADC_CLK_EN    (BIT(20))
-#define APB_SARADC_CLK_EN_M  (APB_SARADC_CLK_EN_V << APB_SARADC_CLK_EN_S)
-#define APB_SARADC_CLK_EN_V  0x00000001U
-#define APB_SARADC_CLK_EN_S  20
-/** APB_SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
- *  Set this bit to enable clk_apll
- */
-#define APB_SARADC_CLK_SEL    0x00000003U
-#define APB_SARADC_CLK_SEL_M  (APB_SARADC_CLK_SEL_V << APB_SARADC_CLK_SEL_S)
-#define APB_SARADC_CLK_SEL_V  0x00000003U
-#define APB_SARADC_CLK_SEL_S  21
-
-/** APB_SARADC_APB_TSENS_CTRL_REG register
- *  digital tsens configure register
- */
-#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
-/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
- *  temperature sensor data out
- */
-#define APB_SARADC_TSENS_OUT    0x000000FFU
-#define APB_SARADC_TSENS_OUT_M  (APB_SARADC_TSENS_OUT_V << APB_SARADC_TSENS_OUT_S)
-#define APB_SARADC_TSENS_OUT_V  0x000000FFU
-#define APB_SARADC_TSENS_OUT_S  0
-/** APB_SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
- *  invert temperature sensor data
- */
-#define APB_SARADC_TSENS_IN_INV    (BIT(13))
-#define APB_SARADC_TSENS_IN_INV_M  (APB_SARADC_TSENS_IN_INV_V << APB_SARADC_TSENS_IN_INV_S)
-#define APB_SARADC_TSENS_IN_INV_V  0x00000001U
-#define APB_SARADC_TSENS_IN_INV_S  13
-/** APB_SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
- *  temperature sensor clock divider
- */
-#define APB_SARADC_TSENS_CLK_DIV    0x000000FFU
-#define APB_SARADC_TSENS_CLK_DIV_M  (APB_SARADC_TSENS_CLK_DIV_V << APB_SARADC_TSENS_CLK_DIV_S)
-#define APB_SARADC_TSENS_CLK_DIV_V  0x000000FFU
-#define APB_SARADC_TSENS_CLK_DIV_S  14
-/** APB_SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
- *  temperature sensor power up
- */
-#define APB_SARADC_TSENS_PU    (BIT(22))
-#define APB_SARADC_TSENS_PU_M  (APB_SARADC_TSENS_PU_V << APB_SARADC_TSENS_PU_S)
-#define APB_SARADC_TSENS_PU_V  0x00000001U
-#define APB_SARADC_TSENS_PU_S  22
-
-/** APB_SARADC_TSENS_CTRL2_REG register
- *  digital tsens configure register
- */
-#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
-/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
- *  tsens clk select
- */
-#define APB_SARADC_TSENS_CLK_SEL    (BIT(15))
-#define APB_SARADC_TSENS_CLK_SEL_M  (APB_SARADC_TSENS_CLK_SEL_V << APB_SARADC_TSENS_CLK_SEL_S)
-#define APB_SARADC_TSENS_CLK_SEL_V  0x00000001U
-#define APB_SARADC_TSENS_CLK_SEL_S  15
-
-/** APB_SARADC_CALI_REG register
- *  digital saradc configure register
- */
-#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
-/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
- *  saradc cali factor
- */
-#define APB_SARADC_APB_SARADC_CALI_CFG    0x0001FFFFU
-#define APB_SARADC_APB_SARADC_CALI_CFG_M  (APB_SARADC_APB_SARADC_CALI_CFG_V << APB_SARADC_APB_SARADC_CALI_CFG_S)
-#define APB_SARADC_APB_SARADC_CALI_CFG_V  0x0001FFFFU
-#define APB_SARADC_APB_SARADC_CALI_CFG_S  0
-
-/** APB_TSENS_WAKE_REG register
- *  digital tsens configure register
- */
-#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
-/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
- *  reg_wakeup_th_low
- */
-#define APB_SARADC_WAKEUP_TH_LOW    0x000000FFU
-#define APB_SARADC_WAKEUP_TH_LOW_M  (APB_SARADC_WAKEUP_TH_LOW_V << APB_SARADC_WAKEUP_TH_LOW_S)
-#define APB_SARADC_WAKEUP_TH_LOW_V  0x000000FFU
-#define APB_SARADC_WAKEUP_TH_LOW_S  0
-/** APB_SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
- *  reg_wakeup_th_high
- */
-#define APB_SARADC_WAKEUP_TH_HIGH    0x000000FFU
-#define APB_SARADC_WAKEUP_TH_HIGH_M  (APB_SARADC_WAKEUP_TH_HIGH_V << APB_SARADC_WAKEUP_TH_HIGH_S)
-#define APB_SARADC_WAKEUP_TH_HIGH_V  0x000000FFU
-#define APB_SARADC_WAKEUP_TH_HIGH_S  8
-/** APB_SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
- *  reg_wakeup_over_upper_th
- */
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH    (BIT(16))
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH_M  (APB_SARADC_WAKEUP_OVER_UPPER_TH_V << APB_SARADC_WAKEUP_OVER_UPPER_TH_S)
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH_V  0x00000001U
-#define APB_SARADC_WAKEUP_OVER_UPPER_TH_S  16
-/** APB_SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
- *  reg_wakeup_mode
- */
-#define APB_SARADC_WAKEUP_MODE    (BIT(17))
-#define APB_SARADC_WAKEUP_MODE_M  (APB_SARADC_WAKEUP_MODE_V << APB_SARADC_WAKEUP_MODE_S)
-#define APB_SARADC_WAKEUP_MODE_V  0x00000001U
-#define APB_SARADC_WAKEUP_MODE_S  17
-/** APB_SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
- *  reg_wakeup_en
- */
-#define APB_SARADC_WAKEUP_EN    (BIT(18))
-#define APB_SARADC_WAKEUP_EN_M  (APB_SARADC_WAKEUP_EN_V << APB_SARADC_WAKEUP_EN_S)
-#define APB_SARADC_WAKEUP_EN_V  0x00000001U
-#define APB_SARADC_WAKEUP_EN_S  18
-
-/** APB_TSENS_SAMPLE_REG register
- *  digital tsens configure register
- */
-#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
-/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
- *  HW sample rate
- */
-#define APB_SARADC_TSENS_SAMPLE_RATE    0x0000FFFFU
-#define APB_SARADC_TSENS_SAMPLE_RATE_M  (APB_SARADC_TSENS_SAMPLE_RATE_V << APB_SARADC_TSENS_SAMPLE_RATE_S)
-#define APB_SARADC_TSENS_SAMPLE_RATE_V  0x0000FFFFU
-#define APB_SARADC_TSENS_SAMPLE_RATE_S  0
-/** APB_SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
- *  HW sample en
- */
-#define APB_SARADC_TSENS_SAMPLE_EN    (BIT(16))
-#define APB_SARADC_TSENS_SAMPLE_EN_M  (APB_SARADC_TSENS_SAMPLE_EN_V << APB_SARADC_TSENS_SAMPLE_EN_S)
-#define APB_SARADC_TSENS_SAMPLE_EN_V  0x00000001U
-#define APB_SARADC_TSENS_SAMPLE_EN_S  16
-
-/** APB_SARADC_CTRL_DATE_REG register
- *  version
- */
-#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
-/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
- *  version
- */
-#define APB_SARADC_DATE    0xFFFFFFFFU
-#define APB_SARADC_DATE_M  (APB_SARADC_DATE_V << APB_SARADC_DATE_S)
-#define APB_SARADC_DATE_V  0xFFFFFFFFU
-#define APB_SARADC_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/beta3/include/soc/apb_saradc_struct.h
deleted file mode 100644
index 9f89d6c729..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/apb_saradc_struct.h
+++ /dev/null
@@ -1,696 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configure Register */
-/** Type of saradc_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_start_force : R/W; bitpos: [0]; default: 0;
-         *  select software enable saradc sample
-         */
-        uint32_t saradc_saradc_start_force:1;
-        /** saradc_saradc_start : R/W; bitpos: [1]; default: 0;
-         *  software enable saradc sample
-         */
-        uint32_t saradc_saradc_start:1;
-        uint32_t reserved_2:4;
-        /** saradc_saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
-         *  SAR clock gated
-         */
-        uint32_t saradc_saradc_sar_clk_gated:1;
-        /** saradc_saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
-         *  SAR clock divider
-         */
-        uint32_t saradc_saradc_sar_clk_div:8;
-        /** saradc_saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
-         *  0 ~ 15 means length 1 ~ 16
-         */
-        uint32_t saradc_saradc_sar_patt_len:3;
-        uint32_t reserved_18:5;
-        /** saradc_saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
-         *  clear the pointer of pattern table for DIG ADC1 CTRL
-         */
-        uint32_t saradc_saradc_sar_patt_p_clear:1;
-        uint32_t reserved_24:3;
-        /** saradc_saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
-         *  force option to xpd sar blocks
-         */
-        uint32_t saradc_saradc_xpd_sar_force:2;
-        /** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
-         *  enable saradc2 power detect driven func.
-         */
-        uint32_t saradc_saradc2_pwdet_drv:1;
-        /** saradc_saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
-         *  wait arbit signal stable after sar_done
-         */
-        uint32_t saradc_saradc_wait_arb_cycle:2;
-    };
-    uint32_t val;
-} apb_saradc_ctrl_reg_t;
-
-/** Type of saradc_ctrl2 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
-         *  enable max meas num
-         */
-        uint32_t saradc_saradc_meas_num_limit:1;
-        /** saradc_saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
-         *  max conversion number
-         */
-        uint32_t saradc_saradc_max_meas_num:8;
-        /** saradc_saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
-         *  1: data to DIG ADC1 CTRL is inverted, otherwise not
-         */
-        uint32_t saradc_saradc_sar1_inv:1;
-        /** saradc_saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
-         *  1: data to DIG ADC2 CTRL is inverted, otherwise not
-         */
-        uint32_t saradc_saradc_sar2_inv:1;
-        uint32_t reserved_11:1;
-        /** saradc_saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
-         *  to set saradc timer target
-         */
-        uint32_t saradc_saradc_timer_target:12;
-        /** saradc_saradc_timer_en : R/W; bitpos: [24]; default: 0;
-         *  to enable saradc timer trigger
-         */
-        uint32_t saradc_saradc_timer_en:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} apb_saradc_ctrl2_reg_t;
-
-/** Type of saradc_filter_ctrl1 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** saradc_apb_saradc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
-         *  Factor of saradc filter1
-         */
-        uint32_t saradc_apb_saradc_filter_factor1:3;
-        /** saradc_apb_saradc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
-         *  Factor of saradc filter0
-         */
-        uint32_t saradc_apb_saradc_filter_factor0:3;
-    };
-    uint32_t val;
-} apb_saradc_filter_ctrl1_reg_t;
-
-/** Type of saradc_sar_patt_tab1 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
-         *  item 0 ~ 3 for pattern table 1 (each item one byte)
-         */
-        uint32_t saradc_saradc_sar_patt_tab1:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} apb_saradc_sar_patt_tab1_reg_t;
-
-/** Type of saradc_sar_patt_tab2 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
-         *  Item 4 ~ 7 for pattern table 1 (each item one byte)
-         */
-        uint32_t saradc_saradc_sar_patt_tab2:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} apb_saradc_sar_patt_tab2_reg_t;
-
-/** Type of saradc_onetime_sample register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:23;
-        /** saradc_saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
-         *  configure onetime atten
-         */
-        uint32_t saradc_saradc_onetime_atten:2;
-        /** saradc_saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
-         *  configure onetime channel
-         */
-        uint32_t saradc_saradc_onetime_channel:4;
-        /** saradc_saradc_onetime_start : R/W; bitpos: [29]; default: 0;
-         *  trigger adc onetime sample
-         */
-        uint32_t saradc_saradc_onetime_start:1;
-        /** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
-         *  enable adc2 onetime sample
-         */
-        uint32_t saradc_saradc2_onetime_sample:1;
-        /** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
-         *  enable adc1 onetime sample
-         */
-        uint32_t saradc_saradc1_onetime_sample:1;
-    };
-    uint32_t val;
-} apb_saradc_onetime_sample_reg_t;
-
-/** Type of saradc_arb_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
-         *  adc2 arbiter force to enableapb controller
-         */
-        uint32_t saradc_adc_arb_apb_force:1;
-        /** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
-         *  adc2 arbiter force to enable rtc controller
-         */
-        uint32_t saradc_adc_arb_rtc_force:1;
-        /** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
-         *  adc2 arbiter force to enable wifi controller
-         */
-        uint32_t saradc_adc_arb_wifi_force:1;
-        /** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
-         *  adc2 arbiter force grant
-         */
-        uint32_t saradc_adc_arb_grant_force:1;
-        /** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
-         *  Set adc2 arbiterapb priority
-         */
-        uint32_t saradc_adc_arb_apb_priority:2;
-        /** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
-         *  Set adc2 arbiter rtc priority
-         */
-        uint32_t saradc_adc_arb_rtc_priority:2;
-        /** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
-         *  Set adc2 arbiter wifi priority
-         */
-        uint32_t saradc_adc_arb_wifi_priority:2;
-        /** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
-         *  adc2 arbiter uses fixed priority
-         */
-        uint32_t saradc_adc_arb_fix_priority:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} apb_saradc_arb_ctrl_reg_t;
-
-/** Type of saradc_filter_ctrl0 register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:18;
-        /** saradc_apb_saradc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
-         *  configure filter1 to adc channel
-         */
-        uint32_t saradc_apb_saradc_filter_channel1:4;
-        /** saradc_apb_saradc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
-         *  configure filter0 to adc channel
-         */
-        uint32_t saradc_apb_saradc_filter_channel0:4;
-        uint32_t reserved_26:5;
-        /** saradc_apb_saradc_filter_reset : R/W; bitpos: [31]; default: 0;
-         *  enable apb_adc1_filter
-         */
-        uint32_t saradc_apb_saradc_filter_reset:1;
-    };
-    uint32_t val;
-} apb_saradc_filter_ctrl0_reg_t;
-
-/** Type of saradc_sar1data_status register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
-         *  saradc1 data
-         */
-        uint32_t saradc_apb_saradc1_data:17;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_saradc_sar1data_status_reg_t;
-
-/** Type of saradc_sar2data_status register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
-         *  saradc2 data
-         */
-        uint32_t saradc_apb_saradc2_data:17;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_saradc_sar2data_status_reg_t;
-
-/** Type of saradc_thres0_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
-         *  configure thres0 to adc channel
-         */
-        uint32_t saradc_apb_saradc_thres0_channel:4;
-        uint32_t reserved_4:1;
-        /** saradc_apb_saradc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
-         *  saradc thres0 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres0_high:13;
-        /** saradc_apb_saradc_thres0_low : R/W; bitpos: [30:18]; default: 0;
-         *  saradc thres0 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres0_low:13;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} apb_saradc_thres0_ctrl_reg_t;
-
-/** Type of saradc_thres1_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
-         *  configure thres1 to adc channel
-         */
-        uint32_t saradc_apb_saradc_thres1_channel:4;
-        uint32_t reserved_4:1;
-        /** saradc_apb_saradc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
-         *  saradc thres1 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres1_high:13;
-        /** saradc_apb_saradc_thres1_low : R/W; bitpos: [30:18]; default: 0;
-         *  saradc thres1 monitor thres
-         */
-        uint32_t saradc_apb_saradc_thres1_low:13;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} apb_saradc_thres1_ctrl_reg_t;
-
-/** Type of saradc_thres_ctrl register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** saradc_apb_saradc_thres_all_en : R/W; bitpos: [27]; default: 0;
-         *  enable thres to all channel
-         */
-        uint32_t saradc_apb_saradc_thres_all_en:1;
-        uint32_t reserved_28:2;
-        /** saradc_apb_saradc_thres1_en : R/W; bitpos: [30]; default: 0;
-         *  enable thres1
-         */
-        uint32_t saradc_apb_saradc_thres1_en:1;
-        /** saradc_apb_saradc_thres0_en : R/W; bitpos: [31]; default: 0;
-         *  enable thres0
-         */
-        uint32_t saradc_apb_saradc_thres0_en:1;
-    };
-    uint32_t val;
-} apb_saradc_thres_ctrl_reg_t;
-
-/** Type of saradc_int_ena register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
-         *  tsens low  interrupt enable
-         */
-        uint32_t saradc_apb_saradc_tsens_int_ena:1;
-        /** saradc_apb_saradc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_ena:1;
-        /** saradc_apb_saradc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_ena:1;
-        /** saradc_apb_saradc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_ena:1;
-        /** saradc_apb_saradc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt enable
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_ena:1;
-        /** saradc_apb_saradc2_done_int_ena : R/W; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt enable
-         */
-        uint32_t saradc_apb_saradc2_done_int_ena:1;
-        /** saradc_apb_saradc1_done_int_ena : R/W; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt enable
-         */
-        uint32_t saradc_apb_saradc1_done_int_ena:1;
-    };
-    uint32_t val;
-} apb_saradc_int_ena_reg_t;
-
-/** Type of saradc_int_raw register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  saradc tsens  interrupt raw
-         */
-        uint32_t saradc_apb_saradc_tsens_int_raw:1;
-        /** saradc_apb_saradc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_raw:1;
-        /** saradc_apb_saradc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_raw:1;
-        /** saradc_apb_saradc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_raw:1;
-        /** saradc_apb_saradc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt raw
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_raw:1;
-        /** saradc_apb_saradc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt raw
-         */
-        uint32_t saradc_apb_saradc2_done_int_raw:1;
-        /** saradc_apb_saradc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt raw
-         */
-        uint32_t saradc_apb_saradc1_done_int_raw:1;
-    };
-    uint32_t val;
-} apb_saradc_int_raw_reg_t;
-
-/** Type of saradc_int_st register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_st : RO; bitpos: [25]; default: 0;
-         *  saradc tsens  interrupt state
-         */
-        uint32_t saradc_apb_saradc_tsens_int_st:1;
-        /** saradc_apb_saradc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_st:1;
-        /** saradc_apb_saradc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_st:1;
-        /** saradc_apb_saradc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_st:1;
-        /** saradc_apb_saradc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt state
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_st:1;
-        /** saradc_apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt state
-         */
-        uint32_t saradc_apb_saradc2_done_int_st:1;
-        /** saradc_apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt state
-         */
-        uint32_t saradc_apb_saradc1_done_int_st:1;
-    };
-    uint32_t val;
-} apb_saradc_int_st_reg_t;
-
-/** Type of saradc_int_clr register
- *  digital saradc int register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** saradc_apb_saradc_tsens_int_clr : WT; bitpos: [25]; default: 0;
-         *  saradc tsens  interrupt clear
-         */
-        uint32_t saradc_apb_saradc_tsens_int_clr:1;
-        /** saradc_apb_saradc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
-         *  saradc thres1 low  interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres1_low_int_clr:1;
-        /** saradc_apb_saradc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
-         *  saradc thres0 low interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres0_low_int_clr:1;
-        /** saradc_apb_saradc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
-         *  saradc thres1 high interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres1_high_int_clr:1;
-        /** saradc_apb_saradc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
-         *  saradc thres0 high interrupt clear
-         */
-        uint32_t saradc_apb_saradc_thres0_high_int_clr:1;
-        /** saradc_apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
-         *  saradc2 done interrupt clear
-         */
-        uint32_t saradc_apb_saradc2_done_int_clr:1;
-        /** saradc_apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
-         *  saradc1 done interrupt clear
-         */
-        uint32_t saradc_apb_saradc1_done_int_clr:1;
-    };
-    uint32_t val;
-} apb_saradc_int_clr_reg_t;
-
-/** Type of saradc_dma_conf register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
-         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
-         */
-        uint32_t saradc_apb_adc_eof_num:16;
-        uint32_t reserved_16:14;
-        /** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
-         *  reset_apb_adc_state
-         */
-        uint32_t saradc_apb_adc_reset_fsm:1;
-        /** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
-         *  enable apb_adc use spi_dma
-         */
-        uint32_t saradc_apb_adc_trans:1;
-    };
-    uint32_t val;
-} apb_saradc_dma_conf_reg_t;
-
-/** Type of saradc_clkm_conf register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
-         *  Integral I2S clock divider value
-         */
-        uint32_t saradc_clkm_div_num:8;
-        /** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
-         *  Fractional clock divider numerator value
-         */
-        uint32_t saradc_clkm_div_b:6;
-        /** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
-         *  Fractional clock divider denominator value
-         */
-        uint32_t saradc_clkm_div_a:6;
-        /** saradc_clk_en : R/W; bitpos: [20]; default: 0;
-         *  reg clk en
-         */
-        uint32_t saradc_clk_en:1;
-        /** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
-         *  Set this bit to enable clk_apll
-         */
-        uint32_t saradc_clk_sel:2;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} apb_saradc_clkm_conf_reg_t;
-
-/** Type of saradc_apb_tsens_ctrl register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        /** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
-         *  temperature sensor data out
-         */
-        uint32_t saradc_tsens_out:8;
-        uint32_t reserved_8:5;
-        /** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
-         *  invert temperature sensor data
-         */
-        uint32_t saradc_tsens_in_inv:1;
-        /** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
-         *  temperature sensor clock divider
-         */
-        uint32_t saradc_tsens_clk_div:8;
-        /** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
-         *  temperature sensor power up
-         */
-        uint32_t saradc_tsens_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} apb_saradc_apb_tsens_ctrl_reg_t;
-
-/** Type of saradc_tsens_ctrl2 register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:15;
-        /** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
-         *  tsens clk select
-         */
-        uint32_t saradc_tsens_clk_sel:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} apb_saradc_tsens_ctrl2_reg_t;
-
-/** Type of saradc_cali register
- *  digital saradc configure register
- */
-typedef union {
-    struct {
-        /** saradc_apb_saradc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
-         *  saradc cali factor
-         */
-        uint32_t saradc_apb_saradc_cali_cfg:17;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_saradc_cali_reg_t;
-
-/** Type of tsens_wake register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        /** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
-         *  reg_wakeup_th_low
-         */
-        uint32_t saradc_wakeup_th_low:8;
-        /** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
-         *  reg_wakeup_th_high
-         */
-        uint32_t saradc_wakeup_th_high:8;
-        /** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
-         *  reg_wakeup_over_upper_th
-         */
-        uint32_t saradc_wakeup_over_upper_th:1;
-        /** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
-         *  reg_wakeup_mode
-         */
-        uint32_t saradc_wakeup_mode:1;
-        /** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
-         *  reg_wakeup_en
-         */
-        uint32_t saradc_wakeup_en:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} apb_tsens_wake_reg_t;
-
-/** Type of tsens_sample register
- *  digital tsens configure register
- */
-typedef union {
-    struct {
-        /** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
-         *  HW sample rate
-         */
-        uint32_t saradc_tsens_sample_rate:16;
-        /** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
-         *  HW sample en
-         */
-        uint32_t saradc_tsens_sample_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} apb_tsens_sample_reg_t;
-
-/** Type of saradc_ctrl_date register
- *  version
- */
-typedef union {
-    struct {
-        /** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
-         *  version
-         */
-        uint32_t saradc_date:32;
-    };
-    uint32_t val;
-} apb_saradc_ctrl_date_reg_t;
-
-
-typedef struct apb_dev_t {
-    volatile apb_saradc_ctrl_reg_t saradc_ctrl;
-    volatile apb_saradc_ctrl2_reg_t saradc_ctrl2;
-    volatile apb_saradc_filter_ctrl1_reg_t saradc_filter_ctrl1;
-    uint32_t reserved_00c[3];
-    volatile apb_saradc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
-    volatile apb_saradc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
-    volatile apb_saradc_onetime_sample_reg_t saradc_onetime_sample;
-    volatile apb_saradc_arb_ctrl_reg_t saradc_arb_ctrl;
-    volatile apb_saradc_filter_ctrl0_reg_t saradc_filter_ctrl0;
-    volatile apb_saradc_sar1data_status_reg_t saradc_sar1data_status;
-    volatile apb_saradc_sar2data_status_reg_t saradc_sar2data_status;
-    volatile apb_saradc_thres0_ctrl_reg_t saradc_thres0_ctrl;
-    volatile apb_saradc_thres1_ctrl_reg_t saradc_thres1_ctrl;
-    volatile apb_saradc_thres_ctrl_reg_t saradc_thres_ctrl;
-    volatile apb_saradc_int_ena_reg_t saradc_int_ena;
-    volatile apb_saradc_int_raw_reg_t saradc_int_raw;
-    volatile apb_saradc_int_st_reg_t saradc_int_st;
-    volatile apb_saradc_int_clr_reg_t saradc_int_clr;
-    volatile apb_saradc_dma_conf_reg_t saradc_dma_conf;
-    volatile apb_saradc_clkm_conf_reg_t saradc_clkm_conf;
-    volatile apb_saradc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
-    volatile apb_saradc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
-    volatile apb_saradc_cali_reg_t saradc_cali;
-    volatile apb_tsens_wake_reg_t tsens_wake;
-    volatile apb_tsens_sample_reg_t tsens_sample;
-    uint32_t reserved_06c[228];
-    volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
-} apb_dev_t;
-
-extern apb_dev_t APB_SARADC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/assist_debug_reg.h b/components/soc/esp32c5/beta3/include/soc/assist_debug_reg.h
deleted file mode 100644
index cda7314f21..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register
- *  core0 monitor enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-
-/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
- *  core0 monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-
-/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
- *  core0 monitor interrupt enable register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S  9
-
-/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
- *  core0 monitor interrupt clr register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
- *  core0 area pc status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
- *  the stackpointer when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
- *  core0 area sp status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
-/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
- *  the PC when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
- *  stack min value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
-/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
- *  stack max value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
-/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
- *  core0 sp pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
- *  stack monitor pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
-/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
- *  record enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
-/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable record PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
- *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
- *  recorded PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
- *  recorded sp
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
-
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
- *  cpu's lastpc before exception
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
-
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
- *  cpu debug mode status, 1 means cpu enter debug mode.
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
- *  cpu debug_module active status
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-
-/** ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_DMACTIVE_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
-/** ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
- *  need desc
- */
-#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_M  (ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V << ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S)
-#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DMACTIVE_LPCORE_S  0
-
-/** ASSIST_DEBUG_CLOCK_GATE_REG register
- *  clock register
- */
-#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c)
-/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 force on the clock gate
- */
-#define ASSIST_DEBUG_CLK_EN    (BIT(0))
-#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
-#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
-#define ASSIST_DEBUG_CLK_EN_S  0
-
-/** ASSIST_DEBUG_DATE_REG register
- *  version register
- */
-#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
-/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 35725648;
- *  version register
- */
-#define ASSIST_DEBUG_DATE    0x0FFFFFFFU
-#define ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
-#define ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
-#define ASSIST_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/assist_debug_struct.h b/components/soc/esp32c5/beta3/include/soc/assist_debug_struct.h
deleted file mode 100644
index d4c634d060..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/assist_debug_struct.h
+++ /dev/null
@@ -1,549 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: monitor configuration registers */
-/** Type of core_0_montr_ena register
- *  core0 monitor enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor enable
-         */
-        uint32_t core_0_area_dram0_0_rd_ena:1;
-        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor enable
-         */
-        uint32_t core_0_area_dram0_0_wr_ena:1;
-        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor enable
-         */
-        uint32_t core_0_area_dram0_1_rd_ena:1;
-        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor enable
-         */
-        uint32_t core_0_area_dram0_1_wr_ena:1;
-        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor enable
-         */
-        uint32_t core_0_area_pif_0_rd_ena:1;
-        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor enable
-         */
-        uint32_t core_0_area_pif_0_wr_ena:1;
-        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor enable
-         */
-        uint32_t core_0_area_pif_1_rd_ena:1;
-        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor enable
-         */
-        uint32_t core_0_area_pif_1_wr_ena:1;
-        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor enable
-         */
-        uint32_t core_0_sp_spill_min_ena:1;
-        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor enable
-         */
-        uint32_t core_0_sp_spill_max_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_montr_ena_reg_t;
-
-/** Type of core_0_area_dram0_0_min register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region0 start addr
-         */
-        uint32_t core_0_area_dram0_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_min_reg_t;
-
-/** Type of core_0_area_dram0_0_max register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region0 end addr
-         */
-        uint32_t core_0_area_dram0_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_max_reg_t;
-
-/** Type of core_0_area_dram0_1_min register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region1 start addr
-         */
-        uint32_t core_0_area_dram0_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_min_reg_t;
-
-/** Type of core_0_area_dram0_1_max register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region1 end addr
-         */
-        uint32_t core_0_area_dram0_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_max_reg_t;
-
-/** Type of core_0_area_pif_0_min register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region0 start addr
-         */
-        uint32_t core_0_area_pif_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_min_reg_t;
-
-/** Type of core_0_area_pif_0_max register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region0 end addr
-         */
-        uint32_t core_0_area_pif_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_max_reg_t;
-
-/** Type of core_0_area_pif_1_min register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region1 start addr
-         */
-        uint32_t core_0_area_pif_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_min_reg_t;
-
-/** Type of core_0_area_pif_1_max register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region1 end addr
-         */
-        uint32_t core_0_area_pif_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_max_reg_t;
-
-/** Type of core_0_area_pc register
- *  core0 area pc status register
- */
-typedef union {
-    struct {
-        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
-         *  the stackpointer when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pc_reg_t;
-
-/** Type of core_0_area_sp register
- *  core0 area sp status register
- */
-typedef union {
-    struct {
-        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
-         *  the PC when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_sp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_sp_reg_t;
-
-/** Type of core_0_sp_min register
- *  stack min value
- */
-typedef union {
-    struct {
-        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
-         */
-        uint32_t core_0_sp_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_min_reg_t;
-
-/** Type of core_0_sp_max register
- *  stack max value
- */
-typedef union {
-    struct {
-        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
-         *  core0 sp pc status register
-         */
-        uint32_t core_0_sp_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_max_reg_t;
-
-/** Type of core_0_sp_pc register
- *  stack monitor pc status register
- */
-typedef union {
-    struct {
-        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
-         */
-        uint32_t core_0_sp_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_pc_reg_t;
-
-
-/** Group: interrupt configuration register */
-/** Type of core_0_intr_raw register
- *  core0 monitor interrupt status register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_rd_raw:1;
-        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_wr_raw:1;
-        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_rd_raw:1;
-        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_wr_raw:1;
-        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_rd_raw:1;
-        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_wr_raw:1;
-        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_rd_raw:1;
-        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_wr_raw:1;
-        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_min_raw:1;
-        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_max_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_raw_reg_t;
-
-/** Type of core_0_intr_ena register
- *  core0 monitor interrupt enable register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_rd_intr_ena:1;
-        /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_wr_intr_ena:1;
-        /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_rd_intr_ena:1;
-        /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_wr_intr_ena:1;
-        /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_rd_intr_ena:1;
-        /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_wr_intr_ena:1;
-        /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_rd_intr_ena:1;
-        /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_wr_intr_ena:1;
-        /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_min_intr_ena:1;
-        /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_max_intr_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_ena_reg_t;
-
-/** Type of core_0_intr_clr register
- *  core0 monitor interrupt clr register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_rd_clr:1;
-        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_wr_clr:1;
-        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_rd_clr:1;
-        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_wr_clr:1;
-        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_rd_clr:1;
-        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_wr_clr:1;
-        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_rd_clr:1;
-        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_wr_clr:1;
-        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_min_clr:1;
-        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_max_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_clr_reg_t;
-
-
-/** Group: pc reording configuration register */
-/** Type of core_0_rcd_en register
- *  record enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable record PC
-         */
-        uint32_t core_0_rcd_recorden:1;
-        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
-         */
-        uint32_t core_0_rcd_pdebugen:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_en_reg_t;
-
-
-/** Group: pc reording status register */
-/** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
-         *  recorded PC
-         */
-        uint32_t core_0_rcd_pdebugpc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugpc_reg_t;
-
-/** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
-         *  recorded sp
-         */
-        uint32_t core_0_rcd_pdebugsp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugsp_reg_t;
-
-
-/** Group: cpu status registers */
-/** Type of core_0_lastpc_before_exception register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
-         *  cpu's lastpc before exception
-         */
-        uint32_t core_0_lastpc_before_exc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_lastpc_before_exception_reg_t;
-
-/** Type of core_0_debug_mode register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
-         *  cpu debug mode status, 1 means cpu enter debug mode.
-         */
-        uint32_t core_0_debug_mode:1;
-        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
-         *  cpu debug_module active status
-         */
-        uint32_t core_0_debug_module_active:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_debug_mode_reg_t;
-
-/** Type of core_0_dmactive_mode register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_dmactive_lpcore : RO; bitpos: [0]; default: 0;
-         *  need desc
-         */
-        uint32_t core_0_dmactive_lpcore:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} assist_debug_core_0_dmactive_mode_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of clock_gate register
- *  clock register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 force on the clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} assist_debug_clock_gate_reg_t;
-
-/** Type of date register
- *  version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725648;
-         *  version register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} assist_debug_date_reg_t;
-
-
-typedef struct assist_debug_dev_t {
-    volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
-    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
-    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
-    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
-    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
-    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
-    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
-    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
-    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
-    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
-    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
-    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
-    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
-    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
-    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
-    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
-    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
-    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
-    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
-    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
-    uint32_t reserved_050[8];
-    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
-    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
-    volatile assist_debug_core_0_dmactive_mode_reg_t core_0_dmactive_mode;
-    volatile assist_debug_clock_gate_reg_t clock_gate;
-    uint32_t reserved_080[223];
-    volatile assist_debug_date_reg_t date;
-} assist_debug_dev_t;
-
-extern assist_debug_dev_t ASSIST_DEBUG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/bitscrambler_reg.h b/components/soc/esp32c5/beta3/include/soc/bitscrambler_reg.h
deleted file mode 100644
index 44bfc3c874..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/bitscrambler_reg.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** BITSCRAMBLER_TX_INST_CFG0_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
-/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
- *  write this bits to specify the one of 8 instruction
- */
-#define BITSCRAMBLER_TX_INST_IDX    0x00000007U
-#define BITSCRAMBLER_TX_INST_IDX_M  (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
-#define BITSCRAMBLER_TX_INST_IDX_V  0x00000007U
-#define BITSCRAMBLER_TX_INST_IDX_S  0
-/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
- *  write this bits to specify the bit position of 257 bit instruction which in units
- *  of 32 bits
- */
-#define BITSCRAMBLER_TX_INST_POS    0x0000000FU
-#define BITSCRAMBLER_TX_INST_POS_M  (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
-#define BITSCRAMBLER_TX_INST_POS_V  0x0000000FU
-#define BITSCRAMBLER_TX_INST_POS_S  3
-
-/** BITSCRAMBLER_TX_INST_CFG1_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
-/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
- *  write this bits to update instruction which specified by
- *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
- *  BITSCRAMBLER_TX_INST_CFG0_REG
- */
-#define BITSCRAMBLER_TX_INST    0xFFFFFFFFU
-#define BITSCRAMBLER_TX_INST_M  (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
-#define BITSCRAMBLER_TX_INST_V  0xFFFFFFFFU
-#define BITSCRAMBLER_TX_INST_S  0
-
-/** BITSCRAMBLER_RX_INST_CFG0_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
-/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
- *  write this bits to specify the one of 8 instruction
- */
-#define BITSCRAMBLER_RX_INST_IDX    0x00000007U
-#define BITSCRAMBLER_RX_INST_IDX_M  (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
-#define BITSCRAMBLER_RX_INST_IDX_V  0x00000007U
-#define BITSCRAMBLER_RX_INST_IDX_S  0
-/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
- *  write this bits to specify the bit position of 257 bit instruction which in units
- *  of 32 bits
- */
-#define BITSCRAMBLER_RX_INST_POS    0x0000000FU
-#define BITSCRAMBLER_RX_INST_POS_M  (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
-#define BITSCRAMBLER_RX_INST_POS_V  0x0000000FU
-#define BITSCRAMBLER_RX_INST_POS_S  3
-
-/** BITSCRAMBLER_RX_INST_CFG1_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
-/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
- *  write this bits to update instruction which specified by
- *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
- *  BITSCRAMBLER_RX_INST_CFG0_REG
- */
-#define BITSCRAMBLER_RX_INST    0xFFFFFFFFU
-#define BITSCRAMBLER_RX_INST_M  (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
-#define BITSCRAMBLER_RX_INST_V  0xFFFFFFFFU
-#define BITSCRAMBLER_RX_INST_S  0
-
-/** BITSCRAMBLER_TX_LUT_CFG0_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
-/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
- *  write this bits to specify the bytes position of LUT RAM based on
- *  reg_bitscrambler_tx_lut_mode
- */
-#define BITSCRAMBLER_TX_LUT_IDX    0x000007FFU
-#define BITSCRAMBLER_TX_LUT_IDX_M  (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
-#define BITSCRAMBLER_TX_LUT_IDX_V  0x000007FFU
-#define BITSCRAMBLER_TX_LUT_IDX_S  0
-/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
- *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
- *  bytes
- */
-#define BITSCRAMBLER_TX_LUT_MODE    0x00000003U
-#define BITSCRAMBLER_TX_LUT_MODE_M  (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
-#define BITSCRAMBLER_TX_LUT_MODE_V  0x00000003U
-#define BITSCRAMBLER_TX_LUT_MODE_S  11
-
-/** BITSCRAMBLER_TX_LUT_CFG1_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
-/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
- *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
- *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
- */
-#define BITSCRAMBLER_TX_LUT    0xFFFFFFFFU
-#define BITSCRAMBLER_TX_LUT_M  (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
-#define BITSCRAMBLER_TX_LUT_V  0xFFFFFFFFU
-#define BITSCRAMBLER_TX_LUT_S  0
-
-/** BITSCRAMBLER_RX_LUT_CFG0_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
-/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
- *  write this bits to specify the bytes position of LUT RAM based on
- *  reg_bitscrambler_rx_lut_mode
- */
-#define BITSCRAMBLER_RX_LUT_IDX    0x000007FFU
-#define BITSCRAMBLER_RX_LUT_IDX_M  (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
-#define BITSCRAMBLER_RX_LUT_IDX_V  0x000007FFU
-#define BITSCRAMBLER_RX_LUT_IDX_S  0
-/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
- *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
- *  bytes
- */
-#define BITSCRAMBLER_RX_LUT_MODE    0x00000003U
-#define BITSCRAMBLER_RX_LUT_MODE_M  (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
-#define BITSCRAMBLER_RX_LUT_MODE_V  0x00000003U
-#define BITSCRAMBLER_RX_LUT_MODE_S  11
-
-/** BITSCRAMBLER_RX_LUT_CFG1_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
-/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
- *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
- *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
- */
-#define BITSCRAMBLER_RX_LUT    0xFFFFFFFFU
-#define BITSCRAMBLER_RX_LUT_M  (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
-#define BITSCRAMBLER_RX_LUT_V  0xFFFFFFFFU
-#define BITSCRAMBLER_RX_LUT_S  0
-
-/** BITSCRAMBLER_TX_TAILING_BITS_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
-/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
- *  write this bits to specify the extra data bit length after getting EOF
- */
-#define BITSCRAMBLER_TX_TAILING_BITS    0x0000FFFFU
-#define BITSCRAMBLER_TX_TAILING_BITS_M  (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
-#define BITSCRAMBLER_TX_TAILING_BITS_V  0x0000FFFFU
-#define BITSCRAMBLER_TX_TAILING_BITS_S  0
-
-/** BITSCRAMBLER_RX_TAILING_BITS_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
-/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
- *  write this bits to specify the extra data bit length after getting EOF
- */
-#define BITSCRAMBLER_RX_TAILING_BITS    0x0000FFFFU
-#define BITSCRAMBLER_RX_TAILING_BITS_M  (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
-#define BITSCRAMBLER_RX_TAILING_BITS_V  0x0000FFFFU
-#define BITSCRAMBLER_RX_TAILING_BITS_S  0
-
-/** BITSCRAMBLER_TX_CTRL_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
-/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
- *  write this bit to enable the bitscrambler tx
- */
-#define BITSCRAMBLER_TX_ENA    (BIT(0))
-#define BITSCRAMBLER_TX_ENA_M  (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
-#define BITSCRAMBLER_TX_ENA_V  0x00000001U
-#define BITSCRAMBLER_TX_ENA_S  0
-/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
- *  write this bit to pause the bitscrambler tx core
- */
-#define BITSCRAMBLER_TX_PAUSE    (BIT(1))
-#define BITSCRAMBLER_TX_PAUSE_M  (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
-#define BITSCRAMBLER_TX_PAUSE_V  0x00000001U
-#define BITSCRAMBLER_TX_PAUSE_S  1
-/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
- *  write this bit to halt the bitscrambler tx core
- */
-#define BITSCRAMBLER_TX_HALT    (BIT(2))
-#define BITSCRAMBLER_TX_HALT_M  (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
-#define BITSCRAMBLER_TX_HALT_V  0x00000001U
-#define BITSCRAMBLER_TX_HALT_S  2
-/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
- *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
- *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
- *  counter by write peripheral buffer
- */
-#define BITSCRAMBLER_TX_EOF_MODE    (BIT(3))
-#define BITSCRAMBLER_TX_EOF_MODE_M  (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
-#define BITSCRAMBLER_TX_EOF_MODE_V  0x00000001U
-#define BITSCRAMBLER_TX_EOF_MODE_S  3
-/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
- *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
- *  core, 0: use the little than operator to get the condition, 1: use not equal
- *  operator to get the condition
- */
-#define BITSCRAMBLER_TX_COND_MODE    (BIT(4))
-#define BITSCRAMBLER_TX_COND_MODE_M  (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
-#define BITSCRAMBLER_TX_COND_MODE_V  0x00000001U
-#define BITSCRAMBLER_TX_COND_MODE_S  4
-/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
- *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
- */
-#define BITSCRAMBLER_TX_FETCH_MODE    (BIT(5))
-#define BITSCRAMBLER_TX_FETCH_MODE_M  (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
-#define BITSCRAMBLER_TX_FETCH_MODE_V  0x00000001U
-#define BITSCRAMBLER_TX_FETCH_MODE_S  5
-/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
- *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
- *  wait write data back done, , 1: ignore write data back
- */
-#define BITSCRAMBLER_TX_HALT_MODE    (BIT(6))
-#define BITSCRAMBLER_TX_HALT_MODE_M  (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
-#define BITSCRAMBLER_TX_HALT_MODE_V  0x00000001U
-#define BITSCRAMBLER_TX_HALT_MODE_S  6
-/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
- *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
- *  wait read data, 1: ignore read data
- */
-#define BITSCRAMBLER_TX_RD_DUMMY    (BIT(7))
-#define BITSCRAMBLER_TX_RD_DUMMY_M  (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
-#define BITSCRAMBLER_TX_RD_DUMMY_V  0x00000001U
-#define BITSCRAMBLER_TX_RD_DUMMY_S  7
-/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
- *  write this bit to reset the bitscrambler tx fifo
- */
-#define BITSCRAMBLER_TX_FIFO_RST    (BIT(8))
-#define BITSCRAMBLER_TX_FIFO_RST_M  (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
-#define BITSCRAMBLER_TX_FIFO_RST_V  0x00000001U
-#define BITSCRAMBLER_TX_FIFO_RST_S  8
-
-/** BITSCRAMBLER_RX_CTRL_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
-/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
- *  write this bit to enable the bitscrambler rx
- */
-#define BITSCRAMBLER_RX_ENA    (BIT(0))
-#define BITSCRAMBLER_RX_ENA_M  (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
-#define BITSCRAMBLER_RX_ENA_V  0x00000001U
-#define BITSCRAMBLER_RX_ENA_S  0
-/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
- *  write this bit to pause the bitscrambler rx core
- */
-#define BITSCRAMBLER_RX_PAUSE    (BIT(1))
-#define BITSCRAMBLER_RX_PAUSE_M  (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
-#define BITSCRAMBLER_RX_PAUSE_V  0x00000001U
-#define BITSCRAMBLER_RX_PAUSE_S  1
-/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
- *  write this bit to halt the bitscrambler rx core
- */
-#define BITSCRAMBLER_RX_HALT    (BIT(2))
-#define BITSCRAMBLER_RX_HALT_M  (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
-#define BITSCRAMBLER_RX_HALT_V  0x00000001U
-#define BITSCRAMBLER_RX_HALT_S  2
-/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
- *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
- *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
- *  buffer, 0 counter by write dma fifo
- */
-#define BITSCRAMBLER_RX_EOF_MODE    (BIT(3))
-#define BITSCRAMBLER_RX_EOF_MODE_M  (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
-#define BITSCRAMBLER_RX_EOF_MODE_V  0x00000001U
-#define BITSCRAMBLER_RX_EOF_MODE_S  3
-/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
- *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
- *  core, 0: use the little than operator to get the condition, 1: use not equal
- *  operator to get the condition
- */
-#define BITSCRAMBLER_RX_COND_MODE    (BIT(4))
-#define BITSCRAMBLER_RX_COND_MODE_M  (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
-#define BITSCRAMBLER_RX_COND_MODE_V  0x00000001U
-#define BITSCRAMBLER_RX_COND_MODE_S  4
-/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
- *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
- */
-#define BITSCRAMBLER_RX_FETCH_MODE    (BIT(5))
-#define BITSCRAMBLER_RX_FETCH_MODE_M  (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
-#define BITSCRAMBLER_RX_FETCH_MODE_V  0x00000001U
-#define BITSCRAMBLER_RX_FETCH_MODE_S  5
-/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
- *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
- *  wait write data back done, , 1: ignore write data back
- */
-#define BITSCRAMBLER_RX_HALT_MODE    (BIT(6))
-#define BITSCRAMBLER_RX_HALT_MODE_M  (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
-#define BITSCRAMBLER_RX_HALT_MODE_V  0x00000001U
-#define BITSCRAMBLER_RX_HALT_MODE_S  6
-/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
- *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
- *  wait read data, 1: ignore read data
- */
-#define BITSCRAMBLER_RX_RD_DUMMY    (BIT(7))
-#define BITSCRAMBLER_RX_RD_DUMMY_M  (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
-#define BITSCRAMBLER_RX_RD_DUMMY_V  0x00000001U
-#define BITSCRAMBLER_RX_RD_DUMMY_S  7
-/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
- *  write this bit to reset the bitscrambler rx fifo
- */
-#define BITSCRAMBLER_RX_FIFO_RST    (BIT(8))
-#define BITSCRAMBLER_RX_FIFO_RST_M  (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
-#define BITSCRAMBLER_RX_FIFO_RST_V  0x00000001U
-#define BITSCRAMBLER_RX_FIFO_RST_S  8
-
-/** BITSCRAMBLER_TX_STATE_REG register
- *  Status registers
- */
-#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
-/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
- *  represents the bitscrambler tx core in halt mode
- */
-#define BITSCRAMBLER_TX_IN_IDLE    (BIT(0))
-#define BITSCRAMBLER_TX_IN_IDLE_M  (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
-#define BITSCRAMBLER_TX_IN_IDLE_V  0x00000001U
-#define BITSCRAMBLER_TX_IN_IDLE_S  0
-/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
- *  represents the bitscrambler tx core in run mode
- */
-#define BITSCRAMBLER_TX_IN_RUN    (BIT(1))
-#define BITSCRAMBLER_TX_IN_RUN_M  (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
-#define BITSCRAMBLER_TX_IN_RUN_V  0x00000001U
-#define BITSCRAMBLER_TX_IN_RUN_S  1
-/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
- *  represents the bitscrambler tx core in wait mode to wait write back done
- */
-#define BITSCRAMBLER_TX_IN_WAIT    (BIT(2))
-#define BITSCRAMBLER_TX_IN_WAIT_M  (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
-#define BITSCRAMBLER_TX_IN_WAIT_V  0x00000001U
-#define BITSCRAMBLER_TX_IN_WAIT_S  2
-/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
- *  represents the bitscrambler tx core in pause mode
- */
-#define BITSCRAMBLER_TX_IN_PAUSE    (BIT(3))
-#define BITSCRAMBLER_TX_IN_PAUSE_M  (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
-#define BITSCRAMBLER_TX_IN_PAUSE_V  0x00000001U
-#define BITSCRAMBLER_TX_IN_PAUSE_S  3
-/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0;
- *  represents the bitscrambler tx fifo in empty state
- */
-#define BITSCRAMBLER_TX_FIFO_EMPTY    (BIT(4))
-#define BITSCRAMBLER_TX_FIFO_EMPTY_M  (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
-#define BITSCRAMBLER_TX_FIFO_EMPTY_V  0x00000001U
-#define BITSCRAMBLER_TX_FIFO_EMPTY_S  4
-/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
- *  represents the bytes numbers of bitscrambler tx core when get EOF
- */
-#define BITSCRAMBLER_TX_EOF_GET_CNT    0x00003FFFU
-#define BITSCRAMBLER_TX_EOF_GET_CNT_M  (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
-#define BITSCRAMBLER_TX_EOF_GET_CNT_V  0x00003FFFU
-#define BITSCRAMBLER_TX_EOF_GET_CNT_S  16
-/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
- *  represents the some EOFs will be lost for bitscrambler tx core
- */
-#define BITSCRAMBLER_TX_EOF_OVERLOAD    (BIT(30))
-#define BITSCRAMBLER_TX_EOF_OVERLOAD_M  (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
-#define BITSCRAMBLER_TX_EOF_OVERLOAD_V  0x00000001U
-#define BITSCRAMBLER_TX_EOF_OVERLOAD_S  30
-/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
- *  write this bit to clear reg_bitscrambler_tx_eof_overload and
- *  reg_bitscrambler_tx_eof_get_cnt registers
- */
-#define BITSCRAMBLER_TX_EOF_TRACE_CLR    (BIT(31))
-#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M  (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
-#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V  0x00000001U
-#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S  31
-
-/** BITSCRAMBLER_RX_STATE_REG register
- *  Status registers
- */
-#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
-/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
- *  represents the bitscrambler rx core in halt mode
- */
-#define BITSCRAMBLER_RX_IN_IDLE    (BIT(0))
-#define BITSCRAMBLER_RX_IN_IDLE_M  (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
-#define BITSCRAMBLER_RX_IN_IDLE_V  0x00000001U
-#define BITSCRAMBLER_RX_IN_IDLE_S  0
-/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
- *  represents the bitscrambler rx core in run mode
- */
-#define BITSCRAMBLER_RX_IN_RUN    (BIT(1))
-#define BITSCRAMBLER_RX_IN_RUN_M  (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
-#define BITSCRAMBLER_RX_IN_RUN_V  0x00000001U
-#define BITSCRAMBLER_RX_IN_RUN_S  1
-/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
- *  represents the bitscrambler rx core in wait mode to wait write back done
- */
-#define BITSCRAMBLER_RX_IN_WAIT    (BIT(2))
-#define BITSCRAMBLER_RX_IN_WAIT_M  (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
-#define BITSCRAMBLER_RX_IN_WAIT_V  0x00000001U
-#define BITSCRAMBLER_RX_IN_WAIT_S  2
-/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
- *  represents the bitscrambler rx core in pause mode
- */
-#define BITSCRAMBLER_RX_IN_PAUSE    (BIT(3))
-#define BITSCRAMBLER_RX_IN_PAUSE_M  (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
-#define BITSCRAMBLER_RX_IN_PAUSE_V  0x00000001U
-#define BITSCRAMBLER_RX_IN_PAUSE_S  3
-/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
- *  represents the bitscrambler rx fifo in full state
- */
-#define BITSCRAMBLER_RX_FIFO_FULL    (BIT(4))
-#define BITSCRAMBLER_RX_FIFO_FULL_M  (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
-#define BITSCRAMBLER_RX_FIFO_FULL_V  0x00000001U
-#define BITSCRAMBLER_RX_FIFO_FULL_S  4
-/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
- *  represents the bytes numbers of bitscrambler rx core when get EOF
- */
-#define BITSCRAMBLER_RX_EOF_GET_CNT    0x00003FFFU
-#define BITSCRAMBLER_RX_EOF_GET_CNT_M  (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
-#define BITSCRAMBLER_RX_EOF_GET_CNT_V  0x00003FFFU
-#define BITSCRAMBLER_RX_EOF_GET_CNT_S  16
-/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
- *  represents the some EOFs will be lost for bitscrambler rx core
- */
-#define BITSCRAMBLER_RX_EOF_OVERLOAD    (BIT(30))
-#define BITSCRAMBLER_RX_EOF_OVERLOAD_M  (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
-#define BITSCRAMBLER_RX_EOF_OVERLOAD_V  0x00000001U
-#define BITSCRAMBLER_RX_EOF_OVERLOAD_S  30
-/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
- *  write this bit to clear reg_bitscrambler_rx_eof_overload and
- *  reg_bitscrambler_rx_eof_get_cnt registers
- */
-#define BITSCRAMBLER_RX_EOF_TRACE_CLR    (BIT(31))
-#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M  (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
-#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V  0x00000001U
-#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S  31
-
-/** BITSCRAMBLER_SYS_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
-/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
- *  write this bit to set the bitscrambler tx loop back to DMA rx
- */
-#define BITSCRAMBLER_LOOP_MODE    (BIT(0))
-#define BITSCRAMBLER_LOOP_MODE_M  (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
-#define BITSCRAMBLER_LOOP_MODE_V  0x00000001U
-#define BITSCRAMBLER_LOOP_MODE_S  0
-/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Reserved
- */
-#define BITSCRAMBLER_CLK_EN    (BIT(31))
-#define BITSCRAMBLER_CLK_EN_M  (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
-#define BITSCRAMBLER_CLK_EN_V  0x00000001U
-#define BITSCRAMBLER_CLK_EN_S  31
-
-/** BITSCRAMBLER_VERSION_REG register
- *  Control and configuration registers
- */
-#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
-/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024;
- *  Reserved
- */
-#define BITSCRAMBLER_BITSCRAMBLER_VER    0x0FFFFFFFU
-#define BITSCRAMBLER_BITSCRAMBLER_VER_M  (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
-#define BITSCRAMBLER_BITSCRAMBLER_VER_V  0x0FFFFFFFU
-#define BITSCRAMBLER_BITSCRAMBLER_VER_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/beta3/include/soc/bitscrambler_struct.h
deleted file mode 100644
index cfcca328ae..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/bitscrambler_struct.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of tx_inst_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
-         *  write this bits to specify the one of 8 instruction
-         */
-        uint32_t tx_inst_idx:3;
-        /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
-         *  write this bits to specify the bit position of 257 bit instruction which in units
-         *  of 32 bits
-         */
-        uint32_t tx_inst_pos:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} bitscrambler_tx_inst_cfg0_reg_t;
-
-/** Type of tx_inst_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_inst : R/W; bitpos: [31:0]; default: 4;
-         *  write this bits to update instruction which specified by
-         *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
-         *  BITSCRAMBLER_TX_INST_CFG0_REG
-         */
-        uint32_t tx_inst:32;
-    };
-    uint32_t val;
-} bitscrambler_tx_inst_cfg1_reg_t;
-
-/** Type of rx_inst_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
-         *  write this bits to specify the one of 8 instruction
-         */
-        uint32_t rx_inst_idx:3;
-        /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
-         *  write this bits to specify the bit position of 257 bit instruction which in units
-         *  of 32 bits
-         */
-        uint32_t rx_inst_pos:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} bitscrambler_rx_inst_cfg0_reg_t;
-
-/** Type of rx_inst_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_inst : R/W; bitpos: [31:0]; default: 12;
-         *  write this bits to update instruction which specified by
-         *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
-         *  BITSCRAMBLER_RX_INST_CFG0_REG
-         */
-        uint32_t rx_inst:32;
-    };
-    uint32_t val;
-} bitscrambler_rx_inst_cfg1_reg_t;
-
-/** Type of tx_lut_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
-         *  write this bits to specify the bytes position of LUT RAM based on
-         *  reg_bitscrambler_tx_lut_mode
-         */
-        uint32_t tx_lut_idx:11;
-        /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
-         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
-         *  bytes
-         */
-        uint32_t tx_lut_mode:2;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} bitscrambler_tx_lut_cfg0_reg_t;
-
-/** Type of tx_lut_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_lut : R/W; bitpos: [31:0]; default: 20;
-         *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
-         *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
-         */
-        uint32_t tx_lut:32;
-    };
-    uint32_t val;
-} bitscrambler_tx_lut_cfg1_reg_t;
-
-/** Type of rx_lut_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
-         *  write this bits to specify the bytes position of LUT RAM based on
-         *  reg_bitscrambler_rx_lut_mode
-         */
-        uint32_t rx_lut_idx:11;
-        /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
-         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
-         *  bytes
-         */
-        uint32_t rx_lut_mode:2;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} bitscrambler_rx_lut_cfg0_reg_t;
-
-/** Type of rx_lut_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_lut : R/W; bitpos: [31:0]; default: 28;
-         *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
-         *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
-         */
-        uint32_t rx_lut:32;
-    };
-    uint32_t val;
-} bitscrambler_rx_lut_cfg1_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of tx_tailing_bits register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
-         *  write this bits to specify the extra data bit length after getting EOF
-         */
-        uint32_t tx_tailing_bits:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} bitscrambler_tx_tailing_bits_reg_t;
-
-/** Type of rx_tailing_bits register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
-         *  write this bits to specify the extra data bit length after getting EOF
-         */
-        uint32_t rx_tailing_bits:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} bitscrambler_rx_tailing_bits_reg_t;
-
-/** Type of tx_ctrl register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_ena : R/W; bitpos: [0]; default: 0;
-         *  write this bit to enable the bitscrambler tx
-         */
-        uint32_t tx_ena:1;
-        /** tx_pause : R/W; bitpos: [1]; default: 0;
-         *  write this bit to pause the bitscrambler tx core
-         */
-        uint32_t tx_pause:1;
-        /** tx_halt : R/W; bitpos: [2]; default: 1;
-         *  write this bit to halt the bitscrambler tx core
-         */
-        uint32_t tx_halt:1;
-        /** tx_eof_mode : R/W; bitpos: [3]; default: 0;
-         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
-         *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
-         *  counter by write peripheral buffer
-         */
-        uint32_t tx_eof_mode:1;
-        /** tx_cond_mode : R/W; bitpos: [4]; default: 0;
-         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
-         *  core, 0: use the little than operator to get the condition, 1: use not equal
-         *  operator to get the condition
-         */
-        uint32_t tx_cond_mode:1;
-        /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
-         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
-         */
-        uint32_t tx_fetch_mode:1;
-        /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
-         *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
-         *  wait write data back done, , 1: ignore write data back
-         */
-        uint32_t tx_halt_mode:1;
-        /** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
-         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
-         *  wait read data, 1: ignore read data
-         */
-        uint32_t tx_rd_dummy:1;
-        /** tx_fifo_rst : WT; bitpos: [8]; default: 0;
-         *  write this bit to reset the bitscrambler tx fifo
-         */
-        uint32_t tx_fifo_rst:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} bitscrambler_tx_ctrl_reg_t;
-
-/** Type of rx_ctrl register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_ena : R/W; bitpos: [0]; default: 0;
-         *  write this bit to enable the bitscrambler rx
-         */
-        uint32_t rx_ena:1;
-        /** rx_pause : R/W; bitpos: [1]; default: 0;
-         *  write this bit to pause the bitscrambler rx core
-         */
-        uint32_t rx_pause:1;
-        /** rx_halt : R/W; bitpos: [2]; default: 1;
-         *  write this bit to halt the bitscrambler rx core
-         */
-        uint32_t rx_halt:1;
-        /** rx_eof_mode : R/W; bitpos: [3]; default: 0;
-         *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
-         *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
-         *  buffer, 0 counter by write dma fifo
-         */
-        uint32_t rx_eof_mode:1;
-        /** rx_cond_mode : R/W; bitpos: [4]; default: 0;
-         *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
-         *  core, 0: use the little than operator to get the condition, 1: use not equal
-         *  operator to get the condition
-         */
-        uint32_t rx_cond_mode:1;
-        /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
-         *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
-         */
-        uint32_t rx_fetch_mode:1;
-        /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
-         *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
-         *  wait write data back done, , 1: ignore write data back
-         */
-        uint32_t rx_halt_mode:1;
-        /** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
-         *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
-         *  wait read data, 1: ignore read data
-         */
-        uint32_t rx_rd_dummy:1;
-        /** rx_fifo_rst : WT; bitpos: [8]; default: 0;
-         *  write this bit to reset the bitscrambler rx fifo
-         */
-        uint32_t rx_fifo_rst:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} bitscrambler_rx_ctrl_reg_t;
-
-/** Type of sys register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** loop_mode : R/W; bitpos: [0]; default: 0;
-         *  write this bit to set the bitscrambler tx loop back to DMA rx
-         */
-        uint32_t loop_mode:1;
-        uint32_t reserved_1:30;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Reserved
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} bitscrambler_sys_reg_t;
-
-
-/** Group: Status registers */
-/** Type of tx_state register
- *  Status registers
- */
-typedef union {
-    struct {
-        /** tx_in_idle : RO; bitpos: [0]; default: 1;
-         *  represents the bitscrambler tx core in halt mode
-         */
-        uint32_t tx_in_idle:1;
-        /** tx_in_run : RO; bitpos: [1]; default: 0;
-         *  represents the bitscrambler tx core in run mode
-         */
-        uint32_t tx_in_run:1;
-        /** tx_in_wait : RO; bitpos: [2]; default: 0;
-         *  represents the bitscrambler tx core in wait mode to wait write back done
-         */
-        uint32_t tx_in_wait:1;
-        /** tx_in_pause : RO; bitpos: [3]; default: 0;
-         *  represents the bitscrambler tx core in pause mode
-         */
-        uint32_t tx_in_pause:1;
-        /** tx_fifo_empty : RO; bitpos: [4]; default: 0;
-         *  represents the bitscrambler tx fifo in empty state
-         */
-        uint32_t tx_fifo_empty:1;
-        uint32_t reserved_5:11;
-        /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
-         *  represents the bytes numbers of bitscrambler tx core when get EOF
-         */
-        uint32_t tx_eof_get_cnt:14;
-        /** tx_eof_overload : RO; bitpos: [30]; default: 0;
-         *  represents the some EOFs will be lost for bitscrambler tx core
-         */
-        uint32_t tx_eof_overload:1;
-        /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
-         *  write this bit to clear reg_bitscrambler_tx_eof_overload and
-         *  reg_bitscrambler_tx_eof_get_cnt registers
-         */
-        uint32_t tx_eof_trace_clr:1;
-    };
-    uint32_t val;
-} bitscrambler_tx_state_reg_t;
-
-/** Type of rx_state register
- *  Status registers
- */
-typedef union {
-    struct {
-        /** rx_in_idle : RO; bitpos: [0]; default: 1;
-         *  represents the bitscrambler rx core in halt mode
-         */
-        uint32_t rx_in_idle:1;
-        /** rx_in_run : RO; bitpos: [1]; default: 0;
-         *  represents the bitscrambler rx core in run mode
-         */
-        uint32_t rx_in_run:1;
-        /** rx_in_wait : RO; bitpos: [2]; default: 0;
-         *  represents the bitscrambler rx core in wait mode to wait write back done
-         */
-        uint32_t rx_in_wait:1;
-        /** rx_in_pause : RO; bitpos: [3]; default: 0;
-         *  represents the bitscrambler rx core in pause mode
-         */
-        uint32_t rx_in_pause:1;
-        /** rx_fifo_full : RO; bitpos: [4]; default: 0;
-         *  represents the bitscrambler rx fifo in full state
-         */
-        uint32_t rx_fifo_full:1;
-        uint32_t reserved_5:11;
-        /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
-         *  represents the bytes numbers of bitscrambler rx core when get EOF
-         */
-        uint32_t rx_eof_get_cnt:14;
-        /** rx_eof_overload : RO; bitpos: [30]; default: 0;
-         *  represents the some EOFs will be lost for bitscrambler rx core
-         */
-        uint32_t rx_eof_overload:1;
-        /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
-         *  write this bit to clear reg_bitscrambler_rx_eof_overload and
-         *  reg_bitscrambler_rx_eof_get_cnt registers
-         */
-        uint32_t rx_eof_trace_clr:1;
-    };
-    uint32_t val;
-} bitscrambler_rx_state_reg_t;
-
-
-/** Group: Version register */
-/** Type of version register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
-         *  Reserved
-         */
-        uint32_t bitscrambler_ver:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} bitscrambler_version_reg_t;
-
-
-typedef struct bitscrambler_dev_t {
-    volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
-    volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
-    volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
-    volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
-    volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
-    volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
-    volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
-    volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
-    volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
-    volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
-    volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
-    volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
-    volatile bitscrambler_tx_state_reg_t tx_state;
-    volatile bitscrambler_rx_state_reg_t rx_state;
-    uint32_t reserved_038[48];
-    volatile bitscrambler_sys_reg_t sys;
-    volatile bitscrambler_version_reg_t version;
-} bitscrambler_dev_t;
-
-extern bitscrambler_dev_t BITSCRAMBLER;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/cache_reg.h b/components/soc/esp32c5/beta3/include/soc/cache_reg.h
deleted file mode 100644
index 34bacbb706..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/cache_reg.h
+++ /dev/null
@@ -1,1289 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** CACHE_L1_CACHE_CTRL_REG register
- *  L1 data Cache(L1-Cache) control register
- */
-#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
-/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0;
- *  The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_BUS0    (BIT(0))
-#define CACHE_L1_CACHE_SHUT_BUS0_M  (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S)
-#define CACHE_L1_CACHE_SHUT_BUS0_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_BUS0_S  0
-/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0;
- *  The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_BUS1    (BIT(1))
-#define CACHE_L1_CACHE_SHUT_BUS1_M  (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S)
-#define CACHE_L1_CACHE_SHUT_BUS1_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_BUS1_S  1
-/** CACHE_L1_CACHE_SHUT_DBUS2 : R/W; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_SHUT_DBUS2    (BIT(2))
-#define CACHE_L1_CACHE_SHUT_DBUS2_M  (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S)
-#define CACHE_L1_CACHE_SHUT_DBUS2_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DBUS2_S  2
-/** CACHE_L1_CACHE_SHUT_DBUS3 : R/W; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_SHUT_DBUS3    (BIT(3))
-#define CACHE_L1_CACHE_SHUT_DBUS3_M  (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S)
-#define CACHE_L1_CACHE_SHUT_DBUS3_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DBUS3_S  3
-
-/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
-/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0;
- *  Set this bit as 1 to enable L1-DCache wrap around mode.
- */
-#define CACHE_L1_CACHE_WRAP    (BIT(4))
-#define CACHE_L1_CACHE_WRAP_M  (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S)
-#define CACHE_L1_CACHE_WRAP_V  0x00000001U
-#define CACHE_L1_CACHE_WRAP_S  4
-
-/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register
- *  Cache tag memory power control register
- */
-#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
-/** CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
- *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S  16
-/** CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
- *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
- */
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S  17
-/** CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
- *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S  18
-
-/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register
- *  Cache data memory power control register
- */
-#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
-/** CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
- *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S  16
-/** CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
- *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S  17
-/** CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
- *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S  18
-
-/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
- *  Cache Freeze control register
- */
-#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
-/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
- *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
- *  software.
- */
-#define CACHE_L1_CACHE_FREEZE_EN    (BIT(16))
-#define CACHE_L1_CACHE_FREEZE_EN_M  (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S)
-#define CACHE_L1_CACHE_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_EN_S  16
-/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_CACHE_FREEZE_MODE    (BIT(17))
-#define CACHE_L1_CACHE_FREEZE_MODE_M  (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S)
-#define CACHE_L1_CACHE_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_MODE_S  17
-/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_CACHE_FREEZE_DONE    (BIT(18))
-#define CACHE_L1_CACHE_FREEZE_DONE_M  (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S)
-#define CACHE_L1_CACHE_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_DONE_S  18
-
-/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
- *  Cache data memory access configure register
- */
-#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
-/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
- *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M  (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S)
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S  16
-/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
- *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M  (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S)
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S  17
-
-/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
- *  Cache tag memory access configure register
- */
-#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
-/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
- *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M  (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S)
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S  16
-/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
- *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M  (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S)
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S  17
-
-/** CACHE_L1_CACHE_PRELOCK_CONF_REG register
- *  L1 Cache prelock configure register
- */
-#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-Cache.
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-Cache.
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 cache prelock.
- */
-#define CACHE_L1_CACHE_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_CACHE_PRELOCK_RGID_M  (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S)
-#define CACHE_L1_CACHE_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_PRELOCK_RGID_S  2
-
-/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register
- *  L1 Cache prelock section0 address configure register
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-Cache, which should be used together with
- *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
- *  L1 Cache prelock section1 address configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
-/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-Cache, which should be used together with
- *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
- *  L1  Cache prelock section size configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_LOCK_CTRL_REG register
- *  Lock-class (manual lock) operation control register
- */
-#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88)
-/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable lock operation. It will be cleared by hardware after lock
- *  operation done
- */
-#define CACHE_LOCK_ENA    (BIT(0))
-#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
-#define CACHE_LOCK_ENA_V  0x00000001U
-#define CACHE_LOCK_ENA_S  0
-/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable unlock operation. It will be cleared by hardware after
- *  unlock operation done
- */
-#define CACHE_UNLOCK_ENA    (BIT(1))
-#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
-#define CACHE_UNLOCK_ENA_V  0x00000001U
-#define CACHE_UNLOCK_ENA_S  1
-/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
- *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
- *  not finished. 1: finished.
- */
-#define CACHE_LOCK_DONE    (BIT(2))
-#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
-#define CACHE_LOCK_DONE_V  0x00000001U
-#define CACHE_LOCK_DONE_S  2
-/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of cache lock/unlock.
- */
-#define CACHE_LOCK_RGID    0x0000000FU
-#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
-#define CACHE_LOCK_RGID_V  0x0000000FU
-#define CACHE_LOCK_RGID_S  3
-
-/** CACHE_LOCK_MAP_REG register
- *  Lock (manual lock) map configure register
- */
-#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c)
-/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply this lock/unlock operation. [4]: L1-Cache
- */
-#define CACHE_LOCK_MAP    0x0000003FU
-#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
-#define CACHE_LOCK_MAP_V  0x0000003FU
-#define CACHE_LOCK_MAP_S  0
-
-/** CACHE_LOCK_ADDR_REG register
- *  Lock (manual lock) address configure register
- */
-#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90)
-/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the lock/unlock
- *  operation, which should be used together with CACHE_LOCK_SIZE_REG
- */
-#define CACHE_LOCK_ADDR    0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
-#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_S  0
-
-/** CACHE_LOCK_SIZE_REG register
- *  Lock (manual lock) size configure register
- */
-#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94)
-/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
- *  Those bits are used to configure the size of the lock/unlock operation, which
- *  should be used together with CACHE_LOCK_ADDR_REG
- */
-#define CACHE_LOCK_SIZE    0x0000FFFFU
-#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
-#define CACHE_LOCK_SIZE_V  0x0000FFFFU
-#define CACHE_LOCK_SIZE_S  0
-
-/** CACHE_SYNC_CTRL_REG register
- *  Sync-class operation control register
- */
-#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
-/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
- *  The bit is used to enable invalidate operation. It will be cleared by hardware
- *  after invalidate operation done. Note that this bit and the other sync-bits
- *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_INVALIDATE_ENA    (BIT(0))
-#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
-#define CACHE_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_INVALIDATE_ENA_S  0
-/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable clean operation. It will be cleared by hardware after
- *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
- *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
- *  bits can not be set to 1 at the same time.
- */
-#define CACHE_CLEAN_ENA    (BIT(1))
-#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
-#define CACHE_CLEAN_ENA_V  0x00000001U
-#define CACHE_CLEAN_ENA_S  1
-/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
- *  The bit is used to enable writeback operation. It will be cleared by hardware after
- *  writeback operation done. Note that this bit and the other sync-bits
- *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_ENA    (BIT(2))
-#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
-#define CACHE_WRITEBACK_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_ENA_S  2
-/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
- *  The bit is used to enable writeback-invalidate operation. It will be cleared by
- *  hardware after writeback-invalidate operation done. Note that this bit and the
- *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
- *  that is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
-#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
-#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
-/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
- *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
- *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
- */
-#define CACHE_SYNC_DONE    (BIT(4))
-#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
-#define CACHE_SYNC_DONE_V  0x00000001U
-#define CACHE_SYNC_DONE_S  4
-/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0;
- *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
- *  writeback, writeback_invalidate)
- */
-#define CACHE_SYNC_RGID    0x0000000FU
-#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
-#define CACHE_SYNC_RGID_V  0x0000000FU
-#define CACHE_SYNC_RGID_S  5
-
-/** CACHE_SYNC_MAP_REG register
- *  Sync map configure register
- */
-#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c)
-/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply the sync operation.  [4]: L1-Cache
- */
-#define CACHE_SYNC_MAP    0x0000003FU
-#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
-#define CACHE_SYNC_MAP_V  0x0000003FU
-#define CACHE_SYNC_MAP_S  0
-
-/** CACHE_SYNC_ADDR_REG register
- *  Sync address configure register
- */
-#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0)
-/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the sync operation,
- *  which should be used together with CACHE_SYNC_SIZE_REG
- */
-#define CACHE_SYNC_ADDR    0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
-#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_S  0
-
-/** CACHE_SYNC_SIZE_REG register
- *  Sync size configure register
- */
-#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4)
-/** CACHE_SYNC_SIZE : R/W; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the sync operation, which should be
- *  used together with CACHE_SYNC_ADDR_REG
- */
-#define CACHE_SYNC_SIZE    0x00FFFFFFU
-#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
-#define CACHE_SYNC_SIZE_V  0x00FFFFFFU
-#define CACHE_SYNC_SIZE_S  0
-
-/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register
- *  L1 Cache  preload-operation control register
- */
-#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8)
-/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_CACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_PRELOAD_ENA_M  (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S)
-#define CACHE_L1_CACHE_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_ENA_S  0
-/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_CACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_PRELOAD_DONE_M  (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S)
-#define CACHE_L1_CACHE_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_DONE_S  1
-/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_CACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_PRELOAD_ORDER_M  (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S)
-#define CACHE_L1_CACHE_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_ORDER_S  2
-/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 cache preload.
- */
-#define CACHE_L1_CACHE_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_CACHE_PRELOAD_RGID_M  (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S)
-#define CACHE_L1_CACHE_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_PRELOAD_RGID_S  3
-
-/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
- *  L1 Cache  preload address configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc)
-/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on L1-Cache,
- *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOAD_ADDR_M  (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S)
-#define CACHE_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
- *  L1 Cache  preload size configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0)
-/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOAD_SIZE_M  (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S)
-#define CACHE_L1_CACHE_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register
- *  L1 Cache autoload-operation control register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134)
-/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_S  0
-/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_M  (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_S  1
-/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M  (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S)
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
- *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 Cache autoload section 0 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 Cache autoload section 0 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 Cache autoload section 1 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 Cache autoload section 1 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
- *  Cache Access Counter Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158)
-/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ENA_M  (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S)
-#define CACHE_L1_BUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_ENA_S  4
-/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ENA_M  (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S)
-#define CACHE_L1_BUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_ENA_S  5
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
- *  Cache Access Counter Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c)
-/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_CLR_M  (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S)
-#define CACHE_L1_BUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_CLR_S  4
-/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_CLR_M  (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S)
-#define CACHE_L1_BUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_CLR_S  5
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
- *  Cache Access Counter Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
-/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_RAW    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_RAW_M  (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S)
-#define CACHE_L1_BUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_RAW_S  4
-/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_RAW    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_RAW_M  (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S)
-#define CACHE_L1_BUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_RAW_S  5
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
- *  Cache Access Counter Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164)
-/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_ST    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ST_M  (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S)
-#define CACHE_L1_BUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_ST_S  4
-/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_ST    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ST_M  (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S)
-#define CACHE_L1_BUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_ST_S  5
-
-/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
- *  Cache Access Fail Configuration register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x168)
-/** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
- *  The bit is used to configure l1 cache access fail check mode. 0: the access fail is
- *  not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
- *  Cache Access Fail Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x16c)
-/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ENA_M  (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S)
-#define CACHE_L1_CACHE_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_ENA_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
- *  L1-Cache Access Fail Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x170)
-/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_CLR_M  (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S)
-#define CACHE_L1_CACHE_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_CLR_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
- *  Cache Access Fail Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x174)
-/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_RAW_M  (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S)
-#define CACHE_L1_CACHE_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_RAW_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
- *  Cache Access Fail Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x178)
-/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
- *  to cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ST_M  (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S)
-#define CACHE_L1_CACHE_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_ST_S  4
-
-/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
- *  Cache Access Counter enable and clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x17c)
-/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_BUS0_CNT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_CNT_ENA_M  (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S)
-#define CACHE_L1_BUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L1_BUS0_CNT_ENA_S  4
-/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_BUS1_CNT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_CNT_ENA_M  (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S)
-#define CACHE_L1_BUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L1_BUS1_CNT_ENA_S  5
-/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
- *  The bit is used to clear dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_BUS0_CNT_CLR    (BIT(20))
-#define CACHE_L1_BUS0_CNT_CLR_M  (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S)
-#define CACHE_L1_BUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L1_BUS0_CNT_CLR_S  20
-/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
- *  The bit is used to clear dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_BUS1_CNT_CLR    (BIT(21))
-#define CACHE_L1_BUS1_CNT_CLR_M  (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S)
-#define CACHE_L1_BUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L1_BUS1_CNT_CLR_S  21
-
-/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
-/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_HIT_CNT_M  (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S)
-#define CACHE_L1_BUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_HIT_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
-/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_MISS_CNT_M  (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S)
-#define CACHE_L1_BUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_MISS_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
-/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M  (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S)
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
-/** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus0 accessing L1-Cache.
- */
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT_M  (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus0 WB-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
-/** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT_M  (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S)
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
-/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_HIT_CNT_M  (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S)
-#define CACHE_L1_BUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_HIT_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
-/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_MISS_CNT_M  (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S)
-#define CACHE_L1_BUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_MISS_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
-/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_CONFLICT_CNT_M  (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S)
-#define CACHE_L1_BUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
-/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus1 accessing L1-Cache.
- */
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus1 WB-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
-/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x210)
-/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
-#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_S  0
-/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x214)
-/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x218)
-/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
-#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_S  0
-/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x21c)
-/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
-
-/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
- *  L1-Cache Access Fail ID/attribution information register
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x230)
-/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ID_M  (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S)
-#define CACHE_L1_CACHE_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ID_S  0
-/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ATTR_M  (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S)
-#define CACHE_L1_CACHE_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ATTR_S  16
-
-/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
- *  L1-Cache Access Fail Address information register
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x234)
-/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_FAIL_ADDR_M  (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S)
-#define CACHE_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_FAIL_ADDR_S  0
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG register
- *  L1-Cache Access Fail Interrupt enable register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x238)
-/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S  4
-/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation done.
- */
-#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
-#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ENA_S  6
-/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The bit is used to enable interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S  11
-/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
-#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ENA_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG register
- *  Sync Preload operation Interrupt clear register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x23c)
-/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
- *  is done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S  4
-/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
- *  done.
- */
-#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
-#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
-#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_CLR_S  6
-/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The bit is used to clear interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S  11
-/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The bit is used to clear interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
-#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
-#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_CLR_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG register
- *  Sync Preload operation Interrupt raw register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x240)
-/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
- *  done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S  4
-/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
-#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
-#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_RAW_S  6
-/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
- *  occurs.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S  11
-/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation error
- *  occurs.
- */
-#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
-#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
-#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_RAW_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG register
- *  L1-Cache Access Fail Interrupt status register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x244)
-/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-Cache
- *  preload-operation is done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M  (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S  4
-/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when Cache
- *  sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
-#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ST_S  6
-/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
- *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S  11
-/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
- *  The bit indicates the status of the interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
-#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ST_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG register
- *  Cache Sync/Preload Operation exception register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x248)
-/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-Cache.
- */
-#define CACHE_L1_CACHE_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_CACHE_PLD_ERR_CODE_M  (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S)
-#define CACHE_L1_CACHE_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_CACHE_PLD_ERR_CODE_S  8
-/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
- *  The values 0-2 are available which means sync map, command conflict and size are
- *  error in Cache System.
- */
-#define CACHE_SYNC_ERR_CODE    0x00000003U
-#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
-#define CACHE_SYNC_ERR_CODE_V  0x00000003U
-#define CACHE_SYNC_ERR_CODE_S  12
-
-/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
- *  Cache Sync Reset control register
- */
-#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c)
-/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
-#define CACHE_L1_CACHE_SYNC_RST_M  (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S)
-#define CACHE_L1_CACHE_SYNC_RST_V  0x00000001U
-#define CACHE_L1_CACHE_SYNC_RST_S  4
-
-/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
- *  Cache Preload Reset control register
- */
-#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
-/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_CACHE_PLD_RST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_RST_M  (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S)
-#define CACHE_L1_CACHE_PLD_RST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_RST_S  4
-
-/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
- *  Cache Autoload buffer clear control register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x254)
-/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
- *  autoload will not work in L1-Cache. This bit should not be active when autoload
- *  works in L1-Cache.
- */
-#define CACHE_L1_CACHE_ALD_BUF_CLR    (BIT(4))
-#define CACHE_L1_CACHE_ALD_BUF_CLR_M  (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S)
-#define CACHE_L1_CACHE_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_ALD_BUF_CLR_S  4
-
-/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
- *  Unallocate request buffer clear registers
- */
-#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258)
-/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 cache where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
-#define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
-#define CACHE_L1_CACHE_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_UNALLOC_CLR_S  4
-
-/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
- *  Cache Tag and Data memory Object control register
- */
-#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x25c)
-/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
- *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
-#define CACHE_L1_CACHE_TAG_OBJECT_M  (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S)
-#define CACHE_L1_CACHE_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_OBJECT_S  4
-/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
- *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_CACHE_MEM_OBJECT    (BIT(10))
-#define CACHE_L1_CACHE_MEM_OBJECT_M  (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S)
-#define CACHE_L1_CACHE_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_CACHE_MEM_OBJECT_S  10
-
-/** CACHE_L1_CACHE_WAY_OBJECT_REG register
- *  Cache Tag and Data memory way register
- */
-#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x260)
-/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
- *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
- *  way1, 2: way2, 3: way3, ?, 7: way7.
- */
-#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
-#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_S  0
-
-/** CACHE_L1_CACHE_VADDR_REG register
- *  Cache Vaddr register
- */
-#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x264)
-/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
- *  Those bits stores the virtual address which will decide where inside the specified
- *  tag memory object will be accessed.
- */
-#define CACHE_L1_CACHE_VADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_VADDR_M  (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S)
-#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_VADDR_S  0
-
-/** CACHE_L1_CACHE_DEBUG_BUS_REG register
- *  Cache Tag/data memory content register
- */
-#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x268)
-/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 616;
- *  This is a constant place where we can write data to or read data from the tag/data
- *  memory on the specified cache.
- */
-#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
-#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_S  0
-
-/** CACHE_DATE_REG register
- *  Version control register
- */
-#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
-/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36716800;
- *  version control register. Note that this default value stored is the latest date
- *  when the hardware logic was updated.
- */
-#define CACHE_DATE    0x0FFFFFFFU
-#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
-#define CACHE_DATE_V  0x0FFFFFFFU
-#define CACHE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/cache_struct.h b/components/soc/esp32c5/beta3/include/soc/cache_struct.h
deleted file mode 100644
index 871f93c19e..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/cache_struct.h
+++ /dev/null
@@ -1,1410 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of l1_cache_ctrl register
- *  L1 data Cache(L1-Cache) control register
- */
-typedef union {
-    struct {
-        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus0:1;
-        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus1:1;
-        /** l1_cache_shut_dbus2 : R/W; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus2:1;
-        /** l1_cache_shut_dbus3 : R/W; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus3:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} cache_l1_cache_ctrl_reg_t;
-
-
-/** Group: Wrap Mode Control and configuration registers */
-/** Type of l1_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
-         *  Set this bit as 1 to enable L1-DCache wrap around mode.
-         */
-        uint32_t l1_cache_wrap:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_wrap_around_ctrl_reg_t;
-
-
-/** Group: Cache Tag Memory Power Control registers */
-/** Type of l1_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_tag_mem_force_on:1;
-        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l1_cache_tag_mem_force_pd:1;
-        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_tag_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} cache_l1_cache_tag_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Power Control registers */
-/** Type of l1_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_data_mem_force_on:1;
-        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_cache_data_mem_force_pd:1;
-        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_data_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} cache_l1_cache_data_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Freeze Control registers */
-/** Type of l1_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_cache_freeze_en:1;
-        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_cache_freeze_mode:1;
-        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_freeze_done:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} cache_l1_cache_freeze_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Access Control and Configuration registers */
-/** Type of l1_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_rd_en:1;
-        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} cache_l1_cache_data_mem_acs_conf_reg_t;
-
-
-/** Group: Cache Tag Memory Access Control and Configuration registers */
-/** Type of l1_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_rd_en:1;
-        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} cache_l1_cache_tag_mem_acs_conf_reg_t;
-
-
-/** Group: Prelock Control and configuration registers */
-/** Type of l1_cache_prelock_conf register
- *  L1 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct0_en:1;
-        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct1_en:1;
-        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 cache prelock.
-         */
-        uint32_t l1_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_prelock_conf_reg_t;
-
-/** Type of l1_cache_prelock_sct0_addr register
- *  L1 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct1_addr register
- *  L1 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_prelock_sct1_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct_size register
- *  L1  Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_dcache_prelock_sct_size_reg_t;
-
-
-/** Group: Lock Control and configuration registers */
-/** Type of lock_ctrl register
- *  Lock-class (manual lock) operation control register
- */
-typedef union {
-    struct {
-        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
-         *  operation done
-         */
-        uint32_t lock_ena:1;
-        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable unlock operation. It will be cleared by hardware after
-         *  unlock operation done
-         */
-        uint32_t unlock_ena:1;
-        /** lock_done : RO; bitpos: [2]; default: 1;
-         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
-         *  not finished. 1: finished.
-         */
-        uint32_t lock_done:1;
-        /** lock_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of cache lock/unlock.
-         */
-        uint32_t lock_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_lock_ctrl_reg_t;
-
-/** Type of lock_map register
- *  Lock (manual lock) map configure register
- */
-typedef union {
-    struct {
-        /** lock_map : R/W; bitpos: [5:0]; default: 0;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply this lock/unlock operation. [4]: L1-Cache
-         */
-        uint32_t lock_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_lock_map_reg_t;
-
-/** Type of lock_addr register
- *  Lock (manual lock) address configure register
- */
-typedef union {
-    struct {
-        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the lock/unlock
-         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
-         */
-        uint32_t lock_addr:32;
-    };
-    uint32_t val;
-} cache_lock_addr_reg_t;
-
-/** Type of lock_size register
- *  Lock (manual lock) size configure register
- */
-typedef union {
-    struct {
-        /** lock_size : R/W; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the lock/unlock operation, which
-         *  should be used together with CACHE_LOCK_ADDR_REG
-         */
-        uint32_t lock_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_lock_size_reg_t;
-
-
-/** Group: Sync Control and configuration registers */
-/** Type of sync_ctrl register
- *  Sync-class operation control register
- */
-typedef union {
-    struct {
-        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
-         *  The bit is used to enable invalidate operation. It will be cleared by hardware
-         *  after invalidate operation done. Note that this bit and the other sync-bits
-         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t invalidate_ena:1;
-        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable clean operation. It will be cleared by hardware after
-         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
-         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
-         *  bits can not be set to 1 at the same time.
-         */
-        uint32_t clean_ena:1;
-        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
-         *  The bit is used to enable writeback operation. It will be cleared by hardware after
-         *  writeback operation done. Note that this bit and the other sync-bits
-         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t writeback_ena:1;
-        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
-         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
-         *  hardware after writeback-invalidate operation done. Note that this bit and the
-         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
-         *  that is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t writeback_invalidate_ena:1;
-        /** sync_done : RO; bitpos: [4]; default: 0;
-         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
-         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
-         */
-        uint32_t sync_done:1;
-        /** sync_rgid : HRO; bitpos: [8:5]; default: 0;
-         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
-         *  writeback, writeback_invalidate)
-         */
-        uint32_t sync_rgid:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} cache_sync_ctrl_reg_t;
-
-/** Type of sync_map register
- *  Sync map configure register
- */
-typedef union {
-    struct {
-        /** sync_map : R/W; bitpos: [5:0]; default: 63;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply the sync operation.  [4]: L1-Cache
-         */
-        uint32_t sync_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_sync_map_reg_t;
-
-/** Type of sync_addr register
- *  Sync address configure register
- */
-typedef union {
-    struct {
-        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the sync operation,
-         *  which should be used together with CACHE_SYNC_SIZE_REG
-         */
-        uint32_t sync_addr:32;
-    };
-    uint32_t val;
-} cache_sync_addr_reg_t;
-
-/** Type of sync_size register
- *  Sync size configure register
- */
-typedef union {
-    struct {
-        /** sync_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the sync operation, which should be
-         *  used together with CACHE_SYNC_ADDR_REG
-         */
-        uint32_t sync_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_sync_size_reg_t;
-
-
-/** Group: Preload Control and configuration registers */
-/** Type of l1_cache_preload_ctrl register
- *  L1 Cache  preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_cache_preload_ena:1;
-        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_cache_preload_done:1;
-        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_cache_preload_order:1;
-        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 cache preload.
-         */
-        uint32_t l1_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_cache_preload_ctrl_reg_t;
-
-/** Type of l1_dcache_preload_addr register
- *  L1 Cache  preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
-         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_cache_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_preload_addr_reg_t;
-
-/** Type of l1_dcache_preload_size register
- *  L1 Cache  preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_cache_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_dcache_preload_size_reg_t;
-
-
-/** Group: Autoload Control and configuration registers */
-/** Type of l1_cache_autoload_ctrl register
- *  L1 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_cache_autoload_ena:1;
-        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_autoload_done:1;
-        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_cache_autoload_order:1;
-        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct0_ena:1;
-        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct1_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_ctrl_reg_t;
-
-/** Type of l1_cache_autoload_sct0_addr register
- *  L1 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct0_size register
- *  L1 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct0_size_reg_t;
-
-/** Type of l1_cache_autoload_sct1_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct1_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct1_size_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of l1_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_ena:1;
-        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_clr:1;
-        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_raw:1;
-        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_st:1;
-        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l1_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l1_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l1_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l1_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
-         *  to cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_st_reg_t;
-
-/** Type of sync_l1_cache_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_cache_pld_done_int_ena:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation done.
-         */
-        uint32_t sync_done_int_ena:1;
-        uint32_t reserved_7:4;
-        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_ena:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_ena:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_sync_l1_cache_preload_int_ena_reg_t;
-
-/** Type of sync_l1_cache_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l1_cache_pld_done_int_clr:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
-         *  done.
-         */
-        uint32_t sync_done_int_clr:1;
-        uint32_t reserved_7:4;
-        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
-         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_clr:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
-         *  The bit is used to clear interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_clr:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_sync_l1_cache_preload_int_clr_reg_t;
-
-/** Type of sync_l1_cache_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l1_cache_pld_done_int_raw:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
-         */
-        uint32_t sync_done_int_raw:1;
-        uint32_t reserved_7:4;
-        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_err_int_raw:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
-         *  occurs.
-         */
-        uint32_t sync_err_int_raw:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_sync_l1_cache_preload_int_raw_reg_t;
-
-/** Type of sync_l1_cache_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l1_cache_pld_done_int_st:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when Cache
-         *  sync-operation is done.
-         */
-        uint32_t sync_done_int_st:1;
-        uint32_t reserved_7:4;
-        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_st:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
-         *  The bit indicates the status of the interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_st:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_sync_l1_cache_preload_int_st_reg_t;
-
-
-/** Group: Cache Access Fail Configuration register */
-/** Type of l1_cache_acs_fail_ctrl register
- *  Cache Access Fail Configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to configure l1 cache access fail check mode. 0: the access fail is
-         *  not propagated to the request, 1: the access fail is propagated to the request
-         */
-        uint32_t l1_cache_acs_fail_check_mode:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_ctrl_reg_t;
-
-
-/** Group: Access Statistics registers */
-/** Type of l1_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_ena:1;
-        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_ena:1;
-        uint32_t reserved_6:14;
-        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
-         *  The bit is used to clear dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_clr:1;
-        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
-         *  The bit is used to clear dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_clr:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l1_bus0_acs_hit_cnt register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus0_acs_miss_cnt register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus0_acs_conflict_cnt register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_conflict_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus0 accessing L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register
- *  L1-DCache bus0 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l1_bus1_acs_hit_cnt register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus1_acs_miss_cnt register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus1_acs_conflict_cnt register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register
- *  L1-DCache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus1 accessing L1-Cache.
-         */
-        uint32_t l1_dbus1_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register
- *  L1-DCache bus1 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_dbus1_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t;
-
-
-/** Group: Access Fail Debug registers */
-/** Type of l1_icache0_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_id:16;
-        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache0_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache0_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_acs_fail_addr_reg_t;
-
-/** Type of l1_icache1_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_id:16;
-        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache1_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache1_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_acs_fail_addr_reg_t;
-
-/** Type of l1_dcache_acs_fail_id_attr register
- *  L1-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_id:16;
-        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_dcache_acs_fail_id_attr_reg_t;
-
-/** Type of l1_dcache_acs_fail_addr register
- *  L1-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_acs_fail_addr_reg_t;
-
-
-/** Group: Operation Exception registers */
-/** Type of sync_l1_cache_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-Cache.
-         */
-        uint32_t l1_cache_pld_err_code:2;
-        uint32_t reserved_10:2;
-        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
-         *  The values 0-2 are available which means sync map, command conflict and size are
-         *  error in Cache System.
-         */
-        uint32_t sync_err_code:2;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_sync_l1_cache_preload_exception_reg_t;
-
-
-/** Group: Sync Reset control and configuration registers */
-/** Type of l1_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_cache_sync_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_rst_ctrl_reg_t;
-
-
-/** Group: Preload Reset control and configuration registers */
-/** Type of l1_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_preload_rst_ctrl_reg_t;
-
-
-/** Group: Autoload buffer clear control and configuration registers */
-/** Type of l1_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
-         *  autoload will not work in L1-Cache. This bit should not be active when autoload
-         *  works in L1-Cache.
-         */
-        uint32_t l1_cache_ald_buf_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
-
-
-/** Group: Unallocate request buffer clear registers */
-/** Type of l1_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_cache_unalloc_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_unallocate_buffer_clear_reg_t;
-
-
-/** Group: Tag and Data Memory Access Control and configuration register */
-/** Type of l1_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_tag_object:1;
-        uint32_t reserved_5:5;
-        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_mem_object:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} cache_l1_cache_object_ctrl_reg_t;
-
-/** Type of l1_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l1_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} cache_l1_cache_way_object_reg_t;
-
-/** Type of l1_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l1_cache_vaddr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_vaddr_reg_t;
-
-/** Type of l1_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 616;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l1_cache_debug_bus:32;
-    };
-    uint32_t val;
-} cache_l1_cache_debug_bus_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36716800;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_date_reg_t;
-
-
-typedef struct cache_dev_t {
-    uint32_t reserved_000;
-    volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl;
-    uint32_t reserved_008[6];
-    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
-    volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
-    volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
-    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
-    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
-    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
-    uint32_t reserved_038[16];
-    volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
-    volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
-    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
-    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
-    volatile cache_lock_ctrl_reg_t lock_ctrl;
-    volatile cache_lock_map_reg_t lock_map;
-    volatile cache_lock_addr_reg_t lock_addr;
-    volatile cache_lock_size_reg_t lock_size;
-    volatile cache_sync_ctrl_reg_t sync_ctrl;
-    volatile cache_sync_map_reg_t sync_map;
-    volatile cache_sync_addr_reg_t sync_addr;
-    volatile cache_sync_size_reg_t sync_size;
-    uint32_t reserved_0a8[12];
-    volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
-    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
-    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
-    uint32_t reserved_0e4[20];
-    volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
-    volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
-    volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
-    volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
-    volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
-    uint32_t reserved_148[4];
-    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
-    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
-    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
-    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
-    volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl;
-    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
-    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
-    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
-    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
-    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
-    uint32_t reserved_180[16];
-    volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
-    volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
-    volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
-    volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt;
-    volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
-    volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
-    volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
-    volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt;
-    uint32_t reserved_1e8[10];
-    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
-    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
-    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
-    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
-    uint32_t reserved_220[4];
-    volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr;
-    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
-    volatile cache_sync_l1_cache_preload_int_ena_reg_t sync_l1_cache_preload_int_ena;
-    volatile cache_sync_l1_cache_preload_int_clr_reg_t sync_l1_cache_preload_int_clr;
-    volatile cache_sync_l1_cache_preload_int_raw_reg_t sync_l1_cache_preload_int_raw;
-    volatile cache_sync_l1_cache_preload_int_st_reg_t sync_l1_cache_preload_int_st;
-    volatile cache_sync_l1_cache_preload_exception_reg_t sync_l1_cache_preload_exception;
-    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
-    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
-    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
-    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
-    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
-    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
-    volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr;
-    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
-    uint32_t reserved_26c[100];
-    volatile cache_date_reg_t date;
-} cache_dev_t;
-
-extern cache_dev_t CACHE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/clic_reg.h b/components/soc/esp32c5/beta3/include/soc/clic_reg.h
deleted file mode 100644
index 1bfe74d623..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/clic_reg.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NLBITS                   3
-#define CLIC_EXT_INTR_NUM_OFFSET 16
-#define DUALCORE_CLIC_CTRL_OFF   0x10000
-
-#define DR_REG_CLIC_BASE      ( 0x20800000 )
-#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
-
-#define CLIC_INT_CONFIG_REG          (DR_REG_CLIC_BASE + 0x0)
-/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
-/*description: .*/
-#define CLIC_INT_CONFIG_NMBITS    0x00000003
-#define CLIC_INT_CONFIG_NMBITS_M  ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S))
-#define CLIC_INT_CONFIG_NMBITS_V  0x3
-#define CLIC_INT_CONFIG_NMBITS_S  5
-/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
-/*description: .*/
-#define CLIC_INT_CONFIG_NLBITS    0x0000000F
-#define CLIC_INT_CONFIG_NLBITS_M  ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S))
-#define CLIC_INT_CONFIG_NLBITS_V  0xF
-#define CLIC_INT_CONFIG_NLBITS_S  1
-/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
-/*description: .*/
-#define CLIC_INT_CONFIG_NVBITS    (BIT(0))
-#define CLIC_INT_CONFIG_NVBITS_M  (BIT(0))
-#define CLIC_INT_CONFIG_NVBITS_V  0x1
-#define CLIC_INT_CONFIG_NVBITS_S  0
-
-#define CLIC_INT_INFO_REG          (DR_REG_CLIC_BASE + 0x4)
-/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
-/*description: .*/
-#define CLIC_INT_INFO_CTLBITS    0x0000000F
-#define CLIC_INT_INFO_CTLBITS_M  ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S))
-#define CLIC_INT_INFO_CTLBITS_V  0xF
-#define CLIC_INT_INFO_CTLBITS_S  21
-/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
-/*description: .*/
-#define CLIC_INT_INFO_VERSION    0x000000FF
-#define CLIC_INT_INFO_VERSION_M  ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S))
-#define CLIC_INT_INFO_VERSION_V  0xFF
-#define CLIC_INT_INFO_VERSION_S  13
-/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
-/*description: .*/
-#define CLIC_INT_INFO_NUM_INT    0x00001FFF
-#define CLIC_INT_INFO_NUM_INT_M  ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S))
-#define CLIC_INT_INFO_NUM_INT_V  0x1FFF
-#define CLIC_INT_INFO_NUM_INT_S  0
-
-#define CLIC_INT_THRESH_REG          (DR_REG_CLIC_BASE + 0x8)
-/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
-/*description: .*/
-#define CLIC_CPU_INT_THRESH    0x000000FF
-#define CLIC_CPU_INT_THRESH_M  ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
-#define CLIC_CPU_INT_THRESH_V  0xFF
-#define CLIC_CPU_INT_THRESH_S  24
-
-#define CLIC_INT_CTRL_REG(i)          (DR_REG_CLIC_CTRL_BASE + (i) * 4)
-/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
-/*description: .*/
-#define CLIC_INT_CTL    0x000000FF
-#define CLIC_INT_CTL_M  ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S))
-#define CLIC_INT_CTL_V  0xFF
-#define CLIC_INT_CTL_S  24
-/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
-/*description: .*/
-#define CLIC_INT_ATTR_MODE    0x00000003
-#define CLIC_INT_ATTR_MODE_M  ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S))
-#define CLIC_INT_ATTR_MODE_V  0x3
-#define CLIC_INT_ATTR_MODE_S  22
-/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: .*/
-#define CLIC_INT_ATTR_TRIG    0x00000003
-#define CLIC_INT_ATTR_TRIG_M  ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S))
-#define CLIC_INT_ATTR_TRIG_V  0x3
-#define CLIC_INT_ATTR_TRIG_S  17
-/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: .*/
-#define CLIC_INT_ATTR_SHV    (BIT(16))
-#define CLIC_INT_ATTR_SHV_M  (BIT(16))
-#define CLIC_INT_ATTR_SHV_V  0x1
-#define CLIC_INT_ATTR_SHV_S  16
-/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: .*/
-#define CLIC_INT_IE    (BIT(8))
-#define CLIC_INT_IE_M  (BIT(8))
-#define CLIC_INT_IE_V  0x1
-#define CLIC_INT_IE_S  8
-/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: .*/
-#define CLIC_INT_IP    (BIT(0))
-#define CLIC_INT_IP_M  (BIT(0))
-#define CLIC_INT_IP_V  0x1
-#define CLIC_INT_IP_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/clint_reg.h b/components/soc/esp32c5/beta3/include/soc/clint_reg.h
deleted file mode 100644
index ac96f4bb82..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/clint_reg.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*CLINT MINT*/
-#define CLINT_MINT_SIP_REG          (DR_REG_CLINT_M_BASE + 0x0)
-/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_SIP    BIT(0)
-#define CLINT_CPU_MINT_SIP_M  BIT(0)
-#define CLINT_CPU_MINT_SIP_V  1
-#define CLINT_CPU_MINT_SIP_S  0
-
-#define CLINT_MINT_MTIMECMP_L_REG          (DR_REG_CLINT_M_BASE + 0x4000)
-/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIMECMP_L    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_L_M  ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
-#define CLINT_CPU_MINT_MTIMECMP_L_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_L_S  0
-
-#define CLINT_MINT_MTIMECMP_H_REG          (DR_REG_CLINT_M_BASE + 0x4004)
-/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIMECMP_H    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_H_M  ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
-#define CLINT_CPU_MINT_MTIMECMP_H_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIMECMP_H_S  0
-
-#define CLINT_MINT_TIMECTL_REG          (DR_REG_CLINT_M_BASE + 0x4010)
-/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define CLINT_MINT_SAMPLING_MODE    0x00000003
-#define CLINT_MINT_SAMPLING_MODE_M  ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
-#define CLINT_MINT_SAMPLING_MODE_V  0x3
-#define CLINT_MINT_SAMPLING_MODE_S  4
-/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_MINT_COUNTER_OVERFLOW  (BIT(3))
-#define CLINT_MINT_COUNTER_OVERFLOW_M  (BIT(3))
-#define CLINT_MINT_COUNTER_OVERFLOW_V  0x1
-#define CLINT_MINT_COUNTER_OVERFLOW_S  3
-/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define CLINT_MINT_COUNTER_EN  (BIT(0))
-#define CLINT_MINT_COUNTER_EN_M  (BIT(0))
-#define CLINT_MINT_COUNTER_EN_V  0x1
-#define CLINT_MINT_COUNTER_EN_S  0
-
-#define CLINT_MINT_MTIME_L_REG          (DR_REG_CLINT_M_BASE + 0xBFF8)
-/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIME_L    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_L_M  ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
-#define CLINT_CPU_MINT_MTIME_L_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_L_S  0
-
-#define CLINT_MINT_MTIME_H_REG          (DR_REG_CLINT_M_BASE + 0xBFFC)
-/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define CLINT_CPU_MINT_MTIME_H    0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_H_M  ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
-#define CLINT_CPU_MINT_MTIME_H_V  0xFFFFFFFF
-#define CLINT_CPU_MINT_MTIME_H_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h b/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h
deleted file mode 100644
index d65e8583d2..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- ************************* ESP32C5 Root Clock Source ****************************
- * 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
- *
- *    This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
- *
- *    The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
- *
- * 2) External 40/48MHz Crystal Clock: XTAL
- *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
- *
- *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
- *    can be computed in runtime through calibration.
- *
- * 4) Internal 32kHz RC Oscillator: RC32K
- *
- *    The exact frequency of this clock can be computed in runtime through calibration.
- *
- * 5) External 32kHz Crystal Clock (optional): XTAL32K
- *
- *    The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
- *    pins.
- *
- *    XTAL32K_CLK can also be calibrated to get its exact frequency.
- *
- * 6) External Slow Clock (optional): OSC_SLOW
- *
- *    A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
- *    RTC_SLOW_CLK.
- *
- *    OSC_SLOW_CLK can also be calibrated to get its exact frequency.
- */
-
-// TODO: [ESP32C5] IDF-8642 (inherit from C6)
-/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
-#define SOC_CLK_RC_FAST_FREQ_APPROX         17500000                            /*!< Approximate RC_FAST_CLK frequency in Hz */
-#define SOC_CLK_RC_SLOW_FREQ_APPROX         136000                              /*!< Approximate RC_SLOW_CLK frequency in Hz */
-#define SOC_CLK_RC32K_FREQ_APPROX           32768                               /*!< Approximate RC32K_CLK frequency in Hz */
-#define SOC_CLK_XTAL32K_FREQ_APPROX         32768                               /*!< Approximate XTAL32K_CLK frequency in Hz */
-#define SOC_CLK_OSC_SLOW_FREQ_APPROX        32768                               /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
-
-// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
-// {loc}: EXT, INT
-// {type}: XTAL, RC
-// [attr] - optional: [frequency], FAST, SLOW
-/**
- * @brief Root clock
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8642 (inherit from C6)
-    SOC_ROOT_CLK_INT_RC_FAST,          /*!< Internal 17.5MHz RC oscillator */
-    SOC_ROOT_CLK_INT_RC_SLOW,          /*!< Internal 136kHz RC oscillator */
-    SOC_ROOT_CLK_EXT_XTAL,             /*!< External 40MHz crystal */
-    SOC_ROOT_CLK_EXT_XTAL32K,          /*!< External 32kHz crystal */
-    SOC_ROOT_CLK_INT_RC32K,            /*!< Internal 32kHz RC oscillator */
-    SOC_ROOT_CLK_EXT_OSC_SLOW,         /*!< External slow clock signal at pin0 */
-} soc_root_clk_t;
-
-/**
- * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
- * @note Enum values are matched with the register field values on purpose
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8642 (inherit from C6)
-    SOC_CPU_CLK_SRC_XTAL = 0,              /*!< Select XTAL_CLK as CPU_CLK source */
-    SOC_CPU_CLK_SRC_RC_FAST = 1,           /*!< Select RC_FAST_CLK as CPU_CLK source */
-    SOC_CPU_CLK_SRC_PLL_F160M = 2,         /*!< Select PLL_F160M_CLK as CPU_CLK source (PLL_F160M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */
-    SOC_CPU_CLK_SRC_PLL_F240M = 3,         /*!< Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */
-    SOC_CPU_CLK_SRC_INVALID,               /*!< Invalid CPU_CLK source */
-} soc_cpu_clk_src_t;
-
-/**
- * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
- * @note Enum values are matched with the register field values on purpose
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8642 (inherit from C6)
-    // SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0,              /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ !!! can't do calibration on esp32c5, don't use it
-    SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1,                 /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
-    SOC_RTC_SLOW_CLK_SRC_RC32K = 2,                   /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
-    SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3,                /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
-    SOC_RTC_SLOW_CLK_SRC_INVALID,                     /*!< Invalid RTC_SLOW_CLK source */
-} soc_rtc_slow_clk_src_t;
-
-/**
- * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
- * @note Enum values are matched with the register field values on purpose
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8642 (inherit from C6)
-    SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1,      /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
-    SOC_RTC_FAST_CLK_SRC_XTAL = 2,         /*!< Select XTAL_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
-} soc_rtc_fast_clk_src_t;
-
-/**
- * @brief Possible main XTAL frequency options on the target
- * @note Enum values equal to the frequency value in MHz
- * @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
- *       the supported ones.
- */
-typedef enum {
-    SOC_XTAL_FREQ_40M = 40,                /*!< 40MHz XTAL */
-    SOC_XTAL_FREQ_48M = 48,                /*!< 48MHz XTAL */
-} soc_xtal_freq_t;
-
-// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
-// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
-// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
-/**
- * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
- *
- * @note enum starts from 1, to save 0 for special purpose
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8642 (inherit from C6)
-    // For CPU domain
-    SOC_MOD_CLK_CPU = 1,                       /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
-    // For RTC domain
-    SOC_MOD_CLK_RTC_FAST,                      /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
-    SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
-    // For digital domain: peripherals, WIFI, BLE
-    SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
-    SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
-    SOC_MOD_CLK_PLL_F240M,                     /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
-    SOC_MOD_CLK_SPLL,                          /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */
-    SOC_MOD_CLK_XTAL32K,                       /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
-    SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
-    SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
-    // For LP peripherals
-    SOC_MOD_CLK_XTAL_D2,                       /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
-
-    SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
-} soc_module_clk_t;
-
-//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
-
-/**
- * @brief Type of SYSTIMER clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8676 (inherit from C6)
-    SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< SYSTIMER source clock is XTAL */
-    SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
-    SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< SYSTIMER source clock default choice is XTAL */
-} soc_periph_systimer_clk_src_t;
-
-//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of GPTimer
- *
- * The following code can be used to iterate all possible clocks:
- * @code{c}
- * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
- * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
- *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
- *     // Test GPTimer with the clock `clk`
- * }
- * @endcode
- */
-#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M/*, SOC_MOD_CLK_RC_FAST*/, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Type of GPTimer clock source
- */
-typedef enum {
-    GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
-    GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
-    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
-} soc_periph_gptimer_clk_src_t;
-
-/**
- * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
- */
-typedef enum {
-    TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,     /*!< Timer group clock source is PLL_F80M */
-    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,             /*!< Timer group clock source is XTAL */
-    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,      /*!< Timer group clock source default choice is PLL_F80M */
-} soc_periph_tg_clk_src_legacy_t;
-
-//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of RMT
- */
-#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M,/* SOC_MOD_CLK_RC_FAST,*/ SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Type of RMT clock source
- */
-typedef enum {
-    RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
-    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
-    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M as the default choice */
-} soc_periph_rmt_clk_src_t;
-
-/**
- * @brief Type of RMT clock source, reserved for the legacy RMT driver
- */
-typedef enum {
-    RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
-    RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,         /*!< RMT source clock is XTAL */
-    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< RMT source clock default choice is PLL_F80M */
-} soc_periph_rmt_clk_src_legacy_t;
-
-//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of Temperature Sensor
- */
-#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief Type of Temp Sensor clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8727 (inherit from C6)
-    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
-} soc_periph_temperature_sensor_clk_src_t;
-
-///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of UART
- */
-#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief Type of UART clock source, reserved for the legacy UART driver
- */
-typedef enum {
-    UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,          /*!< UART source clock is PLL_F80M */
-    UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST,                /*!< UART source clock is RC_FAST */
-    UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,                  /*!< UART source clock is XTAL */
-    UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock default choice is PLL_F80M */
-} soc_periph_uart_clk_src_legacy_t;
-
-/**
- * @brief Array initializer for all supported clock sources of LP_UART
- */
-#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
-
-/**
- * @brief Type of LP_UART clock source
- */
-typedef enum {
-    LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST,         /*!< LP_UART source clock is RC_FAST */
-    LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock is XTAL_D2 */
-    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock default choice is RC_FAST */
-} soc_periph_lp_uart_clk_src_t;
-
-//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of MCPWM Timer
- */
-#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Type of MCPWM timer clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8709 (inherit from C6)
-    MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
-    MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
-} soc_periph_mcpwm_timer_clk_src_t;
-
-/**
- * @brief Array initializer for all supported clock sources of MCPWM Capture Timer
- */
-#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Type of MCPWM capture clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8709 (inherit from C6)
-    MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
-    MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
-} soc_periph_mcpwm_capture_clk_src_t;
-
-/**
- * @brief Array initializer for all supported clock sources of MCPWM Carrier
- */
-#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Type of MCPWM carrier clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8709 (inherit from C6)
-    MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
-    MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
-} soc_periph_mcpwm_carrier_clk_src_t;
-
-///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of I2S
- */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
-
-/**
- * @brief I2S clock source enum
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8713 (inherit from C6)
-    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
-    I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
-    I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
-    I2S_CLK_SRC_EXTERNAL = -1,                                  /*!< Select external clock as source clock */
-} soc_periph_i2s_clk_src_t;
-
-/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of I2C
- */
-#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief Type of I2C clock source.
- */
-typedef enum {
-    I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
-    I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,                  /*!< Select RC_FAST as the source clock */
-    I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,                     /*!< Select XTAL as the default source clock */
-} soc_periph_i2c_clk_src_t;
-
-///////////////////////////////////////////////LP_I2C///////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of LP_I2C
- */
-#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
-
-/**
- * @brief Type of LP_I2C clock source.
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8695 (inherit from C6)
-    LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST,                 /*!< LP_I2C source clock is RTC_FAST */
-    LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2,                  /*!< LP_I2C source clock is XTAL_D2 */
-    LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST,                 /*!< LP_I2C source clock default choice is RTC_FAST */
-} soc_periph_lp_i2c_clk_src_t;
-
-/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of SPI
- */
-#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief Type of SPI clock source.
- */
-typedef enum {
-    SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,            /*!< Select XTAL as SPI source clock */
-    SPI_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M,  /*!< Select PLL_160M as SPI source clock */
-    SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,      /*!< Select RC_FAST as SPI source clock */
-    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,    /*!< Select PLL_160M as SPI source clock */
-} soc_periph_spi_clk_src_t;
-
-//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of SDM
- */
-#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Sigma Delta Modulator clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8687 (inherit from C6)
-    SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
-    SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
-    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
-} soc_periph_sdm_clk_src_t;
-
-//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of Glitch Filter
- */
-#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
-
-/**
- * @brief Glitch filter clock source
- */
-
-typedef enum {  // TODO: [ESP32C5] IDF-8718 (inherit from C6)
-    GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
-    GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
-    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
-} soc_periph_glitch_filter_clk_src_t;
-
-//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of TWAI
- */
-#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL}
-
-/**
- * @brief TWAI clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6)
-    TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the source clock */
-    TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
-} soc_periph_twai_clk_src_t;
-
-//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of ADC digital controller
- */
-#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief ADC digital controller clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6)
-    ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-    ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,   /*!< Select PLL_F80M as the source clock */
-    ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
-    ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M as the default clock choice */
-} soc_periph_adc_digi_clk_src_t;
-
-//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of MWDT
- */
-#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief MWDT clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8650 (inherit from C6)
-    MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-    MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,   /*!< Select PLL fixed 80 MHz as the source clock */
-    MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RTC fast as the source clock */
-    MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,        /*!< Select PLL fixed 80 MHz as the default clock choice */
-} soc_periph_mwdt_clk_src_t;
-
-//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of LEDC
- */
-#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
-
-/**
- * @brief Type of LEDC clock source, reserved for the legacy LEDC driver
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8684 (inherit from C6)
-    LEDC_AUTO_CLK = 0,                              /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
-    LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M,    /*!< Select PLL_F80M clock as the source clock */
-    LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
-    LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-
-    LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
-} soc_periph_ledc_clk_src_legacy_t;
-
-//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
-
-/**
- * @brief Array initializer for all supported clock sources of PARLIO
- */
-#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
-
-/**
- * @brief PARLIO clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6)
-    PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-    PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
-    PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M,   /*!< Select PLL_F240M as the default clock choice */
-} soc_periph_parlio_clk_src_t;
-
-//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
-/**
- * @brief Array initializer for all supported clock sources of MSPI digital controller
- */
-#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
-/**
- * @brief MSPI digital controller clock source
- */
-typedef enum {  // TODO: [ESP32C5] IDF-8649
-    MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
-    MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
-    MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL,           /*!< Select SPLL as the source clock */
-    MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as ROM default clock source */
-} soc_periph_mspi_clk_src_t;
-
-//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
-typedef enum {  // TODO: [ESP32C5] IDF-8642 (inherit from C6)
-    CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
-    CLKOUT_SIG_XTAL     = 5,    /*!< Main crystal oscillator clock */
-    CLKOUT_SIG_PLL_F80M = 13,   /*!< From PLL, usually be 80MHz */
-    CLKOUT_SIG_CPU      = 16,   /*!< CPU clock */
-    CLKOUT_SIG_AHB      = 17,   /*!< AHB clock */
-    CLKOUT_SIG_APB      = 18,   /*!< APB clock */
-    CLKOUT_SIG_XTAL32K  = 21,   /*!< External 32kHz crystal clock */
-    CLKOUT_SIG_EXT32K   = 22,   /*!< External slow clock input through XTAL_32K_P */
-    CLKOUT_SIG_RC_FAST  = 23,   /*!< RC fast clock, about 17.5MHz */
-    CLKOUT_SIG_RC_32K   = 24,   /*!< Internal slow RC oscillator */
-    CLKOUT_SIG_RC_SLOW  = 25,   /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
-    CLKOUT_SIG_INVALID  = 0xFF,
-} soc_clkout_sig_id_t;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/dport_access.h b/components/soc/esp32c5/beta3/include/soc/dport_access.h
deleted file mode 100644
index d5d1550b60..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/dport_access.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include "soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
-
-#define DPORT_INTERRUPT_DISABLE()
-#define DPORT_INTERRUPT_RESTORE()
-
-/**
- * @brief Read a sequence of DPORT registers to the buffer.
- *
- * @param[out] buff_out  Contains the read data.
- * @param[in]  address   Initial address for reading registers.
- * @param[in]  num_words The number of words.
- */
-void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
-
-// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
-#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
-#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
-
-// Write value to DPORT register (does not require protecting)
-#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE((_r), (_v))
-
-#define DPORT_REG_READ(_r)    _DPORT_REG_READ(_r)
-#define DPORT_SEQUENCE_REG_READ(_r)    _DPORT_REG_READ(_r)
-
-//get bit or get bits from register
-#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
-
-//set bit or set bits to register
-#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
-
-//clear bit or clear bits of register
-#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
-
-//set bits of register controlled by mask
-#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
-
-//get field from register, uses field _S & _V to determine mask
-#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
-
-//set field to register, used when _f is not left shifted by _f##_S
-#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
-
-//get field value from a variable, used when _f is not left shifted by _f##_S
-#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
-
-//get field value from a variable, used when _f is left shifted by _f##_S
-#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
-
-//set field value to a variable, used when _f is not left shifted by _f##_S
-#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
-
-//set field value to a variable, used when _f is left shifted by _f##_S
-#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
-
-//generate a value from a field value, used when _f is not left shifted by _f##_S
-#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
-
-//generate a value from a field value, used when _f is left shifted by _f##_S
-#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
-
-//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
-#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
-#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
-#define _DPORT_REG_SET_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
-#define _DPORT_REG_CLR_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
-
-#define DPORT_READ_PERI_REG(addr)       _DPORT_READ_PERI_REG(addr)
-
-//write value to register
-#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
-
-//clear bits of register controlled by mask
-#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
-
-//set bits of register controlled by mask
-#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
-
-//get bits of register controlled by mask
-#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
-
-//get bits of register controlled by highest bit and lowest bit
-#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
-
-//set bits of register controlled by mask and shift
-#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
-
-//get field of register
-#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
-//}}
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ds_reg.h b/components/soc/esp32c5/beta3/include/soc/ds_reg.h
deleted file mode 100644
index d164a12930..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ds_reg.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** DS_Y_MEM register
- *  memory that stores Y
- */
-#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
-#define DS_Y_MEM_SIZE_BYTES 512
-
-/** DS_M_MEM register
- *  memory that stores M
- */
-#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
-#define DS_M_MEM_SIZE_BYTES 512
-
-/** DS_RB_MEM register
- *  memory that stores Rb
- */
-#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
-#define DS_RB_MEM_SIZE_BYTES 512
-
-/** DS_BOX_MEM register
- *  memory that stores BOX
- */
-#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
-#define DS_BOX_MEM_SIZE_BYTES 48
-
-/** DS_IV_MEM register
- *  memory that stores IV
- */
-#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
-#define DS_IV_MEM_SIZE_BYTES 16
-
-/** DS_X_MEM register
- *  memory that stores X
- */
-#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
-#define DS_X_MEM_SIZE_BYTES 512
-
-/** DS_Z_MEM register
- *  memory that stores Z
- */
-#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
-#define DS_Z_MEM_SIZE_BYTES 512
-
-/** DS_SET_START_REG register
- *  DS start control register
- */
-#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
-/** DS_SET_START : WT; bitpos: [0]; default: 0;
- *  set this bit to start DS operation.
- */
-#define DS_SET_START    (BIT(0))
-#define DS_SET_START_M  (DS_SET_START_V << DS_SET_START_S)
-#define DS_SET_START_V  0x00000001U
-#define DS_SET_START_S  0
-
-/** DS_SET_CONTINUE_REG register
- *  DS continue control register
- */
-#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
-/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
- *  set this bit to continue DS operation.
- */
-#define DS_SET_CONTINUE    (BIT(0))
-#define DS_SET_CONTINUE_M  (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
-#define DS_SET_CONTINUE_V  0x00000001U
-#define DS_SET_CONTINUE_S  0
-
-/** DS_SET_FINISH_REG register
- *  DS finish control register
- */
-#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
-/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
- *  Set this bit to finish DS process.
- */
-#define DS_SET_FINISH    (BIT(0))
-#define DS_SET_FINISH_M  (DS_SET_FINISH_V << DS_SET_FINISH_S)
-#define DS_SET_FINISH_V  0x00000001U
-#define DS_SET_FINISH_S  0
-
-/** DS_QUERY_BUSY_REG register
- *  DS query busy register
- */
-#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
-/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
- *  digital signature state. 1'b0: idle, 1'b1: busy
- */
-#define DS_QUERY_BUSY    (BIT(0))
-#define DS_QUERY_BUSY_M  (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
-#define DS_QUERY_BUSY_V  0x00000001U
-#define DS_QUERY_BUSY_S  0
-
-/** DS_QUERY_KEY_WRONG_REG register
- *  DS query key-wrong counter register
- */
-#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
-/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
- *  digital signature key wrong counter
- */
-#define DS_QUERY_KEY_WRONG    0x0000000FU
-#define DS_QUERY_KEY_WRONG_M  (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
-#define DS_QUERY_KEY_WRONG_V  0x0000000FU
-#define DS_QUERY_KEY_WRONG_S  0
-
-/** DS_QUERY_CHECK_REG register
- *  DS query check result register
- */
-#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
-/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
- *  MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
- */
-#define DS_MD_ERROR    (BIT(0))
-#define DS_MD_ERROR_M  (DS_MD_ERROR_V << DS_MD_ERROR_S)
-#define DS_MD_ERROR_V  0x00000001U
-#define DS_MD_ERROR_S  0
-/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
- *  padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
- */
-#define DS_PADDING_BAD    (BIT(1))
-#define DS_PADDING_BAD_M  (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
-#define DS_PADDING_BAD_V  0x00000001U
-#define DS_PADDING_BAD_S  1
-
-/** DS_DATE_REG register
- *  DS version control register
- */
-#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
-/** DS_DATE : R/W; bitpos: [29:0]; default: 538969624;
- *  ds version information
- */
-#define DS_DATE    0x3FFFFFFFU
-#define DS_DATE_M  (DS_DATE_V << DS_DATE_S)
-#define DS_DATE_V  0x3FFFFFFFU
-#define DS_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ds_struct.h b/components/soc/esp32c5/beta3/include/soc/ds_struct.h
deleted file mode 100644
index 74682d8e17..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ds_struct.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: memory type */
-
-/** Group: Control/Status registers */
-/** Type of set_start register
- *  DS start control register
- */
-typedef union {
-    struct {
-        /** set_start : WT; bitpos: [0]; default: 0;
-         *  set this bit to start DS operation.
-         */
-        uint32_t set_start:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ds_set_start_reg_t;
-
-/** Type of set_continue register
- *  DS continue control register
- */
-typedef union {
-    struct {
-        /** set_continue : WT; bitpos: [0]; default: 0;
-         *  set this bit to continue DS operation.
-         */
-        uint32_t set_continue:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ds_set_continue_reg_t;
-
-/** Type of set_finish register
- *  DS finish control register
- */
-typedef union {
-    struct {
-        /** set_finish : WT; bitpos: [0]; default: 0;
-         *  Set this bit to finish DS process.
-         */
-        uint32_t set_finish:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ds_set_finish_reg_t;
-
-/** Type of query_busy register
- *  DS query busy register
- */
-typedef union {
-    struct {
-        /** query_busy : RO; bitpos: [0]; default: 0;
-         *  digital signature state. 1'b0: idle, 1'b1: busy
-         */
-        uint32_t query_busy:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ds_query_busy_reg_t;
-
-/** Type of query_key_wrong register
- *  DS query key-wrong counter register
- */
-typedef union {
-    struct {
-        /** query_key_wrong : RO; bitpos: [3:0]; default: 0;
-         *  digital signature key wrong counter
-         */
-        uint32_t query_key_wrong:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ds_query_key_wrong_reg_t;
-
-/** Type of query_check register
- *  DS query check result register
- */
-typedef union {
-    struct {
-        /** md_error : RO; bitpos: [0]; default: 0;
-         *  MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
-         */
-        uint32_t md_error:1;
-        /** padding_bad : RO; bitpos: [1]; default: 0;
-         *  padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
-         */
-        uint32_t padding_bad:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ds_query_check_reg_t;
-
-
-/** Group: version control register */
-/** Type of date register
- *  DS version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [29:0]; default: 538969624;
-         *  ds version information
-         */
-        uint32_t date:30;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} ds_date_reg_t;
-
-
-typedef struct ds_dev_t {
-    volatile uint32_t y[128];
-    volatile uint32_t m[128];
-    volatile uint32_t rb[128];
-    volatile uint32_t box[12];
-    volatile uint32_t iv[4];
-    uint32_t reserved_640[112];
-    volatile uint32_t x[128];
-    volatile uint32_t z[128];
-    uint32_t reserved_c00[128];
-    volatile ds_set_start_reg_t set_start;
-    volatile ds_set_continue_reg_t set_continue;
-    volatile ds_set_finish_reg_t set_finish;
-    volatile ds_query_busy_reg_t query_busy;
-    volatile ds_query_key_wrong_reg_t query_key_wrong;
-    volatile ds_query_check_reg_t query_check;
-    uint32_t reserved_e18[2];
-    volatile ds_date_reg_t date;
-} ds_dev_t;
-
-extern ds_dev_t DS;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ecc_mult_reg.h b/components/soc/esp32c5/beta3/include/soc/ecc_mult_reg.h
deleted file mode 100644
index 0010c61b40..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ecc_mult_reg.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECC_MULT_INT_RAW_REG register
- *  ECC interrupt raw register, valid in level.
- */
-#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
-/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
-#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_RAW_S  0
-
-/** ECC_MULT_INT_ST_REG register
- *  ECC interrupt status register.
- */
-#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
-/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
-#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ST_S  0
-
-/** ECC_MULT_INT_ENA_REG register
- *  ECC interrupt enable register.
- */
-#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
-/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
-#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ENA_S  0
-
-/** ECC_MULT_INT_CLR_REG register
- *  ECC interrupt clear register.
- */
-#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
-/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
-#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_CLR_S  0
-
-/** ECC_MULT_CONF_REG register
- *  ECC configure register
- */
-#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
-/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
- *  the caculatrion is done.
- */
-#define ECC_MULT_START    (BIT(0))
-#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
-#define ECC_MULT_START_V  0x00000001U
-#define ECC_MULT_START_S  0
-/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
- *  Write 1 to reset ECC Accelerator.
- */
-#define ECC_MULT_RESET    (BIT(1))
-#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
-#define ECC_MULT_RESET_V  0x00000001U
-#define ECC_MULT_RESET_S  1
-/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
- *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
- */
-#define ECC_MULT_KEY_LENGTH    (BIT(2))
-#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
-#define ECC_MULT_KEY_LENGTH_V  0x00000001U
-#define ECC_MULT_KEY_LENGTH_S  2
-/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
- *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
- *  1: p(mod base of curve)
- */
-#define ECC_MULT_MOD_BASE    (BIT(3))
-#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
-#define ECC_MULT_MOD_BASE_V  0x00000001U
-#define ECC_MULT_MOD_BASE_S  3
-/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
- *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
- *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
- *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
- *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
- */
-#define ECC_MULT_WORK_MODE    0x0000000FU
-#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
-#define ECC_MULT_WORK_MODE_V  0x0000000FU
-#define ECC_MULT_WORK_MODE_S  4
-/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define ECC_MULT_SECURITY_MODE    (BIT(8))
-#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
-#define ECC_MULT_SECURITY_MODE_V  0x00000001U
-#define ECC_MULT_SECURITY_MODE_S  8
-/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
- *  The verification result bit of ECC Accelerator, only valid when calculation is done.
- */
-#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
-#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
-#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
-#define ECC_MULT_VERIFICATION_RESULT_S  29
-/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECC_MULT_CLK_EN    (BIT(30))
-#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
-#define ECC_MULT_CLK_EN_V  0x00000001U
-#define ECC_MULT_CLK_EN_S  30
-/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  ECC memory clock gate force on register
- */
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
-
-/** ECC_MULT_DATE_REG register
- *  Version control register
- */
-#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
-/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704;
- *  ECC mult version control register
- */
-#define ECC_MULT_DATE    0x0FFFFFFFU
-#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
-#define ECC_MULT_DATE_V  0x0FFFFFFFU
-#define ECC_MULT_DATE_S  0
-
-/** ECC_MULT_K_MEM register
- *  The memory that stores k.
- */
-#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
-#define ECC_MULT_K_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PX_MEM register
- *  The memory that stores Px.
- */
-#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
-#define ECC_MULT_PX_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PY_MEM register
- *  The memory that stores Py.
- */
-#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
-#define ECC_MULT_PY_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QX_MEM register
- *  The memory that stores Qx.
- */
-#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
-#define ECC_MULT_QX_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QY_MEM register
- *  The memory that stores Qy.
- */
-#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
-#define ECC_MULT_QY_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QZ_MEM register
- *  The memory that stores Qz.
- */
-#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0)
-#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/beta3/include/soc/ecc_mult_struct.h
deleted file mode 100644
index da6e103063..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ecc_mult_struct.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory data */
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECC interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_raw:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECC interrupt status register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_st:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECC interrupt enable register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECC interrupt clear register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of conf register
- *  ECC configure register
- */
-typedef union {
-    struct {
-        /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
-         *  the caculatrion is done.
-         */
-        uint32_t start:1;
-        /** reset : WT; bitpos: [1]; default: 0;
-         *  Write 1 to reset ECC Accelerator.
-         */
-        uint32_t reset:1;
-        /** key_length : R/W; bitpos: [2]; default: 0;
-         *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t key_length:1;
-        /** mod_base : R/W; bitpos: [3]; default: 0;
-         *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
-         *  1: p(mod base of curve)
-         */
-        uint32_t mod_base:1;
-        /** work_mode : R/W; bitpos: [7:4]; default: 0;
-         *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
-         *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
-         *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
-         *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
-         */
-        uint32_t work_mode:4;
-        /** security_mode : R/W; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t security_mode:1;
-        uint32_t reserved_9:20;
-        /** verification_result : RO/SS; bitpos: [29]; default: 0;
-         *  The verification result bit of ECC Accelerator, only valid when calculation is done.
-         */
-        uint32_t verification_result:1;
-        /** clk_en : R/W; bitpos: [30]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_en:1;
-        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
-         *  ECC memory clock gate force on register
-         */
-        uint32_t mem_clock_gate_force_on:1;
-    };
-    uint32_t val;
-} ecc_mult_conf_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720704;
-         *  ECC mult version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecc_mult_date_reg_t;
-
-
-typedef struct ecc_mult_dev_t {
-    uint32_t reserved_000[3];
-    volatile ecc_mult_int_raw_reg_t int_raw;
-    volatile ecc_mult_int_st_reg_t int_st;
-    volatile ecc_mult_int_ena_reg_t int_ena;
-    volatile ecc_mult_int_clr_reg_t int_clr;
-    volatile ecc_mult_conf_reg_t conf;
-    uint32_t reserved_020[55];
-    volatile ecc_mult_date_reg_t date;
-    volatile uint32_t k[8];
-    volatile uint32_t px[8];
-    volatile uint32_t py[8];
-} ecc_mult_dev_t;
-
-extern ecc_mult_dev_t ECC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ecdsa_reg.h b/components/soc/esp32c5/beta3/include/soc/ecdsa_reg.h
deleted file mode 100644
index 6e09925e09..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ecdsa_reg.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECDSA_CONF_REG register
- *  ECDSA configure register
- */
-#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
-/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
- *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
- */
-#define ECDSA_WORK_MODE    0x00000003U
-#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
-#define ECDSA_WORK_MODE_V  0x00000003U
-#define ECDSA_WORK_MODE_S  0
-/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
- *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
- */
-#define ECDSA_ECC_CURVE    (BIT(2))
-#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
-#define ECDSA_ECC_CURVE_V  0x00000001U
-#define ECDSA_ECC_CURVE_S  2
-/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
- *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
- *  written by software.
- */
-#define ECDSA_SOFTWARE_SET_K    (BIT(3))
-#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
-#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_K_S  3
-/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
- *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
- *  software.
- */
-#define ECDSA_SOFTWARE_SET_Z    (BIT(4))
-#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
-#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_Z_S  4
-/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
- *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
- *  deterministic derivation algorithm.
- */
-#define ECDSA_DETERMINISTIC_K    (BIT(5))
-#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
-#define ECDSA_DETERMINISTIC_K_V  0x00000001U
-#define ECDSA_DETERMINISTIC_K_S  5
-/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
- *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
- */
-#define ECDSA_DETERMINISTIC_LOOP    0x0000FFFFU
-#define ECDSA_DETERMINISTIC_LOOP_M  (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
-#define ECDSA_DETERMINISTIC_LOOP_V  0x0000FFFFU
-#define ECDSA_DETERMINISTIC_LOOP_S  6
-
-/** ECDSA_CLK_REG register
- *  ECDSA clock gate register
- */
-#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
-/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
-#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
-#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
-#define ECDSA_CLK_GATE_FORCE_ON_S  0
-
-/** ECDSA_INT_RAW_REG register
- *  ECDSA interrupt raw register, valid in level.
- */
-#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
-/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_RAW    (BIT(0))
-#define ECDSA_CALC_DONE_INT_RAW_M  (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
-#define ECDSA_CALC_DONE_INT_RAW_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_RAW_S  0
-/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
-#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_RAW_S  1
-
-/** ECDSA_INT_ST_REG register
- *  ECDSA interrupt status register.
- */
-#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
-/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_ST    (BIT(0))
-#define ECDSA_CALC_DONE_INT_ST_M  (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
-#define ECDSA_CALC_DONE_INT_ST_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_ST_S  0
-/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ST    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
-#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ST_S  1
-
-/** ECDSA_INT_ENA_REG register
- *  ECDSA interrupt enable register.
- */
-#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
-/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_ENA    (BIT(0))
-#define ECDSA_CALC_DONE_INT_ENA_M  (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
-#define ECDSA_CALC_DONE_INT_ENA_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_ENA_S  0
-/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
-#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ENA_S  1
-
-/** ECDSA_INT_CLR_REG register
- *  ECDSA interrupt clear register.
- */
-#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
-/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_CLR    (BIT(0))
-#define ECDSA_CALC_DONE_INT_CLR_M  (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
-#define ECDSA_CALC_DONE_INT_CLR_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_CLR_S  0
-/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
-#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_CLR_S  1
-
-/** ECDSA_START_REG register
- *  ECDSA start register
- */
-#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
-/** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
- *  after configuration.
- */
-#define ECDSA_START    (BIT(0))
-#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
-#define ECDSA_START_V  0x00000001U
-#define ECDSA_START_S  0
-/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
- *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_LOAD_DONE    (BIT(1))
-#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
-#define ECDSA_LOAD_DONE_V  0x00000001U
-#define ECDSA_LOAD_DONE_S  1
-/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
- *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_GET_DONE    (BIT(2))
-#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
-#define ECDSA_GET_DONE_V  0x00000001U
-#define ECDSA_GET_DONE_S  2
-
-/** ECDSA_STATE_REG register
- *  ECDSA status register
- */
-#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
-/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
- *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
- *  state.
- */
-#define ECDSA_BUSY    0x00000003U
-#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
-#define ECDSA_BUSY_V  0x00000003U
-#define ECDSA_BUSY_S  0
-
-/** ECDSA_RESULT_REG register
- *  ECDSA result register
- */
-#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
-/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
- *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
- *  done.
- */
-#define ECDSA_OPERATION_RESULT    (BIT(0))
-#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
-#define ECDSA_OPERATION_RESULT_V  0x00000001U
-#define ECDSA_OPERATION_RESULT_S  0
-/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
- *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
- *  curve order, then actually taken k = k mod n.
- */
-#define ECDSA_K_VALUE_WARNING    (BIT(1))
-#define ECDSA_K_VALUE_WARNING_M  (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
-#define ECDSA_K_VALUE_WARNING_V  0x00000001U
-#define ECDSA_K_VALUE_WARNING_S  1
-
-/** ECDSA_DATE_REG register
- *  Version control register
- */
-#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
-/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
- *  ECDSA version control register
- */
-#define ECDSA_DATE    0x0FFFFFFFU
-#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
-#define ECDSA_DATE_V  0x0FFFFFFFU
-#define ECDSA_DATE_S  0
-
-/** ECDSA_SHA_MODE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
-/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
- *  Others: invalid.
- */
-#define ECDSA_SHA_MODE    0x00000007U
-#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
-#define ECDSA_SHA_MODE_V  0x00000007U
-#define ECDSA_SHA_MODE_S  0
-
-/** ECDSA_SHA_START_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
-/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_START    (BIT(0))
-#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
-#define ECDSA_SHA_START_V  0x00000001U
-#define ECDSA_SHA_START_S  0
-
-/** ECDSA_SHA_CONTINUE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
-/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_CONTINUE    (BIT(0))
-#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
-#define ECDSA_SHA_CONTINUE_V  0x00000001U
-#define ECDSA_SHA_CONTINUE_S  0
-
-/** ECDSA_SHA_BUSY_REG register
- *  ECDSA status register
- */
-#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
-/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
- *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
- *  calculation. 0: SHA is idle.
- */
-#define ECDSA_SHA_BUSY    (BIT(0))
-#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
-#define ECDSA_SHA_BUSY_V  0x00000001U
-#define ECDSA_SHA_BUSY_S  0
-
-/** ECDSA_MESSAGE_MEM register
- *  The memory that stores message.
- */
-#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
-#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
-
-/** ECDSA_R_MEM register
- *  The memory that stores r.
- */
-#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
-#define ECDSA_R_MEM_SIZE_BYTES 32
-
-/** ECDSA_S_MEM register
- *  The memory that stores s.
- */
-#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
-#define ECDSA_S_MEM_SIZE_BYTES 32
-
-/** ECDSA_Z_MEM register
- *  The memory that stores software written z.
- */
-#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
-#define ECDSA_Z_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAX_MEM register
- *  The memory that stores x coordinates of QA or software written k.
- */
-#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
-#define ECDSA_QAX_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAY_MEM register
- *  The memory that stores y coordinates of QA.
- */
-#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
-#define ECDSA_QAY_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ecdsa_struct.h b/components/soc/esp32c5/beta3/include/soc/ecdsa_struct.h
deleted file mode 100644
index c319499a4d..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ecdsa_struct.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Data Memory */
-
-/** Group: Configuration registers */
-/** Type of conf register
- *  ECDSA configure register
- */
-typedef union {
-    struct {
-        /** work_mode : R/W; bitpos: [1:0]; default: 0;
-         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
-         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
-         */
-        uint32_t work_mode:2;
-        /** ecc_curve : R/W; bitpos: [2]; default: 0;
-         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t ecc_curve:1;
-        /** software_set_k : R/W; bitpos: [3]; default: 0;
-         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
-         *  written by software.
-         */
-        uint32_t software_set_k:1;
-        /** software_set_z : R/W; bitpos: [4]; default: 0;
-         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
-         *  software.
-         */
-        uint32_t software_set_z:1;
-        /** deterministic_k : R/W; bitpos: [5]; default: 0;
-         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
-         *  deterministic derivation algorithm.
-         */
-        uint32_t deterministic_k:1;
-        /** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
-         *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
-         */
-        uint32_t deterministic_loop:16;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} ecdsa_conf_reg_t;
-
-/** Type of start register
- *  ECDSA start register
- */
-typedef union {
-    struct {
-        /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
-         *  after configuration.
-         */
-        uint32_t start:1;
-        /** load_done : WT; bitpos: [1]; default: 0;
-         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t load_done:1;
-        /** get_done : WT; bitpos: [2]; default: 0;
-         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t get_done:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_start_reg_t;
-
-
-/** Group: Clock and reset registers */
-/** Type of clk register
- *  ECDSA clock gate register
- */
-typedef union {
-    struct {
-        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_gate_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_clk_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECDSA interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_raw:1;
-        /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECDSA interrupt status register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_st:1;
-        /** sha_release_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECDSA interrupt enable register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_ena:1;
-        /** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECDSA interrupt clear register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_clr:1;
-        /** sha_release_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_clr_reg_t;
-
-
-/** Group: Status registers */
-/** Type of state register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** busy : RO; bitpos: [1:0]; default: 0;
-         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
-         *  state.
-         */
-        uint32_t busy:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_state_reg_t;
-
-
-/** Group: Result registers */
-/** Type of result register
- *  ECDSA result register
- */
-typedef union {
-    struct {
-        /** operation_result : RO/SS; bitpos: [0]; default: 0;
-         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
-         *  done.
-         */
-        uint32_t operation_result:1;
-        /** k_value_warning : RO/SS; bitpos: [1]; default: 0;
-         *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
-         *  curve order, then actually taken k = k mod n.
-         */
-        uint32_t k_value_warning:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_result_reg_t;
-
-
-/** Group: SHA register */
-/** Type of sha_mode register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
-         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
-         *  Others: invalid.
-         */
-        uint32_t sha_mode:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_sha_mode_reg_t;
-
-/** Type of sha_start register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_start:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_start_reg_t;
-
-/** Type of sha_continue register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_continue:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_continue_reg_t;
-
-/** Type of sha_busy register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** sha_busy : RO; bitpos: [0]; default: 0;
-         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
-         *  calculation. 0: SHA is idle.
-         */
-        uint32_t sha_busy:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_busy_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36716656;
-         *  ECDSA version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecdsa_date_reg_t;
-
-
-typedef struct ecdsa_dev_t {
-    uint32_t reserved_000;
-    volatile ecdsa_conf_reg_t conf;
-    volatile ecdsa_clk_reg_t clk;
-    volatile ecdsa_int_raw_reg_t int_raw;
-    volatile ecdsa_int_st_reg_t int_st;
-    volatile ecdsa_int_ena_reg_t int_ena;
-    volatile ecdsa_int_clr_reg_t int_clr;
-    volatile ecdsa_start_reg_t start;
-    volatile ecdsa_state_reg_t state;
-    volatile ecdsa_result_reg_t result;
-    uint32_t reserved_028[53];
-    volatile ecdsa_date_reg_t date;
-    uint32_t reserved_100[64];
-    volatile ecdsa_sha_mode_reg_t sha_mode;
-    uint32_t reserved_204[3];
-    volatile ecdsa_sha_start_reg_t sha_start;
-    volatile ecdsa_sha_continue_reg_t sha_continue;
-    volatile ecdsa_sha_busy_reg_t sha_busy;
-    uint32_t reserved_21c[25];
-    volatile uint32_t message[8];
-    uint32_t reserved_2a0[472];
-    volatile uint32_t r[8];
-    volatile uint32_t s[8];
-    volatile uint32_t z[8];
-    volatile uint32_t qax[8];
-    volatile uint32_t qay[8];
-} ecdsa_dev_t;
-
-extern ecdsa_dev_t ECDSA;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_reg.h b/components/soc/esp32c5/beta3/include/soc/efuse_reg.h
deleted file mode 100644
index c1454701a2..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,2556 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS0_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled. 1: Disabled. 0: Enabled.
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [7]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_39    (BIT(7))
-#define EFUSE_RD_RESERVE_0_39_M  (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S)
-#define EFUSE_RD_RESERVE_0_39_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_39_S  7
-/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
- *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_ICACHE    (BIT(8))
-#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
-#define EFUSE_DIS_ICACHE_V  0x00000001U
-#define EFUSE_DIS_ICACHE_S  8
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_RD_RESERVE_0_42 : RW; bitpos: [10]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_42    (BIT(10))
-#define EFUSE_RD_RESERVE_0_42_M  (EFUSE_RD_RESERVE_0_42_V << EFUSE_RD_RESERVE_0_42_S)
-#define EFUSE_RD_RESERVE_0_42_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_42_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
- *  Represents whether SPI0 controller during boot_mode_download is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
- *  enabled.
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled.
- *  0: enabled.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode). 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFH    0x00000003U
-#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
-#define EFUSE_USB_DREFH_V  0x00000003U
-#define EFUSE_USB_DREFH_S  21
-/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFL    0x00000003U
-#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
-#define EFUSE_USB_DREFL_V  0x00000003U
-#define EFUSE_USB_DREFL_S  23
-/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
- *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not
- *  exchanged.
- */
-#define EFUSE_USB_EXCHG_PINS    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
-#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_S  25
-/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
- *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
- *  functioned.
- */
-#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
-#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_S  26
-/** EFUSE_RD_RESERVE_0_59 : RW; bitpos: [31:27]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_59    0x0000001FU
-#define EFUSE_RD_RESERVE_0_59_M  (EFUSE_RD_RESERVE_0_59_V << EFUSE_RD_RESERVE_0_59_S)
-#define EFUSE_RD_RESERVE_0_59_V  0x0000001FU
-#define EFUSE_RD_RESERVE_0_59_S  27
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [3:0]; default: 0;
- *  Represents whether the deploy mode of key manager is disable or not. . 1: disabled
- *  . 0: enabled..
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0;
- *  Set the bits to control key manager random number switch cycle. 0: control by
- *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_S  4
-/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0;
- *  Set each bit to control whether corresponding key can only be deployed once. 1 is
- *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  6
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0;
- *  Set each bit to control whether corresponding key must come from key manager. 1 is
- *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  10
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0;
- *  Set this bit to disable software written init key, and force use efuse_init_key.
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(14))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  14
-/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_79    (BIT(15))
-#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
-#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_79_S  15
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original
- *  threshold configuration value of STG0 *2 .1: Original threshold configuration
- *  value of STG0 *4 .2: Original threshold configuration value of STG0 *8 .3:
- *  Original threshold configuration value of STG0 *16 .
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
- *  1: enabled. Even number of 1: disabled.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Represents the purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Represents the purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
- */
-#define EFUSE_SEC_DPA_LEVEL    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
-#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_S  16
-/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [19:18]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_114    0x00000003U
-#define EFUSE_RD_RESERVE_0_114_M  (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S)
-#define EFUSE_RD_RESERVE_0_114_V  0x00000003U
-#define EFUSE_RD_RESERVE_0_114_S  18
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [26:22]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_118    0x0000001FU
-#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
-#define EFUSE_RD_RESERVE_0_118_V  0x0000001FU
-#define EFUSE_RD_RESERVE_0_118_S  22
-/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0;
- *  Set this bitto configure flash encryption use xts-128 key. else use xts-256 key.
- */
-#define EFUSE_KM_XTS_KEY_LENGTH_256    (BIT(27))
-#define EFUSE_KM_XTS_KEY_LENGTH_256_M  (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S)
-#define EFUSE_KM_XTS_KEY_LENGTH_256_V  0x00000001U
-#define EFUSE_KM_XTS_KEY_LENGTH_256_S  27
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
- *  is 2 times the programmed value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disabled or enabled. 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
- *  Represetns whether to lock the efuse xts key. 1. Lock. 0: Unlock.
- */
-#define EFUSE_LOCK_KM_KEY    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
-#define EFUSE_LOCK_KM_KEY_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled..
- *  1: Disable. 0: Enable.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Represents whether security download is enabled or disabled. 1: enabled. 0:
- *  disabled.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Represents the type of UART printing. 00: force enable printing. 01: enable
- *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
- *  at high level. 11: force disable printing.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot..
- *  1: forced. 0:not forced.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  8
-/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
- *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
-/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
- *  enabled. 0:disabled.
- */
-#define EFUSE_HYS_EN_PAD    (BIT(26))
-#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
-#define EFUSE_HYS_EN_PAD_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_S  26
-/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0;
- *  Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2:
- *  Moderate 1. Low. 0: Disabled.
- */
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL    0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V  0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S  27
-/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0;
- *  Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0:
- *  Disable..
- */
-#define EFUSE_XTS_DPA_CLK_ENABLE    (BIT(29))
-#define EFUSE_XTS_DPA_CLK_ENABLE_M  (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
-#define EFUSE_XTS_DPA_CLK_ENABLE_V  0x00000001U
-#define EFUSE_XTS_DPA_CLK_ENABLE_S  29
-/** EFUSE_RD_RESERVE_0_158 : RW; bitpos: [31:30]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_158    0x00000003U
-#define EFUSE_RD_RESERVE_0_158_M  (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S)
-#define EFUSE_RD_RESERVE_0_158_V  0x00000003U
-#define EFUSE_RD_RESERVE_0_158_S  30
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_HUK_GEN_STATE : RO; bitpos: [8:0]; default: 0;
- *  Set the bits to control validation of HUK generate mode. Odd of 1 is invalid..
- *  Even of 1 is valid..
- */
-#define EFUSE_HUK_GEN_STATE    0x000001FFU
-#define EFUSE_HUK_GEN_STATE_M  (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S)
-#define EFUSE_HUK_GEN_STATE_V  0x000001FFU
-#define EFUSE_HUK_GEN_STATE_S  0
-/** EFUSE_XTAL_48M_SEL : RO; bitpos: [11:9]; default: 0;
- *  Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used.
- *  If this field contains Odd number bit '1': Enable 48MHz XTAL. Even number bit '1':
- *  Enable 40MHz XTAL.
- */
-#define EFUSE_XTAL_48M_SEL    0x00000007U
-#define EFUSE_XTAL_48M_SEL_M  (EFUSE_XTAL_48M_SEL_V << EFUSE_XTAL_48M_SEL_S)
-#define EFUSE_XTAL_48M_SEL_V  0x00000007U
-#define EFUSE_XTAL_48M_SEL_S  9
-/** EFUSE_XTAL_48M_SEL_MODE : RO; bitpos: [12]; default: 0;
- *  Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1:
- *  eFuse. 0: strapping-PAD-state.
- */
-#define EFUSE_XTAL_48M_SEL_MODE    (BIT(12))
-#define EFUSE_XTAL_48M_SEL_MODE_M  (EFUSE_XTAL_48M_SEL_MODE_V << EFUSE_XTAL_48M_SEL_MODE_S)
-#define EFUSE_XTAL_48M_SEL_MODE_V  0x00000001U
-#define EFUSE_XTAL_48M_SEL_MODE_S  12
-/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [13]; default: 0;
- *  Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disable.
- */
-#define EFUSE_ECDSA_DISABLE_P192    (BIT(13))
-#define EFUSE_ECDSA_DISABLE_P192_M  (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S)
-#define EFUSE_ECDSA_DISABLE_P192_V  0x00000001U
-#define EFUSE_ECDSA_DISABLE_P192_S  13
-/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [14]; default: 0;
- *  Represents whether to force ecc to use const-time calculation mode. . 1: Enable.
- *  . 0: Disable.
- */
-#define EFUSE_ECC_FORCE_CONST_TIME    (BIT(14))
-#define EFUSE_ECC_FORCE_CONST_TIME_M  (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
-#define EFUSE_ECC_FORCE_CONST_TIME_V  0x00000001U
-#define EFUSE_ECC_FORCE_CONST_TIME_S  14
-/** EFUSE_RD_RESERVE_0_175 : RW; bitpos: [31:15]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_175    0x0001FFFFU
-#define EFUSE_RD_RESERVE_0_175_M  (EFUSE_RD_RESERVE_0_175_V << EFUSE_RD_RESERVE_0_175_S)
-#define EFUSE_RD_RESERVE_0_175_V  0x0001FFFFU
-#define EFUSE_RD_RESERVE_0_175_S  15
-
-/** EFUSE_RD_MAC_SYS0_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents MAC address. Low 32-bit.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SYS1_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Represents MAC address. High 16-bit.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
- *  Represents the extended bits of MAC address.
- */
-#define EFUSE_MAC_EXT    0x0000FFFFU
-#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
-#define EFUSE_MAC_EXT_V  0x0000FFFFU
-#define EFUSE_MAC_EXT_S  16
-
-/** EFUSE_RD_MAC_SYS2_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_0    0x00003FFFU
-#define EFUSE_MAC_RESERVED_0_M  (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
-#define EFUSE_MAC_RESERVED_0_V  0x00003FFFU
-#define EFUSE_MAC_RESERVED_0_S  0
-/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_1    0x0003FFFFU
-#define EFUSE_MAC_RESERVED_1_M  (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
-#define EFUSE_MAC_RESERVED_1_V  0x0003FFFFU
-#define EFUSE_MAC_RESERVED_1_S  14
-
-/** EFUSE_RD_MAC_SYS3_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_2    0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
-#define EFUSE_MAC_RESERVED_2_V  0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_S  0
-/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
- *  Represents the first 14-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
-#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_S  18
-
-/** EFUSE_RD_MAC_SYS4_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the first 14-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
-#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_S  0
-
-/** EFUSE_RD_MAC_SYS5_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the second 32-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Represents rd_sys_part1_data0
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_0_M  (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
-#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_0_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Represents rd_sys_part1_data1
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_1_M  (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
-#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Represents rd_sys_part1_data2
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_2_M  (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
-#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Represents rd_sys_part1_data3
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_3_M  (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
-#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Represents rd_sys_part1_data4
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
-#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Represents rd_sys_part1_data5
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
-#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Represents rd_sys_part1_data6
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
-#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Represents rd_sys_part1_data7
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
-#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_S  0
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Represents rd_usr_data0
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Represents rd_usr_data1
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Represents rd_usr_data2
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Represents rd_usr_data3
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Represents rd_usr_data4
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Represents rd_usr_data5
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Represents rd_usr_data6
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Represents rd_usr_data7
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Represents rd_key0_data0
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Represents rd_key0_data1
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Represents rd_key0_data2
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Represents rd_key0_data3
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Represents rd_key0_data4
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Represents rd_key0_data5
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Represents rd_key0_data6
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Represents rd_key0_data7
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Represents rd_key1_data0
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Represents rd_key1_data1
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Represents rd_key1_data2
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Represents rd_key1_data3
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Represents rd_key1_data4
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Represents rd_key1_data5
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Represents rd_key1_data6
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Represents rd_key1_data7
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Represents rd_key2_data0
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Represents rd_key2_data1
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Represents rd_key2_data2
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Represents rd_key2_data3
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Represents rd_key2_data4
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Represents rd_key2_data5
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Represents rd_key2_data6
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Represents rd_key2_data7
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Represents rd_key3_data0
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Represents rd_key3_data1
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Represents rd_key3_data2
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Represents rd_key3_data3
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Represents rd_key3_data4
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Represents rd_key3_data5
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Represents rd_key3_data6
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Represents rd_key3_data7
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Represents rd_key4_data0
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Represents rd_key4_data1
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Represents rd_key4_data2
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Represents rd_key4_data3
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Represents rd_key4_data4
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Represents rd_key4_data5
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Represents rd_key4_data6
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Represents rd_key4_data7
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Represents rd_key5_data0
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Represents rd_key5_data1
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Represents rd_key5_data2
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Represents rd_key5_data3
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Represents rd_key5_data4
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Represents rd_key5_data5
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Represents rd_key5_data6
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Represents rd_key5_data7
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Represents rd_sys_part2_data0
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Represents rd_sys_part2_data1
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Represents rd_sys_part2_data2
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Represents rd_sys_part2_data3
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Represents rd_sys_part2_data4
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Represents rd_sys_part2_data5
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Represents rd_sys_part2_data6
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Represents rd_sys_part2_data7
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_DATA_ERR0_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Represents the programming error of EFUSE_RD_DIS
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
- *  Represents the programming error of EFUSE_DIS_ICACHE
- */
-#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
-#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
-#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_ICACHE_ERR_S  8
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_JTAG
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
- *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
-/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
- *  Represents the programming error of EFUSE_DIS_TWAI
- */
-#define EFUSE_DIS_TWAI_ERR    (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
-#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
-#define EFUSE_DIS_TWAI_ERR_S  14
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  Represents the programming error of EFUSE_DIS_PAD_JTAG
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  Represents the programming error of EFUSE_USB_DREFH
- */
-#define EFUSE_USB_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
-#define EFUSE_USB_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DREFH_ERR_S  21
-/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
- *  Represents the programming error of EFUSE_USB_DREFL
- */
-#define EFUSE_USB_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
-#define EFUSE_USB_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DREFL_ERR_S  23
-/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
- *  Represents the programming error of EFUSE_USB_EXCHG_PINS
- */
-#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
-#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_ERR_S  25
-/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
- *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
- */
-#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
-
-/** EFUSE_RD_REPEAT_DATA_ERR1_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [3:0]; default: 0;
- *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0;
- *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  4
-/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0;
- *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  6
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0;
- *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  10
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0;
- *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(14))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  14
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Represents the programming error of EFUSE_WDT_DELAY_SEL
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_0
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_1
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_DATA_ERR2_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_2
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_3
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_4
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_5
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
- */
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_EN
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [27]; default: 0;
- *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
- */
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR    (BIT(27))
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S)
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S  27
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Represents the programming error of EFUSE_FLASH_TPUW
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_DATA_ERR3_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
-/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
- *  Represents the programming error of EFUSE_LOCK_KM_KEY
- */
-#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
-#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_ERR_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
- *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_VERSION
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
-/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
- *  Represents the programming error of EFUSE_HYS_EN_PAD
- */
-#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
-#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
-#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_ERR_S  26
-
-/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0;
- *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
- */
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR    0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S)
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V  0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S  27
-/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [29]; default: 0;
- *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
- */
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR    (BIT(29))
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M  (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S)
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V  0x00000001U
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S  29
-
-/** EFUSE_RD_REPEAT_DATA_ERR4_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
-/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [8:0]; default: 0;
- *  Represents the programming error of EFUSE_HUK_GEN_STATE
- */
-#define EFUSE_HUK_GEN_STATE_ERR    0x000001FFU
-#define EFUSE_HUK_GEN_STATE_ERR_M  (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S)
-#define EFUSE_HUK_GEN_STATE_ERR_V  0x000001FFU
-#define EFUSE_HUK_GEN_STATE_ERR_S  0
-/** EFUSE_XTAL_48M_SEL_ERR : RO; bitpos: [11:9]; default: 0;
- *  Represents the programming error of EFUSE_XTAL_48M_SEL
- */
-#define EFUSE_XTAL_48M_SEL_ERR    0x00000007U
-#define EFUSE_XTAL_48M_SEL_ERR_M  (EFUSE_XTAL_48M_SEL_ERR_V << EFUSE_XTAL_48M_SEL_ERR_S)
-#define EFUSE_XTAL_48M_SEL_ERR_V  0x00000007U
-#define EFUSE_XTAL_48M_SEL_ERR_S  9
-/** EFUSE_XTAL_48M_SEL_MODE_ERR : RO; bitpos: [12]; default: 0;
- *  Represents the programming error of EFUSE_XTAL_48M_SEL_MODE
- */
-#define EFUSE_XTAL_48M_SEL_MODE_ERR    (BIT(12))
-#define EFUSE_XTAL_48M_SEL_MODE_ERR_M  (EFUSE_XTAL_48M_SEL_MODE_ERR_V << EFUSE_XTAL_48M_SEL_MODE_ERR_S)
-#define EFUSE_XTAL_48M_SEL_MODE_ERR_V  0x00000001U
-#define EFUSE_XTAL_48M_SEL_MODE_ERR_S  12
-/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [13]; default: 0;
- *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
- */
-#define EFUSE_ECDSA_DISABLE_P192_ERR    (BIT(13))
-#define EFUSE_ECDSA_DISABLE_P192_ERR_M  (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S)
-#define EFUSE_ECDSA_DISABLE_P192_ERR_V  0x00000001U
-#define EFUSE_ECDSA_DISABLE_P192_ERR_S  13
-/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [14]; default: 0;
- *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
- */
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR    (BIT(14))
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M  (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S)
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V  0x00000001U
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S  14
-
-/** EFUSE_RD_RS_DATA_ERR0_REG register
- *  Represents rd_rs_data_err
- */
-#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS_ERR_NUM    0x00000007U
-#define EFUSE_RD_MAC_SYS_ERR_NUM_M  (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S)
-#define EFUSE_RD_MAC_SYS_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_MAC_SYS_ERR_NUM_S  0
-/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_mac_sys is reliable. 1: Means that programming rd_mac_sys failed and the number
- *  of error bytes is over 6.
- */
-#define EFUSE_RD_MAC_SYS_FAIL    (BIT(3))
-#define EFUSE_RD_MAC_SYS_FAIL_M  (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S)
-#define EFUSE_RD_MAC_SYS_FAIL_V  0x00000001U
-#define EFUSE_RD_MAC_SYS_FAIL_S  3
-/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_sys_part1_data
- */
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S)
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S  4
-/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_sys_part1_data is reliable. 1: Means that programming rd_sys_part1_data failed
- *  and the number of error bytes is over 6.
- */
-#define EFUSE_RD_SYS_PART1_DATA_FAIL    (BIT(7))
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_M  (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S)
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_S  7
-/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_usr_data
- */
-#define EFUSE_RD_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_USR_DATA_ERR_NUM_M  (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S)
-#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
-/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_usr_data is reliable. 1: Means that programming rd_usr_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_RD_USR_DATA_FAIL_M  (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S)
-#define EFUSE_RD_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_USR_DATA_FAIL_S  11
-/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_key0_data
- */
-#define EFUSE_RD_KEY0_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_M  (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_S  12
-/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_key0_data is reliable. 1: Means that programming rd_key0_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY0_DATA_FAIL    (BIT(15))
-#define EFUSE_RD_KEY0_DATA_FAIL_M  (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S)
-#define EFUSE_RD_KEY0_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY0_DATA_FAIL_S  15
-/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_key1_data
- */
-#define EFUSE_RD_KEY1_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_M  (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_S  16
-/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_key1_data is reliable. 1: Means that programming rd_key1_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY1_DATA_FAIL    (BIT(19))
-#define EFUSE_RD_KEY1_DATA_FAIL_M  (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S)
-#define EFUSE_RD_KEY1_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY1_DATA_FAIL_S  19
-/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_key2_data
- */
-#define EFUSE_RD_KEY2_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_M  (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_S  20
-/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_key2_data is reliable. 1: Means that programming rd_key2_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY2_DATA_FAIL    (BIT(23))
-#define EFUSE_RD_KEY2_DATA_FAIL_M  (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S)
-#define EFUSE_RD_KEY2_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY2_DATA_FAIL_S  23
-/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_key3_data
- */
-#define EFUSE_RD_KEY3_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_M  (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_S  24
-/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_key3_data is reliable. 1: Means that programming rd_key3_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY3_DATA_FAIL    (BIT(27))
-#define EFUSE_RD_KEY3_DATA_FAIL_M  (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S)
-#define EFUSE_RD_KEY3_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY3_DATA_FAIL_S  27
-/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_key4_data
- */
-#define EFUSE_RD_KEY4_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_M  (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_S  28
-/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_key4_data is reliable. 1: Means that programming rd_key4_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY4_DATA_FAIL    (BIT(31))
-#define EFUSE_RD_KEY4_DATA_FAIL_M  (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S)
-#define EFUSE_RD_KEY4_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY4_DATA_FAIL_S  31
-
-/** EFUSE_RD_RS_DATA_ERR1_REG register
- *  Represents rd_rs_data_err
- */
-#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_key5_data
- */
-#define EFUSE_RD_KEY5_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_M  (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_S  0
-/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_key5_data is reliable. 1: Means that programming rd_key5_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY5_DATA_FAIL    (BIT(3))
-#define EFUSE_RD_KEY5_DATA_FAIL_M  (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S)
-#define EFUSE_RD_KEY5_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY5_DATA_FAIL_S  3
-/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  Represents the error number of registers..The value of this signal means the
- *  number of error bytes in rd_sys_part2_data
- */
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S)
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S  4
-/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0;
- *  Represents error status of register..0: Means no failure and that the data of
- *  rd_sys_part2_data is reliable. 1: Means that programming rd_sys_part2_data failed
- *  and the number of error bytes is over 6.
- */
-#define EFUSE_RD_SYS_PART2_DATA_FAIL    (BIT(7))
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_M  (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S)
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_S  7
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to force enable eFuse register configuration clock signal.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A:  programming operation command 0x5AA5: read operation command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
- *  Configures which block to use for ECDSA key output.
- */
-#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
-#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_S  16
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
- *  Indicates the number of block valid bit.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
- *  Indicates which block is used for ECDSA key output.
- */
-#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
-#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_S  20
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the read hold time.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures the read time.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures the read setup time.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
- *  Configures the waiting time of reading eFuse memory.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the programming setup time.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
- *  Configures the programming hold time.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  24
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
- *  Configures the active programming time.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
-/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
- *  Set this bit to bypass reed solomon correction step.
- */
-#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
-#define EFUSE_BYPASS_RS_CORRECTION_S  0
-/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
- *  Configures block number of programming twice operation.
- */
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
- *  Set this bit to update multi-bit register signals.
- */
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
-#define EFUSE_UPDATE_V  0x00000001U
-#define EFUSE_UPDATE_S  12
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
- *  Configures the inactive programming time.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  13
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_struct.h b/components/soc/esp32c5/beta3/include/soc/efuse_struct.h
deleted file mode 100644
index 88e48c0452..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,2390 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: buffer0 registers */
-/** Type of pgm_data0 register
- *  Represents pgm_data0
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Represents pgm_data1
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Represents pgm_data2
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Represents pgm_data3
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Represents pgm_data4
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Represents pgm_data5
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Represents pgm_data6
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Represents pgm_data7
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-
-/** Group: buffer1 registers */
-/** Type of pgm_check_value0 register
- *  Represents pgm_check_value0
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Represents pgm_check_value1
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Represents pgm_check_value2
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: block0 registers */
-/** Type of rd_wr_dis0 register
- *  Represents rd_wr_dis
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled. 1: Disabled. 0: Enabled.
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis0_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t rd_dis:7;
-        /** rd_reserve_0_39 : RW; bitpos: [7]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_39:1;
-        /** dis_icache : RO; bitpos: [8]; default: 0;
-         *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_icache:1;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** rd_reserve_0_42 : RW; bitpos: [10]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_42:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
-         *  Represents whether SPI0 controller during boot_mode_download is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even
-         *  number: enabled.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled.
-         *  0: enabled.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode). 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefh:2;
-        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefl:2;
-        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
-         *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not
-         *  exchanged.
-         */
-        uint32_t usb_exchg_pins:1;
-        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
-         *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
-         *  functioned.
-         */
-        uint32_t vdd_spi_as_gpio:1;
-        /** rd_reserve_0_59 : RW; bitpos: [31:27]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_59:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** km_disable_deploy_mode : RO; bitpos: [3:0]; default: 0;
-         *  Represents whether the deploy mode of key manager is disable or not. . 1: disabled
-         *  . 0: enabled..
-         */
-        uint32_t km_disable_deploy_mode:4;
-        /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0;
-         *  Set the bits to control key manager random number switch cycle. 0: control by
-         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
-         */
-        uint32_t km_rnd_switch_cycle:2;
-        /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0;
-         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
-         *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
-         */
-        uint32_t km_deploy_only_once:4;
-        /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0;
-         *  Set each bit to control whether corresponding key must come from key manager. 1 is
-         *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
-         */
-        uint32_t force_use_key_manager_key:4;
-        /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0;
-         *  Set this bit to disable software written init key, and force use efuse_init_key.
-         */
-        uint32_t force_disable_sw_init_key:1;
-        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_79:1;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original
-         *  threshold configuration value of STG0 *2 .1: Original threshold configuration
-         *  value of STG0 *4 .2: Original threshold configuration value of STG0 *8 .3:
-         *  Original threshold configuration value of STG0 *16 .
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
-         *  1: enabled. Even number of 1: disabled.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Represents the purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Represents the purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
-         */
-        uint32_t sec_dpa_level:2;
-        /** rd_reserve_0_114 : RW; bitpos: [19:18]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_114:2;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** rd_reserve_0_118 : RW; bitpos: [26:22]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_118:5;
-        /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0;
-         *  Set this bitto configure flash encryption use xts-128 key. else use xts-256 key.
-         */
-        uint32_t km_xts_key_length_256:1;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
-         *  is 2 times the programmed value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** lock_km_key : RO; bitpos: [3]; default: 0;
-         *  Represetns whether to lock the efuse xts key. 1. Lock. 0: Unlock.
-         */
-        uint32_t lock_km_key:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled..
-         *  1: Disable. 0: Enable.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
-         *  disabled.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Represents the type of UART printing. 00: force enable printing. 01: enable
-         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
-         *  at high level. 11: force disable printing.
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [8]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot..
-         *  1: forced. 0:not forced.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [24:9]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
-         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** hys_en_pad : RO; bitpos: [26]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
-         *  enabled. 0:disabled.
-         */
-        uint32_t hys_en_pad:1;
-        /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0;
-         *  Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2:
-         *  Moderate 1. Low. 0: Disabled.
-         */
-        uint32_t xts_dpa_pseudo_level:2;
-        /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0;
-         *  Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0:
-         *  Disable..
-         */
-        uint32_t xts_dpa_clk_enable:1;
-        /** rd_reserve_0_158 : RW; bitpos: [31:30]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_158:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** huk_gen_state : RO; bitpos: [8:0]; default: 0;
-         *  Set the bits to control validation of HUK generate mode. Odd of 1 is invalid..
-         *  Even of 1 is valid..
-         */
-        uint32_t huk_gen_state:9;
-        /** xtal_48m_sel : RO; bitpos: [11:9]; default: 0;
-         *  Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used.
-         *  If this field contains Odd number bit '1': Enable 48MHz XTAL. Even number bit '1':
-         *  Enable 40MHz XTAL.
-         */
-        uint32_t xtal_48m_sel:3;
-        /** xtal_48m_sel_mode : RO; bitpos: [12]; default: 0;
-         *  Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1:
-         *  eFuse. 0: strapping-PAD-state.
-         */
-        uint32_t xtal_48m_sel_mode:1;
-        /** ecdsa_disable_p192 : RO; bitpos: [13]; default: 0;
-         *  Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disable.
-         */
-        uint32_t ecdsa_disable_p192:1;
-        /** ecc_force_const_time : RO; bitpos: [14]; default: 0;
-         *  Represents whether to force ecc to use const-time calculation mode. . 1: Enable.
-         *  . 0: Disable.
-         */
-        uint32_t ecc_force_const_time:1;
-        /** rd_reserve_0_175 : RW; bitpos: [31:15]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_175:17;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-
-/** Group: block1 registers */
-/** Type of rd_mac_sys0 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents MAC address. Low 32-bit.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys0_reg_t;
-
-/** Type of rd_mac_sys1 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Represents MAC address. High 16-bit.
-         */
-        uint32_t mac_1:16;
-        /** mac_ext : RO; bitpos: [31:16]; default: 0;
-         *  Represents the extended bits of MAC address.
-         */
-        uint32_t mac_ext:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys1_reg_t;
-
-/** Type of rd_mac_sys2 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_0:14;
-        /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_1:18;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys2_reg_t;
-
-/** Type of rd_mac_sys3 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_2:18;
-        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
-         *  Represents the first 14-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_0:14;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys3_reg_t;
-
-/** Type of rd_mac_sys4 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the first 14-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_1:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys4_reg_t;
-
-/** Type of rd_mac_sys5 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the second 32-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys5_reg_t;
-
-
-/** Group: block2 registers */
-/** Type of rd_sys_part1_data0 register
- *  Represents rd_sys_part1_data0
- */
-typedef union {
-    struct {
-        /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Represents rd_sys_part1_data1
- */
-typedef union {
-    struct {
-        /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Represents rd_sys_part1_data2
- */
-typedef union {
-    struct {
-        /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Represents rd_sys_part1_data3
- */
-typedef union {
-    struct {
-        /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Represents rd_sys_part1_data4
- */
-typedef union {
-    struct {
-        /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Represents rd_sys_part1_data5
- */
-typedef union {
-    struct {
-        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Represents rd_sys_part1_data6
- */
-typedef union {
-    struct {
-        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Represents rd_sys_part1_data7
- */
-typedef union {
-    struct {
-        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-
-/** Group: block3 registers */
-/** Type of rd_usr_data0 register
- *  Represents rd_usr_data0
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Represents rd_usr_data1
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Represents rd_usr_data2
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Represents rd_usr_data3
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Represents rd_usr_data4
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Represents rd_usr_data5
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Represents rd_usr_data6
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Represents rd_usr_data7
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-
-/** Group: block4 registers */
-/** Type of rd_key0_data0 register
- *  Represents rd_key0_data0
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Represents rd_key0_data1
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Represents rd_key0_data2
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Represents rd_key0_data3
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Represents rd_key0_data4
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Represents rd_key0_data5
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Represents rd_key0_data6
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Represents rd_key0_data7
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-
-/** Group: block5 registers */
-/** Type of rd_key1_data0 register
- *  Represents rd_key1_data0
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Represents rd_key1_data1
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Represents rd_key1_data2
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Represents rd_key1_data3
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Represents rd_key1_data4
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Represents rd_key1_data5
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Represents rd_key1_data6
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Represents rd_key1_data7
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-
-/** Group: block6 registers */
-/** Type of rd_key2_data0 register
- *  Represents rd_key2_data0
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Represents rd_key2_data1
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Represents rd_key2_data2
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Represents rd_key2_data3
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Represents rd_key2_data4
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Represents rd_key2_data5
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Represents rd_key2_data6
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Represents rd_key2_data7
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-
-/** Group: block7 registers */
-/** Type of rd_key3_data0 register
- *  Represents rd_key3_data0
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Represents rd_key3_data1
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Represents rd_key3_data2
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Represents rd_key3_data3
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Represents rd_key3_data4
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Represents rd_key3_data5
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Represents rd_key3_data6
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Represents rd_key3_data7
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-
-/** Group: block8 registers */
-/** Type of rd_key4_data0 register
- *  Represents rd_key4_data0
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Represents rd_key4_data1
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Represents rd_key4_data2
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Represents rd_key4_data3
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Represents rd_key4_data4
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Represents rd_key4_data5
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Represents rd_key4_data6
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Represents rd_key4_data7
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-
-/** Group: block9 registers */
-/** Type of rd_key5_data0 register
- *  Represents rd_key5_data0
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Represents rd_key5_data1
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Represents rd_key5_data2
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Represents rd_key5_data3
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Represents rd_key5_data4
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Represents rd_key5_data5
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Represents rd_key5_data6
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Represents rd_key5_data7
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-
-/** Group: block10 registers */
-/** Type of rd_sys_part2_data0 register
- *  Represents rd_sys_part2_data0
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Represents rd_sys_part2_data1
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Represents rd_sys_part2_data2
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Represents rd_sys_part2_data3
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Represents rd_sys_part2_data4
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Represents rd_sys_part2_data5
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Represents rd_sys_part2_data6
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Represents rd_sys_part2_data7
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: block0 error report registers */
-/** Type of rd_repeat_data_err0 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Represents the programming error of EFUSE_RD_DIS
-         */
-        uint32_t rd_dis_err:7;
-        uint32_t reserved_7:1;
-        /** dis_icache_err : RO; bitpos: [8]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_ICACHE
-         */
-        uint32_t dis_icache_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_JTAG
-         */
-        uint32_t dis_usb_jtag_err:1;
-        uint32_t reserved_10:1;
-        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
-         */
-        uint32_t dis_usb_serial_jtag_err:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_TWAI
-         */
-        uint32_t dis_twai_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  Represents the programming error of EFUSE_USB_DREFH
-         */
-        uint32_t usb_drefh_err:2;
-        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
-         *  Represents the programming error of EFUSE_USB_DREFL
-         */
-        uint32_t usb_drefl_err:2;
-        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
-         *  Represents the programming error of EFUSE_USB_EXCHG_PINS
-         */
-        uint32_t usb_exchg_pins_err:1;
-        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
-         */
-        uint32_t vdd_spi_as_gpio_err:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err0_reg_t;
-
-/** Type of rd_repeat_data_err1 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** km_disable_deploy_mode_err : RO; bitpos: [3:0]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
-         */
-        uint32_t km_disable_deploy_mode_err:4;
-        /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0;
-         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
-         */
-        uint32_t km_rnd_switch_cycle_err:2;
-        /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
-         */
-        uint32_t km_deploy_only_once_err:4;
-        /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
-         */
-        uint32_t force_use_key_manager_key_err:4;
-        /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
-         */
-        uint32_t force_disable_sw_init_key_err:1;
-        uint32_t reserved_15:1;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err1_reg_t;
-
-/** Type of rd_repeat_data_err2 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
-         */
-        uint32_t sec_dpa_level_err:2;
-        uint32_t reserved_18:2;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        uint32_t reserved_22:5;
-        /** km_xts_key_length_256_err : RO; bitpos: [27]; default: 0;
-         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
-         */
-        uint32_t km_xts_key_length_256_err:1;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Represents the programming error of EFUSE_FLASH_TPUW
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err2_reg_t;
-
-/** Type of rd_repeat_data_err3 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
-         */
-        uint32_t dis_usb_serial_jtag_rom_print_err:1;
-        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
-         *  Represents the programming error of EFUSE_LOCK_KM_KEY
-         */
-        uint32_t lock_km_key_err:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_VERSION
-         */
-        uint32_t secure_version_err:16;
-        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
-         */
-        uint32_t secure_boot_disable_fast_wake_err:1;
-        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_HYS_EN_PAD
-         */
-        uint32_t hys_en_pad_err:1;
-        /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
-         */
-        uint32_t xts_dpa_pseudo_level_err:2;
-        /** xts_dpa_clk_enable_err : RO; bitpos: [29]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
-         */
-        uint32_t xts_dpa_clk_enable_err:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err3_reg_t;
-
-/** Type of rd_repeat_data_err4 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** huk_gen_state_err : RO; bitpos: [8:0]; default: 0;
-         *  Represents the programming error of EFUSE_HUK_GEN_STATE
-         */
-        uint32_t huk_gen_state_err:9;
-        /** xtal_48m_sel_err : RO; bitpos: [11:9]; default: 0;
-         *  Represents the programming error of EFUSE_XTAL_48M_SEL
-         */
-        uint32_t xtal_48m_sel_err:3;
-        /** xtal_48m_sel_mode_err : RO; bitpos: [12]; default: 0;
-         *  Represents the programming error of EFUSE_XTAL_48M_SEL_MODE
-         */
-        uint32_t xtal_48m_sel_mode_err:1;
-        /** ecdsa_disable_p192_err : RO; bitpos: [13]; default: 0;
-         *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
-         */
-        uint32_t ecdsa_disable_p192_err:1;
-        /** ecc_force_const_time_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
-         */
-        uint32_t ecc_force_const_time_err:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err4_reg_t;
-
-
-/** Group: RS block error report registers */
-/** Type of rd_rs_data_err0 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_mac_sys
-         */
-        uint32_t rd_mac_sys_err_num:3;
-        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_mac_sys is reliable. 1: Means that programming rd_mac_sys failed and the number
-         *  of error bytes is over 6.
-         */
-        uint32_t rd_mac_sys_fail:1;
-        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_sys_part1_data
-         */
-        uint32_t rd_sys_part1_data_err_num:3;
-        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_sys_part1_data is reliable. 1: Means that programming rd_sys_part1_data failed
-         *  and the number of error bytes is over 6.
-         */
-        uint32_t rd_sys_part1_data_fail:1;
-        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_usr_data
-         */
-        uint32_t rd_usr_data_err_num:3;
-        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_usr_data is reliable. 1: Means that programming rd_usr_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_usr_data_fail:1;
-        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_key0_data
-         */
-        uint32_t rd_key0_data_err_num:3;
-        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_key0_data is reliable. 1: Means that programming rd_key0_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key0_data_fail:1;
-        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_key1_data
-         */
-        uint32_t rd_key1_data_err_num:3;
-        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_key1_data is reliable. 1: Means that programming rd_key1_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key1_data_fail:1;
-        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_key2_data
-         */
-        uint32_t rd_key2_data_err_num:3;
-        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_key2_data is reliable. 1: Means that programming rd_key2_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key2_data_fail:1;
-        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_key3_data
-         */
-        uint32_t rd_key3_data_err_num:3;
-        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_key3_data is reliable. 1: Means that programming rd_key3_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key3_data_fail:1;
-        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_key4_data
-         */
-        uint32_t rd_key4_data_err_num:3;
-        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_key4_data is reliable. 1: Means that programming rd_key4_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key4_data_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err0_reg_t;
-
-/** Type of rd_rs_data_err1 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_key5_data
-         */
-        uint32_t rd_key5_data_err_num:3;
-        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_key5_data is reliable. 1: Means that programming rd_key5_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key5_data_fail:1;
-        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers..The value of this signal means the
-         *  number of error bytes in rd_sys_part2_data
-         */
-        uint32_t rd_sys_part2_data_err_num:3;
-        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register..0: Means no failure and that the data of
-         *  rd_sys_part2_data is reliable. 1: Means that programming rd_sys_part2_data failed
-         *  and the number of error bytes is over 6.
-         */
-        uint32_t rd_sys_part2_data_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err1_reg_t;
-
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuraiton register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
-         *  Configures which block to use for ECDSA key output.
-         */
-        uint32_t cfg_ecdsa_blk:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        uint32_t reserved_4:6;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 160;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35684640;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-typedef struct efuse_dev_t {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
-    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
-    volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2;
-    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
-    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
-    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
-    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
-    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
-    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
-    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
-    uint32_t reserved_190[12];
-    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
-    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    volatile efuse_date_reg_t date;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ext_mem_defs.h b/components/soc/esp32c5/beta3/include/soc/ext_mem_defs.h
deleted file mode 100644
index d0423ee373..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ext_mem_defs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "esp_bit_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !SOC_MMU_PAGE_SIZE
-/**
- * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
- * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
- */
-#define SOC_MMU_PAGE_SIZE 0x10000
-#endif
-
-
-#define SOC_IRAM0_CACHE_ADDRESS_LOW                  0x41000000
-#define SOC_IRAM0_CACHE_ADDRESS_HIGH                 (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
-
-#define SOC_DRAM0_CACHE_ADDRESS_LOW                  SOC_IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
-#define SOC_DRAM0_CACHE_ADDRESS_HIGH                 SOC_IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
-
-#define SOC_IRAM_FLASH_ADDRESS_LOW                   SOC_IRAM0_CACHE_ADDRESS_LOW
-#define SOC_IRAM_FLASH_ADDRESS_HIGH                  SOC_IRAM0_CACHE_ADDRESS_HIGH
-
-#define SOC_DRAM_FLASH_ADDRESS_LOW                   SOC_DRAM0_CACHE_ADDRESS_LOW
-#define SOC_DRAM_FLASH_ADDRESS_HIGH                  SOC_DRAM0_CACHE_ADDRESS_HIGH
-
-#define SOC_BUS_SIZE(bus_name)                       (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)          ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
-
-#define SOC_ADDRESS_IN_IRAM0(vaddr)                  SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
-#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
-#define SOC_ADDRESS_IN_DRAM0(vaddr)                  SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
-#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
-
-#define SOC_MMU_ACCESS_FLASH            0
-#define SOC_MMU_VALID                   BIT(9)
-#define SOC_MMU_SENSITIVE               BIT(10)
-#define SOC_MMU_INVALID_MASK            BIT(9)
-#define SOC_MMU_INVALID                 0
-
-/**
- * MMU entry valid bit mask for mapping value. For an entry:
- * valid bit + value bits
- * valid bit is BIT(9), so value bits are 0x1ff
- */
-#define SOC_MMU_VALID_VAL_MASK 0x1ff
-/**
- * Max MMU available paddr page num.
- * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
- * 256 * 64KB, means MMU can support 16MB paddr at most
- */
-#define SOC_MMU_MAX_PADDR_PAGE_NUM    256
-//MMU entry num
-#define SOC_MMU_ENTRY_NUM   256
-
-/**
- * This is the mask used for mapping. e.g.:
- * 0x4200_0000 & SOC_MMU_VADDR_MASK
- */
-#define SOC_MMU_VADDR_MASK                  ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
-
-#define SOC_MMU_DBUS_VADDR_BASE               0x41000000
-#define SOC_MMU_IBUS_VADDR_BASE               0x41000000
-
-/*------------------------------------------------------------------------------
- * MMU Linear Address
- *----------------------------------------------------------------------------*/
-#if (SOC_MMU_PAGE_SIZE == 0x10000)
-/**
- * - 64KB MMU page size: the last 0xFFFF, which is the offset
- * - 128 MMU entries, needs 0x7F to hold it.
- *
- * Therefore, 0x7F,FFFF
- */
-#define SOC_MMU_LINEAR_ADDR_MASK              0x7FFFFF
-
-#elif (SOC_MMU_PAGE_SIZE == 0x8000)
-/**
- * - 32KB MMU page size: the last 0x7FFF, which is the offset
- * - 128 MMU entries, needs 0x7F to hold it.
- *
- * Therefore, 0x3F,FFFF
- */
-#define SOC_MMU_LINEAR_ADDR_MASK              0x3FFFFF
-
-#elif (SOC_MMU_PAGE_SIZE == 0x4000)
-/**
- * - 16KB MMU page size: the last 0x3FFF, which is the offset
- * - 128 MMU entries, needs 0x7F to hold it.
- *
- * Therefore, 0x1F,FFFF
- */
-#define SOC_MMU_LINEAR_ADDR_MASK              0x1FFFFF
-#endif  //SOC_MMU_PAGE_SIZE
-
-/**
- * - If high linear address isn't 0, this means MMU can recognize these addresses
- * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
- *   Under this condition, we use the max linear space.
- */
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
-#else
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
-#endif
-
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
-#else
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
-#endif
-
-/**
- * I/D share the MMU linear address range
- */
-#ifndef __cplusplus
-_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gdma_channel.h b/components/soc/esp32c5/beta3/include/soc/gdma_channel.h
deleted file mode 100644
index 73ba4976f6..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gdma_channel.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
-#define SOC_GDMA_TRIG_PERIPH_M2M0    (-1)
-#define SOC_GDMA_TRIG_PERIPH_SPI2    (0)
-#define SOC_GDMA_TRIG_PERIPH_UHCI0   (2)
-#define SOC_GDMA_TRIG_PERIPH_I2S0    (3)
-#define SOC_GDMA_TRIG_PERIPH_AES0    (6)
-#define SOC_GDMA_TRIG_PERIPH_SHA0    (7)
-#define SOC_GDMA_TRIG_PERIPH_ADC0    (8)
-#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
-
-// On which system bus is the DMA instance of the peripheral connection mounted
-#define SOC_GDMA_BUS_ANY (-1)
-#define SOC_GDMA_BUS_AHB (0)
-
-#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS     SOC_GDMA_BUS_ANY
-#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS     SOC_GDMA_BUS_AHB
-#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS    SOC_GDMA_BUS_AHB
-#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS     SOC_GDMA_BUS_AHB
-#define SOC_GDMA_TRIG_PERIPH_AES0_BUS     SOC_GDMA_BUS_AHB
-#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS     SOC_GDMA_BUS_AHB
-#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS     SOC_GDMA_BUS_AHB
-#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS  SOC_GDMA_BUS_AHB
diff --git a/components/soc/esp32c5/beta3/include/soc/gdma_reg.h b/components/soc/esp32c5/beta3/include/soc/gdma_reg.h
deleted file mode 100644
index bc014834e1..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gdma_reg.h
+++ /dev/null
@@ -1,3213 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GDMA_IN_INT_RAW_CH0_REG register
- *  Raw status interrupt of channel 0
- */
-#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0)
-/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one inlink
- *  descriptor has been received for Rx channel 0.
- */
-#define GDMA_IN_DONE_CH0_INT_RAW    (BIT(0))
-#define GDMA_IN_DONE_CH0_INT_RAW_M  (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S)
-#define GDMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
-#define GDMA_IN_DONE_CH0_INT_RAW_S  0
-/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one inlink
- *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
- *  turns to high level when the last data pointed by one inlink descriptor has been
- *  received and no data error is detected for Rx channel 0.
- */
-#define GDMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M  (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S)
-#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S  1
-/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when data error is detected only in the
- *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
- *  interrupt is reserved.
- */
-#define GDMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M  (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S)
-#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S  2
-/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt bit turns to high level when detecting inlink descriptor error
- *  including owner error and the second and third word error of inlink descriptor for
- *  Rx channel 0.
- */
-#define GDMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M  (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S)
-#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
-/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
- *  and receiving data is not completed but there is no more inlink for Rx channel 0.
- */
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  4
-/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
- *  overflow.
- */
-#define GDMA_INFIFO_OVF_CH0_INT_RAW    (BIT(5))
-#define GDMA_INFIFO_OVF_CH0_INT_RAW_M  (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S)
-#define GDMA_INFIFO_OVF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH0_INT_RAW_S  5
-/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
- *  underflow.
- */
-#define GDMA_INFIFO_UDF_CH0_INT_RAW    (BIT(6))
-#define GDMA_INFIFO_UDF_CH0_INT_RAW_M  (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S)
-#define GDMA_INFIFO_UDF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH0_INT_RAW_S  6
-
-/** GDMA_IN_INT_ST_CH0_REG register
- *  Masked interrupt of channel 0
- */
-#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4)
-/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH0_INT_ST    (BIT(0))
-#define GDMA_IN_DONE_CH0_INT_ST_M  (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S)
-#define GDMA_IN_DONE_CH0_INT_ST_V  0x00000001U
-#define GDMA_IN_DONE_CH0_INT_ST_S  0
-/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH0_INT_ST_M  (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S)
-#define GDMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH0_INT_ST_S  1
-/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH0_INT_ST_M  (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S)
-#define GDMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH0_INT_ST_S  2
-/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M  (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S)
-#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S  3
-/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S  4
-/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH0_INT_ST    (BIT(5))
-#define GDMA_INFIFO_OVF_CH0_INT_ST_M  (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S)
-#define GDMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH0_INT_ST_S  5
-/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH0_INT_ST    (BIT(6))
-#define GDMA_INFIFO_UDF_CH0_INT_ST_M  (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S)
-#define GDMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH0_INT_ST_S  6
-
-/** GDMA_IN_INT_ENA_CH0_REG register
- *  Interrupt enable bits of channel 0
- */
-#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8)
-/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH0_INT_ENA    (BIT(0))
-#define GDMA_IN_DONE_CH0_INT_ENA_M  (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S)
-#define GDMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
-#define GDMA_IN_DONE_CH0_INT_ENA_S  0
-/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M  (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S)
-#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S  1
-/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M  (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S)
-#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S  2
-/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M  (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S)
-#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
-/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  4
-/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH0_INT_ENA    (BIT(5))
-#define GDMA_INFIFO_OVF_CH0_INT_ENA_M  (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S)
-#define GDMA_INFIFO_OVF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH0_INT_ENA_S  5
-/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH0_INT_ENA    (BIT(6))
-#define GDMA_INFIFO_UDF_CH0_INT_ENA_M  (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S)
-#define GDMA_INFIFO_UDF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH0_INT_ENA_S  6
-
-/** GDMA_IN_INT_CLR_CH0_REG register
- *  Interrupt clear bits of channel 0
- */
-#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc)
-/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH0_INT_CLR    (BIT(0))
-#define GDMA_IN_DONE_CH0_INT_CLR_M  (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S)
-#define GDMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
-#define GDMA_IN_DONE_CH0_INT_CLR_S  0
-/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M  (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S)
-#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S  1
-/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M  (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S)
-#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S  2
-/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M  (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S)
-#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
-/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  4
-/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH0_INT_CLR    (BIT(5))
-#define GDMA_INFIFO_OVF_CH0_INT_CLR_M  (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S)
-#define GDMA_INFIFO_OVF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH0_INT_CLR_S  5
-/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH0_INT_CLR    (BIT(6))
-#define GDMA_INFIFO_UDF_CH0_INT_CLR_M  (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S)
-#define GDMA_INFIFO_UDF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH0_INT_CLR_S  6
-
-/** GDMA_IN_INT_RAW_CH1_REG register
- *  Raw status interrupt of channel 0
- */
-#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10)
-/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one inlink
- *  descriptor has been received for Rx channel 0.
- */
-#define GDMA_IN_DONE_CH1_INT_RAW    (BIT(0))
-#define GDMA_IN_DONE_CH1_INT_RAW_M  (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S)
-#define GDMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
-#define GDMA_IN_DONE_CH1_INT_RAW_S  0
-/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one inlink
- *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
- *  turns to high level when the last data pointed by one inlink descriptor has been
- *  received and no data error is detected for Rx channel 0.
- */
-#define GDMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M  (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S)
-#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S  1
-/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when data error is detected only in the
- *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
- *  interrupt is reserved.
- */
-#define GDMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M  (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S)
-#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S  2
-/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt bit turns to high level when detecting inlink descriptor error
- *  including owner error and the second and third word error of inlink descriptor for
- *  Rx channel 0.
- */
-#define GDMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M  (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S)
-#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
-/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
- *  and receiving data is not completed but there is no more inlink for Rx channel 0.
- */
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  4
-/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
- *  overflow.
- */
-#define GDMA_INFIFO_OVF_CH1_INT_RAW    (BIT(5))
-#define GDMA_INFIFO_OVF_CH1_INT_RAW_M  (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S)
-#define GDMA_INFIFO_OVF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH1_INT_RAW_S  5
-/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
- *  underflow.
- */
-#define GDMA_INFIFO_UDF_CH1_INT_RAW    (BIT(6))
-#define GDMA_INFIFO_UDF_CH1_INT_RAW_M  (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S)
-#define GDMA_INFIFO_UDF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH1_INT_RAW_S  6
-
-/** GDMA_IN_INT_ST_CH1_REG register
- *  Masked interrupt of channel 0
- */
-#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14)
-/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH1_INT_ST    (BIT(0))
-#define GDMA_IN_DONE_CH1_INT_ST_M  (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S)
-#define GDMA_IN_DONE_CH1_INT_ST_V  0x00000001U
-#define GDMA_IN_DONE_CH1_INT_ST_S  0
-/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH1_INT_ST_M  (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S)
-#define GDMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH1_INT_ST_S  1
-/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH1_INT_ST_M  (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S)
-#define GDMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH1_INT_ST_S  2
-/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M  (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S)
-#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S  3
-/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S  4
-/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH1_INT_ST    (BIT(5))
-#define GDMA_INFIFO_OVF_CH1_INT_ST_M  (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S)
-#define GDMA_INFIFO_OVF_CH1_INT_ST_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH1_INT_ST_S  5
-/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH1_INT_ST    (BIT(6))
-#define GDMA_INFIFO_UDF_CH1_INT_ST_M  (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S)
-#define GDMA_INFIFO_UDF_CH1_INT_ST_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH1_INT_ST_S  6
-
-/** GDMA_IN_INT_ENA_CH1_REG register
- *  Interrupt enable bits of channel 0
- */
-#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18)
-/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH1_INT_ENA    (BIT(0))
-#define GDMA_IN_DONE_CH1_INT_ENA_M  (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S)
-#define GDMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
-#define GDMA_IN_DONE_CH1_INT_ENA_S  0
-/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M  (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S)
-#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S  1
-/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M  (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S)
-#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S  2
-/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M  (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S)
-#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
-/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  4
-/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH1_INT_ENA    (BIT(5))
-#define GDMA_INFIFO_OVF_CH1_INT_ENA_M  (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S)
-#define GDMA_INFIFO_OVF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH1_INT_ENA_S  5
-/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH1_INT_ENA    (BIT(6))
-#define GDMA_INFIFO_UDF_CH1_INT_ENA_M  (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S)
-#define GDMA_INFIFO_UDF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH1_INT_ENA_S  6
-
-/** GDMA_IN_INT_CLR_CH1_REG register
- *  Interrupt clear bits of channel 0
- */
-#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c)
-/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH1_INT_CLR    (BIT(0))
-#define GDMA_IN_DONE_CH1_INT_CLR_M  (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S)
-#define GDMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
-#define GDMA_IN_DONE_CH1_INT_CLR_S  0
-/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M  (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S)
-#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S  1
-/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M  (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S)
-#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S  2
-/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M  (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S)
-#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
-/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  4
-/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH1_INT_CLR    (BIT(5))
-#define GDMA_INFIFO_OVF_CH1_INT_CLR_M  (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S)
-#define GDMA_INFIFO_OVF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH1_INT_CLR_S  5
-/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH1_INT_CLR    (BIT(6))
-#define GDMA_INFIFO_UDF_CH1_INT_CLR_M  (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S)
-#define GDMA_INFIFO_UDF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH1_INT_CLR_S  6
-
-/** GDMA_IN_INT_RAW_CH2_REG register
- *  Raw status interrupt of channel 0
- */
-#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20)
-/** GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one inlink
- *  descriptor has been received for Rx channel 0.
- */
-#define GDMA_IN_DONE_CH2_INT_RAW    (BIT(0))
-#define GDMA_IN_DONE_CH2_INT_RAW_M  (GDMA_IN_DONE_CH2_INT_RAW_V << GDMA_IN_DONE_CH2_INT_RAW_S)
-#define GDMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
-#define GDMA_IN_DONE_CH2_INT_RAW_S  0
-/** GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one inlink
- *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
- *  turns to high level when the last data pointed by one inlink descriptor has been
- *  received and no data error is detected for Rx channel 0.
- */
-#define GDMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M  (GDMA_IN_SUC_EOF_CH2_INT_RAW_V << GDMA_IN_SUC_EOF_CH2_INT_RAW_S)
-#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S  1
-/** GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when data error is detected only in the
- *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
- *  interrupt is reserved.
- */
-#define GDMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M  (GDMA_IN_ERR_EOF_CH2_INT_RAW_V << GDMA_IN_ERR_EOF_CH2_INT_RAW_S)
-#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S  2
-/** GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt bit turns to high level when detecting inlink descriptor error
- *  including owner error and the second and third word error of inlink descriptor for
- *  Rx channel 0.
- */
-#define GDMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M  (GDMA_IN_DSCR_ERR_CH2_INT_RAW_V << GDMA_IN_DSCR_ERR_CH2_INT_RAW_S)
-#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
-/** GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
- *  and receiving data is not completed but there is no more inlink for Rx channel 0.
- */
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  4
-/** GDMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
- *  overflow.
- */
-#define GDMA_INFIFO_OVF_CH2_INT_RAW    (BIT(5))
-#define GDMA_INFIFO_OVF_CH2_INT_RAW_M  (GDMA_INFIFO_OVF_CH2_INT_RAW_V << GDMA_INFIFO_OVF_CH2_INT_RAW_S)
-#define GDMA_INFIFO_OVF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH2_INT_RAW_S  5
-/** GDMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
- *  underflow.
- */
-#define GDMA_INFIFO_UDF_CH2_INT_RAW    (BIT(6))
-#define GDMA_INFIFO_UDF_CH2_INT_RAW_M  (GDMA_INFIFO_UDF_CH2_INT_RAW_V << GDMA_INFIFO_UDF_CH2_INT_RAW_S)
-#define GDMA_INFIFO_UDF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH2_INT_RAW_S  6
-
-/** GDMA_IN_INT_ST_CH2_REG register
- *  Masked interrupt of channel 0
- */
-#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24)
-/** GDMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH2_INT_ST    (BIT(0))
-#define GDMA_IN_DONE_CH2_INT_ST_M  (GDMA_IN_DONE_CH2_INT_ST_V << GDMA_IN_DONE_CH2_INT_ST_S)
-#define GDMA_IN_DONE_CH2_INT_ST_V  0x00000001U
-#define GDMA_IN_DONE_CH2_INT_ST_S  0
-/** GDMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH2_INT_ST_M  (GDMA_IN_SUC_EOF_CH2_INT_ST_V << GDMA_IN_SUC_EOF_CH2_INT_ST_S)
-#define GDMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH2_INT_ST_S  1
-/** GDMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH2_INT_ST_M  (GDMA_IN_ERR_EOF_CH2_INT_ST_V << GDMA_IN_ERR_EOF_CH2_INT_ST_S)
-#define GDMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH2_INT_ST_S  2
-/** GDMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M  (GDMA_IN_DSCR_ERR_CH2_INT_ST_V << GDMA_IN_DSCR_ERR_CH2_INT_ST_S)
-#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S  3
-/** GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S  4
-/** GDMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH2_INT_ST    (BIT(5))
-#define GDMA_INFIFO_OVF_CH2_INT_ST_M  (GDMA_INFIFO_OVF_CH2_INT_ST_V << GDMA_INFIFO_OVF_CH2_INT_ST_S)
-#define GDMA_INFIFO_OVF_CH2_INT_ST_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH2_INT_ST_S  5
-/** GDMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH2_INT_ST    (BIT(6))
-#define GDMA_INFIFO_UDF_CH2_INT_ST_M  (GDMA_INFIFO_UDF_CH2_INT_ST_V << GDMA_INFIFO_UDF_CH2_INT_ST_S)
-#define GDMA_INFIFO_UDF_CH2_INT_ST_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH2_INT_ST_S  6
-
-/** GDMA_IN_INT_ENA_CH2_REG register
- *  Interrupt enable bits of channel 0
- */
-#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28)
-/** GDMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH2_INT_ENA    (BIT(0))
-#define GDMA_IN_DONE_CH2_INT_ENA_M  (GDMA_IN_DONE_CH2_INT_ENA_V << GDMA_IN_DONE_CH2_INT_ENA_S)
-#define GDMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
-#define GDMA_IN_DONE_CH2_INT_ENA_S  0
-/** GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M  (GDMA_IN_SUC_EOF_CH2_INT_ENA_V << GDMA_IN_SUC_EOF_CH2_INT_ENA_S)
-#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S  1
-/** GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M  (GDMA_IN_ERR_EOF_CH2_INT_ENA_V << GDMA_IN_ERR_EOF_CH2_INT_ENA_S)
-#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S  2
-/** GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M  (GDMA_IN_DSCR_ERR_CH2_INT_ENA_V << GDMA_IN_DSCR_ERR_CH2_INT_ENA_S)
-#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
-/** GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  4
-/** GDMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH2_INT_ENA    (BIT(5))
-#define GDMA_INFIFO_OVF_CH2_INT_ENA_M  (GDMA_INFIFO_OVF_CH2_INT_ENA_V << GDMA_INFIFO_OVF_CH2_INT_ENA_S)
-#define GDMA_INFIFO_OVF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH2_INT_ENA_S  5
-/** GDMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH2_INT_ENA    (BIT(6))
-#define GDMA_INFIFO_UDF_CH2_INT_ENA_M  (GDMA_INFIFO_UDF_CH2_INT_ENA_V << GDMA_INFIFO_UDF_CH2_INT_ENA_S)
-#define GDMA_INFIFO_UDF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH2_INT_ENA_S  6
-
-/** GDMA_IN_INT_CLR_CH2_REG register
- *  Interrupt clear bits of channel 0
- */
-#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c)
-/** GDMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the IN_DONE_CH_INT interrupt.
- */
-#define GDMA_IN_DONE_CH2_INT_CLR    (BIT(0))
-#define GDMA_IN_DONE_CH2_INT_CLR_M  (GDMA_IN_DONE_CH2_INT_CLR_V << GDMA_IN_DONE_CH2_INT_CLR_S)
-#define GDMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
-#define GDMA_IN_DONE_CH2_INT_CLR_S  0
-/** GDMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
-#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M  (GDMA_IN_SUC_EOF_CH2_INT_CLR_V << GDMA_IN_SUC_EOF_CH2_INT_CLR_S)
-#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S  1
-/** GDMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
- */
-#define GDMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
-#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M  (GDMA_IN_ERR_EOF_CH2_INT_CLR_V << GDMA_IN_ERR_EOF_CH2_INT_CLR_S)
-#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S  2
-/** GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
-#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M  (GDMA_IN_DSCR_ERR_CH2_INT_CLR_V << GDMA_IN_DSCR_ERR_CH2_INT_CLR_S)
-#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
-#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
-/** GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
- */
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(4))
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
-#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  4
-/** GDMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_OVF_CH2_INT_CLR    (BIT(5))
-#define GDMA_INFIFO_OVF_CH2_INT_CLR_M  (GDMA_INFIFO_OVF_CH2_INT_CLR_V << GDMA_INFIFO_OVF_CH2_INT_CLR_S)
-#define GDMA_INFIFO_OVF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_INFIFO_OVF_CH2_INT_CLR_S  5
-/** GDMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_INFIFO_UDF_CH2_INT_CLR    (BIT(6))
-#define GDMA_INFIFO_UDF_CH2_INT_CLR_M  (GDMA_INFIFO_UDF_CH2_INT_CLR_V << GDMA_INFIFO_UDF_CH2_INT_CLR_S)
-#define GDMA_INFIFO_UDF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_INFIFO_UDF_CH2_INT_CLR_S  6
-
-/** GDMA_OUT_INT_RAW_CH0_REG register
- *  Raw status interrupt of channel 0
- */
-#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x30)
-/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one outlink
- *  descriptor has been transmitted to peripherals for Tx channel 0.
- */
-#define GDMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
-#define GDMA_OUT_DONE_CH0_INT_RAW_M  (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S)
-#define GDMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
-#define GDMA_OUT_DONE_CH0_INT_RAW_S  0
-/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one outlink
- *  descriptor has been read from memory for Tx channel 0.
- */
-#define GDMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
-#define GDMA_OUT_EOF_CH0_INT_RAW_M  (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S)
-#define GDMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_OUT_EOF_CH0_INT_RAW_S  1
-/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when detecting outlink descriptor error
- *  including owner error and the second and third word error of outlink descriptor for
- *  Tx channel 0.
- */
-#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
-#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
-/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt bit turns to high level when data corresponding a outlink
- *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
- *  channel 0.
- */
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
-/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
- *  overflow.
- */
-#define GDMA_OUTFIFO_OVF_CH0_INT_RAW    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M  (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S)
-#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S  4
-/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
- *  underflow.
- */
-#define GDMA_OUTFIFO_UDF_CH0_INT_RAW    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M  (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S)
-#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S  5
-
-/** GDMA_OUT_INT_ST_CH0_REG register
- *  Masked interrupt of channel 0
- */
-#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x34)
-/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH0_INT_ST    (BIT(0))
-#define GDMA_OUT_DONE_CH0_INT_ST_M  (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S)
-#define GDMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
-#define GDMA_OUT_DONE_CH0_INT_ST_S  0
-/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH0_INT_ST    (BIT(1))
-#define GDMA_OUT_EOF_CH0_INT_ST_M  (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S)
-#define GDMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
-#define GDMA_OUT_EOF_CH0_INT_ST_S  1
-/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M  (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S)
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
-/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
-/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M  (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S)
-#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S  4
-/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M  (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S)
-#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S  5
-
-/** GDMA_OUT_INT_ENA_CH0_REG register
- *  Interrupt enable bits of channel 0
- */
-#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x38)
-/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
-#define GDMA_OUT_DONE_CH0_INT_ENA_M  (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S)
-#define GDMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
-#define GDMA_OUT_DONE_CH0_INT_ENA_S  0
-/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
-#define GDMA_OUT_EOF_CH0_INT_ENA_M  (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S)
-#define GDMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_OUT_EOF_CH0_INT_ENA_S  1
-/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
-/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
-/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH0_INT_ENA    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M  (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S)
-#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S  4
-/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH0_INT_ENA    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M  (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S)
-#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S  5
-
-/** GDMA_OUT_INT_CLR_CH0_REG register
- *  Interrupt clear bits of channel 0
- */
-#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x3c)
-/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
-#define GDMA_OUT_DONE_CH0_INT_CLR_M  (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S)
-#define GDMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
-#define GDMA_OUT_DONE_CH0_INT_CLR_S  0
-/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
-#define GDMA_OUT_EOF_CH0_INT_CLR_M  (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S)
-#define GDMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_OUT_EOF_CH0_INT_CLR_S  1
-/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
-#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
-/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
-/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH0_INT_CLR    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M  (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S)
-#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S  4
-/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH0_INT_CLR    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M  (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S)
-#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S  5
-
-/** GDMA_OUT_INT_RAW_CH1_REG register
- *  Raw status interrupt of channel 0
- */
-#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x40)
-/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one outlink
- *  descriptor has been transmitted to peripherals for Tx channel 0.
- */
-#define GDMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
-#define GDMA_OUT_DONE_CH1_INT_RAW_M  (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S)
-#define GDMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
-#define GDMA_OUT_DONE_CH1_INT_RAW_S  0
-/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one outlink
- *  descriptor has been read from memory for Tx channel 0.
- */
-#define GDMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
-#define GDMA_OUT_EOF_CH1_INT_RAW_M  (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S)
-#define GDMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_OUT_EOF_CH1_INT_RAW_S  1
-/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when detecting outlink descriptor error
- *  including owner error and the second and third word error of outlink descriptor for
- *  Tx channel 0.
- */
-#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
-#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
-/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt bit turns to high level when data corresponding a outlink
- *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
- *  channel 0.
- */
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
-/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
- *  overflow.
- */
-#define GDMA_OUTFIFO_OVF_CH1_INT_RAW    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M  (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S)
-#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S  4
-/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
- *  underflow.
- */
-#define GDMA_OUTFIFO_UDF_CH1_INT_RAW    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M  (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S)
-#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S  5
-
-/** GDMA_OUT_INT_ST_CH1_REG register
- *  Masked interrupt of channel 0
- */
-#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x44)
-/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH1_INT_ST    (BIT(0))
-#define GDMA_OUT_DONE_CH1_INT_ST_M  (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S)
-#define GDMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
-#define GDMA_OUT_DONE_CH1_INT_ST_S  0
-/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH1_INT_ST    (BIT(1))
-#define GDMA_OUT_EOF_CH1_INT_ST_M  (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S)
-#define GDMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
-#define GDMA_OUT_EOF_CH1_INT_ST_S  1
-/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M  (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S)
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
-/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
-/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH1_INT_ST    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M  (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S)
-#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S  4
-/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH1_INT_ST    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M  (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S)
-#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S  5
-
-/** GDMA_OUT_INT_ENA_CH1_REG register
- *  Interrupt enable bits of channel 0
- */
-#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x48)
-/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
-#define GDMA_OUT_DONE_CH1_INT_ENA_M  (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S)
-#define GDMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
-#define GDMA_OUT_DONE_CH1_INT_ENA_S  0
-/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
-#define GDMA_OUT_EOF_CH1_INT_ENA_M  (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S)
-#define GDMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_OUT_EOF_CH1_INT_ENA_S  1
-/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
-/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
-/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH1_INT_ENA    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M  (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S)
-#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S  4
-/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH1_INT_ENA    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M  (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S)
-#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S  5
-
-/** GDMA_OUT_INT_CLR_CH1_REG register
- *  Interrupt clear bits of channel 0
- */
-#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x4c)
-/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
-#define GDMA_OUT_DONE_CH1_INT_CLR_M  (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S)
-#define GDMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
-#define GDMA_OUT_DONE_CH1_INT_CLR_S  0
-/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
-#define GDMA_OUT_EOF_CH1_INT_CLR_M  (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S)
-#define GDMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_OUT_EOF_CH1_INT_CLR_S  1
-/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
-#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
-/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
-/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH1_INT_CLR    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M  (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S)
-#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S  4
-/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH1_INT_CLR    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M  (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S)
-#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S  5
-
-/** GDMA_OUT_INT_RAW_CH2_REG register
- *  Raw status interrupt of channel 0
- */
-#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x50)
-/** GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one outlink
- *  descriptor has been transmitted to peripherals for Tx channel 0.
- */
-#define GDMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
-#define GDMA_OUT_DONE_CH2_INT_RAW_M  (GDMA_OUT_DONE_CH2_INT_RAW_V << GDMA_OUT_DONE_CH2_INT_RAW_S)
-#define GDMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
-#define GDMA_OUT_DONE_CH2_INT_RAW_S  0
-/** GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when the last data pointed by one outlink
- *  descriptor has been read from memory for Tx channel 0.
- */
-#define GDMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
-#define GDMA_OUT_EOF_CH2_INT_RAW_M  (GDMA_OUT_EOF_CH2_INT_RAW_V << GDMA_OUT_EOF_CH2_INT_RAW_S)
-#define GDMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_OUT_EOF_CH2_INT_RAW_S  1
-/** GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when detecting outlink descriptor error
- *  including owner error and the second and third word error of outlink descriptor for
- *  Tx channel 0.
- */
-#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
-#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
-/** GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt bit turns to high level when data corresponding a outlink
- *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
- *  channel 0.
- */
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
-/** GDMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
- *  overflow.
- */
-#define GDMA_OUTFIFO_OVF_CH2_INT_RAW    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_M  (GDMA_OUTFIFO_OVF_CH2_INT_RAW_V << GDMA_OUTFIFO_OVF_CH2_INT_RAW_S)
-#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_S  4
-/** GDMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
- *  underflow.
- */
-#define GDMA_OUTFIFO_UDF_CH2_INT_RAW    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_M  (GDMA_OUTFIFO_UDF_CH2_INT_RAW_V << GDMA_OUTFIFO_UDF_CH2_INT_RAW_S)
-#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_S  5
-
-/** GDMA_OUT_INT_ST_CH2_REG register
- *  Masked interrupt of channel 0
- */
-#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x54)
-/** GDMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH2_INT_ST    (BIT(0))
-#define GDMA_OUT_DONE_CH2_INT_ST_M  (GDMA_OUT_DONE_CH2_INT_ST_V << GDMA_OUT_DONE_CH2_INT_ST_S)
-#define GDMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
-#define GDMA_OUT_DONE_CH2_INT_ST_S  0
-/** GDMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH2_INT_ST    (BIT(1))
-#define GDMA_OUT_EOF_CH2_INT_ST_M  (GDMA_OUT_EOF_CH2_INT_ST_V << GDMA_OUT_EOF_CH2_INT_ST_S)
-#define GDMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
-#define GDMA_OUT_EOF_CH2_INT_ST_S  1
-/** GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M  (GDMA_OUT_DSCR_ERR_CH2_INT_ST_V << GDMA_OUT_DSCR_ERR_CH2_INT_ST_S)
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
-/** GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
-/** GDMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH2_INT_ST    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH2_INT_ST_M  (GDMA_OUTFIFO_OVF_CH2_INT_ST_V << GDMA_OUTFIFO_OVF_CH2_INT_ST_S)
-#define GDMA_OUTFIFO_OVF_CH2_INT_ST_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH2_INT_ST_S  4
-/** GDMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH2_INT_ST    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH2_INT_ST_M  (GDMA_OUTFIFO_UDF_CH2_INT_ST_V << GDMA_OUTFIFO_UDF_CH2_INT_ST_S)
-#define GDMA_OUTFIFO_UDF_CH2_INT_ST_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH2_INT_ST_S  5
-
-/** GDMA_OUT_INT_ENA_CH2_REG register
- *  Interrupt enable bits of channel 0
- */
-#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x58)
-/** GDMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
-#define GDMA_OUT_DONE_CH2_INT_ENA_M  (GDMA_OUT_DONE_CH2_INT_ENA_V << GDMA_OUT_DONE_CH2_INT_ENA_S)
-#define GDMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
-#define GDMA_OUT_DONE_CH2_INT_ENA_S  0
-/** GDMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
-#define GDMA_OUT_EOF_CH2_INT_ENA_M  (GDMA_OUT_EOF_CH2_INT_ENA_V << GDMA_OUT_EOF_CH2_INT_ENA_S)
-#define GDMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_OUT_EOF_CH2_INT_ENA_S  1
-/** GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
-/** GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
-/** GDMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH2_INT_ENA    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_M  (GDMA_OUTFIFO_OVF_CH2_INT_ENA_V << GDMA_OUTFIFO_OVF_CH2_INT_ENA_S)
-#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_S  4
-/** GDMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH2_INT_ENA    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_M  (GDMA_OUTFIFO_UDF_CH2_INT_ENA_V << GDMA_OUTFIFO_UDF_CH2_INT_ENA_S)
-#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_S  5
-
-/** GDMA_OUT_INT_CLR_CH2_REG register
- *  Interrupt clear bits of channel 0
- */
-#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x5c)
-/** GDMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
- */
-#define GDMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
-#define GDMA_OUT_DONE_CH2_INT_CLR_M  (GDMA_OUT_DONE_CH2_INT_CLR_V << GDMA_OUT_DONE_CH2_INT_CLR_S)
-#define GDMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
-#define GDMA_OUT_DONE_CH2_INT_CLR_S  0
-/** GDMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
-#define GDMA_OUT_EOF_CH2_INT_CLR_M  (GDMA_OUT_EOF_CH2_INT_CLR_V << GDMA_OUT_EOF_CH2_INT_CLR_S)
-#define GDMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_OUT_EOF_CH2_INT_CLR_S  1
-/** GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
- */
-#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
-#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
-#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
-#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
-/** GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
- */
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
-/** GDMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_OVF_CH2_INT_CLR    (BIT(4))
-#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_M  (GDMA_OUTFIFO_OVF_CH2_INT_CLR_V << GDMA_OUTFIFO_OVF_CH2_INT_CLR_S)
-#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_S  4
-/** GDMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
- */
-#define GDMA_OUTFIFO_UDF_CH2_INT_CLR    (BIT(5))
-#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_M  (GDMA_OUTFIFO_UDF_CH2_INT_CLR_V << GDMA_OUTFIFO_UDF_CH2_INT_CLR_S)
-#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_V  0x00000001U
-#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_S  5
-
-/** GDMA_AHB_TEST_REG register
- *  reserved
- */
-#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x60)
-/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
- *  reserved
- */
-#define GDMA_AHB_TESTMODE    0x00000007U
-#define GDMA_AHB_TESTMODE_M  (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S)
-#define GDMA_AHB_TESTMODE_V  0x00000007U
-#define GDMA_AHB_TESTMODE_S  0
-/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
- *  reserved
- */
-#define GDMA_AHB_TESTADDR    0x00000003U
-#define GDMA_AHB_TESTADDR_M  (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S)
-#define GDMA_AHB_TESTADDR_V  0x00000003U
-#define GDMA_AHB_TESTADDR_S  4
-
-/** GDMA_MISC_CONF_REG register
- *  MISC register
- */
-#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x64)
-/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0;
- *  Set this bit then clear this bit to reset the internal ahb FSM.
- */
-#define GDMA_AHBM_RST_INTER    (BIT(0))
-#define GDMA_AHBM_RST_INTER_M  (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S)
-#define GDMA_AHBM_RST_INTER_V  0x00000001U
-#define GDMA_AHBM_RST_INTER_S  0
-/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable priority arbitration function.
- */
-#define GDMA_ARB_PRI_DIS    (BIT(2))
-#define GDMA_ARB_PRI_DIS_M  (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S)
-#define GDMA_ARB_PRI_DIS_V  0x00000001U
-#define GDMA_ARB_PRI_DIS_S  2
-/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define GDMA_CLK_EN    (BIT(3))
-#define GDMA_CLK_EN_M  (GDMA_CLK_EN_V << GDMA_CLK_EN_S)
-#define GDMA_CLK_EN_V  0x00000001U
-#define GDMA_CLK_EN_S  3
-
-/** GDMA_DATE_REG register
- *  Version control register
- */
-#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x68)
-/** GDMA_DATE : R/W; bitpos: [31:0]; default: 36720912;
- *  register version.
- */
-#define GDMA_DATE    0xFFFFFFFFU
-#define GDMA_DATE_M  (GDMA_DATE_V << GDMA_DATE_S)
-#define GDMA_DATE_V  0xFFFFFFFFU
-#define GDMA_DATE_S  0
-
-/** GDMA_IN_CONF0_CH0_REG register
- *  Configure 0 register of Rx channel 0
- */
-#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70)
-/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
- *  This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
- */
-#define GDMA_IN_RST_CH0    (BIT(0))
-#define GDMA_IN_RST_CH0_M  (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S)
-#define GDMA_IN_RST_CH0_V  0x00000001U
-#define GDMA_IN_RST_CH0_S  0
-/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define GDMA_IN_LOOP_TEST_CH0    (BIT(1))
-#define GDMA_IN_LOOP_TEST_CH0_M  (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S)
-#define GDMA_IN_LOOP_TEST_CH0_V  0x00000001U
-#define GDMA_IN_LOOP_TEST_CH0_S  1
-/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
- *  descriptor when accessing internal SRAM.
- */
-#define GDMA_INDSCR_BURST_EN_CH0    (BIT(2))
-#define GDMA_INDSCR_BURST_EN_CH0_M  (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S)
-#define GDMA_INDSCR_BURST_EN_CH0_V  0x00000001U
-#define GDMA_INDSCR_BURST_EN_CH0_S  2
-/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
- *  when accessing internal SRAM.
- */
-#define GDMA_IN_DATA_BURST_EN_CH0    (BIT(3))
-#define GDMA_IN_DATA_BURST_EN_CH0_M  (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S)
-#define GDMA_IN_DATA_BURST_EN_CH0_V  0x00000001U
-#define GDMA_IN_DATA_BURST_EN_CH0_S  3
-/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0;
- *  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
- */
-#define GDMA_MEM_TRANS_EN_CH0    (BIT(4))
-#define GDMA_MEM_TRANS_EN_CH0_M  (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S)
-#define GDMA_MEM_TRANS_EN_CH0_V  0x00000001U
-#define GDMA_MEM_TRANS_EN_CH0_S  4
-/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0;
- *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
- *  task.
- */
-#define GDMA_IN_ETM_EN_CH0    (BIT(5))
-#define GDMA_IN_ETM_EN_CH0_M  (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S)
-#define GDMA_IN_ETM_EN_CH0_V  0x00000001U
-#define GDMA_IN_ETM_EN_CH0_S  5
-
-/** GDMA_IN_CONF1_CH0_REG register
- *  Configure 1 register of Rx channel 0
- */
-#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74)
-/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable checking the owner attribute of the link descriptor.
- */
-#define GDMA_IN_CHECK_OWNER_CH0    (BIT(12))
-#define GDMA_IN_CHECK_OWNER_CH0_M  (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S)
-#define GDMA_IN_CHECK_OWNER_CH0_V  0x00000001U
-#define GDMA_IN_CHECK_OWNER_CH0_S  12
-
-/** GDMA_INFIFO_STATUS_CH0_REG register
- *  Receive FIFO status of Rx channel 0
- */
-#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78)
-/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1;
- *  L1 Rx FIFO full signal for Rx channel 0.
- */
-#define GDMA_INFIFO_FULL_CH0    (BIT(0))
-#define GDMA_INFIFO_FULL_CH0_M  (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S)
-#define GDMA_INFIFO_FULL_CH0_V  0x00000001U
-#define GDMA_INFIFO_FULL_CH0_S  0
-/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
- *  L1 Rx FIFO empty signal for Rx channel 0.
- */
-#define GDMA_INFIFO_EMPTY_CH0    (BIT(1))
-#define GDMA_INFIFO_EMPTY_CH0_M  (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S)
-#define GDMA_INFIFO_EMPTY_CH0_V  0x00000001U
-#define GDMA_INFIFO_EMPTY_CH0_S  1
-/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
- *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
- */
-#define GDMA_INFIFO_CNT_CH0    0x0000003FU
-#define GDMA_INFIFO_CNT_CH0_M  (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S)
-#define GDMA_INFIFO_CNT_CH0_V  0x0000003FU
-#define GDMA_INFIFO_CNT_CH0_S  2
-/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
-#define GDMA_IN_REMAIN_UNDER_1B_CH0_M  (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S)
-#define GDMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_1B_CH0_S  23
-/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
-#define GDMA_IN_REMAIN_UNDER_2B_CH0_M  (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S)
-#define GDMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_2B_CH0_S  24
-/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
-#define GDMA_IN_REMAIN_UNDER_3B_CH0_M  (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S)
-#define GDMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_3B_CH0_S  25
-/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
-#define GDMA_IN_REMAIN_UNDER_4B_CH0_M  (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S)
-#define GDMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_4B_CH0_S  26
-/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define GDMA_IN_BUF_HUNGRY_CH0    (BIT(27))
-#define GDMA_IN_BUF_HUNGRY_CH0_M  (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S)
-#define GDMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
-#define GDMA_IN_BUF_HUNGRY_CH0_S  27
-
-/** GDMA_IN_POP_CH0_REG register
- *  Pop control register of Rx channel 0
- */
-#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c)
-/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
- *  This register stores the data popping from DMA FIFO.
- */
-#define GDMA_INFIFO_RDATA_CH0    0x00000FFFU
-#define GDMA_INFIFO_RDATA_CH0_M  (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S)
-#define GDMA_INFIFO_RDATA_CH0_V  0x00000FFFU
-#define GDMA_INFIFO_RDATA_CH0_S  0
-/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0;
- *  Set this bit to pop data from DMA FIFO.
- */
-#define GDMA_INFIFO_POP_CH0    (BIT(12))
-#define GDMA_INFIFO_POP_CH0_M  (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S)
-#define GDMA_INFIFO_POP_CH0_V  0x00000001U
-#define GDMA_INFIFO_POP_CH0_S  12
-
-/** GDMA_IN_LINK_CH0_REG register
- *  Link descriptor configure and control register of Rx channel 0
- */
-#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80)
-/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0;
- *  This register stores the 20 least significant bits of the first inlink descriptor's
- *  address.
- */
-#define GDMA_INLINK_ADDR_CH0    0x000FFFFFU
-#define GDMA_INLINK_ADDR_CH0_M  (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S)
-#define GDMA_INLINK_ADDR_CH0_V  0x000FFFFFU
-#define GDMA_INLINK_ADDR_CH0_S  0
-/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
- *  Set this bit to return to current inlink descriptor's address when there are some
- *  errors in current receiving data.
- */
-#define GDMA_INLINK_AUTO_RET_CH0    (BIT(20))
-#define GDMA_INLINK_AUTO_RET_CH0_M  (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S)
-#define GDMA_INLINK_AUTO_RET_CH0_V  0x00000001U
-#define GDMA_INLINK_AUTO_RET_CH0_S  20
-/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [21]; default: 0;
- *  Set this bit to stop dealing with the inlink descriptors.
- */
-#define GDMA_INLINK_STOP_CH0    (BIT(21))
-#define GDMA_INLINK_STOP_CH0_M  (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S)
-#define GDMA_INLINK_STOP_CH0_V  0x00000001U
-#define GDMA_INLINK_STOP_CH0_S  21
-/** GDMA_INLINK_START_CH0 : WT; bitpos: [22]; default: 0;
- *  Set this bit to start dealing with the inlink descriptors.
- */
-#define GDMA_INLINK_START_CH0    (BIT(22))
-#define GDMA_INLINK_START_CH0_M  (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S)
-#define GDMA_INLINK_START_CH0_V  0x00000001U
-#define GDMA_INLINK_START_CH0_S  22
-/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [23]; default: 0;
- *  Set this bit to mount a new inlink descriptor.
- */
-#define GDMA_INLINK_RESTART_CH0    (BIT(23))
-#define GDMA_INLINK_RESTART_CH0_M  (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S)
-#define GDMA_INLINK_RESTART_CH0_V  0x00000001U
-#define GDMA_INLINK_RESTART_CH0_S  23
-/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
- *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
- *  working.
- */
-#define GDMA_INLINK_PARK_CH0    (BIT(24))
-#define GDMA_INLINK_PARK_CH0_M  (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S)
-#define GDMA_INLINK_PARK_CH0_V  0x00000001U
-#define GDMA_INLINK_PARK_CH0_S  24
-
-/** GDMA_IN_STATE_CH0_REG register
- *  Receive status of Rx channel 0
- */
-#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84)
-/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
- *  This register stores the current inlink descriptor's address.
- */
-#define GDMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
-#define GDMA_INLINK_DSCR_ADDR_CH0_M  (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S)
-#define GDMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
-#define GDMA_INLINK_DSCR_ADDR_CH0_S  0
-/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
- *  reserved
- */
-#define GDMA_IN_DSCR_STATE_CH0    0x00000003U
-#define GDMA_IN_DSCR_STATE_CH0_M  (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S)
-#define GDMA_IN_DSCR_STATE_CH0_V  0x00000003U
-#define GDMA_IN_DSCR_STATE_CH0_S  18
-/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
- *  reserved
- */
-#define GDMA_IN_STATE_CH0    0x00000007U
-#define GDMA_IN_STATE_CH0_M  (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S)
-#define GDMA_IN_STATE_CH0_V  0x00000007U
-#define GDMA_IN_STATE_CH0_S  20
-
-/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
- *  Inlink descriptor address when EOF occurs of Rx channel 0
- */
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88)
-/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the inlink descriptor when the EOF bit in this
- *  descriptor is 1.
- */
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M  (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S)
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
-
-/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
- *  Inlink descriptor address when errors occur of Rx channel 0
- */
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c)
-/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the inlink descriptor when there are some
- *  errors in current receiving data. Only used when peripheral is UHCI0.
- */
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M  (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S)
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
-
-/** GDMA_IN_DSCR_CH0_REG register
- *  Current inlink descriptor address of Rx channel 0
- */
-#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90)
-/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
- *  The address of the current inlink descriptor x.
- */
-#define GDMA_INLINK_DSCR_CH0    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_CH0_M  (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S)
-#define GDMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_CH0_S  0
-
-/** GDMA_IN_DSCR_BF0_CH0_REG register
- *  The last inlink descriptor address of Rx channel 0
- */
-#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94)
-/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
- *  The address of the last inlink descriptor x-1.
- */
-#define GDMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF0_CH0_M  (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S)
-#define GDMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF0_CH0_S  0
-
-/** GDMA_IN_DSCR_BF1_CH0_REG register
- *  The second-to-last inlink descriptor address of Rx channel 0
- */
-#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98)
-/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
- *  The address of the second-to-last inlink descriptor x-2.
- */
-#define GDMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF1_CH0_M  (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S)
-#define GDMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF1_CH0_S  0
-
-/** GDMA_IN_PRI_CH0_REG register
- *  Priority register of Rx channel 0
- */
-#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c)
-/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
- *  The priority of Rx channel 0. The larger of the value the higher of the priority.
- */
-#define GDMA_RX_PRI_CH0    0x0000000FU
-#define GDMA_RX_PRI_CH0_M  (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S)
-#define GDMA_RX_PRI_CH0_V  0x0000000FU
-#define GDMA_RX_PRI_CH0_S  0
-
-/** GDMA_IN_PERI_SEL_CH0_REG register
- *  Peripheral selection of Rx channel 0
- */
-#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0)
-/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
- *  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2:
- *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
- *  10~15: Dummy
- */
-#define GDMA_PERI_IN_SEL_CH0    0x0000003FU
-#define GDMA_PERI_IN_SEL_CH0_M  (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S)
-#define GDMA_PERI_IN_SEL_CH0_V  0x0000003FU
-#define GDMA_PERI_IN_SEL_CH0_S  0
-
-/** GDMA_OUT_CONF0_CH0_REG register
- *  Configure 0 register of Tx channel 0
- */
-#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0)
-/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
- *  This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
- */
-#define GDMA_OUT_RST_CH0    (BIT(0))
-#define GDMA_OUT_RST_CH0_M  (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S)
-#define GDMA_OUT_RST_CH0_V  0x00000001U
-#define GDMA_OUT_RST_CH0_S  0
-/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_LOOP_TEST_CH0    (BIT(1))
-#define GDMA_OUT_LOOP_TEST_CH0_M  (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S)
-#define GDMA_OUT_LOOP_TEST_CH0_V  0x00000001U
-#define GDMA_OUT_LOOP_TEST_CH0_S  1
-/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
- *  has been transmitted.
- */
-#define GDMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
-#define GDMA_OUT_AUTO_WRBACK_CH0_M  (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S)
-#define GDMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
-#define GDMA_OUT_AUTO_WRBACK_CH0_S  2
-/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
- *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
- *  generated when data need to transmit has been popped from FIFO in DMA
- */
-#define GDMA_OUT_EOF_MODE_CH0    (BIT(3))
-#define GDMA_OUT_EOF_MODE_CH0_M  (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S)
-#define GDMA_OUT_EOF_MODE_CH0_V  0x00000001U
-#define GDMA_OUT_EOF_MODE_CH0_S  3
-/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
- *  descriptor when accessing internal SRAM.
- */
-#define GDMA_OUTDSCR_BURST_EN_CH0    (BIT(4))
-#define GDMA_OUTDSCR_BURST_EN_CH0_M  (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S)
-#define GDMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
-#define GDMA_OUTDSCR_BURST_EN_CH0_S  4
-/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data
- *  when accessing internal SRAM.
- */
-#define GDMA_OUT_DATA_BURST_EN_CH0    (BIT(5))
-#define GDMA_OUT_DATA_BURST_EN_CH0_M  (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S)
-#define GDMA_OUT_DATA_BURST_EN_CH0_V  0x00000001U
-#define GDMA_OUT_DATA_BURST_EN_CH0_S  5
-/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0;
- *  Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm
- *  task.
- */
-#define GDMA_OUT_ETM_EN_CH0    (BIT(6))
-#define GDMA_OUT_ETM_EN_CH0_M  (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S)
-#define GDMA_OUT_ETM_EN_CH0_V  0x00000001U
-#define GDMA_OUT_ETM_EN_CH0_S  6
-
-/** GDMA_OUT_CONF1_CH0_REG register
- *  Configure 1 register of Tx channel 0
- */
-#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4)
-/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable checking the owner attribute of the link descriptor.
- */
-#define GDMA_OUT_CHECK_OWNER_CH0    (BIT(12))
-#define GDMA_OUT_CHECK_OWNER_CH0_M  (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S)
-#define GDMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
-#define GDMA_OUT_CHECK_OWNER_CH0_S  12
-
-/** GDMA_OUTFIFO_STATUS_CH0_REG register
- *  Transmit FIFO status of Tx channel 0
- */
-#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8)
-/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0;
- *  L1 Tx FIFO full signal for Tx channel 0.
- */
-#define GDMA_OUTFIFO_FULL_CH0    (BIT(0))
-#define GDMA_OUTFIFO_FULL_CH0_M  (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S)
-#define GDMA_OUTFIFO_FULL_CH0_V  0x00000001U
-#define GDMA_OUTFIFO_FULL_CH0_S  0
-/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
- *  L1 Tx FIFO empty signal for Tx channel 0.
- */
-#define GDMA_OUTFIFO_EMPTY_CH0    (BIT(1))
-#define GDMA_OUTFIFO_EMPTY_CH0_M  (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S)
-#define GDMA_OUTFIFO_EMPTY_CH0_V  0x00000001U
-#define GDMA_OUTFIFO_EMPTY_CH0_S  1
-/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
- *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
- */
-#define GDMA_OUTFIFO_CNT_CH0    0x0000003FU
-#define GDMA_OUTFIFO_CNT_CH0_M  (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S)
-#define GDMA_OUTFIFO_CNT_CH0_V  0x0000003FU
-#define GDMA_OUTFIFO_CNT_CH0_S  2
-/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
-#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M  (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S)
-#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S  23
-/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
-#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M  (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S)
-#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S  24
-/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
-#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M  (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S)
-#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S  25
-/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
-#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M  (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S)
-#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S  26
-
-/** GDMA_OUT_PUSH_CH0_REG register
- *  Push control register of Rx channel 0
- */
-#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc)
-/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
- *  This register stores the data that need to be pushed into DMA FIFO.
- */
-#define GDMA_OUTFIFO_WDATA_CH0    0x000001FFU
-#define GDMA_OUTFIFO_WDATA_CH0_M  (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S)
-#define GDMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
-#define GDMA_OUTFIFO_WDATA_CH0_S  0
-/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0;
- *  Set this bit to push data into DMA FIFO.
- */
-#define GDMA_OUTFIFO_PUSH_CH0    (BIT(9))
-#define GDMA_OUTFIFO_PUSH_CH0_M  (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S)
-#define GDMA_OUTFIFO_PUSH_CH0_V  0x00000001U
-#define GDMA_OUTFIFO_PUSH_CH0_S  9
-
-/** GDMA_OUT_LINK_CH0_REG register
- *  Link descriptor configure and control register of Tx channel 0
- */
-#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0)
-/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0;
- *  This register stores the 20 least significant bits of the first outlink
- *  descriptor's address.
- */
-#define GDMA_OUTLINK_ADDR_CH0    0x000FFFFFU
-#define GDMA_OUTLINK_ADDR_CH0_M  (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S)
-#define GDMA_OUTLINK_ADDR_CH0_V  0x000FFFFFU
-#define GDMA_OUTLINK_ADDR_CH0_S  0
-/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [20]; default: 0;
- *  Set this bit to stop dealing with the outlink descriptors.
- */
-#define GDMA_OUTLINK_STOP_CH0    (BIT(20))
-#define GDMA_OUTLINK_STOP_CH0_M  (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S)
-#define GDMA_OUTLINK_STOP_CH0_V  0x00000001U
-#define GDMA_OUTLINK_STOP_CH0_S  20
-/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [21]; default: 0;
- *  Set this bit to start dealing with the outlink descriptors.
- */
-#define GDMA_OUTLINK_START_CH0    (BIT(21))
-#define GDMA_OUTLINK_START_CH0_M  (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S)
-#define GDMA_OUTLINK_START_CH0_V  0x00000001U
-#define GDMA_OUTLINK_START_CH0_S  21
-/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [22]; default: 0;
- *  Set this bit to restart a new outlink from the last address.
- */
-#define GDMA_OUTLINK_RESTART_CH0    (BIT(22))
-#define GDMA_OUTLINK_RESTART_CH0_M  (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S)
-#define GDMA_OUTLINK_RESTART_CH0_V  0x00000001U
-#define GDMA_OUTLINK_RESTART_CH0_S  22
-/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
- *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
- *  is working.
- */
-#define GDMA_OUTLINK_PARK_CH0    (BIT(23))
-#define GDMA_OUTLINK_PARK_CH0_M  (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S)
-#define GDMA_OUTLINK_PARK_CH0_V  0x00000001U
-#define GDMA_OUTLINK_PARK_CH0_S  23
-
-/** GDMA_OUT_STATE_CH0_REG register
- *  Transmit status of Tx channel 0
- */
-#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4)
-/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
- *  This register stores the current outlink descriptor's address.
- */
-#define GDMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
-#define GDMA_OUTLINK_DSCR_ADDR_CH0_M  (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S)
-#define GDMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
-#define GDMA_OUTLINK_DSCR_ADDR_CH0_S  0
-/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_DSCR_STATE_CH0    0x00000003U
-#define GDMA_OUT_DSCR_STATE_CH0_M  (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S)
-#define GDMA_OUT_DSCR_STATE_CH0_V  0x00000003U
-#define GDMA_OUT_DSCR_STATE_CH0_S  18
-/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_STATE_CH0    0x00000007U
-#define GDMA_OUT_STATE_CH0_M  (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S)
-#define GDMA_OUT_STATE_CH0_V  0x00000007U
-#define GDMA_OUT_STATE_CH0_S  20
-
-/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register
- *  Outlink descriptor address when EOF occurs of Tx channel 0
- */
-#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8)
-/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the outlink descriptor when the EOF bit in this
- *  descriptor is 1.
- */
-#define GDMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
-#define GDMA_OUT_EOF_DES_ADDR_CH0_M  (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S)
-#define GDMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
-#define GDMA_OUT_EOF_DES_ADDR_CH0_S  0
-
-/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
- *  The last outlink descriptor address when EOF occurs of Tx channel 0
- */
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec)
-/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the outlink descriptor before the last outlink
- *  descriptor.
- */
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
-
-/** GDMA_OUT_DSCR_CH0_REG register
- *  Current inlink descriptor address of Tx channel 0
- */
-#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0)
-/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
- *  The address of the current outlink descriptor y.
- */
-#define GDMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_CH0_M  (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S)
-#define GDMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_CH0_S  0
-
-/** GDMA_OUT_DSCR_BF0_CH0_REG register
- *  The last inlink descriptor address of Tx channel 0
- */
-#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4)
-/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
- *  The address of the last outlink descriptor y-1.
- */
-#define GDMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF0_CH0_M  (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S)
-#define GDMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF0_CH0_S  0
-
-/** GDMA_OUT_DSCR_BF1_CH0_REG register
- *  The second-to-last inlink descriptor address of Tx channel 0
- */
-#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8)
-/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
- *  The address of the second-to-last inlink descriptor x-2.
- */
-#define GDMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF1_CH0_M  (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S)
-#define GDMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF1_CH0_S  0
-
-/** GDMA_OUT_PRI_CH0_REG register
- *  Priority register of Tx channel 0.
- */
-#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc)
-/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
- *  The priority of Tx channel 0. The larger of the value the higher of the priority.
- */
-#define GDMA_TX_PRI_CH0    0x0000000FU
-#define GDMA_TX_PRI_CH0_M  (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S)
-#define GDMA_TX_PRI_CH0_V  0x0000000FU
-#define GDMA_TX_PRI_CH0_S  0
-
-/** GDMA_OUT_PERI_SEL_CH0_REG register
- *  Peripheral selection of Tx channel 0
- */
-#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100)
-/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
- *  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2:
- *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
- *  10~15: Dummy
- */
-#define GDMA_PERI_OUT_SEL_CH0    0x0000003FU
-#define GDMA_PERI_OUT_SEL_CH0_M  (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S)
-#define GDMA_PERI_OUT_SEL_CH0_V  0x0000003FU
-#define GDMA_PERI_OUT_SEL_CH0_S  0
-
-/** GDMA_IN_CONF0_CH1_REG register
- *  Configure 0 register of Rx channel 1
- */
-#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130)
-/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
- *  This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
- */
-#define GDMA_IN_RST_CH1    (BIT(0))
-#define GDMA_IN_RST_CH1_M  (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S)
-#define GDMA_IN_RST_CH1_V  0x00000001U
-#define GDMA_IN_RST_CH1_S  0
-/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define GDMA_IN_LOOP_TEST_CH1    (BIT(1))
-#define GDMA_IN_LOOP_TEST_CH1_M  (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S)
-#define GDMA_IN_LOOP_TEST_CH1_V  0x00000001U
-#define GDMA_IN_LOOP_TEST_CH1_S  1
-/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link
- *  descriptor when accessing internal SRAM.
- */
-#define GDMA_INDSCR_BURST_EN_CH1    (BIT(2))
-#define GDMA_INDSCR_BURST_EN_CH1_M  (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S)
-#define GDMA_INDSCR_BURST_EN_CH1_V  0x00000001U
-#define GDMA_INDSCR_BURST_EN_CH1_S  2
-/** GDMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data
- *  when accessing internal SRAM.
- */
-#define GDMA_IN_DATA_BURST_EN_CH1    (BIT(3))
-#define GDMA_IN_DATA_BURST_EN_CH1_M  (GDMA_IN_DATA_BURST_EN_CH1_V << GDMA_IN_DATA_BURST_EN_CH1_S)
-#define GDMA_IN_DATA_BURST_EN_CH1_V  0x00000001U
-#define GDMA_IN_DATA_BURST_EN_CH1_S  3
-/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0;
- *  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
- */
-#define GDMA_MEM_TRANS_EN_CH1    (BIT(4))
-#define GDMA_MEM_TRANS_EN_CH1_M  (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S)
-#define GDMA_MEM_TRANS_EN_CH1_V  0x00000001U
-#define GDMA_MEM_TRANS_EN_CH1_S  4
-/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0;
- *  Set this bit to 1 to enable etm control mode, dma Rx channel 1 is triggered by etm
- *  task.
- */
-#define GDMA_IN_ETM_EN_CH1    (BIT(5))
-#define GDMA_IN_ETM_EN_CH1_M  (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S)
-#define GDMA_IN_ETM_EN_CH1_V  0x00000001U
-#define GDMA_IN_ETM_EN_CH1_S  5
-
-/** GDMA_IN_CONF1_CH1_REG register
- *  Configure 1 register of Rx channel 1
- */
-#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134)
-/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable checking the owner attribute of the link descriptor.
- */
-#define GDMA_IN_CHECK_OWNER_CH1    (BIT(12))
-#define GDMA_IN_CHECK_OWNER_CH1_M  (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S)
-#define GDMA_IN_CHECK_OWNER_CH1_V  0x00000001U
-#define GDMA_IN_CHECK_OWNER_CH1_S  12
-
-/** GDMA_INFIFO_STATUS_CH1_REG register
- *  Receive FIFO status of Rx channel 1
- */
-#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138)
-/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1;
- *  L1 Rx FIFO full signal for Rx channel 1.
- */
-#define GDMA_INFIFO_FULL_CH1    (BIT(0))
-#define GDMA_INFIFO_FULL_CH1_M  (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S)
-#define GDMA_INFIFO_FULL_CH1_V  0x00000001U
-#define GDMA_INFIFO_FULL_CH1_S  0
-/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
- *  L1 Rx FIFO empty signal for Rx channel 1.
- */
-#define GDMA_INFIFO_EMPTY_CH1    (BIT(1))
-#define GDMA_INFIFO_EMPTY_CH1_M  (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S)
-#define GDMA_INFIFO_EMPTY_CH1_V  0x00000001U
-#define GDMA_INFIFO_EMPTY_CH1_S  1
-/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
- *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
- */
-#define GDMA_INFIFO_CNT_CH1    0x0000003FU
-#define GDMA_INFIFO_CNT_CH1_M  (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S)
-#define GDMA_INFIFO_CNT_CH1_V  0x0000003FU
-#define GDMA_INFIFO_CNT_CH1_S  2
-/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_1B_CH1    (BIT(23))
-#define GDMA_IN_REMAIN_UNDER_1B_CH1_M  (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S)
-#define GDMA_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_1B_CH1_S  23
-/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_2B_CH1    (BIT(24))
-#define GDMA_IN_REMAIN_UNDER_2B_CH1_M  (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S)
-#define GDMA_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_2B_CH1_S  24
-/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_3B_CH1    (BIT(25))
-#define GDMA_IN_REMAIN_UNDER_3B_CH1_M  (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S)
-#define GDMA_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_3B_CH1_S  25
-/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_4B_CH1    (BIT(26))
-#define GDMA_IN_REMAIN_UNDER_4B_CH1_M  (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S)
-#define GDMA_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_4B_CH1_S  26
-/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define GDMA_IN_BUF_HUNGRY_CH1    (BIT(27))
-#define GDMA_IN_BUF_HUNGRY_CH1_M  (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S)
-#define GDMA_IN_BUF_HUNGRY_CH1_V  0x00000001U
-#define GDMA_IN_BUF_HUNGRY_CH1_S  27
-
-/** GDMA_IN_POP_CH1_REG register
- *  Pop control register of Rx channel 1
- */
-#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c)
-/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
- *  This register stores the data popping from DMA FIFO.
- */
-#define GDMA_INFIFO_RDATA_CH1    0x00000FFFU
-#define GDMA_INFIFO_RDATA_CH1_M  (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S)
-#define GDMA_INFIFO_RDATA_CH1_V  0x00000FFFU
-#define GDMA_INFIFO_RDATA_CH1_S  0
-/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0;
- *  Set this bit to pop data from DMA FIFO.
- */
-#define GDMA_INFIFO_POP_CH1    (BIT(12))
-#define GDMA_INFIFO_POP_CH1_M  (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S)
-#define GDMA_INFIFO_POP_CH1_V  0x00000001U
-#define GDMA_INFIFO_POP_CH1_S  12
-
-/** GDMA_IN_LINK_CH1_REG register
- *  Link descriptor configure and control register of Rx channel 1
- */
-#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140)
-/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0;
- *  This register stores the 20 least significant bits of the first inlink descriptor's
- *  address.
- */
-#define GDMA_INLINK_ADDR_CH1    0x000FFFFFU
-#define GDMA_INLINK_ADDR_CH1_M  (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S)
-#define GDMA_INLINK_ADDR_CH1_V  0x000FFFFFU
-#define GDMA_INLINK_ADDR_CH1_S  0
-/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
- *  Set this bit to return to current inlink descriptor's address when there are some
- *  errors in current receiving data.
- */
-#define GDMA_INLINK_AUTO_RET_CH1    (BIT(20))
-#define GDMA_INLINK_AUTO_RET_CH1_M  (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S)
-#define GDMA_INLINK_AUTO_RET_CH1_V  0x00000001U
-#define GDMA_INLINK_AUTO_RET_CH1_S  20
-/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [21]; default: 0;
- *  Set this bit to stop dealing with the inlink descriptors.
- */
-#define GDMA_INLINK_STOP_CH1    (BIT(21))
-#define GDMA_INLINK_STOP_CH1_M  (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S)
-#define GDMA_INLINK_STOP_CH1_V  0x00000001U
-#define GDMA_INLINK_STOP_CH1_S  21
-/** GDMA_INLINK_START_CH1 : WT; bitpos: [22]; default: 0;
- *  Set this bit to start dealing with the inlink descriptors.
- */
-#define GDMA_INLINK_START_CH1    (BIT(22))
-#define GDMA_INLINK_START_CH1_M  (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S)
-#define GDMA_INLINK_START_CH1_V  0x00000001U
-#define GDMA_INLINK_START_CH1_S  22
-/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [23]; default: 0;
- *  Set this bit to mount a new inlink descriptor.
- */
-#define GDMA_INLINK_RESTART_CH1    (BIT(23))
-#define GDMA_INLINK_RESTART_CH1_M  (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S)
-#define GDMA_INLINK_RESTART_CH1_V  0x00000001U
-#define GDMA_INLINK_RESTART_CH1_S  23
-/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
- *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
- *  working.
- */
-#define GDMA_INLINK_PARK_CH1    (BIT(24))
-#define GDMA_INLINK_PARK_CH1_M  (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S)
-#define GDMA_INLINK_PARK_CH1_V  0x00000001U
-#define GDMA_INLINK_PARK_CH1_S  24
-
-/** GDMA_IN_STATE_CH1_REG register
- *  Receive status of Rx channel 1
- */
-#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144)
-/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
- *  This register stores the current inlink descriptor's address.
- */
-#define GDMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
-#define GDMA_INLINK_DSCR_ADDR_CH1_M  (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S)
-#define GDMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
-#define GDMA_INLINK_DSCR_ADDR_CH1_S  0
-/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
- *  reserved
- */
-#define GDMA_IN_DSCR_STATE_CH1    0x00000003U
-#define GDMA_IN_DSCR_STATE_CH1_M  (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S)
-#define GDMA_IN_DSCR_STATE_CH1_V  0x00000003U
-#define GDMA_IN_DSCR_STATE_CH1_S  18
-/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
- *  reserved
- */
-#define GDMA_IN_STATE_CH1    0x00000007U
-#define GDMA_IN_STATE_CH1_M  (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S)
-#define GDMA_IN_STATE_CH1_V  0x00000007U
-#define GDMA_IN_STATE_CH1_S  20
-
-/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
- *  Inlink descriptor address when EOF occurs of Rx channel 1
- */
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148)
-/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the inlink descriptor when the EOF bit in this
- *  descriptor is 1.
- */
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M  (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S)
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
-
-/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
- *  Inlink descriptor address when errors occur of Rx channel 1
- */
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c)
-/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the inlink descriptor when there are some
- *  errors in current receiving data. Only used when peripheral is UHCI0.
- */
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M  (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S)
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
-
-/** GDMA_IN_DSCR_CH1_REG register
- *  Current inlink descriptor address of Rx channel 1
- */
-#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150)
-/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
- *  The address of the current inlink descriptor x.
- */
-#define GDMA_INLINK_DSCR_CH1    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_CH1_M  (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S)
-#define GDMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_CH1_S  0
-
-/** GDMA_IN_DSCR_BF0_CH1_REG register
- *  The last inlink descriptor address of Rx channel 1
- */
-#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154)
-/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
- *  The address of the last inlink descriptor x-1.
- */
-#define GDMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF0_CH1_M  (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S)
-#define GDMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF0_CH1_S  0
-
-/** GDMA_IN_DSCR_BF1_CH1_REG register
- *  The second-to-last inlink descriptor address of Rx channel 1
- */
-#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158)
-/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
- *  The address of the second-to-last inlink descriptor x-2.
- */
-#define GDMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF1_CH1_M  (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S)
-#define GDMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF1_CH1_S  0
-
-/** GDMA_IN_PRI_CH1_REG register
- *  Priority register of Rx channel 1
- */
-#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c)
-/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
- *  The priority of Rx channel 1. The larger of the value the higher of the priority.
- */
-#define GDMA_RX_PRI_CH1    0x0000000FU
-#define GDMA_RX_PRI_CH1_M  (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S)
-#define GDMA_RX_PRI_CH1_V  0x0000000FU
-#define GDMA_RX_PRI_CH1_S  0
-
-/** GDMA_IN_PERI_SEL_CH1_REG register
- *  Peripheral selection of Rx channel 1
- */
-#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160)
-/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
- *  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2:
- *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
- *  10~15: Dummy
- */
-#define GDMA_PERI_IN_SEL_CH1    0x0000003FU
-#define GDMA_PERI_IN_SEL_CH1_M  (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S)
-#define GDMA_PERI_IN_SEL_CH1_V  0x0000003FU
-#define GDMA_PERI_IN_SEL_CH1_S  0
-
-/** GDMA_OUT_CONF0_CH1_REG register
- *  Configure 0 register of Tx channel 1
- */
-#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190)
-/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
- *  This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
- */
-#define GDMA_OUT_RST_CH1    (BIT(0))
-#define GDMA_OUT_RST_CH1_M  (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S)
-#define GDMA_OUT_RST_CH1_V  0x00000001U
-#define GDMA_OUT_RST_CH1_S  0
-/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_LOOP_TEST_CH1    (BIT(1))
-#define GDMA_OUT_LOOP_TEST_CH1_M  (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S)
-#define GDMA_OUT_LOOP_TEST_CH1_V  0x00000001U
-#define GDMA_OUT_LOOP_TEST_CH1_S  1
-/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
- *  has been transmitted.
- */
-#define GDMA_OUT_AUTO_WRBACK_CH1    (BIT(2))
-#define GDMA_OUT_AUTO_WRBACK_CH1_M  (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S)
-#define GDMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
-#define GDMA_OUT_AUTO_WRBACK_CH1_S  2
-/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
- *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
- *  generated when data need to transmit has been popped from FIFO in DMA
- */
-#define GDMA_OUT_EOF_MODE_CH1    (BIT(3))
-#define GDMA_OUT_EOF_MODE_CH1_M  (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S)
-#define GDMA_OUT_EOF_MODE_CH1_V  0x00000001U
-#define GDMA_OUT_EOF_MODE_CH1_S  3
-/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
- *  descriptor when accessing internal SRAM.
- */
-#define GDMA_OUTDSCR_BURST_EN_CH1    (BIT(4))
-#define GDMA_OUTDSCR_BURST_EN_CH1_M  (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S)
-#define GDMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
-#define GDMA_OUTDSCR_BURST_EN_CH1_S  4
-/** GDMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
- *  when accessing internal SRAM.
- */
-#define GDMA_OUT_DATA_BURST_EN_CH1    (BIT(5))
-#define GDMA_OUT_DATA_BURST_EN_CH1_M  (GDMA_OUT_DATA_BURST_EN_CH1_V << GDMA_OUT_DATA_BURST_EN_CH1_S)
-#define GDMA_OUT_DATA_BURST_EN_CH1_V  0x00000001U
-#define GDMA_OUT_DATA_BURST_EN_CH1_S  5
-/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0;
- *  Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm
- *  task.
- */
-#define GDMA_OUT_ETM_EN_CH1    (BIT(6))
-#define GDMA_OUT_ETM_EN_CH1_M  (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S)
-#define GDMA_OUT_ETM_EN_CH1_V  0x00000001U
-#define GDMA_OUT_ETM_EN_CH1_S  6
-
-/** GDMA_OUT_CONF1_CH1_REG register
- *  Configure 1 register of Tx channel 1
- */
-#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194)
-/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable checking the owner attribute of the link descriptor.
- */
-#define GDMA_OUT_CHECK_OWNER_CH1    (BIT(12))
-#define GDMA_OUT_CHECK_OWNER_CH1_M  (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S)
-#define GDMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
-#define GDMA_OUT_CHECK_OWNER_CH1_S  12
-
-/** GDMA_OUTFIFO_STATUS_CH1_REG register
- *  Transmit FIFO status of Tx channel 1
- */
-#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198)
-/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0;
- *  L1 Tx FIFO full signal for Tx channel 1.
- */
-#define GDMA_OUTFIFO_FULL_CH1    (BIT(0))
-#define GDMA_OUTFIFO_FULL_CH1_M  (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S)
-#define GDMA_OUTFIFO_FULL_CH1_V  0x00000001U
-#define GDMA_OUTFIFO_FULL_CH1_S  0
-/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
- *  L1 Tx FIFO empty signal for Tx channel 1.
- */
-#define GDMA_OUTFIFO_EMPTY_CH1    (BIT(1))
-#define GDMA_OUTFIFO_EMPTY_CH1_M  (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S)
-#define GDMA_OUTFIFO_EMPTY_CH1_V  0x00000001U
-#define GDMA_OUTFIFO_EMPTY_CH1_S  1
-/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
- *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
- */
-#define GDMA_OUTFIFO_CNT_CH1    0x0000003FU
-#define GDMA_OUTFIFO_CNT_CH1_M  (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S)
-#define GDMA_OUTFIFO_CNT_CH1_V  0x0000003FU
-#define GDMA_OUTFIFO_CNT_CH1_S  2
-/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_1B_CH1    (BIT(23))
-#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M  (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S)
-#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S  23
-/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_2B_CH1    (BIT(24))
-#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M  (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S)
-#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S  24
-/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_3B_CH1    (BIT(25))
-#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M  (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S)
-#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S  25
-/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_4B_CH1    (BIT(26))
-#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M  (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S)
-#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S  26
-
-/** GDMA_OUT_PUSH_CH1_REG register
- *  Push control register of Rx channel 1
- */
-#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c)
-/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
- *  This register stores the data that need to be pushed into DMA FIFO.
- */
-#define GDMA_OUTFIFO_WDATA_CH1    0x000001FFU
-#define GDMA_OUTFIFO_WDATA_CH1_M  (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S)
-#define GDMA_OUTFIFO_WDATA_CH1_V  0x000001FFU
-#define GDMA_OUTFIFO_WDATA_CH1_S  0
-/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0;
- *  Set this bit to push data into DMA FIFO.
- */
-#define GDMA_OUTFIFO_PUSH_CH1    (BIT(9))
-#define GDMA_OUTFIFO_PUSH_CH1_M  (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S)
-#define GDMA_OUTFIFO_PUSH_CH1_V  0x00000001U
-#define GDMA_OUTFIFO_PUSH_CH1_S  9
-
-/** GDMA_OUT_LINK_CH1_REG register
- *  Link descriptor configure and control register of Tx channel 1
- */
-#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0)
-/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0;
- *  This register stores the 20 least significant bits of the first outlink
- *  descriptor's address.
- */
-#define GDMA_OUTLINK_ADDR_CH1    0x000FFFFFU
-#define GDMA_OUTLINK_ADDR_CH1_M  (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S)
-#define GDMA_OUTLINK_ADDR_CH1_V  0x000FFFFFU
-#define GDMA_OUTLINK_ADDR_CH1_S  0
-/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [20]; default: 0;
- *  Set this bit to stop dealing with the outlink descriptors.
- */
-#define GDMA_OUTLINK_STOP_CH1    (BIT(20))
-#define GDMA_OUTLINK_STOP_CH1_M  (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S)
-#define GDMA_OUTLINK_STOP_CH1_V  0x00000001U
-#define GDMA_OUTLINK_STOP_CH1_S  20
-/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [21]; default: 0;
- *  Set this bit to start dealing with the outlink descriptors.
- */
-#define GDMA_OUTLINK_START_CH1    (BIT(21))
-#define GDMA_OUTLINK_START_CH1_M  (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S)
-#define GDMA_OUTLINK_START_CH1_V  0x00000001U
-#define GDMA_OUTLINK_START_CH1_S  21
-/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [22]; default: 0;
- *  Set this bit to restart a new outlink from the last address.
- */
-#define GDMA_OUTLINK_RESTART_CH1    (BIT(22))
-#define GDMA_OUTLINK_RESTART_CH1_M  (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S)
-#define GDMA_OUTLINK_RESTART_CH1_V  0x00000001U
-#define GDMA_OUTLINK_RESTART_CH1_S  22
-/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
- *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
- *  is working.
- */
-#define GDMA_OUTLINK_PARK_CH1    (BIT(23))
-#define GDMA_OUTLINK_PARK_CH1_M  (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S)
-#define GDMA_OUTLINK_PARK_CH1_V  0x00000001U
-#define GDMA_OUTLINK_PARK_CH1_S  23
-
-/** GDMA_OUT_STATE_CH1_REG register
- *  Transmit status of Tx channel 1
- */
-#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4)
-/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
- *  This register stores the current outlink descriptor's address.
- */
-#define GDMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
-#define GDMA_OUTLINK_DSCR_ADDR_CH1_M  (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S)
-#define GDMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
-#define GDMA_OUTLINK_DSCR_ADDR_CH1_S  0
-/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_DSCR_STATE_CH1    0x00000003U
-#define GDMA_OUT_DSCR_STATE_CH1_M  (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S)
-#define GDMA_OUT_DSCR_STATE_CH1_V  0x00000003U
-#define GDMA_OUT_DSCR_STATE_CH1_S  18
-/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_STATE_CH1    0x00000007U
-#define GDMA_OUT_STATE_CH1_M  (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S)
-#define GDMA_OUT_STATE_CH1_V  0x00000007U
-#define GDMA_OUT_STATE_CH1_S  20
-
-/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register
- *  Outlink descriptor address when EOF occurs of Tx channel 1
- */
-#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8)
-/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the outlink descriptor when the EOF bit in this
- *  descriptor is 1.
- */
-#define GDMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
-#define GDMA_OUT_EOF_DES_ADDR_CH1_M  (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S)
-#define GDMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
-#define GDMA_OUT_EOF_DES_ADDR_CH1_S  0
-
-/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
- *  The last outlink descriptor address when EOF occurs of Tx channel 1
- */
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac)
-/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the outlink descriptor before the last outlink
- *  descriptor.
- */
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1    0xFFFFFFFFU
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M  (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFFU
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
-
-/** GDMA_OUT_DSCR_CH1_REG register
- *  Current inlink descriptor address of Tx channel 1
- */
-#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0)
-/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
- *  The address of the current outlink descriptor y.
- */
-#define GDMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_CH1_M  (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S)
-#define GDMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_CH1_S  0
-
-/** GDMA_OUT_DSCR_BF0_CH1_REG register
- *  The last inlink descriptor address of Tx channel 1
- */
-#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4)
-/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
- *  The address of the last outlink descriptor y-1.
- */
-#define GDMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF0_CH1_M  (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S)
-#define GDMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF0_CH1_S  0
-
-/** GDMA_OUT_DSCR_BF1_CH1_REG register
- *  The second-to-last inlink descriptor address of Tx channel 1
- */
-#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8)
-/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
- *  The address of the second-to-last inlink descriptor x-2.
- */
-#define GDMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF1_CH1_M  (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S)
-#define GDMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF1_CH1_S  0
-
-/** GDMA_OUT_PRI_CH1_REG register
- *  Priority register of Tx channel 1
- */
-#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc)
-/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
- *  The priority of Tx channel 1. The larger of the value the higher of the priority.
- */
-#define GDMA_TX_PRI_CH1    0x0000000FU
-#define GDMA_TX_PRI_CH1_M  (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S)
-#define GDMA_TX_PRI_CH1_V  0x0000000FU
-#define GDMA_TX_PRI_CH1_S  0
-
-/** GDMA_OUT_PERI_SEL_CH1_REG register
- *  Peripheral selection of Tx channel 1
- */
-#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0)
-/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
- *  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2:
- *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
- *  10~15: Dummy
- */
-#define GDMA_PERI_OUT_SEL_CH1    0x0000003FU
-#define GDMA_PERI_OUT_SEL_CH1_M  (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S)
-#define GDMA_PERI_OUT_SEL_CH1_V  0x0000003FU
-#define GDMA_PERI_OUT_SEL_CH1_S  0
-
-/** GDMA_IN_CONF0_CH2_REG register
- *  Configure 0 register of Rx channel 2
- */
-#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0)
-/** GDMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
- *  This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
- */
-#define GDMA_IN_RST_CH2    (BIT(0))
-#define GDMA_IN_RST_CH2_M  (GDMA_IN_RST_CH2_V << GDMA_IN_RST_CH2_S)
-#define GDMA_IN_RST_CH2_V  0x00000001U
-#define GDMA_IN_RST_CH2_S  0
-/** GDMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define GDMA_IN_LOOP_TEST_CH2    (BIT(1))
-#define GDMA_IN_LOOP_TEST_CH2_M  (GDMA_IN_LOOP_TEST_CH2_V << GDMA_IN_LOOP_TEST_CH2_S)
-#define GDMA_IN_LOOP_TEST_CH2_V  0x00000001U
-#define GDMA_IN_LOOP_TEST_CH2_S  1
-/** GDMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link
- *  descriptor when accessing internal SRAM.
- */
-#define GDMA_INDSCR_BURST_EN_CH2    (BIT(2))
-#define GDMA_INDSCR_BURST_EN_CH2_M  (GDMA_INDSCR_BURST_EN_CH2_V << GDMA_INDSCR_BURST_EN_CH2_S)
-#define GDMA_INDSCR_BURST_EN_CH2_V  0x00000001U
-#define GDMA_INDSCR_BURST_EN_CH2_S  2
-/** GDMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data
- *  when accessing internal SRAM.
- */
-#define GDMA_IN_DATA_BURST_EN_CH2    (BIT(3))
-#define GDMA_IN_DATA_BURST_EN_CH2_M  (GDMA_IN_DATA_BURST_EN_CH2_V << GDMA_IN_DATA_BURST_EN_CH2_S)
-#define GDMA_IN_DATA_BURST_EN_CH2_V  0x00000001U
-#define GDMA_IN_DATA_BURST_EN_CH2_S  3
-/** GDMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0;
- *  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
- */
-#define GDMA_MEM_TRANS_EN_CH2    (BIT(4))
-#define GDMA_MEM_TRANS_EN_CH2_M  (GDMA_MEM_TRANS_EN_CH2_V << GDMA_MEM_TRANS_EN_CH2_S)
-#define GDMA_MEM_TRANS_EN_CH2_V  0x00000001U
-#define GDMA_MEM_TRANS_EN_CH2_S  4
-/** GDMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0;
- *  Set this bit to 1 to enable etm control mode, dma Rx channel 2 is triggered by etm
- *  task.
- */
-#define GDMA_IN_ETM_EN_CH2    (BIT(5))
-#define GDMA_IN_ETM_EN_CH2_M  (GDMA_IN_ETM_EN_CH2_V << GDMA_IN_ETM_EN_CH2_S)
-#define GDMA_IN_ETM_EN_CH2_V  0x00000001U
-#define GDMA_IN_ETM_EN_CH2_S  5
-
-/** GDMA_IN_CONF1_CH2_REG register
- *  Configure 1 register of Rx channel 2
- */
-#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4)
-/** GDMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable checking the owner attribute of the link descriptor.
- */
-#define GDMA_IN_CHECK_OWNER_CH2    (BIT(12))
-#define GDMA_IN_CHECK_OWNER_CH2_M  (GDMA_IN_CHECK_OWNER_CH2_V << GDMA_IN_CHECK_OWNER_CH2_S)
-#define GDMA_IN_CHECK_OWNER_CH2_V  0x00000001U
-#define GDMA_IN_CHECK_OWNER_CH2_S  12
-
-/** GDMA_INFIFO_STATUS_CH2_REG register
- *  Receive FIFO status of Rx channel 2
- */
-#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8)
-/** GDMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1;
- *  L1 Rx FIFO full signal for Rx channel 2.
- */
-#define GDMA_INFIFO_FULL_CH2    (BIT(0))
-#define GDMA_INFIFO_FULL_CH2_M  (GDMA_INFIFO_FULL_CH2_V << GDMA_INFIFO_FULL_CH2_S)
-#define GDMA_INFIFO_FULL_CH2_V  0x00000001U
-#define GDMA_INFIFO_FULL_CH2_S  0
-/** GDMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
- *  L1 Rx FIFO empty signal for Rx channel 2.
- */
-#define GDMA_INFIFO_EMPTY_CH2    (BIT(1))
-#define GDMA_INFIFO_EMPTY_CH2_M  (GDMA_INFIFO_EMPTY_CH2_V << GDMA_INFIFO_EMPTY_CH2_S)
-#define GDMA_INFIFO_EMPTY_CH2_V  0x00000001U
-#define GDMA_INFIFO_EMPTY_CH2_S  1
-/** GDMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
- *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
- */
-#define GDMA_INFIFO_CNT_CH2    0x0000003FU
-#define GDMA_INFIFO_CNT_CH2_M  (GDMA_INFIFO_CNT_CH2_V << GDMA_INFIFO_CNT_CH2_S)
-#define GDMA_INFIFO_CNT_CH2_V  0x0000003FU
-#define GDMA_INFIFO_CNT_CH2_S  2
-/** GDMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_1B_CH2    (BIT(23))
-#define GDMA_IN_REMAIN_UNDER_1B_CH2_M  (GDMA_IN_REMAIN_UNDER_1B_CH2_V << GDMA_IN_REMAIN_UNDER_1B_CH2_S)
-#define GDMA_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_1B_CH2_S  23
-/** GDMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_2B_CH2    (BIT(24))
-#define GDMA_IN_REMAIN_UNDER_2B_CH2_M  (GDMA_IN_REMAIN_UNDER_2B_CH2_V << GDMA_IN_REMAIN_UNDER_2B_CH2_S)
-#define GDMA_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_2B_CH2_S  24
-/** GDMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_3B_CH2    (BIT(25))
-#define GDMA_IN_REMAIN_UNDER_3B_CH2_M  (GDMA_IN_REMAIN_UNDER_3B_CH2_V << GDMA_IN_REMAIN_UNDER_3B_CH2_S)
-#define GDMA_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_3B_CH2_S  25
-/** GDMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
- *  reserved
- */
-#define GDMA_IN_REMAIN_UNDER_4B_CH2    (BIT(26))
-#define GDMA_IN_REMAIN_UNDER_4B_CH2_M  (GDMA_IN_REMAIN_UNDER_4B_CH2_V << GDMA_IN_REMAIN_UNDER_4B_CH2_S)
-#define GDMA_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
-#define GDMA_IN_REMAIN_UNDER_4B_CH2_S  26
-/** GDMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0;
- *  reserved
- */
-#define GDMA_IN_BUF_HUNGRY_CH2    (BIT(27))
-#define GDMA_IN_BUF_HUNGRY_CH2_M  (GDMA_IN_BUF_HUNGRY_CH2_V << GDMA_IN_BUF_HUNGRY_CH2_S)
-#define GDMA_IN_BUF_HUNGRY_CH2_V  0x00000001U
-#define GDMA_IN_BUF_HUNGRY_CH2_S  27
-
-/** GDMA_IN_POP_CH2_REG register
- *  Pop control register of Rx channel 2
- */
-#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc)
-/** GDMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
- *  This register stores the data popping from DMA FIFO.
- */
-#define GDMA_INFIFO_RDATA_CH2    0x00000FFFU
-#define GDMA_INFIFO_RDATA_CH2_M  (GDMA_INFIFO_RDATA_CH2_V << GDMA_INFIFO_RDATA_CH2_S)
-#define GDMA_INFIFO_RDATA_CH2_V  0x00000FFFU
-#define GDMA_INFIFO_RDATA_CH2_S  0
-/** GDMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0;
- *  Set this bit to pop data from DMA FIFO.
- */
-#define GDMA_INFIFO_POP_CH2    (BIT(12))
-#define GDMA_INFIFO_POP_CH2_M  (GDMA_INFIFO_POP_CH2_V << GDMA_INFIFO_POP_CH2_S)
-#define GDMA_INFIFO_POP_CH2_V  0x00000001U
-#define GDMA_INFIFO_POP_CH2_S  12
-
-/** GDMA_IN_LINK_CH2_REG register
- *  Link descriptor configure and control register of Rx channel 2
- */
-#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200)
-/** GDMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0;
- *  This register stores the 20 least significant bits of the first inlink descriptor's
- *  address.
- */
-#define GDMA_INLINK_ADDR_CH2    0x000FFFFFU
-#define GDMA_INLINK_ADDR_CH2_M  (GDMA_INLINK_ADDR_CH2_V << GDMA_INLINK_ADDR_CH2_S)
-#define GDMA_INLINK_ADDR_CH2_V  0x000FFFFFU
-#define GDMA_INLINK_ADDR_CH2_S  0
-/** GDMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1;
- *  Set this bit to return to current inlink descriptor's address when there are some
- *  errors in current receiving data.
- */
-#define GDMA_INLINK_AUTO_RET_CH2    (BIT(20))
-#define GDMA_INLINK_AUTO_RET_CH2_M  (GDMA_INLINK_AUTO_RET_CH2_V << GDMA_INLINK_AUTO_RET_CH2_S)
-#define GDMA_INLINK_AUTO_RET_CH2_V  0x00000001U
-#define GDMA_INLINK_AUTO_RET_CH2_S  20
-/** GDMA_INLINK_STOP_CH2 : WT; bitpos: [21]; default: 0;
- *  Set this bit to stop dealing with the inlink descriptors.
- */
-#define GDMA_INLINK_STOP_CH2    (BIT(21))
-#define GDMA_INLINK_STOP_CH2_M  (GDMA_INLINK_STOP_CH2_V << GDMA_INLINK_STOP_CH2_S)
-#define GDMA_INLINK_STOP_CH2_V  0x00000001U
-#define GDMA_INLINK_STOP_CH2_S  21
-/** GDMA_INLINK_START_CH2 : WT; bitpos: [22]; default: 0;
- *  Set this bit to start dealing with the inlink descriptors.
- */
-#define GDMA_INLINK_START_CH2    (BIT(22))
-#define GDMA_INLINK_START_CH2_M  (GDMA_INLINK_START_CH2_V << GDMA_INLINK_START_CH2_S)
-#define GDMA_INLINK_START_CH2_V  0x00000001U
-#define GDMA_INLINK_START_CH2_S  22
-/** GDMA_INLINK_RESTART_CH2 : WT; bitpos: [23]; default: 0;
- *  Set this bit to mount a new inlink descriptor.
- */
-#define GDMA_INLINK_RESTART_CH2    (BIT(23))
-#define GDMA_INLINK_RESTART_CH2_M  (GDMA_INLINK_RESTART_CH2_V << GDMA_INLINK_RESTART_CH2_S)
-#define GDMA_INLINK_RESTART_CH2_V  0x00000001U
-#define GDMA_INLINK_RESTART_CH2_S  23
-/** GDMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1;
- *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
- *  working.
- */
-#define GDMA_INLINK_PARK_CH2    (BIT(24))
-#define GDMA_INLINK_PARK_CH2_M  (GDMA_INLINK_PARK_CH2_V << GDMA_INLINK_PARK_CH2_S)
-#define GDMA_INLINK_PARK_CH2_V  0x00000001U
-#define GDMA_INLINK_PARK_CH2_S  24
-
-/** GDMA_IN_STATE_CH2_REG register
- *  Receive status of Rx channel 2
- */
-#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204)
-/** GDMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
- *  This register stores the current inlink descriptor's address.
- */
-#define GDMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
-#define GDMA_INLINK_DSCR_ADDR_CH2_M  (GDMA_INLINK_DSCR_ADDR_CH2_V << GDMA_INLINK_DSCR_ADDR_CH2_S)
-#define GDMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
-#define GDMA_INLINK_DSCR_ADDR_CH2_S  0
-/** GDMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
- *  reserved
- */
-#define GDMA_IN_DSCR_STATE_CH2    0x00000003U
-#define GDMA_IN_DSCR_STATE_CH2_M  (GDMA_IN_DSCR_STATE_CH2_V << GDMA_IN_DSCR_STATE_CH2_S)
-#define GDMA_IN_DSCR_STATE_CH2_V  0x00000003U
-#define GDMA_IN_DSCR_STATE_CH2_S  18
-/** GDMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
- *  reserved
- */
-#define GDMA_IN_STATE_CH2    0x00000007U
-#define GDMA_IN_STATE_CH2_M  (GDMA_IN_STATE_CH2_V << GDMA_IN_STATE_CH2_S)
-#define GDMA_IN_STATE_CH2_V  0x00000007U
-#define GDMA_IN_STATE_CH2_S  20
-
-/** GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
- *  Inlink descriptor address when EOF occurs of Rx channel 2
- */
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208)
-/** GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the inlink descriptor when the EOF bit in this
- *  descriptor is 1.
- */
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M  (GDMA_IN_SUC_EOF_DES_ADDR_CH2_V << GDMA_IN_SUC_EOF_DES_ADDR_CH2_S)
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
-#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
-
-/** GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
- *  Inlink descriptor address when errors occur of Rx channel 2
- */
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c)
-/** GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the inlink descriptor when there are some
- *  errors in current receiving data. Only used when peripheral is UHCI0.
- */
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M  (GDMA_IN_ERR_EOF_DES_ADDR_CH2_V << GDMA_IN_ERR_EOF_DES_ADDR_CH2_S)
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
-#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
-
-/** GDMA_IN_DSCR_CH2_REG register
- *  Current inlink descriptor address of Rx channel 2
- */
-#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210)
-/** GDMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
- *  The address of the current inlink descriptor x.
- */
-#define GDMA_INLINK_DSCR_CH2    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_CH2_M  (GDMA_INLINK_DSCR_CH2_V << GDMA_INLINK_DSCR_CH2_S)
-#define GDMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_CH2_S  0
-
-/** GDMA_IN_DSCR_BF0_CH2_REG register
- *  The last inlink descriptor address of Rx channel 2
- */
-#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214)
-/** GDMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
- *  The address of the last inlink descriptor x-1.
- */
-#define GDMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF0_CH2_M  (GDMA_INLINK_DSCR_BF0_CH2_V << GDMA_INLINK_DSCR_BF0_CH2_S)
-#define GDMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF0_CH2_S  0
-
-/** GDMA_IN_DSCR_BF1_CH2_REG register
- *  The second-to-last inlink descriptor address of Rx channel 2
- */
-#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218)
-/** GDMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
- *  The address of the second-to-last inlink descriptor x-2.
- */
-#define GDMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF1_CH2_M  (GDMA_INLINK_DSCR_BF1_CH2_V << GDMA_INLINK_DSCR_BF1_CH2_S)
-#define GDMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
-#define GDMA_INLINK_DSCR_BF1_CH2_S  0
-
-/** GDMA_IN_PRI_CH2_REG register
- *  Priority register of Rx channel 2
- */
-#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c)
-/** GDMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
- *  The priority of Rx channel 2. The larger of the value the higher of the priority.
- */
-#define GDMA_RX_PRI_CH2    0x0000000FU
-#define GDMA_RX_PRI_CH2_M  (GDMA_RX_PRI_CH2_V << GDMA_RX_PRI_CH2_S)
-#define GDMA_RX_PRI_CH2_V  0x0000000FU
-#define GDMA_RX_PRI_CH2_S  0
-
-/** GDMA_IN_PERI_SEL_CH2_REG register
- *  Peripheral selection of Rx channel 2
- */
-#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220)
-/** GDMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
- *  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2:
- *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
- *  10~15: Dummy
- */
-#define GDMA_PERI_IN_SEL_CH2    0x0000003FU
-#define GDMA_PERI_IN_SEL_CH2_M  (GDMA_PERI_IN_SEL_CH2_V << GDMA_PERI_IN_SEL_CH2_S)
-#define GDMA_PERI_IN_SEL_CH2_V  0x0000003FU
-#define GDMA_PERI_IN_SEL_CH2_S  0
-
-/** GDMA_OUT_CONF0_CH2_REG register
- *  Configure 0 register of Tx channel 2
- */
-#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250)
-/** GDMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
- *  This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
- */
-#define GDMA_OUT_RST_CH2    (BIT(0))
-#define GDMA_OUT_RST_CH2_M  (GDMA_OUT_RST_CH2_V << GDMA_OUT_RST_CH2_S)
-#define GDMA_OUT_RST_CH2_V  0x00000001U
-#define GDMA_OUT_RST_CH2_S  0
-/** GDMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_LOOP_TEST_CH2    (BIT(1))
-#define GDMA_OUT_LOOP_TEST_CH2_M  (GDMA_OUT_LOOP_TEST_CH2_V << GDMA_OUT_LOOP_TEST_CH2_S)
-#define GDMA_OUT_LOOP_TEST_CH2_V  0x00000001U
-#define GDMA_OUT_LOOP_TEST_CH2_S  1
-/** GDMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
- *  has been transmitted.
- */
-#define GDMA_OUT_AUTO_WRBACK_CH2    (BIT(2))
-#define GDMA_OUT_AUTO_WRBACK_CH2_M  (GDMA_OUT_AUTO_WRBACK_CH2_V << GDMA_OUT_AUTO_WRBACK_CH2_S)
-#define GDMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
-#define GDMA_OUT_AUTO_WRBACK_CH2_S  2
-/** GDMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
- *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is
- *  generated when data need to transmit has been popped from FIFO in DMA
- */
-#define GDMA_OUT_EOF_MODE_CH2    (BIT(3))
-#define GDMA_OUT_EOF_MODE_CH2_M  (GDMA_OUT_EOF_MODE_CH2_V << GDMA_OUT_EOF_MODE_CH2_S)
-#define GDMA_OUT_EOF_MODE_CH2_V  0x00000001U
-#define GDMA_OUT_EOF_MODE_CH2_S  3
-/** GDMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link
- *  descriptor when accessing internal SRAM.
- */
-#define GDMA_OUTDSCR_BURST_EN_CH2    (BIT(4))
-#define GDMA_OUTDSCR_BURST_EN_CH2_M  (GDMA_OUTDSCR_BURST_EN_CH2_V << GDMA_OUTDSCR_BURST_EN_CH2_S)
-#define GDMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
-#define GDMA_OUTDSCR_BURST_EN_CH2_S  4
-/** GDMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0;
- *  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data
- *  when accessing internal SRAM.
- */
-#define GDMA_OUT_DATA_BURST_EN_CH2    (BIT(5))
-#define GDMA_OUT_DATA_BURST_EN_CH2_M  (GDMA_OUT_DATA_BURST_EN_CH2_V << GDMA_OUT_DATA_BURST_EN_CH2_S)
-#define GDMA_OUT_DATA_BURST_EN_CH2_V  0x00000001U
-#define GDMA_OUT_DATA_BURST_EN_CH2_S  5
-/** GDMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0;
- *  Set this bit to 1 to enable etm control mode, dma Tx channel 2 is triggered by etm
- *  task.
- */
-#define GDMA_OUT_ETM_EN_CH2    (BIT(6))
-#define GDMA_OUT_ETM_EN_CH2_M  (GDMA_OUT_ETM_EN_CH2_V << GDMA_OUT_ETM_EN_CH2_S)
-#define GDMA_OUT_ETM_EN_CH2_V  0x00000001U
-#define GDMA_OUT_ETM_EN_CH2_S  6
-
-/** GDMA_OUT_CONF1_CH2_REG register
- *  Configure 1 register of Tx channel 2
- */
-#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254)
-/** GDMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable checking the owner attribute of the link descriptor.
- */
-#define GDMA_OUT_CHECK_OWNER_CH2    (BIT(12))
-#define GDMA_OUT_CHECK_OWNER_CH2_M  (GDMA_OUT_CHECK_OWNER_CH2_V << GDMA_OUT_CHECK_OWNER_CH2_S)
-#define GDMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
-#define GDMA_OUT_CHECK_OWNER_CH2_S  12
-
-/** GDMA_OUTFIFO_STATUS_CH2_REG register
- *  Transmit FIFO status of Tx channel 2
- */
-#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258)
-/** GDMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0;
- *  L1 Tx FIFO full signal for Tx channel 2.
- */
-#define GDMA_OUTFIFO_FULL_CH2    (BIT(0))
-#define GDMA_OUTFIFO_FULL_CH2_M  (GDMA_OUTFIFO_FULL_CH2_V << GDMA_OUTFIFO_FULL_CH2_S)
-#define GDMA_OUTFIFO_FULL_CH2_V  0x00000001U
-#define GDMA_OUTFIFO_FULL_CH2_S  0
-/** GDMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
- *  L1 Tx FIFO empty signal for Tx channel 2.
- */
-#define GDMA_OUTFIFO_EMPTY_CH2    (BIT(1))
-#define GDMA_OUTFIFO_EMPTY_CH2_M  (GDMA_OUTFIFO_EMPTY_CH2_V << GDMA_OUTFIFO_EMPTY_CH2_S)
-#define GDMA_OUTFIFO_EMPTY_CH2_V  0x00000001U
-#define GDMA_OUTFIFO_EMPTY_CH2_S  1
-/** GDMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
- *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
- */
-#define GDMA_OUTFIFO_CNT_CH2    0x0000003FU
-#define GDMA_OUTFIFO_CNT_CH2_M  (GDMA_OUTFIFO_CNT_CH2_V << GDMA_OUTFIFO_CNT_CH2_S)
-#define GDMA_OUTFIFO_CNT_CH2_V  0x0000003FU
-#define GDMA_OUTFIFO_CNT_CH2_S  2
-/** GDMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_1B_CH2    (BIT(23))
-#define GDMA_OUT_REMAIN_UNDER_1B_CH2_M  (GDMA_OUT_REMAIN_UNDER_1B_CH2_V << GDMA_OUT_REMAIN_UNDER_1B_CH2_S)
-#define GDMA_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_1B_CH2_S  23
-/** GDMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_2B_CH2    (BIT(24))
-#define GDMA_OUT_REMAIN_UNDER_2B_CH2_M  (GDMA_OUT_REMAIN_UNDER_2B_CH2_V << GDMA_OUT_REMAIN_UNDER_2B_CH2_S)
-#define GDMA_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_2B_CH2_S  24
-/** GDMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_3B_CH2    (BIT(25))
-#define GDMA_OUT_REMAIN_UNDER_3B_CH2_M  (GDMA_OUT_REMAIN_UNDER_3B_CH2_V << GDMA_OUT_REMAIN_UNDER_3B_CH2_S)
-#define GDMA_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_3B_CH2_S  25
-/** GDMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
- *  reserved
- */
-#define GDMA_OUT_REMAIN_UNDER_4B_CH2    (BIT(26))
-#define GDMA_OUT_REMAIN_UNDER_4B_CH2_M  (GDMA_OUT_REMAIN_UNDER_4B_CH2_V << GDMA_OUT_REMAIN_UNDER_4B_CH2_S)
-#define GDMA_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
-#define GDMA_OUT_REMAIN_UNDER_4B_CH2_S  26
-
-/** GDMA_OUT_PUSH_CH2_REG register
- *  Push control register of Rx channel 2
- */
-#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c)
-/** GDMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
- *  This register stores the data that need to be pushed into DMA FIFO.
- */
-#define GDMA_OUTFIFO_WDATA_CH2    0x000001FFU
-#define GDMA_OUTFIFO_WDATA_CH2_M  (GDMA_OUTFIFO_WDATA_CH2_V << GDMA_OUTFIFO_WDATA_CH2_S)
-#define GDMA_OUTFIFO_WDATA_CH2_V  0x000001FFU
-#define GDMA_OUTFIFO_WDATA_CH2_S  0
-/** GDMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0;
- *  Set this bit to push data into DMA FIFO.
- */
-#define GDMA_OUTFIFO_PUSH_CH2    (BIT(9))
-#define GDMA_OUTFIFO_PUSH_CH2_M  (GDMA_OUTFIFO_PUSH_CH2_V << GDMA_OUTFIFO_PUSH_CH2_S)
-#define GDMA_OUTFIFO_PUSH_CH2_V  0x00000001U
-#define GDMA_OUTFIFO_PUSH_CH2_S  9
-
-/** GDMA_OUT_LINK_CH2_REG register
- *  Link descriptor configure and control register of Tx channel 2
- */
-#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260)
-/** GDMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0;
- *  This register stores the 20 least significant bits of the first outlink
- *  descriptor's address.
- */
-#define GDMA_OUTLINK_ADDR_CH2    0x000FFFFFU
-#define GDMA_OUTLINK_ADDR_CH2_M  (GDMA_OUTLINK_ADDR_CH2_V << GDMA_OUTLINK_ADDR_CH2_S)
-#define GDMA_OUTLINK_ADDR_CH2_V  0x000FFFFFU
-#define GDMA_OUTLINK_ADDR_CH2_S  0
-/** GDMA_OUTLINK_STOP_CH2 : WT; bitpos: [20]; default: 0;
- *  Set this bit to stop dealing with the outlink descriptors.
- */
-#define GDMA_OUTLINK_STOP_CH2    (BIT(20))
-#define GDMA_OUTLINK_STOP_CH2_M  (GDMA_OUTLINK_STOP_CH2_V << GDMA_OUTLINK_STOP_CH2_S)
-#define GDMA_OUTLINK_STOP_CH2_V  0x00000001U
-#define GDMA_OUTLINK_STOP_CH2_S  20
-/** GDMA_OUTLINK_START_CH2 : WT; bitpos: [21]; default: 0;
- *  Set this bit to start dealing with the outlink descriptors.
- */
-#define GDMA_OUTLINK_START_CH2    (BIT(21))
-#define GDMA_OUTLINK_START_CH2_M  (GDMA_OUTLINK_START_CH2_V << GDMA_OUTLINK_START_CH2_S)
-#define GDMA_OUTLINK_START_CH2_V  0x00000001U
-#define GDMA_OUTLINK_START_CH2_S  21
-/** GDMA_OUTLINK_RESTART_CH2 : WT; bitpos: [22]; default: 0;
- *  Set this bit to restart a new outlink from the last address.
- */
-#define GDMA_OUTLINK_RESTART_CH2    (BIT(22))
-#define GDMA_OUTLINK_RESTART_CH2_M  (GDMA_OUTLINK_RESTART_CH2_V << GDMA_OUTLINK_RESTART_CH2_S)
-#define GDMA_OUTLINK_RESTART_CH2_V  0x00000001U
-#define GDMA_OUTLINK_RESTART_CH2_S  22
-/** GDMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
- *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
- *  is working.
- */
-#define GDMA_OUTLINK_PARK_CH2    (BIT(23))
-#define GDMA_OUTLINK_PARK_CH2_M  (GDMA_OUTLINK_PARK_CH2_V << GDMA_OUTLINK_PARK_CH2_S)
-#define GDMA_OUTLINK_PARK_CH2_V  0x00000001U
-#define GDMA_OUTLINK_PARK_CH2_S  23
-
-/** GDMA_OUT_STATE_CH2_REG register
- *  Transmit status of Tx channel 2
- */
-#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264)
-/** GDMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
- *  This register stores the current outlink descriptor's address.
- */
-#define GDMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
-#define GDMA_OUTLINK_DSCR_ADDR_CH2_M  (GDMA_OUTLINK_DSCR_ADDR_CH2_V << GDMA_OUTLINK_DSCR_ADDR_CH2_S)
-#define GDMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
-#define GDMA_OUTLINK_DSCR_ADDR_CH2_S  0
-/** GDMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_DSCR_STATE_CH2    0x00000003U
-#define GDMA_OUT_DSCR_STATE_CH2_M  (GDMA_OUT_DSCR_STATE_CH2_V << GDMA_OUT_DSCR_STATE_CH2_S)
-#define GDMA_OUT_DSCR_STATE_CH2_V  0x00000003U
-#define GDMA_OUT_DSCR_STATE_CH2_S  18
-/** GDMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
- *  reserved
- */
-#define GDMA_OUT_STATE_CH2    0x00000007U
-#define GDMA_OUT_STATE_CH2_M  (GDMA_OUT_STATE_CH2_V << GDMA_OUT_STATE_CH2_S)
-#define GDMA_OUT_STATE_CH2_V  0x00000007U
-#define GDMA_OUT_STATE_CH2_S  20
-
-/** GDMA_OUT_EOF_DES_ADDR_CH2_REG register
- *  Outlink descriptor address when EOF occurs of Tx channel 2
- */
-#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268)
-/** GDMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the outlink descriptor when the EOF bit in this
- *  descriptor is 1.
- */
-#define GDMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
-#define GDMA_OUT_EOF_DES_ADDR_CH2_M  (GDMA_OUT_EOF_DES_ADDR_CH2_V << GDMA_OUT_EOF_DES_ADDR_CH2_S)
-#define GDMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
-#define GDMA_OUT_EOF_DES_ADDR_CH2_S  0
-
-/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
- *  The last outlink descriptor address when EOF occurs of Tx channel 2
- */
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c)
-/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
- *  This register stores the address of the outlink descriptor before the last outlink
- *  descriptor.
- */
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2    0xFFFFFFFFU
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M  (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFFU
-#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
-
-/** GDMA_OUT_DSCR_CH2_REG register
- *  Current inlink descriptor address of Tx channel 2
- */
-#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270)
-/** GDMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
- *  The address of the current outlink descriptor y.
- */
-#define GDMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_CH2_M  (GDMA_OUTLINK_DSCR_CH2_V << GDMA_OUTLINK_DSCR_CH2_S)
-#define GDMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_CH2_S  0
-
-/** GDMA_OUT_DSCR_BF0_CH2_REG register
- *  The last inlink descriptor address of Tx channel 2
- */
-#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274)
-/** GDMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
- *  The address of the last outlink descriptor y-1.
- */
-#define GDMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF0_CH2_M  (GDMA_OUTLINK_DSCR_BF0_CH2_V << GDMA_OUTLINK_DSCR_BF0_CH2_S)
-#define GDMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF0_CH2_S  0
-
-/** GDMA_OUT_DSCR_BF1_CH2_REG register
- *  The second-to-last inlink descriptor address of Tx channel 2
- */
-#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278)
-/** GDMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
- *  The address of the second-to-last inlink descriptor x-2.
- */
-#define GDMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF1_CH2_M  (GDMA_OUTLINK_DSCR_BF1_CH2_V << GDMA_OUTLINK_DSCR_BF1_CH2_S)
-#define GDMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
-#define GDMA_OUTLINK_DSCR_BF1_CH2_S  0
-
-/** GDMA_OUT_PRI_CH2_REG register
- *  Priority register of Tx channel 2
- */
-#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c)
-/** GDMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
- *  The priority of Tx channel 2. The larger of the value the higher of the priority.
- */
-#define GDMA_TX_PRI_CH2    0x0000000FU
-#define GDMA_TX_PRI_CH2_M  (GDMA_TX_PRI_CH2_V << GDMA_TX_PRI_CH2_S)
-#define GDMA_TX_PRI_CH2_V  0x0000000FU
-#define GDMA_TX_PRI_CH2_S  0
-
-/** GDMA_OUT_PERI_SEL_CH2_REG register
- *  Peripheral selection of Tx channel 2
- */
-#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280)
-/** GDMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
- *  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2:
- *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
- *  10~15: Dummy
- */
-#define GDMA_PERI_OUT_SEL_CH2    0x0000003FU
-#define GDMA_PERI_OUT_SEL_CH2_M  (GDMA_PERI_OUT_SEL_CH2_V << GDMA_PERI_OUT_SEL_CH2_S)
-#define GDMA_PERI_OUT_SEL_CH2_V  0x0000003FU
-#define GDMA_PERI_OUT_SEL_CH2_S  0
-
-/** GDMA_BT_TX_SEL_REG register
- *  Bit scrambler selection
- */
-#define GDMA_BT_TX_SEL_REG (DR_REG_GDMA_BASE + 0x284)
-/** GDMA_BT_TX_SEL_CH0 : R/W; bitpos: [0]; default: 0;
- *  This register is used to select wiitch tx channel 0 across bit scrambler module
- */
-#define GDMA_BT_TX_SEL_CH0    (BIT(0))
-#define GDMA_BT_TX_SEL_CH0_M  (GDMA_BT_TX_SEL_CH0_V << GDMA_BT_TX_SEL_CH0_S)
-#define GDMA_BT_TX_SEL_CH0_V  0x00000001U
-#define GDMA_BT_TX_SEL_CH0_S  0
-/** GDMA_BT_TX_SEL_CH1 : R/W; bitpos: [1]; default: 0;
- *  This register is used to select wiitch tx channel 1 across bit scrambler module
- */
-#define GDMA_BT_TX_SEL_CH1    (BIT(1))
-#define GDMA_BT_TX_SEL_CH1_M  (GDMA_BT_TX_SEL_CH1_V << GDMA_BT_TX_SEL_CH1_S)
-#define GDMA_BT_TX_SEL_CH1_V  0x00000001U
-#define GDMA_BT_TX_SEL_CH1_S  1
-/** GDMA_BT_TX_SEL_CH2 : R/W; bitpos: [2]; default: 0;
- *  This register is used to select wiitch tx channel 2 across bit scrambler module
- */
-#define GDMA_BT_TX_SEL_CH2    (BIT(2))
-#define GDMA_BT_TX_SEL_CH2_M  (GDMA_BT_TX_SEL_CH2_V << GDMA_BT_TX_SEL_CH2_S)
-#define GDMA_BT_TX_SEL_CH2_V  0x00000001U
-#define GDMA_BT_TX_SEL_CH2_S  2
-
-/** GDMA_BT_RX_SEL_REG register
- *  Bit scrambler selection
- */
-#define GDMA_BT_RX_SEL_REG (DR_REG_GDMA_BASE + 0x288)
-/** GDMA_BT_RX_SEL_CH0 : R/W; bitpos: [0]; default: 0;
- *  This register is used to select wiitch rx channel 0 across bit scrambler module
- */
-#define GDMA_BT_RX_SEL_CH0    (BIT(0))
-#define GDMA_BT_RX_SEL_CH0_M  (GDMA_BT_RX_SEL_CH0_V << GDMA_BT_RX_SEL_CH0_S)
-#define GDMA_BT_RX_SEL_CH0_V  0x00000001U
-#define GDMA_BT_RX_SEL_CH0_S  0
-/** GDMA_BT_RX_SEL_CH1 : R/W; bitpos: [1]; default: 0;
- *  This register is used to select wiitch rx channel 1 across bit scrambler module
- */
-#define GDMA_BT_RX_SEL_CH1    (BIT(1))
-#define GDMA_BT_RX_SEL_CH1_M  (GDMA_BT_RX_SEL_CH1_V << GDMA_BT_RX_SEL_CH1_S)
-#define GDMA_BT_RX_SEL_CH1_V  0x00000001U
-#define GDMA_BT_RX_SEL_CH1_S  1
-/** GDMA_BT_RX_SEL_CH2 : R/W; bitpos: [2]; default: 0;
- *  This register is used to select wiitch rx channel 2 across bit scrambler module
- */
-#define GDMA_BT_RX_SEL_CH2    (BIT(2))
-#define GDMA_BT_RX_SEL_CH2_M  (GDMA_BT_RX_SEL_CH2_V << GDMA_BT_RX_SEL_CH2_S)
-#define GDMA_BT_RX_SEL_CH2_V  0x00000001U
-#define GDMA_BT_RX_SEL_CH2_S  2
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gdma_struct.h b/components/soc/esp32c5/beta3/include/soc/gdma_struct.h
deleted file mode 100644
index f43ed4365b..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gdma_struct.h
+++ /dev/null
@@ -1,1044 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Interrupt Registers in */
-/** Type of in_int_raw_chn register
- *  Raw status interrupt of channel n
- */
-typedef union {
-    struct {
-        /** in_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received for Rx channel n.
-         */
-        uint32_t in_done_int_raw:1;
-        /** in_suc_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
-         *  descriptor has been received for Rx channel n. For UHCI0 the raw interrupt bit
-         *  turns to high level when the last data pointed by one inlink descriptor has been
-         *  received and no data error is detected for Rx channel n.
-         */
-        uint32_t in_suc_eof_int_raw:1;
-        /** in_err_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when data error is detected only in the
-         *  case that the peripheral is UHCI0 for Rx channel n. For other peripherals this raw
-         *  interrupt is reserved.
-         */
-        uint32_t in_err_eof_int_raw:1;
-        /** in_dscr_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
-         *  including owner error and the second and third word error of inlink descriptor for
-         *  Rx channel n.
-         */
-        uint32_t in_dscr_err_int_raw:1;
-        /** in_dscr_empty_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
-         *  and receiving data is not completed but there is no more inlink for Rx channel n.
-         */
-        uint32_t in_dscr_empty_int_raw:1;
-        /** infifo_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is
-         *  overflow.
-         */
-        uint32_t infifo_ovf_int_raw:1;
-        /** infifo_udf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is
-         *  underflow.
-         */
-        uint32_t infifo_udf_int_raw:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} gdma_in_int_raw_chn_reg_t;
-
-/** Type of in_int_st_chn register
- *  Masked interrupt of channel n
- */
-typedef union {
-    struct {
-        /** in_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_int_st:1;
-        /** in_suc_eof_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_int_st:1;
-        /** in_err_eof_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_int_st:1;
-        /** in_dscr_err_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_int_st:1;
-        /** in_dscr_empty_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_int_st:1;
-        /** infifo_ovf_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_int_st:1;
-        /** infifo_udf_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_int_st:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} gdma_in_int_st_chn_reg_t;
-
-/** Type of in_int_ena_chn register
- *  Interrupt enable bits of channel n
- */
-typedef union {
-    struct {
-        /** in_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_int_ena:1;
-        /** in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_int_ena:1;
-        /** in_err_eof_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_int_ena:1;
-        /** in_dscr_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_int_ena:1;
-        /** in_dscr_empty_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_int_ena:1;
-        /** infifo_ovf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_int_ena:1;
-        /** infifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_int_ena:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} gdma_in_int_ena_chn_reg_t;
-
-/** Type of in_int_clr_chn register
- *  Interrupt clear bits of channel n
- */
-typedef union {
-    struct {
-        /** in_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
-         */
-        uint32_t in_done_int_clr:1;
-        /** in_suc_eof_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-         */
-        uint32_t in_suc_eof_int_clr:1;
-        /** in_err_eof_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-         */
-        uint32_t in_err_eof_int_clr:1;
-        /** in_dscr_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t in_dscr_err_int_clr:1;
-        /** in_dscr_empty_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-         */
-        uint32_t in_dscr_empty_int_clr:1;
-        /** infifo_ovf_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_ovf_int_clr:1;
-        /** infifo_udf_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t infifo_udf_int_clr:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} gdma_in_int_clr_chn_reg_t;
-
-
-/** Group: Interrupt Registers out */
-/** Type of out_int_raw_chn register
- *  Raw status interrupt of channel n
- */
-typedef union {
-    struct {
-        /** out_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been transmitted to peripherals for Tx channel n.
-         */
-        uint32_t out_done_int_raw:1;
-        /** out_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
-         *  descriptor has been read from memory for Tx channel n.
-         */
-        uint32_t out_eof_int_raw:1;
-        /** out_dscr_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
-         *  including owner error and the second and third word error of outlink descriptor for
-         *  Tx channel n.
-         */
-        uint32_t out_dscr_err_int_raw:1;
-        /** out_total_eof_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt bit turns to high level when data corresponding a outlink
-         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
-         *  channel n.
-         */
-        uint32_t out_total_eof_int_raw:1;
-        /** outfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is
-         *  overflow.
-         */
-        uint32_t outfifo_ovf_int_raw:1;
-        /** outfifo_udf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is
-         *  underflow.
-         */
-        uint32_t outfifo_udf_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_out_int_raw_chn_reg_t;
-
-/** Type of out_int_st_chn register
- *  Masked interrupt of channel n
- */
-typedef union {
-    struct {
-        /** out_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_int_st:1;
-        /** out_eof_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_int_st:1;
-        /** out_dscr_err_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_int_st:1;
-        /** out_total_eof_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_int_st:1;
-        /** outfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_int_st:1;
-        /** outfifo_udf_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_out_int_st_chn_reg_t;
-
-/** Type of out_int_ena_chn register
- *  Interrupt enable bits of channel n
- */
-typedef union {
-    struct {
-        /** out_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_int_ena:1;
-        /** out_eof_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_int_ena:1;
-        /** out_dscr_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_int_ena:1;
-        /** out_total_eof_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_int_ena:1;
-        /** outfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_int_ena:1;
-        /** outfifo_udf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_out_int_ena_chn_reg_t;
-
-/** Type of out_int_clr_chn register
- *  Interrupt clear bits of channel n
- */
-typedef union {
-    struct {
-        /** out_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-         */
-        uint32_t out_done_int_clr:1;
-        /** out_eof_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-         */
-        uint32_t out_eof_int_clr:1;
-        /** out_dscr_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-         */
-        uint32_t out_dscr_err_int_clr:1;
-        /** out_total_eof_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-         */
-        uint32_t out_total_eof_int_clr:1;
-        /** outfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_ovf_int_clr:1;
-        /** outfifo_udf_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-         */
-        uint32_t outfifo_udf_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_out_int_clr_chn_reg_t;
-
-
-/** Group: Debug Registers */
-/** Type of ahb_test register
- *  reserved
- */
-typedef union {
-    struct {
-        /** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
-         *  reserved
-         */
-        uint32_t ahb_testmode:3;
-        uint32_t reserved_3:1;
-        /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
-         *  reserved
-         */
-        uint32_t ahb_testaddr:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_ahb_test_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of misc_conf register
- *  MISC register
- */
-typedef union {
-    struct {
-        /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
-         *  Set this bit then clear this bit to reset the internal ahb FSM.
-         */
-        uint32_t ahbm_rst_inter:1;
-        uint32_t reserved_1:1;
-        /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to disable priority arbitration function.
-         */
-        uint32_t arb_pri_dis:1;
-        /** clk_en : R/W; bitpos: [3]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} gdma_misc_conf_reg_t;
-
-
-/** Group: Version Registers */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 36720912;
-         *  register version.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} gdma_date_reg_t;
-
-
-/** Group: Configuration Registers0 */
-/** Type of in_conf0_chn register
- *  Configure 0 register of Rx channel n
- */
-typedef union {
-    struct {
-        /** in_rst : R/W; bitpos: [0]; default: 0;
-         *  This bit is used to reset DMA channel n Rx FSM and Rx FIFO pointer.
-         */
-        uint32_t in_rst:1;
-        /** in_loop_test : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t in_loop_test:1;
-        /** indscr_burst_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Rx channel n reading link
-         *  descriptor when accessing internal SRAM.
-         */
-        uint32_t indscr_burst_en:1;
-        /** in_data_burst_en : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Rx channel n receiving data
-         *  when accessing internal SRAM.
-         */
-        uint32_t in_data_burst_en:1;
-        /** mem_trans_en : R/W; bitpos: [4]; default: 0;
-         *  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
-         */
-        uint32_t mem_trans_en:1;
-        /** in_etm_en : R/W; bitpos: [5]; default: 0;
-         *  Set this bit to 1 to enable etm control mode, dma Rx channel n is triggered by etm
-         *  task.
-         */
-        uint32_t in_etm_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_in_conf0_chn_reg_t;
-
-/** Type of in_conf1_chn register
- *  Configure 1 register of Rx channel n
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** in_check_owner : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t in_check_owner:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} gdma_in_conf1_chn_reg_t;
-
-/** Type of infifo_status_chn register
- *  Receive FIFO status of Rx channel n
- */
-typedef union {
-    struct {
-        /** infifo_full : RO; bitpos: [0]; default: 1;
-         *  L1 Rx FIFO full signal for Rx channel n.
-         */
-        uint32_t infifo_full:1;
-        /** infifo_empty : RO; bitpos: [1]; default: 1;
-         *  L1 Rx FIFO empty signal for Rx channel n.
-         */
-        uint32_t infifo_empty:1;
-        /** infifo_cnt : RO; bitpos: [7:2]; default: 0;
-         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel n.
-         */
-        uint32_t infifo_cnt:6;
-        uint32_t reserved_8:15;
-        /** in_remain_under_1b : RO; bitpos: [23]; default: 1;
-         *  reserved
-         */
-        uint32_t in_remain_under_1b:1;
-        /** in_remain_under_2b : RO; bitpos: [24]; default: 1;
-         *  reserved
-         */
-        uint32_t in_remain_under_2b:1;
-        /** in_remain_under_3b : RO; bitpos: [25]; default: 1;
-         *  reserved
-         */
-        uint32_t in_remain_under_3b:1;
-        /** in_remain_under_4b : RO; bitpos: [26]; default: 1;
-         *  reserved
-         */
-        uint32_t in_remain_under_4b:1;
-        /** in_buf_hungry : RO; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t in_buf_hungry:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gdma_infifo_status_chn_reg_t;
-
-/** Type of in_pop_chn register
- *  Pop control register of Rx channel n
- */
-typedef union {
-    struct {
-        /** infifo_rdata : RO; bitpos: [11:0]; default: 2048;
-         *  This register stores the data popping from DMA FIFO.
-         */
-        uint32_t infifo_rdata:12;
-        /** infifo_pop : WT; bitpos: [12]; default: 0;
-         *  Set this bit to pop data from DMA FIFO.
-         */
-        uint32_t infifo_pop:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} gdma_in_pop_chn_reg_t;
-
-/** Type of in_link_chn register
- *  Link descriptor configure and control register of Rx channel n
- */
-typedef union {
-    struct {
-        /** inlink_addr : R/W; bitpos: [19:0]; default: 0;
-         *  This register stores the 20 least significant bits of the first inlink descriptor's
-         *  address.
-         */
-        uint32_t inlink_addr:20;
-        /** inlink_auto_ret : R/W; bitpos: [20]; default: 1;
-         *  Set this bit to return to current inlink descriptor's address when there are some
-         *  errors in current receiving data.
-         */
-        uint32_t inlink_auto_ret:1;
-        /** inlink_stop : WT; bitpos: [21]; default: 0;
-         *  Set this bit to stop dealing with the inlink descriptors.
-         */
-        uint32_t inlink_stop:1;
-        /** inlink_start : WT; bitpos: [22]; default: 0;
-         *  Set this bit to start dealing with the inlink descriptors.
-         */
-        uint32_t inlink_start:1;
-        /** inlink_restart : WT; bitpos: [23]; default: 0;
-         *  Set this bit to mount a new inlink descriptor.
-         */
-        uint32_t inlink_restart:1;
-        /** inlink_park : RO; bitpos: [24]; default: 1;
-         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
-         *  working.
-         */
-        uint32_t inlink_park:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gdma_in_link_chn_reg_t;
-
-/** Type of in_state_chn register
- *  Receive status of Rx channel n
- */
-typedef union {
-    struct {
-        /** inlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current inlink descriptor's address.
-         */
-        uint32_t inlink_dscr_addr:18;
-        /** in_dscr_state : RO; bitpos: [19:18]; default: 0;
-         *  reserved
-         */
-        uint32_t in_dscr_state:2;
-        /** in_state : RO; bitpos: [22:20]; default: 0;
-         *  reserved
-         */
-        uint32_t in_state:3;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} gdma_in_state_chn_reg_t;
-
-/** Type of in_suc_eof_des_addr_chn register
- *  Inlink descriptor address when EOF occurs of Rx channel n
- */
-typedef union {
-    struct {
-        /** in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t in_suc_eof_des_addr:32;
-    };
-    uint32_t val;
-} gdma_in_suc_eof_des_addr_chn_reg_t;
-
-/** Type of in_err_eof_des_addr_chn register
- *  Inlink descriptor address when errors occur of Rx channel n
- */
-typedef union {
-    struct {
-        /** in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the inlink descriptor when there are some
-         *  errors in current receiving data. Only used when peripheral is UHCI0.
-         */
-        uint32_t in_err_eof_des_addr:32;
-    };
-    uint32_t val;
-} gdma_in_err_eof_des_addr_chn_reg_t;
-
-/** Type of in_dscr_chn register
- *  Current inlink descriptor address of Rx channel n
- */
-typedef union {
-    struct {
-        /** inlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  The address of the current inlink descriptor x.
-         */
-        uint32_t inlink_dscr:32;
-    };
-    uint32_t val;
-} gdma_in_dscr_chn_reg_t;
-
-/** Type of in_dscr_bf0_chn register
- *  The last inlink descriptor address of Rx channel n
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last inlink descriptor x-1.
-         */
-        uint32_t inlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} gdma_in_dscr_bf0_chn_reg_t;
-
-/** Type of in_dscr_bf1_chn register
- *  The second-to-last inlink descriptor address of Rx channel n
- */
-typedef union {
-    struct {
-        /** inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last inlink descriptor x-2.
-         */
-        uint32_t inlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} gdma_in_dscr_bf1_chn_reg_t;
-
-/** Type of in_pri_chn register
- *  Priority register of Rx channel n
- */
-typedef union {
-    struct {
-        /** rx_pri : R/W; bitpos: [3:0]; default: 0;
-         *  The priority of Rx channel n. The larger of the value the higher of the priority.
-         */
-        uint32_t rx_pri:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} gdma_in_pri_chn_reg_t;
-
-/** Type of in_peri_sel_chn register
- *  Peripheral selection of Rx channel n
- */
-typedef union {
-    struct {
-        /** peri_in_sel : R/W; bitpos: [5:0]; default: 63;
-         *  This register is used to select peripheral for Rx channel n. 0:SPI2. 1: Dummy. 2:
-         *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
-         *  10~15: Dummy
-         */
-        uint32_t peri_in_sel:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_in_peri_sel_chn_reg_t;
-
-/** Type of out_conf0_chn register
- *  Configure 0 register of Tx channel n
- */
-typedef union {
-    struct {
-        /** out_rst : R/W; bitpos: [0]; default: 0;
-         *  This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer.
-         */
-        uint32_t out_rst:1;
-        /** out_loop_test : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t out_loop_test:1;
-        /** out_auto_wrback : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
-         *  has been transmitted.
-         */
-        uint32_t out_auto_wrback:1;
-        /** out_eof_mode : R/W; bitpos: [3]; default: 1;
-         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is
-         *  generated when data need to transmit has been popped from FIFO in DMA
-         */
-        uint32_t out_eof_mode:1;
-        /** outdscr_burst_en : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link
-         *  descriptor when accessing internal SRAM.
-         */
-        uint32_t outdscr_burst_en:1;
-        /** out_data_burst_en : R/W; bitpos: [5]; default: 0;
-         *  Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data
-         *  when accessing internal SRAM.
-         */
-        uint32_t out_data_burst_en:1;
-        /** out_etm_en : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm
-         *  task.
-         */
-        uint32_t out_etm_en:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} gdma_out_conf0_chn_reg_t;
-
-/** Type of out_conf1_chn register
- *  Configure 1 register of Tx channel n
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** out_check_owner : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable checking the owner attribute of the link descriptor.
-         */
-        uint32_t out_check_owner:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} gdma_out_conf1_chn_reg_t;
-
-/** Type of outfifo_status_chn register
- *  Transmit FIFO status of Tx channel n
- */
-typedef union {
-    struct {
-        /** outfifo_full : RO; bitpos: [0]; default: 0;
-         *  L1 Tx FIFO full signal for Tx channel n.
-         */
-        uint32_t outfifo_full:1;
-        /** outfifo_empty : RO; bitpos: [1]; default: 1;
-         *  L1 Tx FIFO empty signal for Tx channel n.
-         */
-        uint32_t outfifo_empty:1;
-        /** outfifo_cnt : RO; bitpos: [7:2]; default: 0;
-         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel n.
-         */
-        uint32_t outfifo_cnt:6;
-        uint32_t reserved_8:15;
-        /** out_remain_under_1b : RO; bitpos: [23]; default: 1;
-         *  reserved
-         */
-        uint32_t out_remain_under_1b:1;
-        /** out_remain_under_2b : RO; bitpos: [24]; default: 1;
-         *  reserved
-         */
-        uint32_t out_remain_under_2b:1;
-        /** out_remain_under_3b : RO; bitpos: [25]; default: 1;
-         *  reserved
-         */
-        uint32_t out_remain_under_3b:1;
-        /** out_remain_under_4b : RO; bitpos: [26]; default: 1;
-         *  reserved
-         */
-        uint32_t out_remain_under_4b:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} gdma_outfifo_status_chn_reg_t;
-
-/** Type of out_push_chn register
- *  Push control register of Rx channel n
- */
-typedef union {
-    struct {
-        /** outfifo_wdata : R/W; bitpos: [8:0]; default: 0;
-         *  This register stores the data that need to be pushed into DMA FIFO.
-         */
-        uint32_t outfifo_wdata:9;
-        /** outfifo_push : WT; bitpos: [9]; default: 0;
-         *  Set this bit to push data into DMA FIFO.
-         */
-        uint32_t outfifo_push:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} gdma_out_push_chn_reg_t;
-
-/** Type of out_link_chn register
- *  Link descriptor configure and control register of Tx channel n
- */
-typedef union {
-    struct {
-        /** outlink_addr : R/W; bitpos: [19:0]; default: 0;
-         *  This register stores the 20 least significant bits of the first outlink
-         *  descriptor's address.
-         */
-        uint32_t outlink_addr:20;
-        /** outlink_stop : WT; bitpos: [20]; default: 0;
-         *  Set this bit to stop dealing with the outlink descriptors.
-         */
-        uint32_t outlink_stop:1;
-        /** outlink_start : WT; bitpos: [21]; default: 0;
-         *  Set this bit to start dealing with the outlink descriptors.
-         */
-        uint32_t outlink_start:1;
-        /** outlink_restart : WT; bitpos: [22]; default: 0;
-         *  Set this bit to restart a new outlink from the last address.
-         */
-        uint32_t outlink_restart:1;
-        /** outlink_park : RO; bitpos: [23]; default: 1;
-         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
-         *  is working.
-         */
-        uint32_t outlink_park:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} gdma_out_link_chn_reg_t;
-
-/** Type of out_state_chn register
- *  Transmit status of Tx channel n
- */
-typedef union {
-    struct {
-        /** outlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
-         *  This register stores the current outlink descriptor's address.
-         */
-        uint32_t outlink_dscr_addr:18;
-        /** out_dscr_state : RO; bitpos: [19:18]; default: 0;
-         *  reserved
-         */
-        uint32_t out_dscr_state:2;
-        /** out_state : RO; bitpos: [22:20]; default: 0;
-         *  reserved
-         */
-        uint32_t out_state:3;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} gdma_out_state_chn_reg_t;
-
-/** Type of out_eof_des_addr_chn register
- *  Outlink descriptor address when EOF occurs of Tx channel n
- */
-typedef union {
-    struct {
-        /** out_eof_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the outlink descriptor when the EOF bit in this
-         *  descriptor is 1.
-         */
-        uint32_t out_eof_des_addr:32;
-    };
-    uint32_t val;
-} gdma_out_eof_des_addr_chn_reg_t;
-
-/** Type of out_eof_bfr_des_addr_chn register
- *  The last outlink descriptor address when EOF occurs of Tx channel n
- */
-typedef union {
-    struct {
-        /** out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
-         *  This register stores the address of the outlink descriptor before the last outlink
-         *  descriptor.
-         */
-        uint32_t out_eof_bfr_des_addr:32;
-    };
-    uint32_t val;
-} gdma_out_eof_bfr_des_addr_chn_reg_t;
-
-/** Type of out_dscr_chn register
- *  Current inlink descriptor address of Tx channel n
- */
-typedef union {
-    struct {
-        /** outlink_dscr : RO; bitpos: [31:0]; default: 0;
-         *  The address of the current outlink descriptor y.
-         */
-        uint32_t outlink_dscr:32;
-    };
-    uint32_t val;
-} gdma_out_dscr_chn_reg_t;
-
-/** Type of out_dscr_bf0_chn register
- *  The last inlink descriptor address of Tx channel n
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the last outlink descriptor y-1.
-         */
-        uint32_t outlink_dscr_bf0:32;
-    };
-    uint32_t val;
-} gdma_out_dscr_bf0_chn_reg_t;
-
-/** Type of out_dscr_bf1_chn register
- *  The second-to-last inlink descriptor address of Tx channel n
- */
-typedef union {
-    struct {
-        /** outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
-         *  The address of the second-to-last inlink descriptor x-2.
-         */
-        uint32_t outlink_dscr_bf1:32;
-    };
-    uint32_t val;
-} gdma_out_dscr_bf1_chn_reg_t;
-
-/** Type of out_pri_chn register
- *  Priority register of Tx channel n.
- */
-typedef union {
-    struct {
-        /** tx_pri : R/W; bitpos: [3:0]; default: 0;
-         *  The priority of Tx channel n. The larger of the value the higher of the priority.
-         */
-        uint32_t tx_pri:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} gdma_out_pri_chn_reg_t;
-
-/** Type of out_peri_sel_chn register
- *  Peripheral selection of Tx channel n
- */
-typedef union {
-    struct {
-        /** peri_out_sel : R/W; bitpos: [5:0]; default: 63;
-         *  This register is used to select peripheral for Tx channel n. 0:SPI2. 1: Dummy. 2:
-         *  UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO.
-         *  10~15: Dummy
-         */
-        uint32_t peri_out_sel:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} gdma_out_peri_sel_chn_reg_t;
-
-
-/** Group: Peripheral Select Registers */
-/** Type of bt_tx_sel register
- *  Bit scrambler selection
- */
-typedef union {
-    struct {
-        /** bt_tx_sel_ch0 : R/W; bitpos: [0]; default: 0;
-         *  This register is used to select wiitch tx channel 0 across bit scrambler module
-         */
-        uint32_t bt_tx_sel_ch0:1;
-        /** bt_tx_sel_ch1 : R/W; bitpos: [1]; default: 0;
-         *  This register is used to select wiitch tx channel 1 across bit scrambler module
-         */
-        uint32_t bt_tx_sel_ch1:1;
-        /** bt_tx_sel_ch2 : R/W; bitpos: [2]; default: 0;
-         *  This register is used to select wiitch tx channel 2 across bit scrambler module
-         */
-        uint32_t bt_tx_sel_ch2:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} gdma_bt_tx_sel_reg_t;
-
-/** Type of bt_rx_sel register
- *  Bit scrambler selection
- */
-typedef union {
-    struct {
-        /** bt_rx_sel_ch0 : R/W; bitpos: [0]; default: 0;
-         *  This register is used to select wiitch rx channel 0 across bit scrambler module
-         */
-        uint32_t bt_rx_sel_ch0:1;
-        /** bt_rx_sel_ch1 : R/W; bitpos: [1]; default: 0;
-         *  This register is used to select wiitch rx channel 1 across bit scrambler module
-         */
-        uint32_t bt_rx_sel_ch1:1;
-        /** bt_rx_sel_ch2 : R/W; bitpos: [2]; default: 0;
-         *  This register is used to select wiitch rx channel 2 across bit scrambler module
-         */
-        uint32_t bt_rx_sel_ch2:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} gdma_bt_rx_sel_reg_t;
-
-typedef struct {
-    volatile gdma_in_int_raw_chn_reg_t raw;
-    volatile gdma_in_int_st_chn_reg_t st;
-    volatile gdma_in_int_ena_chn_reg_t ena;
-    volatile gdma_in_int_clr_chn_reg_t clr;
-} gdma_in_int_chn_reg_t;
-
-typedef struct {
-    volatile gdma_out_int_raw_chn_reg_t raw;
-    volatile gdma_out_int_st_chn_reg_t st;
-    volatile gdma_out_int_ena_chn_reg_t ena;
-    volatile gdma_out_int_clr_chn_reg_t clr;
-} gdma_out_int_chn_reg_t;
-
-typedef struct {
-    volatile gdma_in_conf0_chn_reg_t in_conf0;
-    volatile gdma_in_conf1_chn_reg_t in_conf1;
-    volatile gdma_infifo_status_chn_reg_t infifo_status;
-    volatile gdma_in_pop_chn_reg_t in_pop;
-    volatile gdma_in_link_chn_reg_t in_link;
-    volatile gdma_in_state_chn_reg_t in_state;
-    volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
-    volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
-    volatile gdma_in_dscr_chn_reg_t in_dscr;
-    volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
-    volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
-    volatile gdma_in_pri_chn_reg_t in_pri;
-    volatile gdma_in_peri_sel_chn_reg_t in_peri_sel;
-} gdma_in_chn_reg_t;
-
-typedef struct {
-    volatile gdma_out_conf0_chn_reg_t out_conf0;
-    volatile gdma_out_conf1_chn_reg_t out_conf1;
-    volatile gdma_outfifo_status_chn_reg_t outfifo_status;
-    volatile gdma_out_push_chn_reg_t out_push;
-    volatile gdma_out_link_chn_reg_t out_link;
-    volatile gdma_out_state_chn_reg_t out_state;
-    volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
-    volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
-    volatile gdma_out_dscr_chn_reg_t out_dscr;
-    volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
-    volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
-    volatile gdma_out_pri_chn_reg_t out_pri;
-    volatile gdma_out_peri_sel_chn_reg_t out_peri_sel;
-} gdma_out_chn_reg_t;
-
-typedef struct {
-    volatile gdma_in_chn_reg_t in;
-    uint32_t reserved_in[11];
-    volatile gdma_out_chn_reg_t out;
-} gdma_chn_reg_t;
-
-typedef struct gdma_dev_s {
-    volatile gdma_in_int_chn_reg_t in_intr[3];
-    volatile gdma_out_int_chn_reg_t out_intr[3];
-    volatile gdma_ahb_test_reg_t ahb_test;
-    volatile gdma_misc_conf_reg_t misc_conf;
-    volatile gdma_date_reg_t date;
-    uint32_t reserved_06c;
-    volatile gdma_chn_reg_t channel0;
-    uint32_t reserved_104[11];
-    volatile gdma_chn_reg_t channel1;
-    uint32_t reserved_1c4[11];
-    volatile gdma_chn_reg_t channel2;
-    volatile gdma_bt_tx_sel_reg_t bt_tx_sel;
-    volatile gdma_bt_rx_sel_reg_t bt_rx_sel;
-} gdma_dev_t;
-
-extern gdma_dev_t GDMA;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(gdma_dev_t) == 0x28c, "Invalid size of gdma_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gpio_ext_reg.h b/components/soc/esp32c5/beta3/include/soc/gpio_ext_reg.h
deleted file mode 100644
index 0f28c35315..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gpio_ext_reg.h
+++ /dev/null
@@ -1,1102 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GPIO_EXT_SIGMADELTA0_REG register
- *  Duty Cycle Configure Register of SDM0
- */
-#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x0)
-/** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIO_EXT_SD0_IN    0x000000FFU
-#define GPIO_EXT_SD0_IN_M  (GPIO_EXT_SD0_IN_V << GPIO_EXT_SD0_IN_S)
-#define GPIO_EXT_SD0_IN_V  0x000000FFU
-#define GPIO_EXT_SD0_IN_S  0
-/** GPIO_EXT_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIO_EXT_SD0_PRESCALE    0x000000FFU
-#define GPIO_EXT_SD0_PRESCALE_M  (GPIO_EXT_SD0_PRESCALE_V << GPIO_EXT_SD0_PRESCALE_S)
-#define GPIO_EXT_SD0_PRESCALE_V  0x000000FFU
-#define GPIO_EXT_SD0_PRESCALE_S  8
-
-/** GPIO_EXT_SIGMADELTA1_REG register
- *  Duty Cycle Configure Register of SDM1
- */
-#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0x4)
-/** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIO_EXT_SD1_IN    0x000000FFU
-#define GPIO_EXT_SD1_IN_M  (GPIO_EXT_SD1_IN_V << GPIO_EXT_SD1_IN_S)
-#define GPIO_EXT_SD1_IN_V  0x000000FFU
-#define GPIO_EXT_SD1_IN_S  0
-/** GPIO_EXT_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIO_EXT_SD1_PRESCALE    0x000000FFU
-#define GPIO_EXT_SD1_PRESCALE_M  (GPIO_EXT_SD1_PRESCALE_V << GPIO_EXT_SD1_PRESCALE_S)
-#define GPIO_EXT_SD1_PRESCALE_V  0x000000FFU
-#define GPIO_EXT_SD1_PRESCALE_S  8
-
-/** GPIO_EXT_SIGMADELTA2_REG register
- *  Duty Cycle Configure Register of SDM2
- */
-#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x8)
-/** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIO_EXT_SD2_IN    0x000000FFU
-#define GPIO_EXT_SD2_IN_M  (GPIO_EXT_SD2_IN_V << GPIO_EXT_SD2_IN_S)
-#define GPIO_EXT_SD2_IN_V  0x000000FFU
-#define GPIO_EXT_SD2_IN_S  0
-/** GPIO_EXT_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIO_EXT_SD2_PRESCALE    0x000000FFU
-#define GPIO_EXT_SD2_PRESCALE_M  (GPIO_EXT_SD2_PRESCALE_V << GPIO_EXT_SD2_PRESCALE_S)
-#define GPIO_EXT_SD2_PRESCALE_V  0x000000FFU
-#define GPIO_EXT_SD2_PRESCALE_S  8
-
-/** GPIO_EXT_SIGMADELTA3_REG register
- *  Duty Cycle Configure Register of SDM3
- */
-#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0xc)
-/** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0;
- *  This field is used to configure the duty cycle of sigma delta modulation output.
- */
-#define GPIO_EXT_SD3_IN    0x000000FFU
-#define GPIO_EXT_SD3_IN_M  (GPIO_EXT_SD3_IN_V << GPIO_EXT_SD3_IN_S)
-#define GPIO_EXT_SD3_IN_V  0x000000FFU
-#define GPIO_EXT_SD3_IN_S  0
-/** GPIO_EXT_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
- *  This field is used to set a divider value to divide APB clock.
- */
-#define GPIO_EXT_SD3_PRESCALE    0x000000FFU
-#define GPIO_EXT_SD3_PRESCALE_M  (GPIO_EXT_SD3_PRESCALE_V << GPIO_EXT_SD3_PRESCALE_S)
-#define GPIO_EXT_SD3_PRESCALE_V  0x000000FFU
-#define GPIO_EXT_SD3_PRESCALE_S  8
-
-/** GPIO_EXT_SIGMADELTA_MISC_REG register
- *  MISC Register
- */
-#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x24)
-/** GPIO_EXT_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
- *  Clock enable bit of sigma delta modulation.
- */
-#define GPIO_EXT_FUNCTION_CLK_EN    (BIT(30))
-#define GPIO_EXT_FUNCTION_CLK_EN_M  (GPIO_EXT_FUNCTION_CLK_EN_V << GPIO_EXT_FUNCTION_CLK_EN_S)
-#define GPIO_EXT_FUNCTION_CLK_EN_V  0x00000001U
-#define GPIO_EXT_FUNCTION_CLK_EN_S  30
-/** GPIO_EXT_SPI_SWAP : R/W; bitpos: [31]; default: 0;
- *  Reserved.
- */
-#define GPIO_EXT_SPI_SWAP    (BIT(31))
-#define GPIO_EXT_SPI_SWAP_M  (GPIO_EXT_SPI_SWAP_V << GPIO_EXT_SPI_SWAP_S)
-#define GPIO_EXT_SPI_SWAP_V  0x00000001U
-#define GPIO_EXT_SPI_SWAP_S  31
-
-/** GPIO_EXT_PAD_COMP_CONFIG_REG register
- *  PAD Compare configure Register
- */
-#define GPIO_EXT_PAD_COMP_CONFIG_REG (DR_REG_GPIO_EXT_BASE + 0x28)
-/** GPIO_EXT_XPD_COMP : R/W; bitpos: [0]; default: 0;
- *  Pad compare enable bit.
- */
-#define GPIO_EXT_XPD_COMP    (BIT(0))
-#define GPIO_EXT_XPD_COMP_M  (GPIO_EXT_XPD_COMP_V << GPIO_EXT_XPD_COMP_S)
-#define GPIO_EXT_XPD_COMP_V  0x00000001U
-#define GPIO_EXT_XPD_COMP_S  0
-/** GPIO_EXT_MODE_COMP : R/W; bitpos: [1]; default: 0;
- *  1 to enable external reference from PAD[0]. 0 to enable internal reference,
- *  meanwhile PAD[0] can be used as a regular GPIO.
- */
-#define GPIO_EXT_MODE_COMP    (BIT(1))
-#define GPIO_EXT_MODE_COMP_M  (GPIO_EXT_MODE_COMP_V << GPIO_EXT_MODE_COMP_S)
-#define GPIO_EXT_MODE_COMP_V  0x00000001U
-#define GPIO_EXT_MODE_COMP_S  1
-/** GPIO_EXT_DREF_COMP : R/W; bitpos: [4:2]; default: 0;
- *  internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
- */
-#define GPIO_EXT_DREF_COMP    0x00000007U
-#define GPIO_EXT_DREF_COMP_M  (GPIO_EXT_DREF_COMP_V << GPIO_EXT_DREF_COMP_S)
-#define GPIO_EXT_DREF_COMP_V  0x00000007U
-#define GPIO_EXT_DREF_COMP_S  2
-/** GPIO_EXT_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0;
- *  Zero Detect mode select.
- */
-#define GPIO_EXT_ZERO_DET_MODE    0x00000003U
-#define GPIO_EXT_ZERO_DET_MODE_M  (GPIO_EXT_ZERO_DET_MODE_V << GPIO_EXT_ZERO_DET_MODE_S)
-#define GPIO_EXT_ZERO_DET_MODE_V  0x00000003U
-#define GPIO_EXT_ZERO_DET_MODE_S  5
-
-/** GPIO_EXT_PAD_COMP_FILTER_REG register
- *  Zero Detect filter Register
- */
-#define GPIO_EXT_PAD_COMP_FILTER_REG (DR_REG_GPIO_EXT_BASE + 0x2c)
-/** GPIO_EXT_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0;
- *  Zero Detect filter cycle length
- */
-#define GPIO_EXT_ZERO_DET_FILTER_CNT    0xFFFFFFFFU
-#define GPIO_EXT_ZERO_DET_FILTER_CNT_M  (GPIO_EXT_ZERO_DET_FILTER_CNT_V << GPIO_EXT_ZERO_DET_FILTER_CNT_S)
-#define GPIO_EXT_ZERO_DET_FILTER_CNT_V  0xFFFFFFFFU
-#define GPIO_EXT_ZERO_DET_FILTER_CNT_S  0
-
-/** GPIO_EXT_GLITCH_FILTER_CH0_REG register
- *  Glitch Filter Configure Register of Channel0
- */
-#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0x30)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_GLITCH_FILTER_CH1_REG register
- *  Glitch Filter Configure Register of Channel1
- */
-#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0x34)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_GLITCH_FILTER_CH2_REG register
- *  Glitch Filter Configure Register of Channel2
- */
-#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0x38)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_GLITCH_FILTER_CH3_REG register
- *  Glitch Filter Configure Register of Channel3
- */
-#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0x3c)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_GLITCH_FILTER_CH4_REG register
- *  Glitch Filter Configure Register of Channel4
- */
-#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0x40)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_GLITCH_FILTER_CH5_REG register
- *  Glitch Filter Configure Register of Channel5
- */
-#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0x44)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_GLITCH_FILTER_CH6_REG register
- *  Glitch Filter Configure Register of Channel6
- */
-#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0x48)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_GLITCH_FILTER_CH7_REG register
- *  Glitch Filter Configure Register of Channel7
- */
-#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0x4c)
-/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Glitch Filter channel enable bit.
- */
-#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
-#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
-#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
-#define GPIO_EXT_FILTER_CH0_EN_S  0
-/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
- *  Glitch Filter input io number.
- */
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
-/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
- *  Glitch Filter window threshold.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
-/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
- *  Glitch Filter window width.
- */
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
-#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
-
-/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register
- *  Etm Config register of Channel0
- */
-#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x60)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register
- *  Etm Config register of Channel1
- */
-#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x64)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register
- *  Etm Config register of Channel2
- */
-#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x68)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register
- *  Etm Config register of Channel3
- */
-#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x6c)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register
- *  Etm Config register of Channel4
- */
-#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x70)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register
- *  Etm Config register of Channel5
- */
-#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x74)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register
- *  Etm Config register of Channel6
- */
-#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x78)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register
- *  Etm Config register of Channel7
- */
-#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x7c)
-/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
- *  Etm event channel select gpio.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000001FU
-#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
-/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
- *  Etm event send enable bit.
- */
-#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
-#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
-#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
-#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
-
-/** GPIO_EXT_ETM_TASK_P0_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa0)
-/** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO0_EN    (BIT(0))
-#define GPIO_EXT_ETM_TASK_GPIO0_EN_M  (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO0_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO0_EN_S  0
-/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO0_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M  (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S  1
-/** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO1_EN    (BIT(8))
-#define GPIO_EXT_ETM_TASK_GPIO1_EN_M  (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO1_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO1_EN_S  8
-/** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO1_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M  (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S  9
-/** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO2_EN    (BIT(16))
-#define GPIO_EXT_ETM_TASK_GPIO2_EN_M  (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO2_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO2_EN_S  16
-/** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO2_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M  (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S  17
-/** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO3_EN    (BIT(24))
-#define GPIO_EXT_ETM_TASK_GPIO3_EN_M  (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO3_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO3_EN_S  24
-/** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO3_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M  (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S  25
-
-/** GPIO_EXT_ETM_TASK_P1_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa4)
-/** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO4_EN    (BIT(0))
-#define GPIO_EXT_ETM_TASK_GPIO4_EN_M  (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO4_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO4_EN_S  0
-/** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO4_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M  (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S  1
-/** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO5_EN    (BIT(8))
-#define GPIO_EXT_ETM_TASK_GPIO5_EN_M  (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO5_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO5_EN_S  8
-/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO5_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M  (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S  9
-/** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO6_EN    (BIT(16))
-#define GPIO_EXT_ETM_TASK_GPIO6_EN_M  (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO6_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO6_EN_S  16
-/** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO6_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M  (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S  17
-/** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO7_EN    (BIT(24))
-#define GPIO_EXT_ETM_TASK_GPIO7_EN_M  (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO7_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO7_EN_S  24
-/** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO7_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M  (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S  25
-
-/** GPIO_EXT_ETM_TASK_P2_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xa8)
-/** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO8_EN    (BIT(0))
-#define GPIO_EXT_ETM_TASK_GPIO8_EN_M  (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO8_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO8_EN_S  0
-/** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO8_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M  (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S  1
-/** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO9_EN    (BIT(8))
-#define GPIO_EXT_ETM_TASK_GPIO9_EN_M  (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO9_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO9_EN_S  8
-/** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO9_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M  (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S  9
-/** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO10_EN    (BIT(16))
-#define GPIO_EXT_ETM_TASK_GPIO10_EN_M  (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO10_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO10_EN_S  16
-/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO10_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M  (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S  17
-/** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO11_EN    (BIT(24))
-#define GPIO_EXT_ETM_TASK_GPIO11_EN_M  (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO11_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO11_EN_S  24
-/** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO11_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M  (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S  25
-
-/** GPIO_EXT_ETM_TASK_P3_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xac)
-/** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO12_EN    (BIT(0))
-#define GPIO_EXT_ETM_TASK_GPIO12_EN_M  (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO12_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO12_EN_S  0
-/** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO12_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M  (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S  1
-/** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO13_EN    (BIT(8))
-#define GPIO_EXT_ETM_TASK_GPIO13_EN_M  (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO13_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO13_EN_S  8
-/** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO13_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M  (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S  9
-/** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO14_EN    (BIT(16))
-#define GPIO_EXT_ETM_TASK_GPIO14_EN_M  (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO14_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO14_EN_S  16
-/** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO14_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M  (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S  17
-/** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO15_EN    (BIT(24))
-#define GPIO_EXT_ETM_TASK_GPIO15_EN_M  (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO15_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO15_EN_S  24
-/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO15_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M  (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S  25
-
-/** GPIO_EXT_ETM_TASK_P4_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb0)
-/** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO16_EN    (BIT(0))
-#define GPIO_EXT_ETM_TASK_GPIO16_EN_M  (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO16_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO16_EN_S  0
-/** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO16_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M  (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S  1
-/** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO17_EN    (BIT(8))
-#define GPIO_EXT_ETM_TASK_GPIO17_EN_M  (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO17_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO17_EN_S  8
-/** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO17_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M  (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S  9
-/** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO18_EN    (BIT(16))
-#define GPIO_EXT_ETM_TASK_GPIO18_EN_M  (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO18_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO18_EN_S  16
-/** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO18_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M  (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S  17
-/** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO19_EN    (BIT(24))
-#define GPIO_EXT_ETM_TASK_GPIO19_EN_M  (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO19_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO19_EN_S  24
-/** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO19_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M  (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S  25
-
-/** GPIO_EXT_ETM_TASK_P5_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb4)
-/** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO20_EN    (BIT(0))
-#define GPIO_EXT_ETM_TASK_GPIO20_EN_M  (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO20_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO20_EN_S  0
-/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO20_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M  (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S  1
-/** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO21_EN    (BIT(8))
-#define GPIO_EXT_ETM_TASK_GPIO21_EN_M  (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO21_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO21_EN_S  8
-/** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO21_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M  (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S  9
-/** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO22_EN    (BIT(16))
-#define GPIO_EXT_ETM_TASK_GPIO22_EN_M  (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO22_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO22_EN_S  16
-/** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO22_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M  (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S  17
-/** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO23_EN    (BIT(24))
-#define GPIO_EXT_ETM_TASK_GPIO23_EN_M  (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO23_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO23_EN_S  24
-/** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO23_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M  (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S  25
-
-/** GPIO_EXT_ETM_TASK_P6_CFG_REG register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0xb8)
-/** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO24_EN    (BIT(0))
-#define GPIO_EXT_ETM_TASK_GPIO24_EN_M  (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO24_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO24_EN_S  0
-/** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO24_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M  (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S  1
-/** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO25_EN    (BIT(8))
-#define GPIO_EXT_ETM_TASK_GPIO25_EN_M  (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO25_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO25_EN_S  8
-/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO25_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M  (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S  9
-/** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0;
- *  Enable bit of GPIO response etm task.
- */
-#define GPIO_EXT_ETM_TASK_GPIO26_EN    (BIT(16))
-#define GPIO_EXT_ETM_TASK_GPIO26_EN_M  (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S)
-#define GPIO_EXT_ETM_TASK_GPIO26_EN_V  0x00000001U
-#define GPIO_EXT_ETM_TASK_GPIO26_EN_S  16
-/** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0;
- *  GPIO choose a etm task channel.
- */
-#define GPIO_EXT_ETM_TASK_GPIO26_SEL    0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M  (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S)
-#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V  0x00000007U
-#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S  17
-
-/** GPIO_EXT_INT_RAW_REG register
- *  GPIOSD interrupt raw register
- */
-#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0xe0)
-/** GPIO_EXT_COMP0_NEG_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  analog comparator pos edge interrupt raw
- */
-#define GPIO_EXT_COMP0_NEG_INT_RAW    (BIT(0))
-#define GPIO_EXT_COMP0_NEG_INT_RAW_M  (GPIO_EXT_COMP0_NEG_INT_RAW_V << GPIO_EXT_COMP0_NEG_INT_RAW_S)
-#define GPIO_EXT_COMP0_NEG_INT_RAW_V  0x00000001U
-#define GPIO_EXT_COMP0_NEG_INT_RAW_S  0
-/** GPIO_EXT_COMP0_POS_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  analog comparator neg edge interrupt raw
- */
-#define GPIO_EXT_COMP0_POS_INT_RAW    (BIT(1))
-#define GPIO_EXT_COMP0_POS_INT_RAW_M  (GPIO_EXT_COMP0_POS_INT_RAW_V << GPIO_EXT_COMP0_POS_INT_RAW_S)
-#define GPIO_EXT_COMP0_POS_INT_RAW_V  0x00000001U
-#define GPIO_EXT_COMP0_POS_INT_RAW_S  1
-/** GPIO_EXT_COMP0_ALL_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  analog comparator neg or pos edge interrupt raw
- */
-#define GPIO_EXT_COMP0_ALL_INT_RAW    (BIT(2))
-#define GPIO_EXT_COMP0_ALL_INT_RAW_M  (GPIO_EXT_COMP0_ALL_INT_RAW_V << GPIO_EXT_COMP0_ALL_INT_RAW_S)
-#define GPIO_EXT_COMP0_ALL_INT_RAW_V  0x00000001U
-#define GPIO_EXT_COMP0_ALL_INT_RAW_S  2
-
-/** GPIO_EXT_INT_ST_REG register
- *  GPIOSD interrupt masked register
- */
-#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0xe4)
-/** GPIO_EXT_COMP0_NEG_INT_ST : RO; bitpos: [0]; default: 0;
- *  analog comparator pos edge interrupt status
- */
-#define GPIO_EXT_COMP0_NEG_INT_ST    (BIT(0))
-#define GPIO_EXT_COMP0_NEG_INT_ST_M  (GPIO_EXT_COMP0_NEG_INT_ST_V << GPIO_EXT_COMP0_NEG_INT_ST_S)
-#define GPIO_EXT_COMP0_NEG_INT_ST_V  0x00000001U
-#define GPIO_EXT_COMP0_NEG_INT_ST_S  0
-/** GPIO_EXT_COMP0_POS_INT_ST : RO; bitpos: [1]; default: 0;
- *  analog comparator neg edge interrupt status
- */
-#define GPIO_EXT_COMP0_POS_INT_ST    (BIT(1))
-#define GPIO_EXT_COMP0_POS_INT_ST_M  (GPIO_EXT_COMP0_POS_INT_ST_V << GPIO_EXT_COMP0_POS_INT_ST_S)
-#define GPIO_EXT_COMP0_POS_INT_ST_V  0x00000001U
-#define GPIO_EXT_COMP0_POS_INT_ST_S  1
-/** GPIO_EXT_COMP0_ALL_INT_ST : RO; bitpos: [2]; default: 0;
- *  analog comparator neg or pos edge interrupt status
- */
-#define GPIO_EXT_COMP0_ALL_INT_ST    (BIT(2))
-#define GPIO_EXT_COMP0_ALL_INT_ST_M  (GPIO_EXT_COMP0_ALL_INT_ST_V << GPIO_EXT_COMP0_ALL_INT_ST_S)
-#define GPIO_EXT_COMP0_ALL_INT_ST_V  0x00000001U
-#define GPIO_EXT_COMP0_ALL_INT_ST_S  2
-
-/** GPIO_EXT_INT_ENA_REG register
- *  GPIOSD interrupt enable register
- */
-#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0xe8)
-/** GPIO_EXT_COMP0_NEG_INT_ENA : R/W; bitpos: [0]; default: 1;
- *  analog comparator pos edge interrupt enable
- */
-#define GPIO_EXT_COMP0_NEG_INT_ENA    (BIT(0))
-#define GPIO_EXT_COMP0_NEG_INT_ENA_M  (GPIO_EXT_COMP0_NEG_INT_ENA_V << GPIO_EXT_COMP0_NEG_INT_ENA_S)
-#define GPIO_EXT_COMP0_NEG_INT_ENA_V  0x00000001U
-#define GPIO_EXT_COMP0_NEG_INT_ENA_S  0
-/** GPIO_EXT_COMP0_POS_INT_ENA : R/W; bitpos: [1]; default: 1;
- *  analog comparator neg edge interrupt enable
- */
-#define GPIO_EXT_COMP0_POS_INT_ENA    (BIT(1))
-#define GPIO_EXT_COMP0_POS_INT_ENA_M  (GPIO_EXT_COMP0_POS_INT_ENA_V << GPIO_EXT_COMP0_POS_INT_ENA_S)
-#define GPIO_EXT_COMP0_POS_INT_ENA_V  0x00000001U
-#define GPIO_EXT_COMP0_POS_INT_ENA_S  1
-/** GPIO_EXT_COMP0_ALL_INT_ENA : R/W; bitpos: [2]; default: 1;
- *  analog comparator neg or pos edge interrupt enable
- */
-#define GPIO_EXT_COMP0_ALL_INT_ENA    (BIT(2))
-#define GPIO_EXT_COMP0_ALL_INT_ENA_M  (GPIO_EXT_COMP0_ALL_INT_ENA_V << GPIO_EXT_COMP0_ALL_INT_ENA_S)
-#define GPIO_EXT_COMP0_ALL_INT_ENA_V  0x00000001U
-#define GPIO_EXT_COMP0_ALL_INT_ENA_S  2
-
-/** GPIO_EXT_INT_CLR_REG register
- *  GPIOSD interrupt clear register
- */
-#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0xec)
-/** GPIO_EXT_COMP0_NEG_INT_CLR : WT; bitpos: [0]; default: 0;
- *  analog comparator pos edge interrupt clear
- */
-#define GPIO_EXT_COMP0_NEG_INT_CLR    (BIT(0))
-#define GPIO_EXT_COMP0_NEG_INT_CLR_M  (GPIO_EXT_COMP0_NEG_INT_CLR_V << GPIO_EXT_COMP0_NEG_INT_CLR_S)
-#define GPIO_EXT_COMP0_NEG_INT_CLR_V  0x00000001U
-#define GPIO_EXT_COMP0_NEG_INT_CLR_S  0
-/** GPIO_EXT_COMP0_POS_INT_CLR : WT; bitpos: [1]; default: 0;
- *  analog comparator neg edge interrupt clear
- */
-#define GPIO_EXT_COMP0_POS_INT_CLR    (BIT(1))
-#define GPIO_EXT_COMP0_POS_INT_CLR_M  (GPIO_EXT_COMP0_POS_INT_CLR_V << GPIO_EXT_COMP0_POS_INT_CLR_S)
-#define GPIO_EXT_COMP0_POS_INT_CLR_V  0x00000001U
-#define GPIO_EXT_COMP0_POS_INT_CLR_S  1
-/** GPIO_EXT_COMP0_ALL_INT_CLR : WT; bitpos: [2]; default: 0;
- *  analog comparator neg or pos edge interrupt clear
- */
-#define GPIO_EXT_COMP0_ALL_INT_CLR    (BIT(2))
-#define GPIO_EXT_COMP0_ALL_INT_CLR_M  (GPIO_EXT_COMP0_ALL_INT_CLR_V << GPIO_EXT_COMP0_ALL_INT_CLR_S)
-#define GPIO_EXT_COMP0_ALL_INT_CLR_V  0x00000001U
-#define GPIO_EXT_COMP0_ALL_INT_CLR_S  2
-
-/** GPIO_EXT_VERSION_REG register
- *  Version Control Register
- */
-#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0xfc)
-/** GPIO_EXT_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 36704513;
- *  Version control register.
- */
-#define GPIO_EXT_GPIO_SD_DATE    0x0FFFFFFFU
-#define GPIO_EXT_GPIO_SD_DATE_M  (GPIO_EXT_GPIO_SD_DATE_V << GPIO_EXT_GPIO_SD_DATE_S)
-#define GPIO_EXT_GPIO_SD_DATE_V  0x0FFFFFFFU
-#define GPIO_EXT_GPIO_SD_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/beta3/include/soc/gpio_ext_struct.h
deleted file mode 100644
index f4a65cb89c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gpio_ext_struct.h
+++ /dev/null
@@ -1,340 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: SDM Configure Registers */
-/** Type of sigmadeltan register
- *  Duty Cycle Configure Register of SDMn
- */
-typedef union {
-    struct {
-        /** sdn_in : R/W; bitpos: [7:0]; default: 0;
-         *  This field is used to configure the duty cycle of sigma delta modulation output.
-         */
-        uint32_t sdn_in:8;
-        /** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
-         *  This field is used to set a divider value to divide APB clock.
-         */
-        uint32_t sdn_prescale:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} gpio_ext_sigmadeltan_reg_t;
-
-/** Type of sigmadelta_misc register
- *  MISC Register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** function_clk_en : R/W; bitpos: [30]; default: 0;
-         *  Clock enable bit of sigma delta modulation.
-         */
-        uint32_t function_clk_en:1;
-        /** spi_swap : R/W; bitpos: [31]; default: 0;
-         *  Reserved.
-         */
-        uint32_t spi_swap:1;
-    };
-    uint32_t val;
-} gpio_ext_sigmadelta_misc_reg_t;
-
-
-/** Group: Configure Registers */
-/** Type of pad_comp_config register
- *  PAD Compare configure Register
- */
-typedef union {
-    struct {
-        /** xpd_comp : R/W; bitpos: [0]; default: 0;
-         *  Pad compare enable bit.
-         */
-        uint32_t xpd_comp:1;
-        /** mode_comp : R/W; bitpos: [1]; default: 0;
-         *  1 to enable external reference from PAD[0]. 0 to enable internal reference,
-         *  meanwhile PAD[0] can be used as a regular GPIO.
-         */
-        uint32_t mode_comp:1;
-        /** dref_comp : R/W; bitpos: [4:2]; default: 0;
-         *  internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
-         */
-        uint32_t dref_comp:3;
-        /** zero_det_mode : R/W; bitpos: [6:5]; default: 0;
-         *  Zero Detect mode select.
-         */
-        uint32_t zero_det_mode:2;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} gpio_ext_pad_comp_config_reg_t;
-
-/** Type of pad_comp_filter register
- *  Zero Detect filter Register
- */
-typedef union {
-    struct {
-        /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 0;
-         *  Zero Detect filter cycle length
-         */
-        uint32_t zero_det_filter_cnt:32;
-    };
-    uint32_t val;
-} gpio_ext_pad_comp_filter_reg_t;
-
-
-/** Group: Glitch filter Configure Registers */
-/** Type of glitch_filter_chn register
- *  Glitch Filter Configure Register of Channeln
- */
-typedef union {
-    struct {
-        /** filter_ch0_en : R/W; bitpos: [0]; default: 0;
-         *  Glitch Filter channel enable bit.
-         */
-        uint32_t filter_ch0_en:1;
-        /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
-         *  Glitch Filter input io number.
-         */
-        uint32_t filter_ch0_input_io_num:6;
-        /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
-         *  Glitch Filter window threshold.
-         */
-        uint32_t filter_ch0_window_thres:6;
-        /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
-         *  Glitch Filter window width.
-         */
-        uint32_t filter_ch0_window_width:6;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} gpio_ext_glitch_filter_chn_reg_t;
-
-
-/** Group: Etm Configure Registers */
-/** Type of etm_event_chn_cfg register
- *  Etm Config register of Channeln
- */
-typedef union {
-    struct {
-        /** etm_ch0_event_sel : R/W; bitpos: [4:0]; default: 0;
-         *  Etm event channel select gpio.
-         */
-        uint32_t etm_ch0_event_sel:5;
-        uint32_t reserved_5:2;
-        /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
-         *  Etm event send enable bit.
-         */
-        uint32_t etm_ch0_event_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_ext_etm_event_chn_cfg_reg_t;
-
-/** Type of etm_task_pn_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio0_en:1;
-        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio0_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio1_en:1;
-        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio1_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio2_en:1;
-        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio2_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio3_en:1;
-        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio3_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_ext_etm_task_pn_cfg_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_raw register
- *  GPIOSD interrupt raw register
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  analog comparator pos edge interrupt raw
-         */
-        uint32_t comp0_neg_int_raw:1;
-        /** comp0_pos_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  analog comparator neg edge interrupt raw
-         */
-        uint32_t comp0_pos_int_raw:1;
-        /** comp0_all_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  analog comparator neg or pos edge interrupt raw
-         */
-        uint32_t comp0_all_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} gpio_ext_int_raw_reg_t;
-
-/** Type of int_st register
- *  GPIOSD interrupt masked register
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
-         *  analog comparator pos edge interrupt status
-         */
-        uint32_t comp0_neg_int_st:1;
-        /** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
-         *  analog comparator neg edge interrupt status
-         */
-        uint32_t comp0_pos_int_st:1;
-        /** comp0_all_int_st : RO; bitpos: [2]; default: 0;
-         *  analog comparator neg or pos edge interrupt status
-         */
-        uint32_t comp0_all_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} gpio_ext_int_st_reg_t;
-
-/** Type of int_ena register
- *  GPIOSD interrupt enable register
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
-         *  analog comparator pos edge interrupt enable
-         */
-        uint32_t comp0_neg_int_ena:1;
-        /** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
-         *  analog comparator neg edge interrupt enable
-         */
-        uint32_t comp0_pos_int_ena:1;
-        /** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
-         *  analog comparator neg or pos edge interrupt enable
-         */
-        uint32_t comp0_all_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} gpio_ext_int_ena_reg_t;
-
-/** Type of int_clr register
- *  GPIOSD interrupt clear register
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
-         *  analog comparator pos edge interrupt clear
-         */
-        uint32_t comp0_neg_int_clr:1;
-        /** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
-         *  analog comparator neg edge interrupt clear
-         */
-        uint32_t comp0_pos_int_clr:1;
-        /** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
-         *  analog comparator neg or pos edge interrupt clear
-         */
-        uint32_t comp0_all_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} gpio_ext_int_clr_reg_t;
-
-
-/** Group: Version Register */
-/** Type of version register
- *  Version Control Register
- */
-typedef union {
-    struct {
-        /** gpio_sd_date : R/W; bitpos: [27:0]; default: 36704513;
-         *  Version control register.
-         */
-        uint32_t gpio_sd_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_ext_version_reg_t;
-
-
-typedef struct gpio_sd_dev_t {
-    volatile gpio_ext_sigmadeltan_reg_t channel[4];
-    uint32_t reserved_010[5];
-    volatile gpio_ext_sigmadelta_misc_reg_t misc;
-} gpio_sd_dev_t;
-
-typedef struct gpio_ana_cmpr_dev_t {
-    volatile gpio_ext_pad_comp_config_reg_t pad_comp_config;
-    volatile gpio_ext_pad_comp_filter_reg_t pad_comp_filter;
-} gpio_ana_cmpr_dev_t;
-
-typedef struct {
-    volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
-} gpio_glitch_filter_dev_t;
-
-typedef struct gpio_etm_dev_t {
-    volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
-    uint32_t reserved_080[8];
-    volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[7];
-} gpio_etm_dev_t;
-
-typedef struct gpio_ext_dev_t {
-    volatile gpio_sd_dev_t sigma_delta;
-    volatile gpio_ana_cmpr_dev_t ana_cmpr;
-    volatile gpio_glitch_filter_dev_t glitch_filter;
-    uint32_t reserved_050[4];
-    volatile gpio_etm_dev_t etm;
-    uint32_t reserved_0bc[9];
-    volatile gpio_ext_int_raw_reg_t int_raw;
-    volatile gpio_ext_int_st_reg_t int_st;
-    volatile gpio_ext_int_ena_reg_t int_ena;
-    volatile gpio_ext_int_clr_reg_t int_clr;
-    uint32_t reserved_0f0[3];
-    volatile gpio_ext_version_reg_t version;
-} gpio_ext_dev_t;
-
-extern gpio_sd_dev_t SDM;
-extern gpio_glitch_filter_dev_t GLITCH_FILTER;
-extern gpio_etm_dev_t GPIO_ETM;
-extern gpio_ext_dev_t GPIO_EXT;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gpio_num.h b/components/soc/esp32c5/beta3/include/soc/gpio_num.h
deleted file mode 100644
index c0351b94bd..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gpio_num.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief GPIO number
- */
-typedef enum {
-    GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
-    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
-    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
-    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output */
-    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
-    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
-    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
-    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
-    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
-    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
-    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
-    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
-    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
-    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
-    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
-    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
-    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
-    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
-    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
-    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
-    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
-    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
-    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
-    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
-    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
-    GPIO_NUM_24 = 24,   /*!< GPIO24, input and output */
-    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
-    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
-    GPIO_NUM_MAX,
-} gpio_num_t;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gpio_pins.h b/components/soc/esp32c5/beta3/include/soc/gpio_pins.h
deleted file mode 100644
index c630ae4764..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gpio_pins.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
-#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gpio_reg.h b/components/soc/esp32c5/beta3/include/soc/gpio_reg.h
deleted file mode 100644
index d0765dd040..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gpio_reg.h
+++ /dev/null
@@ -1,5727 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GPIO_BT_SELECT_REG register
- *  GPIO bit select register
- */
-#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
-/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0;
- *  GPIO bit select register
- */
-#define GPIO_BT_SEL    0xFFFFFFFFU
-#define GPIO_BT_SEL_M  (GPIO_BT_SEL_V << GPIO_BT_SEL_S)
-#define GPIO_BT_SEL_V  0xFFFFFFFFU
-#define GPIO_BT_SEL_S  0
-
-/** GPIO_OUT_REG register
- *  GPIO output register for GPIO0-30
- */
-#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
-/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [30:0]; default: 0;
- *  GPIO output register for GPIO0-30
- */
-#define GPIO_OUT_DATA_ORIG    0x7FFFFFFFU
-#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
-#define GPIO_OUT_DATA_ORIG_V  0x7FFFFFFFU
-#define GPIO_OUT_DATA_ORIG_S  0
-
-/** GPIO_OUT_W1TS_REG register
- *  GPIO output set register for GPIO0-30
- */
-#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
-/** GPIO_OUT_W1TS : WT; bitpos: [30:0]; default: 0;
- *  GPIO output set register for GPIO0-30
- */
-#define GPIO_OUT_W1TS    0x7FFFFFFFU
-#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
-#define GPIO_OUT_W1TS_V  0x7FFFFFFFU
-#define GPIO_OUT_W1TS_S  0
-
-/** GPIO_OUT_W1TC_REG register
- *  GPIO output clear register for GPIO0-30
- */
-#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
-/** GPIO_OUT_W1TC : WT; bitpos: [30:0]; default: 0;
- *  GPIO output clear register for GPIO0-30
- */
-#define GPIO_OUT_W1TC    0x7FFFFFFFU
-#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
-#define GPIO_OUT_W1TC_V  0x7FFFFFFFU
-#define GPIO_OUT_W1TC_S  0
-
-/** GPIO_SDIO_SELECT_REG register
- *  GPIO sdio select register
- */
-#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c)
-/** GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0;
- *  GPIO sdio select register
- */
-#define GPIO_SDIO_SEL    0x000000FFU
-#define GPIO_SDIO_SEL_M  (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S)
-#define GPIO_SDIO_SEL_V  0x000000FFU
-#define GPIO_SDIO_SEL_S  0
-
-/** GPIO_ENABLE_REG register
- *  GPIO output enable register for GPIO0-30
- */
-#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20)
-/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [30:0]; default: 0;
- *  GPIO output enable register for GPIO0-30
- */
-#define GPIO_ENABLE_DATA    0x7FFFFFFFU
-#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
-#define GPIO_ENABLE_DATA_V  0x7FFFFFFFU
-#define GPIO_ENABLE_DATA_S  0
-
-/** GPIO_ENABLE_W1TS_REG register
- *  GPIO output enable set register for GPIO0-30
- */
-#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
-/** GPIO_ENABLE_W1TS : WT; bitpos: [30:0]; default: 0;
- *  GPIO output enable set register for GPIO0-30
- */
-#define GPIO_ENABLE_W1TS    0x7FFFFFFFU
-#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
-#define GPIO_ENABLE_W1TS_V  0x7FFFFFFFU
-#define GPIO_ENABLE_W1TS_S  0
-
-/** GPIO_ENABLE_W1TC_REG register
- *  GPIO output enable clear register for GPIO0-30
- */
-#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28)
-/** GPIO_ENABLE_W1TC : WT; bitpos: [30:0]; default: 0;
- *  GPIO output enable clear register for GPIO0-30
- */
-#define GPIO_ENABLE_W1TC    0x7FFFFFFFU
-#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
-#define GPIO_ENABLE_W1TC_V  0x7FFFFFFFU
-#define GPIO_ENABLE_W1TC_S  0
-
-/** GPIO_STRAP_REG register
- *  pad strapping register
- */
-#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38)
-/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
- *  pad strapping register
- */
-#define GPIO_STRAPPING    0x0000FFFFU
-#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
-#define GPIO_STRAPPING_V  0x0000FFFFU
-#define GPIO_STRAPPING_S  0
-
-/** GPIO_IN_REG register
- *  GPIO input register for GPIO0-30
- */
-#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c)
-/** GPIO_IN_DATA_NEXT : RO; bitpos: [30:0]; default: 0;
- *  GPIO input register for GPIO0-30
- */
-#define GPIO_IN_DATA_NEXT    0x7FFFFFFFU
-#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
-#define GPIO_IN_DATA_NEXT_V  0x7FFFFFFFU
-#define GPIO_IN_DATA_NEXT_S  0
-
-/** GPIO_STATUS_REG register
- *  GPIO interrupt status register for GPIO0-30
- */
-#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
-/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [30:0]; default: 0;
- *  GPIO interrupt status register for GPIO0-30
- */
-#define GPIO_STATUS_INTERRUPT    0x7FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
-#define GPIO_STATUS_INTERRUPT_V  0x7FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_S  0
-
-/** GPIO_STATUS_W1TS_REG register
- *  GPIO interrupt status set register for GPIO0-30
- */
-#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48)
-/** GPIO_STATUS_W1TS : WT; bitpos: [30:0]; default: 0;
- *  GPIO interrupt status set register for GPIO0-30
- */
-#define GPIO_STATUS_W1TS    0x7FFFFFFFU
-#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
-#define GPIO_STATUS_W1TS_V  0x7FFFFFFFU
-#define GPIO_STATUS_W1TS_S  0
-
-/** GPIO_STATUS_W1TC_REG register
- *  GPIO interrupt status clear register for GPIO0-30
- */
-#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c)
-/** GPIO_STATUS_W1TC : WT; bitpos: [30:0]; default: 0;
- *  GPIO interrupt status clear register for GPIO0-30
- */
-#define GPIO_STATUS_W1TC    0x7FFFFFFFU
-#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
-#define GPIO_STATUS_W1TC_V  0x7FFFFFFFU
-#define GPIO_STATUS_W1TC_S  0
-
-/** GPIO_PCPU_INT_REG register
- *  GPIO PRO_CPU interrupt status register for GPIO0-30
- */
-#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c)
-/** GPIO_PROCPU_INT : RO; bitpos: [30:0]; default: 0;
- *  GPIO PRO_CPU interrupt status register for GPIO0-30
- */
-#define GPIO_PROCPU_INT    0x7FFFFFFFU
-#define GPIO_PROCPU_INT_M  (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S)
-#define GPIO_PROCPU_INT_V  0x7FFFFFFFU
-#define GPIO_PROCPU_INT_S  0
-
-/** GPIO_PCPU_NMI_INT_REG register
- *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30
- */
-#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60)
-/** GPIO_PROCPU_NMI_INT : RO; bitpos: [30:0]; default: 0;
- *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30
- */
-#define GPIO_PROCPU_NMI_INT    0x7FFFFFFFU
-#define GPIO_PROCPU_NMI_INT_M  (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S)
-#define GPIO_PROCPU_NMI_INT_V  0x7FFFFFFFU
-#define GPIO_PROCPU_NMI_INT_S  0
-
-/** GPIO_CPUSDIO_INT_REG register
- *  GPIO CPUSDIO interrupt status register for GPIO0-30
- */
-#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64)
-/** GPIO_SDIO_INT : RO; bitpos: [30:0]; default: 0;
- *  GPIO CPUSDIO interrupt status register for GPIO0-30
- */
-#define GPIO_SDIO_INT    0x7FFFFFFFU
-#define GPIO_SDIO_INT_M  (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S)
-#define GPIO_SDIO_INT_V  0x7FFFFFFFU
-#define GPIO_SDIO_INT_S  0
-
-/** GPIO_PIN0_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74)
-/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
-#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN0_SYNC2_BYPASS_S  0
-/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
-#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN0_PAD_DRIVER_S  2
-/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
-#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN0_SYNC1_BYPASS_S  3
-/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN0_INT_TYPE    0x00000007U
-#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
-#define GPIO_PIN0_INT_TYPE_V  0x00000007U
-#define GPIO_PIN0_INT_TYPE_S  7
-/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
-#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN0_WAKEUP_ENABLE_S  10
-/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN0_CONFIG    0x00000003U
-#define GPIO_PIN0_CONFIG_M  (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S)
-#define GPIO_PIN0_CONFIG_V  0x00000003U
-#define GPIO_PIN0_CONFIG_S  11
-/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN0_INT_ENA    0x0000001FU
-#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
-#define GPIO_PIN0_INT_ENA_V  0x0000001FU
-#define GPIO_PIN0_INT_ENA_S  13
-
-/** GPIO_PIN1_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78)
-/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
-#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN1_SYNC2_BYPASS_S  0
-/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
-#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN1_PAD_DRIVER_S  2
-/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
-#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN1_SYNC1_BYPASS_S  3
-/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN1_INT_TYPE    0x00000007U
-#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
-#define GPIO_PIN1_INT_TYPE_V  0x00000007U
-#define GPIO_PIN1_INT_TYPE_S  7
-/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
-#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN1_WAKEUP_ENABLE_S  10
-/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN1_CONFIG    0x00000003U
-#define GPIO_PIN1_CONFIG_M  (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S)
-#define GPIO_PIN1_CONFIG_V  0x00000003U
-#define GPIO_PIN1_CONFIG_S  11
-/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN1_INT_ENA    0x0000001FU
-#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
-#define GPIO_PIN1_INT_ENA_V  0x0000001FU
-#define GPIO_PIN1_INT_ENA_S  13
-
-/** GPIO_PIN2_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c)
-/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
-#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN2_SYNC2_BYPASS_S  0
-/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
-#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN2_PAD_DRIVER_S  2
-/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
-#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN2_SYNC1_BYPASS_S  3
-/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN2_INT_TYPE    0x00000007U
-#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
-#define GPIO_PIN2_INT_TYPE_V  0x00000007U
-#define GPIO_PIN2_INT_TYPE_S  7
-/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
-#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN2_WAKEUP_ENABLE_S  10
-/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN2_CONFIG    0x00000003U
-#define GPIO_PIN2_CONFIG_M  (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S)
-#define GPIO_PIN2_CONFIG_V  0x00000003U
-#define GPIO_PIN2_CONFIG_S  11
-/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN2_INT_ENA    0x0000001FU
-#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
-#define GPIO_PIN2_INT_ENA_V  0x0000001FU
-#define GPIO_PIN2_INT_ENA_S  13
-
-/** GPIO_PIN3_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
-/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
-#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN3_SYNC2_BYPASS_S  0
-/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
-#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN3_PAD_DRIVER_S  2
-/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
-#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN3_SYNC1_BYPASS_S  3
-/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN3_INT_TYPE    0x00000007U
-#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
-#define GPIO_PIN3_INT_TYPE_V  0x00000007U
-#define GPIO_PIN3_INT_TYPE_S  7
-/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
-#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN3_WAKEUP_ENABLE_S  10
-/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN3_CONFIG    0x00000003U
-#define GPIO_PIN3_CONFIG_M  (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S)
-#define GPIO_PIN3_CONFIG_V  0x00000003U
-#define GPIO_PIN3_CONFIG_S  11
-/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN3_INT_ENA    0x0000001FU
-#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
-#define GPIO_PIN3_INT_ENA_V  0x0000001FU
-#define GPIO_PIN3_INT_ENA_S  13
-
-/** GPIO_PIN4_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84)
-/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
-#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN4_SYNC2_BYPASS_S  0
-/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
-#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN4_PAD_DRIVER_S  2
-/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
-#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN4_SYNC1_BYPASS_S  3
-/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN4_INT_TYPE    0x00000007U
-#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
-#define GPIO_PIN4_INT_TYPE_V  0x00000007U
-#define GPIO_PIN4_INT_TYPE_S  7
-/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
-#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN4_WAKEUP_ENABLE_S  10
-/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN4_CONFIG    0x00000003U
-#define GPIO_PIN4_CONFIG_M  (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S)
-#define GPIO_PIN4_CONFIG_V  0x00000003U
-#define GPIO_PIN4_CONFIG_S  11
-/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN4_INT_ENA    0x0000001FU
-#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
-#define GPIO_PIN4_INT_ENA_V  0x0000001FU
-#define GPIO_PIN4_INT_ENA_S  13
-
-/** GPIO_PIN5_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88)
-/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
-#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN5_SYNC2_BYPASS_S  0
-/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
-#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN5_PAD_DRIVER_S  2
-/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
-#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN5_SYNC1_BYPASS_S  3
-/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN5_INT_TYPE    0x00000007U
-#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
-#define GPIO_PIN5_INT_TYPE_V  0x00000007U
-#define GPIO_PIN5_INT_TYPE_S  7
-/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
-#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN5_WAKEUP_ENABLE_S  10
-/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN5_CONFIG    0x00000003U
-#define GPIO_PIN5_CONFIG_M  (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S)
-#define GPIO_PIN5_CONFIG_V  0x00000003U
-#define GPIO_PIN5_CONFIG_S  11
-/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN5_INT_ENA    0x0000001FU
-#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
-#define GPIO_PIN5_INT_ENA_V  0x0000001FU
-#define GPIO_PIN5_INT_ENA_S  13
-
-/** GPIO_PIN6_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c)
-/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
-#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN6_SYNC2_BYPASS_S  0
-/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
-#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN6_PAD_DRIVER_S  2
-/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
-#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN6_SYNC1_BYPASS_S  3
-/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN6_INT_TYPE    0x00000007U
-#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
-#define GPIO_PIN6_INT_TYPE_V  0x00000007U
-#define GPIO_PIN6_INT_TYPE_S  7
-/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
-#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN6_WAKEUP_ENABLE_S  10
-/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN6_CONFIG    0x00000003U
-#define GPIO_PIN6_CONFIG_M  (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S)
-#define GPIO_PIN6_CONFIG_V  0x00000003U
-#define GPIO_PIN6_CONFIG_S  11
-/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN6_INT_ENA    0x0000001FU
-#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
-#define GPIO_PIN6_INT_ENA_V  0x0000001FU
-#define GPIO_PIN6_INT_ENA_S  13
-
-/** GPIO_PIN7_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
-/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
-#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN7_SYNC2_BYPASS_S  0
-/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
-#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN7_PAD_DRIVER_S  2
-/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
-#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN7_SYNC1_BYPASS_S  3
-/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN7_INT_TYPE    0x00000007U
-#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
-#define GPIO_PIN7_INT_TYPE_V  0x00000007U
-#define GPIO_PIN7_INT_TYPE_S  7
-/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
-#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN7_WAKEUP_ENABLE_S  10
-/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN7_CONFIG    0x00000003U
-#define GPIO_PIN7_CONFIG_M  (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S)
-#define GPIO_PIN7_CONFIG_V  0x00000003U
-#define GPIO_PIN7_CONFIG_S  11
-/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN7_INT_ENA    0x0000001FU
-#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
-#define GPIO_PIN7_INT_ENA_V  0x0000001FU
-#define GPIO_PIN7_INT_ENA_S  13
-
-/** GPIO_PIN8_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94)
-/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
-#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN8_SYNC2_BYPASS_S  0
-/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
-#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN8_PAD_DRIVER_S  2
-/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
-#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN8_SYNC1_BYPASS_S  3
-/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN8_INT_TYPE    0x00000007U
-#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
-#define GPIO_PIN8_INT_TYPE_V  0x00000007U
-#define GPIO_PIN8_INT_TYPE_S  7
-/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
-#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN8_WAKEUP_ENABLE_S  10
-/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN8_CONFIG    0x00000003U
-#define GPIO_PIN8_CONFIG_M  (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S)
-#define GPIO_PIN8_CONFIG_V  0x00000003U
-#define GPIO_PIN8_CONFIG_S  11
-/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN8_INT_ENA    0x0000001FU
-#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
-#define GPIO_PIN8_INT_ENA_V  0x0000001FU
-#define GPIO_PIN8_INT_ENA_S  13
-
-/** GPIO_PIN9_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98)
-/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
-#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN9_SYNC2_BYPASS_S  0
-/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
-#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN9_PAD_DRIVER_S  2
-/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
-#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN9_SYNC1_BYPASS_S  3
-/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN9_INT_TYPE    0x00000007U
-#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
-#define GPIO_PIN9_INT_TYPE_V  0x00000007U
-#define GPIO_PIN9_INT_TYPE_S  7
-/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
-#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN9_WAKEUP_ENABLE_S  10
-/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN9_CONFIG    0x00000003U
-#define GPIO_PIN9_CONFIG_M  (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S)
-#define GPIO_PIN9_CONFIG_V  0x00000003U
-#define GPIO_PIN9_CONFIG_S  11
-/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN9_INT_ENA    0x0000001FU
-#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
-#define GPIO_PIN9_INT_ENA_V  0x0000001FU
-#define GPIO_PIN9_INT_ENA_S  13
-
-/** GPIO_PIN10_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c)
-/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
-#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN10_SYNC2_BYPASS_S  0
-/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
-#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN10_PAD_DRIVER_S  2
-/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
-#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN10_SYNC1_BYPASS_S  3
-/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN10_INT_TYPE    0x00000007U
-#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
-#define GPIO_PIN10_INT_TYPE_V  0x00000007U
-#define GPIO_PIN10_INT_TYPE_S  7
-/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
-#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN10_WAKEUP_ENABLE_S  10
-/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN10_CONFIG    0x00000003U
-#define GPIO_PIN10_CONFIG_M  (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S)
-#define GPIO_PIN10_CONFIG_V  0x00000003U
-#define GPIO_PIN10_CONFIG_S  11
-/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN10_INT_ENA    0x0000001FU
-#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
-#define GPIO_PIN10_INT_ENA_V  0x0000001FU
-#define GPIO_PIN10_INT_ENA_S  13
-
-/** GPIO_PIN11_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0)
-/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
-#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN11_SYNC2_BYPASS_S  0
-/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
-#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN11_PAD_DRIVER_S  2
-/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
-#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN11_SYNC1_BYPASS_S  3
-/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN11_INT_TYPE    0x00000007U
-#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
-#define GPIO_PIN11_INT_TYPE_V  0x00000007U
-#define GPIO_PIN11_INT_TYPE_S  7
-/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
-#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN11_WAKEUP_ENABLE_S  10
-/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN11_CONFIG    0x00000003U
-#define GPIO_PIN11_CONFIG_M  (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S)
-#define GPIO_PIN11_CONFIG_V  0x00000003U
-#define GPIO_PIN11_CONFIG_S  11
-/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN11_INT_ENA    0x0000001FU
-#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
-#define GPIO_PIN11_INT_ENA_V  0x0000001FU
-#define GPIO_PIN11_INT_ENA_S  13
-
-/** GPIO_PIN12_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4)
-/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
-#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN12_SYNC2_BYPASS_S  0
-/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
-#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN12_PAD_DRIVER_S  2
-/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
-#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN12_SYNC1_BYPASS_S  3
-/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN12_INT_TYPE    0x00000007U
-#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
-#define GPIO_PIN12_INT_TYPE_V  0x00000007U
-#define GPIO_PIN12_INT_TYPE_S  7
-/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
-#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN12_WAKEUP_ENABLE_S  10
-/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN12_CONFIG    0x00000003U
-#define GPIO_PIN12_CONFIG_M  (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S)
-#define GPIO_PIN12_CONFIG_V  0x00000003U
-#define GPIO_PIN12_CONFIG_S  11
-/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN12_INT_ENA    0x0000001FU
-#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
-#define GPIO_PIN12_INT_ENA_V  0x0000001FU
-#define GPIO_PIN12_INT_ENA_S  13
-
-/** GPIO_PIN13_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8)
-/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
-#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN13_SYNC2_BYPASS_S  0
-/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
-#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN13_PAD_DRIVER_S  2
-/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
-#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN13_SYNC1_BYPASS_S  3
-/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN13_INT_TYPE    0x00000007U
-#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
-#define GPIO_PIN13_INT_TYPE_V  0x00000007U
-#define GPIO_PIN13_INT_TYPE_S  7
-/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
-#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN13_WAKEUP_ENABLE_S  10
-/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN13_CONFIG    0x00000003U
-#define GPIO_PIN13_CONFIG_M  (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S)
-#define GPIO_PIN13_CONFIG_V  0x00000003U
-#define GPIO_PIN13_CONFIG_S  11
-/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN13_INT_ENA    0x0000001FU
-#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
-#define GPIO_PIN13_INT_ENA_V  0x0000001FU
-#define GPIO_PIN13_INT_ENA_S  13
-
-/** GPIO_PIN14_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac)
-/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
-#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN14_SYNC2_BYPASS_S  0
-/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
-#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN14_PAD_DRIVER_S  2
-/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
-#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN14_SYNC1_BYPASS_S  3
-/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN14_INT_TYPE    0x00000007U
-#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
-#define GPIO_PIN14_INT_TYPE_V  0x00000007U
-#define GPIO_PIN14_INT_TYPE_S  7
-/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
-#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN14_WAKEUP_ENABLE_S  10
-/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN14_CONFIG    0x00000003U
-#define GPIO_PIN14_CONFIG_M  (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S)
-#define GPIO_PIN14_CONFIG_V  0x00000003U
-#define GPIO_PIN14_CONFIG_S  11
-/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN14_INT_ENA    0x0000001FU
-#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
-#define GPIO_PIN14_INT_ENA_V  0x0000001FU
-#define GPIO_PIN14_INT_ENA_S  13
-
-/** GPIO_PIN15_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0)
-/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
-#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN15_SYNC2_BYPASS_S  0
-/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
-#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN15_PAD_DRIVER_S  2
-/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
-#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN15_SYNC1_BYPASS_S  3
-/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN15_INT_TYPE    0x00000007U
-#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
-#define GPIO_PIN15_INT_TYPE_V  0x00000007U
-#define GPIO_PIN15_INT_TYPE_S  7
-/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
-#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN15_WAKEUP_ENABLE_S  10
-/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN15_CONFIG    0x00000003U
-#define GPIO_PIN15_CONFIG_M  (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S)
-#define GPIO_PIN15_CONFIG_V  0x00000003U
-#define GPIO_PIN15_CONFIG_S  11
-/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN15_INT_ENA    0x0000001FU
-#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
-#define GPIO_PIN15_INT_ENA_V  0x0000001FU
-#define GPIO_PIN15_INT_ENA_S  13
-
-/** GPIO_PIN16_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4)
-/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
-#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN16_SYNC2_BYPASS_S  0
-/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
-#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN16_PAD_DRIVER_S  2
-/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
-#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN16_SYNC1_BYPASS_S  3
-/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN16_INT_TYPE    0x00000007U
-#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
-#define GPIO_PIN16_INT_TYPE_V  0x00000007U
-#define GPIO_PIN16_INT_TYPE_S  7
-/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
-#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN16_WAKEUP_ENABLE_S  10
-/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN16_CONFIG    0x00000003U
-#define GPIO_PIN16_CONFIG_M  (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S)
-#define GPIO_PIN16_CONFIG_V  0x00000003U
-#define GPIO_PIN16_CONFIG_S  11
-/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN16_INT_ENA    0x0000001FU
-#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
-#define GPIO_PIN16_INT_ENA_V  0x0000001FU
-#define GPIO_PIN16_INT_ENA_S  13
-
-/** GPIO_PIN17_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8)
-/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
-#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN17_SYNC2_BYPASS_S  0
-/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
-#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN17_PAD_DRIVER_S  2
-/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
-#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN17_SYNC1_BYPASS_S  3
-/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN17_INT_TYPE    0x00000007U
-#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
-#define GPIO_PIN17_INT_TYPE_V  0x00000007U
-#define GPIO_PIN17_INT_TYPE_S  7
-/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
-#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN17_WAKEUP_ENABLE_S  10
-/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN17_CONFIG    0x00000003U
-#define GPIO_PIN17_CONFIG_M  (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S)
-#define GPIO_PIN17_CONFIG_V  0x00000003U
-#define GPIO_PIN17_CONFIG_S  11
-/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN17_INT_ENA    0x0000001FU
-#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
-#define GPIO_PIN17_INT_ENA_V  0x0000001FU
-#define GPIO_PIN17_INT_ENA_S  13
-
-/** GPIO_PIN18_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc)
-/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
-#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN18_SYNC2_BYPASS_S  0
-/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
-#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN18_PAD_DRIVER_S  2
-/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
-#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN18_SYNC1_BYPASS_S  3
-/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN18_INT_TYPE    0x00000007U
-#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
-#define GPIO_PIN18_INT_TYPE_V  0x00000007U
-#define GPIO_PIN18_INT_TYPE_S  7
-/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
-#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN18_WAKEUP_ENABLE_S  10
-/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN18_CONFIG    0x00000003U
-#define GPIO_PIN18_CONFIG_M  (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S)
-#define GPIO_PIN18_CONFIG_V  0x00000003U
-#define GPIO_PIN18_CONFIG_S  11
-/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN18_INT_ENA    0x0000001FU
-#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
-#define GPIO_PIN18_INT_ENA_V  0x0000001FU
-#define GPIO_PIN18_INT_ENA_S  13
-
-/** GPIO_PIN19_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0)
-/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
-#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN19_SYNC2_BYPASS_S  0
-/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
-#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN19_PAD_DRIVER_S  2
-/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
-#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN19_SYNC1_BYPASS_S  3
-/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN19_INT_TYPE    0x00000007U
-#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
-#define GPIO_PIN19_INT_TYPE_V  0x00000007U
-#define GPIO_PIN19_INT_TYPE_S  7
-/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
-#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN19_WAKEUP_ENABLE_S  10
-/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN19_CONFIG    0x00000003U
-#define GPIO_PIN19_CONFIG_M  (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S)
-#define GPIO_PIN19_CONFIG_V  0x00000003U
-#define GPIO_PIN19_CONFIG_S  11
-/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN19_INT_ENA    0x0000001FU
-#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
-#define GPIO_PIN19_INT_ENA_V  0x0000001FU
-#define GPIO_PIN19_INT_ENA_S  13
-
-/** GPIO_PIN20_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4)
-/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
-#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN20_SYNC2_BYPASS_S  0
-/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
-#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN20_PAD_DRIVER_S  2
-/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
-#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN20_SYNC1_BYPASS_S  3
-/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN20_INT_TYPE    0x00000007U
-#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
-#define GPIO_PIN20_INT_TYPE_V  0x00000007U
-#define GPIO_PIN20_INT_TYPE_S  7
-/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
-#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN20_WAKEUP_ENABLE_S  10
-/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN20_CONFIG    0x00000003U
-#define GPIO_PIN20_CONFIG_M  (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S)
-#define GPIO_PIN20_CONFIG_V  0x00000003U
-#define GPIO_PIN20_CONFIG_S  11
-/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN20_INT_ENA    0x0000001FU
-#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
-#define GPIO_PIN20_INT_ENA_V  0x0000001FU
-#define GPIO_PIN20_INT_ENA_S  13
-
-/** GPIO_PIN21_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8)
-/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
-#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN21_SYNC2_BYPASS_S  0
-/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
-#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN21_PAD_DRIVER_S  2
-/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
-#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN21_SYNC1_BYPASS_S  3
-/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN21_INT_TYPE    0x00000007U
-#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
-#define GPIO_PIN21_INT_TYPE_V  0x00000007U
-#define GPIO_PIN21_INT_TYPE_S  7
-/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
-#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN21_WAKEUP_ENABLE_S  10
-/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN21_CONFIG    0x00000003U
-#define GPIO_PIN21_CONFIG_M  (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S)
-#define GPIO_PIN21_CONFIG_V  0x00000003U
-#define GPIO_PIN21_CONFIG_S  11
-/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN21_INT_ENA    0x0000001FU
-#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
-#define GPIO_PIN21_INT_ENA_V  0x0000001FU
-#define GPIO_PIN21_INT_ENA_S  13
-
-/** GPIO_PIN22_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc)
-/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
-#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN22_SYNC2_BYPASS_S  0
-/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
-#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN22_PAD_DRIVER_S  2
-/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
-#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN22_SYNC1_BYPASS_S  3
-/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN22_INT_TYPE    0x00000007U
-#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
-#define GPIO_PIN22_INT_TYPE_V  0x00000007U
-#define GPIO_PIN22_INT_TYPE_S  7
-/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
-#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN22_WAKEUP_ENABLE_S  10
-/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN22_CONFIG    0x00000003U
-#define GPIO_PIN22_CONFIG_M  (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S)
-#define GPIO_PIN22_CONFIG_V  0x00000003U
-#define GPIO_PIN22_CONFIG_S  11
-/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN22_INT_ENA    0x0000001FU
-#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
-#define GPIO_PIN22_INT_ENA_V  0x0000001FU
-#define GPIO_PIN22_INT_ENA_S  13
-
-/** GPIO_PIN23_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0)
-/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
-#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN23_SYNC2_BYPASS_S  0
-/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
-#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN23_PAD_DRIVER_S  2
-/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
-#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN23_SYNC1_BYPASS_S  3
-/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN23_INT_TYPE    0x00000007U
-#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
-#define GPIO_PIN23_INT_TYPE_V  0x00000007U
-#define GPIO_PIN23_INT_TYPE_S  7
-/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
-#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN23_WAKEUP_ENABLE_S  10
-/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN23_CONFIG    0x00000003U
-#define GPIO_PIN23_CONFIG_M  (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S)
-#define GPIO_PIN23_CONFIG_V  0x00000003U
-#define GPIO_PIN23_CONFIG_S  11
-/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN23_INT_ENA    0x0000001FU
-#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
-#define GPIO_PIN23_INT_ENA_V  0x0000001FU
-#define GPIO_PIN23_INT_ENA_S  13
-
-/** GPIO_PIN24_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4)
-/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
-#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN24_SYNC2_BYPASS_S  0
-/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
-#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN24_PAD_DRIVER_S  2
-/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
-#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN24_SYNC1_BYPASS_S  3
-/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN24_INT_TYPE    0x00000007U
-#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
-#define GPIO_PIN24_INT_TYPE_V  0x00000007U
-#define GPIO_PIN24_INT_TYPE_S  7
-/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
-#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN24_WAKEUP_ENABLE_S  10
-/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN24_CONFIG    0x00000003U
-#define GPIO_PIN24_CONFIG_M  (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S)
-#define GPIO_PIN24_CONFIG_V  0x00000003U
-#define GPIO_PIN24_CONFIG_S  11
-/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN24_INT_ENA    0x0000001FU
-#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
-#define GPIO_PIN24_INT_ENA_V  0x0000001FU
-#define GPIO_PIN24_INT_ENA_S  13
-
-/** GPIO_PIN25_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8)
-/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN25_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN25_SYNC2_BYPASS_M  (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
-#define GPIO_PIN25_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN25_SYNC2_BYPASS_S  0
-/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_M  (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
-#define GPIO_PIN25_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN25_PAD_DRIVER_S  2
-/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN25_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN25_SYNC1_BYPASS_M  (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
-#define GPIO_PIN25_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN25_SYNC1_BYPASS_S  3
-/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN25_INT_TYPE    0x00000007U
-#define GPIO_PIN25_INT_TYPE_M  (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
-#define GPIO_PIN25_INT_TYPE_V  0x00000007U
-#define GPIO_PIN25_INT_TYPE_S  7
-/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_M  (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
-#define GPIO_PIN25_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN25_WAKEUP_ENABLE_S  10
-/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN25_CONFIG    0x00000003U
-#define GPIO_PIN25_CONFIG_M  (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S)
-#define GPIO_PIN25_CONFIG_V  0x00000003U
-#define GPIO_PIN25_CONFIG_S  11
-/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN25_INT_ENA    0x0000001FU
-#define GPIO_PIN25_INT_ENA_M  (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
-#define GPIO_PIN25_INT_ENA_V  0x0000001FU
-#define GPIO_PIN25_INT_ENA_S  13
-
-/** GPIO_PIN26_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc)
-/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN26_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN26_SYNC2_BYPASS_M  (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
-#define GPIO_PIN26_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN26_SYNC2_BYPASS_S  0
-/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN26_PAD_DRIVER_M  (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
-#define GPIO_PIN26_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN26_PAD_DRIVER_S  2
-/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN26_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN26_SYNC1_BYPASS_M  (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
-#define GPIO_PIN26_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN26_SYNC1_BYPASS_S  3
-/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN26_INT_TYPE    0x00000007U
-#define GPIO_PIN26_INT_TYPE_M  (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
-#define GPIO_PIN26_INT_TYPE_V  0x00000007U
-#define GPIO_PIN26_INT_TYPE_S  7
-/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN26_WAKEUP_ENABLE_M  (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
-#define GPIO_PIN26_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN26_WAKEUP_ENABLE_S  10
-/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN26_CONFIG    0x00000003U
-#define GPIO_PIN26_CONFIG_M  (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S)
-#define GPIO_PIN26_CONFIG_V  0x00000003U
-#define GPIO_PIN26_CONFIG_S  11
-/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN26_INT_ENA    0x0000001FU
-#define GPIO_PIN26_INT_ENA_M  (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
-#define GPIO_PIN26_INT_ENA_V  0x0000001FU
-#define GPIO_PIN26_INT_ENA_S  13
-
-/** GPIO_PIN27_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0)
-/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN27_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN27_SYNC2_BYPASS_M  (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
-#define GPIO_PIN27_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN27_SYNC2_BYPASS_S  0
-/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN27_PAD_DRIVER_M  (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
-#define GPIO_PIN27_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN27_PAD_DRIVER_S  2
-/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN27_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN27_SYNC1_BYPASS_M  (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
-#define GPIO_PIN27_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN27_SYNC1_BYPASS_S  3
-/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN27_INT_TYPE    0x00000007U
-#define GPIO_PIN27_INT_TYPE_M  (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
-#define GPIO_PIN27_INT_TYPE_V  0x00000007U
-#define GPIO_PIN27_INT_TYPE_S  7
-/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN27_WAKEUP_ENABLE_M  (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
-#define GPIO_PIN27_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN27_WAKEUP_ENABLE_S  10
-/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN27_CONFIG    0x00000003U
-#define GPIO_PIN27_CONFIG_M  (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S)
-#define GPIO_PIN27_CONFIG_V  0x00000003U
-#define GPIO_PIN27_CONFIG_S  11
-/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN27_INT_ENA    0x0000001FU
-#define GPIO_PIN27_INT_ENA_M  (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
-#define GPIO_PIN27_INT_ENA_V  0x0000001FU
-#define GPIO_PIN27_INT_ENA_S  13
-
-/** GPIO_PIN28_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4)
-/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN28_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN28_SYNC2_BYPASS_M  (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
-#define GPIO_PIN28_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN28_SYNC2_BYPASS_S  0
-/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN28_PAD_DRIVER_M  (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
-#define GPIO_PIN28_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN28_PAD_DRIVER_S  2
-/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN28_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN28_SYNC1_BYPASS_M  (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
-#define GPIO_PIN28_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN28_SYNC1_BYPASS_S  3
-/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN28_INT_TYPE    0x00000007U
-#define GPIO_PIN28_INT_TYPE_M  (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
-#define GPIO_PIN28_INT_TYPE_V  0x00000007U
-#define GPIO_PIN28_INT_TYPE_S  7
-/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN28_WAKEUP_ENABLE_M  (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
-#define GPIO_PIN28_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN28_WAKEUP_ENABLE_S  10
-/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN28_CONFIG    0x00000003U
-#define GPIO_PIN28_CONFIG_M  (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S)
-#define GPIO_PIN28_CONFIG_V  0x00000003U
-#define GPIO_PIN28_CONFIG_S  11
-/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN28_INT_ENA    0x0000001FU
-#define GPIO_PIN28_INT_ENA_M  (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
-#define GPIO_PIN28_INT_ENA_V  0x0000001FU
-#define GPIO_PIN28_INT_ENA_S  13
-
-/** GPIO_PIN29_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8)
-/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN29_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN29_SYNC2_BYPASS_M  (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S)
-#define GPIO_PIN29_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN29_SYNC2_BYPASS_S  0
-/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN29_PAD_DRIVER_M  (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S)
-#define GPIO_PIN29_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN29_PAD_DRIVER_S  2
-/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN29_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN29_SYNC1_BYPASS_M  (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S)
-#define GPIO_PIN29_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN29_SYNC1_BYPASS_S  3
-/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN29_INT_TYPE    0x00000007U
-#define GPIO_PIN29_INT_TYPE_M  (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S)
-#define GPIO_PIN29_INT_TYPE_V  0x00000007U
-#define GPIO_PIN29_INT_TYPE_S  7
-/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN29_WAKEUP_ENABLE_M  (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S)
-#define GPIO_PIN29_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN29_WAKEUP_ENABLE_S  10
-/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN29_CONFIG    0x00000003U
-#define GPIO_PIN29_CONFIG_M  (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S)
-#define GPIO_PIN29_CONFIG_V  0x00000003U
-#define GPIO_PIN29_CONFIG_S  11
-/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN29_INT_ENA    0x0000001FU
-#define GPIO_PIN29_INT_ENA_M  (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S)
-#define GPIO_PIN29_INT_ENA_V  0x0000001FU
-#define GPIO_PIN29_INT_ENA_S  13
-
-/** GPIO_PIN30_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec)
-/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN30_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN30_SYNC2_BYPASS_M  (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S)
-#define GPIO_PIN30_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN30_SYNC2_BYPASS_S  0
-/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN30_PAD_DRIVER_M  (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S)
-#define GPIO_PIN30_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN30_PAD_DRIVER_S  2
-/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN30_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN30_SYNC1_BYPASS_M  (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S)
-#define GPIO_PIN30_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN30_SYNC1_BYPASS_S  3
-/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN30_INT_TYPE    0x00000007U
-#define GPIO_PIN30_INT_TYPE_M  (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S)
-#define GPIO_PIN30_INT_TYPE_V  0x00000007U
-#define GPIO_PIN30_INT_TYPE_S  7
-/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN30_WAKEUP_ENABLE_M  (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S)
-#define GPIO_PIN30_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN30_WAKEUP_ENABLE_S  10
-/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN30_CONFIG    0x00000003U
-#define GPIO_PIN30_CONFIG_M  (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S)
-#define GPIO_PIN30_CONFIG_V  0x00000003U
-#define GPIO_PIN30_CONFIG_S  11
-/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN30_INT_ENA    0x0000001FU
-#define GPIO_PIN30_INT_ENA_M  (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S)
-#define GPIO_PIN30_INT_ENA_V  0x0000001FU
-#define GPIO_PIN30_INT_ENA_S  13
-
-/** GPIO_STATUS_NEXT_REG register
- *  GPIO interrupt source register for GPIO0-31
- */
-#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c)
-/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [30:0]; default: 0;
- *  GPIO interrupt source register for GPIO0-31
- */
-#define GPIO_STATUS_INTERRUPT_NEXT    0x7FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
-#define GPIO_STATUS_INTERRUPT_NEXT_V  0x7FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT_S  0
-
-/** GPIO_FUNC0_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154)
-/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC0_IN_SEL    0x0000003FU
-#define GPIO_FUNC0_IN_SEL_M  (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S)
-#define GPIO_FUNC0_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC0_IN_SEL_S  0
-/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC0_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC0_IN_INV_SEL_M  (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S)
-#define GPIO_FUNC0_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_IN_INV_SEL_S  6
-/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG0_IN_SEL    (BIT(7))
-#define GPIO_SIG0_IN_SEL_M  (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S)
-#define GPIO_SIG0_IN_SEL_V  0x00000001U
-#define GPIO_SIG0_IN_SEL_S  7
-
-/** GPIO_FUNC6_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
-/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC6_IN_SEL    0x0000003FU
-#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
-#define GPIO_FUNC6_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC6_IN_SEL_S  0
-/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
-#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_IN_INV_SEL_S  6
-/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG6_IN_SEL    (BIT(7))
-#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
-#define GPIO_SIG6_IN_SEL_V  0x00000001U
-#define GPIO_SIG6_IN_SEL_S  7
-
-/** GPIO_FUNC7_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170)
-/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC7_IN_SEL    0x0000003FU
-#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
-#define GPIO_FUNC7_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC7_IN_SEL_S  0
-/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
-#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_IN_INV_SEL_S  6
-/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG7_IN_SEL    (BIT(7))
-#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
-#define GPIO_SIG7_IN_SEL_V  0x00000001U
-#define GPIO_SIG7_IN_SEL_S  7
-
-/** GPIO_FUNC8_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174)
-/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC8_IN_SEL    0x0000003FU
-#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
-#define GPIO_FUNC8_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC8_IN_SEL_S  0
-/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
-#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_IN_INV_SEL_S  6
-/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG8_IN_SEL    (BIT(7))
-#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
-#define GPIO_SIG8_IN_SEL_V  0x00000001U
-#define GPIO_SIG8_IN_SEL_S  7
-
-/** GPIO_FUNC9_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178)
-/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 56;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC9_IN_SEL    0x0000003FU
-#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
-#define GPIO_FUNC9_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC9_IN_SEL_S  0
-/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
-#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_IN_INV_SEL_S  6
-/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG9_IN_SEL    (BIT(7))
-#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
-#define GPIO_SIG9_IN_SEL_V  0x00000001U
-#define GPIO_SIG9_IN_SEL_S  7
-
-/** GPIO_FUNC10_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c)
-/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC10_IN_SEL    0x0000003FU
-#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
-#define GPIO_FUNC10_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC10_IN_SEL_S  0
-/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
-#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_IN_INV_SEL_S  6
-/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG10_IN_SEL    (BIT(7))
-#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
-#define GPIO_SIG10_IN_SEL_V  0x00000001U
-#define GPIO_SIG10_IN_SEL_S  7
-
-/** GPIO_FUNC11_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180)
-/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC11_IN_SEL    0x0000003FU
-#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
-#define GPIO_FUNC11_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC11_IN_SEL_S  0
-/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
-#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_IN_INV_SEL_S  6
-/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG11_IN_SEL    (BIT(7))
-#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
-#define GPIO_SIG11_IN_SEL_V  0x00000001U
-#define GPIO_SIG11_IN_SEL_S  7
-
-/** GPIO_FUNC12_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184)
-/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC12_IN_SEL    0x0000003FU
-#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
-#define GPIO_FUNC12_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC12_IN_SEL_S  0
-/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
-#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_IN_INV_SEL_S  6
-/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG12_IN_SEL    (BIT(7))
-#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
-#define GPIO_SIG12_IN_SEL_V  0x00000001U
-#define GPIO_SIG12_IN_SEL_S  7
-
-/** GPIO_FUNC13_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188)
-/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC13_IN_SEL    0x0000003FU
-#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
-#define GPIO_FUNC13_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC13_IN_SEL_S  0
-/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
-#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_IN_INV_SEL_S  6
-/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG13_IN_SEL    (BIT(7))
-#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
-#define GPIO_SIG13_IN_SEL_V  0x00000001U
-#define GPIO_SIG13_IN_SEL_S  7
-
-/** GPIO_FUNC14_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c)
-/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC14_IN_SEL    0x0000003FU
-#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
-#define GPIO_FUNC14_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC14_IN_SEL_S  0
-/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
-#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_IN_INV_SEL_S  6
-/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG14_IN_SEL    (BIT(7))
-#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
-#define GPIO_SIG14_IN_SEL_V  0x00000001U
-#define GPIO_SIG14_IN_SEL_S  7
-
-/** GPIO_FUNC15_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190)
-/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC15_IN_SEL    0x0000003FU
-#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
-#define GPIO_FUNC15_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC15_IN_SEL_S  0
-/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
-#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_IN_INV_SEL_S  6
-/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG15_IN_SEL    (BIT(7))
-#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
-#define GPIO_SIG15_IN_SEL_V  0x00000001U
-#define GPIO_SIG15_IN_SEL_S  7
-
-/** GPIO_FUNC16_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194)
-/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC16_IN_SEL    0x0000003FU
-#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
-#define GPIO_FUNC16_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC16_IN_SEL_S  0
-/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
-#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_IN_INV_SEL_S  6
-/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG16_IN_SEL    (BIT(7))
-#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
-#define GPIO_SIG16_IN_SEL_V  0x00000001U
-#define GPIO_SIG16_IN_SEL_S  7
-
-/** GPIO_FUNC17_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198)
-/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC17_IN_SEL    0x0000003FU
-#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
-#define GPIO_FUNC17_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC17_IN_SEL_S  0
-/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
-#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_IN_INV_SEL_S  6
-/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG17_IN_SEL    (BIT(7))
-#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
-#define GPIO_SIG17_IN_SEL_V  0x00000001U
-#define GPIO_SIG17_IN_SEL_S  7
-
-/** GPIO_FUNC19_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0)
-/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC19_IN_SEL    0x0000003FU
-#define GPIO_FUNC19_IN_SEL_M  (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S)
-#define GPIO_FUNC19_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC19_IN_SEL_S  0
-/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC19_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC19_IN_INV_SEL_M  (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S)
-#define GPIO_FUNC19_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_IN_INV_SEL_S  6
-/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG19_IN_SEL    (BIT(7))
-#define GPIO_SIG19_IN_SEL_M  (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S)
-#define GPIO_SIG19_IN_SEL_V  0x00000001U
-#define GPIO_SIG19_IN_SEL_S  7
-
-/** GPIO_FUNC21_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8)
-/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC21_IN_SEL    0x0000003FU
-#define GPIO_FUNC21_IN_SEL_M  (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S)
-#define GPIO_FUNC21_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC21_IN_SEL_S  0
-/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC21_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC21_IN_INV_SEL_M  (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S)
-#define GPIO_FUNC21_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_IN_INV_SEL_S  6
-/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG21_IN_SEL    (BIT(7))
-#define GPIO_SIG21_IN_SEL_M  (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S)
-#define GPIO_SIG21_IN_SEL_V  0x00000001U
-#define GPIO_SIG21_IN_SEL_S  7
-
-/** GPIO_FUNC22_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac)
-/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC22_IN_SEL    0x0000003FU
-#define GPIO_FUNC22_IN_SEL_M  (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S)
-#define GPIO_FUNC22_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC22_IN_SEL_S  0
-/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC22_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC22_IN_INV_SEL_M  (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S)
-#define GPIO_FUNC22_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC22_IN_INV_SEL_S  6
-/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG22_IN_SEL    (BIT(7))
-#define GPIO_SIG22_IN_SEL_M  (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S)
-#define GPIO_SIG22_IN_SEL_V  0x00000001U
-#define GPIO_SIG22_IN_SEL_S  7
-
-/** GPIO_FUNC23_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0)
-/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC23_IN_SEL    0x0000003FU
-#define GPIO_FUNC23_IN_SEL_M  (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S)
-#define GPIO_FUNC23_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC23_IN_SEL_S  0
-/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC23_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC23_IN_INV_SEL_M  (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S)
-#define GPIO_FUNC23_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC23_IN_INV_SEL_S  6
-/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG23_IN_SEL    (BIT(7))
-#define GPIO_SIG23_IN_SEL_M  (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S)
-#define GPIO_SIG23_IN_SEL_V  0x00000001U
-#define GPIO_SIG23_IN_SEL_S  7
-
-/** GPIO_FUNC24_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4)
-/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC24_IN_SEL    0x0000003FU
-#define GPIO_FUNC24_IN_SEL_M  (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S)
-#define GPIO_FUNC24_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC24_IN_SEL_S  0
-/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC24_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC24_IN_INV_SEL_M  (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S)
-#define GPIO_FUNC24_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC24_IN_INV_SEL_S  6
-/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG24_IN_SEL    (BIT(7))
-#define GPIO_SIG24_IN_SEL_M  (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S)
-#define GPIO_SIG24_IN_SEL_V  0x00000001U
-#define GPIO_SIG24_IN_SEL_S  7
-
-/** GPIO_FUNC28_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4)
-/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC28_IN_SEL    0x0000003FU
-#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
-#define GPIO_FUNC28_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC28_IN_SEL_S  0
-/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
-#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC28_IN_INV_SEL_S  6
-/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG28_IN_SEL    (BIT(7))
-#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
-#define GPIO_SIG28_IN_SEL_V  0x00000001U
-#define GPIO_SIG28_IN_SEL_S  7
-
-/** GPIO_FUNC29_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8)
-/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC29_IN_SEL    0x0000003FU
-#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
-#define GPIO_FUNC29_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC29_IN_SEL_S  0
-/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
-#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC29_IN_INV_SEL_S  6
-/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG29_IN_SEL    (BIT(7))
-#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
-#define GPIO_SIG29_IN_SEL_V  0x00000001U
-#define GPIO_SIG29_IN_SEL_S  7
-
-/** GPIO_FUNC30_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc)
-/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC30_IN_SEL    0x0000003FU
-#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
-#define GPIO_FUNC30_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC30_IN_SEL_S  0
-/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
-#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC30_IN_INV_SEL_S  6
-/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG30_IN_SEL    (BIT(7))
-#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
-#define GPIO_SIG30_IN_SEL_V  0x00000001U
-#define GPIO_SIG30_IN_SEL_S  7
-
-/** GPIO_FUNC31_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0)
-/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC31_IN_SEL    0x0000003FU
-#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
-#define GPIO_FUNC31_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC31_IN_SEL_S  0
-/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
-#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC31_IN_INV_SEL_S  6
-/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG31_IN_SEL    (BIT(7))
-#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
-#define GPIO_SIG31_IN_SEL_V  0x00000001U
-#define GPIO_SIG31_IN_SEL_S  7
-
-/** GPIO_FUNC32_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4)
-/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC32_IN_SEL    0x0000003FU
-#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
-#define GPIO_FUNC32_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC32_IN_SEL_S  0
-/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
-#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC32_IN_INV_SEL_S  6
-/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG32_IN_SEL    (BIT(7))
-#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
-#define GPIO_SIG32_IN_SEL_V  0x00000001U
-#define GPIO_SIG32_IN_SEL_S  7
-
-/** GPIO_FUNC33_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8)
-/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC33_IN_SEL    0x0000003FU
-#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
-#define GPIO_FUNC33_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC33_IN_SEL_S  0
-/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
-#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC33_IN_INV_SEL_S  6
-/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG33_IN_SEL    (BIT(7))
-#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
-#define GPIO_SIG33_IN_SEL_V  0x00000001U
-#define GPIO_SIG33_IN_SEL_S  7
-
-/** GPIO_FUNC34_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc)
-/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC34_IN_SEL    0x0000003FU
-#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
-#define GPIO_FUNC34_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC34_IN_SEL_S  0
-/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
-#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC34_IN_INV_SEL_S  6
-/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG34_IN_SEL    (BIT(7))
-#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
-#define GPIO_SIG34_IN_SEL_V  0x00000001U
-#define GPIO_SIG34_IN_SEL_S  7
-
-/** GPIO_FUNC35_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0)
-/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC35_IN_SEL    0x0000003FU
-#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
-#define GPIO_FUNC35_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC35_IN_SEL_S  0
-/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
-#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC35_IN_INV_SEL_S  6
-/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG35_IN_SEL    (BIT(7))
-#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
-#define GPIO_SIG35_IN_SEL_V  0x00000001U
-#define GPIO_SIG35_IN_SEL_S  7
-
-/** GPIO_FUNC40_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4)
-/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC40_IN_SEL    0x0000003FU
-#define GPIO_FUNC40_IN_SEL_M  (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S)
-#define GPIO_FUNC40_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC40_IN_SEL_S  0
-/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC40_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC40_IN_INV_SEL_M  (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S)
-#define GPIO_FUNC40_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC40_IN_INV_SEL_S  6
-/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG40_IN_SEL    (BIT(7))
-#define GPIO_SIG40_IN_SEL_M  (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S)
-#define GPIO_SIG40_IN_SEL_V  0x00000001U
-#define GPIO_SIG40_IN_SEL_S  7
-
-/** GPIO_FUNC41_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8)
-/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC41_IN_SEL    0x0000003FU
-#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
-#define GPIO_FUNC41_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC41_IN_SEL_S  0
-/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
-#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC41_IN_INV_SEL_S  6
-/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG41_IN_SEL    (BIT(7))
-#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
-#define GPIO_SIG41_IN_SEL_V  0x00000001U
-#define GPIO_SIG41_IN_SEL_S  7
-
-/** GPIO_FUNC42_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc)
-/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC42_IN_SEL    0x0000003FU
-#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
-#define GPIO_FUNC42_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC42_IN_SEL_S  0
-/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
-#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC42_IN_INV_SEL_S  6
-/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG42_IN_SEL    (BIT(7))
-#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
-#define GPIO_SIG42_IN_SEL_V  0x00000001U
-#define GPIO_SIG42_IN_SEL_S  7
-
-/** GPIO_FUNC45_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208)
-/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 56;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC45_IN_SEL    0x0000003FU
-#define GPIO_FUNC45_IN_SEL_M  (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S)
-#define GPIO_FUNC45_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC45_IN_SEL_S  0
-/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC45_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC45_IN_INV_SEL_M  (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S)
-#define GPIO_FUNC45_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC45_IN_INV_SEL_S  6
-/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG45_IN_SEL    (BIT(7))
-#define GPIO_SIG45_IN_SEL_M  (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S)
-#define GPIO_SIG45_IN_SEL_V  0x00000001U
-#define GPIO_SIG45_IN_SEL_S  7
-
-/** GPIO_FUNC46_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c)
-/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 56;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC46_IN_SEL    0x0000003FU
-#define GPIO_FUNC46_IN_SEL_M  (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S)
-#define GPIO_FUNC46_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC46_IN_SEL_S  0
-/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC46_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC46_IN_INV_SEL_M  (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S)
-#define GPIO_FUNC46_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC46_IN_INV_SEL_S  6
-/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG46_IN_SEL    (BIT(7))
-#define GPIO_SIG46_IN_SEL_M  (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S)
-#define GPIO_SIG46_IN_SEL_V  0x00000001U
-#define GPIO_SIG46_IN_SEL_S  7
-
-/** GPIO_FUNC47_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210)
-/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC47_IN_SEL    0x0000003FU
-#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
-#define GPIO_FUNC47_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC47_IN_SEL_S  0
-/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
-#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC47_IN_INV_SEL_S  6
-/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG47_IN_SEL    (BIT(7))
-#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
-#define GPIO_SIG47_IN_SEL_V  0x00000001U
-#define GPIO_SIG47_IN_SEL_S  7
-
-/** GPIO_FUNC48_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214)
-/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC48_IN_SEL    0x0000003FU
-#define GPIO_FUNC48_IN_SEL_M  (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S)
-#define GPIO_FUNC48_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC48_IN_SEL_S  0
-/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC48_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC48_IN_INV_SEL_M  (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S)
-#define GPIO_FUNC48_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC48_IN_INV_SEL_S  6
-/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG48_IN_SEL    (BIT(7))
-#define GPIO_SIG48_IN_SEL_M  (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S)
-#define GPIO_SIG48_IN_SEL_V  0x00000001U
-#define GPIO_SIG48_IN_SEL_S  7
-
-/** GPIO_FUNC49_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218)
-/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC49_IN_SEL    0x0000003FU
-#define GPIO_FUNC49_IN_SEL_M  (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S)
-#define GPIO_FUNC49_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC49_IN_SEL_S  0
-/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC49_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC49_IN_INV_SEL_M  (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S)
-#define GPIO_FUNC49_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC49_IN_INV_SEL_S  6
-/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG49_IN_SEL    (BIT(7))
-#define GPIO_SIG49_IN_SEL_M  (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S)
-#define GPIO_SIG49_IN_SEL_V  0x00000001U
-#define GPIO_SIG49_IN_SEL_S  7
-
-/** GPIO_FUNC50_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c)
-/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC50_IN_SEL    0x0000003FU
-#define GPIO_FUNC50_IN_SEL_M  (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S)
-#define GPIO_FUNC50_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC50_IN_SEL_S  0
-/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC50_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC50_IN_INV_SEL_M  (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S)
-#define GPIO_FUNC50_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC50_IN_INV_SEL_S  6
-/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG50_IN_SEL    (BIT(7))
-#define GPIO_SIG50_IN_SEL_M  (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S)
-#define GPIO_SIG50_IN_SEL_V  0x00000001U
-#define GPIO_SIG50_IN_SEL_S  7
-
-/** GPIO_FUNC51_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220)
-/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC51_IN_SEL    0x0000003FU
-#define GPIO_FUNC51_IN_SEL_M  (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S)
-#define GPIO_FUNC51_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC51_IN_SEL_S  0
-/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC51_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC51_IN_INV_SEL_M  (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S)
-#define GPIO_FUNC51_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC51_IN_INV_SEL_S  6
-/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG51_IN_SEL    (BIT(7))
-#define GPIO_SIG51_IN_SEL_M  (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S)
-#define GPIO_SIG51_IN_SEL_V  0x00000001U
-#define GPIO_SIG51_IN_SEL_S  7
-
-/** GPIO_FUNC52_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224)
-/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC52_IN_SEL    0x0000003FU
-#define GPIO_FUNC52_IN_SEL_M  (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S)
-#define GPIO_FUNC52_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC52_IN_SEL_S  0
-/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC52_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC52_IN_INV_SEL_M  (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S)
-#define GPIO_FUNC52_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC52_IN_INV_SEL_S  6
-/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG52_IN_SEL    (BIT(7))
-#define GPIO_SIG52_IN_SEL_M  (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S)
-#define GPIO_SIG52_IN_SEL_V  0x00000001U
-#define GPIO_SIG52_IN_SEL_S  7
-
-/** GPIO_FUNC53_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228)
-/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC53_IN_SEL    0x0000003FU
-#define GPIO_FUNC53_IN_SEL_M  (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S)
-#define GPIO_FUNC53_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC53_IN_SEL_S  0
-/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC53_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC53_IN_INV_SEL_M  (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S)
-#define GPIO_FUNC53_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC53_IN_INV_SEL_S  6
-/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG53_IN_SEL    (BIT(7))
-#define GPIO_SIG53_IN_SEL_M  (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S)
-#define GPIO_SIG53_IN_SEL_V  0x00000001U
-#define GPIO_SIG53_IN_SEL_S  7
-
-/** GPIO_FUNC54_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c)
-/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC54_IN_SEL    0x0000003FU
-#define GPIO_FUNC54_IN_SEL_M  (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S)
-#define GPIO_FUNC54_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC54_IN_SEL_S  0
-/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC54_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC54_IN_INV_SEL_M  (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S)
-#define GPIO_FUNC54_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC54_IN_INV_SEL_S  6
-/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG54_IN_SEL    (BIT(7))
-#define GPIO_SIG54_IN_SEL_M  (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S)
-#define GPIO_SIG54_IN_SEL_V  0x00000001U
-#define GPIO_SIG54_IN_SEL_S  7
-
-/** GPIO_FUNC63_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250)
-/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC63_IN_SEL    0x0000003FU
-#define GPIO_FUNC63_IN_SEL_M  (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S)
-#define GPIO_FUNC63_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC63_IN_SEL_S  0
-/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC63_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC63_IN_INV_SEL_M  (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S)
-#define GPIO_FUNC63_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC63_IN_INV_SEL_S  6
-/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG63_IN_SEL    (BIT(7))
-#define GPIO_SIG63_IN_SEL_M  (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S)
-#define GPIO_SIG63_IN_SEL_V  0x00000001U
-#define GPIO_SIG63_IN_SEL_S  7
-
-/** GPIO_FUNC64_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254)
-/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC64_IN_SEL    0x0000003FU
-#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
-#define GPIO_FUNC64_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC64_IN_SEL_S  0
-/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
-#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC64_IN_INV_SEL_S  6
-/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG64_IN_SEL    (BIT(7))
-#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
-#define GPIO_SIG64_IN_SEL_V  0x00000001U
-#define GPIO_SIG64_IN_SEL_S  7
-
-/** GPIO_FUNC65_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258)
-/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC65_IN_SEL    0x0000003FU
-#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
-#define GPIO_FUNC65_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC65_IN_SEL_S  0
-/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
-#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC65_IN_INV_SEL_S  6
-/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG65_IN_SEL    (BIT(7))
-#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
-#define GPIO_SIG65_IN_SEL_V  0x00000001U
-#define GPIO_SIG65_IN_SEL_S  7
-
-/** GPIO_FUNC66_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c)
-/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC66_IN_SEL    0x0000003FU
-#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
-#define GPIO_FUNC66_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC66_IN_SEL_S  0
-/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
-#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC66_IN_INV_SEL_S  6
-/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG66_IN_SEL    (BIT(7))
-#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
-#define GPIO_SIG66_IN_SEL_V  0x00000001U
-#define GPIO_SIG66_IN_SEL_S  7
-
-/** GPIO_FUNC67_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260)
-/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC67_IN_SEL    0x0000003FU
-#define GPIO_FUNC67_IN_SEL_M  (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S)
-#define GPIO_FUNC67_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC67_IN_SEL_S  0
-/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC67_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC67_IN_INV_SEL_M  (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S)
-#define GPIO_FUNC67_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC67_IN_INV_SEL_S  6
-/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG67_IN_SEL    (BIT(7))
-#define GPIO_SIG67_IN_SEL_M  (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S)
-#define GPIO_SIG67_IN_SEL_V  0x00000001U
-#define GPIO_SIG67_IN_SEL_S  7
-
-/** GPIO_FUNC68_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264)
-/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC68_IN_SEL    0x0000003FU
-#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
-#define GPIO_FUNC68_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC68_IN_SEL_S  0
-/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
-#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC68_IN_INV_SEL_S  6
-/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG68_IN_SEL    (BIT(7))
-#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
-#define GPIO_SIG68_IN_SEL_V  0x00000001U
-#define GPIO_SIG68_IN_SEL_S  7
-
-/** GPIO_FUNC69_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268)
-/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC69_IN_SEL    0x0000003FU
-#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
-#define GPIO_FUNC69_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC69_IN_SEL_S  0
-/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
-#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC69_IN_INV_SEL_S  6
-/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG69_IN_SEL    (BIT(7))
-#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
-#define GPIO_SIG69_IN_SEL_V  0x00000001U
-#define GPIO_SIG69_IN_SEL_S  7
-
-/** GPIO_FUNC70_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c)
-/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC70_IN_SEL    0x0000003FU
-#define GPIO_FUNC70_IN_SEL_M  (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S)
-#define GPIO_FUNC70_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC70_IN_SEL_S  0
-/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC70_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC70_IN_INV_SEL_M  (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S)
-#define GPIO_FUNC70_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC70_IN_INV_SEL_S  6
-/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG70_IN_SEL    (BIT(7))
-#define GPIO_SIG70_IN_SEL_M  (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S)
-#define GPIO_SIG70_IN_SEL_V  0x00000001U
-#define GPIO_SIG70_IN_SEL_S  7
-
-/** GPIO_FUNC71_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270)
-/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC71_IN_SEL    0x0000003FU
-#define GPIO_FUNC71_IN_SEL_M  (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S)
-#define GPIO_FUNC71_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC71_IN_SEL_S  0
-/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC71_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC71_IN_INV_SEL_M  (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S)
-#define GPIO_FUNC71_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC71_IN_INV_SEL_S  6
-/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG71_IN_SEL    (BIT(7))
-#define GPIO_SIG71_IN_SEL_M  (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S)
-#define GPIO_SIG71_IN_SEL_V  0x00000001U
-#define GPIO_SIG71_IN_SEL_S  7
-
-/** GPIO_FUNC72_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274)
-/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC72_IN_SEL    0x0000003FU
-#define GPIO_FUNC72_IN_SEL_M  (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S)
-#define GPIO_FUNC72_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC72_IN_SEL_S  0
-/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC72_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC72_IN_INV_SEL_M  (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S)
-#define GPIO_FUNC72_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC72_IN_INV_SEL_S  6
-/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG72_IN_SEL    (BIT(7))
-#define GPIO_SIG72_IN_SEL_M  (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S)
-#define GPIO_SIG72_IN_SEL_V  0x00000001U
-#define GPIO_SIG72_IN_SEL_S  7
-
-/** GPIO_FUNC73_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278)
-/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 56;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC73_IN_SEL    0x0000003FU
-#define GPIO_FUNC73_IN_SEL_M  (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S)
-#define GPIO_FUNC73_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC73_IN_SEL_S  0
-/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC73_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC73_IN_INV_SEL_M  (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S)
-#define GPIO_FUNC73_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC73_IN_INV_SEL_S  6
-/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG73_IN_SEL    (BIT(7))
-#define GPIO_SIG73_IN_SEL_M  (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S)
-#define GPIO_SIG73_IN_SEL_V  0x00000001U
-#define GPIO_SIG73_IN_SEL_S  7
-
-/** GPIO_FUNC77_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288)
-/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 56;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC77_IN_SEL    0x0000003FU
-#define GPIO_FUNC77_IN_SEL_M  (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S)
-#define GPIO_FUNC77_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC77_IN_SEL_S  0
-/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC77_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC77_IN_INV_SEL_M  (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S)
-#define GPIO_FUNC77_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC77_IN_INV_SEL_S  6
-/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG77_IN_SEL    (BIT(7))
-#define GPIO_SIG77_IN_SEL_M  (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S)
-#define GPIO_SIG77_IN_SEL_V  0x00000001U
-#define GPIO_SIG77_IN_SEL_S  7
-
-/** GPIO_FUNC81_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298)
-/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC81_IN_SEL    0x0000003FU
-#define GPIO_FUNC81_IN_SEL_M  (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S)
-#define GPIO_FUNC81_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC81_IN_SEL_S  0
-/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC81_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC81_IN_INV_SEL_M  (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S)
-#define GPIO_FUNC81_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC81_IN_INV_SEL_S  6
-/** GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG81_IN_SEL    (BIT(7))
-#define GPIO_SIG81_IN_SEL_M  (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S)
-#define GPIO_SIG81_IN_SEL_V  0x00000001U
-#define GPIO_SIG81_IN_SEL_S  7
-
-/** GPIO_FUNC82_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c)
-/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC82_IN_SEL    0x0000003FU
-#define GPIO_FUNC82_IN_SEL_M  (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S)
-#define GPIO_FUNC82_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC82_IN_SEL_S  0
-/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC82_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC82_IN_INV_SEL_M  (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S)
-#define GPIO_FUNC82_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC82_IN_INV_SEL_S  6
-/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG82_IN_SEL    (BIT(7))
-#define GPIO_SIG82_IN_SEL_M  (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S)
-#define GPIO_SIG82_IN_SEL_V  0x00000001U
-#define GPIO_SIG82_IN_SEL_S  7
-
-/** GPIO_FUNC83_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0)
-/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC83_IN_SEL    0x0000003FU
-#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
-#define GPIO_FUNC83_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC83_IN_SEL_S  0
-/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
-#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC83_IN_INV_SEL_S  6
-/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG83_IN_SEL    (BIT(7))
-#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
-#define GPIO_SIG83_IN_SEL_V  0x00000001U
-#define GPIO_SIG83_IN_SEL_S  7
-
-/** GPIO_FUNC84_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4)
-/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC84_IN_SEL    0x0000003FU
-#define GPIO_FUNC84_IN_SEL_M  (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S)
-#define GPIO_FUNC84_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC84_IN_SEL_S  0
-/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC84_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC84_IN_INV_SEL_M  (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S)
-#define GPIO_FUNC84_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC84_IN_INV_SEL_S  6
-/** GPIO_SIG84_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG84_IN_SEL    (BIT(7))
-#define GPIO_SIG84_IN_SEL_M  (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S)
-#define GPIO_SIG84_IN_SEL_V  0x00000001U
-#define GPIO_SIG84_IN_SEL_S  7
-
-/** GPIO_FUNC85_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8)
-/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC85_IN_SEL    0x0000003FU
-#define GPIO_FUNC85_IN_SEL_M  (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S)
-#define GPIO_FUNC85_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC85_IN_SEL_S  0
-/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC85_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC85_IN_INV_SEL_M  (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S)
-#define GPIO_FUNC85_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC85_IN_INV_SEL_S  6
-/** GPIO_SIG85_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG85_IN_SEL    (BIT(7))
-#define GPIO_SIG85_IN_SEL_M  (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S)
-#define GPIO_SIG85_IN_SEL_V  0x00000001U
-#define GPIO_SIG85_IN_SEL_S  7
-
-/** GPIO_FUNC86_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac)
-/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC86_IN_SEL    0x0000003FU
-#define GPIO_FUNC86_IN_SEL_M  (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S)
-#define GPIO_FUNC86_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC86_IN_SEL_S  0
-/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC86_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC86_IN_INV_SEL_M  (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S)
-#define GPIO_FUNC86_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC86_IN_INV_SEL_S  6
-/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG86_IN_SEL    (BIT(7))
-#define GPIO_SIG86_IN_SEL_M  (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S)
-#define GPIO_SIG86_IN_SEL_V  0x00000001U
-#define GPIO_SIG86_IN_SEL_S  7
-
-/** GPIO_FUNC87_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0)
-/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC87_IN_SEL    0x0000003FU
-#define GPIO_FUNC87_IN_SEL_M  (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S)
-#define GPIO_FUNC87_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC87_IN_SEL_S  0
-/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC87_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC87_IN_INV_SEL_M  (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S)
-#define GPIO_FUNC87_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC87_IN_INV_SEL_S  6
-/** GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG87_IN_SEL    (BIT(7))
-#define GPIO_SIG87_IN_SEL_M  (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S)
-#define GPIO_SIG87_IN_SEL_V  0x00000001U
-#define GPIO_SIG87_IN_SEL_S  7
-
-/** GPIO_FUNC88_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4)
-/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC88_IN_SEL    0x0000003FU
-#define GPIO_FUNC88_IN_SEL_M  (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S)
-#define GPIO_FUNC88_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC88_IN_SEL_S  0
-/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC88_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC88_IN_INV_SEL_M  (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S)
-#define GPIO_FUNC88_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC88_IN_INV_SEL_S  6
-/** GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG88_IN_SEL    (BIT(7))
-#define GPIO_SIG88_IN_SEL_M  (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S)
-#define GPIO_SIG88_IN_SEL_V  0x00000001U
-#define GPIO_SIG88_IN_SEL_S  7
-
-/** GPIO_FUNC89_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8)
-/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC89_IN_SEL    0x0000003FU
-#define GPIO_FUNC89_IN_SEL_M  (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S)
-#define GPIO_FUNC89_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC89_IN_SEL_S  0
-/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC89_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC89_IN_INV_SEL_M  (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S)
-#define GPIO_FUNC89_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC89_IN_INV_SEL_S  6
-/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG89_IN_SEL    (BIT(7))
-#define GPIO_SIG89_IN_SEL_M  (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S)
-#define GPIO_SIG89_IN_SEL_V  0x00000001U
-#define GPIO_SIG89_IN_SEL_S  7
-
-/** GPIO_FUNC90_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc)
-/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC90_IN_SEL    0x0000003FU
-#define GPIO_FUNC90_IN_SEL_M  (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S)
-#define GPIO_FUNC90_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC90_IN_SEL_S  0
-/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC90_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC90_IN_INV_SEL_M  (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S)
-#define GPIO_FUNC90_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC90_IN_INV_SEL_S  6
-/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG90_IN_SEL    (BIT(7))
-#define GPIO_SIG90_IN_SEL_M  (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S)
-#define GPIO_SIG90_IN_SEL_V  0x00000001U
-#define GPIO_SIG90_IN_SEL_S  7
-
-/** GPIO_FUNC91_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0)
-/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC91_IN_SEL    0x0000003FU
-#define GPIO_FUNC91_IN_SEL_M  (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S)
-#define GPIO_FUNC91_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC91_IN_SEL_S  0
-/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC91_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC91_IN_INV_SEL_M  (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S)
-#define GPIO_FUNC91_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC91_IN_INV_SEL_S  6
-/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG91_IN_SEL    (BIT(7))
-#define GPIO_SIG91_IN_SEL_M  (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S)
-#define GPIO_SIG91_IN_SEL_V  0x00000001U
-#define GPIO_SIG91_IN_SEL_S  7
-
-/** GPIO_FUNC92_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
-/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC92_IN_SEL    0x0000003FU
-#define GPIO_FUNC92_IN_SEL_M  (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S)
-#define GPIO_FUNC92_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC92_IN_SEL_S  0
-/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC92_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC92_IN_INV_SEL_M  (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S)
-#define GPIO_FUNC92_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC92_IN_INV_SEL_S  6
-/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG92_IN_SEL    (BIT(7))
-#define GPIO_SIG92_IN_SEL_M  (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S)
-#define GPIO_SIG92_IN_SEL_V  0x00000001U
-#define GPIO_SIG92_IN_SEL_S  7
-
-/** GPIO_FUNC93_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8)
-/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC93_IN_SEL    0x0000003FU
-#define GPIO_FUNC93_IN_SEL_M  (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S)
-#define GPIO_FUNC93_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC93_IN_SEL_S  0
-/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC93_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC93_IN_INV_SEL_M  (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S)
-#define GPIO_FUNC93_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC93_IN_INV_SEL_S  6
-/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG93_IN_SEL    (BIT(7))
-#define GPIO_SIG93_IN_SEL_M  (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S)
-#define GPIO_SIG93_IN_SEL_V  0x00000001U
-#define GPIO_SIG93_IN_SEL_S  7
-
-/** GPIO_FUNC94_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc)
-/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC94_IN_SEL    0x0000003FU
-#define GPIO_FUNC94_IN_SEL_M  (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S)
-#define GPIO_FUNC94_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC94_IN_SEL_S  0
-/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC94_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC94_IN_INV_SEL_M  (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S)
-#define GPIO_FUNC94_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC94_IN_INV_SEL_S  6
-/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG94_IN_SEL    (BIT(7))
-#define GPIO_SIG94_IN_SEL_M  (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S)
-#define GPIO_SIG94_IN_SEL_V  0x00000001U
-#define GPIO_SIG94_IN_SEL_S  7
-
-/** GPIO_FUNC95_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0)
-/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC95_IN_SEL    0x0000003FU
-#define GPIO_FUNC95_IN_SEL_M  (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S)
-#define GPIO_FUNC95_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC95_IN_SEL_S  0
-/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC95_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC95_IN_INV_SEL_M  (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S)
-#define GPIO_FUNC95_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC95_IN_INV_SEL_S  6
-/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG95_IN_SEL    (BIT(7))
-#define GPIO_SIG95_IN_SEL_M  (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S)
-#define GPIO_SIG95_IN_SEL_V  0x00000001U
-#define GPIO_SIG95_IN_SEL_S  7
-
-/** GPIO_FUNC97_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8)
-/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC97_IN_SEL    0x0000003FU
-#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
-#define GPIO_FUNC97_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC97_IN_SEL_S  0
-/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
-#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC97_IN_INV_SEL_S  6
-/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG97_IN_SEL    (BIT(7))
-#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
-#define GPIO_SIG97_IN_SEL_V  0x00000001U
-#define GPIO_SIG97_IN_SEL_S  7
-
-/** GPIO_FUNC98_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
-/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC98_IN_SEL    0x0000003FU
-#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
-#define GPIO_FUNC98_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC98_IN_SEL_S  0
-/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
-#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC98_IN_INV_SEL_S  6
-/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG98_IN_SEL    (BIT(7))
-#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
-#define GPIO_SIG98_IN_SEL_V  0x00000001U
-#define GPIO_SIG98_IN_SEL_S  7
-
-/** GPIO_FUNC99_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
-/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC99_IN_SEL    0x0000003FU
-#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
-#define GPIO_FUNC99_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC99_IN_SEL_S  0
-/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
-#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC99_IN_INV_SEL_S  6
-/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG99_IN_SEL    (BIT(7))
-#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
-#define GPIO_SIG99_IN_SEL_V  0x00000001U
-#define GPIO_SIG99_IN_SEL_S  7
-
-/** GPIO_FUNC100_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
-/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC100_IN_SEL    0x0000003FU
-#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
-#define GPIO_FUNC100_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC100_IN_SEL_S  0
-/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
-#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC100_IN_INV_SEL_S  6
-/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG100_IN_SEL    (BIT(7))
-#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
-#define GPIO_SIG100_IN_SEL_V  0x00000001U
-#define GPIO_SIG100_IN_SEL_S  7
-
-/** GPIO_FUNC101_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
-/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC101_IN_SEL    0x0000003FU
-#define GPIO_FUNC101_IN_SEL_M  (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S)
-#define GPIO_FUNC101_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC101_IN_SEL_S  0
-/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC101_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC101_IN_INV_SEL_M  (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S)
-#define GPIO_FUNC101_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC101_IN_INV_SEL_S  6
-/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG101_IN_SEL    (BIT(7))
-#define GPIO_SIG101_IN_SEL_M  (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S)
-#define GPIO_SIG101_IN_SEL_V  0x00000001U
-#define GPIO_SIG101_IN_SEL_S  7
-
-/** GPIO_FUNC102_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
-/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC102_IN_SEL    0x0000003FU
-#define GPIO_FUNC102_IN_SEL_M  (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S)
-#define GPIO_FUNC102_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC102_IN_SEL_S  0
-/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC102_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC102_IN_INV_SEL_M  (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S)
-#define GPIO_FUNC102_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC102_IN_INV_SEL_S  6
-/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG102_IN_SEL    (BIT(7))
-#define GPIO_SIG102_IN_SEL_M  (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S)
-#define GPIO_SIG102_IN_SEL_V  0x00000001U
-#define GPIO_SIG102_IN_SEL_S  7
-
-/** GPIO_FUNC103_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
-/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC103_IN_SEL    0x0000003FU
-#define GPIO_FUNC103_IN_SEL_M  (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S)
-#define GPIO_FUNC103_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC103_IN_SEL_S  0
-/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC103_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC103_IN_INV_SEL_M  (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S)
-#define GPIO_FUNC103_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC103_IN_INV_SEL_S  6
-/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG103_IN_SEL    (BIT(7))
-#define GPIO_SIG103_IN_SEL_M  (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S)
-#define GPIO_SIG103_IN_SEL_V  0x00000001U
-#define GPIO_SIG103_IN_SEL_S  7
-
-/** GPIO_FUNC104_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
-/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC104_IN_SEL    0x0000003FU
-#define GPIO_FUNC104_IN_SEL_M  (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S)
-#define GPIO_FUNC104_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC104_IN_SEL_S  0
-/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC104_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC104_IN_INV_SEL_M  (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S)
-#define GPIO_FUNC104_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC104_IN_INV_SEL_S  6
-/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG104_IN_SEL    (BIT(7))
-#define GPIO_SIG104_IN_SEL_M  (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S)
-#define GPIO_SIG104_IN_SEL_V  0x00000001U
-#define GPIO_SIG104_IN_SEL_S  7
-
-/** GPIO_FUNC105_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
-/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC105_IN_SEL    0x0000003FU
-#define GPIO_FUNC105_IN_SEL_M  (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S)
-#define GPIO_FUNC105_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC105_IN_SEL_S  0
-/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC105_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC105_IN_INV_SEL_M  (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S)
-#define GPIO_FUNC105_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC105_IN_INV_SEL_S  6
-/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG105_IN_SEL    (BIT(7))
-#define GPIO_SIG105_IN_SEL_M  (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S)
-#define GPIO_SIG105_IN_SEL_V  0x00000001U
-#define GPIO_SIG105_IN_SEL_S  7
-
-/** GPIO_FUNC106_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
-/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC106_IN_SEL    0x0000003FU
-#define GPIO_FUNC106_IN_SEL_M  (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S)
-#define GPIO_FUNC106_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC106_IN_SEL_S  0
-/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC106_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC106_IN_INV_SEL_M  (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S)
-#define GPIO_FUNC106_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC106_IN_INV_SEL_S  6
-/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG106_IN_SEL    (BIT(7))
-#define GPIO_SIG106_IN_SEL_M  (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S)
-#define GPIO_SIG106_IN_SEL_V  0x00000001U
-#define GPIO_SIG106_IN_SEL_S  7
-
-/** GPIO_FUNC107_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
-/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC107_IN_SEL    0x0000003FU
-#define GPIO_FUNC107_IN_SEL_M  (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S)
-#define GPIO_FUNC107_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC107_IN_SEL_S  0
-/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC107_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC107_IN_INV_SEL_M  (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S)
-#define GPIO_FUNC107_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC107_IN_INV_SEL_S  6
-/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG107_IN_SEL    (BIT(7))
-#define GPIO_SIG107_IN_SEL_M  (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S)
-#define GPIO_SIG107_IN_SEL_V  0x00000001U
-#define GPIO_SIG107_IN_SEL_S  7
-
-/** GPIO_FUNC108_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
-/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC108_IN_SEL    0x0000003FU
-#define GPIO_FUNC108_IN_SEL_M  (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S)
-#define GPIO_FUNC108_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC108_IN_SEL_S  0
-/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC108_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC108_IN_INV_SEL_M  (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S)
-#define GPIO_FUNC108_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC108_IN_INV_SEL_S  6
-/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG108_IN_SEL    (BIT(7))
-#define GPIO_SIG108_IN_SEL_M  (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S)
-#define GPIO_SIG108_IN_SEL_V  0x00000001U
-#define GPIO_SIG108_IN_SEL_S  7
-
-/** GPIO_FUNC109_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
-/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC109_IN_SEL    0x0000003FU
-#define GPIO_FUNC109_IN_SEL_M  (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S)
-#define GPIO_FUNC109_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC109_IN_SEL_S  0
-/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC109_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC109_IN_INV_SEL_M  (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S)
-#define GPIO_FUNC109_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC109_IN_INV_SEL_S  6
-/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG109_IN_SEL    (BIT(7))
-#define GPIO_SIG109_IN_SEL_M  (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S)
-#define GPIO_SIG109_IN_SEL_V  0x00000001U
-#define GPIO_SIG109_IN_SEL_S  7
-
-/** GPIO_FUNC110_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
-/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC110_IN_SEL    0x0000003FU
-#define GPIO_FUNC110_IN_SEL_M  (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S)
-#define GPIO_FUNC110_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC110_IN_SEL_S  0
-/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC110_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC110_IN_INV_SEL_M  (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S)
-#define GPIO_FUNC110_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC110_IN_INV_SEL_S  6
-/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG110_IN_SEL    (BIT(7))
-#define GPIO_SIG110_IN_SEL_M  (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S)
-#define GPIO_SIG110_IN_SEL_V  0x00000001U
-#define GPIO_SIG110_IN_SEL_S  7
-
-/** GPIO_FUNC111_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
-/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC111_IN_SEL    0x0000003FU
-#define GPIO_FUNC111_IN_SEL_M  (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S)
-#define GPIO_FUNC111_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC111_IN_SEL_S  0
-/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC111_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC111_IN_INV_SEL_M  (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S)
-#define GPIO_FUNC111_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC111_IN_INV_SEL_S  6
-/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG111_IN_SEL    (BIT(7))
-#define GPIO_SIG111_IN_SEL_M  (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S)
-#define GPIO_SIG111_IN_SEL_V  0x00000001U
-#define GPIO_SIG111_IN_SEL_S  7
-
-/** GPIO_FUNC112_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314)
-/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC112_IN_SEL    0x0000003FU
-#define GPIO_FUNC112_IN_SEL_M  (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S)
-#define GPIO_FUNC112_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC112_IN_SEL_S  0
-/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC112_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC112_IN_INV_SEL_M  (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S)
-#define GPIO_FUNC112_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC112_IN_INV_SEL_S  6
-/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG112_IN_SEL    (BIT(7))
-#define GPIO_SIG112_IN_SEL_M  (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S)
-#define GPIO_SIG112_IN_SEL_V  0x00000001U
-#define GPIO_SIG112_IN_SEL_S  7
-
-/** GPIO_FUNC113_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318)
-/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC113_IN_SEL    0x0000003FU
-#define GPIO_FUNC113_IN_SEL_M  (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S)
-#define GPIO_FUNC113_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC113_IN_SEL_S  0
-/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC113_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC113_IN_INV_SEL_M  (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S)
-#define GPIO_FUNC113_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC113_IN_INV_SEL_S  6
-/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG113_IN_SEL    (BIT(7))
-#define GPIO_SIG113_IN_SEL_M  (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S)
-#define GPIO_SIG113_IN_SEL_V  0x00000001U
-#define GPIO_SIG113_IN_SEL_S  7
-
-/** GPIO_FUNC114_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
-/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC114_IN_SEL    0x0000003FU
-#define GPIO_FUNC114_IN_SEL_M  (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S)
-#define GPIO_FUNC114_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC114_IN_SEL_S  0
-/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC114_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC114_IN_INV_SEL_M  (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S)
-#define GPIO_FUNC114_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC114_IN_INV_SEL_S  6
-/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG114_IN_SEL    (BIT(7))
-#define GPIO_SIG114_IN_SEL_M  (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S)
-#define GPIO_SIG114_IN_SEL_V  0x00000001U
-#define GPIO_SIG114_IN_SEL_S  7
-
-/** GPIO_FUNC115_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
-/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC115_IN_SEL    0x0000003FU
-#define GPIO_FUNC115_IN_SEL_M  (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S)
-#define GPIO_FUNC115_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC115_IN_SEL_S  0
-/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC115_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC115_IN_INV_SEL_M  (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S)
-#define GPIO_FUNC115_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC115_IN_INV_SEL_S  6
-/** GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG115_IN_SEL    (BIT(7))
-#define GPIO_SIG115_IN_SEL_M  (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S)
-#define GPIO_SIG115_IN_SEL_V  0x00000001U
-#define GPIO_SIG115_IN_SEL_S  7
-
-/** GPIO_FUNC116_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324)
-/** GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC116_IN_SEL    0x0000003FU
-#define GPIO_FUNC116_IN_SEL_M  (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S)
-#define GPIO_FUNC116_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC116_IN_SEL_S  0
-/** GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC116_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC116_IN_INV_SEL_M  (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S)
-#define GPIO_FUNC116_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC116_IN_INV_SEL_S  6
-/** GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG116_IN_SEL    (BIT(7))
-#define GPIO_SIG116_IN_SEL_M  (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S)
-#define GPIO_SIG116_IN_SEL_V  0x00000001U
-#define GPIO_SIG116_IN_SEL_S  7
-
-/** GPIO_FUNC117_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328)
-/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC117_IN_SEL    0x0000003FU
-#define GPIO_FUNC117_IN_SEL_M  (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S)
-#define GPIO_FUNC117_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC117_IN_SEL_S  0
-/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC117_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC117_IN_INV_SEL_M  (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S)
-#define GPIO_FUNC117_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC117_IN_INV_SEL_S  6
-/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG117_IN_SEL    (BIT(7))
-#define GPIO_SIG117_IN_SEL_M  (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S)
-#define GPIO_SIG117_IN_SEL_V  0x00000001U
-#define GPIO_SIG117_IN_SEL_S  7
-
-/** GPIO_FUNC118_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
-/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC118_IN_SEL    0x0000003FU
-#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
-#define GPIO_FUNC118_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC118_IN_SEL_S  0
-/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
-#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC118_IN_INV_SEL_S  6
-/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG118_IN_SEL    (BIT(7))
-#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
-#define GPIO_SIG118_IN_SEL_V  0x00000001U
-#define GPIO_SIG118_IN_SEL_S  7
-
-/** GPIO_FUNC119_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
-/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC119_IN_SEL    0x0000003FU
-#define GPIO_FUNC119_IN_SEL_M  (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S)
-#define GPIO_FUNC119_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC119_IN_SEL_S  0
-/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC119_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC119_IN_INV_SEL_M  (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S)
-#define GPIO_FUNC119_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC119_IN_INV_SEL_S  6
-/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG119_IN_SEL    (BIT(7))
-#define GPIO_SIG119_IN_SEL_M  (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S)
-#define GPIO_SIG119_IN_SEL_V  0x00000001U
-#define GPIO_SIG119_IN_SEL_S  7
-
-/** GPIO_FUNC120_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334)
-/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC120_IN_SEL    0x0000003FU
-#define GPIO_FUNC120_IN_SEL_M  (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S)
-#define GPIO_FUNC120_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC120_IN_SEL_S  0
-/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC120_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC120_IN_INV_SEL_M  (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S)
-#define GPIO_FUNC120_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC120_IN_INV_SEL_S  6
-/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG120_IN_SEL    (BIT(7))
-#define GPIO_SIG120_IN_SEL_M  (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S)
-#define GPIO_SIG120_IN_SEL_V  0x00000001U
-#define GPIO_SIG120_IN_SEL_S  7
-
-/** GPIO_FUNC121_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338)
-/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC121_IN_SEL    0x0000003FU
-#define GPIO_FUNC121_IN_SEL_M  (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S)
-#define GPIO_FUNC121_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC121_IN_SEL_S  0
-/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC121_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC121_IN_INV_SEL_M  (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S)
-#define GPIO_FUNC121_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC121_IN_INV_SEL_S  6
-/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG121_IN_SEL    (BIT(7))
-#define GPIO_SIG121_IN_SEL_M  (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S)
-#define GPIO_SIG121_IN_SEL_V  0x00000001U
-#define GPIO_SIG121_IN_SEL_S  7
-
-/** GPIO_FUNC122_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c)
-/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC122_IN_SEL    0x0000003FU
-#define GPIO_FUNC122_IN_SEL_M  (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S)
-#define GPIO_FUNC122_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC122_IN_SEL_S  0
-/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC122_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC122_IN_INV_SEL_M  (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S)
-#define GPIO_FUNC122_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC122_IN_INV_SEL_S  6
-/** GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG122_IN_SEL    (BIT(7))
-#define GPIO_SIG122_IN_SEL_M  (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S)
-#define GPIO_SIG122_IN_SEL_V  0x00000001U
-#define GPIO_SIG122_IN_SEL_S  7
-
-/** GPIO_FUNC123_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340)
-/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC123_IN_SEL    0x0000003FU
-#define GPIO_FUNC123_IN_SEL_M  (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S)
-#define GPIO_FUNC123_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC123_IN_SEL_S  0
-/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC123_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC123_IN_INV_SEL_M  (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S)
-#define GPIO_FUNC123_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC123_IN_INV_SEL_S  6
-/** GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG123_IN_SEL    (BIT(7))
-#define GPIO_SIG123_IN_SEL_M  (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S)
-#define GPIO_SIG123_IN_SEL_V  0x00000001U
-#define GPIO_SIG123_IN_SEL_S  7
-
-/** GPIO_FUNC124_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344)
-/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 60;
- *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
- *  high level. s=0x3C: set this port always low level.
- */
-#define GPIO_FUNC124_IN_SEL    0x0000003FU
-#define GPIO_FUNC124_IN_SEL_M  (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S)
-#define GPIO_FUNC124_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC124_IN_SEL_S  0
-/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC124_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC124_IN_INV_SEL_M  (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S)
-#define GPIO_FUNC124_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC124_IN_INV_SEL_S  6
-/** GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG124_IN_SEL    (BIT(7))
-#define GPIO_SIG124_IN_SEL_M  (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S)
-#define GPIO_SIG124_IN_SEL_V  0x00000001U
-#define GPIO_SIG124_IN_SEL_S  7
-
-/** GPIO_FUNC0_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
-/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC0_OUT_SEL    0x000000FFU
-#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
-#define GPIO_FUNC0_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC0_OUT_SEL_S  0
-/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC0_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
-#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_OUT_INV_SEL_S  8
-/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC0_OEN_SEL    (BIT(9))
-#define GPIO_FUNC0_OEN_SEL_M  (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S)
-#define GPIO_FUNC0_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC0_OEN_SEL_S  9
-/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC0_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC0_OEN_INV_SEL_M  (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S)
-#define GPIO_FUNC0_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC1_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
-/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC1_OUT_SEL    0x000000FFU
-#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
-#define GPIO_FUNC1_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC1_OUT_SEL_S  0
-/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC1_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
-#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC1_OUT_INV_SEL_S  8
-/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC1_OEN_SEL    (BIT(9))
-#define GPIO_FUNC1_OEN_SEL_M  (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S)
-#define GPIO_FUNC1_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC1_OEN_SEL_S  9
-/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC1_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC1_OEN_INV_SEL_M  (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S)
-#define GPIO_FUNC1_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC1_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC2_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
-/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC2_OUT_SEL    0x000000FFU
-#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
-#define GPIO_FUNC2_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC2_OUT_SEL_S  0
-/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC2_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
-#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC2_OUT_INV_SEL_S  8
-/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC2_OEN_SEL    (BIT(9))
-#define GPIO_FUNC2_OEN_SEL_M  (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S)
-#define GPIO_FUNC2_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC2_OEN_SEL_S  9
-/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC2_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC2_OEN_INV_SEL_M  (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S)
-#define GPIO_FUNC2_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC2_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC3_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
-/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC3_OUT_SEL    0x000000FFU
-#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
-#define GPIO_FUNC3_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC3_OUT_SEL_S  0
-/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC3_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
-#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC3_OUT_INV_SEL_S  8
-/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC3_OEN_SEL    (BIT(9))
-#define GPIO_FUNC3_OEN_SEL_M  (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S)
-#define GPIO_FUNC3_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC3_OEN_SEL_S  9
-/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC3_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC3_OEN_INV_SEL_M  (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S)
-#define GPIO_FUNC3_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC3_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC4_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
-/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC4_OUT_SEL    0x000000FFU
-#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
-#define GPIO_FUNC4_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC4_OUT_SEL_S  0
-/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC4_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
-#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC4_OUT_INV_SEL_S  8
-/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC4_OEN_SEL    (BIT(9))
-#define GPIO_FUNC4_OEN_SEL_M  (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S)
-#define GPIO_FUNC4_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC4_OEN_SEL_S  9
-/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC4_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC4_OEN_INV_SEL_M  (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S)
-#define GPIO_FUNC4_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC4_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC5_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568)
-/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC5_OUT_SEL    0x000000FFU
-#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
-#define GPIO_FUNC5_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC5_OUT_SEL_S  0
-/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC5_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
-#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC5_OUT_INV_SEL_S  8
-/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC5_OEN_SEL    (BIT(9))
-#define GPIO_FUNC5_OEN_SEL_M  (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S)
-#define GPIO_FUNC5_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC5_OEN_SEL_S  9
-/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC5_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC5_OEN_INV_SEL_M  (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S)
-#define GPIO_FUNC5_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC5_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC6_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
-/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC6_OUT_SEL    0x000000FFU
-#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
-#define GPIO_FUNC6_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC6_OUT_SEL_S  0
-/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC6_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
-#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_OUT_INV_SEL_S  8
-/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC6_OEN_SEL    (BIT(9))
-#define GPIO_FUNC6_OEN_SEL_M  (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S)
-#define GPIO_FUNC6_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC6_OEN_SEL_S  9
-/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC6_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC6_OEN_INV_SEL_M  (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S)
-#define GPIO_FUNC6_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC7_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
-/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC7_OUT_SEL    0x000000FFU
-#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
-#define GPIO_FUNC7_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC7_OUT_SEL_S  0
-/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC7_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
-#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_OUT_INV_SEL_S  8
-/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC7_OEN_SEL    (BIT(9))
-#define GPIO_FUNC7_OEN_SEL_M  (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S)
-#define GPIO_FUNC7_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC7_OEN_SEL_S  9
-/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC7_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC7_OEN_INV_SEL_M  (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S)
-#define GPIO_FUNC7_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC8_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
-/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC8_OUT_SEL    0x000000FFU
-#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
-#define GPIO_FUNC8_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC8_OUT_SEL_S  0
-/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC8_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
-#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_OUT_INV_SEL_S  8
-/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC8_OEN_SEL    (BIT(9))
-#define GPIO_FUNC8_OEN_SEL_M  (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S)
-#define GPIO_FUNC8_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC8_OEN_SEL_S  9
-/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC8_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC8_OEN_INV_SEL_M  (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S)
-#define GPIO_FUNC8_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC9_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
-/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC9_OUT_SEL    0x000000FFU
-#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
-#define GPIO_FUNC9_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC9_OUT_SEL_S  0
-/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC9_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
-#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_OUT_INV_SEL_S  8
-/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC9_OEN_SEL    (BIT(9))
-#define GPIO_FUNC9_OEN_SEL_M  (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S)
-#define GPIO_FUNC9_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC9_OEN_SEL_S  9
-/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC9_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC9_OEN_INV_SEL_M  (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S)
-#define GPIO_FUNC9_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC10_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
-/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC10_OUT_SEL    0x000000FFU
-#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
-#define GPIO_FUNC10_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC10_OUT_SEL_S  0
-/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC10_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
-#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_OUT_INV_SEL_S  8
-/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC10_OEN_SEL    (BIT(9))
-#define GPIO_FUNC10_OEN_SEL_M  (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S)
-#define GPIO_FUNC10_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC10_OEN_SEL_S  9
-/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC10_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC10_OEN_INV_SEL_M  (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S)
-#define GPIO_FUNC10_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC11_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
-/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC11_OUT_SEL    0x000000FFU
-#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
-#define GPIO_FUNC11_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC11_OUT_SEL_S  0
-/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC11_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
-#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_OUT_INV_SEL_S  8
-/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC11_OEN_SEL    (BIT(9))
-#define GPIO_FUNC11_OEN_SEL_M  (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S)
-#define GPIO_FUNC11_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC11_OEN_SEL_S  9
-/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC11_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC11_OEN_INV_SEL_M  (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S)
-#define GPIO_FUNC11_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC12_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
-/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC12_OUT_SEL    0x000000FFU
-#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
-#define GPIO_FUNC12_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC12_OUT_SEL_S  0
-/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC12_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
-#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_OUT_INV_SEL_S  8
-/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC12_OEN_SEL    (BIT(9))
-#define GPIO_FUNC12_OEN_SEL_M  (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S)
-#define GPIO_FUNC12_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC12_OEN_SEL_S  9
-/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC12_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC12_OEN_INV_SEL_M  (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S)
-#define GPIO_FUNC12_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC13_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
-/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC13_OUT_SEL    0x000000FFU
-#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
-#define GPIO_FUNC13_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC13_OUT_SEL_S  0
-/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC13_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
-#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_OUT_INV_SEL_S  8
-/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC13_OEN_SEL    (BIT(9))
-#define GPIO_FUNC13_OEN_SEL_M  (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S)
-#define GPIO_FUNC13_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC13_OEN_SEL_S  9
-/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC13_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC13_OEN_INV_SEL_M  (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S)
-#define GPIO_FUNC13_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC14_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
-/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC14_OUT_SEL    0x000000FFU
-#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
-#define GPIO_FUNC14_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC14_OUT_SEL_S  0
-/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC14_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
-#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_OUT_INV_SEL_S  8
-/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC14_OEN_SEL    (BIT(9))
-#define GPIO_FUNC14_OEN_SEL_M  (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S)
-#define GPIO_FUNC14_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC14_OEN_SEL_S  9
-/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC14_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC14_OEN_INV_SEL_M  (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S)
-#define GPIO_FUNC14_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC15_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
-/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC15_OUT_SEL    0x000000FFU
-#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
-#define GPIO_FUNC15_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC15_OUT_SEL_S  0
-/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC15_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
-#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_OUT_INV_SEL_S  8
-/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC15_OEN_SEL    (BIT(9))
-#define GPIO_FUNC15_OEN_SEL_M  (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S)
-#define GPIO_FUNC15_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC15_OEN_SEL_S  9
-/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC15_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC15_OEN_INV_SEL_M  (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S)
-#define GPIO_FUNC15_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC16_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
-/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC16_OUT_SEL    0x000000FFU
-#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
-#define GPIO_FUNC16_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC16_OUT_SEL_S  0
-/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC16_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
-#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_OUT_INV_SEL_S  8
-/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC16_OEN_SEL    (BIT(9))
-#define GPIO_FUNC16_OEN_SEL_M  (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S)
-#define GPIO_FUNC16_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC16_OEN_SEL_S  9
-/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC16_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC16_OEN_INV_SEL_M  (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S)
-#define GPIO_FUNC16_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC17_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
-/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC17_OUT_SEL    0x000000FFU
-#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
-#define GPIO_FUNC17_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC17_OUT_SEL_S  0
-/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC17_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
-#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_OUT_INV_SEL_S  8
-/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC17_OEN_SEL    (BIT(9))
-#define GPIO_FUNC17_OEN_SEL_M  (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S)
-#define GPIO_FUNC17_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC17_OEN_SEL_S  9
-/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC17_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC17_OEN_INV_SEL_M  (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S)
-#define GPIO_FUNC17_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC18_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
-/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC18_OUT_SEL    0x000000FFU
-#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
-#define GPIO_FUNC18_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC18_OUT_SEL_S  0
-/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC18_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
-#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC18_OUT_INV_SEL_S  8
-/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC18_OEN_SEL    (BIT(9))
-#define GPIO_FUNC18_OEN_SEL_M  (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S)
-#define GPIO_FUNC18_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC18_OEN_SEL_S  9
-/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC18_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC18_OEN_INV_SEL_M  (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S)
-#define GPIO_FUNC18_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC18_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC19_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
-/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC19_OUT_SEL    0x000000FFU
-#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
-#define GPIO_FUNC19_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC19_OUT_SEL_S  0
-/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC19_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
-#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_OUT_INV_SEL_S  8
-/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC19_OEN_SEL    (BIT(9))
-#define GPIO_FUNC19_OEN_SEL_M  (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S)
-#define GPIO_FUNC19_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC19_OEN_SEL_S  9
-/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC19_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC19_OEN_INV_SEL_M  (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S)
-#define GPIO_FUNC19_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC20_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
-/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC20_OUT_SEL    0x000000FFU
-#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
-#define GPIO_FUNC20_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC20_OUT_SEL_S  0
-/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC20_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
-#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC20_OUT_INV_SEL_S  8
-/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC20_OEN_SEL    (BIT(9))
-#define GPIO_FUNC20_OEN_SEL_M  (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S)
-#define GPIO_FUNC20_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC20_OEN_SEL_S  9
-/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC20_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC20_OEN_INV_SEL_M  (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S)
-#define GPIO_FUNC20_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC20_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC21_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
-/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC21_OUT_SEL    0x000000FFU
-#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
-#define GPIO_FUNC21_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC21_OUT_SEL_S  0
-/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC21_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
-#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_OUT_INV_SEL_S  8
-/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC21_OEN_SEL    (BIT(9))
-#define GPIO_FUNC21_OEN_SEL_M  (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S)
-#define GPIO_FUNC21_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC21_OEN_SEL_S  9
-/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC21_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC21_OEN_INV_SEL_M  (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S)
-#define GPIO_FUNC21_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC22_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
-/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC22_OUT_SEL    0x000000FFU
-#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
-#define GPIO_FUNC22_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC22_OUT_SEL_S  0
-/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC22_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
-#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC22_OUT_INV_SEL_S  8
-/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC22_OEN_SEL    (BIT(9))
-#define GPIO_FUNC22_OEN_SEL_M  (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S)
-#define GPIO_FUNC22_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC22_OEN_SEL_S  9
-/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC22_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC22_OEN_INV_SEL_M  (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S)
-#define GPIO_FUNC22_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC22_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC23_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
-/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC23_OUT_SEL    0x000000FFU
-#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
-#define GPIO_FUNC23_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC23_OUT_SEL_S  0
-/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC23_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
-#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC23_OUT_INV_SEL_S  8
-/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC23_OEN_SEL    (BIT(9))
-#define GPIO_FUNC23_OEN_SEL_M  (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S)
-#define GPIO_FUNC23_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC23_OEN_SEL_S  9
-/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC23_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC23_OEN_INV_SEL_M  (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S)
-#define GPIO_FUNC23_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC23_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC24_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
-/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC24_OUT_SEL    0x000000FFU
-#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
-#define GPIO_FUNC24_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC24_OUT_SEL_S  0
-/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC24_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
-#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC24_OUT_INV_SEL_S  8
-/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC24_OEN_SEL    (BIT(9))
-#define GPIO_FUNC24_OEN_SEL_M  (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S)
-#define GPIO_FUNC24_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC24_OEN_SEL_S  9
-/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC24_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC24_OEN_INV_SEL_M  (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S)
-#define GPIO_FUNC24_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC24_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC25_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8)
-/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC25_OUT_SEL    0x000000FFU
-#define GPIO_FUNC25_OUT_SEL_M  (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
-#define GPIO_FUNC25_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC25_OUT_SEL_S  0
-/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC25_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC25_OUT_INV_SEL_M  (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
-#define GPIO_FUNC25_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC25_OUT_INV_SEL_S  8
-/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC25_OEN_SEL    (BIT(9))
-#define GPIO_FUNC25_OEN_SEL_M  (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S)
-#define GPIO_FUNC25_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC25_OEN_SEL_S  9
-/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC25_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC25_OEN_INV_SEL_M  (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S)
-#define GPIO_FUNC25_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC25_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC26_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc)
-/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC26_OUT_SEL    0x000000FFU
-#define GPIO_FUNC26_OUT_SEL_M  (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
-#define GPIO_FUNC26_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC26_OUT_SEL_S  0
-/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC26_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC26_OUT_INV_SEL_M  (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
-#define GPIO_FUNC26_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC26_OUT_INV_SEL_S  8
-/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC26_OEN_SEL    (BIT(9))
-#define GPIO_FUNC26_OEN_SEL_M  (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S)
-#define GPIO_FUNC26_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC26_OEN_SEL_S  9
-/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC26_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC26_OEN_INV_SEL_M  (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S)
-#define GPIO_FUNC26_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC26_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC27_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0)
-/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC27_OUT_SEL    0x000000FFU
-#define GPIO_FUNC27_OUT_SEL_M  (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
-#define GPIO_FUNC27_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC27_OUT_SEL_S  0
-/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC27_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC27_OUT_INV_SEL_M  (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
-#define GPIO_FUNC27_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC27_OUT_INV_SEL_S  8
-/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC27_OEN_SEL    (BIT(9))
-#define GPIO_FUNC27_OEN_SEL_M  (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S)
-#define GPIO_FUNC27_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC27_OEN_SEL_S  9
-/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC27_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC27_OEN_INV_SEL_M  (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S)
-#define GPIO_FUNC27_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC27_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC28_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4)
-/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC28_OUT_SEL    0x000000FFU
-#define GPIO_FUNC28_OUT_SEL_M  (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
-#define GPIO_FUNC28_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC28_OUT_SEL_S  0
-/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC28_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC28_OUT_INV_SEL_M  (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
-#define GPIO_FUNC28_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC28_OUT_INV_SEL_S  8
-/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC28_OEN_SEL    (BIT(9))
-#define GPIO_FUNC28_OEN_SEL_M  (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S)
-#define GPIO_FUNC28_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC28_OEN_SEL_S  9
-/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC28_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC28_OEN_INV_SEL_M  (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S)
-#define GPIO_FUNC28_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC28_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC29_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8)
-/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC29_OUT_SEL    0x000000FFU
-#define GPIO_FUNC29_OUT_SEL_M  (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S)
-#define GPIO_FUNC29_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC29_OUT_SEL_S  0
-/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC29_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC29_OUT_INV_SEL_M  (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S)
-#define GPIO_FUNC29_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC29_OUT_INV_SEL_S  8
-/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC29_OEN_SEL    (BIT(9))
-#define GPIO_FUNC29_OEN_SEL_M  (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S)
-#define GPIO_FUNC29_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC29_OEN_SEL_S  9
-/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC29_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC29_OEN_INV_SEL_M  (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S)
-#define GPIO_FUNC29_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC29_OEN_INV_SEL_S  10
-
-/** GPIO_FUNC30_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc)
-/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [7:0]; default: 128;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
- *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC30_OUT_SEL    0x000000FFU
-#define GPIO_FUNC30_OUT_SEL_M  (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S)
-#define GPIO_FUNC30_OUT_SEL_V  0x000000FFU
-#define GPIO_FUNC30_OUT_SEL_S  0
-/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [8]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC30_OUT_INV_SEL    (BIT(8))
-#define GPIO_FUNC30_OUT_INV_SEL_M  (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S)
-#define GPIO_FUNC30_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC30_OUT_INV_SEL_S  8
-/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [9]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC30_OEN_SEL    (BIT(9))
-#define GPIO_FUNC30_OEN_SEL_M  (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S)
-#define GPIO_FUNC30_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC30_OEN_SEL_S  9
-/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC30_OEN_INV_SEL    (BIT(10))
-#define GPIO_FUNC30_OEN_INV_SEL_M  (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S)
-#define GPIO_FUNC30_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC30_OEN_INV_SEL_S  10
-
-/** GPIO_CLOCK_GATE_REG register
- *  GPIO clock gate register
- */
-#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c)
-/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  set this bit to enable GPIO clock gate
- */
-#define GPIO_CLK_EN    (BIT(0))
-#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
-#define GPIO_CLK_EN_V  0x00000001U
-#define GPIO_CLK_EN_S  0
-
-/** GPIO_DATE_REG register
- *  GPIO version register
- */
-#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc)
-/** GPIO_DATE : R/W; bitpos: [27:0]; default: 36704512;
- *  version register
- */
-#define GPIO_DATE    0x0FFFFFFFU
-#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
-#define GPIO_DATE_V  0x0FFFFFFFU
-#define GPIO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/gpio_sig_map.h b/components/soc/esp32c5/beta3/include/soc/gpio_sig_map.h
deleted file mode 100644
index 4051c57f68..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gpio_sig_map.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#define EXT_ADC_START_IDX                       0
-#define LEDC_LS_SIG_OUT0_IDX                    0
-#define LEDC_LS_SIG_OUT1_IDX                    1
-#define LEDC_LS_SIG_OUT2_IDX                    2
-#define LEDC_LS_SIG_OUT3_IDX                    3
-#define LEDC_LS_SIG_OUT4_IDX                    4
-#define LEDC_LS_SIG_OUT5_IDX                    5
-#define U0RXD_IN_IDX                            6
-#define U0TXD_OUT_IDX                           6
-#define U0CTS_IN_IDX                            7
-#define U0RTS_OUT_IDX                           7
-#define U0DSR_IN_IDX                            8
-#define U0DTR_OUT_IDX                           8
-#define U1RXD_IN_IDX                            9
-#define U1TXD_OUT_IDX                           9
-#define U1CTS_IN_IDX                            10
-#define U1RTS_OUT_IDX                           10
-#define U1DSR_IN_IDX                            11
-#define U1DTR_OUT_IDX                           11
-#define I2S_MCLK_IN_IDX                         12
-#define I2S_MCLK_OUT_IDX                        12
-#define I2SO_BCK_IN_IDX                         13
-#define I2SO_BCK_OUT_IDX                        13
-#define I2SO_WS_IN_IDX                          14
-#define I2SO_WS_OUT_IDX                         14
-#define I2SI_SD_IN_IDX                          15
-#define I2SO_SD_OUT_IDX                         15
-#define I2SI_BCK_IN_IDX                         16
-#define I2SI_BCK_OUT_IDX                        16
-#define I2SI_WS_IN_IDX                          17
-#define I2SI_WS_OUT_IDX                         17
-#define I2SO_SD1_OUT_IDX                        18
-#define USB_JTAG_TDO_BRIDGE_IDX                 19
-#define USB_JTAG_TRST_IDX                       19
-#define CPU_TESTBUS0_IDX                        20
-#define USB_OTG_32K_IN_IDX                      21
-#define CPU_TESTBUS1_IDX                        21
-#define USB_OTG_25M_IN_IDX                      22
-#define CPU_TESTBUS2_IDX                        22
-#define USB_OTG_PRB_IN_IDX                      23
-#define CPU_TESTBUS3_IDX                        23
-#define USB_OTG_SNS_IN_IDX                      24
-#define CPU_TESTBUS4_IDX                        24
-#define CPU_TESTBUS5_IDX                        25
-#define CPU_TESTBUS6_IDX                        26
-#define CPU_TESTBUS7_IDX                        27
-#define CPU_GPIO_IN0_IDX                        28
-#define CPU_GPIO_OUT0_IDX                       28
-#define CPU_GPIO_IN1_IDX                        29
-#define CPU_GPIO_OUT1_IDX                       29
-#define CPU_GPIO_IN2_IDX                        30
-#define CPU_GPIO_OUT2_IDX                       30
-#define CPU_GPIO_IN3_IDX                        31
-#define CPU_GPIO_OUT3_IDX                       31
-#define CPU_GPIO_IN4_IDX                        32
-#define CPU_GPIO_OUT4_IDX                       32
-#define CPU_GPIO_IN5_IDX                        33
-#define CPU_GPIO_OUT5_IDX                       33
-#define CPU_GPIO_IN6_IDX                        34
-#define CPU_GPIO_OUT6_IDX                       34
-#define CPU_GPIO_IN7_IDX                        35
-#define CPU_GPIO_OUT7_IDX                       35
-#define USB_JTAG_TCK_IDX                        36
-#define USB_JTAG_TMS_IDX                        37
-#define USB_JTAG_TDI_IDX                        38
-#define USB_JTAG_TDO_IDX                        39
-#define USB_EXTPHY_VP_IDX                       40
-#define USB_EXTPHY_OEN_IDX                      40
-#define USB_EXTPHY_VM_IDX                       41
-#define USB_EXTPHY_SPEED_IDX                    41
-#define USB_EXTPHY_RCV_IDX                      42
-#define USB_EXTPHY_VPO_IDX                      42
-#define USB_EXTPHY_VMO_IDX                      43
-#define USB_EXTPHY_SUSPND_IDX                   44
-#define I2CEXT0_SCL_IN_IDX                      45
-#define I2CEXT0_SCL_OUT_IDX                     45
-#define I2CEXT0_SDA_IN_IDX                      46
-#define I2CEXT0_SDA_OUT_IDX                     46
-#define PARL_RX_DATA0_IDX                       47
-#define PARL_TX_DATA0_IDX                       47
-#define PARL_RX_DATA1_IDX                       48
-#define PARL_TX_DATA1_IDX                       48
-#define PARL_RX_DATA2_IDX                       49
-#define PARL_TX_DATA2_IDX                       49
-#define PARL_RX_DATA3_IDX                       50
-#define PARL_TX_DATA3_IDX                       50
-#define PARL_RX_DATA4_IDX                       51
-#define PARL_TX_DATA4_IDX                       51
-#define PARL_RX_DATA5_IDX                       52
-#define PARL_TX_DATA5_IDX                       52
-#define PARL_RX_DATA6_IDX                       53
-#define PARL_TX_DATA6_IDX                       53
-#define PARL_RX_DATA7_IDX                       54
-#define PARL_TX_DATA7_IDX                       54
-#define ANT_SEL4_IDX                            55
-#define ANT_SEL5_IDX                            56
-#define ANT_SEL6_IDX                            57
-#define ANT_SEL7_IDX                            58
-#define ANT_SEL8_IDX                            59
-#define ANT_SEL9_IDX                            60
-#define ANT_SEL10_IDX                           61
-#define SDIO_TOHOST_INT_OUT_IDX                 62
-#define FSPICLK_IN_IDX                          63
-#define FSPICLK_OUT_MUX_IDX                     63
-#define FSPIQ_IN_IDX                            64
-#define FSPIQ_OUT_IDX                           64
-#define FSPID_IN_IDX                            65
-#define FSPID_OUT_IDX                           65
-#define FSPIHD_IN_IDX                           66
-#define FSPIHD_OUT_IDX                          66
-#define FSPIWP_IN_IDX                           67
-#define FSPIWP_OUT_IDX                          67
-#define FSPICS0_IN_IDX                          68
-#define FSPICS0_OUT_IDX                         68
-#define PARL_RX_CLK_IN_IDX                      69
-#define PARL_RX_CLK_OUT_IDX                     69
-#define PARL_TX_CLK_IN_IDX                      70
-#define PARL_TX_CLK_OUT_IDX                     70
-#define RMT_SIG_IN0_IDX                         71
-#define RMT_SIG_OUT0_IDX                        71
-#define RMT_SIG_IN1_IDX                         72
-#define RMT_SIG_OUT1_IDX                        72
-#define TWAI0_RX_IDX                            73
-#define TWAI0_TX_IDX                            73
-#define TWAI0_BUS_OFF_ON_IDX                    74
-#define TWAI0_CLKOUT_IDX                        75
-#define TWAI0_STANDBY_IDX                       76
-#define TWAI1_RX_IDX                            77
-#define TWAI1_TX_IDX                            77
-#define TWAI1_BUS_OFF_ON_IDX                    78
-#define TWAI1_CLKOUT_IDX                        79
-#define TWAI1_STANDBY_IDX                       80
-#define EXTERN_PRIORITY_I_IDX                   81
-#define EXTERN_PRIORITY_O_IDX                   81
-#define EXTERN_ACTIVE_I_IDX                     82
-#define EXTERN_ACTIVE_O_IDX                     82
-#define PCNT_RST_IN0_IDX                        83
-#define GPIO_SD0_OUT_IDX                        83
-#define PCNT_RST_IN1_IDX                        84
-#define GPIO_SD1_OUT_IDX                        84
-#define PCNT_RST_IN2_IDX                        85
-#define GPIO_SD2_OUT_IDX                        85
-#define PCNT_RST_IN3_IDX                        86
-#define GPIO_SD3_OUT_IDX                        86
-#define PWM0_SYNC0_IN_IDX                       87
-#define PWM0_OUT0A_IDX                          87
-#define PWM0_SYNC1_IN_IDX                       88
-#define PWM0_OUT0B_IDX                          88
-#define PWM0_SYNC2_IN_IDX                       89
-#define PWM0_OUT1A_IDX                          89
-#define PWM0_F0_IN_IDX                          90
-#define PWM0_OUT1B_IDX                          90
-#define PWM0_F1_IN_IDX                          91
-#define PWM0_OUT2A_IDX                          91
-#define PWM0_F2_IN_IDX                          92
-#define PWM0_OUT2B_IDX                          92
-#define PWM0_CAP0_IN_IDX                        93
-#define ANT_SEL0_IDX                            93
-#define PWM0_CAP1_IN_IDX                        94
-#define ANT_SEL1_IDX                            94
-#define PWM0_CAP2_IN_IDX                        95
-#define ANT_SEL2_IDX                            95
-#define ANT_SEL3_IDX                            96
-#define SIG_IN_FUNC_97_IDX                      97
-#define SIG_IN_FUNC97_IDX                       97
-#define SIG_IN_FUNC_98_IDX                      98
-#define SIG_IN_FUNC98_IDX                       98
-#define SIG_IN_FUNC_99_IDX                      99
-#define SIG_IN_FUNC99_IDX                       99
-#define SIG_IN_FUNC_100_IDX                     100
-#define SIG_IN_FUNC100_IDX                      100
-#define PCNT_SIG_CH0_IN0_IDX                    101
-#define FSPICS1_OUT_IDX                         101
-#define PCNT_SIG_CH1_IN0_IDX                    102
-#define FSPICS2_OUT_IDX                         102
-#define PCNT_CTRL_CH0_IN0_IDX                   103
-#define FSPICS3_OUT_IDX                         103
-#define PCNT_CTRL_CH1_IN0_IDX                   104
-#define FSPICS4_OUT_IDX                         104
-#define PCNT_SIG_CH0_IN1_IDX                    105
-#define FSPICS5_OUT_IDX                         105
-#define PCNT_SIG_CH1_IN1_IDX                    106
-#define USB_OTG_CHRG_OUT_IDX                    106
-#define PCNT_CTRL_CH0_IN1_IDX                   107
-#define USB_OTG_DISCHRG_OUT_IDX                 107
-#define PCNT_CTRL_CH1_IN1_IDX                   108
-#define USB_OTG_PRB_EN_OUT_IDX                  108
-#define PCNT_SIG_CH0_IN2_IDX                    109
-#define USB_OTG_SNS_EN_OUT_IDX                  109
-#define PCNT_SIG_CH1_IN2_IDX                    110
-#define ANT_SEL11_IDX                           110
-#define PCNT_CTRL_CH0_IN2_IDX                   111
-#define ANT_SEL12_IDX                           111
-#define PCNT_CTRL_CH1_IN2_IDX                   112
-#define ANT_SEL13_IDX                           112
-#define PCNT_SIG_CH0_IN3_IDX                    113
-#define ANT_SEL14_IDX                           113
-#define PCNT_SIG_CH1_IN3_IDX                    114
-#define SPICLK_OUT_MUX_IDX                      114
-#define PCNT_CTRL_CH0_IN3_IDX                   115
-#define SPICS0_OUT_IDX                          115
-#define PCNT_CTRL_CH1_IN3_IDX                   116
-#define SPICS1_OUT_IDX                          116
-#define GPIO_EVENT_MATRIX_IN0_IDX               117
-#define GPIO_TASK_MATRIX_OUT0_IDX               117
-#define GPIO_EVENT_MATRIX_IN1_IDX               118
-#define GPIO_TASK_MATRIX_OUT1_IDX               118
-#define GPIO_EVENT_MATRIX_IN2_IDX               119
-#define GPIO_TASK_MATRIX_OUT2_IDX               119
-#define GPIO_EVENT_MATRIX_IN3_IDX               120
-#define GPIO_TASK_MATRIX_OUT3_IDX               120
-#define SPIQ_IN_IDX                             121
-#define SPIQ_OUT_IDX                            121
-#define SPID_IN_IDX                             122
-#define SPID_OUT_IDX                            122
-#define SPIHD_IN_IDX                            123
-#define SPIHD_OUT_IDX                           123
-#define SPIWP_IN_IDX                            124
-#define SPIWP_OUT_IDX                           124
-#define CLK_OUT_OUT1_IDX                        125
-#define CLK_OUT_OUT2_IDX                        126
-#define CLK_OUT_OUT3_IDX                        127
-// version date 2301100
-#define SIG_GPIO_OUT_IDX                        128
diff --git a/components/soc/esp32c5/beta3/include/soc/gpio_struct.h b/components/soc/esp32c5/beta3/include/soc/gpio_struct.h
deleted file mode 100644
index d8c1203e97..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/gpio_struct.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configuration register */
-/** Type of bt_select register
- *  GPIO bit select register
- */
-typedef union {
-    struct {
-        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
-         *  GPIO bit select register
-         */
-        uint32_t bt_sel:32;
-    };
-    uint32_t val;
-} gpio_bt_select_reg_t;
-
-/** Type of out register
- *  GPIO output register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** out_data_orig : R/W/SC/WTC; bitpos: [30:0]; default: 0;
-         *  GPIO output register for GPIO0-30
-         */
-        uint32_t out_data_orig:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_out_reg_t;
-
-/** Type of out_w1ts register
- *  GPIO output set register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** out_w1ts : WT; bitpos: [30:0]; default: 0;
-         *  GPIO output set register for GPIO0-30
-         */
-        uint32_t out_w1ts:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_out_w1ts_reg_t;
-
-/** Type of out_w1tc register
- *  GPIO output clear register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** out_w1tc : WT; bitpos: [30:0]; default: 0;
-         *  GPIO output clear register for GPIO0-30
-         */
-        uint32_t out_w1tc:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_out_w1tc_reg_t;
-
-/** Type of sdio_select register
- *  GPIO sdio select register
- */
-typedef union {
-    struct {
-        /** sdio_sel : R/W; bitpos: [7:0]; default: 0;
-         *  GPIO sdio select register
-         */
-        uint32_t sdio_sel:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_sdio_select_reg_t;
-
-/** Type of enable register
- *  GPIO output enable register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** enable_data : R/W/WTC; bitpos: [30:0]; default: 0;
-         *  GPIO output enable register for GPIO0-30
-         */
-        uint32_t enable_data:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_enable_reg_t;
-
-/** Type of enable_w1ts register
- *  GPIO output enable set register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** enable_w1ts : WT; bitpos: [30:0]; default: 0;
-         *  GPIO output enable set register for GPIO0-30
-         */
-        uint32_t enable_w1ts:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_enable_w1ts_reg_t;
-
-/** Type of enable_w1tc register
- *  GPIO output enable clear register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** enable_w1tc : WT; bitpos: [30:0]; default: 0;
-         *  GPIO output enable clear register for GPIO0-30
-         */
-        uint32_t enable_w1tc:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_enable_w1tc_reg_t;
-
-/** Type of strap register
- *  pad strapping register
- */
-typedef union {
-    struct {
-        /** strapping : RO; bitpos: [15:0]; default: 0;
-         *  pad strapping register
-         */
-        uint32_t strapping:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} gpio_strap_reg_t;
-
-/** Type of in register
- *  GPIO input register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** in_data_next : RO; bitpos: [30:0]; default: 0;
-         *  GPIO input register for GPIO0-30
-         */
-        uint32_t in_data_next:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_in_reg_t;
-
-/** Type of status register
- *  GPIO interrupt status register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** status_interrupt : R/W/WTC; bitpos: [30:0]; default: 0;
-         *  GPIO interrupt status register for GPIO0-30
-         */
-        uint32_t status_interrupt:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_status_reg_t;
-
-/** Type of status_w1ts register
- *  GPIO interrupt status set register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** status_w1ts : WT; bitpos: [30:0]; default: 0;
-         *  GPIO interrupt status set register for GPIO0-30
-         */
-        uint32_t status_w1ts:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_status_w1ts_reg_t;
-
-/** Type of status_w1tc register
- *  GPIO interrupt status clear register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** status_w1tc : WT; bitpos: [30:0]; default: 0;
-         *  GPIO interrupt status clear register for GPIO0-30
-         */
-        uint32_t status_w1tc:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_status_w1tc_reg_t;
-
-/** Type of pcpu_int register
- *  GPIO PRO_CPU interrupt status register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** procpu_int : RO; bitpos: [30:0]; default: 0;
-         *  GPIO PRO_CPU interrupt status register for GPIO0-30
-         */
-        uint32_t procpu_int:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_pcpu_int_reg_t;
-
-/** Type of pcpu_nmi_int register
- *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** procpu_nmi_int : RO; bitpos: [30:0]; default: 0;
-         *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-30
-         */
-        uint32_t procpu_nmi_int:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_pcpu_nmi_int_reg_t;
-
-/** Type of cpusdio_int register
- *  GPIO CPUSDIO interrupt status register for GPIO0-30
- */
-typedef union {
-    struct {
-        /** sdio_int : RO; bitpos: [30:0]; default: 0;
-         *  GPIO CPUSDIO interrupt status register for GPIO0-30
-         */
-        uint32_t sdio_int:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_cpusdio_int_reg_t;
-
-/** Type of pinn register
- *  GPIO pin configuration register
- */
-typedef union {
-    struct {
-        /** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
-         *  posedge.
-         */
-        uint32_t sync2_bypass:2;
-        /** pad_driver : R/W; bitpos: [2]; default: 0;
-         *  set this bit to select pad driver. 1:open-drain. 0:normal.
-         */
-        uint32_t pad_driver:1;
-        /** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
-         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
-         *  posedge.
-         */
-        uint32_t sync1_bypass:2;
-        uint32_t reserved_5:2;
-        /** int_type : R/W; bitpos: [9:7]; default: 0;
-         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
-         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
-         *  at high level
-         */
-        uint32_t int_type:3;
-        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-         */
-        uint32_t wakeup_enable:1;
-        /** config : R/W; bitpos: [12:11]; default: 0;
-         *  reserved
-         */
-        uint32_t config:2;
-        /** int_ena : R/W; bitpos: [17:13]; default: 0;
-         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-         *  interrupt.
-         */
-        uint32_t int_ena:5;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} gpio_pinn_reg_t;
-
-/** Type of status_next register
- *  GPIO interrupt source register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** status_interrupt_next : RO; bitpos: [30:0]; default: 0;
-         *  GPIO interrupt source register for GPIO0-31
-         */
-        uint32_t status_interrupt_next:31;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} gpio_status_next_reg_t;
-
-/** Type of func_in_sel_cfg register
- *  GPIO input function configuration register
- */
-typedef union {
-    struct {
-        /** in_sel : R/W; bitpos: [5:0]; default: 60;
-         *  set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always
-         *  high level. s=0x3C: set this port always low level.
-         */
-        uint32_t in_sel:6;
-        /** in_inv_sel : R/W; bitpos: [6]; default: 0;
-         *  set this bit to invert input signal. 1:invert. 0:not invert.
-         */
-        uint32_t in_inv_sel:1;
-        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
-         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
-         */
-        uint32_t sig_in_sel:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_func_in_sel_cfg_reg_t;
-
-/** Type of func_out_sel_cfg register
- *  GPIO output function select register
- */
-typedef union {
-    struct {
-        /** out_sel : R/W/SC; bitpos: [7:0]; default: 128;
-         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
-         *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
-         *  GPIO_OUT_REG[n].
-         */
-        uint32_t out_sel:8;
-        /** out_inv_sel : R/W/SC; bitpos: [8]; default: 0;
-         *  set this bit to invert output signal.1:invert.0:not invert.
-         */
-        uint32_t out_inv_sel:1;
-        /** oen_sel : R/W; bitpos: [9]; default: 0;
-         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-         *  enable signal.0:use peripheral output enable signal.
-         */
-        uint32_t oen_sel:1;
-        /** oen_inv_sel : R/W; bitpos: [10]; default: 0;
-         *  set this bit to invert output enable signal.1:invert.0:not invert.
-         */
-        uint32_t oen_inv_sel:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} gpio_func_out_sel_cfg_reg_t;
-
-/** Type of clock_gate register
- *  GPIO clock gate register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  set this bit to enable GPIO clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} gpio_clock_gate_reg_t;
-
-/** Type of date register
- *  GPIO version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36704512;
-         *  version register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_date_reg_t;
-
-
-typedef struct gpio_dev_t {
-    volatile gpio_bt_select_reg_t bt_select;
-    volatile gpio_out_reg_t out;
-    volatile gpio_out_w1ts_reg_t out_w1ts;
-    volatile gpio_out_w1tc_reg_t out_w1tc;
-    uint32_t reserved_010[3];
-    volatile gpio_sdio_select_reg_t sdio_select;
-    volatile gpio_enable_reg_t enable;
-    volatile gpio_enable_w1ts_reg_t enable_w1ts;
-    volatile gpio_enable_w1tc_reg_t enable_w1tc;
-    uint32_t reserved_02c[3];
-    volatile gpio_strap_reg_t strap;
-    volatile gpio_in_reg_t in;
-    uint32_t reserved_040;
-    volatile gpio_status_reg_t status;
-    volatile gpio_status_w1ts_reg_t status_w1ts;
-    volatile gpio_status_w1tc_reg_t status_w1tc;
-    uint32_t reserved_050[3];
-    volatile gpio_pcpu_int_reg_t pcpu_int;
-    volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
-    volatile gpio_cpusdio_int_reg_t cpusdio_int;
-    uint32_t reserved_068[3];
-    volatile gpio_pinn_reg_t pin[31];
-    uint32_t reserved_0f0[23];
-    volatile gpio_status_next_reg_t status_next;
-    uint32_t reserved_150;
-    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; /* Reserved func: 1-5, 18, 20, 25-27, 36-39, 43-44, 55-62, 74-76, 78-80, 96, 125-127 */
-    uint32_t reserved_34b[128];
-    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[31];
-    uint32_t reserved_5d0[23];
-    volatile gpio_clock_gate_reg_t clock_gate;
-    uint32_t reserved_630[51];
-    volatile gpio_date_reg_t date;
-} gpio_dev_t;
-
-extern gpio_dev_t GPIO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hardware_lock_reg.h b/components/soc/esp32c5/beta3/include/soc/hardware_lock_reg.h
deleted file mode 100644
index 75451751c6..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hardware_lock_reg.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ATOMIC_ADDR_LOCK_REG register
- *  hardware lock regsiter
- */
-#define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
-/** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
- *  read to acquire hardware lock, write to release hardware lock
- */
-#define ATOMIC_LOCK    0x00000003U
-#define ATOMIC_LOCK_M  (ATOMIC_LOCK_V << ATOMIC_LOCK_S)
-#define ATOMIC_LOCK_V  0x00000003U
-#define ATOMIC_LOCK_S  0
-
-/** ATOMIC_LR_ADDR_REG register
- *  gloable lr address regsiter
- */
-#define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
-/** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  backup gloable address
- */
-#define ATOMIC_GLOABLE_LR_ADDR    0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_ADDR_M  (ATOMIC_GLOABLE_LR_ADDR_V << ATOMIC_GLOABLE_LR_ADDR_S)
-#define ATOMIC_GLOABLE_LR_ADDR_V  0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_ADDR_S  0
-
-/** ATOMIC_LR_VALUE_REG register
- *  gloable lr value regsiter
- */
-#define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
-/** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  backup gloable value
- */
-#define ATOMIC_GLOABLE_LR_VALUE    0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_VALUE_M  (ATOMIC_GLOABLE_LR_VALUE_V << ATOMIC_GLOABLE_LR_VALUE_S)
-#define ATOMIC_GLOABLE_LR_VALUE_V  0xFFFFFFFFU
-#define ATOMIC_GLOABLE_LR_VALUE_S  0
-
-/** ATOMIC_LOCK_STATUS_REG register
- *  lock status regsiter
- */
-#define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
-/** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
- *  read hareware lock status for debug
- */
-#define ATOMIC_LOCK_STATUS    0x00000003U
-#define ATOMIC_LOCK_STATUS_M  (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
-#define ATOMIC_LOCK_STATUS_V  0x00000003U
-#define ATOMIC_LOCK_STATUS_S  0
-
-/** ATOMIC_COUNTER_REG register
- *  wait counter register
- */
-#define ATOMIC_COUNTER_REG (DR_REG_ATOMIC_BASE + 0x10)
-/** ATOMIC_WAIT_COUNTER : R/W; bitpos: [15:0]; default: 0;
- *  delay counter
- */
-#define ATOMIC_WAIT_COUNTER    0x0000FFFFU
-#define ATOMIC_WAIT_COUNTER_M  (ATOMIC_WAIT_COUNTER_V << ATOMIC_WAIT_COUNTER_S)
-#define ATOMIC_WAIT_COUNTER_V  0x0000FFFFU
-#define ATOMIC_WAIT_COUNTER_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hardware_lock_struct.h b/components/soc/esp32c5/beta3/include/soc/hardware_lock_struct.h
deleted file mode 100644
index 799d6b4ba9..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hardware_lock_struct.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configuration registers */
-/** Type of addr_lock register
- *  hardware lock regsiter
- */
-typedef union {
-    struct {
-        /** lock : R/W; bitpos: [1:0]; default: 0;
-         *  read to acquire hardware lock, write to release hardware lock
-         */
-        uint32_t lock:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} atomic_addr_lock_reg_t;
-
-/** Type of lr_addr register
- *  gloable lr address regsiter
- */
-typedef union {
-    struct {
-        /** gloable_lr_addr : R/W; bitpos: [31:0]; default: 0;
-         *  backup gloable address
-         */
-        uint32_t gloable_lr_addr:32;
-    };
-    uint32_t val;
-} atomic_lr_addr_reg_t;
-
-/** Type of lr_value register
- *  gloable lr value regsiter
- */
-typedef union {
-    struct {
-        /** gloable_lr_value : R/W; bitpos: [31:0]; default: 0;
-         *  backup gloable value
-         */
-        uint32_t gloable_lr_value:32;
-    };
-    uint32_t val;
-} atomic_lr_value_reg_t;
-
-/** Type of lock_status register
- *  lock status regsiter
- */
-typedef union {
-    struct {
-        /** lock_status : RO; bitpos: [1:0]; default: 0;
-         *  read hareware lock status for debug
-         */
-        uint32_t lock_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} atomic_lock_status_reg_t;
-
-/** Type of counter register
- *  wait counter register
- */
-typedef union {
-    struct {
-        /** wait_counter : R/W; bitpos: [15:0]; default: 0;
-         *  delay counter
-         */
-        uint32_t wait_counter:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} atomic_counter_reg_t;
-
-
-typedef struct atomic_dev_t {
-    volatile atomic_addr_lock_reg_t addr_lock;
-    volatile atomic_lr_addr_reg_t lr_addr;
-    volatile atomic_lr_value_reg_t lr_value;
-    volatile atomic_lock_status_reg_t lock_status;
-    volatile atomic_counter_reg_t counter;
-} atomic_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(atomic_dev_t) == 0x14, "Invalid size of atomic_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hmac_reg.h b/components/soc/esp32c5/beta3/include/soc/hmac_reg.h
deleted file mode 100644
index 9ed7eb1273..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hmac_reg.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HMAC_SET_START_REG register
- *  Process control register 0.
- */
-#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
-/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
- *  Start hmac operation.
- */
-#define HMAC_SET_START    (BIT(0))
-#define HMAC_SET_START_M  (HMAC_SET_START_V << HMAC_SET_START_S)
-#define HMAC_SET_START_V  0x00000001U
-#define HMAC_SET_START_S  0
-
-/** HMAC_SET_PARA_PURPOSE_REG register
- *  Configure purpose.
- */
-#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
-/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
- *  Set hmac parameter purpose.
- */
-#define HMAC_PURPOSE_SET    0x0000000FU
-#define HMAC_PURPOSE_SET_M  (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
-#define HMAC_PURPOSE_SET_V  0x0000000FU
-#define HMAC_PURPOSE_SET_S  0
-
-/** HMAC_SET_PARA_KEY_REG register
- *  Configure key.
- */
-#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
-/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
- *  Set hmac parameter key.
- */
-#define HMAC_KEY_SET    0x00000007U
-#define HMAC_KEY_SET_M  (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
-#define HMAC_KEY_SET_V  0x00000007U
-#define HMAC_KEY_SET_S  0
-
-/** HMAC_SET_PARA_FINISH_REG register
- *  Finish initial configuration.
- */
-#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
-/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
- *  Finish hmac configuration.
- */
-#define HMAC_SET_PARA_END    (BIT(0))
-#define HMAC_SET_PARA_END_M  (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
-#define HMAC_SET_PARA_END_V  0x00000001U
-#define HMAC_SET_PARA_END_S  0
-
-/** HMAC_SET_MESSAGE_ONE_REG register
- *  Process control register 1.
- */
-#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
-/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
- *  Call SHA to calculate one message block.
- */
-#define HMAC_SET_TEXT_ONE    (BIT(0))
-#define HMAC_SET_TEXT_ONE_M  (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
-#define HMAC_SET_TEXT_ONE_V  0x00000001U
-#define HMAC_SET_TEXT_ONE_S  0
-
-/** HMAC_SET_MESSAGE_ING_REG register
- *  Process control register 2.
- */
-#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
-/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
- *  Continue typical hmac.
- */
-#define HMAC_SET_TEXT_ING    (BIT(0))
-#define HMAC_SET_TEXT_ING_M  (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
-#define HMAC_SET_TEXT_ING_V  0x00000001U
-#define HMAC_SET_TEXT_ING_S  0
-
-/** HMAC_SET_MESSAGE_END_REG register
- *  Process control register 3.
- */
-#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
-/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
- *  Start hardware padding.
- */
-#define HMAC_SET_TEXT_END    (BIT(0))
-#define HMAC_SET_TEXT_END_M  (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
-#define HMAC_SET_TEXT_END_V  0x00000001U
-#define HMAC_SET_TEXT_END_S  0
-
-/** HMAC_SET_RESULT_FINISH_REG register
- *  Process control register 4.
- */
-#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
-/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
- *  After read result from upstream, then let hmac back to idle.
- */
-#define HMAC_SET_RESULT_END    (BIT(0))
-#define HMAC_SET_RESULT_END_M  (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
-#define HMAC_SET_RESULT_END_V  0x00000001U
-#define HMAC_SET_RESULT_END_S  0
-
-/** HMAC_SET_INVALIDATE_JTAG_REG register
- *  Invalidate register 0.
- */
-#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
-/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
- *  Clear result from hmac downstream JTAG.
- */
-#define HMAC_SET_INVALIDATE_JTAG    (BIT(0))
-#define HMAC_SET_INVALIDATE_JTAG_M  (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
-#define HMAC_SET_INVALIDATE_JTAG_V  0x00000001U
-#define HMAC_SET_INVALIDATE_JTAG_S  0
-
-/** HMAC_SET_INVALIDATE_DS_REG register
- *  Invalidate register 1.
- */
-#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
-/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
- *  Clear result from hmac downstream DS.
- */
-#define HMAC_SET_INVALIDATE_DS    (BIT(0))
-#define HMAC_SET_INVALIDATE_DS_M  (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
-#define HMAC_SET_INVALIDATE_DS_V  0x00000001U
-#define HMAC_SET_INVALIDATE_DS_S  0
-
-/** HMAC_QUERY_ERROR_REG register
- *  Error register.
- */
-#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
-/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
- *  Hmac configuration state. 0: key are agree with purpose. 1: error
- */
-#define HMAC_QUREY_CHECK    (BIT(0))
-#define HMAC_QUREY_CHECK_M  (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
-#define HMAC_QUREY_CHECK_V  0x00000001U
-#define HMAC_QUREY_CHECK_S  0
-
-/** HMAC_QUERY_BUSY_REG register
- *  Busy register.
- */
-#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
-/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
- *  Hmac state. 1'b0: idle. 1'b1: busy
- */
-#define HMAC_BUSY_STATE    (BIT(0))
-#define HMAC_BUSY_STATE_M  (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
-#define HMAC_BUSY_STATE_V  0x00000001U
-#define HMAC_BUSY_STATE_S  0
-
-/** HMAC_WR_MESSAGE_MEM register
- *  Message block memory.
- */
-#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
-#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
-
-/** HMAC_RD_RESULT_MEM register
- *  Result from upstream.
- */
-#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
-#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
-
-/** HMAC_SET_MESSAGE_PAD_REG register
- *  Process control register 5.
- */
-#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
-/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
- *  Start software padding.
- */
-#define HMAC_SET_TEXT_PAD    (BIT(0))
-#define HMAC_SET_TEXT_PAD_M  (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
-#define HMAC_SET_TEXT_PAD_V  0x00000001U
-#define HMAC_SET_TEXT_PAD_S  0
-
-/** HMAC_ONE_BLOCK_REG register
- *  Process control register 6.
- */
-#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
-/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
- *  Don't have to do padding.
- */
-#define HMAC_SET_ONE_BLOCK    (BIT(0))
-#define HMAC_SET_ONE_BLOCK_M  (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
-#define HMAC_SET_ONE_BLOCK_V  0x00000001U
-#define HMAC_SET_ONE_BLOCK_S  0
-
-/** HMAC_SOFT_JTAG_CTRL_REG register
- *  Jtag register 0.
- */
-#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
-/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
- *  Turn on JTAG verification.
- */
-#define HMAC_SOFT_JTAG_CTRL    (BIT(0))
-#define HMAC_SOFT_JTAG_CTRL_M  (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
-#define HMAC_SOFT_JTAG_CTRL_V  0x00000001U
-#define HMAC_SOFT_JTAG_CTRL_S  0
-
-/** HMAC_WR_JTAG_REG register
- *  Jtag register 1.
- */
-#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
-/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
- *  32-bit of key to be compared.
- */
-#define HMAC_WR_JTAG    0xFFFFFFFFU
-#define HMAC_WR_JTAG_M  (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
-#define HMAC_WR_JTAG_V  0xFFFFFFFFU
-#define HMAC_WR_JTAG_S  0
-
-/** HMAC_DATE_REG register
- *  Date register.
- */
-#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
-/** HMAC_DATE : R/W; bitpos: [29:0]; default: 538969624;
- *  Hmac date information/ hmac version information.
- */
-#define HMAC_DATE    0x3FFFFFFFU
-#define HMAC_DATE_M  (HMAC_DATE_V << HMAC_DATE_S)
-#define HMAC_DATE_V  0x3FFFFFFFU
-#define HMAC_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hmac_struct.h b/components/soc/esp32c5/beta3/include/soc/hmac_struct.h
deleted file mode 100644
index 088c652c51..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hmac_struct.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of set_start register
- *  Process control register 0.
- */
-typedef union {
-    struct {
-        /** set_start : WS; bitpos: [0]; default: 0;
-         *  Start hmac operation.
-         */
-        uint32_t set_start:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_start_reg_t;
-
-/** Type of set_para_purpose register
- *  Configure purpose.
- */
-typedef union {
-    struct {
-        /** purpose_set : WO; bitpos: [3:0]; default: 0;
-         *  Set hmac parameter purpose.
-         */
-        uint32_t purpose_set:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hmac_set_para_purpose_reg_t;
-
-/** Type of set_para_key register
- *  Configure key.
- */
-typedef union {
-    struct {
-        /** key_set : WO; bitpos: [2:0]; default: 0;
-         *  Set hmac parameter key.
-         */
-        uint32_t key_set:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hmac_set_para_key_reg_t;
-
-/** Type of set_para_finish register
- *  Finish initial configuration.
- */
-typedef union {
-    struct {
-        /** set_para_end : WS; bitpos: [0]; default: 0;
-         *  Finish hmac configuration.
-         */
-        uint32_t set_para_end:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_para_finish_reg_t;
-
-/** Type of set_message_one register
- *  Process control register 1.
- */
-typedef union {
-    struct {
-        /** set_text_one : WS; bitpos: [0]; default: 0;
-         *  Call SHA to calculate one message block.
-         */
-        uint32_t set_text_one:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_message_one_reg_t;
-
-/** Type of set_message_ing register
- *  Process control register 2.
- */
-typedef union {
-    struct {
-        /** set_text_ing : WS; bitpos: [0]; default: 0;
-         *  Continue typical hmac.
-         */
-        uint32_t set_text_ing:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_message_ing_reg_t;
-
-/** Type of set_message_end register
- *  Process control register 3.
- */
-typedef union {
-    struct {
-        /** set_text_end : WS; bitpos: [0]; default: 0;
-         *  Start hardware padding.
-         */
-        uint32_t set_text_end:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_message_end_reg_t;
-
-/** Type of set_result_finish register
- *  Process control register 4.
- */
-typedef union {
-    struct {
-        /** set_result_end : WS; bitpos: [0]; default: 0;
-         *  After read result from upstream, then let hmac back to idle.
-         */
-        uint32_t set_result_end:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_result_finish_reg_t;
-
-/** Type of set_invalidate_jtag register
- *  Invalidate register 0.
- */
-typedef union {
-    struct {
-        /** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
-         *  Clear result from hmac downstream JTAG.
-         */
-        uint32_t set_invalidate_jtag:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_invalidate_jtag_reg_t;
-
-/** Type of set_invalidate_ds register
- *  Invalidate register 1.
- */
-typedef union {
-    struct {
-        /** set_invalidate_ds : WS; bitpos: [0]; default: 0;
-         *  Clear result from hmac downstream DS.
-         */
-        uint32_t set_invalidate_ds:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_invalidate_ds_reg_t;
-
-/** Type of set_message_pad register
- *  Process control register 5.
- */
-typedef union {
-    struct {
-        /** set_text_pad : WO; bitpos: [0]; default: 0;
-         *  Start software padding.
-         */
-        uint32_t set_text_pad:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_set_message_pad_reg_t;
-
-/** Type of one_block register
- *  Process control register 6.
- */
-typedef union {
-    struct {
-        /** set_one_block : WS; bitpos: [0]; default: 0;
-         *  Don't have to do padding.
-         */
-        uint32_t set_one_block:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_one_block_reg_t;
-
-/** Type of soft_jtag_ctrl register
- *  Jtag register 0.
- */
-typedef union {
-    struct {
-        /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
-         *  Turn on JTAG verification.
-         */
-        uint32_t soft_jtag_ctrl:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_soft_jtag_ctrl_reg_t;
-
-/** Type of wr_jtag register
- *  Jtag register 1.
- */
-typedef union {
-    struct {
-        /** wr_jtag : WO; bitpos: [31:0]; default: 0;
-         *  32-bit of key to be compared.
-         */
-        uint32_t wr_jtag:32;
-    };
-    uint32_t val;
-} hmac_wr_jtag_reg_t;
-
-
-/** Group: Status Register */
-/** Type of query_error register
- *  Error register.
- */
-typedef union {
-    struct {
-        /** qurey_check : RO; bitpos: [0]; default: 0;
-         *  Hmac configuration state. 0: key are agree with purpose. 1: error
-         */
-        uint32_t qurey_check:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_query_error_reg_t;
-
-/** Type of query_busy register
- *  Busy register.
- */
-typedef union {
-    struct {
-        /** busy_state : RO; bitpos: [0]; default: 0;
-         *  Hmac state. 1'b0: idle. 1'b1: busy
-         */
-        uint32_t busy_state:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hmac_query_busy_reg_t;
-
-
-/** Group: Memory Type */
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [29:0]; default: 538969624;
-         *  Hmac date information/ hmac version information.
-         */
-        uint32_t date:30;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} hmac_date_reg_t;
-
-
-typedef struct hmac_dev_t {
-    uint32_t reserved_000[16];
-    volatile hmac_set_start_reg_t set_start;
-    volatile hmac_set_para_purpose_reg_t set_para_purpose;
-    volatile hmac_set_para_key_reg_t set_para_key;
-    volatile hmac_set_para_finish_reg_t set_para_finish;
-    volatile hmac_set_message_one_reg_t set_message_one;
-    volatile hmac_set_message_ing_reg_t set_message_ing;
-    volatile hmac_set_message_end_reg_t set_message_end;
-    volatile hmac_set_result_finish_reg_t set_result_finish;
-    volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
-    volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
-    volatile hmac_query_error_reg_t query_error;
-    volatile hmac_query_busy_reg_t query_busy;
-    uint32_t reserved_070[4];
-    volatile uint32_t wr_message[16];
-    volatile uint32_t rd_result[8];
-    uint32_t reserved_0e0[4];
-    volatile hmac_set_message_pad_reg_t set_message_pad;
-    volatile hmac_one_block_reg_t one_block;
-    volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
-    volatile hmac_wr_jtag_reg_t wr_jtag;
-    uint32_t reserved_100[63];
-    volatile hmac_date_reg_t date;
-} hmac_dev_t;
-
-extern hmac_dev_t HMAC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hp_apm_reg.h b/components/soc/esp32c5/beta3/include/soc/hp_apm_reg.h
deleted file mode 100644
index 5779eea6fa..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hp_apm_reg.h
+++ /dev/null
@@ -1,1950 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HP_APM_REGION_FILTER_EN_REG register
- *  Region filter enable register
- */
-#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0)
-/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1;
- *  Region filter enable
- */
-#define HP_APM_REGION_FILTER_EN    0x0000FFFFU
-#define HP_APM_REGION_FILTER_EN_M  (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S)
-#define HP_APM_REGION_FILTER_EN_V  0x0000FFFFU
-#define HP_APM_REGION_FILTER_EN_S  0
-
-/** HP_APM_REGION0_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4)
-/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region0
- */
-#define HP_APM_REGION0_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_START_M  (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S)
-#define HP_APM_REGION0_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_START_S  0
-
-/** HP_APM_REGION0_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8)
-/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region0
- */
-#define HP_APM_REGION0_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_END_M  (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S)
-#define HP_APM_REGION0_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION0_ADDR_END_S  0
-
-/** HP_APM_REGION0_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION0_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc)
-/** HP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION0_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION0_R0_PMS_X_M  (HP_APM_REGION0_R0_PMS_X_V << HP_APM_REGION0_R0_PMS_X_S)
-#define HP_APM_REGION0_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION0_R0_PMS_X_S  0
-/** HP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION0_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION0_R0_PMS_W_M  (HP_APM_REGION0_R0_PMS_W_V << HP_APM_REGION0_R0_PMS_W_S)
-#define HP_APM_REGION0_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION0_R0_PMS_W_S  1
-/** HP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION0_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION0_R0_PMS_R_M  (HP_APM_REGION0_R0_PMS_R_V << HP_APM_REGION0_R0_PMS_R_S)
-#define HP_APM_REGION0_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION0_R0_PMS_R_S  2
-/** HP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION0_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION0_R1_PMS_X_M  (HP_APM_REGION0_R1_PMS_X_V << HP_APM_REGION0_R1_PMS_X_S)
-#define HP_APM_REGION0_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION0_R1_PMS_X_S  4
-/** HP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION0_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION0_R1_PMS_W_M  (HP_APM_REGION0_R1_PMS_W_V << HP_APM_REGION0_R1_PMS_W_S)
-#define HP_APM_REGION0_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION0_R1_PMS_W_S  5
-/** HP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION0_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION0_R1_PMS_R_M  (HP_APM_REGION0_R1_PMS_R_V << HP_APM_REGION0_R1_PMS_R_S)
-#define HP_APM_REGION0_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION0_R1_PMS_R_S  6
-/** HP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION0_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION0_R2_PMS_X_M  (HP_APM_REGION0_R2_PMS_X_V << HP_APM_REGION0_R2_PMS_X_S)
-#define HP_APM_REGION0_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION0_R2_PMS_X_S  8
-/** HP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION0_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION0_R2_PMS_W_M  (HP_APM_REGION0_R2_PMS_W_V << HP_APM_REGION0_R2_PMS_W_S)
-#define HP_APM_REGION0_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION0_R2_PMS_W_S  9
-/** HP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION0_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION0_R2_PMS_R_M  (HP_APM_REGION0_R2_PMS_R_V << HP_APM_REGION0_R2_PMS_R_S)
-#define HP_APM_REGION0_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION0_R2_PMS_R_S  10
-/** HP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define HP_APM_REGION0_LOCK    (BIT(11))
-#define HP_APM_REGION0_LOCK_M  (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S)
-#define HP_APM_REGION0_LOCK_V  0x00000001U
-#define HP_APM_REGION0_LOCK_S  11
-
-/** HP_APM_REGION1_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10)
-/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region1
- */
-#define HP_APM_REGION1_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_START_M  (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S)
-#define HP_APM_REGION1_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_START_S  0
-
-/** HP_APM_REGION1_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14)
-/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region1
- */
-#define HP_APM_REGION1_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_END_M  (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S)
-#define HP_APM_REGION1_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION1_ADDR_END_S  0
-
-/** HP_APM_REGION1_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION1_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x18)
-/** HP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION1_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION1_R0_PMS_X_M  (HP_APM_REGION1_R0_PMS_X_V << HP_APM_REGION1_R0_PMS_X_S)
-#define HP_APM_REGION1_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION1_R0_PMS_X_S  0
-/** HP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION1_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION1_R0_PMS_W_M  (HP_APM_REGION1_R0_PMS_W_V << HP_APM_REGION1_R0_PMS_W_S)
-#define HP_APM_REGION1_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION1_R0_PMS_W_S  1
-/** HP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION1_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION1_R0_PMS_R_M  (HP_APM_REGION1_R0_PMS_R_V << HP_APM_REGION1_R0_PMS_R_S)
-#define HP_APM_REGION1_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION1_R0_PMS_R_S  2
-/** HP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION1_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION1_R1_PMS_X_M  (HP_APM_REGION1_R1_PMS_X_V << HP_APM_REGION1_R1_PMS_X_S)
-#define HP_APM_REGION1_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION1_R1_PMS_X_S  4
-/** HP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION1_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION1_R1_PMS_W_M  (HP_APM_REGION1_R1_PMS_W_V << HP_APM_REGION1_R1_PMS_W_S)
-#define HP_APM_REGION1_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION1_R1_PMS_W_S  5
-/** HP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION1_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION1_R1_PMS_R_M  (HP_APM_REGION1_R1_PMS_R_V << HP_APM_REGION1_R1_PMS_R_S)
-#define HP_APM_REGION1_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION1_R1_PMS_R_S  6
-/** HP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION1_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION1_R2_PMS_X_M  (HP_APM_REGION1_R2_PMS_X_V << HP_APM_REGION1_R2_PMS_X_S)
-#define HP_APM_REGION1_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION1_R2_PMS_X_S  8
-/** HP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION1_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION1_R2_PMS_W_M  (HP_APM_REGION1_R2_PMS_W_V << HP_APM_REGION1_R2_PMS_W_S)
-#define HP_APM_REGION1_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION1_R2_PMS_W_S  9
-/** HP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION1_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION1_R2_PMS_R_M  (HP_APM_REGION1_R2_PMS_R_V << HP_APM_REGION1_R2_PMS_R_S)
-#define HP_APM_REGION1_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION1_R2_PMS_R_S  10
-/** HP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region1 configuration
- */
-#define HP_APM_REGION1_LOCK    (BIT(11))
-#define HP_APM_REGION1_LOCK_M  (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S)
-#define HP_APM_REGION1_LOCK_V  0x00000001U
-#define HP_APM_REGION1_LOCK_S  11
-
-/** HP_APM_REGION2_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c)
-/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region2
- */
-#define HP_APM_REGION2_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_START_M  (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S)
-#define HP_APM_REGION2_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_START_S  0
-
-/** HP_APM_REGION2_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20)
-/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region2
- */
-#define HP_APM_REGION2_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_END_M  (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S)
-#define HP_APM_REGION2_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION2_ADDR_END_S  0
-
-/** HP_APM_REGION2_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION2_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x24)
-/** HP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION2_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION2_R0_PMS_X_M  (HP_APM_REGION2_R0_PMS_X_V << HP_APM_REGION2_R0_PMS_X_S)
-#define HP_APM_REGION2_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION2_R0_PMS_X_S  0
-/** HP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION2_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION2_R0_PMS_W_M  (HP_APM_REGION2_R0_PMS_W_V << HP_APM_REGION2_R0_PMS_W_S)
-#define HP_APM_REGION2_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION2_R0_PMS_W_S  1
-/** HP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION2_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION2_R0_PMS_R_M  (HP_APM_REGION2_R0_PMS_R_V << HP_APM_REGION2_R0_PMS_R_S)
-#define HP_APM_REGION2_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION2_R0_PMS_R_S  2
-/** HP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION2_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION2_R1_PMS_X_M  (HP_APM_REGION2_R1_PMS_X_V << HP_APM_REGION2_R1_PMS_X_S)
-#define HP_APM_REGION2_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION2_R1_PMS_X_S  4
-/** HP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION2_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION2_R1_PMS_W_M  (HP_APM_REGION2_R1_PMS_W_V << HP_APM_REGION2_R1_PMS_W_S)
-#define HP_APM_REGION2_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION2_R1_PMS_W_S  5
-/** HP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION2_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION2_R1_PMS_R_M  (HP_APM_REGION2_R1_PMS_R_V << HP_APM_REGION2_R1_PMS_R_S)
-#define HP_APM_REGION2_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION2_R1_PMS_R_S  6
-/** HP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION2_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION2_R2_PMS_X_M  (HP_APM_REGION2_R2_PMS_X_V << HP_APM_REGION2_R2_PMS_X_S)
-#define HP_APM_REGION2_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION2_R2_PMS_X_S  8
-/** HP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION2_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION2_R2_PMS_W_M  (HP_APM_REGION2_R2_PMS_W_V << HP_APM_REGION2_R2_PMS_W_S)
-#define HP_APM_REGION2_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION2_R2_PMS_W_S  9
-/** HP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION2_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION2_R2_PMS_R_M  (HP_APM_REGION2_R2_PMS_R_V << HP_APM_REGION2_R2_PMS_R_S)
-#define HP_APM_REGION2_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION2_R2_PMS_R_S  10
-/** HP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region2 configuration
- */
-#define HP_APM_REGION2_LOCK    (BIT(11))
-#define HP_APM_REGION2_LOCK_M  (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S)
-#define HP_APM_REGION2_LOCK_V  0x00000001U
-#define HP_APM_REGION2_LOCK_S  11
-
-/** HP_APM_REGION3_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28)
-/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region3
- */
-#define HP_APM_REGION3_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_START_M  (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S)
-#define HP_APM_REGION3_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_START_S  0
-
-/** HP_APM_REGION3_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c)
-/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region3
- */
-#define HP_APM_REGION3_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_END_M  (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S)
-#define HP_APM_REGION3_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION3_ADDR_END_S  0
-
-/** HP_APM_REGION3_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION3_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x30)
-/** HP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION3_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION3_R0_PMS_X_M  (HP_APM_REGION3_R0_PMS_X_V << HP_APM_REGION3_R0_PMS_X_S)
-#define HP_APM_REGION3_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION3_R0_PMS_X_S  0
-/** HP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION3_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION3_R0_PMS_W_M  (HP_APM_REGION3_R0_PMS_W_V << HP_APM_REGION3_R0_PMS_W_S)
-#define HP_APM_REGION3_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION3_R0_PMS_W_S  1
-/** HP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION3_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION3_R0_PMS_R_M  (HP_APM_REGION3_R0_PMS_R_V << HP_APM_REGION3_R0_PMS_R_S)
-#define HP_APM_REGION3_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION3_R0_PMS_R_S  2
-/** HP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION3_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION3_R1_PMS_X_M  (HP_APM_REGION3_R1_PMS_X_V << HP_APM_REGION3_R1_PMS_X_S)
-#define HP_APM_REGION3_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION3_R1_PMS_X_S  4
-/** HP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION3_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION3_R1_PMS_W_M  (HP_APM_REGION3_R1_PMS_W_V << HP_APM_REGION3_R1_PMS_W_S)
-#define HP_APM_REGION3_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION3_R1_PMS_W_S  5
-/** HP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION3_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION3_R1_PMS_R_M  (HP_APM_REGION3_R1_PMS_R_V << HP_APM_REGION3_R1_PMS_R_S)
-#define HP_APM_REGION3_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION3_R1_PMS_R_S  6
-/** HP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION3_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION3_R2_PMS_X_M  (HP_APM_REGION3_R2_PMS_X_V << HP_APM_REGION3_R2_PMS_X_S)
-#define HP_APM_REGION3_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION3_R2_PMS_X_S  8
-/** HP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION3_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION3_R2_PMS_W_M  (HP_APM_REGION3_R2_PMS_W_V << HP_APM_REGION3_R2_PMS_W_S)
-#define HP_APM_REGION3_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION3_R2_PMS_W_S  9
-/** HP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION3_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION3_R2_PMS_R_M  (HP_APM_REGION3_R2_PMS_R_V << HP_APM_REGION3_R2_PMS_R_S)
-#define HP_APM_REGION3_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION3_R2_PMS_R_S  10
-/** HP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region3 configuration
- */
-#define HP_APM_REGION3_LOCK    (BIT(11))
-#define HP_APM_REGION3_LOCK_M  (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S)
-#define HP_APM_REGION3_LOCK_V  0x00000001U
-#define HP_APM_REGION3_LOCK_S  11
-
-/** HP_APM_REGION4_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34)
-/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region4
- */
-#define HP_APM_REGION4_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_START_M  (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S)
-#define HP_APM_REGION4_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_START_S  0
-
-/** HP_APM_REGION4_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38)
-/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region4
- */
-#define HP_APM_REGION4_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_END_M  (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S)
-#define HP_APM_REGION4_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION4_ADDR_END_S  0
-
-/** HP_APM_REGION4_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION4_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c)
-/** HP_APM_REGION4_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION4_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION4_R0_PMS_X_M  (HP_APM_REGION4_R0_PMS_X_V << HP_APM_REGION4_R0_PMS_X_S)
-#define HP_APM_REGION4_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION4_R0_PMS_X_S  0
-/** HP_APM_REGION4_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION4_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION4_R0_PMS_W_M  (HP_APM_REGION4_R0_PMS_W_V << HP_APM_REGION4_R0_PMS_W_S)
-#define HP_APM_REGION4_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION4_R0_PMS_W_S  1
-/** HP_APM_REGION4_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION4_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION4_R0_PMS_R_M  (HP_APM_REGION4_R0_PMS_R_V << HP_APM_REGION4_R0_PMS_R_S)
-#define HP_APM_REGION4_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION4_R0_PMS_R_S  2
-/** HP_APM_REGION4_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION4_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION4_R1_PMS_X_M  (HP_APM_REGION4_R1_PMS_X_V << HP_APM_REGION4_R1_PMS_X_S)
-#define HP_APM_REGION4_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION4_R1_PMS_X_S  4
-/** HP_APM_REGION4_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION4_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION4_R1_PMS_W_M  (HP_APM_REGION4_R1_PMS_W_V << HP_APM_REGION4_R1_PMS_W_S)
-#define HP_APM_REGION4_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION4_R1_PMS_W_S  5
-/** HP_APM_REGION4_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION4_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION4_R1_PMS_R_M  (HP_APM_REGION4_R1_PMS_R_V << HP_APM_REGION4_R1_PMS_R_S)
-#define HP_APM_REGION4_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION4_R1_PMS_R_S  6
-/** HP_APM_REGION4_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION4_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION4_R2_PMS_X_M  (HP_APM_REGION4_R2_PMS_X_V << HP_APM_REGION4_R2_PMS_X_S)
-#define HP_APM_REGION4_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION4_R2_PMS_X_S  8
-/** HP_APM_REGION4_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION4_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION4_R2_PMS_W_M  (HP_APM_REGION4_R2_PMS_W_V << HP_APM_REGION4_R2_PMS_W_S)
-#define HP_APM_REGION4_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION4_R2_PMS_W_S  9
-/** HP_APM_REGION4_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION4_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION4_R2_PMS_R_M  (HP_APM_REGION4_R2_PMS_R_V << HP_APM_REGION4_R2_PMS_R_S)
-#define HP_APM_REGION4_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION4_R2_PMS_R_S  10
-/** HP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region4 configuration
- */
-#define HP_APM_REGION4_LOCK    (BIT(11))
-#define HP_APM_REGION4_LOCK_M  (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S)
-#define HP_APM_REGION4_LOCK_V  0x00000001U
-#define HP_APM_REGION4_LOCK_S  11
-
-/** HP_APM_REGION5_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40)
-/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region5
- */
-#define HP_APM_REGION5_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_START_M  (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S)
-#define HP_APM_REGION5_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_START_S  0
-
-/** HP_APM_REGION5_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44)
-/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region5
- */
-#define HP_APM_REGION5_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_END_M  (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S)
-#define HP_APM_REGION5_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION5_ADDR_END_S  0
-
-/** HP_APM_REGION5_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION5_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x48)
-/** HP_APM_REGION5_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION5_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION5_R0_PMS_X_M  (HP_APM_REGION5_R0_PMS_X_V << HP_APM_REGION5_R0_PMS_X_S)
-#define HP_APM_REGION5_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION5_R0_PMS_X_S  0
-/** HP_APM_REGION5_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION5_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION5_R0_PMS_W_M  (HP_APM_REGION5_R0_PMS_W_V << HP_APM_REGION5_R0_PMS_W_S)
-#define HP_APM_REGION5_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION5_R0_PMS_W_S  1
-/** HP_APM_REGION5_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION5_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION5_R0_PMS_R_M  (HP_APM_REGION5_R0_PMS_R_V << HP_APM_REGION5_R0_PMS_R_S)
-#define HP_APM_REGION5_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION5_R0_PMS_R_S  2
-/** HP_APM_REGION5_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION5_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION5_R1_PMS_X_M  (HP_APM_REGION5_R1_PMS_X_V << HP_APM_REGION5_R1_PMS_X_S)
-#define HP_APM_REGION5_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION5_R1_PMS_X_S  4
-/** HP_APM_REGION5_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION5_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION5_R1_PMS_W_M  (HP_APM_REGION5_R1_PMS_W_V << HP_APM_REGION5_R1_PMS_W_S)
-#define HP_APM_REGION5_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION5_R1_PMS_W_S  5
-/** HP_APM_REGION5_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION5_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION5_R1_PMS_R_M  (HP_APM_REGION5_R1_PMS_R_V << HP_APM_REGION5_R1_PMS_R_S)
-#define HP_APM_REGION5_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION5_R1_PMS_R_S  6
-/** HP_APM_REGION5_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION5_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION5_R2_PMS_X_M  (HP_APM_REGION5_R2_PMS_X_V << HP_APM_REGION5_R2_PMS_X_S)
-#define HP_APM_REGION5_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION5_R2_PMS_X_S  8
-/** HP_APM_REGION5_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION5_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION5_R2_PMS_W_M  (HP_APM_REGION5_R2_PMS_W_V << HP_APM_REGION5_R2_PMS_W_S)
-#define HP_APM_REGION5_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION5_R2_PMS_W_S  9
-/** HP_APM_REGION5_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION5_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION5_R2_PMS_R_M  (HP_APM_REGION5_R2_PMS_R_V << HP_APM_REGION5_R2_PMS_R_S)
-#define HP_APM_REGION5_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION5_R2_PMS_R_S  10
-/** HP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region5 configuration
- */
-#define HP_APM_REGION5_LOCK    (BIT(11))
-#define HP_APM_REGION5_LOCK_M  (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S)
-#define HP_APM_REGION5_LOCK_V  0x00000001U
-#define HP_APM_REGION5_LOCK_S  11
-
-/** HP_APM_REGION6_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c)
-/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region6
- */
-#define HP_APM_REGION6_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_START_M  (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S)
-#define HP_APM_REGION6_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_START_S  0
-
-/** HP_APM_REGION6_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50)
-/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region6
- */
-#define HP_APM_REGION6_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_END_M  (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S)
-#define HP_APM_REGION6_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION6_ADDR_END_S  0
-
-/** HP_APM_REGION6_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION6_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x54)
-/** HP_APM_REGION6_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION6_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION6_R0_PMS_X_M  (HP_APM_REGION6_R0_PMS_X_V << HP_APM_REGION6_R0_PMS_X_S)
-#define HP_APM_REGION6_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION6_R0_PMS_X_S  0
-/** HP_APM_REGION6_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION6_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION6_R0_PMS_W_M  (HP_APM_REGION6_R0_PMS_W_V << HP_APM_REGION6_R0_PMS_W_S)
-#define HP_APM_REGION6_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION6_R0_PMS_W_S  1
-/** HP_APM_REGION6_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION6_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION6_R0_PMS_R_M  (HP_APM_REGION6_R0_PMS_R_V << HP_APM_REGION6_R0_PMS_R_S)
-#define HP_APM_REGION6_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION6_R0_PMS_R_S  2
-/** HP_APM_REGION6_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION6_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION6_R1_PMS_X_M  (HP_APM_REGION6_R1_PMS_X_V << HP_APM_REGION6_R1_PMS_X_S)
-#define HP_APM_REGION6_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION6_R1_PMS_X_S  4
-/** HP_APM_REGION6_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION6_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION6_R1_PMS_W_M  (HP_APM_REGION6_R1_PMS_W_V << HP_APM_REGION6_R1_PMS_W_S)
-#define HP_APM_REGION6_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION6_R1_PMS_W_S  5
-/** HP_APM_REGION6_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION6_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION6_R1_PMS_R_M  (HP_APM_REGION6_R1_PMS_R_V << HP_APM_REGION6_R1_PMS_R_S)
-#define HP_APM_REGION6_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION6_R1_PMS_R_S  6
-/** HP_APM_REGION6_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION6_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION6_R2_PMS_X_M  (HP_APM_REGION6_R2_PMS_X_V << HP_APM_REGION6_R2_PMS_X_S)
-#define HP_APM_REGION6_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION6_R2_PMS_X_S  8
-/** HP_APM_REGION6_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION6_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION6_R2_PMS_W_M  (HP_APM_REGION6_R2_PMS_W_V << HP_APM_REGION6_R2_PMS_W_S)
-#define HP_APM_REGION6_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION6_R2_PMS_W_S  9
-/** HP_APM_REGION6_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION6_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION6_R2_PMS_R_M  (HP_APM_REGION6_R2_PMS_R_V << HP_APM_REGION6_R2_PMS_R_S)
-#define HP_APM_REGION6_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION6_R2_PMS_R_S  10
-/** HP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region6 configuration
- */
-#define HP_APM_REGION6_LOCK    (BIT(11))
-#define HP_APM_REGION6_LOCK_M  (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S)
-#define HP_APM_REGION6_LOCK_V  0x00000001U
-#define HP_APM_REGION6_LOCK_S  11
-
-/** HP_APM_REGION7_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58)
-/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region7
- */
-#define HP_APM_REGION7_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_START_M  (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S)
-#define HP_APM_REGION7_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_START_S  0
-
-/** HP_APM_REGION7_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c)
-/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region7
- */
-#define HP_APM_REGION7_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_END_M  (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S)
-#define HP_APM_REGION7_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION7_ADDR_END_S  0
-
-/** HP_APM_REGION7_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION7_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x60)
-/** HP_APM_REGION7_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION7_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION7_R0_PMS_X_M  (HP_APM_REGION7_R0_PMS_X_V << HP_APM_REGION7_R0_PMS_X_S)
-#define HP_APM_REGION7_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION7_R0_PMS_X_S  0
-/** HP_APM_REGION7_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION7_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION7_R0_PMS_W_M  (HP_APM_REGION7_R0_PMS_W_V << HP_APM_REGION7_R0_PMS_W_S)
-#define HP_APM_REGION7_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION7_R0_PMS_W_S  1
-/** HP_APM_REGION7_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION7_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION7_R0_PMS_R_M  (HP_APM_REGION7_R0_PMS_R_V << HP_APM_REGION7_R0_PMS_R_S)
-#define HP_APM_REGION7_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION7_R0_PMS_R_S  2
-/** HP_APM_REGION7_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION7_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION7_R1_PMS_X_M  (HP_APM_REGION7_R1_PMS_X_V << HP_APM_REGION7_R1_PMS_X_S)
-#define HP_APM_REGION7_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION7_R1_PMS_X_S  4
-/** HP_APM_REGION7_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION7_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION7_R1_PMS_W_M  (HP_APM_REGION7_R1_PMS_W_V << HP_APM_REGION7_R1_PMS_W_S)
-#define HP_APM_REGION7_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION7_R1_PMS_W_S  5
-/** HP_APM_REGION7_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION7_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION7_R1_PMS_R_M  (HP_APM_REGION7_R1_PMS_R_V << HP_APM_REGION7_R1_PMS_R_S)
-#define HP_APM_REGION7_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION7_R1_PMS_R_S  6
-/** HP_APM_REGION7_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION7_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION7_R2_PMS_X_M  (HP_APM_REGION7_R2_PMS_X_V << HP_APM_REGION7_R2_PMS_X_S)
-#define HP_APM_REGION7_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION7_R2_PMS_X_S  8
-/** HP_APM_REGION7_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION7_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION7_R2_PMS_W_M  (HP_APM_REGION7_R2_PMS_W_V << HP_APM_REGION7_R2_PMS_W_S)
-#define HP_APM_REGION7_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION7_R2_PMS_W_S  9
-/** HP_APM_REGION7_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION7_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION7_R2_PMS_R_M  (HP_APM_REGION7_R2_PMS_R_V << HP_APM_REGION7_R2_PMS_R_S)
-#define HP_APM_REGION7_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION7_R2_PMS_R_S  10
-/** HP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region7 configuration
- */
-#define HP_APM_REGION7_LOCK    (BIT(11))
-#define HP_APM_REGION7_LOCK_M  (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S)
-#define HP_APM_REGION7_LOCK_V  0x00000001U
-#define HP_APM_REGION7_LOCK_S  11
-
-/** HP_APM_REGION8_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64)
-/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region8
- */
-#define HP_APM_REGION8_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_START_M  (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S)
-#define HP_APM_REGION8_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_START_S  0
-
-/** HP_APM_REGION8_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68)
-/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region8
- */
-#define HP_APM_REGION8_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_END_M  (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S)
-#define HP_APM_REGION8_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION8_ADDR_END_S  0
-
-/** HP_APM_REGION8_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION8_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c)
-/** HP_APM_REGION8_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION8_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION8_R0_PMS_X_M  (HP_APM_REGION8_R0_PMS_X_V << HP_APM_REGION8_R0_PMS_X_S)
-#define HP_APM_REGION8_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION8_R0_PMS_X_S  0
-/** HP_APM_REGION8_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION8_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION8_R0_PMS_W_M  (HP_APM_REGION8_R0_PMS_W_V << HP_APM_REGION8_R0_PMS_W_S)
-#define HP_APM_REGION8_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION8_R0_PMS_W_S  1
-/** HP_APM_REGION8_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION8_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION8_R0_PMS_R_M  (HP_APM_REGION8_R0_PMS_R_V << HP_APM_REGION8_R0_PMS_R_S)
-#define HP_APM_REGION8_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION8_R0_PMS_R_S  2
-/** HP_APM_REGION8_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION8_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION8_R1_PMS_X_M  (HP_APM_REGION8_R1_PMS_X_V << HP_APM_REGION8_R1_PMS_X_S)
-#define HP_APM_REGION8_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION8_R1_PMS_X_S  4
-/** HP_APM_REGION8_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION8_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION8_R1_PMS_W_M  (HP_APM_REGION8_R1_PMS_W_V << HP_APM_REGION8_R1_PMS_W_S)
-#define HP_APM_REGION8_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION8_R1_PMS_W_S  5
-/** HP_APM_REGION8_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION8_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION8_R1_PMS_R_M  (HP_APM_REGION8_R1_PMS_R_V << HP_APM_REGION8_R1_PMS_R_S)
-#define HP_APM_REGION8_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION8_R1_PMS_R_S  6
-/** HP_APM_REGION8_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION8_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION8_R2_PMS_X_M  (HP_APM_REGION8_R2_PMS_X_V << HP_APM_REGION8_R2_PMS_X_S)
-#define HP_APM_REGION8_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION8_R2_PMS_X_S  8
-/** HP_APM_REGION8_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION8_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION8_R2_PMS_W_M  (HP_APM_REGION8_R2_PMS_W_V << HP_APM_REGION8_R2_PMS_W_S)
-#define HP_APM_REGION8_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION8_R2_PMS_W_S  9
-/** HP_APM_REGION8_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION8_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION8_R2_PMS_R_M  (HP_APM_REGION8_R2_PMS_R_V << HP_APM_REGION8_R2_PMS_R_S)
-#define HP_APM_REGION8_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION8_R2_PMS_R_S  10
-/** HP_APM_REGION8_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region8 configuration
- */
-#define HP_APM_REGION8_LOCK    (BIT(11))
-#define HP_APM_REGION8_LOCK_M  (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S)
-#define HP_APM_REGION8_LOCK_V  0x00000001U
-#define HP_APM_REGION8_LOCK_S  11
-
-/** HP_APM_REGION9_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70)
-/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region9
- */
-#define HP_APM_REGION9_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_START_M  (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S)
-#define HP_APM_REGION9_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_START_S  0
-
-/** HP_APM_REGION9_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74)
-/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region9
- */
-#define HP_APM_REGION9_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_END_M  (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S)
-#define HP_APM_REGION9_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION9_ADDR_END_S  0
-
-/** HP_APM_REGION9_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION9_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x78)
-/** HP_APM_REGION9_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION9_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION9_R0_PMS_X_M  (HP_APM_REGION9_R0_PMS_X_V << HP_APM_REGION9_R0_PMS_X_S)
-#define HP_APM_REGION9_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION9_R0_PMS_X_S  0
-/** HP_APM_REGION9_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION9_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION9_R0_PMS_W_M  (HP_APM_REGION9_R0_PMS_W_V << HP_APM_REGION9_R0_PMS_W_S)
-#define HP_APM_REGION9_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION9_R0_PMS_W_S  1
-/** HP_APM_REGION9_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION9_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION9_R0_PMS_R_M  (HP_APM_REGION9_R0_PMS_R_V << HP_APM_REGION9_R0_PMS_R_S)
-#define HP_APM_REGION9_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION9_R0_PMS_R_S  2
-/** HP_APM_REGION9_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION9_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION9_R1_PMS_X_M  (HP_APM_REGION9_R1_PMS_X_V << HP_APM_REGION9_R1_PMS_X_S)
-#define HP_APM_REGION9_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION9_R1_PMS_X_S  4
-/** HP_APM_REGION9_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION9_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION9_R1_PMS_W_M  (HP_APM_REGION9_R1_PMS_W_V << HP_APM_REGION9_R1_PMS_W_S)
-#define HP_APM_REGION9_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION9_R1_PMS_W_S  5
-/** HP_APM_REGION9_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION9_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION9_R1_PMS_R_M  (HP_APM_REGION9_R1_PMS_R_V << HP_APM_REGION9_R1_PMS_R_S)
-#define HP_APM_REGION9_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION9_R1_PMS_R_S  6
-/** HP_APM_REGION9_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION9_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION9_R2_PMS_X_M  (HP_APM_REGION9_R2_PMS_X_V << HP_APM_REGION9_R2_PMS_X_S)
-#define HP_APM_REGION9_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION9_R2_PMS_X_S  8
-/** HP_APM_REGION9_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION9_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION9_R2_PMS_W_M  (HP_APM_REGION9_R2_PMS_W_V << HP_APM_REGION9_R2_PMS_W_S)
-#define HP_APM_REGION9_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION9_R2_PMS_W_S  9
-/** HP_APM_REGION9_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION9_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION9_R2_PMS_R_M  (HP_APM_REGION9_R2_PMS_R_V << HP_APM_REGION9_R2_PMS_R_S)
-#define HP_APM_REGION9_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION9_R2_PMS_R_S  10
-/** HP_APM_REGION9_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region9 configuration
- */
-#define HP_APM_REGION9_LOCK    (BIT(11))
-#define HP_APM_REGION9_LOCK_M  (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S)
-#define HP_APM_REGION9_LOCK_V  0x00000001U
-#define HP_APM_REGION9_LOCK_S  11
-
-/** HP_APM_REGION10_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c)
-/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region10
- */
-#define HP_APM_REGION10_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_START_M  (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S)
-#define HP_APM_REGION10_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_START_S  0
-
-/** HP_APM_REGION10_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80)
-/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region10
- */
-#define HP_APM_REGION10_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_END_M  (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S)
-#define HP_APM_REGION10_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION10_ADDR_END_S  0
-
-/** HP_APM_REGION10_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION10_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x84)
-/** HP_APM_REGION10_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION10_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION10_R0_PMS_X_M  (HP_APM_REGION10_R0_PMS_X_V << HP_APM_REGION10_R0_PMS_X_S)
-#define HP_APM_REGION10_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION10_R0_PMS_X_S  0
-/** HP_APM_REGION10_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION10_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION10_R0_PMS_W_M  (HP_APM_REGION10_R0_PMS_W_V << HP_APM_REGION10_R0_PMS_W_S)
-#define HP_APM_REGION10_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION10_R0_PMS_W_S  1
-/** HP_APM_REGION10_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION10_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION10_R0_PMS_R_M  (HP_APM_REGION10_R0_PMS_R_V << HP_APM_REGION10_R0_PMS_R_S)
-#define HP_APM_REGION10_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION10_R0_PMS_R_S  2
-/** HP_APM_REGION10_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION10_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION10_R1_PMS_X_M  (HP_APM_REGION10_R1_PMS_X_V << HP_APM_REGION10_R1_PMS_X_S)
-#define HP_APM_REGION10_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION10_R1_PMS_X_S  4
-/** HP_APM_REGION10_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION10_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION10_R1_PMS_W_M  (HP_APM_REGION10_R1_PMS_W_V << HP_APM_REGION10_R1_PMS_W_S)
-#define HP_APM_REGION10_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION10_R1_PMS_W_S  5
-/** HP_APM_REGION10_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION10_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION10_R1_PMS_R_M  (HP_APM_REGION10_R1_PMS_R_V << HP_APM_REGION10_R1_PMS_R_S)
-#define HP_APM_REGION10_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION10_R1_PMS_R_S  6
-/** HP_APM_REGION10_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION10_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION10_R2_PMS_X_M  (HP_APM_REGION10_R2_PMS_X_V << HP_APM_REGION10_R2_PMS_X_S)
-#define HP_APM_REGION10_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION10_R2_PMS_X_S  8
-/** HP_APM_REGION10_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION10_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION10_R2_PMS_W_M  (HP_APM_REGION10_R2_PMS_W_V << HP_APM_REGION10_R2_PMS_W_S)
-#define HP_APM_REGION10_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION10_R2_PMS_W_S  9
-/** HP_APM_REGION10_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION10_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION10_R2_PMS_R_M  (HP_APM_REGION10_R2_PMS_R_V << HP_APM_REGION10_R2_PMS_R_S)
-#define HP_APM_REGION10_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION10_R2_PMS_R_S  10
-/** HP_APM_REGION10_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region10 configuration
- */
-#define HP_APM_REGION10_LOCK    (BIT(11))
-#define HP_APM_REGION10_LOCK_M  (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S)
-#define HP_APM_REGION10_LOCK_V  0x00000001U
-#define HP_APM_REGION10_LOCK_S  11
-
-/** HP_APM_REGION11_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88)
-/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region11
- */
-#define HP_APM_REGION11_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_START_M  (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S)
-#define HP_APM_REGION11_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_START_S  0
-
-/** HP_APM_REGION11_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c)
-/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region11
- */
-#define HP_APM_REGION11_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_END_M  (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S)
-#define HP_APM_REGION11_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION11_ADDR_END_S  0
-
-/** HP_APM_REGION11_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION11_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x90)
-/** HP_APM_REGION11_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION11_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION11_R0_PMS_X_M  (HP_APM_REGION11_R0_PMS_X_V << HP_APM_REGION11_R0_PMS_X_S)
-#define HP_APM_REGION11_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION11_R0_PMS_X_S  0
-/** HP_APM_REGION11_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION11_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION11_R0_PMS_W_M  (HP_APM_REGION11_R0_PMS_W_V << HP_APM_REGION11_R0_PMS_W_S)
-#define HP_APM_REGION11_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION11_R0_PMS_W_S  1
-/** HP_APM_REGION11_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION11_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION11_R0_PMS_R_M  (HP_APM_REGION11_R0_PMS_R_V << HP_APM_REGION11_R0_PMS_R_S)
-#define HP_APM_REGION11_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION11_R0_PMS_R_S  2
-/** HP_APM_REGION11_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION11_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION11_R1_PMS_X_M  (HP_APM_REGION11_R1_PMS_X_V << HP_APM_REGION11_R1_PMS_X_S)
-#define HP_APM_REGION11_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION11_R1_PMS_X_S  4
-/** HP_APM_REGION11_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION11_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION11_R1_PMS_W_M  (HP_APM_REGION11_R1_PMS_W_V << HP_APM_REGION11_R1_PMS_W_S)
-#define HP_APM_REGION11_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION11_R1_PMS_W_S  5
-/** HP_APM_REGION11_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION11_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION11_R1_PMS_R_M  (HP_APM_REGION11_R1_PMS_R_V << HP_APM_REGION11_R1_PMS_R_S)
-#define HP_APM_REGION11_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION11_R1_PMS_R_S  6
-/** HP_APM_REGION11_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION11_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION11_R2_PMS_X_M  (HP_APM_REGION11_R2_PMS_X_V << HP_APM_REGION11_R2_PMS_X_S)
-#define HP_APM_REGION11_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION11_R2_PMS_X_S  8
-/** HP_APM_REGION11_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION11_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION11_R2_PMS_W_M  (HP_APM_REGION11_R2_PMS_W_V << HP_APM_REGION11_R2_PMS_W_S)
-#define HP_APM_REGION11_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION11_R2_PMS_W_S  9
-/** HP_APM_REGION11_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION11_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION11_R2_PMS_R_M  (HP_APM_REGION11_R2_PMS_R_V << HP_APM_REGION11_R2_PMS_R_S)
-#define HP_APM_REGION11_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION11_R2_PMS_R_S  10
-/** HP_APM_REGION11_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region11 configuration
- */
-#define HP_APM_REGION11_LOCK    (BIT(11))
-#define HP_APM_REGION11_LOCK_M  (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S)
-#define HP_APM_REGION11_LOCK_V  0x00000001U
-#define HP_APM_REGION11_LOCK_S  11
-
-/** HP_APM_REGION12_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94)
-/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region12
- */
-#define HP_APM_REGION12_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_START_M  (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S)
-#define HP_APM_REGION12_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_START_S  0
-
-/** HP_APM_REGION12_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98)
-/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region12
- */
-#define HP_APM_REGION12_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_END_M  (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S)
-#define HP_APM_REGION12_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION12_ADDR_END_S  0
-
-/** HP_APM_REGION12_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION12_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c)
-/** HP_APM_REGION12_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION12_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION12_R0_PMS_X_M  (HP_APM_REGION12_R0_PMS_X_V << HP_APM_REGION12_R0_PMS_X_S)
-#define HP_APM_REGION12_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION12_R0_PMS_X_S  0
-/** HP_APM_REGION12_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION12_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION12_R0_PMS_W_M  (HP_APM_REGION12_R0_PMS_W_V << HP_APM_REGION12_R0_PMS_W_S)
-#define HP_APM_REGION12_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION12_R0_PMS_W_S  1
-/** HP_APM_REGION12_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION12_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION12_R0_PMS_R_M  (HP_APM_REGION12_R0_PMS_R_V << HP_APM_REGION12_R0_PMS_R_S)
-#define HP_APM_REGION12_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION12_R0_PMS_R_S  2
-/** HP_APM_REGION12_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION12_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION12_R1_PMS_X_M  (HP_APM_REGION12_R1_PMS_X_V << HP_APM_REGION12_R1_PMS_X_S)
-#define HP_APM_REGION12_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION12_R1_PMS_X_S  4
-/** HP_APM_REGION12_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION12_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION12_R1_PMS_W_M  (HP_APM_REGION12_R1_PMS_W_V << HP_APM_REGION12_R1_PMS_W_S)
-#define HP_APM_REGION12_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION12_R1_PMS_W_S  5
-/** HP_APM_REGION12_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION12_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION12_R1_PMS_R_M  (HP_APM_REGION12_R1_PMS_R_V << HP_APM_REGION12_R1_PMS_R_S)
-#define HP_APM_REGION12_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION12_R1_PMS_R_S  6
-/** HP_APM_REGION12_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION12_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION12_R2_PMS_X_M  (HP_APM_REGION12_R2_PMS_X_V << HP_APM_REGION12_R2_PMS_X_S)
-#define HP_APM_REGION12_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION12_R2_PMS_X_S  8
-/** HP_APM_REGION12_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION12_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION12_R2_PMS_W_M  (HP_APM_REGION12_R2_PMS_W_V << HP_APM_REGION12_R2_PMS_W_S)
-#define HP_APM_REGION12_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION12_R2_PMS_W_S  9
-/** HP_APM_REGION12_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION12_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION12_R2_PMS_R_M  (HP_APM_REGION12_R2_PMS_R_V << HP_APM_REGION12_R2_PMS_R_S)
-#define HP_APM_REGION12_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION12_R2_PMS_R_S  10
-/** HP_APM_REGION12_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region12 configuration
- */
-#define HP_APM_REGION12_LOCK    (BIT(11))
-#define HP_APM_REGION12_LOCK_M  (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S)
-#define HP_APM_REGION12_LOCK_V  0x00000001U
-#define HP_APM_REGION12_LOCK_S  11
-
-/** HP_APM_REGION13_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0)
-/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region13
- */
-#define HP_APM_REGION13_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_START_M  (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S)
-#define HP_APM_REGION13_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_START_S  0
-
-/** HP_APM_REGION13_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4)
-/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region13
- */
-#define HP_APM_REGION13_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_END_M  (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S)
-#define HP_APM_REGION13_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION13_ADDR_END_S  0
-
-/** HP_APM_REGION13_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION13_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8)
-/** HP_APM_REGION13_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION13_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION13_R0_PMS_X_M  (HP_APM_REGION13_R0_PMS_X_V << HP_APM_REGION13_R0_PMS_X_S)
-#define HP_APM_REGION13_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION13_R0_PMS_X_S  0
-/** HP_APM_REGION13_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION13_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION13_R0_PMS_W_M  (HP_APM_REGION13_R0_PMS_W_V << HP_APM_REGION13_R0_PMS_W_S)
-#define HP_APM_REGION13_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION13_R0_PMS_W_S  1
-/** HP_APM_REGION13_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION13_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION13_R0_PMS_R_M  (HP_APM_REGION13_R0_PMS_R_V << HP_APM_REGION13_R0_PMS_R_S)
-#define HP_APM_REGION13_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION13_R0_PMS_R_S  2
-/** HP_APM_REGION13_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION13_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION13_R1_PMS_X_M  (HP_APM_REGION13_R1_PMS_X_V << HP_APM_REGION13_R1_PMS_X_S)
-#define HP_APM_REGION13_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION13_R1_PMS_X_S  4
-/** HP_APM_REGION13_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION13_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION13_R1_PMS_W_M  (HP_APM_REGION13_R1_PMS_W_V << HP_APM_REGION13_R1_PMS_W_S)
-#define HP_APM_REGION13_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION13_R1_PMS_W_S  5
-/** HP_APM_REGION13_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION13_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION13_R1_PMS_R_M  (HP_APM_REGION13_R1_PMS_R_V << HP_APM_REGION13_R1_PMS_R_S)
-#define HP_APM_REGION13_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION13_R1_PMS_R_S  6
-/** HP_APM_REGION13_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION13_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION13_R2_PMS_X_M  (HP_APM_REGION13_R2_PMS_X_V << HP_APM_REGION13_R2_PMS_X_S)
-#define HP_APM_REGION13_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION13_R2_PMS_X_S  8
-/** HP_APM_REGION13_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION13_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION13_R2_PMS_W_M  (HP_APM_REGION13_R2_PMS_W_V << HP_APM_REGION13_R2_PMS_W_S)
-#define HP_APM_REGION13_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION13_R2_PMS_W_S  9
-/** HP_APM_REGION13_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION13_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION13_R2_PMS_R_M  (HP_APM_REGION13_R2_PMS_R_V << HP_APM_REGION13_R2_PMS_R_S)
-#define HP_APM_REGION13_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION13_R2_PMS_R_S  10
-/** HP_APM_REGION13_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region13 configuration
- */
-#define HP_APM_REGION13_LOCK    (BIT(11))
-#define HP_APM_REGION13_LOCK_M  (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S)
-#define HP_APM_REGION13_LOCK_V  0x00000001U
-#define HP_APM_REGION13_LOCK_S  11
-
-/** HP_APM_REGION14_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac)
-/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region14
- */
-#define HP_APM_REGION14_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_START_M  (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S)
-#define HP_APM_REGION14_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_START_S  0
-
-/** HP_APM_REGION14_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0)
-/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region14
- */
-#define HP_APM_REGION14_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_END_M  (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S)
-#define HP_APM_REGION14_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION14_ADDR_END_S  0
-
-/** HP_APM_REGION14_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION14_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4)
-/** HP_APM_REGION14_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION14_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION14_R0_PMS_X_M  (HP_APM_REGION14_R0_PMS_X_V << HP_APM_REGION14_R0_PMS_X_S)
-#define HP_APM_REGION14_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION14_R0_PMS_X_S  0
-/** HP_APM_REGION14_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION14_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION14_R0_PMS_W_M  (HP_APM_REGION14_R0_PMS_W_V << HP_APM_REGION14_R0_PMS_W_S)
-#define HP_APM_REGION14_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION14_R0_PMS_W_S  1
-/** HP_APM_REGION14_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION14_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION14_R0_PMS_R_M  (HP_APM_REGION14_R0_PMS_R_V << HP_APM_REGION14_R0_PMS_R_S)
-#define HP_APM_REGION14_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION14_R0_PMS_R_S  2
-/** HP_APM_REGION14_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION14_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION14_R1_PMS_X_M  (HP_APM_REGION14_R1_PMS_X_V << HP_APM_REGION14_R1_PMS_X_S)
-#define HP_APM_REGION14_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION14_R1_PMS_X_S  4
-/** HP_APM_REGION14_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION14_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION14_R1_PMS_W_M  (HP_APM_REGION14_R1_PMS_W_V << HP_APM_REGION14_R1_PMS_W_S)
-#define HP_APM_REGION14_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION14_R1_PMS_W_S  5
-/** HP_APM_REGION14_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION14_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION14_R1_PMS_R_M  (HP_APM_REGION14_R1_PMS_R_V << HP_APM_REGION14_R1_PMS_R_S)
-#define HP_APM_REGION14_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION14_R1_PMS_R_S  6
-/** HP_APM_REGION14_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION14_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION14_R2_PMS_X_M  (HP_APM_REGION14_R2_PMS_X_V << HP_APM_REGION14_R2_PMS_X_S)
-#define HP_APM_REGION14_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION14_R2_PMS_X_S  8
-/** HP_APM_REGION14_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION14_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION14_R2_PMS_W_M  (HP_APM_REGION14_R2_PMS_W_V << HP_APM_REGION14_R2_PMS_W_S)
-#define HP_APM_REGION14_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION14_R2_PMS_W_S  9
-/** HP_APM_REGION14_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION14_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION14_R2_PMS_R_M  (HP_APM_REGION14_R2_PMS_R_V << HP_APM_REGION14_R2_PMS_R_S)
-#define HP_APM_REGION14_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION14_R2_PMS_R_S  10
-/** HP_APM_REGION14_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region14 configuration
- */
-#define HP_APM_REGION14_LOCK    (BIT(11))
-#define HP_APM_REGION14_LOCK_M  (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S)
-#define HP_APM_REGION14_LOCK_V  0x00000001U
-#define HP_APM_REGION14_LOCK_S  11
-
-/** HP_APM_REGION15_ADDR_START_REG register
- *  Region address register
- */
-#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8)
-/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region15
- */
-#define HP_APM_REGION15_ADDR_START    0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_START_M  (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S)
-#define HP_APM_REGION15_ADDR_START_V  0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_START_S  0
-
-/** HP_APM_REGION15_ADDR_END_REG register
- *  Region address register
- */
-#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc)
-/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region15
- */
-#define HP_APM_REGION15_ADDR_END    0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_END_M  (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S)
-#define HP_APM_REGION15_ADDR_END_V  0xFFFFFFFFU
-#define HP_APM_REGION15_ADDR_END_S  0
-
-/** HP_APM_REGION15_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define HP_APM_REGION15_PMS_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0)
-/** HP_APM_REGION15_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define HP_APM_REGION15_R0_PMS_X    (BIT(0))
-#define HP_APM_REGION15_R0_PMS_X_M  (HP_APM_REGION15_R0_PMS_X_V << HP_APM_REGION15_R0_PMS_X_S)
-#define HP_APM_REGION15_R0_PMS_X_V  0x00000001U
-#define HP_APM_REGION15_R0_PMS_X_S  0
-/** HP_APM_REGION15_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define HP_APM_REGION15_R0_PMS_W    (BIT(1))
-#define HP_APM_REGION15_R0_PMS_W_M  (HP_APM_REGION15_R0_PMS_W_V << HP_APM_REGION15_R0_PMS_W_S)
-#define HP_APM_REGION15_R0_PMS_W_V  0x00000001U
-#define HP_APM_REGION15_R0_PMS_W_S  1
-/** HP_APM_REGION15_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define HP_APM_REGION15_R0_PMS_R    (BIT(2))
-#define HP_APM_REGION15_R0_PMS_R_M  (HP_APM_REGION15_R0_PMS_R_V << HP_APM_REGION15_R0_PMS_R_S)
-#define HP_APM_REGION15_R0_PMS_R_V  0x00000001U
-#define HP_APM_REGION15_R0_PMS_R_S  2
-/** HP_APM_REGION15_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define HP_APM_REGION15_R1_PMS_X    (BIT(4))
-#define HP_APM_REGION15_R1_PMS_X_M  (HP_APM_REGION15_R1_PMS_X_V << HP_APM_REGION15_R1_PMS_X_S)
-#define HP_APM_REGION15_R1_PMS_X_V  0x00000001U
-#define HP_APM_REGION15_R1_PMS_X_S  4
-/** HP_APM_REGION15_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define HP_APM_REGION15_R1_PMS_W    (BIT(5))
-#define HP_APM_REGION15_R1_PMS_W_M  (HP_APM_REGION15_R1_PMS_W_V << HP_APM_REGION15_R1_PMS_W_S)
-#define HP_APM_REGION15_R1_PMS_W_V  0x00000001U
-#define HP_APM_REGION15_R1_PMS_W_S  5
-/** HP_APM_REGION15_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define HP_APM_REGION15_R1_PMS_R    (BIT(6))
-#define HP_APM_REGION15_R1_PMS_R_M  (HP_APM_REGION15_R1_PMS_R_V << HP_APM_REGION15_R1_PMS_R_S)
-#define HP_APM_REGION15_R1_PMS_R_V  0x00000001U
-#define HP_APM_REGION15_R1_PMS_R_S  6
-/** HP_APM_REGION15_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define HP_APM_REGION15_R2_PMS_X    (BIT(8))
-#define HP_APM_REGION15_R2_PMS_X_M  (HP_APM_REGION15_R2_PMS_X_V << HP_APM_REGION15_R2_PMS_X_S)
-#define HP_APM_REGION15_R2_PMS_X_V  0x00000001U
-#define HP_APM_REGION15_R2_PMS_X_S  8
-/** HP_APM_REGION15_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define HP_APM_REGION15_R2_PMS_W    (BIT(9))
-#define HP_APM_REGION15_R2_PMS_W_M  (HP_APM_REGION15_R2_PMS_W_V << HP_APM_REGION15_R2_PMS_W_S)
-#define HP_APM_REGION15_R2_PMS_W_V  0x00000001U
-#define HP_APM_REGION15_R2_PMS_W_S  9
-/** HP_APM_REGION15_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define HP_APM_REGION15_R2_PMS_R    (BIT(10))
-#define HP_APM_REGION15_R2_PMS_R_M  (HP_APM_REGION15_R2_PMS_R_V << HP_APM_REGION15_R2_PMS_R_S)
-#define HP_APM_REGION15_R2_PMS_R_V  0x00000001U
-#define HP_APM_REGION15_R2_PMS_R_S  10
-/** HP_APM_REGION15_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region15 configuration
- */
-#define HP_APM_REGION15_LOCK    (BIT(11))
-#define HP_APM_REGION15_LOCK_M  (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S)
-#define HP_APM_REGION15_LOCK_V  0x00000001U
-#define HP_APM_REGION15_LOCK_S  11
-
-/** HP_APM_FUNC_CTRL_REG register
- *  PMS function control register
- */
-#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4)
-/** HP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
- *  PMS M0 function enable
- */
-#define HP_APM_M0_PMS_FUNC_EN    (BIT(0))
-#define HP_APM_M0_PMS_FUNC_EN_M  (HP_APM_M0_PMS_FUNC_EN_V << HP_APM_M0_PMS_FUNC_EN_S)
-#define HP_APM_M0_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M0_PMS_FUNC_EN_S  0
-/** HP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
- *  PMS M1 function enable
- */
-#define HP_APM_M1_PMS_FUNC_EN    (BIT(1))
-#define HP_APM_M1_PMS_FUNC_EN_M  (HP_APM_M1_PMS_FUNC_EN_V << HP_APM_M1_PMS_FUNC_EN_S)
-#define HP_APM_M1_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M1_PMS_FUNC_EN_S  1
-/** HP_APM_M2_PMS_FUNC_EN : R/W; bitpos: [2]; default: 1;
- *  PMS M2 function enable
- */
-#define HP_APM_M2_PMS_FUNC_EN    (BIT(2))
-#define HP_APM_M2_PMS_FUNC_EN_M  (HP_APM_M2_PMS_FUNC_EN_V << HP_APM_M2_PMS_FUNC_EN_S)
-#define HP_APM_M2_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M2_PMS_FUNC_EN_S  2
-/** HP_APM_M3_PMS_FUNC_EN : R/W; bitpos: [3]; default: 1;
- *  PMS M3 function enable
- */
-#define HP_APM_M3_PMS_FUNC_EN    (BIT(3))
-#define HP_APM_M3_PMS_FUNC_EN_M  (HP_APM_M3_PMS_FUNC_EN_V << HP_APM_M3_PMS_FUNC_EN_S)
-#define HP_APM_M3_PMS_FUNC_EN_V  0x00000001U
-#define HP_APM_M3_PMS_FUNC_EN_S  3
-
-/** HP_APM_M0_STATUS_REG register
- *  M0 status register
- */
-#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8)
-/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M0_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M0_EXCEPTION_STATUS_M  (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S)
-#define HP_APM_M0_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M0_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M0_STATUS_CLR_REG register
- *  M0 status clear register
- */
-#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc)
-/** HP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M0_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M0_REGION_STATUS_CLR_M  (HP_APM_M0_REGION_STATUS_CLR_V << HP_APM_M0_REGION_STATUS_CLR_S)
-#define HP_APM_M0_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M0_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M0_EXCEPTION_INFO0_REG register
- *  M0 exception_info0 register
- */
-#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0)
-/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M0_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M0_EXCEPTION_REGION_M  (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S)
-#define HP_APM_M0_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M0_EXCEPTION_REGION_S  0
-/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M0_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M0_EXCEPTION_MODE_M  (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S)
-#define HP_APM_M0_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M0_EXCEPTION_MODE_S  16
-/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M0_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M0_EXCEPTION_ID_M  (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S)
-#define HP_APM_M0_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M0_EXCEPTION_ID_S  18
-
-/** HP_APM_M0_EXCEPTION_INFO1_REG register
- *  M0 exception_info1 register
- */
-#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4)
-/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M0_EXCEPTION_ADDR_M  (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S)
-#define HP_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M0_EXCEPTION_ADDR_S  0
-
-/** HP_APM_M1_STATUS_REG register
- *  M1 status register
- */
-#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8)
-/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M1_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M1_EXCEPTION_STATUS_M  (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S)
-#define HP_APM_M1_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M1_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M1_STATUS_CLR_REG register
- *  M1 status clear register
- */
-#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc)
-/** HP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M1_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M1_REGION_STATUS_CLR_M  (HP_APM_M1_REGION_STATUS_CLR_V << HP_APM_M1_REGION_STATUS_CLR_S)
-#define HP_APM_M1_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M1_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M1_EXCEPTION_INFO0_REG register
- *  M1 exception_info0 register
- */
-#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0)
-/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M1_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M1_EXCEPTION_REGION_M  (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S)
-#define HP_APM_M1_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M1_EXCEPTION_REGION_S  0
-/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M1_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M1_EXCEPTION_MODE_M  (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S)
-#define HP_APM_M1_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M1_EXCEPTION_MODE_S  16
-/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M1_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M1_EXCEPTION_ID_M  (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S)
-#define HP_APM_M1_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M1_EXCEPTION_ID_S  18
-
-/** HP_APM_M1_EXCEPTION_INFO1_REG register
- *  M1 exception_info1 register
- */
-#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4)
-/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M1_EXCEPTION_ADDR_M  (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S)
-#define HP_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M1_EXCEPTION_ADDR_S  0
-
-/** HP_APM_M2_STATUS_REG register
- *  M2 status register
- */
-#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8)
-/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M2_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M2_EXCEPTION_STATUS_M  (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S)
-#define HP_APM_M2_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M2_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M2_STATUS_CLR_REG register
- *  M2 status clear register
- */
-#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec)
-/** HP_APM_M2_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M2_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M2_REGION_STATUS_CLR_M  (HP_APM_M2_REGION_STATUS_CLR_V << HP_APM_M2_REGION_STATUS_CLR_S)
-#define HP_APM_M2_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M2_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M2_EXCEPTION_INFO0_REG register
- *  M2 exception_info0 register
- */
-#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0)
-/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M2_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M2_EXCEPTION_REGION_M  (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S)
-#define HP_APM_M2_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M2_EXCEPTION_REGION_S  0
-/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M2_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M2_EXCEPTION_MODE_M  (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S)
-#define HP_APM_M2_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M2_EXCEPTION_MODE_S  16
-/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M2_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M2_EXCEPTION_ID_M  (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S)
-#define HP_APM_M2_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M2_EXCEPTION_ID_S  18
-
-/** HP_APM_M2_EXCEPTION_INFO1_REG register
- *  M2 exception_info1 register
- */
-#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4)
-/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M2_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M2_EXCEPTION_ADDR_M  (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S)
-#define HP_APM_M2_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M2_EXCEPTION_ADDR_S  0
-
-/** HP_APM_M3_STATUS_REG register
- *  M3 status register
- */
-#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8)
-/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define HP_APM_M3_EXCEPTION_STATUS    0x00000003U
-#define HP_APM_M3_EXCEPTION_STATUS_M  (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S)
-#define HP_APM_M3_EXCEPTION_STATUS_V  0x00000003U
-#define HP_APM_M3_EXCEPTION_STATUS_S  0
-
-/** HP_APM_M3_STATUS_CLR_REG register
- *  M3 status clear register
- */
-#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc)
-/** HP_APM_M3_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define HP_APM_M3_REGION_STATUS_CLR    (BIT(0))
-#define HP_APM_M3_REGION_STATUS_CLR_M  (HP_APM_M3_REGION_STATUS_CLR_V << HP_APM_M3_REGION_STATUS_CLR_S)
-#define HP_APM_M3_REGION_STATUS_CLR_V  0x00000001U
-#define HP_APM_M3_REGION_STATUS_CLR_S  0
-
-/** HP_APM_M3_EXCEPTION_INFO0_REG register
- *  M3 exception_info0 register
- */
-#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100)
-/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
- *  Exception region
- */
-#define HP_APM_M3_EXCEPTION_REGION    0x0000FFFFU
-#define HP_APM_M3_EXCEPTION_REGION_M  (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S)
-#define HP_APM_M3_EXCEPTION_REGION_V  0x0000FFFFU
-#define HP_APM_M3_EXCEPTION_REGION_S  0
-/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define HP_APM_M3_EXCEPTION_MODE    0x00000003U
-#define HP_APM_M3_EXCEPTION_MODE_M  (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S)
-#define HP_APM_M3_EXCEPTION_MODE_V  0x00000003U
-#define HP_APM_M3_EXCEPTION_MODE_S  16
-/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define HP_APM_M3_EXCEPTION_ID    0x0000001FU
-#define HP_APM_M3_EXCEPTION_ID_M  (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S)
-#define HP_APM_M3_EXCEPTION_ID_V  0x0000001FU
-#define HP_APM_M3_EXCEPTION_ID_S  18
-
-/** HP_APM_M3_EXCEPTION_INFO1_REG register
- *  M3 exception_info1 register
- */
-#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104)
-/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define HP_APM_M3_EXCEPTION_ADDR    0xFFFFFFFFU
-#define HP_APM_M3_EXCEPTION_ADDR_M  (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S)
-#define HP_APM_M3_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define HP_APM_M3_EXCEPTION_ADDR_S  0
-
-/** HP_APM_INT_EN_REG register
- *  APM interrupt enable register
- */
-#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108)
-/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
- *  APM M0 interrupt enable
- */
-#define HP_APM_M0_APM_INT_EN    (BIT(0))
-#define HP_APM_M0_APM_INT_EN_M  (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S)
-#define HP_APM_M0_APM_INT_EN_V  0x00000001U
-#define HP_APM_M0_APM_INT_EN_S  0
-/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
- *  APM M1 interrupt enable
- */
-#define HP_APM_M1_APM_INT_EN    (BIT(1))
-#define HP_APM_M1_APM_INT_EN_M  (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S)
-#define HP_APM_M1_APM_INT_EN_V  0x00000001U
-#define HP_APM_M1_APM_INT_EN_S  1
-/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0;
- *  APM M2 interrupt enable
- */
-#define HP_APM_M2_APM_INT_EN    (BIT(2))
-#define HP_APM_M2_APM_INT_EN_M  (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S)
-#define HP_APM_M2_APM_INT_EN_V  0x00000001U
-#define HP_APM_M2_APM_INT_EN_S  2
-/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0;
- *  APM M3 interrupt enable
- */
-#define HP_APM_M3_APM_INT_EN    (BIT(3))
-#define HP_APM_M3_APM_INT_EN_M  (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S)
-#define HP_APM_M3_APM_INT_EN_V  0x00000001U
-#define HP_APM_M3_APM_INT_EN_S  3
-
-/** HP_APM_CLOCK_GATE_REG register
- *  clock gating register
- */
-#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x10c)
-/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define HP_APM_CLK_EN    (BIT(0))
-#define HP_APM_CLK_EN_M  (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S)
-#define HP_APM_CLK_EN_V  0x00000001U
-#define HP_APM_CLK_EN_S  0
-
-/** HP_APM_DATE_REG register
- *  Version register
- */
-#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc)
-/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664;
- *  reg_date
- */
-#define HP_APM_DATE    0x0FFFFFFFU
-#define HP_APM_DATE_M  (HP_APM_DATE_V << HP_APM_DATE_S)
-#define HP_APM_DATE_V  0x0FFFFFFFU
-#define HP_APM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hp_apm_struct.h b/components/soc/esp32c5/beta3/include/soc/hp_apm_struct.h
deleted file mode 100644
index 04c89c8a5e..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hp_apm_struct.h
+++ /dev/null
@@ -1,1734 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Region filter enable register */
-/** Type of region_filter_en register
- *  Region filter enable register
- */
-typedef union {
-    struct {
-        /** region_filter_en : R/W; bitpos: [15:0]; default: 1;
-         *  Region filter enable
-         */
-        uint32_t region_filter_en:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} hp_apm_region_filter_en_reg_t;
-
-
-/** Group: Region address register */
-/** Type of region0_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region0
-         */
-        uint32_t region0_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region0_addr_start_reg_t;
-
-/** Type of region0_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region0
-         */
-        uint32_t region0_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region0_addr_end_reg_t;
-
-/** Type of region1_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region1
-         */
-        uint32_t region1_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region1_addr_start_reg_t;
-
-/** Type of region1_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region1
-         */
-        uint32_t region1_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region1_addr_end_reg_t;
-
-/** Type of region2_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region2
-         */
-        uint32_t region2_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region2_addr_start_reg_t;
-
-/** Type of region2_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region2
-         */
-        uint32_t region2_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region2_addr_end_reg_t;
-
-/** Type of region3_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region3
-         */
-        uint32_t region3_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region3_addr_start_reg_t;
-
-/** Type of region3_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region3
-         */
-        uint32_t region3_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region3_addr_end_reg_t;
-
-/** Type of region4_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region4_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region4
-         */
-        uint32_t region4_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region4_addr_start_reg_t;
-
-/** Type of region4_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region4_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region4
-         */
-        uint32_t region4_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region4_addr_end_reg_t;
-
-/** Type of region5_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region5_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region5
-         */
-        uint32_t region5_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region5_addr_start_reg_t;
-
-/** Type of region5_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region5_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region5
-         */
-        uint32_t region5_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region5_addr_end_reg_t;
-
-/** Type of region6_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region6_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region6
-         */
-        uint32_t region6_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region6_addr_start_reg_t;
-
-/** Type of region6_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region6_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region6
-         */
-        uint32_t region6_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region6_addr_end_reg_t;
-
-/** Type of region7_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region7_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region7
-         */
-        uint32_t region7_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region7_addr_start_reg_t;
-
-/** Type of region7_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region7_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region7
-         */
-        uint32_t region7_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region7_addr_end_reg_t;
-
-/** Type of region8_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region8_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region8
-         */
-        uint32_t region8_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region8_addr_start_reg_t;
-
-/** Type of region8_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region8_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region8
-         */
-        uint32_t region8_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region8_addr_end_reg_t;
-
-/** Type of region9_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region9_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region9
-         */
-        uint32_t region9_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region9_addr_start_reg_t;
-
-/** Type of region9_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region9_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region9
-         */
-        uint32_t region9_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region9_addr_end_reg_t;
-
-/** Type of region10_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region10_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region10
-         */
-        uint32_t region10_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region10_addr_start_reg_t;
-
-/** Type of region10_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region10_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region10
-         */
-        uint32_t region10_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region10_addr_end_reg_t;
-
-/** Type of region11_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region11_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region11
-         */
-        uint32_t region11_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region11_addr_start_reg_t;
-
-/** Type of region11_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region11_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region11
-         */
-        uint32_t region11_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region11_addr_end_reg_t;
-
-/** Type of region12_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region12_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region12
-         */
-        uint32_t region12_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region12_addr_start_reg_t;
-
-/** Type of region12_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region12_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region12
-         */
-        uint32_t region12_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region12_addr_end_reg_t;
-
-/** Type of region13_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region13_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region13
-         */
-        uint32_t region13_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region13_addr_start_reg_t;
-
-/** Type of region13_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region13_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region13
-         */
-        uint32_t region13_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region13_addr_end_reg_t;
-
-/** Type of region14_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region14_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region14
-         */
-        uint32_t region14_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region14_addr_start_reg_t;
-
-/** Type of region14_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region14_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region14
-         */
-        uint32_t region14_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region14_addr_end_reg_t;
-
-/** Type of region15_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region15_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region15
-         */
-        uint32_t region15_addr_start:32;
-    };
-    uint32_t val;
-} hp_apm_region15_addr_start_reg_t;
-
-/** Type of region15_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region15_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region15
-         */
-        uint32_t region15_addr_end:32;
-    };
-    uint32_t val;
-} hp_apm_region15_addr_end_reg_t;
-
-
-/** Group: Region access authority attribute register */
-/** Type of region0_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_x:1;
-        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_w:1;
-        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_x:1;
-        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_w:1;
-        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_x:1;
-        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_w:1;
-        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_r:1;
-        /** region0_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region0 configuration
-         */
-        uint32_t region0_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region0_pms_attr_reg_t;
-
-/** Type of region1_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_x:1;
-        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_w:1;
-        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_x:1;
-        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_w:1;
-        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_x:1;
-        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_w:1;
-        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_r:1;
-        /** region1_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region1 configuration
-         */
-        uint32_t region1_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region1_pms_attr_reg_t;
-
-/** Type of region2_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_x:1;
-        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_w:1;
-        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_x:1;
-        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_w:1;
-        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_x:1;
-        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_w:1;
-        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_r:1;
-        /** region2_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region2 configuration
-         */
-        uint32_t region2_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region2_pms_attr_reg_t;
-
-/** Type of region3_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_x:1;
-        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_w:1;
-        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_x:1;
-        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_w:1;
-        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_x:1;
-        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_w:1;
-        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_r:1;
-        /** region3_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region3 configuration
-         */
-        uint32_t region3_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region3_pms_attr_reg_t;
-
-/** Type of region4_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region4_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region4_r0_pms_x:1;
-        /** region4_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region4_r0_pms_w:1;
-        /** region4_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region4_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region4_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region4_r1_pms_x:1;
-        /** region4_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region4_r1_pms_w:1;
-        /** region4_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region4_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region4_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region4_r2_pms_x:1;
-        /** region4_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region4_r2_pms_w:1;
-        /** region4_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region4_r2_pms_r:1;
-        /** region4_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region4 configuration
-         */
-        uint32_t region4_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region4_pms_attr_reg_t;
-
-/** Type of region5_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region5_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region5_r0_pms_x:1;
-        /** region5_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region5_r0_pms_w:1;
-        /** region5_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region5_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region5_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region5_r1_pms_x:1;
-        /** region5_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region5_r1_pms_w:1;
-        /** region5_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region5_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region5_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region5_r2_pms_x:1;
-        /** region5_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region5_r2_pms_w:1;
-        /** region5_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region5_r2_pms_r:1;
-        /** region5_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region5 configuration
-         */
-        uint32_t region5_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region5_pms_attr_reg_t;
-
-/** Type of region6_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region6_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region6_r0_pms_x:1;
-        /** region6_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region6_r0_pms_w:1;
-        /** region6_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region6_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region6_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region6_r1_pms_x:1;
-        /** region6_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region6_r1_pms_w:1;
-        /** region6_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region6_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region6_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region6_r2_pms_x:1;
-        /** region6_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region6_r2_pms_w:1;
-        /** region6_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region6_r2_pms_r:1;
-        /** region6_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region6 configuration
-         */
-        uint32_t region6_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region6_pms_attr_reg_t;
-
-/** Type of region7_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region7_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region7_r0_pms_x:1;
-        /** region7_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region7_r0_pms_w:1;
-        /** region7_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region7_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region7_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region7_r1_pms_x:1;
-        /** region7_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region7_r1_pms_w:1;
-        /** region7_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region7_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region7_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region7_r2_pms_x:1;
-        /** region7_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region7_r2_pms_w:1;
-        /** region7_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region7_r2_pms_r:1;
-        /** region7_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region7 configuration
-         */
-        uint32_t region7_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region7_pms_attr_reg_t;
-
-/** Type of region8_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region8_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region8_r0_pms_x:1;
-        /** region8_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region8_r0_pms_w:1;
-        /** region8_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region8_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region8_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region8_r1_pms_x:1;
-        /** region8_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region8_r1_pms_w:1;
-        /** region8_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region8_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region8_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region8_r2_pms_x:1;
-        /** region8_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region8_r2_pms_w:1;
-        /** region8_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region8_r2_pms_r:1;
-        /** region8_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region8 configuration
-         */
-        uint32_t region8_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region8_pms_attr_reg_t;
-
-/** Type of region9_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region9_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region9_r0_pms_x:1;
-        /** region9_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region9_r0_pms_w:1;
-        /** region9_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region9_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region9_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region9_r1_pms_x:1;
-        /** region9_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region9_r1_pms_w:1;
-        /** region9_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region9_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region9_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region9_r2_pms_x:1;
-        /** region9_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region9_r2_pms_w:1;
-        /** region9_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region9_r2_pms_r:1;
-        /** region9_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region9 configuration
-         */
-        uint32_t region9_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region9_pms_attr_reg_t;
-
-/** Type of region10_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region10_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region10_r0_pms_x:1;
-        /** region10_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region10_r0_pms_w:1;
-        /** region10_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region10_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region10_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region10_r1_pms_x:1;
-        /** region10_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region10_r1_pms_w:1;
-        /** region10_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region10_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region10_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region10_r2_pms_x:1;
-        /** region10_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region10_r2_pms_w:1;
-        /** region10_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region10_r2_pms_r:1;
-        /** region10_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region10 configuration
-         */
-        uint32_t region10_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region10_pms_attr_reg_t;
-
-/** Type of region11_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region11_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region11_r0_pms_x:1;
-        /** region11_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region11_r0_pms_w:1;
-        /** region11_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region11_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region11_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region11_r1_pms_x:1;
-        /** region11_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region11_r1_pms_w:1;
-        /** region11_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region11_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region11_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region11_r2_pms_x:1;
-        /** region11_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region11_r2_pms_w:1;
-        /** region11_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region11_r2_pms_r:1;
-        /** region11_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region11 configuration
-         */
-        uint32_t region11_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region11_pms_attr_reg_t;
-
-/** Type of region12_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region12_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region12_r0_pms_x:1;
-        /** region12_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region12_r0_pms_w:1;
-        /** region12_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region12_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region12_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region12_r1_pms_x:1;
-        /** region12_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region12_r1_pms_w:1;
-        /** region12_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region12_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region12_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region12_r2_pms_x:1;
-        /** region12_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region12_r2_pms_w:1;
-        /** region12_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region12_r2_pms_r:1;
-        /** region12_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region12 configuration
-         */
-        uint32_t region12_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region12_pms_attr_reg_t;
-
-/** Type of region13_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region13_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region13_r0_pms_x:1;
-        /** region13_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region13_r0_pms_w:1;
-        /** region13_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region13_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region13_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region13_r1_pms_x:1;
-        /** region13_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region13_r1_pms_w:1;
-        /** region13_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region13_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region13_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region13_r2_pms_x:1;
-        /** region13_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region13_r2_pms_w:1;
-        /** region13_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region13_r2_pms_r:1;
-        /** region13_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region13 configuration
-         */
-        uint32_t region13_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region13_pms_attr_reg_t;
-
-/** Type of region14_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region14_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region14_r0_pms_x:1;
-        /** region14_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region14_r0_pms_w:1;
-        /** region14_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region14_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region14_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region14_r1_pms_x:1;
-        /** region14_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region14_r1_pms_w:1;
-        /** region14_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region14_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region14_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region14_r2_pms_x:1;
-        /** region14_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region14_r2_pms_w:1;
-        /** region14_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region14_r2_pms_r:1;
-        /** region14_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region14 configuration
-         */
-        uint32_t region14_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region14_pms_attr_reg_t;
-
-/** Type of region15_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region15_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region15_r0_pms_x:1;
-        /** region15_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region15_r0_pms_w:1;
-        /** region15_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region15_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region15_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region15_r1_pms_x:1;
-        /** region15_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region15_r1_pms_w:1;
-        /** region15_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region15_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region15_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region15_r2_pms_x:1;
-        /** region15_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region15_r2_pms_w:1;
-        /** region15_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region15_r2_pms_r:1;
-        /** region15_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region15 configuration
-         */
-        uint32_t region15_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} hp_apm_region15_pms_attr_reg_t;
-
-
-/** Group: PMS function control register */
-/** Type of func_ctrl register
- *  PMS function control register
- */
-typedef union {
-    struct {
-        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
-         *  PMS M0 function enable
-         */
-        uint32_t m0_pms_func_en:1;
-        /** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
-         *  PMS M1 function enable
-         */
-        uint32_t m1_pms_func_en:1;
-        /** m2_pms_func_en : R/W; bitpos: [2]; default: 1;
-         *  PMS M2 function enable
-         */
-        uint32_t m2_pms_func_en:1;
-        /** m3_pms_func_en : R/W; bitpos: [3]; default: 1;
-         *  PMS M3 function enable
-         */
-        uint32_t m3_pms_func_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_apm_func_ctrl_reg_t;
-
-
-/** Group: M0 status register */
-/** Type of m0_status register
- *  M0 status register
- */
-typedef union {
-    struct {
-        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m0_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m0_status_reg_t;
-
-
-/** Group: M0 status clear register */
-/** Type of m0_status_clr register
- *  M0 status clear register
- */
-typedef union {
-    struct {
-        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m0_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m0_status_clr_reg_t;
-
-
-/** Group: M0 exception_info0 register */
-/** Type of m0_exception_info0 register
- *  M0 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m0_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m0_exception_region:16;
-        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m0_exception_mode:2;
-        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m0_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m0_exception_info0_reg_t;
-
-
-/** Group: M0 exception_info1 register */
-/** Type of m0_exception_info1 register
- *  M0 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m0_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m0_exception_info1_reg_t;
-
-
-/** Group: M1 status register */
-/** Type of m1_status register
- *  M1 status register
- */
-typedef union {
-    struct {
-        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m1_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m1_status_reg_t;
-
-
-/** Group: M1 status clear register */
-/** Type of m1_status_clr register
- *  M1 status clear register
- */
-typedef union {
-    struct {
-        /** m1_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m1_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m1_status_clr_reg_t;
-
-
-/** Group: M1 exception_info0 register */
-/** Type of m1_exception_info0 register
- *  M1 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m1_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m1_exception_region:16;
-        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m1_exception_mode:2;
-        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m1_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m1_exception_info0_reg_t;
-
-
-/** Group: M1 exception_info1 register */
-/** Type of m1_exception_info1 register
- *  M1 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m1_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m1_exception_info1_reg_t;
-
-
-/** Group: M2 status register */
-/** Type of m2_status register
- *  M2 status register
- */
-typedef union {
-    struct {
-        /** m2_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m2_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m2_status_reg_t;
-
-
-/** Group: M2 status clear register */
-/** Type of m2_status_clr register
- *  M2 status clear register
- */
-typedef union {
-    struct {
-        /** m2_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m2_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m2_status_clr_reg_t;
-
-
-/** Group: M2 exception_info0 register */
-/** Type of m2_exception_info0 register
- *  M2 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m2_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m2_exception_region:16;
-        /** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m2_exception_mode:2;
-        /** m2_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m2_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m2_exception_info0_reg_t;
-
-
-/** Group: M2 exception_info1 register */
-/** Type of m2_exception_info1 register
- *  M2 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m2_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m2_exception_info1_reg_t;
-
-
-/** Group: M3 status register */
-/** Type of m3_status register
- *  M3 status register
- */
-typedef union {
-    struct {
-        /** m3_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m3_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_apm_m3_status_reg_t;
-
-
-/** Group: M3 status clear register */
-/** Type of m3_status_clr register
- *  M3 status clear register
- */
-typedef union {
-    struct {
-        /** m3_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m3_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_m3_status_clr_reg_t;
-
-
-/** Group: M3 exception_info0 register */
-/** Type of m3_exception_info0 register
- *  M3 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m3_exception_region : RO; bitpos: [15:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m3_exception_region:16;
-        /** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m3_exception_mode:2;
-        /** m3_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m3_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} hp_apm_m3_exception_info0_reg_t;
-
-
-/** Group: M3 exception_info1 register */
-/** Type of m3_exception_info1 register
- *  M3 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m3_exception_addr:32;
-    };
-    uint32_t val;
-} hp_apm_m3_exception_info1_reg_t;
-
-
-/** Group: APM interrupt enable register */
-/** Type of int_en register
- *  APM interrupt enable register
- */
-typedef union {
-    struct {
-        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
-         *  APM M0 interrupt enable
-         */
-        uint32_t m0_apm_int_en:1;
-        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
-         *  APM M1 interrupt enable
-         */
-        uint32_t m1_apm_int_en:1;
-        /** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
-         *  APM M2 interrupt enable
-         */
-        uint32_t m2_apm_int_en:1;
-        /** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
-         *  APM M3 interrupt enable
-         */
-        uint32_t m3_apm_int_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_apm_int_en_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_apm_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725664;
-         *  reg_date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} hp_apm_date_reg_t;
-
-
-typedef struct hp_apm_dev_t {
-    volatile hp_apm_region_filter_en_reg_t region_filter_en;
-    volatile hp_apm_region0_addr_start_reg_t region0_addr_start;
-    volatile hp_apm_region0_addr_end_reg_t region0_addr_end;
-    volatile hp_apm_region0_pms_attr_reg_t region0_pms_attr;
-    volatile hp_apm_region1_addr_start_reg_t region1_addr_start;
-    volatile hp_apm_region1_addr_end_reg_t region1_addr_end;
-    volatile hp_apm_region1_pms_attr_reg_t region1_pms_attr;
-    volatile hp_apm_region2_addr_start_reg_t region2_addr_start;
-    volatile hp_apm_region2_addr_end_reg_t region2_addr_end;
-    volatile hp_apm_region2_pms_attr_reg_t region2_pms_attr;
-    volatile hp_apm_region3_addr_start_reg_t region3_addr_start;
-    volatile hp_apm_region3_addr_end_reg_t region3_addr_end;
-    volatile hp_apm_region3_pms_attr_reg_t region3_pms_attr;
-    volatile hp_apm_region4_addr_start_reg_t region4_addr_start;
-    volatile hp_apm_region4_addr_end_reg_t region4_addr_end;
-    volatile hp_apm_region4_pms_attr_reg_t region4_pms_attr;
-    volatile hp_apm_region5_addr_start_reg_t region5_addr_start;
-    volatile hp_apm_region5_addr_end_reg_t region5_addr_end;
-    volatile hp_apm_region5_pms_attr_reg_t region5_pms_attr;
-    volatile hp_apm_region6_addr_start_reg_t region6_addr_start;
-    volatile hp_apm_region6_addr_end_reg_t region6_addr_end;
-    volatile hp_apm_region6_pms_attr_reg_t region6_pms_attr;
-    volatile hp_apm_region7_addr_start_reg_t region7_addr_start;
-    volatile hp_apm_region7_addr_end_reg_t region7_addr_end;
-    volatile hp_apm_region7_pms_attr_reg_t region7_pms_attr;
-    volatile hp_apm_region8_addr_start_reg_t region8_addr_start;
-    volatile hp_apm_region8_addr_end_reg_t region8_addr_end;
-    volatile hp_apm_region8_pms_attr_reg_t region8_pms_attr;
-    volatile hp_apm_region9_addr_start_reg_t region9_addr_start;
-    volatile hp_apm_region9_addr_end_reg_t region9_addr_end;
-    volatile hp_apm_region9_pms_attr_reg_t region9_pms_attr;
-    volatile hp_apm_region10_addr_start_reg_t region10_addr_start;
-    volatile hp_apm_region10_addr_end_reg_t region10_addr_end;
-    volatile hp_apm_region10_pms_attr_reg_t region10_pms_attr;
-    volatile hp_apm_region11_addr_start_reg_t region11_addr_start;
-    volatile hp_apm_region11_addr_end_reg_t region11_addr_end;
-    volatile hp_apm_region11_pms_attr_reg_t region11_pms_attr;
-    volatile hp_apm_region12_addr_start_reg_t region12_addr_start;
-    volatile hp_apm_region12_addr_end_reg_t region12_addr_end;
-    volatile hp_apm_region12_pms_attr_reg_t region12_pms_attr;
-    volatile hp_apm_region13_addr_start_reg_t region13_addr_start;
-    volatile hp_apm_region13_addr_end_reg_t region13_addr_end;
-    volatile hp_apm_region13_pms_attr_reg_t region13_pms_attr;
-    volatile hp_apm_region14_addr_start_reg_t region14_addr_start;
-    volatile hp_apm_region14_addr_end_reg_t region14_addr_end;
-    volatile hp_apm_region14_pms_attr_reg_t region14_pms_attr;
-    volatile hp_apm_region15_addr_start_reg_t region15_addr_start;
-    volatile hp_apm_region15_addr_end_reg_t region15_addr_end;
-    volatile hp_apm_region15_pms_attr_reg_t region15_pms_attr;
-    volatile hp_apm_func_ctrl_reg_t func_ctrl;
-    volatile hp_apm_m0_status_reg_t m0_status;
-    volatile hp_apm_m0_status_clr_reg_t m0_status_clr;
-    volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0;
-    volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1;
-    volatile hp_apm_m1_status_reg_t m1_status;
-    volatile hp_apm_m1_status_clr_reg_t m1_status_clr;
-    volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0;
-    volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1;
-    volatile hp_apm_m2_status_reg_t m2_status;
-    volatile hp_apm_m2_status_clr_reg_t m2_status_clr;
-    volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0;
-    volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1;
-    volatile hp_apm_m3_status_reg_t m3_status;
-    volatile hp_apm_m3_status_clr_reg_t m3_status_clr;
-    volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0;
-    volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1;
-    volatile hp_apm_int_en_reg_t int_en;
-    volatile hp_apm_clock_gate_reg_t clock_gate;
-    uint32_t reserved_110[443];
-    volatile hp_apm_date_reg_t date;
-} hp_apm_dev_t;
-
-extern hp_apm_dev_t HP_APM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h b/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h
deleted file mode 100644
index faf1abf7f3..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h
+++ /dev/null
@@ -1,784 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
- *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
- */
-#define HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYS_BASE + 0x0)
-/** HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
- */
-#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
-#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S)
-#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT_S  0
-/** HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
-#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
-#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
-#define HP_SYS_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
-/** HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
- *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
- */
-#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
-#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
-#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
-#define HP_SYS_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
-/** HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
- *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
- */
-#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
-#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
-
-/** HP_SYS_SRAM_USAGE_CONF_REG register
- *  HP memory usage configuration register
- */
-#define HP_SYS_SRAM_USAGE_CONF_REG (DR_REG_HP_SYS_BASE + 0x4)
-/** HP_SYS_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define HP_SYS_CACHE_USAGE    (BIT(0))
-#define HP_SYS_CACHE_USAGE_M  (HP_SYS_CACHE_USAGE_V << HP_SYS_CACHE_USAGE_S)
-#define HP_SYS_CACHE_USAGE_V  0x00000001U
-#define HP_SYS_CACHE_USAGE_S  0
-/** HP_SYS_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
- *  0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
- */
-#define HP_SYS_SRAM_USAGE    0x0000000FU
-#define HP_SYS_SRAM_USAGE_M  (HP_SYS_SRAM_USAGE_V << HP_SYS_SRAM_USAGE_S)
-#define HP_SYS_SRAM_USAGE_V  0x0000000FU
-#define HP_SYS_SRAM_USAGE_S  8
-/** HP_SYS_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
- *  Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
- */
-#define HP_SYS_MAC_DUMP_ALLOC    (BIT(16))
-#define HP_SYS_MAC_DUMP_ALLOC_M  (HP_SYS_MAC_DUMP_ALLOC_V << HP_SYS_MAC_DUMP_ALLOC_S)
-#define HP_SYS_MAC_DUMP_ALLOC_V  0x00000001U
-#define HP_SYS_MAC_DUMP_ALLOC_S  16
-
-/** HP_SYS_SEC_DPA_CONF_REG register
- *  HP anti-DPA security configuration register
- */
-#define HP_SYS_SEC_DPA_CONF_REG (DR_REG_HP_SYS_BASE + 0x8)
-/** HP_SYS_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
- *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
- *  the number, the stronger the ability to resist DPA attacks and the higher the
- *  security level, but it will increase the computational overhead of the hardware
- *  crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
- */
-#define HP_SYS_SEC_DPA_LEVEL    0x00000003U
-#define HP_SYS_SEC_DPA_LEVEL_M  (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S)
-#define HP_SYS_SEC_DPA_LEVEL_V  0x00000003U
-#define HP_SYS_SEC_DPA_LEVEL_S  0
-/** HP_SYS_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
- *  This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
- *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
- */
-#define HP_SYS_SEC_DPA_CFG_SEL    (BIT(2))
-#define HP_SYS_SEC_DPA_CFG_SEL_M  (HP_SYS_SEC_DPA_CFG_SEL_V << HP_SYS_SEC_DPA_CFG_SEL_S)
-#define HP_SYS_SEC_DPA_CFG_SEL_V  0x00000001U
-#define HP_SYS_SEC_DPA_CFG_SEL_S  2
-
-/** HP_SYS_CPU_PERI_TIMEOUT_CONF_REG register
- *  CPU_PERI_TIMEOUT configuration register
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0xc)
-/** HP_SYS_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYS_CPU_PERI_TIMEOUT_THRES_M  (HP_SYS_CPU_PERI_TIMEOUT_THRES_V << HP_SYS_CPU_PERI_TIMEOUT_THRES_S)
-#define HP_SYS_CPU_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYS_CPU_PERI_TIMEOUT_THRES_S  0
-/** HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYS_CPU_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
- *  registers
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYS_CPU_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG register
- *  CPU_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x10)
-/** HP_SYS_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_M  (HP_SYS_CPU_PERI_TIMEOUT_ADDR_V << HP_SYS_CPU_PERI_TIMEOUT_ADDR_S)
-#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYS_CPU_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYS_CPU_PERI_TIMEOUT_UID_REG register
- *  CPU_PERI_TIMEOUT_UID register
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x14)
-/** HP_SYS_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYS_CPU_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYS_CPU_PERI_TIMEOUT_UID_M  (HP_SYS_CPU_PERI_TIMEOUT_UID_V << HP_SYS_CPU_PERI_TIMEOUT_UID_S)
-#define HP_SYS_CPU_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYS_CPU_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYS_HP_PERI_TIMEOUT_CONF_REG register
- *  HP_PERI_TIMEOUT configuration register
- */
-#define HP_SYS_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x18)
-/** HP_SYS_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYS_HP_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYS_HP_PERI_TIMEOUT_THRES_M  (HP_SYS_HP_PERI_TIMEOUT_THRES_V << HP_SYS_HP_PERI_TIMEOUT_THRES_S)
-#define HP_SYS_HP_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYS_HP_PERI_TIMEOUT_THRES_S  0
-/** HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYS_HP_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
- */
-#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYS_HP_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYS_HP_PERI_TIMEOUT_ADDR_REG register
- *  HP_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYS_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x1c)
-/** HP_SYS_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYS_HP_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYS_HP_PERI_TIMEOUT_ADDR_M  (HP_SYS_HP_PERI_TIMEOUT_ADDR_V << HP_SYS_HP_PERI_TIMEOUT_ADDR_S)
-#define HP_SYS_HP_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYS_HP_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYS_HP_PERI_TIMEOUT_UID_REG register
- *  HP_PERI_TIMEOUT_UID register
- */
-#define HP_SYS_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x20)
-/** HP_SYS_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYS_HP_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYS_HP_PERI_TIMEOUT_UID_M  (HP_SYS_HP_PERI_TIMEOUT_UID_V << HP_SYS_HP_PERI_TIMEOUT_UID_S)
-#define HP_SYS_HP_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYS_HP_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYS_MODEM_PERI_TIMEOUT_CONF_REG register
- *  MODEM_PERI_TIMEOUT configuration register
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x24)
-/** HP_SYS_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_M  (HP_SYS_MODEM_PERI_TIMEOUT_THRES_V << HP_SYS_MODEM_PERI_TIMEOUT_THRES_S)
-#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYS_MODEM_PERI_TIMEOUT_THRES_S  0
-/** HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYS_MODEM_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing modem registers
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYS_MODEM_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYS_MODEM_PERI_TIMEOUT_ADDR_REG register
- *  MODEM_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x28)
-/** HP_SYS_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_M  (HP_SYS_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYS_MODEM_PERI_TIMEOUT_ADDR_S)
-#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYS_MODEM_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYS_MODEM_PERI_TIMEOUT_UID_REG register
- *  MODEM_PERI_TIMEOUT_UID register
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x2c)
-/** HP_SYS_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYS_MODEM_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYS_MODEM_PERI_TIMEOUT_UID_M  (HP_SYS_MODEM_PERI_TIMEOUT_UID_V << HP_SYS_MODEM_PERI_TIMEOUT_UID_S)
-#define HP_SYS_MODEM_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYS_MODEM_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYS_SDIO_CTRL_REG register
- *  SDIO Control configuration register
- */
-#define HP_SYS_SDIO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x30)
-/** HP_SYS_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
- *  Set this bit as 1 to disable SDIO_PROB function. disable by default.
- */
-#define HP_SYS_DIS_SDIO_PROB    (BIT(0))
-#define HP_SYS_DIS_SDIO_PROB_M  (HP_SYS_DIS_SDIO_PROB_V << HP_SYS_DIS_SDIO_PROB_S)
-#define HP_SYS_DIS_SDIO_PROB_V  0x00000001U
-#define HP_SYS_DIS_SDIO_PROB_S  0
-/** HP_SYS_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
- *  Enable sdio slave to access other peripherals on the chip
- */
-#define HP_SYS_SDIO_WIN_ACCESS_EN    (BIT(1))
-#define HP_SYS_SDIO_WIN_ACCESS_EN_M  (HP_SYS_SDIO_WIN_ACCESS_EN_V << HP_SYS_SDIO_WIN_ACCESS_EN_S)
-#define HP_SYS_SDIO_WIN_ACCESS_EN_V  0x00000001U
-#define HP_SYS_SDIO_WIN_ACCESS_EN_S  1
-
-/** HP_SYS_ROM_TABLE_LOCK_REG register
- *  Rom-Table lock register
- */
-#define HP_SYS_ROM_TABLE_LOCK_REG (DR_REG_HP_SYS_BASE + 0x38)
-/** HP_SYS_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
- *  XXXX
- */
-#define HP_SYS_ROM_TABLE_LOCK    (BIT(0))
-#define HP_SYS_ROM_TABLE_LOCK_M  (HP_SYS_ROM_TABLE_LOCK_V << HP_SYS_ROM_TABLE_LOCK_S)
-#define HP_SYS_ROM_TABLE_LOCK_V  0x00000001U
-#define HP_SYS_ROM_TABLE_LOCK_S  0
-
-/** HP_SYS_ROM_TABLE_REG register
- *  Rom-Table register
- */
-#define HP_SYS_ROM_TABLE_REG (DR_REG_HP_SYS_BASE + 0x3c)
-/** HP_SYS_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
- *  XXXX
- */
-#define HP_SYS_ROM_TABLE    0xFFFFFFFFU
-#define HP_SYS_ROM_TABLE_M  (HP_SYS_ROM_TABLE_V << HP_SYS_ROM_TABLE_S)
-#define HP_SYS_ROM_TABLE_V  0xFFFFFFFFU
-#define HP_SYS_ROM_TABLE_S  0
-
-/** HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG register
- *  Core Debug runstall configure register
- */
-#define HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x40)
-/** HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
- */
-#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
-#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S)
-#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
-#define HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S  0
-/** HP_SYS_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0;
- *  Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
- *  not stalled.
- */
-#define HP_SYS_CORE_RUNSTALLED    (BIT(1))
-#define HP_SYS_CORE_RUNSTALLED_M  (HP_SYS_CORE_RUNSTALLED_V << HP_SYS_CORE_RUNSTALLED_S)
-#define HP_SYS_CORE_RUNSTALLED_V  0x00000001U
-#define HP_SYS_CORE_RUNSTALLED_S  1
-
-/** HP_SYS_MEM_TEST_CONF_REG register
- *  MEM_TEST configuration register
- */
-#define HP_SYS_MEM_TEST_CONF_REG (DR_REG_HP_SYS_BASE + 0x44)
-/** HP_SYS_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
- *  This field controls hp system memory WPULSE parameter.
- */
-#define HP_SYS_HP_MEM_WPULSE    0x00000007U
-#define HP_SYS_HP_MEM_WPULSE_M  (HP_SYS_HP_MEM_WPULSE_V << HP_SYS_HP_MEM_WPULSE_S)
-#define HP_SYS_HP_MEM_WPULSE_V  0x00000007U
-#define HP_SYS_HP_MEM_WPULSE_S  0
-/** HP_SYS_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
- *  This field controls hp system memory WA parameter.
- */
-#define HP_SYS_HP_MEM_WA    0x00000007U
-#define HP_SYS_HP_MEM_WA_M  (HP_SYS_HP_MEM_WA_V << HP_SYS_HP_MEM_WA_S)
-#define HP_SYS_HP_MEM_WA_V  0x00000007U
-#define HP_SYS_HP_MEM_WA_S  3
-/** HP_SYS_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
- *  This field controls hp system memory RA parameter.
- */
-#define HP_SYS_HP_MEM_RA    0x00000003U
-#define HP_SYS_HP_MEM_RA_M  (HP_SYS_HP_MEM_RA_V << HP_SYS_HP_MEM_RA_S)
-#define HP_SYS_HP_MEM_RA_V  0x00000003U
-#define HP_SYS_HP_MEM_RA_S  6
-
-/** HP_SYS_AUDIO_CODEC_SDADC_CNTL_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEC_SDADC_CNTL_REG (DR_REG_HP_SYS_BASE + 0x50)
-/** HP_SYS_SDADC_PAD_EN_VNCP : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define HP_SYS_SDADC_PAD_EN_VNCP    (BIT(0))
-#define HP_SYS_SDADC_PAD_EN_VNCP_M  (HP_SYS_SDADC_PAD_EN_VNCP_V << HP_SYS_SDADC_PAD_EN_VNCP_S)
-#define HP_SYS_SDADC_PAD_EN_VNCP_V  0x00000001U
-#define HP_SYS_SDADC_PAD_EN_VNCP_S  0
-/** HP_SYS_SDADC_PAD_FAST_CHG : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define HP_SYS_SDADC_PAD_FAST_CHG    (BIT(1))
-#define HP_SYS_SDADC_PAD_FAST_CHG_M  (HP_SYS_SDADC_PAD_FAST_CHG_V << HP_SYS_SDADC_PAD_FAST_CHG_S)
-#define HP_SYS_SDADC_PAD_FAST_CHG_V  0x00000001U
-#define HP_SYS_SDADC_PAD_FAST_CHG_S  1
-/** HP_SYS_SDADC_PAD_EN_0V : R/W; bitpos: [2]; default: 0;
- *  reserved
- */
-#define HP_SYS_SDADC_PAD_EN_0V    (BIT(2))
-#define HP_SYS_SDADC_PAD_EN_0V_M  (HP_SYS_SDADC_PAD_EN_0V_V << HP_SYS_SDADC_PAD_EN_0V_S)
-#define HP_SYS_SDADC_PAD_EN_0V_V  0x00000001U
-#define HP_SYS_SDADC_PAD_EN_0V_S  2
-/** HP_SYS_SDADC_EN_CHOPPER : R/W; bitpos: [3]; default: 1;
- *  reserved
- */
-#define HP_SYS_SDADC_EN_CHOPPER    (BIT(3))
-#define HP_SYS_SDADC_EN_CHOPPER_M  (HP_SYS_SDADC_EN_CHOPPER_V << HP_SYS_SDADC_EN_CHOPPER_S)
-#define HP_SYS_SDADC_EN_CHOPPER_V  0x00000001U
-#define HP_SYS_SDADC_EN_CHOPPER_S  3
-/** HP_SYS_SDADC_EN_DEM : R/W; bitpos: [4]; default: 1;
- *  reserved
- */
-#define HP_SYS_SDADC_EN_DEM    (BIT(4))
-#define HP_SYS_SDADC_EN_DEM_M  (HP_SYS_SDADC_EN_DEM_V << HP_SYS_SDADC_EN_DEM_S)
-#define HP_SYS_SDADC_EN_DEM_V  0x00000001U
-#define HP_SYS_SDADC_EN_DEM_S  4
-/** HP_SYS_SDADC_DREG_OA : R/W; bitpos: [7:5]; default: 3;
- *  reserved
- */
-#define HP_SYS_SDADC_DREG_OA    0x00000007U
-#define HP_SYS_SDADC_DREG_OA_M  (HP_SYS_SDADC_DREG_OA_V << HP_SYS_SDADC_DREG_OA_S)
-#define HP_SYS_SDADC_DREG_OA_V  0x00000007U
-#define HP_SYS_SDADC_DREG_OA_S  5
-/** HP_SYS_SDADC_DGAIN_INPUT : R/W; bitpos: [9:8]; default: 3;
- *  reserved
- */
-#define HP_SYS_SDADC_DGAIN_INPUT    0x00000003U
-#define HP_SYS_SDADC_DGAIN_INPUT_M  (HP_SYS_SDADC_DGAIN_INPUT_V << HP_SYS_SDADC_DGAIN_INPUT_S)
-#define HP_SYS_SDADC_DGAIN_INPUT_V  0x00000003U
-#define HP_SYS_SDADC_DGAIN_INPUT_S  8
-/** HP_SYS_SDADC_DCAP : R/W; bitpos: [14:10]; default: 12;
- *  reserved
- */
-#define HP_SYS_SDADC_DCAP    0x0000001FU
-#define HP_SYS_SDADC_DCAP_M  (HP_SYS_SDADC_DCAP_V << HP_SYS_SDADC_DCAP_S)
-#define HP_SYS_SDADC_DCAP_V  0x0000001FU
-#define HP_SYS_SDADC_DCAP_S  10
-
-/** HP_SYS_AUDIO_CODEC_DAC_L_CNTL_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEC_DAC_L_CNTL_REG (DR_REG_HP_SYS_BASE + 0x54)
-/** HP_SYS_ENHANCE_L_AUDIO_DAC : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define HP_SYS_ENHANCE_L_AUDIO_DAC    (BIT(0))
-#define HP_SYS_ENHANCE_L_AUDIO_DAC_M  (HP_SYS_ENHANCE_L_AUDIO_DAC_V << HP_SYS_ENHANCE_L_AUDIO_DAC_S)
-#define HP_SYS_ENHANCE_L_AUDIO_DAC_V  0x00000001U
-#define HP_SYS_ENHANCE_L_AUDIO_DAC_S  0
-/** HP_SYS_GAIN_L_AUDIO_DAC : R/W; bitpos: [5:1]; default: 19;
- *  reserved
- */
-#define HP_SYS_GAIN_L_AUDIO_DAC    0x0000001FU
-#define HP_SYS_GAIN_L_AUDIO_DAC_M  (HP_SYS_GAIN_L_AUDIO_DAC_V << HP_SYS_GAIN_L_AUDIO_DAC_S)
-#define HP_SYS_GAIN_L_AUDIO_DAC_V  0x0000001FU
-#define HP_SYS_GAIN_L_AUDIO_DAC_S  1
-/** HP_SYS_MUTE_L_AUDIO_DAC : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define HP_SYS_MUTE_L_AUDIO_DAC    (BIT(6))
-#define HP_SYS_MUTE_L_AUDIO_DAC_M  (HP_SYS_MUTE_L_AUDIO_DAC_V << HP_SYS_MUTE_L_AUDIO_DAC_S)
-#define HP_SYS_MUTE_L_AUDIO_DAC_V  0x00000001U
-#define HP_SYS_MUTE_L_AUDIO_DAC_S  6
-/** HP_SYS_XPD_L_AUDIO_DAC : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define HP_SYS_XPD_L_AUDIO_DAC    (BIT(7))
-#define HP_SYS_XPD_L_AUDIO_DAC_M  (HP_SYS_XPD_L_AUDIO_DAC_V << HP_SYS_XPD_L_AUDIO_DAC_S)
-#define HP_SYS_XPD_L_AUDIO_DAC_V  0x00000001U
-#define HP_SYS_XPD_L_AUDIO_DAC_S  7
-
-/** HP_SYS_AUDIO_CODEC_DAC_L_DIN_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEC_DAC_L_DIN_REG (DR_REG_HP_SYS_BASE + 0x58)
-/** HP_SYS_DAC_DIN_L : R/W; bitpos: [21:0]; default: 0;
- *  reserved
- */
-#define HP_SYS_DAC_DIN_L    0x003FFFFFU
-#define HP_SYS_DAC_DIN_L_M  (HP_SYS_DAC_DIN_L_V << HP_SYS_DAC_DIN_L_S)
-#define HP_SYS_DAC_DIN_L_V  0x003FFFFFU
-#define HP_SYS_DAC_DIN_L_S  0
-
-/** HP_SYS_AUDIO_CODEC_DAC_R_CNTL_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEC_DAC_R_CNTL_REG (DR_REG_HP_SYS_BASE + 0x5c)
-/** HP_SYS_ENHANCE_R_AUDIO_DAC : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define HP_SYS_ENHANCE_R_AUDIO_DAC    (BIT(0))
-#define HP_SYS_ENHANCE_R_AUDIO_DAC_M  (HP_SYS_ENHANCE_R_AUDIO_DAC_V << HP_SYS_ENHANCE_R_AUDIO_DAC_S)
-#define HP_SYS_ENHANCE_R_AUDIO_DAC_V  0x00000001U
-#define HP_SYS_ENHANCE_R_AUDIO_DAC_S  0
-/** HP_SYS_GAIN_R_AUDIO_DAC : R/W; bitpos: [5:1]; default: 19;
- *  reserved
- */
-#define HP_SYS_GAIN_R_AUDIO_DAC    0x0000001FU
-#define HP_SYS_GAIN_R_AUDIO_DAC_M  (HP_SYS_GAIN_R_AUDIO_DAC_V << HP_SYS_GAIN_R_AUDIO_DAC_S)
-#define HP_SYS_GAIN_R_AUDIO_DAC_V  0x0000001FU
-#define HP_SYS_GAIN_R_AUDIO_DAC_S  1
-/** HP_SYS_MUTE_R_AUDIO_DAC : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define HP_SYS_MUTE_R_AUDIO_DAC    (BIT(6))
-#define HP_SYS_MUTE_R_AUDIO_DAC_M  (HP_SYS_MUTE_R_AUDIO_DAC_V << HP_SYS_MUTE_R_AUDIO_DAC_S)
-#define HP_SYS_MUTE_R_AUDIO_DAC_V  0x00000001U
-#define HP_SYS_MUTE_R_AUDIO_DAC_S  6
-/** HP_SYS_XPD_R_AUDIO_DAC : R/W; bitpos: [7]; default: 0;
- *  reserved
- */
-#define HP_SYS_XPD_R_AUDIO_DAC    (BIT(7))
-#define HP_SYS_XPD_R_AUDIO_DAC_M  (HP_SYS_XPD_R_AUDIO_DAC_V << HP_SYS_XPD_R_AUDIO_DAC_S)
-#define HP_SYS_XPD_R_AUDIO_DAC_V  0x00000001U
-#define HP_SYS_XPD_R_AUDIO_DAC_S  7
-
-/** HP_SYS_AUDIO_CODEC_DAC_R_DIN_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEC_DAC_R_DIN_REG (DR_REG_HP_SYS_BASE + 0x60)
-/** HP_SYS_DAC_DIN_R : R/W; bitpos: [21:0]; default: 0;
- *  reserved
- */
-#define HP_SYS_DAC_DIN_R    0x003FFFFFU
-#define HP_SYS_DAC_DIN_R_M  (HP_SYS_DAC_DIN_R_V << HP_SYS_DAC_DIN_R_S)
-#define HP_SYS_DAC_DIN_R_V  0x003FFFFFU
-#define HP_SYS_DAC_DIN_R_S  0
-
-/** HP_SYS_AUDIO_CODEC_PLL_CNTL_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEC_PLL_CNTL_REG (DR_REG_HP_SYS_BASE + 0x64)
-/** HP_SYS_CAL_STOP_PLLA : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define HP_SYS_CAL_STOP_PLLA    (BIT(0))
-#define HP_SYS_CAL_STOP_PLLA_M  (HP_SYS_CAL_STOP_PLLA_V << HP_SYS_CAL_STOP_PLLA_S)
-#define HP_SYS_CAL_STOP_PLLA_V  0x00000001U
-#define HP_SYS_CAL_STOP_PLLA_S  0
-/** HP_SYS_CAL_END_PLLA : RO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define HP_SYS_CAL_END_PLLA    (BIT(1))
-#define HP_SYS_CAL_END_PLLA_M  (HP_SYS_CAL_END_PLLA_V << HP_SYS_CAL_END_PLLA_S)
-#define HP_SYS_CAL_END_PLLA_V  0x00000001U
-#define HP_SYS_CAL_END_PLLA_S  1
-
-/** HP_SYS_AUDIO_CODEC_DATA_MODE_CNTL_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEC_DATA_MODE_CNTL_REG (DR_REG_HP_SYS_BASE + 0x68)
-/** HP_SYS_AUDIO_ADC_MODE : R/W; bitpos: [1:0]; default: 0;
- *  reserved
- */
-#define HP_SYS_AUDIO_ADC_MODE    0x00000003U
-#define HP_SYS_AUDIO_ADC_MODE_M  (HP_SYS_AUDIO_ADC_MODE_V << HP_SYS_AUDIO_ADC_MODE_S)
-#define HP_SYS_AUDIO_ADC_MODE_V  0x00000003U
-#define HP_SYS_AUDIO_ADC_MODE_S  0
-/** HP_SYS_AUDIO_DAC_DSM_MODE_R : R/W; bitpos: [3:2]; default: 0;
- *  reserved
- */
-#define HP_SYS_AUDIO_DAC_DSM_MODE_R    0x00000003U
-#define HP_SYS_AUDIO_DAC_DSM_MODE_R_M  (HP_SYS_AUDIO_DAC_DSM_MODE_R_V << HP_SYS_AUDIO_DAC_DSM_MODE_R_S)
-#define HP_SYS_AUDIO_DAC_DSM_MODE_R_V  0x00000003U
-#define HP_SYS_AUDIO_DAC_DSM_MODE_R_S  2
-/** HP_SYS_AUDIO_DAC_DSM_MODE_L : R/W; bitpos: [5:4]; default: 0;
- *  reserved
- */
-#define HP_SYS_AUDIO_DAC_DSM_MODE_L    0x00000003U
-#define HP_SYS_AUDIO_DAC_DSM_MODE_L_M  (HP_SYS_AUDIO_DAC_DSM_MODE_L_V << HP_SYS_AUDIO_DAC_DSM_MODE_L_S)
-#define HP_SYS_AUDIO_DAC_DSM_MODE_L_V  0x00000003U
-#define HP_SYS_AUDIO_DAC_DSM_MODE_L_S  4
-
-/** HP_SYS_SPROM_CTRL_REG register
- *  reserved
- */
-#define HP_SYS_SPROM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
-/** HP_SYS_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
- *  reserved
- */
-#define HP_SYS_SPROM_MEM_AUX_CTRL    0xFFFFFFFFU
-#define HP_SYS_SPROM_MEM_AUX_CTRL_M  (HP_SYS_SPROM_MEM_AUX_CTRL_V << HP_SYS_SPROM_MEM_AUX_CTRL_S)
-#define HP_SYS_SPROM_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define HP_SYS_SPROM_MEM_AUX_CTRL_S  0
-
-/** HP_SYS_SPRAM_CTRL_REG register
- *  reserved
- */
-#define HP_SYS_SPRAM_CTRL_REG (DR_REG_HP_SYS_BASE + 0x74)
-/** HP_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  reserved
- */
-#define HP_SYS_SPRAM_MEM_AUX_CTRL    0xFFFFFFFFU
-#define HP_SYS_SPRAM_MEM_AUX_CTRL_M  (HP_SYS_SPRAM_MEM_AUX_CTRL_V << HP_SYS_SPRAM_MEM_AUX_CTRL_S)
-#define HP_SYS_SPRAM_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define HP_SYS_SPRAM_MEM_AUX_CTRL_S  0
-
-/** HP_SYS_SPRF_CTRL_REG register
- *  reserved
- */
-#define HP_SYS_SPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x78)
-/** HP_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  reserved
- */
-#define HP_SYS_SPRF_MEM_AUX_CTRL    0xFFFFFFFFU
-#define HP_SYS_SPRF_MEM_AUX_CTRL_M  (HP_SYS_SPRF_MEM_AUX_CTRL_V << HP_SYS_SPRF_MEM_AUX_CTRL_S)
-#define HP_SYS_SPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define HP_SYS_SPRF_MEM_AUX_CTRL_S  0
-
-/** HP_SYS_SDPRF_CTRL_REG register
- *  reserved
- */
-#define HP_SYS_SDPRF_CTRL_REG (DR_REG_HP_SYS_BASE + 0x7c)
-/** HP_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
- *  reserved
- */
-#define HP_SYS_SDPRF_MEM_AUX_CTRL    0xFFFFFFFFU
-#define HP_SYS_SDPRF_MEM_AUX_CTRL_M  (HP_SYS_SDPRF_MEM_AUX_CTRL_V << HP_SYS_SDPRF_MEM_AUX_CTRL_S)
-#define HP_SYS_SDPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define HP_SYS_SDPRF_MEM_AUX_CTRL_S  0
-
-/** HP_SYS_AUDIO_CODEX_CTRL0_REG register
- *  reserved
- */
-#define HP_SYS_AUDIO_CODEX_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x80)
-/** HP_SYS_DAC_IN_R1_IE : R/W; bitpos: [0]; default: 1;
- *  reserved
- */
-#define HP_SYS_DAC_IN_R1_IE    (BIT(0))
-#define HP_SYS_DAC_IN_R1_IE_M  (HP_SYS_DAC_IN_R1_IE_V << HP_SYS_DAC_IN_R1_IE_S)
-#define HP_SYS_DAC_IN_R1_IE_V  0x00000001U
-#define HP_SYS_DAC_IN_R1_IE_S  0
-/** HP_SYS_DAC_IN_R1_OE : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define HP_SYS_DAC_IN_R1_OE    (BIT(1))
-#define HP_SYS_DAC_IN_R1_OE_M  (HP_SYS_DAC_IN_R1_OE_V << HP_SYS_DAC_IN_R1_OE_S)
-#define HP_SYS_DAC_IN_R1_OE_V  0x00000001U
-#define HP_SYS_DAC_IN_R1_OE_S  1
-/** HP_SYS_DAC_IN_R0_IE : R/W; bitpos: [2]; default: 1;
- *  reserved
- */
-#define HP_SYS_DAC_IN_R0_IE    (BIT(2))
-#define HP_SYS_DAC_IN_R0_IE_M  (HP_SYS_DAC_IN_R0_IE_V << HP_SYS_DAC_IN_R0_IE_S)
-#define HP_SYS_DAC_IN_R0_IE_V  0x00000001U
-#define HP_SYS_DAC_IN_R0_IE_S  2
-/** HP_SYS_DAC_IN_R0_OE : R/W; bitpos: [3]; default: 0;
- *  reserved
- */
-#define HP_SYS_DAC_IN_R0_OE    (BIT(3))
-#define HP_SYS_DAC_IN_R0_OE_M  (HP_SYS_DAC_IN_R0_OE_V << HP_SYS_DAC_IN_R0_OE_S)
-#define HP_SYS_DAC_IN_R0_OE_V  0x00000001U
-#define HP_SYS_DAC_IN_R0_OE_S  3
-/** HP_SYS_ADC_DATA_4_IE : R/W; bitpos: [4]; default: 0;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_4_IE    (BIT(4))
-#define HP_SYS_ADC_DATA_4_IE_M  (HP_SYS_ADC_DATA_4_IE_V << HP_SYS_ADC_DATA_4_IE_S)
-#define HP_SYS_ADC_DATA_4_IE_V  0x00000001U
-#define HP_SYS_ADC_DATA_4_IE_S  4
-/** HP_SYS_ADC_DATA_4_OE : R/W; bitpos: [5]; default: 1;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_4_OE    (BIT(5))
-#define HP_SYS_ADC_DATA_4_OE_M  (HP_SYS_ADC_DATA_4_OE_V << HP_SYS_ADC_DATA_4_OE_S)
-#define HP_SYS_ADC_DATA_4_OE_V  0x00000001U
-#define HP_SYS_ADC_DATA_4_OE_S  5
-/** HP_SYS_ADC_DATA_3_IE : R/W; bitpos: [6]; default: 0;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_3_IE    (BIT(6))
-#define HP_SYS_ADC_DATA_3_IE_M  (HP_SYS_ADC_DATA_3_IE_V << HP_SYS_ADC_DATA_3_IE_S)
-#define HP_SYS_ADC_DATA_3_IE_V  0x00000001U
-#define HP_SYS_ADC_DATA_3_IE_S  6
-/** HP_SYS_ADC_DATA_3_OE : R/W; bitpos: [7]; default: 1;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_3_OE    (BIT(7))
-#define HP_SYS_ADC_DATA_3_OE_M  (HP_SYS_ADC_DATA_3_OE_V << HP_SYS_ADC_DATA_3_OE_S)
-#define HP_SYS_ADC_DATA_3_OE_V  0x00000001U
-#define HP_SYS_ADC_DATA_3_OE_S  7
-/** HP_SYS_ADC_DATA_2_IE : R/W; bitpos: [8]; default: 0;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_2_IE    (BIT(8))
-#define HP_SYS_ADC_DATA_2_IE_M  (HP_SYS_ADC_DATA_2_IE_V << HP_SYS_ADC_DATA_2_IE_S)
-#define HP_SYS_ADC_DATA_2_IE_V  0x00000001U
-#define HP_SYS_ADC_DATA_2_IE_S  8
-/** HP_SYS_ADC_DATA_2_OE : R/W; bitpos: [9]; default: 1;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_2_OE    (BIT(9))
-#define HP_SYS_ADC_DATA_2_OE_M  (HP_SYS_ADC_DATA_2_OE_V << HP_SYS_ADC_DATA_2_OE_S)
-#define HP_SYS_ADC_DATA_2_OE_V  0x00000001U
-#define HP_SYS_ADC_DATA_2_OE_S  9
-/** HP_SYS_ADC_DATA_1_IE : R/W; bitpos: [10]; default: 0;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_1_IE    (BIT(10))
-#define HP_SYS_ADC_DATA_1_IE_M  (HP_SYS_ADC_DATA_1_IE_V << HP_SYS_ADC_DATA_1_IE_S)
-#define HP_SYS_ADC_DATA_1_IE_V  0x00000001U
-#define HP_SYS_ADC_DATA_1_IE_S  10
-/** HP_SYS_ADC_DATA_1_OE : R/W; bitpos: [11]; default: 1;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_1_OE    (BIT(11))
-#define HP_SYS_ADC_DATA_1_OE_M  (HP_SYS_ADC_DATA_1_OE_V << HP_SYS_ADC_DATA_1_OE_S)
-#define HP_SYS_ADC_DATA_1_OE_V  0x00000001U
-#define HP_SYS_ADC_DATA_1_OE_S  11
-/** HP_SYS_ADC_DATA_0_IE : R/W; bitpos: [12]; default: 0;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_0_IE    (BIT(12))
-#define HP_SYS_ADC_DATA_0_IE_M  (HP_SYS_ADC_DATA_0_IE_V << HP_SYS_ADC_DATA_0_IE_S)
-#define HP_SYS_ADC_DATA_0_IE_V  0x00000001U
-#define HP_SYS_ADC_DATA_0_IE_S  12
-/** HP_SYS_ADC_DATA_0_OE : R/W; bitpos: [13]; default: 1;
- *  reserved
- */
-#define HP_SYS_ADC_DATA_0_OE    (BIT(13))
-#define HP_SYS_ADC_DATA_0_OE_M  (HP_SYS_ADC_DATA_0_OE_V << HP_SYS_ADC_DATA_0_OE_S)
-#define HP_SYS_ADC_DATA_0_OE_V  0x00000001U
-#define HP_SYS_ADC_DATA_0_OE_S  13
-/** HP_SYS_ADC_CK_DATA_IE : R/W; bitpos: [14]; default: 0;
- *  reserved
- */
-#define HP_SYS_ADC_CK_DATA_IE    (BIT(14))
-#define HP_SYS_ADC_CK_DATA_IE_M  (HP_SYS_ADC_CK_DATA_IE_V << HP_SYS_ADC_CK_DATA_IE_S)
-#define HP_SYS_ADC_CK_DATA_IE_V  0x00000001U
-#define HP_SYS_ADC_CK_DATA_IE_S  14
-/** HP_SYS_ADC_CK_DATA_OE : R/W; bitpos: [15]; default: 1;
- *  reserved
- */
-#define HP_SYS_ADC_CK_DATA_OE    (BIT(15))
-#define HP_SYS_ADC_CK_DATA_OE_M  (HP_SYS_ADC_CK_DATA_OE_V << HP_SYS_ADC_CK_DATA_OE_S)
-#define HP_SYS_ADC_CK_DATA_OE_V  0x00000001U
-#define HP_SYS_ADC_CK_DATA_OE_S  15
-
-/** HP_SYS_RND_ECO_REG register
- *  redcy eco register.
- */
-#define HP_SYS_RND_ECO_REG (DR_REG_HP_SYS_BASE + 0x3e0)
-/** HP_SYS_REDCY_ENA : W/R; bitpos: [0]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYS_REDCY_ENA    (BIT(0))
-#define HP_SYS_REDCY_ENA_M  (HP_SYS_REDCY_ENA_V << HP_SYS_REDCY_ENA_S)
-#define HP_SYS_REDCY_ENA_V  0x00000001U
-#define HP_SYS_REDCY_ENA_S  0
-/** HP_SYS_REDCY_RESULT : RO; bitpos: [1]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYS_REDCY_RESULT    (BIT(1))
-#define HP_SYS_REDCY_RESULT_M  (HP_SYS_REDCY_RESULT_V << HP_SYS_REDCY_RESULT_S)
-#define HP_SYS_REDCY_RESULT_V  0x00000001U
-#define HP_SYS_REDCY_RESULT_S  1
-
-/** HP_SYS_RND_ECO_LOW_REG register
- *  redcy eco low register.
- */
-#define HP_SYS_RND_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0x3e4)
-/** HP_SYS_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYS_REDCY_LOW    0xFFFFFFFFU
-#define HP_SYS_REDCY_LOW_M  (HP_SYS_REDCY_LOW_V << HP_SYS_REDCY_LOW_S)
-#define HP_SYS_REDCY_LOW_V  0xFFFFFFFFU
-#define HP_SYS_REDCY_LOW_S  0
-
-/** HP_SYS_RND_ECO_HIGH_REG register
- *  redcy eco high register.
- */
-#define HP_SYS_RND_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0x3e8)
-/** HP_SYS_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
- *  Only reserved for ECO.
- */
-#define HP_SYS_REDCY_HIGH    0xFFFFFFFFU
-#define HP_SYS_REDCY_HIGH_M  (HP_SYS_REDCY_HIGH_V << HP_SYS_REDCY_HIGH_S)
-#define HP_SYS_REDCY_HIGH_V  0xFFFFFFFFU
-#define HP_SYS_REDCY_HIGH_S  0
-
-/** HP_SYS_DEBUG_REG register
- *  HP-SYSTEM debug register
- */
-#define HP_SYS_DEBUG_REG (DR_REG_HP_SYS_BASE + 0x3f4)
-/** HP_SYS_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
- *  Reserved
- */
-#define HP_SYS_FPGA_DEBUG    (BIT(0))
-#define HP_SYS_FPGA_DEBUG_M  (HP_SYS_FPGA_DEBUG_V << HP_SYS_FPGA_DEBUG_S)
-#define HP_SYS_FPGA_DEBUG_V  0x00000001U
-#define HP_SYS_FPGA_DEBUG_S  0
-
-/** HP_SYS_CLOCK_GATE_REG register
- *  HP-SYSTEM clock gating configure register
- */
-#define HP_SYS_CLOCK_GATE_REG (DR_REG_HP_SYS_BASE + 0x3f8)
-/** HP_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to force on clock gating.
- */
-#define HP_SYS_CLK_EN    (BIT(0))
-#define HP_SYS_CLK_EN_M  (HP_SYS_CLK_EN_V << HP_SYS_CLK_EN_S)
-#define HP_SYS_CLK_EN_V  0x00000001U
-#define HP_SYS_CLK_EN_S  0
-
-/** HP_SYS_DATE_REG register
- *  Date register.
- */
-#define HP_SYS_DATE_REG (DR_REG_HP_SYS_BASE + 0x3fc)
-/** HP_SYS_DATE : R/W; bitpos: [27:0]; default: 36720768;
- *  HP-SYSTEM date information/ HP-SYSTEM version information.
- */
-#define HP_SYS_DATE    0x0FFFFFFFU
-#define HP_SYS_DATE_M  (HP_SYS_DATE_V << HP_SYS_DATE_S)
-#define HP_SYS_DATE_V  0x0FFFFFFFU
-#define HP_SYS_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/hp_system_struct.h b/components/soc/esp32c5/beta3/include/soc/hp_system_struct.h
deleted file mode 100644
index 3df7db3931..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/hp_system_struct.h
+++ /dev/null
@@ -1,760 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of external_device_encrypt_decrypt_control register
- *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
- */
-typedef union {
-    struct {
-        /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
-         */
-        uint32_t enable_spi_manual_encrypt:1;
-        /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t enable_download_db_encrypt:1;
-        /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
-         *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
-         */
-        uint32_t enable_download_g0cb_decrypt:1;
-        /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
-         *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
-         */
-        uint32_t enable_download_manual_encrypt:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_sys_external_device_encrypt_decrypt_control_reg_t;
-
-/** Type of sram_usage_conf register
- *  HP memory usage configuration register
- */
-typedef union {
-    struct {
-        /** cache_usage : HRO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t cache_usage:1;
-        uint32_t reserved_1:7;
-        /** sram_usage : R/W; bitpos: [11:8]; default: 0;
-         *  0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
-         */
-        uint32_t sram_usage:4;
-        uint32_t reserved_12:4;
-        /** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
-         */
-        uint32_t mac_dump_alloc:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} hp_sys_sram_usage_conf_reg_t;
-
-/** Type of sec_dpa_conf register
- *  HP anti-DPA security configuration register
- */
-typedef union {
-    struct {
-        /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
-         *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
-         *  the number, the stronger the ability to resist DPA attacks and the higher the
-         *  security level, but it will increase the computational overhead of the hardware
-         *  crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
-         */
-        uint32_t sec_dpa_level:2;
-        /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
-         *  This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
-         *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
-         */
-        uint32_t sec_dpa_cfg_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_sys_sec_dpa_conf_reg_t;
-
-/** Type of sdio_ctrl register
- *  SDIO Control configuration register
- */
-typedef union {
-    struct {
-        /** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
-         *  Set this bit as 1 to disable SDIO_PROB function. disable by default.
-         */
-        uint32_t dis_sdio_prob:1;
-        /** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
-         *  Enable sdio slave to access other peripherals on the chip
-         */
-        uint32_t sdio_win_access_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_sys_sdio_ctrl_reg_t;
-
-/** Type of rom_table_lock register
- *  Rom-Table lock register
- */
-typedef union {
-    struct {
-        /** rom_table_lock : R/W; bitpos: [0]; default: 0;
-         *  XXXX
-         */
-        uint32_t rom_table_lock:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_sys_rom_table_lock_reg_t;
-
-/** Type of rom_table register
- *  Rom-Table register
- */
-typedef union {
-    struct {
-        /** rom_table : R/W; bitpos: [31:0]; default: 0;
-         *  XXXX
-         */
-        uint32_t rom_table:32;
-    };
-    uint32_t val;
-} hp_sys_rom_table_reg_t;
-
-/** Type of core_debug_runstall_conf register
- *  Core Debug runstall configure register
- */
-typedef union {
-    struct {
-        /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
-         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
-         */
-        uint32_t core_debug_runstall_enable:1;
-        /** core_runstalled : RO; bitpos: [1]; default: 0;
-         *  Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
-         *  not stalled.
-         */
-        uint32_t core_runstalled:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_sys_core_debug_runstall_conf_reg_t;
-
-/** Type of mem_test_conf register
- *  MEM_TEST configuration register
- */
-typedef union {
-    struct {
-        /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
-         *  This field controls hp system memory WPULSE parameter.
-         */
-        uint32_t hp_mem_wpulse:3;
-        /** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
-         *  This field controls hp system memory WA parameter.
-         */
-        uint32_t hp_mem_wa:3;
-        /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
-         *  This field controls hp system memory RA parameter.
-         */
-        uint32_t hp_mem_ra:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hp_sys_mem_test_conf_reg_t;
-
-/** Type of audio_codec_sdadc_cntl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdadc_pad_en_vncp : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdadc_pad_en_vncp:1;
-        /** sdadc_pad_fast_chg : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t sdadc_pad_fast_chg:1;
-        /** sdadc_pad_en_0v : R/W; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t sdadc_pad_en_0v:1;
-        /** sdadc_en_chopper : R/W; bitpos: [3]; default: 1;
-         *  reserved
-         */
-        uint32_t sdadc_en_chopper:1;
-        /** sdadc_en_dem : R/W; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t sdadc_en_dem:1;
-        /** sdadc_dreg_oa : R/W; bitpos: [7:5]; default: 3;
-         *  reserved
-         */
-        uint32_t sdadc_dreg_oa:3;
-        /** sdadc_dgain_input : R/W; bitpos: [9:8]; default: 3;
-         *  reserved
-         */
-        uint32_t sdadc_dgain_input:2;
-        /** sdadc_dcap : R/W; bitpos: [14:10]; default: 12;
-         *  reserved
-         */
-        uint32_t sdadc_dcap:5;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} hp_sys_audio_codec_sdadc_cntl_reg_t;
-
-/** Type of audio_codec_dac_l_cntl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** enhance_l_audio_dac : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t enhance_l_audio_dac:1;
-        /** gain_l_audio_dac : R/W; bitpos: [5:1]; default: 19;
-         *  reserved
-         */
-        uint32_t gain_l_audio_dac:5;
-        /** mute_l_audio_dac : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t mute_l_audio_dac:1;
-        /** xpd_l_audio_dac : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t xpd_l_audio_dac:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hp_sys_audio_codec_dac_l_cntl_reg_t;
-
-/** Type of audio_codec_dac_l_din register
- *  reserved
- */
-typedef union {
-    struct {
-        /** dac_din_l : R/W; bitpos: [21:0]; default: 0;
-         *  reserved
-         */
-        uint32_t dac_din_l:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} hp_sys_audio_codec_dac_l_din_reg_t;
-
-/** Type of audio_codec_dac_r_cntl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** enhance_r_audio_dac : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t enhance_r_audio_dac:1;
-        /** gain_r_audio_dac : R/W; bitpos: [5:1]; default: 19;
-         *  reserved
-         */
-        uint32_t gain_r_audio_dac:5;
-        /** mute_r_audio_dac : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t mute_r_audio_dac:1;
-        /** xpd_r_audio_dac : R/W; bitpos: [7]; default: 0;
-         *  reserved
-         */
-        uint32_t xpd_r_audio_dac:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hp_sys_audio_codec_dac_r_cntl_reg_t;
-
-/** Type of audio_codec_dac_r_din register
- *  reserved
- */
-typedef union {
-    struct {
-        /** dac_din_r : R/W; bitpos: [21:0]; default: 0;
-         *  reserved
-         */
-        uint32_t dac_din_r:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} hp_sys_audio_codec_dac_r_din_reg_t;
-
-/** Type of audio_codec_pll_cntl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** cal_stop_plla : R/W; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t cal_stop_plla:1;
-        /** cal_end_plla : RO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t cal_end_plla:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_sys_audio_codec_pll_cntl_reg_t;
-
-/** Type of audio_codec_data_mode_cntl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** audio_adc_mode : R/W; bitpos: [1:0]; default: 0;
-         *  reserved
-         */
-        uint32_t audio_adc_mode:2;
-        /** audio_dac_dsm_mode_r : R/W; bitpos: [3:2]; default: 0;
-         *  reserved
-         */
-        uint32_t audio_dac_dsm_mode_r:2;
-        /** audio_dac_dsm_mode_l : R/W; bitpos: [5:4]; default: 0;
-         *  reserved
-         */
-        uint32_t audio_dac_dsm_mode_l:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_sys_audio_codec_data_mode_cntl_reg_t;
-
-/** Type of sprom_ctrl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
-         *  reserved
-         */
-        uint32_t sprom_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} hp_sys_sprom_ctrl_reg_t;
-
-/** Type of spram_ctrl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
-         *  reserved
-         */
-        uint32_t spram_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} hp_sys_spram_ctrl_reg_t;
-
-/** Type of sprf_ctrl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
-         *  reserved
-         */
-        uint32_t sprf_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} hp_sys_sprf_ctrl_reg_t;
-
-/** Type of sdprf_ctrl register
- *  reserved
- */
-typedef union {
-    struct {
-        /** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
-         *  reserved
-         */
-        uint32_t sdprf_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} hp_sys_sdprf_ctrl_reg_t;
-
-/** Type of audio_codex_ctrl0 register
- *  reserved
- */
-typedef union {
-    struct {
-        /** dac_in_r1_ie : R/W; bitpos: [0]; default: 1;
-         *  reserved
-         */
-        uint32_t dac_in_r1_ie:1;
-        /** dac_in_r1_oe : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t dac_in_r1_oe:1;
-        /** dac_in_r0_ie : R/W; bitpos: [2]; default: 1;
-         *  reserved
-         */
-        uint32_t dac_in_r0_ie:1;
-        /** dac_in_r0_oe : R/W; bitpos: [3]; default: 0;
-         *  reserved
-         */
-        uint32_t dac_in_r0_oe:1;
-        /** adc_data_4_ie : R/W; bitpos: [4]; default: 0;
-         *  reserved
-         */
-        uint32_t adc_data_4_ie:1;
-        /** adc_data_4_oe : R/W; bitpos: [5]; default: 1;
-         *  reserved
-         */
-        uint32_t adc_data_4_oe:1;
-        /** adc_data_3_ie : R/W; bitpos: [6]; default: 0;
-         *  reserved
-         */
-        uint32_t adc_data_3_ie:1;
-        /** adc_data_3_oe : R/W; bitpos: [7]; default: 1;
-         *  reserved
-         */
-        uint32_t adc_data_3_oe:1;
-        /** adc_data_2_ie : R/W; bitpos: [8]; default: 0;
-         *  reserved
-         */
-        uint32_t adc_data_2_ie:1;
-        /** adc_data_2_oe : R/W; bitpos: [9]; default: 1;
-         *  reserved
-         */
-        uint32_t adc_data_2_oe:1;
-        /** adc_data_1_ie : R/W; bitpos: [10]; default: 0;
-         *  reserved
-         */
-        uint32_t adc_data_1_ie:1;
-        /** adc_data_1_oe : R/W; bitpos: [11]; default: 1;
-         *  reserved
-         */
-        uint32_t adc_data_1_oe:1;
-        /** adc_data_0_ie : R/W; bitpos: [12]; default: 0;
-         *  reserved
-         */
-        uint32_t adc_data_0_ie:1;
-        /** adc_data_0_oe : R/W; bitpos: [13]; default: 1;
-         *  reserved
-         */
-        uint32_t adc_data_0_oe:1;
-        /** adc_ck_data_ie : R/W; bitpos: [14]; default: 0;
-         *  reserved
-         */
-        uint32_t adc_ck_data_ie:1;
-        /** adc_ck_data_oe : R/W; bitpos: [15]; default: 1;
-         *  reserved
-         */
-        uint32_t adc_ck_data_oe:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} hp_sys_audio_codex_ctrl0_reg_t;
-
-/** Type of clock_gate register
- *  HP-SYSTEM clock gating configure register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to force on clock gating.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_sys_clock_gate_reg_t;
-
-
-/** Group: Timeout Register */
-/** Type of cpu_peri_timeout_conf register
- *  CPU_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t cpu_peri_timeout_thres:16;
-        /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t cpu_peri_timeout_int_clear:1;
-        /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
-         *  registers
-         */
-        uint32_t cpu_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_sys_cpu_peri_timeout_conf_reg_t;
-
-/** Type of cpu_peri_timeout_addr register
- *  CPU_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t cpu_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_sys_cpu_peri_timeout_addr_reg_t;
-
-/** Type of cpu_peri_timeout_uid register
- *  CPU_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t cpu_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_sys_cpu_peri_timeout_uid_reg_t;
-
-/** Type of hp_peri_timeout_conf register
- *  HP_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t hp_peri_timeout_thres:16;
-        /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t hp_peri_timeout_int_clear:1;
-        /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
-         */
-        uint32_t hp_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_sys_hp_peri_timeout_conf_reg_t;
-
-/** Type of hp_peri_timeout_addr register
- *  HP_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t hp_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_sys_hp_peri_timeout_addr_reg_t;
-
-/** Type of hp_peri_timeout_uid register
- *  HP_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t hp_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_sys_hp_peri_timeout_uid_reg_t;
-
-/** Type of modem_peri_timeout_conf register
- *  MODEM_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t modem_peri_timeout_thres:16;
-        /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t modem_peri_timeout_int_clear:1;
-        /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing modem registers
-         */
-        uint32_t modem_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_sys_modem_peri_timeout_conf_reg_t;
-
-/** Type of modem_peri_timeout_addr register
- *  MODEM_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t modem_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_sys_modem_peri_timeout_addr_reg_t;
-
-/** Type of modem_peri_timeout_uid register
- *  MODEM_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t modem_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_sys_modem_peri_timeout_uid_reg_t;
-
-
-/** Group: Redcy ECO Registers */
-/** Type of rnd_eco register
- *  redcy eco register.
- */
-typedef union {
-    struct {
-        /** redcy_ena : W/R; bitpos: [0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_ena:1;
-        /** redcy_result : RO; bitpos: [1]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_sys_rnd_eco_reg_t;
-
-/** Type of rnd_eco_low register
- *  redcy eco low register.
- */
-typedef union {
-    struct {
-        /** redcy_low : W/R; bitpos: [31:0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_low:32;
-    };
-    uint32_t val;
-} hp_sys_rnd_eco_low_reg_t;
-
-/** Type of rnd_eco_high register
- *  redcy eco high register.
- */
-typedef union {
-    struct {
-        /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_high:32;
-    };
-    uint32_t val;
-} hp_sys_rnd_eco_high_reg_t;
-
-
-/** Group: Debug Register */
-/** Type of debug register
- *  HP-SYSTEM debug register
- */
-typedef union {
-    struct {
-        /** fpga_debug : R/W; bitpos: [0]; default: 1;
-         *  Reserved
-         */
-        uint32_t fpga_debug:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_sys_debug_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720768;
-         *  HP-SYSTEM date information/ HP-SYSTEM version information.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} hp_sys_date_reg_t;
-
-
-typedef struct {
-    volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
-    volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
-    volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;
-    volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
-    volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
-    volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
-    volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
-    volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
-    volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
-    volatile hp_sys_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
-    volatile hp_sys_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
-    volatile hp_sys_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
-    volatile hp_sys_sdio_ctrl_reg_t sdio_ctrl;
-    uint32_t reserved_034;
-    volatile hp_sys_rom_table_lock_reg_t rom_table_lock;
-    volatile hp_sys_rom_table_reg_t rom_table;
-    volatile hp_sys_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
-    volatile hp_sys_mem_test_conf_reg_t mem_test_conf;
-    uint32_t reserved_048[2];
-    volatile hp_sys_audio_codec_sdadc_cntl_reg_t audio_codec_sdadc_cntl;
-    volatile hp_sys_audio_codec_dac_l_cntl_reg_t audio_codec_dac_l_cntl;
-    volatile hp_sys_audio_codec_dac_l_din_reg_t audio_codec_dac_l_din;
-    volatile hp_sys_audio_codec_dac_r_cntl_reg_t audio_codec_dac_r_cntl;
-    volatile hp_sys_audio_codec_dac_r_din_reg_t audio_codec_dac_r_din;
-    volatile hp_sys_audio_codec_pll_cntl_reg_t audio_codec_pll_cntl;
-    volatile hp_sys_audio_codec_data_mode_cntl_reg_t audio_codec_data_mode_cntl;
-    uint32_t reserved_06c;
-    volatile hp_sys_sprom_ctrl_reg_t sprom_ctrl;
-    volatile hp_sys_spram_ctrl_reg_t spram_ctrl;
-    volatile hp_sys_sprf_ctrl_reg_t sprf_ctrl;
-    volatile hp_sys_sdprf_ctrl_reg_t sdprf_ctrl;
-    volatile hp_sys_audio_codex_ctrl0_reg_t audio_codex_ctrl0;
-    uint32_t reserved_084[215];
-    volatile hp_sys_rnd_eco_reg_t rnd_eco;
-    volatile hp_sys_rnd_eco_low_reg_t rnd_eco_low;
-    volatile hp_sys_rnd_eco_high_reg_t rnd_eco_high;
-    uint32_t reserved_3ec[2];
-    volatile hp_sys_debug_reg_t debug;
-    volatile hp_sys_clock_gate_reg_t clock_gate;
-    volatile hp_sys_date_reg_t date;
-} hp_sys_dev_t;
-
-extern hp_sys_dev_t HP_SYSTEM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/huk_reg.h b/components/soc/esp32c5/beta3/include/soc/huk_reg.h
deleted file mode 100644
index 3f394c71e4..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/huk_reg.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HUK_CLK_REG register
- *  HUK Generator clock gate control register
- */
-#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
-/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Write 1 to force on register clock gate.
- */
-#define HUK_CLK_EN    (BIT(0))
-#define HUK_CLK_EN_M  (HUK_CLK_EN_V << HUK_CLK_EN_S)
-#define HUK_CLK_EN_V  0x00000001U
-#define HUK_CLK_EN_S  0
-/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
- *  Write 1 to force on memory clock gate.
- */
-#define HUK_MEM_CG_FORCE_ON    (BIT(1))
-#define HUK_MEM_CG_FORCE_ON_M  (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
-#define HUK_MEM_CG_FORCE_ON_V  0x00000001U
-#define HUK_MEM_CG_FORCE_ON_S  1
-
-/** HUK_INT_RAW_REG register
- *  HUK Generator interrupt raw register, valid in level.
- */
-#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
-/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the huk_prep_done_int interrupt
- */
-#define HUK_PREP_DONE_INT_RAW    (BIT(0))
-#define HUK_PREP_DONE_INT_RAW_M  (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
-#define HUK_PREP_DONE_INT_RAW_V  0x00000001U
-#define HUK_PREP_DONE_INT_RAW_S  0
-/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the huk_proc_done_int interrupt
- */
-#define HUK_PROC_DONE_INT_RAW    (BIT(1))
-#define HUK_PROC_DONE_INT_RAW_M  (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
-#define HUK_PROC_DONE_INT_RAW_V  0x00000001U
-#define HUK_PROC_DONE_INT_RAW_S  1
-/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the huk_post_done_int interrupt
- */
-#define HUK_POST_DONE_INT_RAW    (BIT(2))
-#define HUK_POST_DONE_INT_RAW_M  (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
-#define HUK_POST_DONE_INT_RAW_V  0x00000001U
-#define HUK_POST_DONE_INT_RAW_S  2
-
-/** HUK_INT_ST_REG register
- *  HUK Generator interrupt status register.
- */
-#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
-/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the huk_prep_done_int interrupt
- */
-#define HUK_PREP_DONE_INT_ST    (BIT(0))
-#define HUK_PREP_DONE_INT_ST_M  (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
-#define HUK_PREP_DONE_INT_ST_V  0x00000001U
-#define HUK_PREP_DONE_INT_ST_S  0
-/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the huk_proc_done_int interrupt
- */
-#define HUK_PROC_DONE_INT_ST    (BIT(1))
-#define HUK_PROC_DONE_INT_ST_M  (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
-#define HUK_PROC_DONE_INT_ST_V  0x00000001U
-#define HUK_PROC_DONE_INT_ST_S  1
-/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the huk_post_done_int interrupt
- */
-#define HUK_POST_DONE_INT_ST    (BIT(2))
-#define HUK_POST_DONE_INT_ST_M  (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
-#define HUK_POST_DONE_INT_ST_V  0x00000001U
-#define HUK_POST_DONE_INT_ST_S  2
-
-/** HUK_INT_ENA_REG register
- *  HUK Generator interrupt enable register.
- */
-#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
-/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the huk_prep_done_int interrupt
- */
-#define HUK_PREP_DONE_INT_ENA    (BIT(0))
-#define HUK_PREP_DONE_INT_ENA_M  (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
-#define HUK_PREP_DONE_INT_ENA_V  0x00000001U
-#define HUK_PREP_DONE_INT_ENA_S  0
-/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the huk_proc_done_int interrupt
- */
-#define HUK_PROC_DONE_INT_ENA    (BIT(1))
-#define HUK_PROC_DONE_INT_ENA_M  (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
-#define HUK_PROC_DONE_INT_ENA_V  0x00000001U
-#define HUK_PROC_DONE_INT_ENA_S  1
-/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the huk_post_done_int interrupt
- */
-#define HUK_POST_DONE_INT_ENA    (BIT(2))
-#define HUK_POST_DONE_INT_ENA_M  (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
-#define HUK_POST_DONE_INT_ENA_V  0x00000001U
-#define HUK_POST_DONE_INT_ENA_S  2
-
-/** HUK_INT_CLR_REG register
- *  HUK Generator interrupt clear register.
- */
-#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
-/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the huk_prep_done_int interrupt
- */
-#define HUK_PREP_DONE_INT_CLR    (BIT(0))
-#define HUK_PREP_DONE_INT_CLR_M  (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
-#define HUK_PREP_DONE_INT_CLR_V  0x00000001U
-#define HUK_PREP_DONE_INT_CLR_S  0
-/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the huk_proc_done_int interrupt
- */
-#define HUK_PROC_DONE_INT_CLR    (BIT(1))
-#define HUK_PROC_DONE_INT_CLR_M  (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
-#define HUK_PROC_DONE_INT_CLR_V  0x00000001U
-#define HUK_PROC_DONE_INT_CLR_S  1
-/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the huk_post_done_int interrupt
- */
-#define HUK_POST_DONE_INT_CLR    (BIT(2))
-#define HUK_POST_DONE_INT_CLR_M  (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
-#define HUK_POST_DONE_INT_CLR_V  0x00000001U
-#define HUK_POST_DONE_INT_CLR_S  2
-
-/** HUK_CONF_REG register
- *  HUK Generator configuration register
- */
-#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
-/** HUK_MODE : R/W; bitpos: [0]; default: 0;
- *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
- *  huk recovery mode.
- */
-#define HUK_MODE    (BIT(0))
-#define HUK_MODE_M  (HUK_MODE_V << HUK_MODE_S)
-#define HUK_MODE_V  0x00000001U
-#define HUK_MODE_S  0
-
-/** HUK_START_REG register
- *  HUK Generator control register
- */
-#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
-/** HUK_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
- */
-#define HUK_START    (BIT(0))
-#define HUK_START_M  (HUK_START_V << HUK_START_S)
-#define HUK_START_V  0x00000001U
-#define HUK_START_S  0
-/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
- *  Write 1 to start HUK Generator at IDLE state.
- */
-#define HUK_CONTINUE    (BIT(1))
-#define HUK_CONTINUE_M  (HUK_CONTINUE_V << HUK_CONTINUE_S)
-#define HUK_CONTINUE_V  0x00000001U
-#define HUK_CONTINUE_S  1
-
-/** HUK_STATE_REG register
- *  HUK Generator state register
- */
-#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
-/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
- *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
- */
-#define HUK_STATE    0x00000003U
-#define HUK_STATE_M  (HUK_STATE_V << HUK_STATE_S)
-#define HUK_STATE_V  0x00000003U
-#define HUK_STATE_S  0
-
-/** HUK_STATUS_REG register
- *  HUK Generator HUK status register
- */
-#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
-/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
- *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
- *  2: HUK is generated but invalid. 3: reserved.
- */
-#define HUK_STATUS    0x00000003U
-#define HUK_STATUS_M  (HUK_STATUS_V << HUK_STATUS_S)
-#define HUK_STATUS_V  0x00000003U
-#define HUK_STATUS_S  0
-/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
- *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
- *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
- */
-#define HUK_RISK_LEVEL    0x00000007U
-#define HUK_RISK_LEVEL_M  (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
-#define HUK_RISK_LEVEL_V  0x00000007U
-#define HUK_RISK_LEVEL_S  2
-
-/** HUK_DATE_REG register
- *  Version control register
- */
-#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
-/** HUK_DATE : R/W; bitpos: [27:0]; default: 36720704;
- *  HUK Generator version control register.
- */
-#define HUK_DATE    0x0FFFFFFFU
-#define HUK_DATE_M  (HUK_DATE_V << HUK_DATE_S)
-#define HUK_DATE_V  0x0FFFFFFFU
-#define HUK_DATE_S  0
-
-/** HUK_INFO_MEM register
- *  The memory that stores HUK info.
- */
-#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
-#define HUK_INFO_MEM_SIZE_BYTES 384
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/huk_struct.h b/components/soc/esp32c5/beta3/include/soc/huk_struct.h
deleted file mode 100644
index ac2002070a..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/huk_struct.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory data */
-
-/** Group: Clock gate register */
-/** Type of clk register
- *  HUK Generator clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_en:1;
-        /** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to force on memory clock gate.
-         */
-        uint32_t mem_cg_force_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} huk_clk_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  HUK Generator interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the huk_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_raw:1;
-        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the huk_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_raw:1;
-        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the huk_post_done_int interrupt
-         */
-        uint32_t post_done_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} huk_int_raw_reg_t;
-
-/** Type of int_st register
- *  HUK Generator interrupt status register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the huk_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_st:1;
-        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the huk_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_st:1;
-        /** post_done_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the huk_post_done_int interrupt
-         */
-        uint32_t post_done_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} huk_int_st_reg_t;
-
-/** Type of int_ena register
- *  HUK Generator interrupt enable register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the huk_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_ena:1;
-        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the huk_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_ena:1;
-        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the huk_post_done_int interrupt
-         */
-        uint32_t post_done_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} huk_int_ena_reg_t;
-
-/** Type of int_clr register
- *  HUK Generator interrupt clear register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the huk_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_clr:1;
-        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the huk_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_clr:1;
-        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the huk_post_done_int interrupt
-         */
-        uint32_t post_done_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} huk_int_clr_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of conf register
- *  HUK Generator configuration register
- */
-typedef union {
-    struct {
-        /** mode : R/W; bitpos: [0]; default: 0;
-         *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
-         *  huk recovery mode.
-         */
-        uint32_t mode:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} huk_conf_reg_t;
-
-
-/** Group: Control registers */
-/** Type of start register
- *  HUK Generator control register
- */
-typedef union {
-    struct {
-        /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start HUK Generator at IDLE state.
-         */
-        uint32_t start:1;
-        /** conti : WT; bitpos: [1]; default: 0;
-         *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
-         */
-        uint32_t conti:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} huk_start_reg_t;
-
-
-/** Group: State registers */
-/** Type of state register
- *  HUK Generator state register
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [1:0]; default: 0;
-         *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
-         */
-        uint32_t state:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} huk_state_reg_t;
-
-
-/** Group: Result registers */
-/** Type of status register
- *  HUK Generator HUK status register
- */
-typedef union {
-    struct {
-        /** status : RO; bitpos: [1:0]; default: 0;
-         *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
-         *  2: HUK is generated but invalid. 3: reserved.
-         */
-        uint32_t status:2;
-        /** risk_level : RO; bitpos: [4:2]; default: 0;
-         *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
-         *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
-         */
-        uint32_t risk_level:3;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} huk_status_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720704;
-         *  HUK Generator version control register.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} huk_date_reg_t;
-
-
-typedef struct huk_dev_t {
-    uint32_t reserved_000;
-    volatile huk_clk_reg_t clk;
-    volatile huk_int_raw_reg_t int_raw;
-    volatile huk_int_st_reg_t int_st;
-    volatile huk_int_ena_reg_t int_ena;
-    volatile huk_int_clr_reg_t int_clr;
-    uint32_t reserved_018[2];
-    volatile huk_conf_reg_t conf;
-    volatile huk_start_reg_t start;
-    volatile huk_state_reg_t state;
-    uint32_t reserved_02c[2];
-    volatile huk_status_reg_t status;
-    uint32_t reserved_038[49];
-    volatile huk_date_reg_t date;
-    volatile uint32_t info[96];
-} huk_dev_t;
-
-extern huk_dev_t HUK;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/i2c_reg.h b/components/soc/esp32c5/beta3/include/soc/i2c_reg.h
deleted file mode 100644
index 49f3185e78..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/i2c_reg.h
+++ /dev/null
@@ -1,1521 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2C_SCL_LOW_PERIOD_REG register
- *  Configures the low level width of the SCL Clock.
- */
-#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
-/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  Configures the low level width of the SCL Clock.
- *  Measurement unit: i2c_sclk.
- */
-#define I2C_SCL_LOW_PERIOD    0x000001FFU
-#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
-#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
-#define I2C_SCL_LOW_PERIOD_S  0
-
-/** I2C_CTR_REG register
- *  Transmission setting
- */
-#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
-/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
- *  Configures the SDA output mode
- *  1: Direct output,
- *
- *  0: Open drain output.
- */
-#define I2C_SDA_FORCE_OUT    (BIT(0))
-#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
-#define I2C_SDA_FORCE_OUT_V  0x00000001U
-#define I2C_SDA_FORCE_OUT_S  0
-/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
- *  Configures the SCL output mode
- *  1: Direct output,
- *
- *  0: Open drain output.
- */
-#define I2C_SCL_FORCE_OUT    (BIT(1))
-#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
-#define I2C_SCL_FORCE_OUT_V  0x00000001U
-#define I2C_SCL_FORCE_OUT_S  1
-/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
- *  Configures the sample mode for SDA.
- *  1: Sample SDA data on the SCL low level.
- *
- *  0: Sample SDA data on the SCL high level.
- */
-#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
-#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
-#define I2C_SAMPLE_SCL_LEVEL_S  2
-/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
- *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
- *  reached the threshold.
- */
-#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
-#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
-#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
-#define I2C_RX_FULL_ACK_LEVEL_S  3
-/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
- *  Configures the module as an I2C Master or Slave.
- *  0: Slave
- *
- *  1: Master
- */
-#define I2C_MS_MODE    (BIT(4))
-#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
-#define I2C_MS_MODE_V  0x00000001U
-#define I2C_MS_MODE_S  4
-/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
- *  Configures to start sending the data in txfifo for slave.
- *  0: No effect
- *
- *  1: Start
- */
-#define I2C_TRANS_START    (BIT(5))
-#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
-#define I2C_TRANS_START_V  0x00000001U
-#define I2C_TRANS_START_S  5
-/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
- *  Configures to control the sending order for data needing to be sent.
- *  1: send data from the least significant bit,
- *
- *  0: send data from the most significant bit.
- */
-#define I2C_TX_LSB_FIRST    (BIT(6))
-#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
-#define I2C_TX_LSB_FIRST_V  0x00000001U
-#define I2C_TX_LSB_FIRST_S  6
-/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
- *  Configures to control the storage order for received data.
- *  1: receive data from the least significant bit
- *
- *  0: receive data from the most significant bit.
- */
-#define I2C_RX_LSB_FIRST    (BIT(7))
-#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
-#define I2C_RX_LSB_FIRST_V  0x00000001U
-#define I2C_RX_LSB_FIRST_S  7
-/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether to gate clock signal for registers.
- *
- *  0: Force clock on for registers
- *
- *  1: Support clock only when registers are read or written to by software.
- */
-#define I2C_CLK_EN    (BIT(8))
-#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
-#define I2C_CLK_EN_V  0x00000001U
-#define I2C_CLK_EN_S  8
-/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
- *  Configures to enable I2C bus arbitration detection.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_ARBITRATION_EN    (BIT(9))
-#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
-#define I2C_ARBITRATION_EN_V  0x00000001U
-#define I2C_ARBITRATION_EN_S  9
-/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
- *  Configures to reset the SCL_FSM.
- *  0: No effect
- *
- *  1: Reset
- */
-#define I2C_FSM_RST    (BIT(10))
-#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
-#define I2C_FSM_RST_V  0x00000001U
-#define I2C_FSM_RST_S  10
-/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
- *  Configures this bit for synchronization
- *  0: No effect
- *
- *  1: Synchronize
- */
-#define I2C_CONF_UPGATE    (BIT(11))
-#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
-#define I2C_CONF_UPGATE_V  0x00000001U
-#define I2C_CONF_UPGATE_S  11
-/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
- *  Configures to enable slave to send data automatically
- *  0: Disable
- *
- *  1: Enable
- */
-#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
-#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
-#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
-#define I2C_SLV_TX_AUTO_START_EN_S  12
-/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
- *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
- *  0: Not check
- *
- *  1: Check
- */
-#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
-#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
-#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
-#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
-/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
- *  Configures to support the 7bit general call function.
- *  0: Not support
- *
- *  1: Support
- */
-#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
-#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
-#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
-#define I2C_ADDR_BROADCASTING_EN_S  14
-
-/** I2C_SR_REG register
- *  Describe I2C work status.
- */
-#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
-/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
- *  Represents the received ACK value in master mode or slave mode.
- *  0: ACK,
- *
- *  1: NACK.
- */
-#define I2C_RESP_REC    (BIT(0))
-#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
-#define I2C_RESP_REC_V  0x00000001U
-#define I2C_RESP_REC_S  0
-/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
- *  Represents the transfer direction in slave mode,.
- *  1: Master reads from slave,
- *
- *  0: Master writes to slave.
- */
-#define I2C_SLAVE_RW    (BIT(1))
-#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
-#define I2C_SLAVE_RW_V  0x00000001U
-#define I2C_SLAVE_RW_S  1
-/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
- *  Represents whether the I2C controller loses control of SCL line.
- *  0: No arbitration lost
- *
- *  1: Arbitration lost
- */
-#define I2C_ARB_LOST    (BIT(3))
-#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
-#define I2C_ARB_LOST_V  0x00000001U
-#define I2C_ARB_LOST_S  3
-/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
- *  Represents the I2C bus state.
- *  1: The I2C bus is busy transferring data,
- *
- *  0: The I2C bus is in idle state.
- */
-#define I2C_BUS_BUSY    (BIT(4))
-#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
-#define I2C_BUS_BUSY_V  0x00000001U
-#define I2C_BUS_BUSY_S  4
-/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
- *  Represents whether the address sent by the master is equal to the address of the
- *  slave.
- *  Valid only when the module is configured as an I2C Slave.
- *  0: Not equal
- *
- *  1: Equal
- */
-#define I2C_SLAVE_ADDRESSED    (BIT(5))
-#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
-#define I2C_SLAVE_ADDRESSED_V  0x00000001U
-#define I2C_SLAVE_ADDRESSED_S  5
-/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
- *  Represents the number of data bytes to be sent.
- */
-#define I2C_RXFIFO_CNT    0x0000003FU
-#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
-#define I2C_RXFIFO_CNT_V  0x0000003FU
-#define I2C_RXFIFO_CNT_S  8
-/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
- *  Represents the cause of SCL clocking stretching in slave mode.
- *  0: Stretching SCL low when the master starts to read data.
- *
- *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
- *
- *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
- */
-#define I2C_STRETCH_CAUSE    0x00000003U
-#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
-#define I2C_STRETCH_CAUSE_V  0x00000003U
-#define I2C_STRETCH_CAUSE_S  14
-/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
- *  Represents the number of data bytes received in RAM.
- */
-#define I2C_TXFIFO_CNT    0x0000003FU
-#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
-#define I2C_TXFIFO_CNT_V  0x0000003FU
-#define I2C_TXFIFO_CNT_S  18
-/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
- *  Represents the states of the I2C module state machine.
- *  0: Idle,
- *
- *  1: Address shift,
- *
- *  2: ACK address,
- *
- *  3: Rx data,
- *
- *  4: Tx data,
- *
- *  5: Send ACK,
- *
- *  6: Wait ACK
- */
-#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
-#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
-#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
-#define I2C_SCL_MAIN_STATE_LAST_S  24
-/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
- *  Represents the states of the state machine used to produce SCL.
- *  0: Idle,
- *
- *  1: Start,
- *
- *  2: Negative edge,
- *
- *  3: Low,
- *
- *  4: Positive edge,
- *
- *  5: High,
- *
- *  6: Stop
- */
-#define I2C_SCL_STATE_LAST    0x00000007U
-#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
-#define I2C_SCL_STATE_LAST_V  0x00000007U
-#define I2C_SCL_STATE_LAST_S  28
-
-/** I2C_TO_REG register
- *  Setting time out control for receiving data.
- */
-#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
-/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
- *  Configures the timeout threshold period for SCL stucking at high or low level. The
- *  actual period is 2^(reg_time_out_value).
- *  Measurement unit: i2c_sclk.
- */
-#define I2C_TIME_OUT_VALUE    0x0000001FU
-#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
-#define I2C_TIME_OUT_VALUE_V  0x0000001FU
-#define I2C_TIME_OUT_VALUE_S  0
-/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
- *  Configures to enable time out control.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_TIME_OUT_EN    (BIT(5))
-#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
-#define I2C_TIME_OUT_EN_V  0x00000001U
-#define I2C_TIME_OUT_EN_S  5
-
-/** I2C_SLAVE_ADDR_REG register
- *  Local slave address setting
- */
-#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
-/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
- *  Configure the slave address of I2C Slave.
- */
-#define I2C_SLAVE_ADDR    0x00007FFFU
-#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
-#define I2C_SLAVE_ADDR_V  0x00007FFFU
-#define I2C_SLAVE_ADDR_S  0
-/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
- *  Configures to enable the slave 10-bit addressing mode in master mode.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_ADDR_10BIT_EN    (BIT(31))
-#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
-#define I2C_ADDR_10BIT_EN_V  0x00000001U
-#define I2C_ADDR_10BIT_EN_S  31
-
-/** I2C_FIFO_ST_REG register
- *  FIFO status register.
- */
-#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
-/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
- *  Represents the offset address of the APB reading from RXFIFO
- */
-#define I2C_RXFIFO_RADDR    0x0000001FU
-#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
-#define I2C_RXFIFO_RADDR_V  0x0000001FU
-#define I2C_RXFIFO_RADDR_S  0
-/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
- *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
- */
-#define I2C_RXFIFO_WADDR    0x0000001FU
-#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
-#define I2C_RXFIFO_WADDR_V  0x0000001FU
-#define I2C_RXFIFO_WADDR_S  5
-/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
- *  Represents the offset address of i2c module reading from TXFIFO.
- */
-#define I2C_TXFIFO_RADDR    0x0000001FU
-#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
-#define I2C_TXFIFO_RADDR_V  0x0000001FU
-#define I2C_TXFIFO_RADDR_S  10
-/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
- *  Represents the offset address of APB bus writing to TXFIFO.
- */
-#define I2C_TXFIFO_WADDR    0x0000001FU
-#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
-#define I2C_TXFIFO_WADDR_V  0x0000001FU
-#define I2C_TXFIFO_WADDR_S  15
-/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
- *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
- *  I2C slave mode.
- */
-#define I2C_SLAVE_RW_POINT    0x000000FFU
-#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
-#define I2C_SLAVE_RW_POINT_V  0x000000FFU
-#define I2C_SLAVE_RW_POINT_S  22
-
-/** I2C_FIFO_CONF_REG register
- *  FIFO configuration register.
- */
-#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
-/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
- *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
- *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
- */
-#define I2C_RXFIFO_WM_THRHD    0x0000001FU
-#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
-#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
-#define I2C_RXFIFO_WM_THRHD_S  0
-/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
- *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
- *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
- */
-#define I2C_TXFIFO_WM_THRHD    0x0000001FU
-#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
-#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
-#define I2C_TXFIFO_WM_THRHD_S  5
-/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
- *  Configures to enable APB nonfifo access.
- */
-#define I2C_NONFIFO_EN    (BIT(10))
-#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
-#define I2C_NONFIFO_EN_V  0x00000001U
-#define I2C_NONFIFO_EN_S  10
-/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
- *  Configures to enable double addressing mode. When this mode is enabled, the byte
- *  received after the I2C address byte represents the offset address in the I2C Slave
- *  RAM.
- *  0: Disable
- *
- *  1: Enable
- */
-#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
-#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
-#define I2C_FIFO_ADDR_CFG_EN_S  11
-/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
- *  Configures to reset RXFIFO.
- *  0: No effect
- *
- *  1: Reset
- */
-#define I2C_RX_FIFO_RST    (BIT(12))
-#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
-#define I2C_RX_FIFO_RST_V  0x00000001U
-#define I2C_RX_FIFO_RST_S  12
-/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
- *  Configures to reset TXFIFO.
- *  0: No effect
- *
- *  1: Reset
- */
-#define I2C_TX_FIFO_RST    (BIT(13))
-#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
-#define I2C_TX_FIFO_RST_V  0x00000001U
-#define I2C_TX_FIFO_RST_S  13
-/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
- *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
- *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
- *  0: No effect
- *
- *  1: Enable
- */
-#define I2C_FIFO_PRT_EN    (BIT(14))
-#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
-#define I2C_FIFO_PRT_EN_V  0x00000001U
-#define I2C_FIFO_PRT_EN_S  14
-
-/** I2C_DATA_REG register
- *  Rx FIFO read data.
- */
-#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
-/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
- *  Represents the value of RXFIFO read data.
- */
-#define I2C_FIFO_RDATA    0x000000FFU
-#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
-#define I2C_FIFO_RDATA_V  0x000000FFU
-#define I2C_FIFO_RDATA_S  0
-
-/** I2C_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
-/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
-#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
-#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_RAW_S  0
-/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
- *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
-#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
-#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_RAW_S  1
-/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
-#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_RAW_S  2
-/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
- *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_RAW    (BIT(3))
-#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
-#define I2C_END_DETECT_INT_RAW_V  0x00000001U
-#define I2C_END_DETECT_INT_RAW_S  3
-/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
- *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
-#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
-/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
- *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
-#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_RAW_S  5
-/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
- *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
-#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
-/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
- *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
-#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_RAW_S  7
-/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
- *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_RAW    (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
-#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
-#define I2C_TIME_OUT_INT_RAW_S  8
-/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
- *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_RAW    (BIT(9))
-#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
-#define I2C_TRANS_START_INT_RAW_V  0x00000001U
-#define I2C_TRANS_START_INT_RAW_S  9
-/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
- *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_RAW    (BIT(10))
-#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
-#define I2C_NACK_INT_RAW_V  0x00000001U
-#define I2C_NACK_INT_RAW_S  10
-/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
- *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
-#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_RAW_S  11
-/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
-#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_RAW_S  12
-/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
- *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
-#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
-#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_RAW_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
- *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
-/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
- *  The raw interrupt status of I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_RAW    (BIT(15))
-#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
-#define I2C_DET_START_INT_RAW_V  0x00000001U
-#define I2C_DET_START_INT_RAW_S  15
-/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
- *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
-#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_RAW_S  16
-/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
- *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
-#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
-#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_RAW_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0;
- *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M  (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S  18
-
-/** I2C_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
-/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
-#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
-#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_CLR_S  0
-/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
-#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
-#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_CLR_S  1
-/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
-#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_CLR_S  2
-/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_CLR    (BIT(3))
-#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
-#define I2C_END_DETECT_INT_CLR_V  0x00000001U
-#define I2C_END_DETECT_INT_CLR_S  3
-/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
-#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
-/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
-#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_CLR_S  5
-/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
-#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
-/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
-#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_CLR_S  7
-/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_CLR    (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
-#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
-#define I2C_TIME_OUT_INT_CLR_S  8
-/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_CLR    (BIT(9))
-#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
-#define I2C_TRANS_START_INT_CLR_V  0x00000001U
-#define I2C_TRANS_START_INT_CLR_S  9
-/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_CLR    (BIT(10))
-#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
-#define I2C_NACK_INT_CLR_V  0x00000001U
-#define I2C_NACK_INT_CLR_S  10
-/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
-#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_CLR_S  11
-/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
-#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_CLR_S  12
-/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
-#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
-#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_CLR_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
-/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Write 1 to clear I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_CLR    (BIT(15))
-#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
-#define I2C_DET_START_INT_CLR_V  0x00000001U
-#define I2C_DET_START_INT_CLR_S  15
-/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
-#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_CLR_S  16
-/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
-#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
-#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_CLR_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M  (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S  18
-
-/** I2C_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
-/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
-#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_ENA_S  0
-/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
-#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_ENA_S  1
-/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
-#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_ENA_S  2
-/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_ENA    (BIT(3))
-#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
-#define I2C_END_DETECT_INT_ENA_V  0x00000001U
-#define I2C_END_DETECT_INT_ENA_S  3
-/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
-#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
-/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
-#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_ENA_S  5
-/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
-#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
-/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
-#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_ENA_S  7
-/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_ENA    (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
-#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
-#define I2C_TIME_OUT_INT_ENA_S  8
-/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_ENA    (BIT(9))
-#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
-#define I2C_TRANS_START_INT_ENA_V  0x00000001U
-#define I2C_TRANS_START_INT_ENA_S  9
-/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_ENA    (BIT(10))
-#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
-#define I2C_NACK_INT_ENA_V  0x00000001U
-#define I2C_NACK_INT_ENA_S  10
-/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
-#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_ENA_S  11
-/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
-#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_ENA_S  12
-/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
-#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_ENA_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
-/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  Write 1 to enable I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_ENA    (BIT(15))
-#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
-#define I2C_DET_START_INT_ENA_V  0x00000001U
-#define I2C_DET_START_INT_ENA_S  15
-/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
-#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_ENA_S  16
-/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
-#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_ENA_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S  18
-
-/** I2C_INT_STATUS_REG register
- *  Status of captured I2C communication events
- */
-#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
-/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
-#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_ST_S  0
-/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
-#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_ST_S  1
-/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
-#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_ST_S  2
-/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_ST    (BIT(3))
-#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
-#define I2C_END_DETECT_INT_ST_V  0x00000001U
-#define I2C_END_DETECT_INT_ST_S  3
-/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
-#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
-/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
-#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_ST_S  5
-/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
-#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
-/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
-#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_ST_S  7
-/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_ST    (BIT(8))
-#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
-#define I2C_TIME_OUT_INT_ST_V  0x00000001U
-#define I2C_TIME_OUT_INT_ST_S  8
-/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_ST    (BIT(9))
-#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
-#define I2C_TRANS_START_INT_ST_V  0x00000001U
-#define I2C_TRANS_START_INT_ST_S  9
-/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_ST    (BIT(10))
-#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
-#define I2C_NACK_INT_ST_V  0x00000001U
-#define I2C_NACK_INT_ST_S  10
-/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
-#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_ST_S  11
-/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
-#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_ST_S  12
-/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
-#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_ST_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
- *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
-#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
-/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  The masked interrupt status status of I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_ST    (BIT(15))
-#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
-#define I2C_DET_START_INT_ST_V  0x00000001U
-#define I2C_DET_START_INT_ST_S  15
-/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
- *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
-#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_ST_S  16
-/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
- *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
-#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_ST_S  17
-/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0;
- *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
- */
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST    (BIT(18))
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S)
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V  0x00000001U
-#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S  18
-
-/** I2C_SDA_HOLD_REG register
- *  Configures the hold time after a negative SCL edge.
- */
-#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
-/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
- *  Configures the time to hold the data after the falling edge of SCL.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SDA_HOLD_TIME    0x000001FFU
-#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
-#define I2C_SDA_HOLD_TIME_V  0x000001FFU
-#define I2C_SDA_HOLD_TIME_S  0
-
-/** I2C_SDA_SAMPLE_REG register
- *  Configures the sample time after a positive SCL edge.
- */
-#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
-/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
- *  Configures the sample time after a positive SCL edge.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SDA_SAMPLE_TIME    0x000001FFU
-#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
-#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
-#define I2C_SDA_SAMPLE_TIME_S  0
-
-/** I2C_SCL_HIGH_PERIOD_REG register
- *  Configures the high level width of SCL
- */
-#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
-/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  Configures for how long SCL remains high in master mode.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_HIGH_PERIOD    0x000001FFU
-#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
-#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
-#define I2C_SCL_HIGH_PERIOD_S  0
-/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
- *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
-#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
-#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
-#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
-
-/** I2C_SCL_START_HOLD_REG register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
-/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the falling edge of SDA and the falling edge of SCL for
- *  a START condition.
- *  Measurement unit: i2c_sclk.
- */
-#define I2C_SCL_START_HOLD_TIME    0x000001FFU
-#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
-#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
-#define I2C_SCL_START_HOLD_TIME_S  0
-
-/** I2C_SCL_RSTART_SETUP_REG register
- *  Configures the delay between the positive edge of SCL and the negative edge of SDA
- */
-#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
-/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the positive edge of SCL and the negative edge of SDA
- *  for a RESTART condition.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
-#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
-#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
-#define I2C_SCL_RSTART_SETUP_TIME_S  0
-
-/** I2C_SCL_STOP_HOLD_REG register
- *  Configures the delay after the SCL clock edge for a stop condition
- */
-#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
-/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the delay after the STOP condition.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
-#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
-#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
-#define I2C_SCL_STOP_HOLD_TIME_S  0
-
-/** I2C_SCL_STOP_SETUP_REG register
- *  Configures the delay between the SDA and SCL rising edge for a stop condition.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
-/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the rising edge of SCL and the rising edge of SDA.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
-#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
-#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
-#define I2C_SCL_STOP_SETUP_TIME_S  0
-
-/** I2C_FILTER_CFG_REG register
- *  SCL and SDA filter configuration register
- */
-#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
-/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
- *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
- *  input has smaller width than this register value, the I2C controller will ignore
- *  that pulse.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_FILTER_THRES    0x0000000FU
-#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
-#define I2C_SCL_FILTER_THRES_V  0x0000000FU
-#define I2C_SCL_FILTER_THRES_S  0
-/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
- *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
- *  input has smaller width than this register value, the I2C controller will ignore
- *  that pulse.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SDA_FILTER_THRES    0x0000000FU
-#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
-#define I2C_SDA_FILTER_THRES_V  0x0000000FU
-#define I2C_SDA_FILTER_THRES_S  4
-/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
- *  Configures to enable the filter function for SCL.
- */
-#define I2C_SCL_FILTER_EN    (BIT(8))
-#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
-#define I2C_SCL_FILTER_EN_V  0x00000001U
-#define I2C_SCL_FILTER_EN_S  8
-/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
- *  Configures to enable the filter function for SDA.
- */
-#define I2C_SDA_FILTER_EN    (BIT(9))
-#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
-#define I2C_SDA_FILTER_EN_V  0x00000001U
-#define I2C_SDA_FILTER_EN_S  9
-
-/** I2C_COMD0_REG register
- *  I2C command register 0
- */
-#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
-/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 0. It consists of three parts:
- *  op_code is the command,
- *  0: RSTART,
- *  1: WRITE,
- *  2: READ,
- *  3: STOP,
- *  4: END.
- *
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more information.
- */
-#define I2C_COMMAND0    0x00003FFFU
-#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
-#define I2C_COMMAND0_V  0x00003FFFU
-#define I2C_COMMAND0_S  0
-/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 0 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND0_DONE    (BIT(31))
-#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
-#define I2C_COMMAND0_DONE_V  0x00000001U
-#define I2C_COMMAND0_DONE_S  31
-
-/** I2C_COMD1_REG register
- *  I2C command register 1
- */
-#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
-/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 1. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND1    0x00003FFFU
-#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
-#define I2C_COMMAND1_V  0x00003FFFU
-#define I2C_COMMAND1_S  0
-/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 1 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND1_DONE    (BIT(31))
-#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
-#define I2C_COMMAND1_DONE_V  0x00000001U
-#define I2C_COMMAND1_DONE_S  31
-
-/** I2C_COMD2_REG register
- *  I2C command register 2
- */
-#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
-/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 2. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND2    0x00003FFFU
-#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
-#define I2C_COMMAND2_V  0x00003FFFU
-#define I2C_COMMAND2_S  0
-/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 2 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND2_DONE    (BIT(31))
-#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
-#define I2C_COMMAND2_DONE_V  0x00000001U
-#define I2C_COMMAND2_DONE_S  31
-
-/** I2C_COMD3_REG register
- *  I2C command register 3
- */
-#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
-/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 3. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND3    0x00003FFFU
-#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
-#define I2C_COMMAND3_V  0x00003FFFU
-#define I2C_COMMAND3_S  0
-/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 3 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND3_DONE    (BIT(31))
-#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
-#define I2C_COMMAND3_DONE_V  0x00000001U
-#define I2C_COMMAND3_DONE_S  31
-
-/** I2C_COMD4_REG register
- *  I2C command register 4
- */
-#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
-/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 4. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND4    0x00003FFFU
-#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
-#define I2C_COMMAND4_V  0x00003FFFU
-#define I2C_COMMAND4_S  0
-/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 4 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND4_DONE    (BIT(31))
-#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
-#define I2C_COMMAND4_DONE_V  0x00000001U
-#define I2C_COMMAND4_DONE_S  31
-
-/** I2C_COMD5_REG register
- *  I2C command register 5
- */
-#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
-/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 5. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND5    0x00003FFFU
-#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
-#define I2C_COMMAND5_V  0x00003FFFU
-#define I2C_COMMAND5_S  0
-/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 5 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND5_DONE    (BIT(31))
-#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
-#define I2C_COMMAND5_DONE_V  0x00000001U
-#define I2C_COMMAND5_DONE_S  31
-
-/** I2C_COMD6_REG register
- *  I2C command register 6
- */
-#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
-/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 6. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND6    0x00003FFFU
-#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
-#define I2C_COMMAND6_V  0x00003FFFU
-#define I2C_COMMAND6_S  0
-/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 6 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND6_DONE    (BIT(31))
-#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
-#define I2C_COMMAND6_DONE_V  0x00000001U
-#define I2C_COMMAND6_DONE_S  31
-
-/** I2C_COMD7_REG register
- *  I2C command register 7
- */
-#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
-/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 7. See details in I2C_CMD0_REG[13:0].
- */
-#define I2C_COMMAND7    0x00003FFFU
-#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
-#define I2C_COMMAND7_V  0x00003FFFU
-#define I2C_COMMAND7_S  0
-/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 7 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define I2C_COMMAND7_DONE    (BIT(31))
-#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
-#define I2C_COMMAND7_DONE_V  0x00000001U
-#define I2C_COMMAND7_DONE_S  31
-
-/** I2C_SCL_ST_TIME_OUT_REG register
- *  SCL status time out register
- */
-#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
-/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
- *  more than 23.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_ST_TO_I2C    0x0000001FU
-#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
-#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
-#define I2C_SCL_ST_TO_I2C_S  0
-
-/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
- *  SCL main status time out register
- */
-#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
-/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
- *  no more than 23.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
-#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
-#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
-#define I2C_SCL_MAIN_ST_TO_I2C_S  0
-
-/** I2C_SCL_SP_CONF_REG register
- *  Power configuration register
- */
-#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
-/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
- *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
- *  equals to reg_scl_rst_slv_num[4:0].
- */
-#define I2C_SCL_RST_SLV_EN    (BIT(0))
-#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
-#define I2C_SCL_RST_SLV_EN_V  0x00000001U
-#define I2C_SCL_RST_SLV_EN_S  0
-/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
- *  Configure the pulses of SCL generated in I2C master mode.
- *  Valid when reg_scl_rst_slv_en is 1.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_SCL_RST_SLV_NUM    0x0000001FU
-#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
-#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
-#define I2C_SCL_RST_SLV_NUM_S  1
-/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
- *  Configures to power down the I2C output SCL line.
- *  0: Not power down.
- *
- *  1: Power down.
- *  Valid only when reg_scl_force_out is 1.
- */
-#define I2C_SCL_PD_EN    (BIT(6))
-#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
-#define I2C_SCL_PD_EN_V  0x00000001U
-#define I2C_SCL_PD_EN_S  6
-/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
- *  Configures to power down the I2C output SDA line.
- *  0: Not power down.
- *
- *  1: Power down.
- *  Valid only when reg_sda_force_out is 1.
- */
-#define I2C_SDA_PD_EN    (BIT(7))
-#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
-#define I2C_SDA_PD_EN_V  0x00000001U
-#define I2C_SDA_PD_EN_S  7
-
-/** I2C_SCL_STRETCH_CONF_REG register
- *  Set SCL stretch of I2C slave
- */
-#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
-/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
- *  Configures the time period to release the SCL line from stretching to avoid timing
- *  violation. Usually it should be larger than the SDA setup time.
- *  Measurement unit: i2c_sclk
- */
-#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
-#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
-#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
-#define I2C_STRETCH_PROTECT_NUM_S  0
-/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
- *  Configures to enable slave SCL stretch function.
- *  0: Disable
- *
- *  1: Enable
- *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
- *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
- */
-#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
-#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
-#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
-#define I2C_SLAVE_SCL_STRETCH_EN_S  10
-/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
- *  Configures to clear the I2C slave SCL stretch function.
- *  0: No effect
- *
- *  1: Clear
- */
-#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
-#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
-#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
-#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
-/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
- *  Configures to enable the function for slave to control ACK level.
- *  0: Disable
- *
- *  1: Enable
- */
-#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
-/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
- *  Set the ACK level when slave controlling ACK level function enables.
- *  0: Low level
- *
- *  1: High level
- */
-#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
-#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
-#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
-#define I2C_SLAVE_BYTE_ACK_LVL_S  13
-
-/** I2C_DATE_REG register
- *  Version register
- */
-#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
-/** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050;
- *  Version control register.
- */
-#define I2C_DATE    0xFFFFFFFFU
-#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
-#define I2C_DATE_V  0xFFFFFFFFU
-#define I2C_DATE_S  0
-
-/** I2C_TXFIFO_START_ADDR_REG register
- *  I2C TXFIFO base address register
- */
-#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
-/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Represents the I2C txfifo first address.
- */
-#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
-#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
-#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define I2C_TXFIFO_START_ADDR_S  0
-
-/** I2C_RXFIFO_START_ADDR_REG register
- *  I2C RXFIFO base address register
- */
-#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
-/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Represents the I2C rxfifo first address.
- */
-#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
-#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
-#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define I2C_RXFIFO_START_ADDR_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/i2c_struct.h b/components/soc/esp32c5/beta3/include/soc/i2c_struct.h
deleted file mode 100644
index 336bbfa073..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/i2c_struct.h
+++ /dev/null
@@ -1,1122 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Timing registers */
-/** Type of scl_low_period register
- *  Configures the low level width of the SCL Clock.
- */
-typedef union {
-    struct {
-        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the low level width of the SCL Clock.
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t scl_low_period:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_low_period_reg_t;
-
-/** Type of sda_hold register
- *  Configures the hold time after a negative SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the time to hold the data after the falling edge of SCL.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_sda_hold_reg_t;
-
-/** Type of sda_sample register
- *  Configures the sample time after a positive SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the sample time after a positive SCL edge.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_sample_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_sda_sample_reg_t;
-
-/** Type of scl_high_period register
- *  Configures the high level width of SCL
- */
-typedef union {
-    struct {
-        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
-         *  Configures for how long SCL remains high in master mode.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_high_period:9;
-        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
-         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_wait_high_period:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} i2c_scl_high_period_reg_t;
-
-/** Type of scl_start_hold register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-typedef union {
-    struct {
-        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
-         *  a START condition.
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t scl_start_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_start_hold_reg_t;
-
-/** Type of scl_rstart_setup register
- *  Configures the delay between the positive edge of SCL and the negative edge of SDA
- */
-typedef union {
-    struct {
-        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the positive edge of SCL and the negative edge of SDA
-         *  for a RESTART condition.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_rstart_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_rstart_setup_reg_t;
-
-/** Type of scl_stop_hold register
- *  Configures the delay after the SCL clock edge for a stop condition
- */
-typedef union {
-    struct {
-        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the delay after the STOP condition.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_stop_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_stop_hold_reg_t;
-
-/** Type of scl_stop_setup register
- *  Configures the delay between the SDA and SCL rising edge for a stop condition.
- *  Measurement unit: i2c_sclk
- */
-typedef union {
-    struct {
-        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the rising edge of SCL and the rising edge of SDA.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_stop_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_stop_setup_reg_t;
-
-/** Type of scl_st_time_out register
- *  SCL status time out register
- */
-typedef union {
-    struct {
-        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
-         *  more than 23.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} i2c_scl_st_time_out_reg_t;
-
-/** Type of scl_main_st_time_out register
- *  SCL main status time out register
- */
-typedef union {
-    struct {
-        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
-         *  no more than 23.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_main_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} i2c_scl_main_st_time_out_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of ctr register
- *  Transmission setting
- */
-typedef union {
-    struct {
-        /** sda_force_out : R/W; bitpos: [0]; default: 0;
-         *  Configures the SDA output mode
-         *  1: Direct output,
-         *
-         *  0: Open drain output.
-         */
-        uint32_t sda_force_out:1;
-        /** scl_force_out : R/W; bitpos: [1]; default: 0;
-         *  Configures the SCL output mode
-         *  1: Direct output,
-         *
-         *  0: Open drain output.
-         */
-        uint32_t scl_force_out:1;
-        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
-         *  Configures the sample mode for SDA.
-         *  1: Sample SDA data on the SCL low level.
-         *
-         *  0: Sample SDA data on the SCL high level.
-         */
-        uint32_t sample_scl_level:1;
-        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
-         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
-         *  reached the threshold.
-         */
-        uint32_t rx_full_ack_level:1;
-        /** ms_mode : R/W; bitpos: [4]; default: 0;
-         *  Configures the module as an I2C Master or Slave.
-         *  0: Slave
-         *
-         *  1: Master
-         */
-        uint32_t ms_mode:1;
-        /** trans_start : WT; bitpos: [5]; default: 0;
-         *  Configures to start sending the data in txfifo for slave.
-         *  0: No effect
-         *
-         *  1: Start
-         */
-        uint32_t trans_start:1;
-        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
-         *  Configures to control the sending order for data needing to be sent.
-         *  1: send data from the least significant bit,
-         *
-         *  0: send data from the most significant bit.
-         */
-        uint32_t tx_lsb_first:1;
-        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
-         *  Configures to control the storage order for received data.
-         *  1: receive data from the least significant bit
-         *
-         *  0: receive data from the most significant bit.
-         */
-        uint32_t rx_lsb_first:1;
-        /** clk_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether to gate clock signal for registers.
-         *
-         *  0: Force clock on for registers
-         *
-         *  1: Support clock only when registers are read or written to by software.
-         */
-        uint32_t clk_en:1;
-        /** arbitration_en : R/W; bitpos: [9]; default: 1;
-         *  Configures to enable I2C bus arbitration detection.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t arbitration_en:1;
-        /** fsm_rst : WT; bitpos: [10]; default: 0;
-         *  Configures to reset the SCL_FSM.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t fsm_rst:1;
-        /** conf_upgate : WT; bitpos: [11]; default: 0;
-         *  Configures this bit for synchronization
-         *  0: No effect
-         *
-         *  1: Synchronize
-         */
-        uint32_t conf_upgate:1;
-        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
-         *  Configures to enable slave to send data automatically
-         *  0: Disable
-         *
-         *  1: Enable
-         */
-        uint32_t slv_tx_auto_start_en:1;
-        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
-         *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
-         *  0: Not check
-         *
-         *  1: Check
-         */
-        uint32_t addr_10bit_rw_check_en:1;
-        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
-         *  Configures to support the 7bit general call function.
-         *  0: Not support
-         *
-         *  1: Support
-         */
-        uint32_t addr_broadcasting_en:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} i2c_ctr_reg_t;
-
-/** Type of to register
- *  Setting time out control for receiving data.
- */
-typedef union {
-    struct {
-        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the timeout threshold period for SCL stucking at high or low level. The
-         *  actual period is 2^(reg_time_out_value).
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t time_out_value:5;
-        /** time_out_en : R/W; bitpos: [5]; default: 0;
-         *  Configures to enable time out control.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t time_out_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} i2c_to_reg_t;
-
-/** Type of slave_addr register
- *  Local slave address setting
- */
-typedef union {
-    struct {
-        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
-         *  Configure the slave address of I2C Slave.
-         */
-        uint32_t slave_addr:15;
-        uint32_t reserved_15:16;
-        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
-         *  Configures to enable the slave 10-bit addressing mode in master mode.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t addr_10bit_en:1;
-    };
-    uint32_t val;
-} i2c_slave_addr_reg_t;
-
-/** Type of fifo_conf register
- *  FIFO configuration register.
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
-         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
-         *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t rxfifo_wm_thrhd:5;
-        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
-         *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
-         *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t txfifo_wm_thrhd:5;
-        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
-         *  Configures to enable APB nonfifo access.
-         */
-        uint32_t nonfifo_en:1;
-        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
-         *  Configures to enable double addressing mode. When this mode is enabled, the byte
-         *  received after the I2C address byte represents the offset address in the I2C Slave
-         *  RAM.
-         *  0: Disable
-         *
-         *  1: Enable
-         */
-        uint32_t fifo_addr_cfg_en:1;
-        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
-         *  Configures to reset RXFIFO.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t rx_fifo_rst:1;
-        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
-         *  Configures to reset TXFIFO.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t tx_fifo_rst:1;
-        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
-         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
-         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t fifo_prt_en:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} i2c_fifo_conf_reg_t;
-
-/** Type of filter_cfg register
- *  SCL and SDA filter configuration register
- */
-typedef union {
-    struct {
-        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
-         *  input has smaller width than this register value, the I2C controller will ignore
-         *  that pulse.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_filter_thres:4;
-        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
-         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
-         *  input has smaller width than this register value, the I2C controller will ignore
-         *  that pulse.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_filter_thres:4;
-        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
-         *  Configures to enable the filter function for SCL.
-         */
-        uint32_t scl_filter_en:1;
-        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
-         *  Configures to enable the filter function for SDA.
-         */
-        uint32_t sda_filter_en:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} i2c_filter_cfg_reg_t;
-
-/** Type of scl_sp_conf register
- *  Power configuration register
- */
-typedef union {
-    struct {
-        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
-         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
-         *  equals to reg_scl_rst_slv_num[4:0].
-         */
-        uint32_t scl_rst_slv_en:1;
-        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
-         *  Configure the pulses of SCL generated in I2C master mode.
-         *  Valid when reg_scl_rst_slv_en is 1.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_rst_slv_num:5;
-        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
-         *  Configures to power down the I2C output SCL line.
-         *  0: Not power down.
-         *
-         *  1: Power down.
-         *  Valid only when reg_scl_force_out is 1.
-         */
-        uint32_t scl_pd_en:1;
-        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
-         *  Configures to power down the I2C output SDA line.
-         *  0: Not power down.
-         *
-         *  1: Power down.
-         *  Valid only when reg_sda_force_out is 1.
-         */
-        uint32_t sda_pd_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} i2c_scl_sp_conf_reg_t;
-
-/** Type of scl_stretch_conf register
- *  Set SCL stretch of I2C slave
- */
-typedef union {
-    struct {
-        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
-         *  Configures the time period to release the SCL line from stretching to avoid timing
-         *  violation. Usually it should be larger than the SDA setup time.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t stretch_protect_num:10;
-        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
-         *  Configures to enable slave SCL stretch function.
-         *  0: Disable
-         *
-         *  1: Enable
-         *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
-         *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
-         */
-        uint32_t slave_scl_stretch_en:1;
-        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
-         *  Configures to clear the I2C slave SCL stretch function.
-         *  0: No effect
-         *
-         *  1: Clear
-         */
-        uint32_t slave_scl_stretch_clr:1;
-        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
-         *  Configures to enable the function for slave to control ACK level.
-         *  0: Disable
-         *
-         *  1: Enable
-         */
-        uint32_t slave_byte_ack_ctl_en:1;
-        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
-         *  Set the ACK level when slave controlling ACK level function enables.
-         *  0: Low level
-         *
-         *  1: High level
-         */
-        uint32_t slave_byte_ack_lvl:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} i2c_scl_stretch_conf_reg_t;
-
-
-/** Group: Status registers */
-/** Type of sr register
- *  Describe I2C work status.
- */
-typedef union {
-    struct {
-        /** resp_rec : RO; bitpos: [0]; default: 0;
-         *  Represents the received ACK value in master mode or slave mode.
-         *  0: ACK,
-         *
-         *  1: NACK.
-         */
-        uint32_t resp_rec:1;
-        /** slave_rw : RO; bitpos: [1]; default: 0;
-         *  Represents the transfer direction in slave mode,.
-         *  1: Master reads from slave,
-         *
-         *  0: Master writes to slave.
-         */
-        uint32_t slave_rw:1;
-        uint32_t reserved_2:1;
-        /** arb_lost : RO; bitpos: [3]; default: 0;
-         *  Represents whether the I2C controller loses control of SCL line.
-         *  0: No arbitration lost
-         *
-         *  1: Arbitration lost
-         */
-        uint32_t arb_lost:1;
-        /** bus_busy : RO; bitpos: [4]; default: 0;
-         *  Represents the I2C bus state.
-         *  1: The I2C bus is busy transferring data,
-         *
-         *  0: The I2C bus is in idle state.
-         */
-        uint32_t bus_busy:1;
-        /** slave_addressed : RO; bitpos: [5]; default: 0;
-         *  Represents whether the address sent by the master is equal to the address of the
-         *  slave.
-         *  Valid only when the module is configured as an I2C Slave.
-         *  0: Not equal
-         *
-         *  1: Equal
-         */
-        uint32_t slave_addressed:1;
-        uint32_t reserved_6:2;
-        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
-         *  Represents the number of data bytes to be sent.
-         */
-        uint32_t rxfifo_cnt:6;
-        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
-         *  Represents the cause of SCL clocking stretching in slave mode.
-         *  0: Stretching SCL low when the master starts to read data.
-         *
-         *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
-         *
-         *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
-         */
-        uint32_t stretch_cause:2;
-        uint32_t reserved_16:2;
-        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
-         *  Represents the number of data bytes received in RAM.
-         */
-        uint32_t txfifo_cnt:6;
-        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
-         *  Represents the states of the I2C module state machine.
-         *  0: Idle,
-         *
-         *  1: Address shift,
-         *
-         *  2: ACK address,
-         *
-         *  3: Rx data,
-         *
-         *  4: Tx data,
-         *
-         *  5: Send ACK,
-         *
-         *  6: Wait ACK
-         */
-        uint32_t scl_main_state_last:3;
-        uint32_t reserved_27:1;
-        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
-         *  Represents the states of the state machine used to produce SCL.
-         *  0: Idle,
-         *
-         *  1: Start,
-         *
-         *  2: Negative edge,
-         *
-         *  3: Low,
-         *
-         *  4: Positive edge,
-         *
-         *  5: High,
-         *
-         *  6: Stop
-         */
-        uint32_t scl_state_last:3;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2c_sr_reg_t;
-
-/** Type of fifo_st register
- *  FIFO status register.
- */
-typedef union {
-    struct {
-        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
-         *  Represents the offset address of the APB reading from RXFIFO
-         */
-        uint32_t rxfifo_raddr:5;
-        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
-         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
-         */
-        uint32_t rxfifo_waddr:5;
-        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
-         *  Represents the offset address of i2c module reading from TXFIFO.
-         */
-        uint32_t txfifo_raddr:5;
-        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
-         *  Represents the offset address of APB bus writing to TXFIFO.
-         */
-        uint32_t txfifo_waddr:5;
-        uint32_t reserved_20:2;
-        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
-         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
-         *  I2C slave mode.
-         */
-        uint32_t slave_rw_point:8;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2c_fifo_st_reg_t;
-
-/** Type of data register
- *  Rx FIFO read data.
- */
-typedef union {
-    struct {
-        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
-         *  Represents the value of RXFIFO read data.
-         */
-        uint32_t fifo_rdata:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} i2c_data_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_raw:1;
-        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
-         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
-         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_raw:1;
-        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
-         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_raw:1;
-        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
-         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_raw:1;
-        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
-         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_raw:1;
-        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
-         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_raw:1;
-        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
-         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_raw:1;
-        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
-         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_raw:1;
-        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
-         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_raw:1;
-        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
-         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_raw:1;
-        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_raw:1;
-        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
-         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_raw:1;
-        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
-         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_raw:1;
-        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
-         *  The raw interrupt status of I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_raw:1;
-        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
-         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_raw:1;
-        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
-         *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_raw:1;
-        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
-         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_raw:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_raw_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_clr:1;
-        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_clr:1;
-        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_clr:1;
-        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_clr:1;
-        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_clr:1;
-        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_clr:1;
-        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_clr:1;
-        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_clr:1;
-        /** nack_int_clr : WT; bitpos: [10]; default: 0;
-         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_clr:1;
-        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_clr:1;
-        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_clr:1;
-        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
-         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_clr:1;
-        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
-         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_clr:1;
-        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  Write 1 to clear I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_clr:1;
-        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
-         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_clr:1;
-        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
-         *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_clr:1;
-        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
-         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_clr:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_clr_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_ena:1;
-        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_ena:1;
-        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_ena:1;
-        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_ena:1;
-        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_ena:1;
-        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_ena:1;
-        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_ena:1;
-        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_ena:1;
-        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_ena:1;
-        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_ena:1;
-        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_ena:1;
-        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_ena:1;
-        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_ena:1;
-        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Write 1 to enable I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_ena:1;
-        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_ena:1;
-        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_ena:1;
-        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
-         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_ena:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_ena_reg_t;
-
-/** Type of int_status register
- *  Status of captured I2C communication events
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_st:1;
-        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_st:1;
-        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_st:1;
-        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_st:1;
-        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_st:1;
-        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_st:1;
-        /** time_out_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_st:1;
-        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_st:1;
-        /** nack_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_st:1;
-        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_st:1;
-        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_st:1;
-        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_st:1;
-        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_st:1;
-        /** det_start_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_st:1;
-        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_st:1;
-        /** general_call_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_st:1;
-        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
-         *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
-         */
-        uint32_t slave_addr_unmatch_int_st:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} i2c_int_status_reg_t;
-
-
-/** Group: Command registers */
-/** Type of comd register
- *  I2C command register n
- */
-typedef union {
-    struct {
-        /** command0 : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 0. It consists of three parts:
-         *  op_code is the command,
-         *  0: RSTART,
-         *  1: WRITE,
-         *  2: READ,
-         *  3: STOP,
-         *  4: END.
-         *
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more information.
-         */
-        uint32_t command:14;
-        uint32_t reserved_14:17;
-        /** command_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command 0 is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command_done:1;
-    };
-    uint32_t val;
-} i2c_comd_reg_t;
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35656050;
-         *  Version control register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} i2c_date_reg_t;
-
-
-/** Group: Address register */
-/** Type of txfifo_start_addr register
- *  I2C TXFIFO base address register
- */
-typedef union {
-    struct {
-        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Represents the I2C txfifo first address.
-         */
-        uint32_t txfifo_start_addr:32;
-    };
-    uint32_t val;
-} i2c_txfifo_start_addr_reg_t;
-
-/** Type of rxfifo_start_addr register
- *  I2C RXFIFO base address register
- */
-typedef union {
-    struct {
-        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Represents the I2C rxfifo first address.
-         */
-        uint32_t rxfifo_start_addr:32;
-    };
-    uint32_t val;
-} i2c_rxfifo_start_addr_reg_t;
-
-
-typedef struct i2c_dev_t {
-    volatile i2c_scl_low_period_reg_t scl_low_period;
-    volatile i2c_ctr_reg_t ctr;
-    volatile i2c_sr_reg_t sr;
-    volatile i2c_to_reg_t to;
-    volatile i2c_slave_addr_reg_t slave_addr;
-    volatile i2c_fifo_st_reg_t fifo_st;
-    volatile i2c_fifo_conf_reg_t fifo_conf;
-    volatile i2c_data_reg_t data;
-    volatile i2c_int_raw_reg_t int_raw;
-    volatile i2c_int_clr_reg_t int_clr;
-    volatile i2c_int_ena_reg_t int_ena;
-    volatile i2c_int_status_reg_t int_status;
-    volatile i2c_sda_hold_reg_t sda_hold;
-    volatile i2c_sda_sample_reg_t sda_sample;
-    volatile i2c_scl_high_period_reg_t scl_high_period;
-    uint32_t reserved_03c;
-    volatile i2c_scl_start_hold_reg_t scl_start_hold;
-    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
-    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
-    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
-    volatile i2c_filter_cfg_reg_t filter_cfg;
-    uint32_t reserved_054;
-    volatile i2c_comd_reg_t command[8];
-    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
-    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
-    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
-    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
-    uint32_t reserved_088[28];
-    volatile i2c_date_reg_t date;
-    uint32_t reserved_0fc;
-    volatile uint32_t txfifo_mem[32];
-    volatile uint32_t rxfifo_mem[32];
-} i2c_dev_t;
-
-extern i2c_dev_t I2C0;
-extern i2c_dev_t I2C1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/i2s_reg.h b/components/soc/esp32c5/beta3/include/soc/i2s_reg.h
deleted file mode 100644
index 21d7c89692..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/i2s_reg.h
+++ /dev/null
@@ -1,1268 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2S_INT_RAW_REG register
- *  I2S interrupt raw register, valid in level.
- */
-#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
-/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_RAW    (BIT(0))
-#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
-#define I2S_RX_DONE_INT_RAW_V  0x00000001U
-#define I2S_RX_DONE_INT_RAW_S  0
-/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_RAW    (BIT(1))
-#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
-#define I2S_TX_DONE_INT_RAW_V  0x00000001U
-#define I2S_TX_DONE_INT_RAW_S  1
-/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_RAW    (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
-#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_RX_HUNG_INT_RAW_S  2
-/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_RAW    (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
-#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_TX_HUNG_INT_RAW_S  3
-
-/** I2S_INT_ST_REG register
- *  I2S interrupt status register.
- */
-#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
-/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ST    (BIT(0))
-#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
-#define I2S_RX_DONE_INT_ST_V  0x00000001U
-#define I2S_RX_DONE_INT_ST_S  0
-/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ST    (BIT(1))
-#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
-#define I2S_TX_DONE_INT_ST_V  0x00000001U
-#define I2S_TX_DONE_INT_ST_S  1
-/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ST    (BIT(2))
-#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
-#define I2S_RX_HUNG_INT_ST_V  0x00000001U
-#define I2S_RX_HUNG_INT_ST_S  2
-/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ST    (BIT(3))
-#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
-#define I2S_TX_HUNG_INT_ST_V  0x00000001U
-#define I2S_TX_HUNG_INT_ST_S  3
-
-/** I2S_INT_ENA_REG register
- *  I2S interrupt enable register.
- */
-#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
-/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ENA    (BIT(0))
-#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
-#define I2S_RX_DONE_INT_ENA_V  0x00000001U
-#define I2S_RX_DONE_INT_ENA_S  0
-/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ENA    (BIT(1))
-#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
-#define I2S_TX_DONE_INT_ENA_V  0x00000001U
-#define I2S_TX_DONE_INT_ENA_S  1
-/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ENA    (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
-#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_RX_HUNG_INT_ENA_S  2
-/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ENA    (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
-#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_TX_HUNG_INT_ENA_S  3
-
-/** I2S_INT_CLR_REG register
- *  I2S interrupt clear register.
- */
-#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
-/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_CLR    (BIT(0))
-#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
-#define I2S_RX_DONE_INT_CLR_V  0x00000001U
-#define I2S_RX_DONE_INT_CLR_S  0
-/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_CLR    (BIT(1))
-#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
-#define I2S_TX_DONE_INT_CLR_V  0x00000001U
-#define I2S_TX_DONE_INT_CLR_S  1
-/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_CLR    (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
-#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_RX_HUNG_INT_CLR_S  2
-/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_CLR    (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
-#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_TX_HUNG_INT_CLR_S  3
-
-/** I2S_RX_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
-/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset receiver
- */
-#define I2S_RX_RESET    (BIT(0))
-#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
-#define I2S_RX_RESET_V  0x00000001U
-#define I2S_RX_RESET_S  0
-/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Rx AFIFO
- */
-#define I2S_RX_FIFO_RESET    (BIT(1))
-#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
-#define I2S_RX_FIFO_RESET_V  0x00000001U
-#define I2S_RX_FIFO_RESET_S  1
-/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start receiving data
- */
-#define I2S_RX_START    (BIT(2))
-#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
-#define I2S_RX_START_V  0x00000001U
-#define I2S_RX_START_S  2
-/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave receiver mode
- */
-#define I2S_RX_SLAVE_MOD    (BIT(3))
-#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
-#define I2S_RX_SLAVE_MOD_V  0x00000001U
-#define I2S_RX_SLAVE_MOD_S  3
-/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
- *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
- *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
- */
-#define I2S_RX_STOP_MODE    0x00000003U
-#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
-#define I2S_RX_STOP_MODE_V  0x00000003U
-#define I2S_RX_STOP_MODE_S  4
-/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable receiver  in mono mode
- */
-#define I2S_RX_MONO    (BIT(6))
-#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
-#define I2S_RX_MONO_V  0x00000001U
-#define I2S_RX_MONO_S  6
-/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
- */
-#define I2S_RX_BIG_ENDIAN    (BIT(7))
-#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
-#define I2S_RX_BIG_ENDIAN_V  0x00000001U
-#define I2S_RX_BIG_ENDIAN_S  7
-/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_RX_UPDATE    (BIT(8))
-#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
-#define I2S_RX_UPDATE_V  0x00000001U
-#define I2S_RX_UPDATE_S  8
-/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
- *  channel data value is valid in I2S RX mono mode.
- */
-#define I2S_RX_MONO_FST_VLD    (BIT(9))
-#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
-#define I2S_RX_MONO_FST_VLD_V  0x00000001U
-#define I2S_RX_MONO_FST_VLD_S  9
-/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
- *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_RX_PCM_CONF    0x00000003U
-#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
-#define I2S_RX_PCM_CONF_V  0x00000003U
-#define I2S_RX_PCM_CONF_S  10
-/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass Compress/Decompress module for received data.
- */
-#define I2S_RX_PCM_BYPASS    (BIT(12))
-#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
-#define I2S_RX_PCM_BYPASS_V  0x00000001U
-#define I2S_RX_PCM_BYPASS_S  12
-/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable receiver in Phillips standard mode
- */
-#define I2S_RX_MSB_SHIFT    (BIT(13))
-#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
-#define I2S_RX_MSB_SHIFT_V  0x00000001U
-#define I2S_RX_MSB_SHIFT_S  13
-/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
- */
-#define I2S_RX_LEFT_ALIGN    (BIT(15))
-#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
-#define I2S_RX_LEFT_ALIGN_V  0x00000001U
-#define I2S_RX_LEFT_ALIGN_S  15
-/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
- */
-#define I2S_RX_24_FILL_EN    (BIT(16))
-#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
-#define I2S_RX_24_FILL_EN_V  0x00000001U
-#define I2S_RX_24_FILL_EN_S  16
-/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
- *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
- */
-#define I2S_RX_WS_IDLE_POL    (BIT(17))
-#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
-#define I2S_RX_WS_IDLE_POL_V  0x00000001U
-#define I2S_RX_WS_IDLE_POL_S  17
-/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
- *  is received first.
- */
-#define I2S_RX_BIT_ORDER    (BIT(18))
-#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
-#define I2S_RX_BIT_ORDER_V  0x00000001U
-#define I2S_RX_BIT_ORDER_S  18
-/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Rx mode . 0: Disable.
- */
-#define I2S_RX_TDM_EN    (BIT(19))
-#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
-#define I2S_RX_TDM_EN_V  0x00000001U
-#define I2S_RX_TDM_EN_S  19
-/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Rx mode . 0: Disable.
- */
-#define I2S_RX_PDM_EN    (BIT(20))
-#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
-#define I2S_RX_PDM_EN_V  0x00000001U
-#define I2S_RX_PDM_EN_S  20
-/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in receiver mode.
- */
-#define I2S_RX_BCK_DIV_NUM    0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
-#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_S  21
-
-/** I2S_TX_CONF_REG register
- *  I2S TX configure register
- */
-#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
-/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset transmitter
- */
-#define I2S_TX_RESET    (BIT(0))
-#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
-#define I2S_TX_RESET_V  0x00000001U
-#define I2S_TX_RESET_S  0
-/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Tx AFIFO
- */
-#define I2S_TX_FIFO_RESET    (BIT(1))
-#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
-#define I2S_TX_FIFO_RESET_V  0x00000001U
-#define I2S_TX_FIFO_RESET_S  1
-/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start transmitting data
- */
-#define I2S_TX_START    (BIT(2))
-#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
-#define I2S_TX_START_V  0x00000001U
-#define I2S_TX_START_S  2
-/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave transmitter mode
- */
-#define I2S_TX_SLAVE_MOD    (BIT(3))
-#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
-#define I2S_TX_SLAVE_MOD_V  0x00000001U
-#define I2S_TX_SLAVE_MOD_S  3
-/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
- */
-#define I2S_TX_STOP_EN    (BIT(4))
-#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
-#define I2S_TX_STOP_EN_V  0x00000001U
-#define I2S_TX_STOP_EN_S  4
-/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
- *  1: The value of Left channel data is equal to the value of right channel data in
- *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
- *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
- */
-#define I2S_TX_CHAN_EQUAL    (BIT(5))
-#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
-#define I2S_TX_CHAN_EQUAL_V  0x00000001U
-#define I2S_TX_CHAN_EQUAL_S  5
-/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable transmitter in mono mode
- */
-#define I2S_TX_MONO    (BIT(6))
-#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
-#define I2S_TX_MONO_V  0x00000001U
-#define I2S_TX_MONO_S  6
-/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
- *  value.
- */
-#define I2S_TX_BIG_ENDIAN    (BIT(7))
-#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
-#define I2S_TX_BIG_ENDIAN_V  0x00000001U
-#define I2S_TX_BIG_ENDIAN_S  7
-/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_TX_UPDATE    (BIT(8))
-#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
-#define I2S_TX_UPDATE_V  0x00000001U
-#define I2S_TX_UPDATE_S  8
-/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
- *  channel data value is valid in I2S TX mono mode.
- */
-#define I2S_TX_MONO_FST_VLD    (BIT(9))
-#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
-#define I2S_TX_MONO_FST_VLD_V  0x00000001U
-#define I2S_TX_MONO_FST_VLD_S  9
-/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
- *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_TX_PCM_CONF    0x00000003U
-#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
-#define I2S_TX_PCM_CONF_V  0x00000003U
-#define I2S_TX_PCM_CONF_S  10
-/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass  Compress/Decompress module for transmitted data.
- */
-#define I2S_TX_PCM_BYPASS    (BIT(12))
-#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
-#define I2S_TX_PCM_BYPASS_V  0x00000001U
-#define I2S_TX_PCM_BYPASS_S  12
-/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable transmitter in Phillips standard mode
- */
-#define I2S_TX_MSB_SHIFT    (BIT(13))
-#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
-#define I2S_TX_MSB_SHIFT_V  0x00000001U
-#define I2S_TX_MSB_SHIFT_S  13
-/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
- *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
- *  generate pos/neg edge in master mode.
- */
-#define I2S_TX_BCK_NO_DLY    (BIT(14))
-#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
-#define I2S_TX_BCK_NO_DLY_V  0x00000001U
-#define I2S_TX_BCK_NO_DLY_S  14
-/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
- */
-#define I2S_TX_LEFT_ALIGN    (BIT(15))
-#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
-#define I2S_TX_LEFT_ALIGN_V  0x00000001U
-#define I2S_TX_LEFT_ALIGN_S  15
-/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
- */
-#define I2S_TX_24_FILL_EN    (BIT(16))
-#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
-#define I2S_TX_24_FILL_EN_V  0x00000001U
-#define I2S_TX_24_FILL_EN_S  16
-/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
- *  WS should be 1 when sending left channel data, and WS is 0in right channel.
- */
-#define I2S_TX_WS_IDLE_POL    (BIT(17))
-#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
-#define I2S_TX_WS_IDLE_POL_V  0x00000001U
-#define I2S_TX_WS_IDLE_POL_S  17
-/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
- *  sent first.
- */
-#define I2S_TX_BIT_ORDER    (BIT(18))
-#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
-#define I2S_TX_BIT_ORDER_V  0x00000001U
-#define I2S_TX_BIT_ORDER_S  18
-/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Tx mode . 0: Disable.
- */
-#define I2S_TX_TDM_EN    (BIT(19))
-#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
-#define I2S_TX_TDM_EN_V  0x00000001U
-#define I2S_TX_TDM_EN_S  19
-/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Tx mode . 0: Disable.
- */
-#define I2S_TX_PDM_EN    (BIT(20))
-#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
-#define I2S_TX_PDM_EN_V  0x00000001U
-#define I2S_TX_PDM_EN_S  20
-/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in transmitter mode.
- */
-#define I2S_TX_BCK_DIV_NUM    0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
-#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_S  21
-/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
- *  I2S transmitter channel mode configuration bits.
- */
-#define I2S_TX_CHAN_MOD    0x00000007U
-#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
-#define I2S_TX_CHAN_MOD_V  0x00000007U
-#define I2S_TX_CHAN_MOD_S  27
-/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
- *  Enable signal loop back mode with transmitter module and receiver module sharing
- *  the same WS and BCK signals.
- */
-#define I2S_SIG_LOOPBACK    (BIT(30))
-#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
-#define I2S_SIG_LOOPBACK_V  0x00000001U
-#define I2S_SIG_LOOPBACK_S  30
-
-/** I2S_RX_CONF1_REG register
- *  I2S RX configure register 1
- */
-#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
-/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
-#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_S  0
-/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
- *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_RX_BITS_MOD    0x0000001FU
-#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
-#define I2S_RX_BITS_MOD_V  0x0000001FU
-#define I2S_RX_BITS_MOD_S  14
-/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Rx half sample bits -1.
- */
-#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
-#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_S  19
-/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Rx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
-#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_S  27
-
-/** I2S_TX_CONF1_REG register
- *  I2S TX configure register 1
- */
-#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
-/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
-#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_S  0
-/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
- *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_TX_BITS_MOD    0x0000001FU
-#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
-#define I2S_TX_BITS_MOD_V  0x0000001FU
-#define I2S_TX_BITS_MOD_S  14
-/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Tx half sample bits -1.
- */
-#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
-#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_S  19
-/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Tx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
-#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_S  27
-
-/** I2S_TX_PCM2PDM_CONF_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40)
-/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
- *  I2S TX PDM OSR2 value
- */
-#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
-#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_S  1
-/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
- *  I2S TX PDM prescale for sigmadelta
- */
-#define I2S_TX_PDM_PRESCALE    0x000000FFU
-#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
-#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
-#define I2S_TX_PDM_PRESCALE_S  5
-/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_S  13
-/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_S  15
-/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
-/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
-/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
- *  I2S TX PDM sigmadelta dither2 value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
-/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
- *  I2S TX PDM sigmadelta dither value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
-/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
- *  I2S TX PDM dac mode enable
- */
-#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
-#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_2OUT_EN_S  23
-/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
- *  I2S TX PDM dac 2channel enable
- */
-#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
-#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_MODE_EN_S  24
-/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
- *  I2S TX PDM Converter enable
- */
-#define I2S_PCM2PDM_CONV_EN    (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
-#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
-#define I2S_PCM2PDM_CONV_EN_S  25
-
-/** I2S_TX_PCM2PDM_CONF1_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44)
-/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
- *  I2S TX PDM Fp
- */
-#define I2S_TX_PDM_FP    0x000003FFU
-#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
-#define I2S_TX_PDM_FP_V  0x000003FFU
-#define I2S_TX_PDM_FP_S  0
-/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
- *  I2S TX PDM Fs
- */
-#define I2S_TX_PDM_FS    0x000003FFU
-#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
-#define I2S_TX_PDM_FS_V  0x000003FFU
-#define I2S_TX_PDM_FS_S  10
-/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
- *  I2S_TX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
-#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_S  20
-/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
- *  I2S_TX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
-#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_S  23
-
-/** I2S_RX_PDM2PCM_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48)
-/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable PDM2PCM RX mode. 0: DIsable.
- */
-#define I2S_RX_PDM2PCM_EN    (BIT(19))
-#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
-#define I2S_RX_PDM2PCM_EN_V  0x00000001U
-#define I2S_RX_PDM2PCM_EN_S  19
-/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
- *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
- *  sampling rate is 128. 0: down sampling rate is 64.
- */
-#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
-#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
-#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
-#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
-/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
- *  Configure PDM RX amplify number.
- */
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
-/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
- *  I2S PDM RX bypass hp filter or not.
- */
-#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
-#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
-#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
-#define I2S_RX_PDM_HP_BYPASS_S  25
-/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
- *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
- *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_RX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_RX_IIR_HP_MULT12_5_M  (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
-#define I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_RX_IIR_HP_MULT12_5_S  26
-/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
- *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
- *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_RX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_RX_IIR_HP_MULT12_0_M  (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
-#define I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_RX_IIR_HP_MULT12_0_S  29
-
-/** I2S_RX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
-/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
-#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
-/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
-#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
-/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
-#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
-/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
-#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
-/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
-#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
-/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
-#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
-/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
-#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
-/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
-#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
-/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
-#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN8_EN_S  8
-/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
-#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN9_EN_S  9
-/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
-#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN10_EN_S  10
-/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
-#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN11_EN_S  11
-/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
-#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN12_EN_S  12
-/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
-#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN13_EN_S  13
-/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
-#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN14_EN_S  14
-/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
-#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN15_EN_S  15
-/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
-#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
-
-/** I2S_TX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
-/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
-#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN0_EN_S  0
-/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
-#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN1_EN_S  1
-/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
-#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN2_EN_S  2
-/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
-#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN3_EN_S  3
-/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
-#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN4_EN_S  4
-/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
-#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN5_EN_S  5
-/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
-#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN6_EN_S  6
-/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
-#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN7_EN_S  7
-/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
-#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN8_EN_S  8
-/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
-#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN9_EN_S  9
-/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
-#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN10_EN_S  10
-/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
-#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN11_EN_S  11
-/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
-#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN12_EN_S  12
-/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
-#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN13_EN_S  13
-/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
-#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN14_EN_S  14
-/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
-#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN15_EN_S  15
-/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
-#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
-/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
- *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
- *  only the data of the enabled channels is sent, then this bit should be set. Clear
- *  it when all the data stored in DMA TX buffer is for enabled channels.
- */
-#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
-#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
-#define I2S_TX_TDM_SKIP_MSK_EN_S  20
-
-/** I2S_RX_TIMING_REG register
- *  I2S RX timing control register
- */
-#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
-/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD_IN_DM    0x00000003U
-#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
-#define I2S_RX_SD_IN_DM_V  0x00000003U
-#define I2S_RX_SD_IN_DM_S  0
-/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD1_IN_DM    0x00000003U
-#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
-#define I2S_RX_SD1_IN_DM_V  0x00000003U
-#define I2S_RX_SD1_IN_DM_S  4
-/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
- *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD2_IN_DM    0x00000003U
-#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
-#define I2S_RX_SD2_IN_DM_V  0x00000003U
-#define I2S_RX_SD2_IN_DM_S  8
-/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
- *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD3_IN_DM    0x00000003U
-#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
-#define I2S_RX_SD3_IN_DM_V  0x00000003U
-#define I2S_RX_SD3_IN_DM_S  12
-/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_OUT_DM    0x00000003U
-#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
-#define I2S_RX_WS_OUT_DM_V  0x00000003U
-#define I2S_RX_WS_OUT_DM_S  16
-/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_OUT_DM    0x00000003U
-#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
-#define I2S_RX_BCK_OUT_DM_V  0x00000003U
-#define I2S_RX_BCK_OUT_DM_S  20
-/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_IN_DM    0x00000003U
-#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
-#define I2S_RX_WS_IN_DM_V  0x00000003U
-#define I2S_RX_WS_IN_DM_S  24
-/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_IN_DM    0x00000003U
-#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
-#define I2S_RX_BCK_IN_DM_V  0x00000003U
-#define I2S_RX_BCK_IN_DM_S  28
-
-/** I2S_TX_TIMING_REG register
- *  I2S TX timing control register
- */
-#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
-/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD_OUT_DM    0x00000003U
-#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
-#define I2S_TX_SD_OUT_DM_V  0x00000003U
-#define I2S_TX_SD_OUT_DM_S  0
-/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD1_OUT_DM    0x00000003U
-#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
-#define I2S_TX_SD1_OUT_DM_V  0x00000003U
-#define I2S_TX_SD1_OUT_DM_S  4
-/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_OUT_DM    0x00000003U
-#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
-#define I2S_TX_WS_OUT_DM_V  0x00000003U
-#define I2S_TX_WS_OUT_DM_S  16
-/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_OUT_DM    0x00000003U
-#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
-#define I2S_TX_BCK_OUT_DM_V  0x00000003U
-#define I2S_TX_BCK_OUT_DM_S  20
-/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_IN_DM    0x00000003U
-#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
-#define I2S_TX_WS_IN_DM_V  0x00000003U
-#define I2S_TX_WS_IN_DM_S  24
-/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_IN_DM    0x00000003U
-#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
-#define I2S_TX_BCK_IN_DM_V  0x00000003U
-#define I2S_TX_BCK_IN_DM_S  28
-
-/** I2S_LC_HUNG_CONF_REG register
- *  I2S HUNG configure register.
- */
-#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
-/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
- *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
- *  when fifo hung counter is equal to this value
- */
-#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
-#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_S  0
-/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
- *  The bits are used to scale tick counter threshold. The tick counter is reset when
- *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
- */
-#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
- *  The enable bit for FIFO timeout
- */
-#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-
-/** I2S_RXEOF_NUM_REG register
- *  I2S RX data number control register.
- */
-#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
-/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
- *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
- *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
- */
-#define I2S_RX_EOF_NUM    0x00000FFFU
-#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
-#define I2S_RX_EOF_NUM_V  0x00000FFFU
-#define I2S_RX_EOF_NUM_S  0
-
-/** I2S_CONF_SIGLE_DATA_REG register
- *  I2S signal data register
- */
-#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
-/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The configured constant channel data to be sent out.
- */
-#define I2S_SINGLE_DATA    0xFFFFFFFFU
-#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
-#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
-#define I2S_SINGLE_DATA_S  0
-
-/** I2S_STATE_REG register
- *  I2S TX status register
- */
-#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
-/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
- *  1: i2s_tx is idle state. 0: i2s_tx is working.
- */
-#define I2S_TX_IDLE    (BIT(0))
-#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
-#define I2S_TX_IDLE_V  0x00000001U
-#define I2S_TX_IDLE_S  0
-
-/** I2S_ETM_CONF_REG register
- *  I2S ETM configure register
- */
-#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
-/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
- *  I2S ETM send x words event. When sending word number of
- *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
-#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_S  0
-/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
- *  I2S ETM receive x words event. When receiving word number of
- *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
-
-/** I2S_FIFO_CNT_REG register
- *  I2S sync counter register
- */
-#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x74)
-/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
- *  tx fifo counter value.
- */
-#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
-#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
-#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
-#define I2S_TX_FIFO_CNT_S  0
-/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset tx fifo counter.
- */
-#define I2S_TX_FIFO_CNT_RST    (BIT(31))
-#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
-#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
-#define I2S_TX_FIFO_CNT_RST_S  31
-
-/** I2S_BCK_CNT_REG register
- *  I2S sync counter register
- */
-#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x78)
-/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
- *  tx bck counter value.
- */
-#define I2S_TX_BCK_CNT    0x7FFFFFFFU
-#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
-#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
-#define I2S_TX_BCK_CNT_S  0
-/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset tx bck counter.
- */
-#define I2S_TX_BCK_CNT_RST    (BIT(31))
-#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
-#define I2S_TX_BCK_CNT_RST_V  0x00000001U
-#define I2S_TX_BCK_CNT_RST_S  31
-
-/** I2S_CLK_GATE_REG register
- *  Clock gate register
- */
-#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0x7c)
-/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  set this bit to enable clock gate
- */
-#define I2S_CLK_EN    (BIT(0))
-#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
-#define I2S_CLK_EN_V  0x00000001U
-#define I2S_CLK_EN_S  0
-
-/** I2S_DATE_REG register
- *  Version control register
- */
-#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80)
-/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
- *  I2S version control register
- */
-#define I2S_DATE    0x0FFFFFFFU
-#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
-#define I2S_DATE_V  0x0FFFFFFFU
-#define I2S_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/i2s_struct.h b/components/soc/esp32c5/beta3/include/soc/i2s_struct.h
deleted file mode 100644
index 71fc30249c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/i2s_struct.h
+++ /dev/null
@@ -1,1007 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  I2S interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_raw:1;
-        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_raw:1;
-        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_raw_reg_t;
-
-/** Type of int_st register
- *  I2S interrupt status register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_st:1;
-        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_st:1;
-        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_st_reg_t;
-
-/** Type of int_ena register
- *  I2S interrupt enable register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_ena:1;
-        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_ena_reg_t;
-
-/** Type of int_clr register
- *  I2S interrupt clear register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_clr:1;
-        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of rx_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        /** rx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset receiver
-         */
-        uint32_t rx_reset:1;
-        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Rx AFIFO
-         */
-        uint32_t rx_fifo_reset:1;
-        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start receiving data
-         */
-        uint32_t rx_start:1;
-        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave receiver mode
-         */
-        uint32_t rx_slave_mod:1;
-        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
-         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
-         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-         */
-        uint32_t rx_stop_mode:2;
-        /** rx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable receiver  in mono mode
-         */
-        uint32_t rx_mono:1;
-        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-         */
-        uint32_t rx_big_endian:1;
-        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t rx_update:1;
-        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
-         *  channel data value is valid in I2S RX mono mode.
-         */
-        uint32_t rx_mono_fst_vld:1;
-        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
-         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t rx_pcm_conf:2;
-        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass Compress/Decompress module for received data.
-         */
-        uint32_t rx_pcm_bypass:1;
-        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable receiver in Phillips standard mode
-         */
-        uint32_t rx_msb_shift:1;
-        uint32_t reserved_14:1;
-        /** rx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-         */
-        uint32_t rx_left_align:1;
-        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-         */
-        uint32_t rx_24_fill_en:1;
-        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-         */
-        uint32_t rx_ws_idle_pol:1;
-        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
-         *  is received first.
-         */
-        uint32_t rx_bit_order:1;
-        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_tdm_en:1;
-        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_pdm_en:1;
-        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in receiver mode.
-         */
-        uint32_t rx_bck_div_num:6;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} i2s_rx_conf_reg_t;
-
-/** Type of rx_conf1 register
- *  I2S RX configure register 1
- */
-typedef union {
-    struct {
-        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t rx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
-         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t rx_bits_mod:5;
-        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Rx half sample bits -1.
-         */
-        uint32_t rx_half_sample_bits:8;
-        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Rx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t rx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_rx_conf1_reg_t;
-
-/** Type of rx_pdm2pcm_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:19;
-        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable PDM2PCM RX mode. 0: DIsable.
-         */
-        uint32_t rx_pdm2pcm_en:1;
-        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
-         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
-         *  sampling rate is 128. 0: down sampling rate is 64.
-         */
-        uint32_t rx_pdm_sinc_dsr_16_en:1;
-        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
-         *  Configure PDM RX amplify number.
-         */
-        uint32_t rx_pdm2pcm_amplify_num:4;
-        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
-         *  I2S PDM RX bypass hp filter or not.
-         */
-        uint32_t rx_pdm_hp_bypass:1;
-        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
-         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
-         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t rx_iir_hp_mult12_5:3;
-        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
-         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
-         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t rx_iir_hp_mult12_0:3;
-    };
-    uint32_t val;
-} i2s_rx_pdm2pcm_conf_reg_t;
-
-/** Type of rx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan0_en:1;
-        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan1_en:1;
-        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan2_en:1;
-        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan3_en:1;
-        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan4_en:1;
-        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan5_en:1;
-        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan6_en:1;
-        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan7_en:1;
-        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan8_en:1;
-        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan9_en:1;
-        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan10_en:1;
-        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan11_en:1;
-        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan12_en:1;
-        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan13_en:1;
-        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan14_en:1;
-        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan15_en:1;
-        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t rx_tdm_tot_chan_num:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_rx_tdm_ctrl_reg_t;
-
-/** Type of rxeof_num register
- *  I2S RX data number control register.
- */
-typedef union {
-    struct {
-        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
-         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
-         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
-         */
-        uint32_t rx_eof_num:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_rxeof_num_reg_t;
-
-
-/** Group: TX Control and configuration registers */
-/** Type of tx_conf register
- *  I2S TX configure register
- */
-typedef union {
-    struct {
-        /** tx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset transmitter
-         */
-        uint32_t tx_reset:1;
-        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Tx AFIFO
-         */
-        uint32_t tx_fifo_reset:1;
-        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start transmitting data
-         */
-        uint32_t tx_start:1;
-        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave transmitter mode
-         */
-        uint32_t tx_slave_mod:1;
-        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
-         */
-        uint32_t tx_stop_en:1;
-        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
-         *  1: The value of Left channel data is equal to the value of right channel data in
-         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
-         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-         */
-        uint32_t tx_chan_equal:1;
-        /** tx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable transmitter in mono mode
-         */
-        uint32_t tx_mono:1;
-        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
-         *  value.
-         */
-        uint32_t tx_big_endian:1;
-        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t tx_update:1;
-        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
-         *  channel data value is valid in I2S TX mono mode.
-         */
-        uint32_t tx_mono_fst_vld:1;
-        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
-         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t tx_pcm_conf:2;
-        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
-         */
-        uint32_t tx_pcm_bypass:1;
-        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable transmitter in Phillips standard mode
-         */
-        uint32_t tx_msb_shift:1;
-        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
-         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
-         *  generate pos/neg edge in master mode.
-         */
-        uint32_t tx_bck_no_dly:1;
-        /** tx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-         */
-        uint32_t tx_left_align:1;
-        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-         */
-        uint32_t tx_24_fill_en:1;
-        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
-         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
-         */
-        uint32_t tx_ws_idle_pol:1;
-        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
-         *  sent first.
-         */
-        uint32_t tx_bit_order:1;
-        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_tdm_en:1;
-        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_pdm_en:1;
-        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in transmitter mode.
-         */
-        uint32_t tx_bck_div_num:6;
-        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
-         *  I2S transmitter channel mode configuration bits.
-         */
-        uint32_t tx_chan_mod:3;
-        /** sig_loopback : R/W; bitpos: [30]; default: 0;
-         *  Enable signal loop back mode with transmitter module and receiver module sharing
-         *  the same WS and BCK signals.
-         */
-        uint32_t sig_loopback:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2s_tx_conf_reg_t;
-
-/** Type of tx_conf1 register
- *  I2S TX configure register 1
- */
-typedef union {
-    struct {
-        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t tx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
-         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t tx_bits_mod:5;
-        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Tx half sample bits -1.
-         */
-        uint32_t tx_half_sample_bits:8;
-        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Tx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t tx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_tx_conf1_reg_t;
-
-/** Type of tx_pcm2pdm_conf register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
-         *  I2S TX PDM OSR2 value
-         */
-        uint32_t tx_pdm_sinc_osr2:4;
-        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
-         *  I2S TX PDM prescale for sigmadelta
-         */
-        uint32_t tx_pdm_prescale:8;
-        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_hp_in_shift:2;
-        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_lp_in_shift:2;
-        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sinc_in_shift:2;
-        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sigmadelta_in_shift:2;
-        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
-         *  I2S TX PDM sigmadelta dither2 value
-         */
-        uint32_t tx_pdm_sigmadelta_dither2:1;
-        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
-         *  I2S TX PDM sigmadelta dither value
-         */
-        uint32_t tx_pdm_sigmadelta_dither:1;
-        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
-         *  I2S TX PDM dac mode enable
-         */
-        uint32_t tx_pdm_dac_2out_en:1;
-        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
-         *  I2S TX PDM dac 2channel enable
-         */
-        uint32_t tx_pdm_dac_mode_en:1;
-        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
-         *  I2S TX PDM Converter enable
-         */
-        uint32_t pcm2pdm_conv_en:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf_reg_t;
-
-/** Type of tx_pcm2pdm_conf1 register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
-         *  I2S TX PDM Fp
-         */
-        uint32_t tx_pdm_fp:10;
-        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
-         *  I2S TX PDM Fs
-         */
-        uint32_t tx_pdm_fs:10;
-        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_5:3;
-        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_0:3;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf1_reg_t;
-
-/** Type of tx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan0_en:1;
-        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan1_en:1;
-        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan2_en:1;
-        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan3_en:1;
-        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan4_en:1;
-        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan5_en:1;
-        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan6_en:1;
-        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan7_en:1;
-        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan8_en:1;
-        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan9_en:1;
-        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan10_en:1;
-        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan11_en:1;
-        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan12_en:1;
-        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan13_en:1;
-        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan14_en:1;
-        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan15_en:1;
-        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t tx_tdm_tot_chan_num:4;
-        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
-         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
-         *  only the data of the enabled channels is sent, then this bit should be set. Clear
-         *  it when all the data stored in DMA TX buffer is for enabled channels.
-         */
-        uint32_t tx_tdm_skip_msk_en:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} i2s_tx_tdm_ctrl_reg_t;
-
-
-/** Group: RX clock and timing registers */
-/** Type of rx_timing register
- *  I2S RX timing control register
- */
-typedef union {
-    struct {
-        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd_in_dm:2;
-        uint32_t reserved_2:2;
-        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd1_in_dm:2;
-        uint32_t reserved_6:2;
-        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
-         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd2_in_dm:2;
-        uint32_t reserved_10:2;
-        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
-         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd3_in_dm:2;
-        uint32_t reserved_14:2;
-        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_rx_timing_reg_t;
-
-
-/** Group: TX clock and timing registers */
-/** Type of tx_timing register
- *  I2S TX timing control register
- */
-typedef union {
-    struct {
-        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd_out_dm:2;
-        uint32_t reserved_2:2;
-        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd1_out_dm:2;
-        uint32_t reserved_6:10;
-        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_tx_timing_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of lc_hung_conf register
- *  I2S HUNG configure register.
- */
-typedef union {
-    struct {
-        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
-         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
-         *  when fifo hung counter is equal to this value
-         */
-        uint32_t lc_fifo_timeout:8;
-        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
-         *  The bits are used to scale tick counter threshold. The tick counter is reset when
-         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-         */
-        uint32_t lc_fifo_timeout_shift:3;
-        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
-         *  The enable bit for FIFO timeout
-         */
-        uint32_t lc_fifo_timeout_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_lc_hung_conf_reg_t;
-
-/** Type of conf_sigle_data register
- *  I2S signal data register
- */
-typedef union {
-    struct {
-        /** single_data : R/W; bitpos: [31:0]; default: 0;
-         *  The configured constant channel data to be sent out.
-         */
-        uint32_t single_data:32;
-    };
-    uint32_t val;
-} i2s_conf_sigle_data_reg_t;
-
-
-/** Group: TX status registers */
-/** Type of state register
- *  I2S TX status register
- */
-typedef union {
-    struct {
-        /** tx_idle : RO; bitpos: [0]; default: 1;
-         *  1: i2s_tx is idle state. 0: i2s_tx is working.
-         */
-        uint32_t tx_idle:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_state_reg_t;
-
-
-/** Group: ETM registers */
-/** Type of etm_conf register
- *  I2S ETM configure register
- */
-typedef union {
-    struct {
-        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
-         *  I2S ETM send x words event. When sending word number of
-         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_tx_send_word_num:10;
-        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
-         *  I2S ETM receive x words event. When receiving word number of
-         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_rx_receive_word_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_etm_conf_reg_t;
-
-
-/** Group: Sync counter registers */
-/** Type of fifo_cnt register
- *  I2S sync counter register
- */
-typedef union {
-    struct {
-        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
-         *  tx fifo counter value.
-         */
-        uint32_t tx_fifo_cnt:31;
-        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset tx fifo counter.
-         */
-        uint32_t tx_fifo_cnt_rst:1;
-    };
-    uint32_t val;
-} i2s_fifo_cnt_reg_t;
-
-/** Type of bck_cnt register
- *  I2S sync counter register
- */
-typedef union {
-    struct {
-        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
-         *  tx bck counter value.
-         */
-        uint32_t tx_bck_cnt:31;
-        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset tx bck counter.
-         */
-        uint32_t tx_bck_cnt_rst:1;
-    };
-    uint32_t val;
-} i2s_bck_cnt_reg_t;
-
-
-/** Group: Clock registers */
-/** Type of clk_gate register
- *  Clock gate register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  set this bit to enable clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_clk_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36713024;
-         *  I2S version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} i2s_date_reg_t;
-
-
-typedef struct i2s_dev_t {
-    uint32_t reserved_000[3];
-    volatile i2s_int_raw_reg_t int_raw;
-    volatile i2s_int_st_reg_t int_st;
-    volatile i2s_int_ena_reg_t int_ena;
-    volatile i2s_int_clr_reg_t int_clr;
-    uint32_t reserved_01c;
-    volatile i2s_rx_conf_reg_t rx_conf;
-    volatile i2s_tx_conf_reg_t tx_conf;
-    volatile i2s_rx_conf1_reg_t rx_conf1;
-    volatile i2s_tx_conf1_reg_t tx_conf1;
-    uint32_t reserved_030[4];
-    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
-    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
-    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
-    uint32_t reserved_04c;
-    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
-    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
-    volatile i2s_rx_timing_reg_t rx_timing;
-    volatile i2s_tx_timing_reg_t tx_timing;
-    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
-    volatile i2s_rxeof_num_reg_t rxeof_num;
-    volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
-    volatile i2s_state_reg_t state;
-    volatile i2s_etm_conf_reg_t etm_conf;
-    volatile i2s_fifo_cnt_reg_t fifo_cnt;
-    volatile i2s_bck_cnt_reg_t bck_cnt;
-    volatile i2s_clk_gate_reg_t clk_gate;
-    volatile i2s_date_reg_t date;
-} i2s_dev_t;
-
-extern i2s_dev_t I2S0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ieee802154_reg.h b/components/soc/esp32c5/beta3/include/soc/ieee802154_reg.h
deleted file mode 100644
index ebad2cf559..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ieee802154_reg.h
+++ /dev/null
@@ -1,545 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready.
-#define IEEE802154_REG_BASE              0x600A3000
-
-#define IEEE802154_COMMAND_REG (IEEE802154_REG_BASE + 0x0000)
-#define IEEE802154_OPCODE 0x000000FF
-#define IEEE802154_OPCODE_S 0
-
-#define IEEE802154_CTRL_CFG_REG (IEEE802154_REG_BASE + 0x0004)
-#define IEEE802154_MAC_INF3_ENABLE (BIT(31))
-#define IEEE802154_MAC_INF3_ENABLE_S 31
-#define IEEE802154_MAC_INF2_ENABLE (BIT(30))
-#define IEEE802154_MAC_INF2_ENABLE_S 30
-#define IEEE802154_MAC_INF1_ENABLE (BIT(29))
-#define IEEE802154_MAC_INF1_ENABLE_S 29
-#define IEEE802154_MAC_INF0_ENABLE (BIT(28))
-#define IEEE802154_MAC_INF0_ENABLE_S 28
-#define IEEE802154_RX_DONE_TRIGGER_IDLE (BIT(27))
-#define IEEE802154_RX_DONE_TRIGGER_IDLE_S 27
-#define IEEE802154_FORCE_RX_ENB (BIT(26))
-#define IEEE802154_FORCE_RX_ENB_S 26
-#define IEEE802154_NO_RSS_TRK_ENB (BIT(25))
-#define IEEE802154_NO_RSS_TRK_ENB_S 25
-#define IEEE802154_BIT_ORDER (BIT(24))
-#define IEEE802154_BIT_ORDER_S 24
-#define IEEE802154_COEX_ARB_DELAY 0x000000FF
-#define IEEE802154_COEX_ARB_DELAY_S 16
-#define IEEE802154_FILTER_ENHANCE (BIT(14))
-#define IEEE802154_FILTER_ENHANCE_S 14
-#define IEEE802154_AUTOPEND_ENHANCE (BIT(12))
-#define IEEE802154_AUTOPEND_ENHANCE_S 12
-#define IEEE802154_DIS_FRAME_VERSION_RSV_FILTER (BIT(11))
-#define IEEE802154_DIS_FRAME_VERSION_RSV_FILTER_S 11
-#define IEEE802154_PROMISCUOUS_MODE (BIT(7))
-#define IEEE802154_PROMISCUOUS_MODE_S 7
-#define IEEE802154_PAN_COORDINATOR (BIT(6))
-#define IEEE802154_PAN_COORDINATOR_S 6
-#define IEEE802154_DIS_IFS_CONTROL (BIT(5))
-#define IEEE802154_DIS_IFS_CONTROL_S 5
-#define IEEE802154_HW_AUTO_ACK_RX_EN (BIT(3))
-#define IEEE802154_HW_AUTO_ACK_RX_EN_S 3
-#define HW_ENHANCE_ACK_TX_EN (BIT(1))
-#define HW_ENHANCE_ACK_TX_EN_S 1
-#define IEEE802154_HW_AUTO_ACK_TX_EN (BIT(0))
-#define IEEE802154_HW_AUTO_ACK_TX_EN_S 0
-
-#define IEEE802154_INF0_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0008)
-#define IEEE802154_MAC_INF0_SHORT_ADDR 0x0000FFFF
-#define IEEE802154_MAC_INF0_SHORT_ADDR_S 0
-
-#define IEEE802154_INF0_PAN_ID_REG (IEEE802154_REG_BASE + 0x000C)
-#define IEEE802154_MAC_INF0_PAN_ID 0x0000FFFF
-#define IEEE802154_MAC_INF0_PAN_ID_S 0
-
-#define IEEE802154_INF0_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0010)
-#define IEEE802154_MAC_INF0_EXTEND_ADDR0 0xFFFFFFFF
-#define IEEE802154_MAC_INF0_EXTEND_ADDR0_S 0
-
-#define IEEE802154_INF0_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0014)
-#define IEEE802154_MAC_INF0_EXTEND_ADDR1 0xFFFFFFFF
-#define IEEE802154_MAC_INF0_EXTEND_ADDR1_S 0
-
-#define IEEE802154_INF1_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0018)
-#define IEEE802154_MAC_INF1_SHORT_ADDR 0x0000FFFF
-#define IEEE802154_MAC_INF1_SHORT_ADDR_S 0
-
-#define IEEE802154_INF1_PAN_ID_REG (IEEE802154_REG_BASE + 0x001C)
-#define IEEE802154_MAC_INF1_PAN_ID 0x0000FFFF
-#define IEEE802154_MAC_INF1_PAN_ID_S 0
-
-#define IEEE802154_INF1_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0020)
-#define IEEE802154_MAC_INF1_EXTEND_ADDR0 0xFFFFFFFF
-#define IEEE802154_MAC_INF1_EXTEND_ADDR0_S 0
-
-#define IEEE802154_INF1_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0024)
-#define IEEE802154_MAC_INF1_EXTEND_ADDR1 0xFFFFFFFF
-#define IEEE802154_MAC_INF1_EXTEND_ADDR1_S 0
-
-#define IEEE802154_INF2_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0028)
-#define IEEE802154_MAC_INF2_SHORT_ADDR 0x0000FFFF
-#define IEEE802154_MAC_INF2_SHORT_ADDR_S 0
-
-#define IEEE802154_INF2_PAN_ID_REG (IEEE802154_REG_BASE + 0x002C)
-#define IEEE802154_MAC_INF2_PAN_ID 0x0000FFFF
-#define IEEE802154_MAC_INF2_PAN_ID_S 0
-
-#define IEEE802154_INF2_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0030)
-#define IEEE802154_MAC_INF2_EXTEND_ADDR0 0xFFFFFFFF
-#define IEEE802154_MAC_INF2_EXTEND_ADDR0_S 0
-
-#define IEEE802154_INF2_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0034)
-#define IEEE802154_MAC_INF2_EXTEND_ADDR1 0xFFFFFFFF
-#define IEEE802154_MAC_INF2_EXTEND_ADDR1_S 0
-
-#define IEEE802154_INF3_SHORT_ADDR_REG (IEEE802154_REG_BASE + 0x0038)
-#define IEEE802154_MAC_INF3_SHORT_ADDR 0x0000FFFF
-#define IEEE802154_MAC_INF3_SHORT_ADDR_S 0
-
-#define IEEE802154_INF3_PAN_ID_REG (IEEE802154_REG_BASE + 0x003C)
-#define IEEE802154_MAC_INF3_PAN_ID 0x0000FFFF
-#define IEEE802154_MAC_INF3_PAN_ID_S 0
-
-#define IEEE802154_INF3_EXTEND_ADDR0_REG (IEEE802154_REG_BASE + 0x0040)
-#define IEEE802154_MAC_INF3_EXTEND_ADDR0 0xFFFFFFFF
-#define IEEE802154_MAC_INF3_EXTEND_ADDR0_S 0
-
-#define IEEE802154_INF3_EXTEND_ADDR1_REG (IEEE802154_REG_BASE + 0x0044)
-#define IEEE802154_MAC_INF3_EXTEND_ADDR1 0xFFFFFFFF
-#define IEEE802154_MAC_INF3_EXTEND_ADDR1_S 0
-
-#define IEEE802154_CHANNEL_REG (IEEE802154_REG_BASE + 0x0048)
-#define IEEE802154_HOP 0x0000007F
-#define IEEE802154_HOP_S 0
-
-#define IEEE802154_TX_POWER_REG (IEEE802154_REG_BASE + 0x004C)
-#define IEEE802154_TX_POWER 0x0000001F
-#define IEEE802154_TX_POWER_S 0
-
-#define IEEE802154_ED_SCAN_DURATION_REG (IEEE802154_REG_BASE + 0x0050)
-#define IEEE802154_ED_SCAN_WAIT_DLY 0x0000000F
-#define IEEE802154_ED_SCAN_WAIT_DLY_S 24
-#define IEEE802154_ED_SCAN_DURATION 0x00FFFFFF
-#define IEEE802154_ED_SCAN_DURATION_S 0
-
-#define IEEE802154_ED_SCAN_CFG_REG (IEEE802154_REG_BASE + 0x0054)
-#define IEEE802154_CCA_BUSY (BIT(24))
-#define IEEE802154_CCA_BUSY_S 24
-#define IEEE802154_ED_RSS 0x000000FF
-#define IEEE802154_ED_RSS_S 16
-#define IEEE802154_CCA_MODE 0x00000003
-#define IEEE802154_CCA_MODE_S 14
-#define IEEE802154_DIS_ED_POWER_SEL (BIT(13))
-#define IEEE802154_DIS_ED_POWER_SEL_S 13
-#define IEEE802154_ED_SAMPLE_MODE 0x00000003
-#define IEEE802154_ED_SAMPLE_MODE_S 11
-#define IEEE802154_CCA_ED_THRESHOLD 0x000000FF
-#define IEEE802154_CCA_ED_THRESHOLD_S 0
-
-#define IEEE802154_IFS_REG (IEEE802154_REG_BASE + 0x0058)
-#define IEEE802154_LIFS 0x000003FF
-#define IEEE802154_LIFS_S 16
-#define IEEE802154_SIFS 0x000000FF
-#define IEEE802154_SIFS_S 0
-
-#define IEEE802154_ACK_TIMEOUT_REG (IEEE802154_REG_BASE + 0x005C)
-#define IEEE802154_ACK_TIMEOUT 0x0000FFFF
-#define IEEE802154_ACK_TIMEOUT_S 0
-
-#define IEEE802154_EVENT_EN_REG (IEEE802154_REG_BASE + 0x0060)
-#define IEEE802154_EVENT_EN 0x00001FFF
-#define IEEE802154_EVENT_EN_S 0
-
-#define IEEE802154_EVENT_STATUS_REG (IEEE802154_REG_BASE + 0x0064)
-#define IEEE802154_EVENT_STATUS 0x00001FFF
-#define IEEE802154_EVENT_STATUS_S 0
-
-#define IEEE802154_RX_ABORT_INTR_CTRL_REG (IEEE802154_REG_BASE + 0x0068)
-#define IEEE802154_RX_ABORT_INTR_CTRL 0x7FFFFFFF
-#define IEEE802154_RX_ABORT_INTR_CTRL_S 0
-
-#define IEEE802154_ACK_FRAME_PENDING_EN_REG (IEEE802154_REG_BASE + 0x006c)
-#define IEEE802154_ACK_TX_ACK_TIMEOUT 0x0000FFFF
-#define IEEE802154_ACK_TX_ACK_TIMEOUT_S 16
-#define IEEE802154_ACK_FRAME_PENDING_EN (BIT(0))
-#define IEEE802154_ACK_FRAME_PENDING_EN_S 0
-
-#define IEEE802154_COEX_PTI_REG (IEEE802154_REG_BASE + 0x0070)
-#define IEEE802154_CLOSE_RF_SEL (BIT(8))
-#define IEEE802154_CLOSE_RF_SEL_S 8
-#define IEEE802154_COEX_ACK_PTI 0x0000000F
-#define IEEE802154_COEX_ACK_PTI_S 4
-#define IEEE802154_COEX_PTI 0x0000000F
-#define IEEE802154_COEX_PTI_S 0
-
-#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL_REG (IEEE802154_REG_BASE + 0x0078)
-#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL 0x7FFFFFFF
-#define IEEE802154_TX_ABORT_INTERRUPT_CONTROL_S 0
-
-#define IEEE802154_ENHANCE_ACK_CFG_REG (IEEE802154_REG_BASE + 0x7C)
-#define IEEE802154_TX_ENH_ACK_GENERATE_DONE_NOTIFY 0xFFFFFFFF
-#define IEEE802154_TX_ENH_ACK_GENERATE_DONE_NOTIFY_S 0
-
-#define IEEE802154_RX_STATUS_REG (IEEE802154_REG_BASE + 0x0080)
-#define IEEE802154_SFD_MATCH (BIT(21))
-#define IEEE802154_SFD_MATCH_S 21
-#define IEEE802154_PREAMBLE_MATCH (BIT(20))
-#define IEEE802154_PREAMBLE_MATCH_S 20
-#define IEEE802154_RX_STATE 0x00000007
-#define IEEE802154_RX_STATE_S 16
-#define IEEE802154_RX_ABORT_STATUS 0x0000001F
-#define IEEE802154_RX_ABORT_STATUS_S 4
-#define IEEE802154_FILTER_FAIL_STATUS 0x0000000F
-#define IEEE802154_FILTER_FAIL_STATUS_S 0
-
-#define IEEE802154_TX_STATUS_REG (IEEE802154_REG_BASE + 0x0084)
-#define IEEE802154_TX_SEC_ERROR_CODE 0x0000000F
-#define IEEE802154_TX_SEC_ERROR_CODE_S 16
-#define IEEE802154_TX_ABORT_STATUS 0x0000001F
-#define IEEE802154_TX_ABORT_STATUS_S 4
-#define IEEE802154_TX_STATE 0x0000000F
-#define IEEE802154_TX_STATE_S 0
-
-#define IEEE802154_TXRX_STATUS_REG (IEEE802154_REG_BASE + 0x0088)
-#define IEEE802154_RF_CTRL_STATE 0x0000000F
-#define IEEE802154_RF_CTRL_STATE_S 16
-#define IEEE802154_ED_TRIGGER_TX_PROC (BIT(11))
-#define IEEE802154_ED_TRIGGER_TX_PROC_S 11
-#define IEEE802154_ED_PROC (BIT(10))
-#define IEEE802154_ED_PROC_S 10
-#define IEEE802154_RX_PROC (BIT(9))
-#define IEEE802154_RX_PROC_S 9
-#define IEEE802154_TX_PROC (BIT(8))
-#define IEEE802154_TX_PROC_S 8
-#define IEEE802154_TXRX_STATE 0x0000000F
-#define IEEE802154_TXRX_STATE_S 0
-
-#define IEEE802154_TX_CCM_SCHEDULE_STATUS_REG (IEEE802154_REG_BASE + 0x008c)
-#define IEEE802154_TX_CCM_SCHEDULE_STATUS 0x7FFFFFFF
-#define IEEE802154_TX_CCM_SCHEDULE_STATUS_S 0
-
-#define IEEE802154_RX_LENGTH_REG (IEEE802154_REG_BASE + 0x00a4)
-#define IEEE802154_RX_LENGTH 0x0000007F
-#define IEEE802154_RX_LENGTH_S 0
-
-#define IEEE802154_TIME0_THRESHOLD_REG (IEEE802154_REG_BASE + 0x00a8)
-#define IEEE802154_TIMER0_THRESHOLD 0xFFFFFFFF
-#define IEEE802154_TIMER0_THRESHOLD_S 0
-
-#define IEEE802154_TIME0_VALUE_REG (IEEE802154_REG_BASE + 0x00ac)
-#define IEEE802154_TIMER0_VALUE 0xFFFFFFFF
-#define IEEE802154_TIMER0_VALUE_S 0
-
-#define IEEE802154_TIME1_THRESHOLD_REG (IEEE802154_REG_BASE + 0x00b0)
-#define IEEE802154_TIMER1_THRESHOLD 0xFFFFFFFF
-#define IEEE802154_TIMER1_THRESHOLD_S 0
-
-#define IEEE802154_TIME1_VALUE_REG (IEEE802154_REG_BASE + 0x00b4)
-#define IEEE802154_TIMER1_VALUE 0xFFFFFFFF
-#define IEEE802154_TIMER1_VALUE_S 0
-
-#define IEEE802154_CLK_COUNTER_MATCH_VAL_REG (IEEE802154_REG_BASE + 0x00b8)
-#define IEEE802154_CLK_COUNT_MATCH_VAL 0x0000FFFF
-#define IEEE802154_CLK_COUNT_MATCH_VAL_S 0
-
-#define IEEE802154_CLK_COUNTER_REG (IEEE802154_REG_BASE + 0x00bc)
-#define IEEE802154_CLK_625US_CNT 0x0000FFFF
-#define IEEE802154_CLK_625US_CNT_S 0
-
-#define IEEE802154_IFS_COUNTER_REG (IEEE802154_REG_BASE + 0x00c0)
-#define IEEE802154_IFS_COUNTER_EN (BIT(16))
-#define IEEE802154_IFS_COUNTER_EN_S 16
-#define IEEE802154_IFS_COUNTER 0x000003FF
-#define IEEE802154_IFS_COUNTER_S 0
-
-#define IEEE802154_SFD_WAIT_SYMBOL_REG (IEEE802154_REG_BASE + 0x00c4)
-#define IEEE802154_SFD_WAIT_SYMBOL_NUM 0x0000000F
-#define IEEE802154_SFD_WAIT_SYMBOL_NUM_S 0
-
-#define IEEE802154_TXRX_PATH_DELAY_REG (IEEE802154_REG_BASE + 0x00c8)
-#define IEEE802154_RX_PATH_DELAY 0x0000003F
-#define IEEE802154_RX_PATH_DELAY_S 16
-#define IEEE802154_TX_PATH_DELAY 0x0000003F
-#define IEEE802154_TX_PATH_DELAY_S 0
-
-#define IEEE802154_BB_CLK_REG (IEEE802154_REG_BASE + 0x00cc)
-#define IEEE802154_BB_CLK_FREQ_MINUS_1 0x0000001F
-#define IEEE802154_BB_CLK_FREQ_MINUS_1_S 0
-
-#define IEEE802154_TXDMA_ADDR_REG (IEEE802154_REG_BASE + 0x00D0)
-#define IEEE802154_TXDMA_ADDR 0xFFFFFFFF
-#define IEEE802154_TXDMA_ADDR_S 0
-
-#define IEEE802154_TXDMA_CTRL_STATE_REG (IEEE802154_REG_BASE + 0x00D4)
-#define IEEE802154_TXDMA_FETCH_BYTE_CNT 0x0000007F
-#define IEEE802154_TXDMA_FETCH_BYTE_CNT_S 24
-#define IEEE802154_TXDMA_STATE 0x0000001F
-#define IEEE802154_TXDMA_STATE_S 16
-#define IEEE802154_TXDMA_FILL_ENTRY 0x00000007
-#define IEEE802154_TXDMA_FILL_ENTRY_S 4
-#define IEEE802154_TXDMA_WATER_LEVEL 0x00000007
-#define IEEE802154_TXDMA_WATER_LEVEL_S 0
-
-#define IEEE802154_TXDMA_ERR_REG (IEEE802154_REG_BASE + 0x00D8)
-#define IEEE802154_TXDMA_ERR 0x0000000F
-#define IEEE802154_TXDMA_ERR_S 0
-
-#define IEEE802154_RXDMA_ADDR_REG (IEEE802154_REG_BASE + 0x00E0)
-#define IEEE802154_RXDMA_ADDR 0xFFFFFFFF
-#define IEEE802154_RXDMA_ADDR_S 0
-
-#define IEEE802154_RXDMA_CTRL_STATE_REG (IEEE802154_REG_BASE + 0x00E4)
-#define IEEE802154_RXDMA_APPEND_FREQ_OFFSET (BIT(25))
-#define IEEE802154_RXDMA_APPEND_FREQ_OFFSET_S 25
-#define IEEE802154_RXDMA_APPEND_LQI_OFFSET (BIT(24))
-#define IEEE802154_RXDMA_APPEND_LQI_OFFSET_S 24
-#define IEEE802154_RXDMA_STATE 0x0000001F
-#define IEEE802154_RXDMA_STATE_S 16
-#define IEEE802154_RXDMA_WATER_LEVEL 0x00000007
-#define IEEE802154_RXDMA_WATER_LEVEL_S 0
-
-#define IEEE802154_RXDMA_ERR_REG (IEEE802154_REG_BASE + 0x00E8)
-#define IEEE802154_RXDMA_ERR 0x0000000F
-#define IEEE802154_RXDMA_ERR_S 0
-
-#define IEEE802154_DMA_GCK_CFG_REG (IEEE802154_REG_BASE + 0x00F0)
-#define IEEE802154_DMA_GCK_CFG (BIT(0))
-#define IEEE802154_DMA_GCK_CFG_S 0
-
-#define IEEE802154_DMA_DUMMY_REG (IEEE802154_REG_BASE + 0x00F4)
-#define IEEE802154_DMA_DUMMY_DATA 0xFFFFFFFF
-#define IEEE802154_DMA_DUMMY_DATA_S
-
-#define IEEE802154_PAON_DELAY_REG (IEEE802154_REG_BASE + 0x0100)
-#define IEEE802154_PAON_DELAY 0x000003FF
-#define IEEE802154_PAON_DELAY_S 0
-
-#define IEEE802154_TXON_DELAY_REG (IEEE802154_REG_BASE + 0x0104)
-#define IEEE802154_TXON_DELAY 0x000003FF
-#define IEEE802154_TXON_DELAY_S 0
-
-#define IEEE802154_TXEN_STOP_DELAY_REG (IEEE802154_REG_BASE + 0x0108)
-#define IEEE802154_TXEN_STOP_DLY 0x0000003F
-#define IEEE802154_TXEN_STOP_DLY_S 0
-
-#define IEEE802154_TXOFF_DELAY_REG (IEEE802154_REG_BASE + 0x010c)
-#define IEEE802154_TXOFF_DELAY 0x0000003F
-#define IEEE802154_TXOFF_DELAY_S 0
-
-#define IEEE802154_RXON_DELAY_REG (IEEE802154_REG_BASE + 0x0110)
-#define IEEE802154_RXON_DELAY 0x000007FF
-#define IEEE802154_RXON_DELAY_S 0
-
-#define IEEE802154_TXRX_SWITCH_DELAY_REG (IEEE802154_REG_BASE + 0x0114)
-#define IEEE802154_TXRX_SWITCH_DELAY 0x000003FF
-#define IEEE802154_TXRX_SWITCH_DELAY_S 0
-
-#define IEEE802154_CONT_RX_DELAY_REG (IEEE802154_REG_BASE + 0x0118)
-#define IEEE802154_CONT_RX_DELAY 0x0000003F
-#define IEEE802154_CONT_RX_DELAY_S 0
-
-#define IEEE802154_DCDC_CTRL_REG (IEEE802154_REG_BASE + 0x011c)
-#define IEEE802154_TX_DCDC_UP (BIT(31))
-#define IEEE802154_TX_DCDC_UP_S 31
-#define IEEE802154_DCDC_CTRL_EN (BIT(16))
-#define IEEE802154_DCDC_CTRL_EN_S 16
-#define IEEE802154_DCDC_DOWN_DELAY 0x000000FF
-#define IEEE802154_DCDC_DOWN_DELAY_S 8
-#define IEEE802154_DCDC_PRE_UP_DELAY 0x000000FF
-#define IEEE802154_DCDC_PRE_UP_DELAY_S 0
-
-#define IEEE802154_DEBUG_CTRL_REG (IEEE802154_REG_BASE + 0x0120)
-#define IEEE802154_DEBUG_TRIGGER_DUMP_EN (BIT(31))
-#define IEEE802154_DEBUG_TRIGGER_DUMP_EN_S 31
-#define IEEE802154_DEBUG_STATE_MATCH_DUMP_EN (BIT(30))
-#define IEEE802154_DEBUG_STATE_MATCH_DUMP_EN_S 30
-#define IEEE802154_DEBUG_TRIGGER_PULSE_SELECT 0x00000007
-#define IEEE802154_DEBUG_TRIGGER_PULSE_SELECT_S 24
-#define IEEE802154_DEBUG_TRIGGER_STATE_MATCH_VALUE 0x0000001F
-#define IEEE802154_DEBUG_TRIGGER_STATE_MATCH_VALUE_S 16
-#define IEEE802154_DEBUG_SER_DEBUG_SEL 0x0000000F
-#define IEEE802154_DEBUG_SER_DEBUG_SEL_S 12
-#define IEEE802154_DEBUG_TRIGGER_STATE_SELECT 0x0000000F
-#define IEEE802154_DEBUG_TRIGGER_STATE_SELECT_S 8
-#define IEEE802154_DEBUG_SIGNAL_SEL 0x00000007
-#define IEEE802154_DEBUG_SIGNAL_SEL_S 0
-
-#define IEEE802154_SEC_CTRL_REG (IEEE802154_REG_BASE + 0x0128)
-#define IEEE802154_SEC_PAYLOAD_OFFSET 0x0000007F
-#define IEEE802154_SEC_PAYLOAD_OFFSET_S 8
-#define IEEE802154_SEC_EN (BIT(0))
-#define IEEE802154_SEC_EN_S 0
-
-#define IEEE802154_SEC_EXTEND_ADDRESS0_REG (IEEE802154_REG_BASE + 0x012c)
-#define IEEE802154_SEC_EXTEND_ADDRESS0 0xFFFFFFFF
-#define IEEE802154_SEC_EXTEND_ADDRESS0_S 0
-
-#define IEEE802154_SEC_EXTEND_ADDRESS1_REG (IEEE802154_REG_BASE + 0x0130)
-#define IEEE802154_SEC_EXTEND_ADDRESS1 0xFFFFFFFF
-#define IEEE802154_SEC_EXTEND_ADDRESS1_S 0
-
-#define IEEE802154_SEC_KEY0_REG (IEEE802154_REG_BASE + 0x0134)
-#define IEEE802154_SEC_KEY0 0xFFFFFFFF
-#define IEEE802154_SEC_KEY0_S 0
-
-#define IEEE802154_SEC_KEY1_REG (IEEE802154_REG_BASE + 0x0138)
-#define IEEE802154_SEC_KEY1 0xFFFFFFFF
-#define IEEE802154_SEC_KEY1_S 0
-
-#define IEEE802154_SEC_KEY2_REG (IEEE802154_REG_BASE + 0x013c)
-#define IEEE802154_SEC_KEY2 0xFFFFFFFF
-#define IEEE802154_SEC_KEY2_S 0
-
-#define IEEE802154_SEC_KEY3_REG (IEEE802154_REG_BASE + 0x0140)
-#define IEEE802154_SEC_KEY3 0xFFFFFFFF
-#define IEEE802154_SEC_KEY3_S 0
-
-#define IEEE802154_SFD_TIMEOUT_CNT_REG (IEEE802154_REG_BASE + 0x0144)
-#define IEEE802154_SFD_TIMEOUT_CNT 0x0000FFFF
-#define IEEE802154_SFD_TIMEOUT_CNT_S 0
-
-#define IEEE802154_CRC_ERROR_CNT_REG (IEEE802154_REG_BASE + 0x0148)
-#define IEEE802154_CRC_ERROR_CNT 0x0000FFFF
-#define IEEE802154_CRC_ERROR_CNT_S 0
-
-#define IEEE802154_ED_ABORT_CNT_REG (IEEE802154_REG_BASE + 0x014c)
-#define IEEE802154_ED_ABORT_CNT 0x0000FFFF
-#define IEEE802154_ED_ABORT_CNT_S 0
-
-#define IEEE802154_CCA_FAIL_CNT_REG (IEEE802154_REG_BASE + 0x0150)
-#define IEEE802154_CCA_FAIL_CNT 0x0000FFFF
-#define IEEE802154_CCA_FAIL_CNT_S 0
-
-#define IEEE802154_RX_FILTER_FAIL_CNT_REG (IEEE802154_REG_BASE + 0x0154)
-#define IEEE802154_RX_FILTER_FAIL_CNT 0x0000FFFF
-#define IEEE802154_RX_FILTER_FAIL_CNT_S 0
-
-#define IEEE802154_NO_RSS_DETECT_CNT_REG (IEEE802154_REG_BASE + 0x0158)
-#define IEEE802154_NO_RSS_DETECT_CNT 0x0000FFFF
-#define IEEE802154_NO_RSS_DETECT_CNT_S 0
-
-#define IEEE802154_RX_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x015c)
-#define IEEE802154_RX_ABORT_COEX_CNT 0x0000FFFF
-#define IEEE802154_RX_ABORT_COEX_CNT_S 0
-
-#define IEEE802154_RX_RESTART_CNT_REG (IEEE802154_REG_BASE + 0x0160)
-#define IEEE802154_RX_RESTART_CNT 0x0000FFFF
-#define IEEE802154_RX_RESTART_CNT_S 0
-
-#define IEEE802154_TX_ACK_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0164)
-#define IEEE802154_TX_ACK_ABORT_COEX_CNT 0x0000FFFF
-#define IEEE802154_TX_ACK_ABORT_COEX_CNT_S 0
-
-#define IEEE802154_ED_SCAN_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0168)
-#define IEEE802154_ED_SCAN_COEX_CNT 0x0000FFFF
-#define IEEE802154_ED_SCAN_COEX_CNT_S 0
-
-#define IEEE802154_RX_ACK_ABORT_COEX_CNT_REG (IEEE802154_REG_BASE + 0x016c)
-#define IEEE802154_RX_ACK_ABORT_COEX_CNT 0x0000FFFF
-#define IEEE802154_RX_ACK_ABORT_COEX_CNT_S 0
-
-#define IEEE802154_RX_ACK_TIMEOUT_CNT_REG (IEEE802154_REG_BASE + 0x0170)
-#define IEEE802154_RX_ACK_TIMEOUT_CNT 0x0000FFFF
-#define IEEE802154_RX_ACK_TIMEOUT_CNT_S 0
-
-#define IEEE802154_TX_BREAK_COEX_CNT_REG (IEEE802154_REG_BASE + 0x0174)
-#define IEEE802154_TX_BREAK_COEX_CNT 0x0000FFFF
-#define IEEE802154_TX_BREAK_COEX_CNT_S 0
-
-#define IEEE802154_TX_SECURITY_ERROR_CNT_REG (IEEE802154_REG_BASE + 0x0178)
-#define IEEE802154_TX_SECURITY_ERROR_CNT 0x0000FFFF
-#define IEEE802154_TX_SECURITY_ERROR_CNT_S 0
-
-#define IEEE802154_CCA_BUSY_CNT_REG (IEEE802154_REG_BASE + 0x017c)
-#define IEEE802154_CCA_BUSY_CNT 0x0000FFFF
-#define IEEE802154_CCA_BUSY_CNT_S 0
-
-#define IEEE802154_ERROR_CNT_CLEAR_REG (IEEE802154_REG_BASE + 0x0180)
-#define IEEE802154_SFD_TIMEOUT_CNT_CLEAR (BIT(14))
-#define IEEE802154_SFD_TIMEOUT_CNT_CLEAR_S 14
-#define IEEE802154_CRC_ERROR_CNT_CLEAR (BIT(13))
-#define IEEE802154_CRC_ERROR_CNT_CLEAR_S 13
-#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR (BIT(12))
-#define IEEE802154_RX_FILTER_FAIL_CNT_CLEAR_S 12
-#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR (BIT(11))
-#define IEEE802154_NO_RSS_DETECT_CNT_CLEAR_S 11
-#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR (BIT(10))
-#define IEEE802154_RX_ABORT_COEX_CNT_CLEAR_S 10
-#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR (BIT(9))
-#define IEEE802154_RX_ACK_ABORT_COEX_CNT_CLEAR_S 9
-#define IEEE802154_RX_RESTART_CNT_CLEAR (BIT(8))
-#define IEEE802154_RX_RESTART_CNT_CLEAR_S 8
-#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR (BIT(7))
-#define IEEE802154_RX_ACK_TIMEOUT_CNT_CLEAR_S 7
-#define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR (BIT(6))
-#define IEEE802154_TX_ACK_ABORT_COEX_CNT_CLEAR_S 6
-#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR (BIT(5))
-#define IEEE802154_TX_BREAK_COEX_CNT_CLEAR_S 5
-#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR (BIT(4))
-#define IEEE802154_TX_SECURITY_ERROR_CNT_CLEAR_S 4
-#define IEEE802154_ED_ABORT_CNT_CLEAR (BIT(3))
-#define IEEE802154_ED_ABORT_CNT_CLEAR_S 3
-#define IEEE802154_CCA_FAIL_CNT_CLEAR (BIT(2))
-#define IEEE802154_CCA_FAIL_CNT_CLEAR_S 2
-#define IEEE802154_CCA_BUSY_CNT_CLEAR (BIT(1))
-#define IEEE802154_CCA_BUSY_CNT_CLEAR_S 1
-#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR (BIT(0))
-#define IEEE802154_ED_SCAN_COEX_CNT_CLEAR_S 0
-
-#define DEBUG_SEL_CFG0_REG (IEEE802154_REG_BASE + 0x184)
-#define DEBUG_FIELD3_SEL 0x0000001F
-#define DEBUG_FIELD3_SEL_S 24
-#define DEBUG_FIELD2_SEL 0x0000001F
-#define DEBUG_FIELD2_SEL_S 16
-#define DEBUG_FIELD1_SEL 0x0000001F
-#define DEBUG_FIELD1_SEL_S 8
-#define DEBUG_FIELD0_SEL 0x0000001F
-#define DEBUG_FIELD0_SEL_S 0
-
-#define DEBUG_SEL_CFG1_REG (IEEE802154_REG_BASE + 0x188)
-#define DEBUG_FIELD7_SEL 0x0000001F
-#define DEBUG_FIELD7_SEL_S 24
-#define DEBUG_FIELD6_SEL 0x0000001F
-#define DEBUG_FIELD6_SEL_S 16
-#define DEBUG_FIELD5_SEL 0x0000001F
-#define DEBUG_FIELD5_SEL_S 8
-#define DEBUG_FIELD4_SEL 0x0000001F
-#define DEBUG_FIELD4_SEL_S 0
-
-#define IEEE802154_MAC_DATE_REG (IEEE802154_REG_BASE + 0x18c)
-#define IEEE802154_MAC_DATE 0xFFFFFFFF
-#define IEEE802154_MAC_DATE_S 0
-#define IEEE802154_MAC_DATE_VERSION 0x220907
-
-// For ETM feature.
-#define ETM_REG_BASE    0x600A8800
-#define ETM_CHEN_AD0_REG (ETM_REG_BASE + 0x0000)
-#define ETM_CHENSET_AD0_REG (ETM_REG_BASE + 0x0004)
-#define ETM_CHENCLR_AD0_REG (ETM_REG_BASE + 0x0008)
-#define ETM_CH0_EVT_ID_REG (ETM_REG_BASE + 0x0018)
-#define ETM_CH0_TASK_ID_REG (ETM_REG_BASE + 0x001C)
-
-#define ETM_CH_OFFSET 0x08
-
-#define ETM_EVENT_TIMER1_OVERFLOW  58
-#define ETM_EVENT_TIMER0_OVERFLOW  59
-#define ETM_TASK_ED_TRIG_TX        64
-#define ETM_TASK_RX_START          65
-#define ETM_TASK_TX_START          68
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ieee802154_struct.h b/components/soc/esp32c5/beta3/include/soc/ieee802154_struct.h
deleted file mode 100644
index f0599beebd..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ieee802154_struct.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// TODO: ZB-93, rewrite this file using regdesc tools when IEEE802154.csv is ready.
-typedef volatile struct esp_ieee802154_s {
-    union {
-        struct {
-            uint32_t cmd:        8;
-            uint32_t reserved8:  24;
-        };
-        uint32_t val;
-    } cmd; // 0x00
-
-    union {
-        struct {
-            uint32_t auto_ack_tx:        1;
-            uint32_t auto_enhack:  1;
-            uint32_t reserved2:  1;
-            uint32_t auto_ack_rx:      1;
-            uint32_t reserved4:  1;
-            uint32_t ifs_dis: 1;
-            uint32_t coordinator: 1;
-            uint32_t promiscuous: 1;
-            uint32_t reserved8: 3;
-            uint32_t version_filter_dis: 1;
-            uint32_t pending_enhance: 1;
-            uint32_t reserved13: 1;
-            uint32_t filter_enhance_dis: 1;
-            uint32_t reserved15: 1;
-            uint32_t coex_arb_delay: 8;
-            uint32_t bit_order: 1;
-            uint32_t no_rssi_trigger_break_en: 1;
-            uint32_t coex_force_rx: 1;
-            uint32_t rx_done_trig_idle: 1;
-            uint32_t multipan_mask: 4;
-        };
-        uint32_t val;
-    } conf; // 0x04
-
-    struct {
-        union {
-            struct {
-                uint32_t addr:        16;
-                uint32_t reserved16:  16;
-            };
-            uint32_t val;
-        } short_addr; // 0x08
-
-        union {
-            struct {
-                uint32_t id:        16;
-                uint32_t reserved16:  16;
-            };
-            uint32_t val;
-        } panid; // 0x0c
-
-        uint32_t ext_addr0; // 0x10
-        uint32_t ext_addr1; // 0x14
-    } multipan[4];
-
-    union {
-        struct {
-            uint32_t freq:        7;
-            uint32_t reserved7:  25;
-        };
-        uint32_t val;
-    } channel; //0x48
-
-    union {
-        struct {
-            uint32_t power:        5;
-            uint32_t reserved5:  27;
-        };
-        uint32_t val;
-    } txpower; //0x4c
-
-    union {
-        struct {
-            uint32_t duration:        24;
-            uint32_t delay:  4;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } ed_duration; //0x50
-
-    union {
-        struct {
-            uint32_t cca_threshold:        8;
-            uint32_t reserved8: 3;
-            uint32_t ed_sample_rate: 2;
-            uint32_t ed_sample_mode: 1;
-            uint32_t cca_mode:  2;
-            uint32_t ed_rss: 8;
-            uint32_t cca_busy: 1;
-            uint32_t reserved25: 7;
-        };
-        uint32_t val;
-    } ed_cfg; //0x54
-
-    union {
-        struct {
-            uint32_t sifs:        8;
-            uint32_t reserved8: 8;
-            uint32_t lifs: 10;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } ifs_cfg; //0x58
-
-    union {
-        struct {
-            uint32_t timeout:        16;
-            uint32_t reserved16: 16;
-        };
-        uint32_t val;
-    } ack_timeout; //0x5c
-
-    union {
-        struct {
-            uint32_t events: 13;
-            uint32_t reserved13: 19;
-        };
-        uint32_t val;
-    } event_en; //0x60
-
-    union {
-        struct {
-            uint32_t events: 13;
-            uint32_t reserved13: 19;
-        };
-        uint32_t val;
-    } event_status; //0x64
-
-    union {
-        struct {
-            uint32_t rx_abort_en: 31;
-            uint32_t reserved31: 1;
-        };
-        uint32_t val;
-    } rx_abort_event_en; //0x68
-
-    union {
-        struct {
-            uint32_t pending: 1;
-            uint32_t reserved1: 15;
-            uint32_t pending_timeout: 16;
-        };
-        uint32_t val;
-    } pending_cfg; //0x6c
-
-    union {
-        struct {
-            uint32_t pti: 4;
-            uint32_t hw_ack_pti: 4;
-            uint32_t close_rf_sel: 1;
-            uint32_t reserved9: 23;
-        };
-        uint32_t val;
-    } pti; //0x70
-
-    uint32_t reserved_74; //0x74
-
-    union {
-        struct {
-            uint32_t tx_abort_en: 31;
-            uint32_t reserved31: 1;
-        };
-        uint32_t val;
-    } tx_abort_event_en; //0x78
-
-    uint32_t enhack_generate_done_notify; //0x7c
-
-    union {
-        struct {
-            uint32_t filter_fail_reason: 4;
-            uint32_t rx_abort_reason: 5;
-            uint32_t reserved9: 7;
-            uint32_t rx_state: 3;
-            uint32_t reserved19: 1;
-            uint32_t preamble_match: 1;
-            uint32_t sfd_match: 1;
-            uint32_t reserved22: 10;
-        };
-        uint32_t val;
-    } rx_status; // 0x80
-
-    union {
-        struct {
-            uint32_t tx_state: 4;
-            uint32_t tx_abort_reason: 5;
-            uint32_t reserved9: 7;
-            uint32_t tx_security_error: 4;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } tx_status; //0x84
-
-    union {
-        struct {
-            uint32_t txrx_status: 4;
-            uint32_t reserved4: 4;
-            uint32_t tx_proc: 1;
-            uint32_t rx_proc: 1;
-            uint32_t ed_proc: 1;
-            uint32_t ed_trig_tx_proc: 1;
-            uint32_t reserved12: 4;
-            uint32_t rf_ctrl_state: 4;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } txrx_status; //0x88
-
-    uint32_t tx_sec_schedule_state; //0x8c
-
-    union {
-        struct {
-            uint32_t pkt_gck: 1;
-            uint32_t ctrl_gck: 1;
-            uint32_t reserved2: 30;
-        };
-        uint32_t val;
-    } core_gck_cfg; //0x90
-
-    uint32_t reserved_94; //0x94
-    uint32_t reserved_98; //0x98
-    uint32_t reserved_9c; //0x9c
-    uint32_t reserved_a0; //0xa0
-
-    uint32_t rx_length; //0xa4
-
-    uint32_t timer0_threshold; //0xa8
-    uint32_t timer0_value; //0xac
-    uint32_t timer1_threshold; //0xb0
-    uint32_t timer1_value; //0xb4
-    uint32_t clk_counter_threshold; //0xb8
-    uint32_t clk_counter_value; //0xbc
-
-    union {
-        struct {
-            uint32_t ifs_counter: 10;
-            uint32_t reserved10: 6;
-            uint32_t ifs_counter_en: 1;
-            uint32_t reserved17: 15;
-        };
-        uint32_t val;
-    } ifs_counter_cfg; //0xc0
-
-    union {
-        struct {
-            uint32_t sfd_wait_symbol_num: 4;
-            uint32_t reserved4: 28;
-        };
-        uint32_t val;
-    } sfd_wait; //0xc4
-
-    union {
-        struct {
-            uint32_t tx_path_delay: 6;
-            uint32_t reserved6: 10;
-            uint32_t rx_path_delay: 6;
-            uint32_t reserved624: 10;
-        };
-        uint32_t val;
-    } txrx_path_delay; //0xc8
-
-    uint32_t bb_clk; //0xcc
-    uint32_t dma_tx_addr; //0xd0
-
-    union {
-        struct {
-            uint32_t txdma_water_level: 3;
-            uint32_t reserved3: 1;
-            uint32_t txdma_fill_entry: 3;
-            uint32_t reserved7: 9;
-            uint32_t txdma_ctrl_state: 5;
-            uint32_t reserved21: 3;
-            uint32_t txdma_fetch_byte_cnt: 7;
-            uint32_t reserved31: 1;
-        };
-        uint32_t val;
-    } dma_tx_cfg; //0xd4
-
-    uint32_t dma_tx_err; //0xd8
-
-    uint32_t reserved_dc; //0xdc
-
-    uint32_t dma_rx_addr; //0xe0
-
-    union {
-        struct {
-            uint32_t rxdma_water_level: 3;
-            uint32_t reserved3: 13;
-            uint32_t rxdma_ctrl_state: 5;
-            uint32_t reserved21: 3;
-            uint32_t rxdma_append_lqi: 1;
-            uint32_t rxdma_append_freq_offset: 1;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } dma_rx_cfg; //0xe4
-
-    uint32_t dma_rx_err; //0xe8
-
-    uint32_t reserved_ec; //x0ec
-
-    uint32_t dma_gck; //0xf0
-    uint32_t dma_dummy_data; //0xf4
-    uint32_t reserved_f8; //0xf8
-    uint32_t reserved_fc; //0xfc
-
-    union {
-        struct {
-            uint32_t delay: 10;
-            uint32_t reserved10: 22;
-        };
-        uint32_t val;
-    } pa_on_delay; //0x100
-
-    union {
-        struct {
-            uint32_t delay: 10;
-            uint32_t reserved10: 22;
-        };
-        uint32_t val;
-    } tx_on_delay; //0x104
-
-    union {
-        struct {
-            uint32_t delay: 6;
-            uint32_t reserved6: 26;
-        };
-        uint32_t val;
-    } txen_stop_delay; //0x108
-
-    union {
-        struct {
-            uint32_t delay: 6;
-            uint32_t reserved6: 26;
-        };
-        uint32_t val;
-    } tx_off_delay; //0x10c
-
-    union {
-        struct {
-            uint32_t delay: 11;
-            uint32_t reserved11: 21;
-        };
-        uint32_t val;
-    } rx_on_delay; //0x110
-
-    union {
-        struct {
-            uint32_t delay: 10;
-            uint32_t reserved10: 22;
-        };
-        uint32_t val;
-    } txrx_switch_delay; //0x114
-
-    uint32_t cont_rx_delay; //0x118
-
-    union {
-        struct {
-            uint32_t dcdc_pre_up_delay: 8;
-            uint32_t dcdc_down_delay: 8;
-            uint32_t dcdc_ctrl_en: 1;
-            uint32_t reserved17: 14;
-            uint32_t tx_dcdc_up: 1;
-        };
-        uint32_t val;
-    } dcdc_ctrl; //0x11c
-
-    union {
-        struct {
-            uint32_t debug_sel: 3;
-            uint32_t reserved3: 5;
-            uint32_t trig_st_sel: 4;
-            uint32_t ser_debug_sel: 4;
-            uint32_t trig_st_match_val: 5;
-            uint32_t reserved21: 3;
-            uint32_t trig_pulse_sel: 3;
-            uint32_t reserved27: 3;
-            uint32_t trig_st_match_dump_en: 1;
-            uint32_t trig_pulse_dump_en: 1;
-        };
-        uint32_t val;
-    } debug_ctrl; //0x120
-
-    uint32_t tx_dma_err_sts_reg; //0x124
-    union {
-        struct {
-            uint32_t tx_security_en: 1;
-            uint32_t reserved1: 7;
-            uint32_t security_offset: 7;
-            uint32_t reserved15: 17;
-        };
-        uint32_t val;
-    } security_ctrl; //0x128
-
-    uint32_t security_addr0; //0x12c
-    uint32_t security_addr1; //0x130
-    uint32_t security_key0; //0x134
-    uint32_t security_key1; //0x138
-    uint32_t security_key2; //0x13c
-    uint32_t security_key3; //0x140
-
-    uint32_t debug_sfd_timeout_cnt; //0x144
-    uint32_t debug_crc_error_cnt; //0x148
-    uint32_t debug_ed_abort_cnt; //0x14c
-    uint32_t debug_cca_fail_cnt; //0x150
-    uint32_t debug_rx_filter_fail_cnt;  //0x154
-    uint32_t debug_no_rss_detect_cnt;  //0x158
-    uint32_t debug_rx_abort_coex_cnt;  //0x15c
-    uint32_t debug_rx_restart_cnt;  //0x160
-    uint32_t debug_tx_ack_abort_coex_cnt; //0x164
-    uint32_t debug_ed_scan_break_coex_cnt; //0x168
-    uint32_t debug_rx_ack_abort_coex_cnt; //0x16c
-    uint32_t debug_rx_ack_timeout_cnt; //0x170
-    uint32_t debug_tx_break_coex_cnt; //0x174
-    uint32_t debug_tx_security_error_cnt; //0x178
-    uint32_t debug_cca_busy_cnt; //0x17c
-
-    union {
-        struct {
-            uint32_t debug_ed_scan_break_coex_cnt: 1;
-            uint32_t debug_cca_busy_cnt: 1;
-            uint32_t debug_cca_fail_cnt: 1;
-            uint32_t debug_ed_abort_cnt: 1;
-            uint32_t debug_tx_security_error_cnt: 1;
-            uint32_t debug_tx_break_coex_cnt: 1;
-            uint32_t debug_tx_ack_abort_coex_cnt: 1;
-            uint32_t debug_rx_ack_timeout_cnt: 1;
-            uint32_t debug_rx_restart_cnt: 1;
-            uint32_t debug_rx_ack_abort_coex_cnt: 1;
-            uint32_t debug_rx_abort_coex_cnt: 1;
-            uint32_t debug_no_rss_detect_cnt: 1;
-            uint32_t debug_rx_filter_fail_cnt: 1;
-            uint32_t debug_crc_error_cnt: 1;
-            uint32_t debug_sfd_timeout_cnt: 1;
-            uint32_t reserved15: 17;
-        };
-        uint32_t val;
-    } debug_cnt_clr; //0x180
-    union {
-        struct {
-            uint32_t debug_field0_sel: 8;
-            uint32_t debug_field1_sel: 8;
-            uint32_t debug_field2_sel: 8;
-            uint32_t debug_field3_sel: 8;
-        };
-        uint32_t val;
-    } debug_sel_cfg0; //0x184
-    union {
-        struct {
-            uint32_t debug_field4_sel: 8;
-            uint32_t debug_field5_sel: 8;
-            uint32_t debug_field6_sel: 8;
-            uint32_t debug_field7_sel: 8;
-        };
-        uint32_t val;
-    } debug_sel_cfg1; //0x188
-
-    uint32_t i154_version; //0x18c
-
-} esp_ieee802154_t;
-
-extern esp_ieee802154_t IEEE802154;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h
deleted file mode 100644
index 7c3d892dd5..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h
+++ /dev/null
@@ -1,1044 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register
- *  WIFI_MAC_INTR mapping register
- */
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
-/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M  (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S)
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register
- *  WIFI_MAC_NMI mapping register
- */
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
-/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M  (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S)
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S  0
-
-/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register
- *  WIFI_PWR_INTR mapping register
- */
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
-/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M  (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S)
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register
- *  WIFI_BB_INTR mapping register
- */
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
-/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M  (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S)
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register
- *  BT_MAC_INTR mapping register
- */
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
-/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M  (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S)
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register
- *  BT_BB_INTR mapping register
- */
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
-/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M  (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S)
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register
- *  BT_BB_NMI mapping register
- */
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
-/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S)
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register
- *  LP_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
-/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register
- *  COEX_INTR mapping register
- */
-#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
-/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_COEX_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_COEX_INTR_MAP_M  (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S)
-#define INTERRUPT_CORE0_COEX_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_COEX_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register
- *  BLE_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
-/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register
- *  BLE_SEC_INTR mapping register
- */
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
-/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M  (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S)
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register
- *  I2C_MST_INTR mapping register
- */
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
-/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M  (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S)
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register
- *  ZB_MAC_INTR mapping register
- */
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
-/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M  (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S)
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register
- *  PMU_INTR mapping register
- */
-#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
-/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PMU_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PMU_INTR_MAP_M  (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S)
-#define INTERRUPT_CORE0_PMU_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PMU_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register
- *  EFUSE_INTR mapping register
- */
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
-/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M  (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S)
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
- *  LP_RTC_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
-/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_UART_INTR_MAP_REG register
- *  LP_UART_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
-/** INTERRUPT_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_UART_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_UART_INTR_MAP_M  (INTERRUPT_CORE0_LP_UART_INTR_MAP_V << INTERRUPT_CORE0_LP_UART_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_UART_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_UART_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG register
- *  LP_I2C_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
-/** INTERRUPT_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_I2C_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_M  (INTERRUPT_CORE0_LP_I2C_INTR_MAP_V << INTERRUPT_CORE0_LP_I2C_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register
- *  LP_WDT_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
-/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M  (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
- *  LP_PERI_TIMEOUT_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
-/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register
- *  LP_APM_M0_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
-/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG register
- *  LP_APM_M1_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
-/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_HUK_INTR_MAP_REG register
- *  HUK_INTR mapping register
- */
-#define INTERRUPT_CORE0_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
-/** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HUK_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HUK_INTR_MAP_M  (INTERRUPT_CORE0_HUK_INTR_MAP_V << INTERRUPT_CORE0_HUK_INTR_MAP_S)
-#define INTERRUPT_CORE0_HUK_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HUK_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
- *  CPU_INTR_FROM_CPU_0 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
- *  CPU_INTR_FROM_CPU_1 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
- *  CPU_INTR_FROM_CPU_2 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
- *  CPU_INTR_FROM_CPU_3 mapping register
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
-/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
- *  ASSIST_DEBUG_INTR mapping register
- */
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
-/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register
- *  TRACE_INTR mapping register
- */
-#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
-/** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TRACE_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TRACE_INTR_MAP_M  (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S)
-#define INTERRUPT_CORE0_TRACE_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TRACE_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register
- *  CACHE_INTR mapping register
- */
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
-/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CACHE_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_M  (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S)
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CACHE_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
- *  CPU_PERI_TIMEOUT_INTR mapping register
- */
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
-/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
- *  GPIO_INTERRUPT_PRO mapping register
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
-
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register
- *  GPIO_INTERRUPT_EXT mapping register
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
-/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP    0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S)
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S  0
-
-/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register
- *  PAU_INTR mapping register
- */
-#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
-/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PAU_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PAU_INTR_MAP_M  (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S)
-#define INTERRUPT_CORE0_PAU_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PAU_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
- *  HP_PERI_TIMEOUT_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
-/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
- *  MODEM_PERI_TIMEOUT_INTR mapping register
- */
-#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
-/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
-#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
- *  HP_APM_M0_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
-/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
- *  HP_APM_M1_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
-/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
- *  HP_APM_M2_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
-/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
- *  HP_APM_M3_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
-/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
- *  HP_APM_M4_INTR mapping register
- */
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
-/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S)
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG register
- *  LP_APM0_INTR mapping register
- */
-#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
-/** INTERRUPT_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LP_APM0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM0_INTR_MAP_S)
-#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LP_APM0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register
- *  MSPI_INTR mapping register
- */
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
-/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_MSPI_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_M  (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S)
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_MSPI_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_I2S_INTR_MAP_REG register
- *  I2S_INTR mapping register
- */
-#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
-/** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_I2S_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_I2S_INTR_MAP_M  (INTERRUPT_CORE0_I2S_INTR_MAP_V << INTERRUPT_CORE0_I2S_INTR_MAP_S)
-#define INTERRUPT_CORE0_I2S_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_I2S_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
- *  UHCI0_INTR mapping register
- */
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
-/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S)
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register
- *  UART0_INTR mapping register
- */
-#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
-/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_UART0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_UART0_INTR_MAP_M  (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S)
-#define INTERRUPT_CORE0_UART0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_UART0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
- *  UART1_INTR mapping register
- */
-#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
-/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_UART1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_UART1_INTR_MAP_M  (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S)
-#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register
- *  LEDC_INTR mapping register
- */
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
-/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_LEDC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_M  (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S)
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_LEDC_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TWAI0_INTR_MAP_REG register
- *  TWAI0_INTR mapping register
- */
-#define INTERRUPT_CORE0_TWAI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
-/** INTERRUPT_CORE0_TWAI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TWAI0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TWAI0_INTR_MAP_M  (INTERRUPT_CORE0_TWAI0_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_INTR_MAP_S)
-#define INTERRUPT_CORE0_TWAI0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TWAI0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG register
- *  TWAI0_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
-/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TWAI1_INTR_MAP_REG register
- *  TWAI1_INTR mapping register
- */
-#define INTERRUPT_CORE0_TWAI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
-/** INTERRUPT_CORE0_TWAI1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TWAI1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TWAI1_INTR_MAP_M  (INTERRUPT_CORE0_TWAI1_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_INTR_MAP_S)
-#define INTERRUPT_CORE0_TWAI1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TWAI1_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG register
- *  TWAI1_TIMER_INTR mapping register
- */
-#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
-/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S)
-#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register
- *  USB_SERIAL_JTAG_INTR mapping register
- */
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
-/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_M  (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S)
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
- *  RMT_INTR mapping register
- */
-#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
-/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_RMT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_RMT_INTR_MAP_M  (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S)
-#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
- *  I2C_EXT0_INTR mapping register
- */
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
-/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register
- *  TG0_T0_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
-/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M  (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register
- *  TG0_WDT_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
-/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register
- *  TG1_T0_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
-/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M  (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register
- *  TG1_WDT_INTR mapping register
- */
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
-/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S)
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
- *  SYSTIMER_TARGET0_INTR mapping register
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
-/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
- *  SYSTIMER_TARGET1_INTR mapping register
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
-/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
- *  SYSTIMER_TARGET2_INTR mapping register
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
-/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register
- *  APB_ADC_INTR mapping register
- */
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
-/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M  (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S)
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_PWM_INTR_MAP_REG register
- *  PWM_INTR mapping register
- */
-#define INTERRUPT_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
-/** INTERRUPT_CORE0_PWM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PWM_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PWM_INTR_MAP_M  (INTERRUPT_CORE0_PWM_INTR_MAP_V << INTERRUPT_CORE0_PWM_INTR_MAP_S)
-#define INTERRUPT_CORE0_PWM_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PWM_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register
- *  PCNT_INTR mapping register
- */
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
-/** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PCNT_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_M  (INTERRUPT_CORE0_PCNT_INTR_MAP_V << INTERRUPT_CORE0_PCNT_INTR_MAP_S)
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register
- *  PARL_IO_TX_INTR mapping register
- */
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
-/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_M  (INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S)
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register
- *  PARL_IO_RX_INTR mapping register
- */
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
-/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_M  (INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S)
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register
- *  DMA_IN_CH0_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
-/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register
- *  DMA_IN_CH1_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
-/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register
- *  DMA_IN_CH2_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
-/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
- *  DMA_OUT_CH0_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
-/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
- *  DMA_OUT_CH1_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
-/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
- *  DMA_OUT_CH2_INTR mapping register
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
-/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S)
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register
- *  GPSPI2_INTR mapping register
- */
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
-/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M  (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S)
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_AES_INTR_MAP_REG register
- *  AES_INTR mapping register
- */
-#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
-/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_AES_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_AES_INTR_MAP_M  (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S)
-#define INTERRUPT_CORE0_AES_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_AES_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
- *  SHA_INTR mapping register
- */
-#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
-/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_SHA_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_SHA_INTR_MAP_M  (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S)
-#define INTERRUPT_CORE0_SHA_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_SHA_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register
- *  RSA_INTR mapping register
- */
-#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
-/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_RSA_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_RSA_INTR_MAP_M  (INTERRUPT_CORE0_RSA_INTR_MAP_V << INTERRUPT_CORE0_RSA_INTR_MAP_S)
-#define INTERRUPT_CORE0_RSA_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_RSA_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
- *  ECC_INTR mapping register
- */
-#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
-/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ECC_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ECC_INTR_MAP_M  (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S)
-#define INTERRUPT_CORE0_ECC_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ECC_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
- *  ECDSA_INTR mapping register
- */
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
-/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M  (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S)
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_KM_INTR_MAP_REG register
- *  KM_INTR mapping register
- */
-#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
-/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Configures the interrupt source into one CPU interrupt.
- */
-#define INTERRUPT_CORE0_KM_INTR_MAP    0x0000003FU
-#define INTERRUPT_CORE0_KM_INTR_MAP_M  (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S)
-#define INTERRUPT_CORE0_KM_INTR_MAP_V  0x0000003FU
-#define INTERRUPT_CORE0_KM_INTR_MAP_S  0
-
-/** INTERRUPT_CORE0_INT_STATUS_0_REG register
- *  Status register for interrupt sources 0 ~ 31
- */
-#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
-/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the status of the interrupt sources numbered from .Each bit corresponds
- *  to one interrupt source
- *  0:The corresponding interrupt source triggered an interrupt
- *  1:No interrupt triggered
- */
-#define INTERRUPT_CORE0_INT_STATUS_0    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_0_M  (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S)
-#define INTERRUPT_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_0_S  0
-
-/** INTERRUPT_CORE0_INT_STATUS_1_REG register
- *  Status register for interrupt sources 32 ~ 63
- */
-#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
-/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the status of the interrupt sources numbered from .Each bit corresponds
- *  to one interrupt source
- *  0:The corresponding interrupt source triggered an interrupt
- *  1:No interrupt triggered
- */
-#define INTERRUPT_CORE0_INT_STATUS_1    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_1_M  (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S)
-#define INTERRUPT_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_1_S  0
-
-/** INTERRUPT_CORE0_INT_STATUS_2_REG register
- *  Status register for interrupt sources 64 ~ 95
- */
-#define INTERRUPT_CORE0_INT_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
-/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the status of the interrupt sources numbered from .Each bit corresponds
- *  to one interrupt source
- *  0:The corresponding interrupt source triggered an interrupt
- *  1:No interrupt triggered
- */
-#define INTERRUPT_CORE0_INT_STATUS_2    0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_2_M  (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S)
-#define INTERRUPT_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
-#define INTERRUPT_CORE0_INT_STATUS_2_S  0
-
-/** INTERRUPT_CORE0_CLOCK_GATE_REG register
- *  Interrupt clock gating configure register
- */
-#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
-/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Interrupt clock gating configure register
- */
-#define INTERRUPT_CORE0_REG_CLK_EN    (BIT(0))
-#define INTERRUPT_CORE0_REG_CLK_EN_M  (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S)
-#define INTERRUPT_CORE0_REG_CLK_EN_V  0x00000001U
-#define INTERRUPT_CORE0_REG_CLK_EN_S  0
-
-/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register
- *  Version control register
- */
-#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc)
-/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36773985;
- *  Version control register
- */
-#define INTERRUPT_CORE0_INTERRUPT_DATE    0x0FFFFFFFU
-#define INTERRUPT_CORE0_INTERRUPT_DATE_M  (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S)
-#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0x0FFFFFFFU
-#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_struct.h
deleted file mode 100644
index 360ffb7c3c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/interrupt_matrix_struct.h
+++ /dev/null
@@ -1,1385 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of wifi_mac_intr_map register
- *  WIFI_MAC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t wifi_mac_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_mac_intr_map_reg_t;
-
-/** Type of wifi_mac_nmi_map register
- *  WIFI_MAC_NMI mapping register
- */
-typedef union {
-    struct {
-        /** wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t wifi_mac_nmi_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_mac_nmi_map_reg_t;
-
-/** Type of wifi_pwr_intr_map register
- *  WIFI_PWR_INTR mapping register
- */
-typedef union {
-    struct {
-        /** wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t wifi_pwr_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_pwr_intr_map_reg_t;
-
-/** Type of wifi_bb_intr_map register
- *  WIFI_BB_INTR mapping register
- */
-typedef union {
-    struct {
-        /** wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t wifi_bb_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_wifi_bb_intr_map_reg_t;
-
-/** Type of bt_mac_intr_map register
- *  BT_MAC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t bt_mac_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_bt_mac_intr_map_reg_t;
-
-/** Type of bt_bb_intr_map register
- *  BT_BB_INTR mapping register
- */
-typedef union {
-    struct {
-        /** bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t bt_bb_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_bt_bb_intr_map_reg_t;
-
-/** Type of bt_bb_nmi_map register
- *  BT_BB_NMI mapping register
- */
-typedef union {
-    struct {
-        /** bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t bt_bb_nmi_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_bt_bb_nmi_map_reg_t;
-
-/** Type of lp_timer_intr_map register
- *  LP_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_timer_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_timer_intr_map_reg_t;
-
-/** Type of coex_intr_map register
- *  COEX_INTR mapping register
- */
-typedef union {
-    struct {
-        /** coex_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t coex_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_coex_intr_map_reg_t;
-
-/** Type of ble_timer_intr_map register
- *  BLE_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t ble_timer_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_ble_timer_intr_map_reg_t;
-
-/** Type of ble_sec_intr_map register
- *  BLE_SEC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t ble_sec_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_ble_sec_intr_map_reg_t;
-
-/** Type of i2c_mst_intr_map register
- *  I2C_MST_INTR mapping register
- */
-typedef union {
-    struct {
-        /** i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t i2c_mst_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_i2c_mst_intr_map_reg_t;
-
-/** Type of zb_mac_intr_map register
- *  ZB_MAC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t zb_mac_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_zb_mac_intr_map_reg_t;
-
-/** Type of pmu_intr_map register
- *  PMU_INTR mapping register
- */
-typedef union {
-    struct {
-        /** pmu_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t pmu_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_pmu_intr_map_reg_t;
-
-/** Type of efuse_intr_map register
- *  EFUSE_INTR mapping register
- */
-typedef union {
-    struct {
-        /** efuse_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t efuse_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_efuse_intr_map_reg_t;
-
-/** Type of lp_rtc_timer_intr_map register
- *  LP_RTC_TIMER_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_rtc_timer_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_rtc_timer_intr_map_reg_t;
-
-/** Type of lp_uart_intr_map register
- *  LP_UART_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_uart_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_uart_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_uart_intr_map_reg_t;
-
-/** Type of lp_i2c_intr_map register
- *  LP_I2C_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_i2c_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_i2c_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_i2c_intr_map_reg_t;
-
-/** Type of lp_wdt_intr_map register
- *  LP_WDT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_wdt_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_wdt_intr_map_reg_t;
-
-/** Type of lp_peri_timeout_intr_map register
- *  LP_PERI_TIMEOUT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_peri_timeout_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_peri_timeout_intr_map_reg_t;
-
-/** Type of lp_apm_m0_intr_map register
- *  LP_APM_M0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_apm_m0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_apm_m0_intr_map_reg_t;
-
-/** Type of lp_apm_m1_intr_map register
- *  LP_APM_M1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_apm_m1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_apm_m1_intr_map_reg_t;
-
-/** Type of huk_intr_map register
- *  HUK_INTR mapping register
- */
-typedef union {
-    struct {
-        /** huk_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t huk_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_huk_intr_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_0_map register
- *  CPU_INTR_FROM_CPU_0 mapping register
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t cpu_intr_from_cpu_0_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_1_map register
- *  CPU_INTR_FROM_CPU_1 mapping register
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t cpu_intr_from_cpu_1_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_2_map register
- *  CPU_INTR_FROM_CPU_2 mapping register
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t cpu_intr_from_cpu_2_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_3_map register
- *  CPU_INTR_FROM_CPU_3 mapping register
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t cpu_intr_from_cpu_3_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t;
-
-/** Type of assist_debug_intr_map register
- *  ASSIST_DEBUG_INTR mapping register
- */
-typedef union {
-    struct {
-        /** assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t assist_debug_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_assist_debug_intr_map_reg_t;
-
-/** Type of trace_intr_map register
- *  TRACE_INTR mapping register
- */
-typedef union {
-    struct {
-        /** trace_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t trace_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_trace_intr_map_reg_t;
-
-/** Type of cache_intr_map register
- *  CACHE_INTR mapping register
- */
-typedef union {
-    struct {
-        /** cache_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t cache_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_cache_intr_map_reg_t;
-
-/** Type of cpu_peri_timeout_intr_map register
- *  CPU_PERI_TIMEOUT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t cpu_peri_timeout_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_cpu_peri_timeout_intr_map_reg_t;
-
-/** Type of gpio_interrupt_pro_map register
- *  GPIO_INTERRUPT_PRO mapping register
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t gpio_interrupt_pro_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_gpio_interrupt_pro_map_reg_t;
-
-/** Type of gpio_interrupt_pro_nmi_map register
- *  GPIO_INTERRUPT_PRO_NMI mapping register
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t gpio_interrupt_pro_nmi_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_gpio_interrupt_pro_nmi_map_reg_t;
-
-/** Type of gpio_interrupt_sd_map register
- *  GPIO_INTERRUPT_SD mapping register
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_sd_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t gpio_interrupt_sd_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_gpio_interrupt_sd_map_reg_t;
-
-/** Type of pau_intr_map register
- *  PAU_INTR mapping register
- */
-typedef union {
-    struct {
-        /** pau_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t pau_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_pau_intr_map_reg_t;
-
-/** Type of hp_peri_timeout_intr_map register
- *  HP_PERI_TIMEOUT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t hp_peri_timeout_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_hp_peri_timeout_intr_map_reg_t;
-
-/** Type of modem_peri_timeout_intr_map register
- *  MODEM_PERI_TIMEOUT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t modem_peri_timeout_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_modem_peri_timeout_intr_map_reg_t;
-
-/** Type of hp_apm_m0_intr_map register
- *  HP_APM_M0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t hp_apm_m0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m0_intr_map_reg_t;
-
-/** Type of hp_apm_m1_intr_map register
- *  HP_APM_M1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t hp_apm_m1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m1_intr_map_reg_t;
-
-/** Type of hp_apm_m2_intr_map register
- *  HP_APM_M2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t hp_apm_m2_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m2_intr_map_reg_t;
-
-/** Type of hp_apm_m3_intr_map register
- *  HP_APM_M3_INTR mapping register
- */
-typedef union {
-    struct {
-        /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t hp_apm_m3_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_hp_apm_m3_intr_map_reg_t;
-
-/** Type of lp_apm0_intr_map register
- *  LP_APM0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** lp_apm0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t lp_apm0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_lp_apm0_intr_map_reg_t;
-
-/** Type of mspi_intr_map register
- *  MSPI_INTR mapping register
- */
-typedef union {
-    struct {
-        /** mspi_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t mspi_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_mspi_intr_map_reg_t;
-
-/** Type of i2s1_intr_map register
- *  I2S1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t i2s1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_i2s1_intr_map_reg_t;
-
-/** Type of uhci0_intr_map register
- *  UHCI0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** uhci0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t uhci0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_uhci0_intr_map_reg_t;
-
-/** Type of uart0_intr_map register
- *  UART0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t uart0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_uart0_intr_map_reg_t;
-
-/** Type of uart1_intr_map register
- *  UART1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t uart1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_uart1_intr_map_reg_t;
-
-/** Type of ledc_intr_map register
- *  LEDC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** ledc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t ledc_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_ledc_intr_map_reg_t;
-
-/** Type of can0_intr_map register
- *  CAN0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** can0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t can0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_can0_intr_map_reg_t;
-
-/** Type of can1_intr_map register
- *  CAN1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** can1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t can1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_can1_intr_map_reg_t;
-
-/** Type of usb_intr_map register
- *  USB_INTR mapping register
- */
-typedef union {
-    struct {
-        /** usb_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t usb_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_usb_intr_map_reg_t;
-
-/** Type of rmt_intr_map register
- *  RMT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** rmt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t rmt_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_rmt_intr_map_reg_t;
-
-/** Type of i2c_ext0_intr_map register
- *  I2C_EXT0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t i2c_ext0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_i2c_ext0_intr_map_reg_t;
-
-/** Type of tg0_t0_intr_map register
- *  TG0_T0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t tg0_t0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_tg0_t0_intr_map_reg_t;
-
-/** Type of tg0_t1_intr_map register
- *  TG0_T1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t tg0_t1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_tg0_t1_intr_map_reg_t;
-
-/** Type of tg0_wdt_intr_map register
- *  TG0_WDT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t tg0_wdt_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_tg0_wdt_intr_map_reg_t;
-
-/** Type of tg1_t0_intr_map register
- *  TG1_T0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t tg1_t0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_tg1_t0_intr_map_reg_t;
-
-/** Type of tg1_t1_intr_map register
- *  TG1_T1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t tg1_t1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_tg1_t1_intr_map_reg_t;
-
-/** Type of tg1_wdt_intr_map register
- *  TG1_WDT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t tg1_wdt_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_tg1_wdt_intr_map_reg_t;
-
-/** Type of systimer_target0_intr_map register
- *  SYSTIMER_TARGET0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t systimer_target0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_systimer_target0_intr_map_reg_t;
-
-/** Type of systimer_target1_intr_map register
- *  SYSTIMER_TARGET1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t systimer_target1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_systimer_target1_intr_map_reg_t;
-
-/** Type of systimer_target2_intr_map register
- *  SYSTIMER_TARGET2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t systimer_target2_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_systimer_target2_intr_map_reg_t;
-
-/** Type of apb_adc_intr_map register
- *  APB_ADC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t apb_adc_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_apb_adc_intr_map_reg_t;
-
-/** Type of pwm_intr_map register
- *  PWM_INTR mapping register
- */
-typedef union {
-    struct {
-        /** pwm_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t pwm_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_pwm_intr_map_reg_t;
-
-/** Type of pcnt_intr_map register
- *  PCNT_INTR mapping register
- */
-typedef union {
-    struct {
-        /** pcnt_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t pcnt_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_pcnt_intr_map_reg_t;
-
-/** Type of parl_io_tx_intr_map register
- *  PARL_IO_TX_INTR mapping register
- */
-typedef union {
-    struct {
-        /** parl_io_tx_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t parl_io_tx_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_parl_io_tx_intr_map_reg_t;
-
-/** Type of parl_io_rx_intr_map register
- *  PARL_IO_RX_INTR mapping register
- */
-typedef union {
-    struct {
-        /** parl_io_rx_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t parl_io_rx_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_parl_io_rx_intr_map_reg_t;
-
-/** Type of slc0_intr_map register
- *  SLC0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** slc0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t slc0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_slc0_intr_map_reg_t;
-
-/** Type of slc1_intr_map register
- *  SLC1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** slc1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t slc1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_slc1_intr_map_reg_t;
-
-/** Type of usb_otg20_intr_map register
- *  USB_OTG20_INTR mapping register
- */
-typedef union {
-    struct {
-        /** usb_otg20_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t usb_otg20_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_usb_otg20_intr_map_reg_t;
-
-/** Type of usb_otg20_multi_proc_intr_map register
- *  USB_OTG20_MULTI_PROC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** usb_otg20_multi_proc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t usb_otg20_multi_proc_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_usb_otg20_multi_proc_intr_map_reg_t;
-
-/** Type of usb_otg20_misc_intr_map register
- *  USB_OTG20_MISC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** usb_otg20_misc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t usb_otg20_misc_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_usb_otg20_misc_intr_map_reg_t;
-
-/** Type of dma_in_ch0_intr_map register
- *  DMA_IN_CH0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t dma_in_ch0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch0_intr_map_reg_t;
-
-/** Type of dma_in_ch1_intr_map register
- *  DMA_IN_CH1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t dma_in_ch1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch1_intr_map_reg_t;
-
-/** Type of dma_in_ch2_intr_map register
- *  DMA_IN_CH2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** dma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t dma_in_ch2_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_dma_in_ch2_intr_map_reg_t;
-
-/** Type of dma_out_ch0_intr_map register
- *  DMA_OUT_CH0_INTR mapping register
- */
-typedef union {
-    struct {
-        /** dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t dma_out_ch0_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch0_intr_map_reg_t;
-
-/** Type of dma_out_ch1_intr_map register
- *  DMA_OUT_CH1_INTR mapping register
- */
-typedef union {
-    struct {
-        /** dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t dma_out_ch1_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch1_intr_map_reg_t;
-
-/** Type of dma_out_ch2_intr_map register
- *  DMA_OUT_CH2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** dma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t dma_out_ch2_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_dma_out_ch2_intr_map_reg_t;
-
-/** Type of gpspi2_intr_map register
- *  GPSPI2_INTR mapping register
- */
-typedef union {
-    struct {
-        /** gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t gpspi2_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_gpspi2_intr_map_reg_t;
-
-/** Type of aes_intr_map register
- *  AES_INTR mapping register
- */
-typedef union {
-    struct {
-        /** aes_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t aes_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_aes_intr_map_reg_t;
-
-/** Type of sha_intr_map register
- *  SHA_INTR mapping register
- */
-typedef union {
-    struct {
-        /** sha_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t sha_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_sha_intr_map_reg_t;
-
-/** Type of rsa_intr_map register
- *  RSA_INTR mapping register
- */
-typedef union {
-    struct {
-        /** rsa_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t rsa_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_rsa_intr_map_reg_t;
-
-/** Type of ecc_intr_map register
- *  ECC_INTR mapping register
- */
-typedef union {
-    struct {
-        /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t ecc_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_ecc_intr_map_reg_t;
-
-/** Type of ecdsa_intr_map register
- *  ECDSA_INTR mapping register
- */
-typedef union {
-    struct {
-        /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t ecdsa_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_ecdsa_intr_map_reg_t;
-
-/** Type of km_intr_map register
- *  KM_INTR mapping register
- */
-typedef union {
-    struct {
-        /** km_intr_map : R/W; bitpos: [5:0]; default: 0;
-         *  Configures the interrupt source into one CPU interrupt.
-         */
-        uint32_t km_intr_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} interrupt_core0_km_intr_map_reg_t;
-
-/** Type of int_status_reg_0 register
- *  Status register for interrupt sources 0 ~ 31
- */
-typedef union {
-    struct {
-        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the status of the interrupt sources numbered from .Each bit corresponds
-         *  to one interrupt source
-         *  0:The corresponding interrupt source triggered an interrupt
-         *  1:No interrupt triggered
-         */
-        uint32_t int_status_0:32;
-    };
-    uint32_t val;
-} interrupt_core0_int_status_reg_0_reg_t;
-
-/** Type of int_status_reg_1 register
- *  Status register for interrupt sources 32 ~ 63
- */
-typedef union {
-    struct {
-        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the status of the interrupt sources numbered from .Each bit corresponds
-         *  to one interrupt source
-         *  0:The corresponding interrupt source triggered an interrupt
-         *  1:No interrupt triggered
-         */
-        uint32_t int_status_1:32;
-    };
-    uint32_t val;
-} interrupt_core0_int_status_reg_1_reg_t;
-
-/** Type of int_status_reg_2 register
- *  Status register for interrupt sources 64 ~ 95
- */
-typedef union {
-    struct {
-        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the status of the interrupt sources numbered from .Each bit corresponds
-         *  to one interrupt source
-         *  0:The corresponding interrupt source triggered an interrupt
-         *  1:No interrupt triggered
-         */
-        uint32_t int_status_2:32;
-    };
-    uint32_t val;
-} interrupt_core0_int_status_reg_2_reg_t;
-
-/** Type of clock_gate register
- *  Interrupt clock gating configure register
- */
-typedef union {
-    struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
-         *  Interrupt clock gating configure register
-         */
-        uint32_t reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} interrupt_core0_clock_gate_reg_t;
-
-
-/** Group: Version Register */
-/** Type of interrupt_date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** interrupt_date : R/W; bitpos: [27:0]; default: 36717104;
-         *  Version control register
-         */
-        uint32_t interrupt_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} interrupt_core0_interrupt_date_reg_t;
-
-
-typedef struct intmtx_core0_dev_t {
-    volatile interrupt_core0_wifi_mac_intr_map_reg_t wifi_mac_intr_map;
-    volatile interrupt_core0_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map;
-    volatile interrupt_core0_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map;
-    volatile interrupt_core0_wifi_bb_intr_map_reg_t wifi_bb_intr_map;
-    volatile interrupt_core0_bt_mac_intr_map_reg_t bt_mac_intr_map;
-    volatile interrupt_core0_bt_bb_intr_map_reg_t bt_bb_intr_map;
-    volatile interrupt_core0_bt_bb_nmi_map_reg_t bt_bb_nmi_map;
-    volatile interrupt_core0_lp_timer_intr_map_reg_t lp_timer_intr_map;
-    volatile interrupt_core0_coex_intr_map_reg_t coex_intr_map;
-    volatile interrupt_core0_ble_timer_intr_map_reg_t ble_timer_intr_map;
-    volatile interrupt_core0_ble_sec_intr_map_reg_t ble_sec_intr_map;
-    volatile interrupt_core0_i2c_mst_intr_map_reg_t i2c_mst_intr_map;
-    volatile interrupt_core0_zb_mac_intr_map_reg_t zb_mac_intr_map;
-    volatile interrupt_core0_pmu_intr_map_reg_t pmu_intr_map;
-    volatile interrupt_core0_efuse_intr_map_reg_t efuse_intr_map;
-    volatile interrupt_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
-    volatile interrupt_core0_lp_uart_intr_map_reg_t lp_uart_intr_map;
-    volatile interrupt_core0_lp_i2c_intr_map_reg_t lp_i2c_intr_map;
-    volatile interrupt_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
-    volatile interrupt_core0_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
-    volatile interrupt_core0_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
-    volatile interrupt_core0_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map;
-    volatile interrupt_core0_huk_intr_map_reg_t huk_intr_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
-    volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
-    volatile interrupt_core0_assist_debug_intr_map_reg_t assist_debug_intr_map;
-    volatile interrupt_core0_trace_intr_map_reg_t trace_intr_map;
-    volatile interrupt_core0_cache_intr_map_reg_t cache_intr_map;
-    volatile interrupt_core0_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map;
-    volatile interrupt_core0_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map;
-    volatile interrupt_core0_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map;
-    volatile interrupt_core0_gpio_interrupt_sd_map_reg_t gpio_interrupt_sd_map;
-    volatile interrupt_core0_pau_intr_map_reg_t pau_intr_map;
-    volatile interrupt_core0_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map;
-    volatile interrupt_core0_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map;
-    volatile interrupt_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
-    volatile interrupt_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
-    volatile interrupt_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
-    volatile interrupt_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
-    volatile interrupt_core0_lp_apm0_intr_map_reg_t lp_apm0_intr_map;
-    volatile interrupt_core0_mspi_intr_map_reg_t mspi_intr_map;
-    volatile interrupt_core0_i2s1_intr_map_reg_t i2s1_intr_map;
-    volatile interrupt_core0_uhci0_intr_map_reg_t uhci0_intr_map;
-    volatile interrupt_core0_uart0_intr_map_reg_t uart0_intr_map;
-    volatile interrupt_core0_uart1_intr_map_reg_t uart1_intr_map;
-    volatile interrupt_core0_ledc_intr_map_reg_t ledc_intr_map;
-    volatile interrupt_core0_can0_intr_map_reg_t can0_intr_map;
-    volatile interrupt_core0_can1_intr_map_reg_t can1_intr_map;
-    volatile interrupt_core0_usb_intr_map_reg_t usb_intr_map;
-    volatile interrupt_core0_rmt_intr_map_reg_t rmt_intr_map;
-    volatile interrupt_core0_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map;
-    volatile interrupt_core0_tg0_t0_intr_map_reg_t tg0_t0_intr_map;
-    volatile interrupt_core0_tg0_t1_intr_map_reg_t tg0_t1_intr_map;
-    volatile interrupt_core0_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map;
-    volatile interrupt_core0_tg1_t0_intr_map_reg_t tg1_t0_intr_map;
-    volatile interrupt_core0_tg1_t1_intr_map_reg_t tg1_t1_intr_map;
-    volatile interrupt_core0_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map;
-    volatile interrupt_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
-    volatile interrupt_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
-    volatile interrupt_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
-    volatile interrupt_core0_apb_adc_intr_map_reg_t apb_adc_intr_map;
-    volatile interrupt_core0_pwm_intr_map_reg_t pwm_intr_map;
-    volatile interrupt_core0_pcnt_intr_map_reg_t pcnt_intr_map;
-    volatile interrupt_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map;
-    volatile interrupt_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map;
-    volatile interrupt_core0_slc0_intr_map_reg_t slc0_intr_map;
-    volatile interrupt_core0_slc1_intr_map_reg_t slc1_intr_map;
-    volatile interrupt_core0_usb_otg20_intr_map_reg_t usb_otg20_intr_map;
-    volatile interrupt_core0_usb_otg20_multi_proc_intr_map_reg_t usb_otg20_multi_proc_intr_map;
-    volatile interrupt_core0_usb_otg20_misc_intr_map_reg_t usb_otg20_misc_intr_map;
-    volatile interrupt_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map;
-    volatile interrupt_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map;
-    volatile interrupt_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map;
-    volatile interrupt_core0_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map;
-    volatile interrupt_core0_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map;
-    volatile interrupt_core0_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map;
-    volatile interrupt_core0_gpspi2_intr_map_reg_t gpspi2_intr_map;
-    volatile interrupt_core0_aes_intr_map_reg_t aes_intr_map;
-    volatile interrupt_core0_sha_intr_map_reg_t sha_intr_map;
-    volatile interrupt_core0_rsa_intr_map_reg_t rsa_intr_map;
-    volatile interrupt_core0_ecc_intr_map_reg_t ecc_intr_map;
-    volatile interrupt_core0_ecdsa_intr_map_reg_t ecdsa_intr_map;
-    volatile interrupt_core0_km_intr_map_reg_t km_intr_map;
-    volatile interrupt_core0_int_status_reg_0_reg_t int_status_reg_0;
-    volatile interrupt_core0_int_status_reg_1_reg_t int_status_reg_1;
-    volatile interrupt_core0_int_status_reg_2_reg_t int_status_reg_2;
-    volatile interrupt_core0_clock_gate_reg_t clock_gate;
-    uint32_t reserved_164[422];
-    volatile interrupt_core0_interrupt_date_reg_t interrupt_date;
-} interrupt_core0_dev_t;
-
-extern interrupt_core0_dev_t INTMTX;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(interrupt_core0_dev_t) == 0x800, "Invalid size of interrupt_core0_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/interrupts.h b/components/soc/esp32c5/beta3/include/soc/interrupts.h
deleted file mode 100644
index 18031cc2af..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/interrupts.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-//Interrupt hardware source table
-//This table is decided by hardware, don't touch this.
-typedef enum {
-    ETS_WIFI_MAC_INTR_SOURCE = 0,               /**< interrupt of WiFi MAC, level*/
-    ETS_WIFI_MAC_NMI_SOURCE,                    /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
-    ETS_WIFI_PWR_INTR_SOURCE,                   /**< */
-    ETS_WIFI_BB_INTR_SOURCE,                    /**< interrupt of WiFi BB, level, we can do some calibration*/
-    ETS_BT_MAC_INTR_SOURCE,                     /**< will be cancelled*/
-    ETS_BT_BB_INTR_SOURCE,                      /**< interrupt of BT BB, level*/
-    ETS_BT_BB_NMI_SOURCE,                       /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
-    ETS_LP_TIMER_INTR_SOURCE,
-    ETS_COEX_INTR_SOURCE,
-    ETS_BLE_TIMER_INTR_SOURCE,
-    ETS_BLE_SEC_INTR_SOURCE,
-    ETS_I2C_MASTER_SOURCE,                      /**< interrupt of I2C Master, level*/
-    ETS_ZB_MAC_INTR_SOURCE,
-    ETS_PMU_INTR_SOURCE,
-    ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
-    ETS_LP_RTC_TIMER_INTR_SOURCE,
-    ETS_LP_UART_INTR_SOURCE,
-    ETS_LP_I2C_INTR_SOURCE,
-    ETS_LP_WDT_INTR_SOURCE,
-    ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
-    ETS_LP_APM_M0_INTR_SOURCE,
-    ETS_LP_APM_M1_INTR_SOURCE,
-    ETS_HUK_INTR_SOURCE,
-    ETS_FROM_CPU_INTR0_SOURCE,                  /**< interrupt0 generated from a CPU, level*/
-    ETS_FROM_CPU_INTR1_SOURCE,                  /**< interrupt1 generated from a CPU, level*/
-    ETS_FROM_CPU_INTR2_SOURCE,                  /**< interrupt2 generated from a CPU, level*/
-    ETS_FROM_CPU_INTR3_SOURCE,                  /**< interrupt3 generated from a CPU, level*/
-    ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
-    ETS_TRACE_INTR_SOURCE,
-    ETS_CACHE_INTR_SOURCE,
-    ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
-    ETS_GPIO_INTR_SOURCE,                       /**< interrupt of GPIO, level*/
-    ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
-    ETS_GPIO_SD_INTR_SOURCE,
-    ETS_PAU_INTR_SOURCE,
-    ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
-    ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
-    ETS_HP_APM_M0_INTR_SOURCE,
-    ETS_HP_APM_M1_INTR_SOURCE,
-    ETS_HP_APM_M2_INTR_SOURCE,
-    ETS_HP_APM_M3_INTR_SOURCE,
-    ETS_LP_APM0_INTR_SOURCE,
-    ETS_MSPI_INTR_SOURCE,
-    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
-    ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
-    ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
-    ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
-    ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
-    ETS_TWAI0_INTR_SOURCE,                      /**< interrupt of twai0, level*/
-    ETS_TWAI1_INTR_SOURCE,                      /**< interrupt of twai1, level*/
-    ETS_USB_SERIAL_JTAG_INTR_SOURCE,            /**< interrupt of USB, level*/
-    ETS_RMT_INTR_SOURCE,                        /**< interrupt of remote controller, level*/
-    ETS_I2C_EXT0_INTR_SOURCE,                   /**< interrupt of I2C controller1, level*/
-    ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level*/
-    ETS_TG0_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER1, level*/
-    ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
-    ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
-    ETS_TG1_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER1, level*/
-    ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
-    ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
-    ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
-    ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
-    ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/
-    ETS_MCPWM0_INTR_SOURCE,                     /**< interrupt of MCPWM0, LEVEL*/
-    ETS_PCNT_INTR_SOURCE,
-    ETS_PARL_IO_TX_INTR_SOURCE,
-    ETS_PARL_IO_RX_INTR_SOURCE,
-    ETS_SLC0_INTR_SOURCE,
-    ETS_SLC1_INTR_SOURCE,
-    ETS_USB_OTG20_INTR_SOURCE,
-    ETS_USB_OTG20_MULTI_PROC_INTR_SOURCE,
-    ETS_USB_OTG20_MISC_INTR_SOURCE,
-    ETS_DMA_IN_CH0_INTR_SOURCE,                    /**< interrupt of general DMA IN channel 0, LEVEL*/
-    ETS_DMA_IN_CH1_INTR_SOURCE,                    /**< interrupt of general DMA IN channel 1, LEVEL*/
-    ETS_DMA_IN_CH2_INTR_SOURCE,                    /**< interrupt of general DMA IN channel 2, LEVEL*/
-    ETS_DMA_OUT_CH0_INTR_SOURCE,                   /**< interrupt of general DMA OUT channel 0, LEVEL*/
-    ETS_DMA_OUT_CH1_INTR_SOURCE,                   /**< interrupt of general DMA OUT channel 1, LEVEL*/
-    ETS_DMA_OUT_CH2_INTR_SOURCE,                   /**< interrupt of general DMA OUT channel 2, LEVEL*/
-    ETS_GPSPI2_INTR_SOURCE,
-    ETS_AES_INTR_SOURCE,                        /**< interrupt of AES accelerator, level*/
-    ETS_SHA_INTR_SOURCE,                        /**< interrupt of SHA accelerator, level*/
-    ETS_RSA_INTR_SOURCE,                        /**< interrupt of RSA accelerator, level*/
-    ETS_ECC_INTR_SOURCE,                        /**< interrupt of ECC accelerator, level*/
-    ETS_ECDSA_INTR_SOURCE,
-    ETS_KM_INTR_SOURCE,
-    ETS_MAX_INTR_SOURCE,
-} periph_interrupt_t;
-
-extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/intpri_reg.h b/components/soc/esp32c5/beta3/include/soc/intpri_reg.h
deleted file mode 100644
index 67aa1c8cff..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/intpri_reg.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
-/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_0    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_0_M  (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
-#define INTPRI_CPU_INTR_FROM_CPU_0_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_0_S  0
-
-/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
-/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_1    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_1_M  (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
-#define INTPRI_CPU_INTR_FROM_CPU_1_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_1_S  0
-
-/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
-/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_2    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_2_M  (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
-#define INTPRI_CPU_INTR_FROM_CPU_2_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_2_S  0
-
-/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
- *  register description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
-/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
- *  Need add description
- */
-#define INTPRI_CPU_INTR_FROM_CPU_3    (BIT(0))
-#define INTPRI_CPU_INTR_FROM_CPU_3_M  (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
-#define INTPRI_CPU_INTR_FROM_CPU_3_V  0x00000001U
-#define INTPRI_CPU_INTR_FROM_CPU_3_S  0
-
-/** INTPRI_DATE_REG register
- *  register description
- */
-#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
-/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784;
- *  Need add description
- */
-#define INTPRI_DATE    0x0FFFFFFFU
-#define INTPRI_DATE_M  (INTPRI_DATE_V << INTPRI_DATE_S)
-#define INTPRI_DATE_V  0x0FFFFFFFU
-#define INTPRI_DATE_S  0
-
-/** INTPRI_CLOCK_GATE_REG register
- *  register description
- */
-#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
-/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Need add description
- */
-#define INTPRI_CLK_EN    (BIT(0))
-#define INTPRI_CLK_EN_M  (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
-#define INTPRI_CLK_EN_V  0x00000001U
-#define INTPRI_CLK_EN_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/intpri_struct.h b/components/soc/esp32c5/beta3/include/soc/intpri_struct.h
deleted file mode 100644
index 460811245d..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/intpri_struct.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Interrupt Registers */
-/** Type of cpu_intr_from_cpu_0 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_0:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_0_reg_t;
-
-/** Type of cpu_intr_from_cpu_1 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_1:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_1_reg_t;
-
-/** Type of cpu_intr_from_cpu_2 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_2:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_2_reg_t;
-
-/** Type of cpu_intr_from_cpu_3 register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_3:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_cpu_intr_from_cpu_3_reg_t;
-
-
-/** Group: Version Registers */
-/** Type of date register
- *  register description
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36712784;
-         *  Need add description
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} intpri_date_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of clock_gate register
- *  register description
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Need add description
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intpri_clock_gate_reg_t;
-
-
-typedef struct intpri_dev_t {
-    uint32_t reserved_000[36];
-    volatile intpri_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
-    volatile intpri_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
-    volatile intpri_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
-    volatile intpri_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
-    volatile intpri_date_reg_t date;
-    volatile intpri_clock_gate_reg_t clock_gate;
-} intpri_dev_t;
-
-extern intpri_dev_t INTPRI;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(intpri_dev_t) == 0xa8, "Invalid size of intpri_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h b/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h
deleted file mode 100644
index 2cb8bd4349..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Used to enable sleep mode pin functions */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-
-#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
-#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
-#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_MTMS
-#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_MTDI
-#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_MTCK
-#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_MTDO
-#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_GPIO6
-#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
-#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
-#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
-#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_U0TXD
-#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_U0RXD
-#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_SDIO_DATA1
-#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_SDIO_DATA0
-#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_SDIO_CLK
-#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_SDIO_CMD
-#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_SDIO_DATA3
-#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_SDIO_DATA2
-#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_SPICS0
-#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_SPIQ
-#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_SPIWP
-#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_VDD_SPI
-#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_PAD_SPIHD
-#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_PAD_SPICLK
-#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_PAD_SPID
-#define IO_MUX_GPIO25_REG                   PERIPHS_IO_MUX_U_PAD_GPIO25
-#define IO_MUX_GPIO26_REG                   PERIPHS_IO_MUX_U_PAD_GPIO26
-
-#define PIN_FUNC_GPIO								1
-
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-#define SPI_HD_GPIO_NUM              22
-#define SPI_WP_GPIO_NUM              20
-#define SPI_CS0_GPIO_NUM             18
-#define SPI_CLK_GPIO_NUM             23
-#define SPI_D_GPIO_NUM               24
-#define SPI_Q_GPIO_NUM               19
-
-#define SD_CLK_GPIO_NUM              14
-#define SD_CMD_GPIO_NUM              15
-#define SD_DATA0_GPIO_NUM            13
-#define SD_DATA1_GPIO_NUM            12
-#define SD_DATA2_GPIO_NUM            17
-#define SD_DATA3_GPIO_NUM            16
-
-#define USB_INT_PHY0_DM_GPIO_NUM              25
-#define USB_INT_PHY0_DP_GPIO_NUM              26
-
-#define EXT_OSC_SLOW_GPIO_NUM        0
-
-#define MAX_RTC_GPIO_NUM              8
-#define MAX_PAD_GPIO_NUM             26
-#define MAX_GPIO_NUM                 30
-#define DIG_IO_HOLD_BIT_SHIFT        32
-
-
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-
-#define CLK_OUT3                                    0x1f
-#define CLK_OUT3_V                                  CLK_OUT3
-#define CLK_OUT3_S                                  10
-#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
-#define CLK_OUT2                                    0x1f
-#define CLK_OUT2_V                                  CLK_OUT2
-#define CLK_OUT2_S                                  5
-#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
-#define CLK_OUT1                                    0x1f
-#define CLK_OUT1_V                                  CLK_OUT1
-#define CLK_OUT1_S                                  0
-#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
-// definitions above are inherited from previous version of code, should double check
-
-// definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P            (REG_IO_MUX_BASE + 0x4)
-#define FUNC_XTAL_32K_P_GPIO0                                            1
-#define FUNC_XTAL_32K_P_GPIO0_0                                          0
-
-#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N            (REG_IO_MUX_BASE + 0x8)
-#define FUNC_XTAL_32K_N_GPIO1                                            1
-#define FUNC_XTAL_32K_N_GPIO1_0                                          0
-
-#define PERIPHS_IO_MUX_U_PAD_MTMS                  (REG_IO_MUX_BASE + 0xC)
-#define FUNC_MTMS_FSPIQ                                                  2
-#define FUNC_MTMS_GPIO2                                                  1
-#define FUNC_MTMS_MTMS                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_MTDI                  (REG_IO_MUX_BASE + 0x10)
-#define FUNC_MTDI_GPIO3                                                  1
-#define FUNC_MTDI_MTDI                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_MTCK                 (REG_IO_MUX_BASE + 0x14)
-#define FUNC_MTCK_FSPIHD                                                 2
-#define FUNC_MTCK_GPIO4                                                  1
-#define FUNC_MTCK_MTCK                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_MTDO                 (REG_IO_MUX_BASE + 0x18)
-#define FUNC_MTDO_FSPIWP                                                 2
-#define FUNC_MTDO_GPIO5                                                  1
-#define FUNC_MTDO_MTDO                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO6                (REG_IO_MUX_BASE + 0x1C)
-#define FUNC_GPIO6_FSPICLK                                               2
-#define FUNC_GPIO6_GPIO6                                                 1
-#define FUNC_GPIO6_GPIO6_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x20)
-#define FUNC_GPIO7_FSPID                                                 2
-#define FUNC_GPIO7_GPIO7                                                 1
-#define FUNC_GPIO7_GPIO7_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x24)
-#define FUNC_GPIO8_DAC_DSM_IN_R2                                         3
-#define FUNC_GPIO8_GPIO8                                                 1
-#define FUNC_GPIO8_GPIO8_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x28)
-#define FUNC_GPIO9_DAC_DSM_IN_R3                                         3
-#define FUNC_GPIO9_GPIO9                                                 1
-#define FUNC_GPIO9_GPIO9_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_U0TXD                (REG_IO_MUX_BASE + 0x2C)
-#define FUNC_U0TXD_GPIO10                                                1
-#define FUNC_U0TXD_U0TXD                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_U0RXD                (REG_IO_MUX_BASE + 0x30)
-#define FUNC_U0RXD_GPIO11                                                1
-#define FUNC_U0RXD_U0RXD                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA1           (REG_IO_MUX_BASE + 0x34)
-#define FUNC_SDIO_DATA1_DAC_DSM_IN_L1                                    3
-#define FUNC_SDIO_DATA1_FSPICS0                                          2
-#define FUNC_SDIO_DATA1_GPIO12                                           1
-#define FUNC_SDIO_DATA1_SDIO_DATA1                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA0           (REG_IO_MUX_BASE + 0x38)
-#define FUNC_SDIO_DATA0_DAC_DSM_IN_L0                                    3
-#define FUNC_SDIO_DATA0_FSPICS1                                          2
-#define FUNC_SDIO_DATA0_GPIO13                                           1
-#define FUNC_SDIO_DATA0_SDIO_DATA0                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_SDIO_CLK             (REG_IO_MUX_BASE + 0x3C)
-#define FUNC_SDIO_CLK_CKO_AUDIO_DAC                                      3
-#define FUNC_SDIO_CLK_FSPICS2                                            2
-#define FUNC_SDIO_CLK_GPIO14                                             1
-#define FUNC_SDIO_CLK_SDIO_CLK                                           0
-
-#define PERIPHS_IO_MUX_U_PAD_SDIO_CMD             (REG_IO_MUX_BASE + 0x40)
-#define FUNC_SDIO_CMD_CKO_PLLA                                           3
-#define FUNC_SDIO_CMD_FSPICS3                                            2
-#define FUNC_SDIO_CMD_GPIO15                                             1
-#define FUNC_SDIO_CMD_SDIO_CMD                                           0
-
-#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA3           (REG_IO_MUX_BASE + 0x44)
-#define FUNC_SDIO_DATA3_DAC_DSM_IN_L3                                    3
-#define FUNC_SDIO_DATA3_FSPICS4                                          2
-#define FUNC_SDIO_DATA3_GPIO16                                           1
-#define FUNC_SDIO_DATA3_SDIO_DATA3                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_SDIO_DATA2           (REG_IO_MUX_BASE + 0x48)
-#define FUNC_SDIO_DATA2_DAC_DSM_IN_L2                                    3
-#define FUNC_SDIO_DATA2_FSPICS5                                          2
-#define FUNC_SDIO_DATA2_GPIO17                                           1
-#define FUNC_SDIO_DATA2_SDIO_DATA2                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_SPICS0               (REG_IO_MUX_BASE + 0x4C)
-#define FUNC_SPICS0_GPIO18                                               1
-#define FUNC_SPICS0_SPICS0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_SPIQ                 (REG_IO_MUX_BASE + 0x50)
-#define FUNC_SPIQ_GPIO19                                                 1
-#define FUNC_SPIQ_SPIQ                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_SPIWP                (REG_IO_MUX_BASE + 0x54)
-#define FUNC_SPIWP_GPIO20                                                1
-#define FUNC_SPIWP_SPIWP                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_VDD_SPI              (REG_IO_MUX_BASE + 0x58)
-#define FUNC_VDD_SPI_GPIO21                                              1
-#define FUNC_VDD_SPI_GPIO21_0                                            0
-
-#define PERIPHS_IO_MUX_U_PAD_SPIHD                (REG_IO_MUX_BASE + 0x5C)
-#define FUNC_SPIHD_GPIO22                                                1
-#define FUNC_SPIHD_SPIHD                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_SPICLK               (REG_IO_MUX_BASE + 0x60)
-#define FUNC_SPICLK_GPIO23                                               1
-#define FUNC_SPICLK_SPICLK                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_SPID                 (REG_IO_MUX_BASE + 0x64)
-#define FUNC_SPID_GPIO24                                                 1
-#define FUNC_SPID_SPID                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO25               (REG_IO_MUX_BASE + 0x68)
-#define FUNC_GPIO25_GPIO25                                               1
-#define FUNC_GPIO25_GPIO25_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO26               (REG_IO_MUX_BASE + 0x6C)
-#define FUNC_GPIO26_GPIO26                                               1
-#define FUNC_GPIO26_GPIO26_0                                             0
-
-/** IO_MUX_PIN_CTRL_REG register
- *  Clock Output Configuration Register
- */
-#define IO_MUX_PIN_CTRL_REG (DR_REG_IO_MUX_BASE + 0x0)
-/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15;
- *  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
- *  CLK_OUT_out1 can be found in peripheral output signals.
- */
-#define IO_MUX_CLK_OUT1    0x0000001FU
-#define IO_MUX_CLK_OUT1_M  (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
-#define IO_MUX_CLK_OUT1_V  0x0000001FU
-#define IO_MUX_CLK_OUT1_S  0
-/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15;
- *  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
- *  CLK_OUT_out2 can be found in peripheral output signals.
- */
-#define IO_MUX_CLK_OUT2    0x0000001FU
-#define IO_MUX_CLK_OUT2_M  (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
-#define IO_MUX_CLK_OUT2_V  0x0000001FU
-#define IO_MUX_CLK_OUT2_S  5
-/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7;
- *  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
- *  CLK_OUT_out3 can be found in peripheral output signals.
- */
-#define IO_MUX_CLK_OUT3    0x0000001FU
-#define IO_MUX_CLK_OUT3_M  (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
-#define IO_MUX_CLK_OUT3_V  0x0000001FU
-#define IO_MUX_CLK_OUT3_S  10
-
-/** IO_MUX_DATE_REG register
- *  IO MUX Version Control Register
- */
-#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0xfc)
-/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36708704;
- *  Version control register
- */
-#define IO_MUX_REG_DATE    0x0FFFFFFFU
-#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
-#define IO_MUX_REG_DATE_V  0x0FFFFFFFU
-#define IO_MUX_REG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h b/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
deleted file mode 100644
index fdab268dfe..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configure Registers */
-/** Type of pin_ctrl register
- *  Clock Output Configuration Register
- */
-typedef union {
-    struct {
-        /** clk_out1 : R/W; bitpos: [4:0]; default: 15;
-         *  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
-         *  CLK_OUT_out1 can be found in peripheral output signals.
-         */
-        uint32_t clk_out1:5;
-        /** clk_out2 : R/W; bitpos: [9:5]; default: 15;
-         *  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
-         *  CLK_OUT_out2 can be found in peripheral output signals.
-         */
-        uint32_t clk_out2:5;
-        /** clk_out3 : R/W; bitpos: [14:10]; default: 7;
-         *  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
-         *  CLK_OUT_out3 can be found in peripheral output signals.
-         */
-        uint32_t clk_out3:5;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} io_mux_pin_ctrl_reg_t;
-
-/** Type of gpio register
- *  IO MUX Configure Register for pad XTAL_32K_P
- */
-typedef union {
-    struct {
-        /** mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.
-         */
-        uint32_t mcu_oe:1;
-        /** slp_sel : R/W; bitpos: [1]; default: 0;
-         *  Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-         */
-        uint32_t slp_sel:1;
-        /** mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0:
-         *  internal pull-down disabled.
-         */
-        uint32_t mcu_wpd:1;
-        /** mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0:
-         *  internal pull-up disabled.
-         */
-        uint32_t mcu_wpu:1;
-        /** mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.
-         */
-        uint32_t mcu_ie:1;
-        /** mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2:
-         *  ~20mA. 3: ~40mA.
-         */
-        uint32_t mcu_drv:2;
-        /** fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down
-         *  disabled.
-         */
-        uint32_t fun_wpd:1;
-        /** fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up
-         *  disabled.
-         */
-        uint32_t fun_wpu:1;
-        /** fun_ie : R/W; bitpos: [9]; default: 0;
-         *  Input enable of the pad. 1: input enabled. 0: input disabled.
-         */
-        uint32_t fun_ie:1;
-        /** fun_drv : R/W; bitpos: [11:10]; default: 2;
-         *  Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.
-         */
-        uint32_t fun_drv:2;
-        /** mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2.
-         *  etc.
-         */
-        uint32_t mcu_sel:3;
-        /** filter_en : R/W; bitpos: [15]; default: 0;
-         *  Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.
-         */
-        uint32_t filter_en:1;
-        /** hys_en : R/W; bitpos: [16]; default: 0;
-         *  Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0:
-         *  Hysteresis disabled.
-         */
-        uint32_t hys_en:1;
-        /** hys_sel : R/W; bitpos: [17]; default: 0;
-         *  Select enabling signals of the pad from software and efuse hardware. 1: Select
-         *  enabling signal from slftware. 0: Select enabling signal from efuse hardware.
-         */
-        uint32_t hys_sel:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} io_mux_gpio_reg_t;
-
-/** Type of date register
- *  IO MUX Version Control Register
- */
-typedef union {
-    struct {
-        /** reg_date : R/W; bitpos: [27:0]; default: 36708704;
-         *  Version control register
-         */
-        uint32_t reg_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} io_mux_date_reg_t;
-
-
-typedef struct io_mux_dev_t {
-    volatile io_mux_pin_ctrl_reg_t pin_ctrl;
-    volatile io_mux_gpio_reg_t gpio[27];
-    uint32_t reserved_070[35];
-    volatile io_mux_date_reg_t date;
-} io_mux_dev_t;
-
-extern io_mux_dev_t IO_MUX;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/keymng_reg.h b/components/soc/esp32c5/beta3/include/soc/keymng_reg.h
deleted file mode 100644
index d75565dbc8..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/keymng_reg.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** KEYMNG_CLK_REG register
- *  Key Manager clock gate control register
- */
-#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
-/** KEYMNG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Write 1 to force on register clock gate.
- */
-#define KEYMNG_CLK_EN    (BIT(0))
-#define KEYMNG_CLK_EN_M  (KEYMNG_CLK_EN_V << KEYMNG_CLK_EN_S)
-#define KEYMNG_CLK_EN_V  0x00000001U
-#define KEYMNG_CLK_EN_S  0
-/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
- *  Write 1 to force on memory clock gate.
- */
-#define KEYMNG_MEM_CG_FORCE_ON    (BIT(1))
-#define KEYMNG_MEM_CG_FORCE_ON_M  (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
-#define KEYMNG_MEM_CG_FORCE_ON_V  0x00000001U
-#define KEYMNG_MEM_CG_FORCE_ON_S  1
-
-/** KEYMNG_INT_RAW_REG register
- *  Key Manager interrupt raw register, valid in level.
- */
-#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
-/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the km_prep_done_int interrupt
- */
-#define KEYMNG_PREP_DONE_INT_RAW    (BIT(0))
-#define KEYMNG_PREP_DONE_INT_RAW_M  (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
-#define KEYMNG_PREP_DONE_INT_RAW_V  0x00000001U
-#define KEYMNG_PREP_DONE_INT_RAW_S  0
-/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the km_proc_done_int interrupt
- */
-#define KEYMNG_PROC_DONE_INT_RAW    (BIT(1))
-#define KEYMNG_PROC_DONE_INT_RAW_M  (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
-#define KEYMNG_PROC_DONE_INT_RAW_V  0x00000001U
-#define KEYMNG_PROC_DONE_INT_RAW_S  1
-/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the km_post_done_int interrupt
- */
-#define KEYMNG_POST_DONE_INT_RAW    (BIT(2))
-#define KEYMNG_POST_DONE_INT_RAW_M  (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
-#define KEYMNG_POST_DONE_INT_RAW_V  0x00000001U
-#define KEYMNG_POST_DONE_INT_RAW_S  2
-
-/** KEYMNG_INT_ST_REG register
- *  Key Manager interrupt status register.
- */
-#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
-/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the km_prep_done_int interrupt
- */
-#define KEYMNG_PREP_DONE_INT_ST    (BIT(0))
-#define KEYMNG_PREP_DONE_INT_ST_M  (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
-#define KEYMNG_PREP_DONE_INT_ST_V  0x00000001U
-#define KEYMNG_PREP_DONE_INT_ST_S  0
-/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the km_proc_done_int interrupt
- */
-#define KEYMNG_PROC_DONE_INT_ST    (BIT(1))
-#define KEYMNG_PROC_DONE_INT_ST_M  (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
-#define KEYMNG_PROC_DONE_INT_ST_V  0x00000001U
-#define KEYMNG_PROC_DONE_INT_ST_S  1
-/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the km_post_done_int interrupt
- */
-#define KEYMNG_POST_DONE_INT_ST    (BIT(2))
-#define KEYMNG_POST_DONE_INT_ST_M  (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
-#define KEYMNG_POST_DONE_INT_ST_V  0x00000001U
-#define KEYMNG_POST_DONE_INT_ST_S  2
-
-/** KEYMNG_INT_ENA_REG register
- *  Key Manager interrupt enable register.
- */
-#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
-/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the km_prep_done_int interrupt
- */
-#define KEYMNG_PREP_DONE_INT_ENA    (BIT(0))
-#define KEYMNG_PREP_DONE_INT_ENA_M  (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
-#define KEYMNG_PREP_DONE_INT_ENA_V  0x00000001U
-#define KEYMNG_PREP_DONE_INT_ENA_S  0
-/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the km_proc_done_int interrupt
- */
-#define KEYMNG_PROC_DONE_INT_ENA    (BIT(1))
-#define KEYMNG_PROC_DONE_INT_ENA_M  (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
-#define KEYMNG_PROC_DONE_INT_ENA_V  0x00000001U
-#define KEYMNG_PROC_DONE_INT_ENA_S  1
-/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the km_post_done_int interrupt
- */
-#define KEYMNG_POST_DONE_INT_ENA    (BIT(2))
-#define KEYMNG_POST_DONE_INT_ENA_M  (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
-#define KEYMNG_POST_DONE_INT_ENA_V  0x00000001U
-#define KEYMNG_POST_DONE_INT_ENA_S  2
-
-/** KEYMNG_INT_CLR_REG register
- *  Key Manager interrupt clear register.
- */
-#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
-/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the km_prep_done_int interrupt
- */
-#define KEYMNG_PREP_DONE_INT_CLR    (BIT(0))
-#define KEYMNG_PREP_DONE_INT_CLR_M  (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
-#define KEYMNG_PREP_DONE_INT_CLR_V  0x00000001U
-#define KEYMNG_PREP_DONE_INT_CLR_S  0
-/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the km_proc_done_int interrupt
- */
-#define KEYMNG_PROC_DONE_INT_CLR    (BIT(1))
-#define KEYMNG_PROC_DONE_INT_CLR_M  (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
-#define KEYMNG_PROC_DONE_INT_CLR_V  0x00000001U
-#define KEYMNG_PROC_DONE_INT_CLR_S  1
-/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the km_post_done_int interrupt
- */
-#define KEYMNG_POST_DONE_INT_CLR    (BIT(2))
-#define KEYMNG_POST_DONE_INT_CLR_M  (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
-#define KEYMNG_POST_DONE_INT_CLR_V  0x00000001U
-#define KEYMNG_POST_DONE_INT_CLR_S  2
-
-/** KEYMNG_STATIC_REG register
- *  Key Manager static configuration register
- */
-#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
-/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [1:0]; default: 0;
- *  Set each bit to choose efuse key instead of key manager deployed key. Each bit
- *  stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
- */
-#define KEYMNG_USE_EFUSE_KEY    0x00000003U
-#define KEYMNG_USE_EFUSE_KEY_M  (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
-#define KEYMNG_USE_EFUSE_KEY_V  0x00000003U
-#define KEYMNG_USE_EFUSE_KEY_S  0
-/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [8:4]; default: 15;
- *  The core clock cycle number to sample one rng input data. Please set it bigger than
- *  the clock cycle ratio: T_rng/T_km
- */
-#define KEYMNG_RND_SWITCH_CYCLE    0x0000001FU
-#define KEYMNG_RND_SWITCH_CYCLE_M  (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
-#define KEYMNG_RND_SWITCH_CYCLE_V  0x0000001FU
-#define KEYMNG_RND_SWITCH_CYCLE_S  4
-/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [9]; default: 0;
- *  Set this bit to use software written init key instead of efuse_init_key.
- */
-#define KEYMNG_USE_SW_INIT_KEY    (BIT(9))
-#define KEYMNG_USE_SW_INIT_KEY_M  (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
-#define KEYMNG_USE_SW_INIT_KEY_V  0x00000001U
-#define KEYMNG_USE_SW_INIT_KEY_S  9
-/** KEYMNG_XTS_AES_KEY_LEN : R/W; bitpos: [10]; default: 0;
- *  Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
- *  xts-aes-128.
- */
-#define KEYMNG_XTS_AES_KEY_LEN    (BIT(10))
-#define KEYMNG_XTS_AES_KEY_LEN_M  (KEYMNG_XTS_AES_KEY_LEN_V << KEYMNG_XTS_AES_KEY_LEN_S)
-#define KEYMNG_XTS_AES_KEY_LEN_V  0x00000001U
-#define KEYMNG_XTS_AES_KEY_LEN_S  10
-
-/** KEYMNG_LOCK_REG register
- *  Key Manager static configuration locker register
- */
-#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
-/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [1:0]; default: 0;
- *  Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
- *  reg_use_efuse_key.
- */
-#define KEYMNG_USE_EFUSE_KEY_LOCK    0x00000003U
-#define KEYMNG_USE_EFUSE_KEY_LOCK_M  (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
-#define KEYMNG_USE_EFUSE_KEY_LOCK_V  0x00000003U
-#define KEYMNG_USE_EFUSE_KEY_LOCK_S  0
-/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [4]; default: 0;
- *  Write 1 to lock reg_rnd_switch_cycle.
- */
-#define KEYMNG_RND_SWITCH_CYCLE_LOCK    (BIT(4))
-#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M  (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
-#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V  0x00000001U
-#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S  4
-/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [5]; default: 0;
- *  Write 1 to lock reg_use_sw_init_key.
- */
-#define KEYMNG_USE_SW_INIT_KEY_LOCK    (BIT(5))
-#define KEYMNG_USE_SW_INIT_KEY_LOCK_M  (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
-#define KEYMNG_USE_SW_INIT_KEY_LOCK_V  0x00000001U
-#define KEYMNG_USE_SW_INIT_KEY_LOCK_S  5
-/** KEYMNG_XTS_AES_KEY_LEN_LOCK : R/W1; bitpos: [6]; default: 0;
- *  Write 1 to lock reg_xts_aes_key_len.
- */
-#define KEYMNG_XTS_AES_KEY_LEN_LOCK    (BIT(6))
-#define KEYMNG_XTS_AES_KEY_LEN_LOCK_M  (KEYMNG_XTS_AES_KEY_LEN_LOCK_V << KEYMNG_XTS_AES_KEY_LEN_LOCK_S)
-#define KEYMNG_XTS_AES_KEY_LEN_LOCK_V  0x00000001U
-#define KEYMNG_XTS_AES_KEY_LEN_LOCK_S  6
-
-/** KEYMNG_CONF_REG register
- *  Key Manager configuration register
- */
-#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
-/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
- *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
- */
-#define KEYMNG_KGEN_MODE    0x00000007U
-#define KEYMNG_KGEN_MODE_M  (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
-#define KEYMNG_KGEN_MODE_V  0x00000007U
-#define KEYMNG_KGEN_MODE_S  0
-/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
- *  Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
- *  xts_256_2_key. 4. xts_128_key. others: reserved.
- */
-#define KEYMNG_KEY_PURPOSE    0x0000000FU
-#define KEYMNG_KEY_PURPOSE_M  (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
-#define KEYMNG_KEY_PURPOSE_V  0x0000000FU
-#define KEYMNG_KEY_PURPOSE_S  3
-
-/** KEYMNG_START_REG register
- *  Key Manager control register
- */
-#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
-/** KEYMNG_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
- */
-#define KEYMNG_START    (BIT(0))
-#define KEYMNG_START_M  (KEYMNG_START_V << KEYMNG_START_S)
-#define KEYMNG_START_V  0x00000001U
-#define KEYMNG_START_S  0
-/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
- *  Write 1 to start Key Manager at IDLE state.
- */
-#define KEYMNG_CONTINUE    (BIT(1))
-#define KEYMNG_CONTINUE_M  (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
-#define KEYMNG_CONTINUE_V  0x00000001U
-#define KEYMNG_CONTINUE_S  1
-
-/** KEYMNG_STATE_REG register
- *  Key Manager state register
- */
-#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
-/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
- *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
- */
-#define KEYMNG_STATE    0x00000003U
-#define KEYMNG_STATE_M  (KEYMNG_STATE_V << KEYMNG_STATE_S)
-#define KEYMNG_STATE_V  0x00000003U
-#define KEYMNG_STATE_S  0
-
-/** KEYMNG_RESULT_REG register
- *  Key Manager operation result register
- */
-#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
-/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
- *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
- *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
- */
-#define KEYMNG_PROC_RESULT    (BIT(0))
-#define KEYMNG_PROC_RESULT_M  (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
-#define KEYMNG_PROC_RESULT_V  0x00000001U
-#define KEYMNG_PROC_RESULT_S  0
-
-/** KEYMNG_KEY_VLD_REG register
- *  Key Manager key status register
- */
-#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
-/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0;
- *  The status bit for key_ecdsa.   1: The key has been deployed correctly. 0: The key
- *  has not been deployed yet.
- */
-#define KEYMNG_KEY_ECDSA_VLD    (BIT(0))
-#define KEYMNG_KEY_ECDSA_VLD_M  (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S)
-#define KEYMNG_KEY_ECDSA_VLD_V  0x00000001U
-#define KEYMNG_KEY_ECDSA_VLD_S  0
-/** KEYMNG_KEY_XTS_VLD : RO; bitpos: [1]; default: 0;
- *  The status bit for key_xts.        1: The key has been deployed correctly. 0: The
- *  key has not been deployed yet.
- */
-#define KEYMNG_KEY_XTS_VLD    (BIT(1))
-#define KEYMNG_KEY_XTS_VLD_M  (KEYMNG_KEY_XTS_VLD_V << KEYMNG_KEY_XTS_VLD_S)
-#define KEYMNG_KEY_XTS_VLD_V  0x00000001U
-#define KEYMNG_KEY_XTS_VLD_S  1
-
-/** KEYMNG_HUK_VLD_REG register
- *  Key Manager HUK status register
- */
-#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
-/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
- *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
- */
-#define KEYMNG_HUK_VALID    (BIT(0))
-#define KEYMNG_HUK_VALID_M  (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
-#define KEYMNG_HUK_VALID_V  0x00000001U
-#define KEYMNG_HUK_VALID_S  0
-
-/** KEYMNG_DATE_REG register
- *  Version control register
- */
-#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
-/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36720704;
- *  Key Manager version control register.
- */
-#define KEYMNG_DATE    0x0FFFFFFFU
-#define KEYMNG_DATE_M  (KEYMNG_DATE_V << KEYMNG_DATE_S)
-#define KEYMNG_DATE_V  0x0FFFFFFFU
-#define KEYMNG_DATE_S  0
-
-/** KEYMNG_ASSIST_INFO_MEM register
- *  The memory that stores assist key info.
- */
-#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
-#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
-
-/** KEYMNG_PUBLIC_INFO_MEM register
- *  The memory that stores public key info.
- */
-#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
-#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
-
-/** KEYMNG_SW_INIT_KEY_MEM register
- *  The memory that stores software written init key.
- */
-#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
-#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/keymng_struct.h b/components/soc/esp32c5/beta3/include/soc/keymng_struct.h
deleted file mode 100644
index 47f0630b99..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/keymng_struct.h
+++ /dev/null
@@ -1,340 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory data */
-
-/** Group: Clock gate register */
-/** Type of clk register
- *  Key Manager clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_en:1;
-        /** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to force on memory clock gate.
-         */
-        uint32_t mem_cg_force_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} keymng_clk_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  Key Manager interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the km_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_raw:1;
-        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the km_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_raw:1;
-        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the km_post_done_int interrupt
-         */
-        uint32_t post_done_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} keymng_int_raw_reg_t;
-
-/** Type of int_st register
- *  Key Manager interrupt status register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the km_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_st:1;
-        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the km_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_st:1;
-        /** post_done_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the km_post_done_int interrupt
-         */
-        uint32_t post_done_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} keymng_int_st_reg_t;
-
-/** Type of int_ena register
- *  Key Manager interrupt enable register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the km_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_ena:1;
-        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the km_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_ena:1;
-        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the km_post_done_int interrupt
-         */
-        uint32_t post_done_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} keymng_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Key Manager interrupt clear register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the km_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_clr:1;
-        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the km_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_clr:1;
-        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the km_post_done_int interrupt
-         */
-        uint32_t post_done_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} keymng_int_clr_reg_t;
-
-
-/** Group: Static configuration registers */
-/** Type of static register
- *  Key Manager static configuration register
- */
-typedef union {
-    struct {
-        /** use_efuse_key : R/W; bitpos: [1:0]; default: 0;
-         *  Set each bit to choose efuse key instead of key manager deployed key. Each bit
-         *  stands for a key type: bit 1 for xts_key; bit 0 for ecdsa_key
-         */
-        uint32_t use_efuse_key:2;
-        uint32_t reserved_2:2;
-        /** rnd_switch_cycle : R/W; bitpos: [8:4]; default: 15;
-         *  The core clock cycle number to sample one rng input data. Please set it bigger than
-         *  the clock cycle ratio: T_rng/T_km
-         */
-        uint32_t rnd_switch_cycle:5;
-        /** use_sw_init_key : R/W; bitpos: [9]; default: 0;
-         *  Set this bit to use software written init key instead of efuse_init_key.
-         */
-        uint32_t use_sw_init_key:1;
-        /** xts_aes_key_len : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to choose using xts-aes-256 or xts-aes-128. 1: use xts-aes-256. 0: use
-         *  xts-aes-128.
-         */
-        uint32_t xts_aes_key_len:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} keymng_static_reg_t;
-
-/** Type of lock register
- *  Key Manager static configuration locker register
- */
-typedef union {
-    struct {
-        /** use_efuse_key_lock : R/W1; bitpos: [1:0]; default: 0;
-         *  Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
-         *  reg_use_efuse_key.
-         */
-        uint32_t use_efuse_key_lock:2;
-        uint32_t reserved_2:2;
-        /** rnd_switch_cycle_lock : R/W1; bitpos: [4]; default: 0;
-         *  Write 1 to lock reg_rnd_switch_cycle.
-         */
-        uint32_t rnd_switch_cycle_lock:1;
-        /** use_sw_init_key_lock : R/W1; bitpos: [5]; default: 0;
-         *  Write 1 to lock reg_use_sw_init_key.
-         */
-        uint32_t use_sw_init_key_lock:1;
-        /** xts_aes_key_len_lock : R/W1; bitpos: [6]; default: 0;
-         *  Write 1 to lock reg_xts_aes_key_len.
-         */
-        uint32_t xts_aes_key_len_lock:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} keymng_lock_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of conf register
- *  Key Manager configuration register
- */
-typedef union {
-    struct {
-        /** kgen_mode : R/W; bitpos: [2:0]; default: 0;
-         *  Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
-         *  mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
-         */
-        uint32_t kgen_mode:3;
-        /** key_purpose : R/W; bitpos: [6:3]; default: 0;
-         *  Set this field to choose the key purpose. 1: ecdsa_key 2: xts_256_1_key. 3:
-         *  xts_256_2_key. 4. xts_128_key. others: reserved.
-         */
-        uint32_t key_purpose:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} keymng_conf_reg_t;
-
-
-/** Group: Control registers */
-/** Type of start register
- *  Key Manager control register
- */
-typedef union {
-    struct {
-        /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start Key Manager at IDLE state.
-         */
-        uint32_t start:1;
-        /** conti : WT; bitpos: [1]; default: 0;
-         *  Write 1 to continue Key Manager operation at LOAD/GAIN state.
-         */
-        uint32_t conti:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} keymng_start_reg_t;
-
-
-/** Group: State registers */
-/** Type of state register
- *  Key Manager state register
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [1:0]; default: 0;
-         *  The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
-         */
-        uint32_t state:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} keymng_state_reg_t;
-
-
-/** Group: Result registers */
-/** Type of result register
- *  Key Manager operation result register
- */
-typedef union {
-    struct {
-        /** proc_result : RO/SS; bitpos: [0]; default: 0;
-         *  The procedure result bit of Key Manager, only valid when Key Manager procedure is
-         *  done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
-         */
-        uint32_t proc_result:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} keymng_result_reg_t;
-
-/** Type of key_vld register
- *  Key Manager key status register
- */
-typedef union {
-    struct {
-        /** key_ecdsa_vld : RO; bitpos: [0]; default: 0;
-         *  The status bit for key_ecdsa.   1: The key has been deployed correctly. 0: The key
-         *  has not been deployed yet.
-         */
-        uint32_t key_ecdsa_vld:1;
-        /** key_xts_vld : RO; bitpos: [1]; default: 0;
-         *  The status bit for key_xts.        1: The key has been deployed correctly. 0: The
-         *  key has not been deployed yet.
-         */
-        uint32_t key_xts_vld:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} keymng_key_vld_reg_t;
-
-/** Type of huk_vld register
- *  Key Manager HUK status register
- */
-typedef union {
-    struct {
-        /** huk_valid : RO; bitpos: [0]; default: 0;
-         *  The HUK status. 0: HUK is not valid. 1: HUK is valid.
-         */
-        uint32_t huk_valid:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} keymng_huk_vld_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720704;
-         *  Key Manager version control register.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} keymng_date_reg_t;
-
-
-typedef struct keymng_dev_t {
-    uint32_t reserved_000;
-    volatile keymng_clk_reg_t clk;
-    volatile keymng_int_raw_reg_t int_raw;
-    volatile keymng_int_st_reg_t int_st;
-    volatile keymng_int_ena_reg_t int_ena;
-    volatile keymng_int_clr_reg_t int_clr;
-    volatile keymng_static_reg_t static_cfg;
-    volatile keymng_lock_reg_t lock;
-    volatile keymng_conf_reg_t conf;
-    volatile keymng_start_reg_t start;
-    volatile keymng_state_reg_t state;
-    volatile keymng_result_reg_t result;
-    volatile keymng_key_vld_reg_t key_vld;
-    volatile keymng_huk_vld_reg_t huk_vld;
-    uint32_t reserved_038[49];
-    volatile keymng_date_reg_t date;
-    volatile uint32_t assist_info[16];
-    volatile uint32_t public_info[16];
-    volatile uint32_t sw_init_key[8];
-} keymng_dev_t;
-
-extern keymng_dev_t KEYMNG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ledc_reg.h b/components/soc/esp32c5/beta3/include/soc/ledc_reg.h
deleted file mode 100644
index 6f13034d72..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ledc_reg.h
+++ /dev/null
@@ -1,2334 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LEDC_CH0_CONF0_REG register
- *  Configuration register 0 for channel 0
- */
-#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0)
-/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
- *  Configures which timer is channel 0 selected.\\0: Select timer0\\1: Select
- *  timer1\\2: Select timer2\\3: Select timer3
- */
-#define LEDC_TIMER_SEL_CH0    0x00000003U
-#define LEDC_TIMER_SEL_CH0_M  (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S)
-#define LEDC_TIMER_SEL_CH0_V  0x00000003U
-#define LEDC_TIMER_SEL_CH0_S  0
-/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable signal output on channel 0.\\0: Signal output
- *  disable\\1: Signal output enable
- */
-#define LEDC_SIG_OUT_EN_CH0    (BIT(2))
-#define LEDC_SIG_OUT_EN_CH0_M  (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S)
-#define LEDC_SIG_OUT_EN_CH0_V  0x00000001U
-#define LEDC_SIG_OUT_EN_CH0_S  2
-/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0;
- *  Configures the output value when channel 0 is inactive. Valid only when
- *  LEDC_SIG_OUT_EN_CH0 is 0.\\0: Output level is low\\1: Output level is high
- */
-#define LEDC_IDLE_LV_CH0    (BIT(3))
-#define LEDC_IDLE_LV_CH0_M  (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S)
-#define LEDC_IDLE_LV_CH0_V  0x00000001U
-#define LEDC_IDLE_LV_CH0_S  3
-/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to update LEDC_HPOINT_CH0, LEDC_DUTY_START_CH0,
- *  LEDC_SIG_OUT_EN_CH0, LEDC_TIMER_SEL_CH0, LEDC_DUTY_NUM_CH0, LEDC_DUTY_CYCLE_CH0,
- *  LEDC_DUTY_SCALE_CH0, LEDC_DUTY_INC_CH0, and LEDC_OVF_CNT_EN_CH0 fields for channel
- *  0, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_PARA_UP_CH0    (BIT(4))
-#define LEDC_PARA_UP_CH0_M  (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S)
-#define LEDC_PARA_UP_CH0_V  0x00000001U
-#define LEDC_PARA_UP_CH0_S  4
-/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0;
- *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH0_INT interrupt
- *  will be triggered when channel 0 overflows for (LEDC_OVF_NUM_CH0 + 1) times.
- */
-#define LEDC_OVF_NUM_CH0    0x000003FFU
-#define LEDC_OVF_NUM_CH0_M  (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S)
-#define LEDC_OVF_NUM_CH0_V  0x000003FFU
-#define LEDC_OVF_NUM_CH0_S  5
-/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the ovf_cnt of channel 0.\\0: Disable\\1: Enable
- */
-#define LEDC_OVF_CNT_EN_CH0    (BIT(15))
-#define LEDC_OVF_CNT_EN_CH0_M  (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S)
-#define LEDC_OVF_CNT_EN_CH0_V  0x00000001U
-#define LEDC_OVF_CNT_EN_CH0_S  15
-/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to reset the  ovf_cnt of channel 0.\\0: Invalid. No
- *  effect\\1: Reset the ovf_cnt
- */
-#define LEDC_OVF_CNT_RESET_CH0    (BIT(16))
-#define LEDC_OVF_CNT_RESET_CH0_M  (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S)
-#define LEDC_OVF_CNT_RESET_CH0_V  0x00000001U
-#define LEDC_OVF_CNT_RESET_CH0_S  16
-
-/** LEDC_CH0_HPOINT_REG register
- *  High point register for channel 0
- */
-#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4)
-/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0;
- *  Configures high point of signal output on channel 0. The output value changes to
- *  high when the selected timers has reached the value specified by this register.
- */
-#define LEDC_HPOINT_CH0    0x000FFFFFU
-#define LEDC_HPOINT_CH0_M  (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S)
-#define LEDC_HPOINT_CH0_V  0x000FFFFFU
-#define LEDC_HPOINT_CH0_S  0
-
-/** LEDC_CH0_DUTY_REG register
- *  Initial duty cycle register for channel 0
- */
-#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8)
-/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0;
- *  Configures the duty of signal output on channel 0.
- */
-#define LEDC_DUTY_CH0    0x01FFFFFFU
-#define LEDC_DUTY_CH0_M  (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S)
-#define LEDC_DUTY_CH0_V  0x01FFFFFFU
-#define LEDC_DUTY_CH0_S  0
-
-/** LEDC_CH0_CONF1_REG register
- *  Configuration register 1 for channel 0
- */
-#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc)
-/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0;
- *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
- *  effect\\1: Take effect
- */
-#define LEDC_DUTY_START_CH0    (BIT(31))
-#define LEDC_DUTY_START_CH0_M  (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S)
-#define LEDC_DUTY_START_CH0_V  0x00000001U
-#define LEDC_DUTY_START_CH0_S  31
-
-/** LEDC_CH0_DUTY_R_REG register
- *  Current duty cycle register for channel 0
- */
-#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10)
-/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0;
- *  Represents the current duty of output signal on channel 0.
- */
-#define LEDC_DUTY_CH0_R    0x01FFFFFFU
-#define LEDC_DUTY_CH0_R_M  (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S)
-#define LEDC_DUTY_CH0_R_V  0x01FFFFFFU
-#define LEDC_DUTY_CH0_R_S  0
-
-/** LEDC_CH1_CONF0_REG register
- *  Configuration register 0 for channel 1
- */
-#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14)
-/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
- *  Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select
- *  timer1\\2: Select timer2\\3: Select timer3
- */
-#define LEDC_TIMER_SEL_CH1    0x00000003U
-#define LEDC_TIMER_SEL_CH1_M  (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S)
-#define LEDC_TIMER_SEL_CH1_V  0x00000003U
-#define LEDC_TIMER_SEL_CH1_S  0
-/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable signal output on channel 1.\\0: Signal output
- *  disable\\1: Signal output enable
- */
-#define LEDC_SIG_OUT_EN_CH1    (BIT(2))
-#define LEDC_SIG_OUT_EN_CH1_M  (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S)
-#define LEDC_SIG_OUT_EN_CH1_V  0x00000001U
-#define LEDC_SIG_OUT_EN_CH1_S  2
-/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0;
- *  Configures the output value when channel 1 is inactive. Valid only when
- *  LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high
- */
-#define LEDC_IDLE_LV_CH1    (BIT(3))
-#define LEDC_IDLE_LV_CH1_M  (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S)
-#define LEDC_IDLE_LV_CH1_V  0x00000001U
-#define LEDC_IDLE_LV_CH1_S  3
-/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1,
- *  LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1,
- *  LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel
- *  1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_PARA_UP_CH1    (BIT(4))
-#define LEDC_PARA_UP_CH1_M  (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S)
-#define LEDC_PARA_UP_CH1_V  0x00000001U
-#define LEDC_PARA_UP_CH1_S  4
-/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0;
- *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt
- *  will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times.
- */
-#define LEDC_OVF_NUM_CH1    0x000003FFU
-#define LEDC_OVF_NUM_CH1_M  (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S)
-#define LEDC_OVF_NUM_CH1_V  0x000003FFU
-#define LEDC_OVF_NUM_CH1_S  5
-/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable
- */
-#define LEDC_OVF_CNT_EN_CH1    (BIT(15))
-#define LEDC_OVF_CNT_EN_CH1_M  (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S)
-#define LEDC_OVF_CNT_EN_CH1_V  0x00000001U
-#define LEDC_OVF_CNT_EN_CH1_S  15
-/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to reset the  ovf_cnt of channel 1.\\0: Invalid. No
- *  effect\\1: Reset the ovf_cnt
- */
-#define LEDC_OVF_CNT_RESET_CH1    (BIT(16))
-#define LEDC_OVF_CNT_RESET_CH1_M  (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S)
-#define LEDC_OVF_CNT_RESET_CH1_V  0x00000001U
-#define LEDC_OVF_CNT_RESET_CH1_S  16
-
-/** LEDC_CH1_HPOINT_REG register
- *  High point register for channel 1
- */
-#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18)
-/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0;
- *  Configures high point of signal output on channel 1. The output value changes to
- *  high when the selected timers has reached the value specified by this register.
- */
-#define LEDC_HPOINT_CH1    0x000FFFFFU
-#define LEDC_HPOINT_CH1_M  (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S)
-#define LEDC_HPOINT_CH1_V  0x000FFFFFU
-#define LEDC_HPOINT_CH1_S  0
-
-/** LEDC_CH1_DUTY_REG register
- *  Initial duty cycle register for channel 1
- */
-#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c)
-/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0;
- *  Configures the duty of signal output on channel 1.
- */
-#define LEDC_DUTY_CH1    0x01FFFFFFU
-#define LEDC_DUTY_CH1_M  (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S)
-#define LEDC_DUTY_CH1_V  0x01FFFFFFU
-#define LEDC_DUTY_CH1_S  0
-
-/** LEDC_CH1_CONF1_REG register
- *  Configuration register 1 for channel 1
- */
-#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20)
-/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0;
- *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
- *  effect\\1: Take effect
- */
-#define LEDC_DUTY_START_CH1    (BIT(31))
-#define LEDC_DUTY_START_CH1_M  (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S)
-#define LEDC_DUTY_START_CH1_V  0x00000001U
-#define LEDC_DUTY_START_CH1_S  31
-
-/** LEDC_CH1_DUTY_R_REG register
- *  Current duty cycle register for channel 1
- */
-#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24)
-/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0;
- *  Represents the current duty of output signal on channel 1.
- */
-#define LEDC_DUTY_CH1_R    0x01FFFFFFU
-#define LEDC_DUTY_CH1_R_M  (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S)
-#define LEDC_DUTY_CH1_R_V  0x01FFFFFFU
-#define LEDC_DUTY_CH1_R_S  0
-
-/** LEDC_CH2_CONF0_REG register
- *  Configuration register 0 for channel 2
- */
-#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28)
-/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
- *  Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select
- *  timer1\\2: Select timer2\\3: Select timer3
- */
-#define LEDC_TIMER_SEL_CH2    0x00000003U
-#define LEDC_TIMER_SEL_CH2_M  (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S)
-#define LEDC_TIMER_SEL_CH2_V  0x00000003U
-#define LEDC_TIMER_SEL_CH2_S  0
-/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable signal output on channel 2.\\0: Signal output
- *  disable\\1: Signal output enable
- */
-#define LEDC_SIG_OUT_EN_CH2    (BIT(2))
-#define LEDC_SIG_OUT_EN_CH2_M  (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S)
-#define LEDC_SIG_OUT_EN_CH2_V  0x00000001U
-#define LEDC_SIG_OUT_EN_CH2_S  2
-/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0;
- *  Configures the output value when channel 2 is inactive. Valid only when
- *  LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high
- */
-#define LEDC_IDLE_LV_CH2    (BIT(3))
-#define LEDC_IDLE_LV_CH2_M  (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S)
-#define LEDC_IDLE_LV_CH2_V  0x00000001U
-#define LEDC_IDLE_LV_CH2_S  3
-/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2,
- *  LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2,
- *  LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel
- *  2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_PARA_UP_CH2    (BIT(4))
-#define LEDC_PARA_UP_CH2_M  (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S)
-#define LEDC_PARA_UP_CH2_V  0x00000001U
-#define LEDC_PARA_UP_CH2_S  4
-/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0;
- *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt
- *  will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times.
- */
-#define LEDC_OVF_NUM_CH2    0x000003FFU
-#define LEDC_OVF_NUM_CH2_M  (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S)
-#define LEDC_OVF_NUM_CH2_V  0x000003FFU
-#define LEDC_OVF_NUM_CH2_S  5
-/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable
- */
-#define LEDC_OVF_CNT_EN_CH2    (BIT(15))
-#define LEDC_OVF_CNT_EN_CH2_M  (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S)
-#define LEDC_OVF_CNT_EN_CH2_V  0x00000001U
-#define LEDC_OVF_CNT_EN_CH2_S  15
-/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to reset the  ovf_cnt of channel 2.\\0: Invalid. No
- *  effect\\1: Reset the ovf_cnt
- */
-#define LEDC_OVF_CNT_RESET_CH2    (BIT(16))
-#define LEDC_OVF_CNT_RESET_CH2_M  (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S)
-#define LEDC_OVF_CNT_RESET_CH2_V  0x00000001U
-#define LEDC_OVF_CNT_RESET_CH2_S  16
-
-/** LEDC_CH2_HPOINT_REG register
- *  High point register for channel 2
- */
-#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c)
-/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0;
- *  Configures high point of signal output on channel 2. The output value changes to
- *  high when the selected timers has reached the value specified by this register.
- */
-#define LEDC_HPOINT_CH2    0x000FFFFFU
-#define LEDC_HPOINT_CH2_M  (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S)
-#define LEDC_HPOINT_CH2_V  0x000FFFFFU
-#define LEDC_HPOINT_CH2_S  0
-
-/** LEDC_CH2_DUTY_REG register
- *  Initial duty cycle register for channel 2
- */
-#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30)
-/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0;
- *  Configures the duty of signal output on channel 2.
- */
-#define LEDC_DUTY_CH2    0x01FFFFFFU
-#define LEDC_DUTY_CH2_M  (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S)
-#define LEDC_DUTY_CH2_V  0x01FFFFFFU
-#define LEDC_DUTY_CH2_S  0
-
-/** LEDC_CH2_CONF1_REG register
- *  Configuration register 1 for channel 2
- */
-#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34)
-/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0;
- *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
- *  effect\\1: Take effect
- */
-#define LEDC_DUTY_START_CH2    (BIT(31))
-#define LEDC_DUTY_START_CH2_M  (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S)
-#define LEDC_DUTY_START_CH2_V  0x00000001U
-#define LEDC_DUTY_START_CH2_S  31
-
-/** LEDC_CH2_DUTY_R_REG register
- *  Current duty cycle register for channel 2
- */
-#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38)
-/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0;
- *  Represents the current duty of output signal on channel 2.
- */
-#define LEDC_DUTY_CH2_R    0x01FFFFFFU
-#define LEDC_DUTY_CH2_R_M  (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S)
-#define LEDC_DUTY_CH2_R_V  0x01FFFFFFU
-#define LEDC_DUTY_CH2_R_S  0
-
-/** LEDC_CH3_CONF0_REG register
- *  Configuration register 0 for channel 3
- */
-#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c)
-/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0;
- *  Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select
- *  timer1\\2: Select timer2\\3: Select timer3
- */
-#define LEDC_TIMER_SEL_CH3    0x00000003U
-#define LEDC_TIMER_SEL_CH3_M  (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S)
-#define LEDC_TIMER_SEL_CH3_V  0x00000003U
-#define LEDC_TIMER_SEL_CH3_S  0
-/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable signal output on channel 3.\\0: Signal output
- *  disable\\1: Signal output enable
- */
-#define LEDC_SIG_OUT_EN_CH3    (BIT(2))
-#define LEDC_SIG_OUT_EN_CH3_M  (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S)
-#define LEDC_SIG_OUT_EN_CH3_V  0x00000001U
-#define LEDC_SIG_OUT_EN_CH3_S  2
-/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0;
- *  Configures the output value when channel 3 is inactive. Valid only when
- *  LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high
- */
-#define LEDC_IDLE_LV_CH3    (BIT(3))
-#define LEDC_IDLE_LV_CH3_M  (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S)
-#define LEDC_IDLE_LV_CH3_V  0x00000001U
-#define LEDC_IDLE_LV_CH3_S  3
-/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3,
- *  LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3,
- *  LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel
- *  3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_PARA_UP_CH3    (BIT(4))
-#define LEDC_PARA_UP_CH3_M  (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S)
-#define LEDC_PARA_UP_CH3_V  0x00000001U
-#define LEDC_PARA_UP_CH3_S  4
-/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0;
- *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt
- *  will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times.
- */
-#define LEDC_OVF_NUM_CH3    0x000003FFU
-#define LEDC_OVF_NUM_CH3_M  (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S)
-#define LEDC_OVF_NUM_CH3_V  0x000003FFU
-#define LEDC_OVF_NUM_CH3_S  5
-/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable
- */
-#define LEDC_OVF_CNT_EN_CH3    (BIT(15))
-#define LEDC_OVF_CNT_EN_CH3_M  (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S)
-#define LEDC_OVF_CNT_EN_CH3_V  0x00000001U
-#define LEDC_OVF_CNT_EN_CH3_S  15
-/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to reset the  ovf_cnt of channel 3.\\0: Invalid. No
- *  effect\\1: Reset the ovf_cnt
- */
-#define LEDC_OVF_CNT_RESET_CH3    (BIT(16))
-#define LEDC_OVF_CNT_RESET_CH3_M  (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S)
-#define LEDC_OVF_CNT_RESET_CH3_V  0x00000001U
-#define LEDC_OVF_CNT_RESET_CH3_S  16
-
-/** LEDC_CH3_HPOINT_REG register
- *  High point register for channel 3
- */
-#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40)
-/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0;
- *  Configures high point of signal output on channel 3. The output value changes to
- *  high when the selected timers has reached the value specified by this register.
- */
-#define LEDC_HPOINT_CH3    0x000FFFFFU
-#define LEDC_HPOINT_CH3_M  (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S)
-#define LEDC_HPOINT_CH3_V  0x000FFFFFU
-#define LEDC_HPOINT_CH3_S  0
-
-/** LEDC_CH3_DUTY_REG register
- *  Initial duty cycle register for channel 3
- */
-#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44)
-/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0;
- *  Configures the duty of signal output on channel 3.
- */
-#define LEDC_DUTY_CH3    0x01FFFFFFU
-#define LEDC_DUTY_CH3_M  (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S)
-#define LEDC_DUTY_CH3_V  0x01FFFFFFU
-#define LEDC_DUTY_CH3_S  0
-
-/** LEDC_CH3_CONF1_REG register
- *  Configuration register 1 for channel 3
- */
-#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48)
-/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0;
- *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
- *  effect\\1: Take effect
- */
-#define LEDC_DUTY_START_CH3    (BIT(31))
-#define LEDC_DUTY_START_CH3_M  (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S)
-#define LEDC_DUTY_START_CH3_V  0x00000001U
-#define LEDC_DUTY_START_CH3_S  31
-
-/** LEDC_CH3_DUTY_R_REG register
- *  Current duty cycle register for channel 3
- */
-#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c)
-/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0;
- *  Represents the current duty of output signal on channel 3.
- */
-#define LEDC_DUTY_CH3_R    0x01FFFFFFU
-#define LEDC_DUTY_CH3_R_M  (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S)
-#define LEDC_DUTY_CH3_R_V  0x01FFFFFFU
-#define LEDC_DUTY_CH3_R_S  0
-
-/** LEDC_CH4_CONF0_REG register
- *  Configuration register 0 for channel 4
- */
-#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50)
-/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0;
- *  Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select
- *  timer1\\2: Select timer2\\3: Select timer3
- */
-#define LEDC_TIMER_SEL_CH4    0x00000003U
-#define LEDC_TIMER_SEL_CH4_M  (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S)
-#define LEDC_TIMER_SEL_CH4_V  0x00000003U
-#define LEDC_TIMER_SEL_CH4_S  0
-/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable signal output on channel 4.\\0: Signal output
- *  disable\\1: Signal output enable
- */
-#define LEDC_SIG_OUT_EN_CH4    (BIT(2))
-#define LEDC_SIG_OUT_EN_CH4_M  (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S)
-#define LEDC_SIG_OUT_EN_CH4_V  0x00000001U
-#define LEDC_SIG_OUT_EN_CH4_S  2
-/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0;
- *  Configures the output value when channel 4 is inactive. Valid only when
- *  LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high
- */
-#define LEDC_IDLE_LV_CH4    (BIT(3))
-#define LEDC_IDLE_LV_CH4_M  (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S)
-#define LEDC_IDLE_LV_CH4_V  0x00000001U
-#define LEDC_IDLE_LV_CH4_S  3
-/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4,
- *  LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4,
- *  LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel
- *  4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_PARA_UP_CH4    (BIT(4))
-#define LEDC_PARA_UP_CH4_M  (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S)
-#define LEDC_PARA_UP_CH4_V  0x00000001U
-#define LEDC_PARA_UP_CH4_S  4
-/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0;
- *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt
- *  will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times.
- */
-#define LEDC_OVF_NUM_CH4    0x000003FFU
-#define LEDC_OVF_NUM_CH4_M  (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S)
-#define LEDC_OVF_NUM_CH4_V  0x000003FFU
-#define LEDC_OVF_NUM_CH4_S  5
-/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable
- */
-#define LEDC_OVF_CNT_EN_CH4    (BIT(15))
-#define LEDC_OVF_CNT_EN_CH4_M  (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S)
-#define LEDC_OVF_CNT_EN_CH4_V  0x00000001U
-#define LEDC_OVF_CNT_EN_CH4_S  15
-/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to reset the  ovf_cnt of channel 4.\\0: Invalid. No
- *  effect\\1: Reset the ovf_cnt
- */
-#define LEDC_OVF_CNT_RESET_CH4    (BIT(16))
-#define LEDC_OVF_CNT_RESET_CH4_M  (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S)
-#define LEDC_OVF_CNT_RESET_CH4_V  0x00000001U
-#define LEDC_OVF_CNT_RESET_CH4_S  16
-
-/** LEDC_CH4_HPOINT_REG register
- *  High point register for channel 4
- */
-#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54)
-/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0;
- *  Configures high point of signal output on channel 4. The output value changes to
- *  high when the selected timers has reached the value specified by this register.
- */
-#define LEDC_HPOINT_CH4    0x000FFFFFU
-#define LEDC_HPOINT_CH4_M  (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S)
-#define LEDC_HPOINT_CH4_V  0x000FFFFFU
-#define LEDC_HPOINT_CH4_S  0
-
-/** LEDC_CH4_DUTY_REG register
- *  Initial duty cycle register for channel 4
- */
-#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58)
-/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0;
- *  Configures the duty of signal output on channel 4.
- */
-#define LEDC_DUTY_CH4    0x01FFFFFFU
-#define LEDC_DUTY_CH4_M  (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S)
-#define LEDC_DUTY_CH4_V  0x01FFFFFFU
-#define LEDC_DUTY_CH4_S  0
-
-/** LEDC_CH4_CONF1_REG register
- *  Configuration register 1 for channel 4
- */
-#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c)
-/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0;
- *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
- *  effect\\1: Take effect
- */
-#define LEDC_DUTY_START_CH4    (BIT(31))
-#define LEDC_DUTY_START_CH4_M  (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S)
-#define LEDC_DUTY_START_CH4_V  0x00000001U
-#define LEDC_DUTY_START_CH4_S  31
-
-/** LEDC_CH4_DUTY_R_REG register
- *  Current duty cycle register for channel 4
- */
-#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60)
-/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0;
- *  Represents the current duty of output signal on channel 4.
- */
-#define LEDC_DUTY_CH4_R    0x01FFFFFFU
-#define LEDC_DUTY_CH4_R_M  (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S)
-#define LEDC_DUTY_CH4_R_V  0x01FFFFFFU
-#define LEDC_DUTY_CH4_R_S  0
-
-/** LEDC_CH5_CONF0_REG register
- *  Configuration register 0 for channel 5
- */
-#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64)
-/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0;
- *  Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select
- *  timer1\\2: Select timer2\\3: Select timer3
- */
-#define LEDC_TIMER_SEL_CH5    0x00000003U
-#define LEDC_TIMER_SEL_CH5_M  (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S)
-#define LEDC_TIMER_SEL_CH5_V  0x00000003U
-#define LEDC_TIMER_SEL_CH5_S  0
-/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable signal output on channel 5.\\0: Signal output
- *  disable\\1: Signal output enable
- */
-#define LEDC_SIG_OUT_EN_CH5    (BIT(2))
-#define LEDC_SIG_OUT_EN_CH5_M  (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S)
-#define LEDC_SIG_OUT_EN_CH5_V  0x00000001U
-#define LEDC_SIG_OUT_EN_CH5_S  2
-/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0;
- *  Configures the output value when channel 5 is inactive. Valid only when
- *  LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high
- */
-#define LEDC_IDLE_LV_CH5    (BIT(3))
-#define LEDC_IDLE_LV_CH5_M  (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S)
-#define LEDC_IDLE_LV_CH5_V  0x00000001U
-#define LEDC_IDLE_LV_CH5_S  3
-/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5,
- *  LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5,
- *  LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel
- *  5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_PARA_UP_CH5    (BIT(4))
-#define LEDC_PARA_UP_CH5_M  (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S)
-#define LEDC_PARA_UP_CH5_V  0x00000001U
-#define LEDC_PARA_UP_CH5_S  4
-/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0;
- *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt
- *  will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times.
- */
-#define LEDC_OVF_NUM_CH5    0x000003FFU
-#define LEDC_OVF_NUM_CH5_M  (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S)
-#define LEDC_OVF_NUM_CH5_V  0x000003FFU
-#define LEDC_OVF_NUM_CH5_S  5
-/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable
- */
-#define LEDC_OVF_CNT_EN_CH5    (BIT(15))
-#define LEDC_OVF_CNT_EN_CH5_M  (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S)
-#define LEDC_OVF_CNT_EN_CH5_V  0x00000001U
-#define LEDC_OVF_CNT_EN_CH5_S  15
-/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to reset the  ovf_cnt of channel 5.\\0: Invalid. No
- *  effect\\1: Reset the ovf_cnt
- */
-#define LEDC_OVF_CNT_RESET_CH5    (BIT(16))
-#define LEDC_OVF_CNT_RESET_CH5_M  (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S)
-#define LEDC_OVF_CNT_RESET_CH5_V  0x00000001U
-#define LEDC_OVF_CNT_RESET_CH5_S  16
-
-/** LEDC_CH5_HPOINT_REG register
- *  High point register for channel 5
- */
-#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68)
-/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0;
- *  Configures high point of signal output on channel 5. The output value changes to
- *  high when the selected timers has reached the value specified by this register.
- */
-#define LEDC_HPOINT_CH5    0x000FFFFFU
-#define LEDC_HPOINT_CH5_M  (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S)
-#define LEDC_HPOINT_CH5_V  0x000FFFFFU
-#define LEDC_HPOINT_CH5_S  0
-
-/** LEDC_CH5_DUTY_REG register
- *  Initial duty cycle register for channel 5
- */
-#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c)
-/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0;
- *  Configures the duty of signal output on channel 5.
- */
-#define LEDC_DUTY_CH5    0x01FFFFFFU
-#define LEDC_DUTY_CH5_M  (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S)
-#define LEDC_DUTY_CH5_V  0x01FFFFFFU
-#define LEDC_DUTY_CH5_S  0
-
-/** LEDC_CH5_CONF1_REG register
- *  Configuration register 1 for channel 5
- */
-#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70)
-/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0;
- *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
- *  effect\\1: Take effect
- */
-#define LEDC_DUTY_START_CH5    (BIT(31))
-#define LEDC_DUTY_START_CH5_M  (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S)
-#define LEDC_DUTY_START_CH5_V  0x00000001U
-#define LEDC_DUTY_START_CH5_S  31
-
-/** LEDC_CH5_DUTY_R_REG register
- *  Current duty cycle register for channel 5
- */
-#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74)
-/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0;
- *  Represents the current duty of output signal on channel 5.
- */
-#define LEDC_DUTY_CH5_R    0x01FFFFFFU
-#define LEDC_DUTY_CH5_R_M  (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S)
-#define LEDC_DUTY_CH5_R_V  0x01FFFFFFU
-#define LEDC_DUTY_CH5_R_S  0
-
-/** LEDC_TIMER0_CONF_REG register
- *  Timer 0 configuration register
- */
-#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0)
-/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
- *  Configures the range of the counter in timer 0.
- */
-#define LEDC_TIMER0_DUTY_RES    0x0000001FU
-#define LEDC_TIMER0_DUTY_RES_M  (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S)
-#define LEDC_TIMER0_DUTY_RES_V  0x0000001FU
-#define LEDC_TIMER0_DUTY_RES_S  0
-/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0;
- *  Configures the divisor for the divider in timer 0.The least significant eight bits
- *  represent the fractional part.
- */
-#define LEDC_CLK_DIV_TIMER0    0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER0_M  (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S)
-#define LEDC_CLK_DIV_TIMER0_V  0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER0_S  5
-/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to pause the counter in timer 0.\\0: Normal\\1: Pause
- */
-#define LEDC_TIMER0_PAUSE    (BIT(23))
-#define LEDC_TIMER0_PAUSE_M  (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S)
-#define LEDC_TIMER0_PAUSE_V  0x00000001U
-#define LEDC_TIMER0_PAUSE_S  23
-/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1;
- *  Configures whether or not to reset timer 0. The counter will show 0 after
- *  reset.\\0: Not reset\\1: Reset
- */
-#define LEDC_TIMER0_RST    (BIT(24))
-#define LEDC_TIMER0_RST_M  (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S)
-#define LEDC_TIMER0_RST_V  0x00000001U
-#define LEDC_TIMER0_RST_S  24
-/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to update LEDC_CLK_DIV_TIMER0 and
- *  LEDC_TIMER0_DUTY_RES.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_TIMER0_PARA_UP    (BIT(26))
-#define LEDC_TIMER0_PARA_UP_M  (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S)
-#define LEDC_TIMER0_PARA_UP_V  0x00000001U
-#define LEDC_TIMER0_PARA_UP_S  26
-
-/** LEDC_TIMER0_VALUE_REG register
- *  Timer 0 current counter value register
- */
-#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4)
-/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0;
- *  Represents the current counter value of timer 0.
- */
-#define LEDC_TIMER0_CNT    0x000FFFFFU
-#define LEDC_TIMER0_CNT_M  (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S)
-#define LEDC_TIMER0_CNT_V  0x000FFFFFU
-#define LEDC_TIMER0_CNT_S  0
-
-/** LEDC_TIMER1_CONF_REG register
- *  Timer 1 configuration register
- */
-#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8)
-/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
- *  Configures the range of the counter in timer 1.
- */
-#define LEDC_TIMER1_DUTY_RES    0x0000001FU
-#define LEDC_TIMER1_DUTY_RES_M  (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S)
-#define LEDC_TIMER1_DUTY_RES_V  0x0000001FU
-#define LEDC_TIMER1_DUTY_RES_S  0
-/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0;
- *  Configures the divisor for the divider in timer 1.The least significant eight bits
- *  represent the fractional part.
- */
-#define LEDC_CLK_DIV_TIMER1    0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER1_M  (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S)
-#define LEDC_CLK_DIV_TIMER1_V  0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER1_S  5
-/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause
- */
-#define LEDC_TIMER1_PAUSE    (BIT(23))
-#define LEDC_TIMER1_PAUSE_M  (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S)
-#define LEDC_TIMER1_PAUSE_V  0x00000001U
-#define LEDC_TIMER1_PAUSE_S  23
-/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1;
- *  Configures whether or not to reset timer 1. The counter will show 0 after
- *  reset.\\0: Not reset\\1: Reset
- */
-#define LEDC_TIMER1_RST    (BIT(24))
-#define LEDC_TIMER1_RST_M  (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S)
-#define LEDC_TIMER1_RST_V  0x00000001U
-#define LEDC_TIMER1_RST_S  24
-/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to update LEDC_CLK_DIV_TIMER1 and
- *  LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_TIMER1_PARA_UP    (BIT(26))
-#define LEDC_TIMER1_PARA_UP_M  (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S)
-#define LEDC_TIMER1_PARA_UP_V  0x00000001U
-#define LEDC_TIMER1_PARA_UP_S  26
-
-/** LEDC_TIMER1_VALUE_REG register
- *  Timer 1 current counter value register
- */
-#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac)
-/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0;
- *  Represents the current counter value of timer 1.
- */
-#define LEDC_TIMER1_CNT    0x000FFFFFU
-#define LEDC_TIMER1_CNT_M  (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S)
-#define LEDC_TIMER1_CNT_V  0x000FFFFFU
-#define LEDC_TIMER1_CNT_S  0
-
-/** LEDC_TIMER2_CONF_REG register
- *  Timer 2 configuration register
- */
-#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0)
-/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
- *  Configures the range of the counter in timer 2.
- */
-#define LEDC_TIMER2_DUTY_RES    0x0000001FU
-#define LEDC_TIMER2_DUTY_RES_M  (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S)
-#define LEDC_TIMER2_DUTY_RES_V  0x0000001FU
-#define LEDC_TIMER2_DUTY_RES_S  0
-/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0;
- *  Configures the divisor for the divider in timer 2.The least significant eight bits
- *  represent the fractional part.
- */
-#define LEDC_CLK_DIV_TIMER2    0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER2_M  (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S)
-#define LEDC_CLK_DIV_TIMER2_V  0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER2_S  5
-/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause
- */
-#define LEDC_TIMER2_PAUSE    (BIT(23))
-#define LEDC_TIMER2_PAUSE_M  (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S)
-#define LEDC_TIMER2_PAUSE_V  0x00000001U
-#define LEDC_TIMER2_PAUSE_S  23
-/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1;
- *  Configures whether or not to reset timer 2. The counter will show 0 after
- *  reset.\\0: Not reset\\1: Reset
- */
-#define LEDC_TIMER2_RST    (BIT(24))
-#define LEDC_TIMER2_RST_M  (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S)
-#define LEDC_TIMER2_RST_V  0x00000001U
-#define LEDC_TIMER2_RST_S  24
-/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to update LEDC_CLK_DIV_TIMER2 and
- *  LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_TIMER2_PARA_UP    (BIT(26))
-#define LEDC_TIMER2_PARA_UP_M  (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S)
-#define LEDC_TIMER2_PARA_UP_V  0x00000001U
-#define LEDC_TIMER2_PARA_UP_S  26
-
-/** LEDC_TIMER2_VALUE_REG register
- *  Timer 2 current counter value register
- */
-#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4)
-/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0;
- *  Represents the current counter value of timer 2.
- */
-#define LEDC_TIMER2_CNT    0x000FFFFFU
-#define LEDC_TIMER2_CNT_M  (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S)
-#define LEDC_TIMER2_CNT_V  0x000FFFFFU
-#define LEDC_TIMER2_CNT_S  0
-
-/** LEDC_TIMER3_CONF_REG register
- *  Timer 3 configuration register
- */
-#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8)
-/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0;
- *  Configures the range of the counter in timer 3.
- */
-#define LEDC_TIMER3_DUTY_RES    0x0000001FU
-#define LEDC_TIMER3_DUTY_RES_M  (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S)
-#define LEDC_TIMER3_DUTY_RES_V  0x0000001FU
-#define LEDC_TIMER3_DUTY_RES_S  0
-/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0;
- *  Configures the divisor for the divider in timer 3.The least significant eight bits
- *  represent the fractional part.
- */
-#define LEDC_CLK_DIV_TIMER3    0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER3_M  (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S)
-#define LEDC_CLK_DIV_TIMER3_V  0x0003FFFFU
-#define LEDC_CLK_DIV_TIMER3_S  5
-/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause
- */
-#define LEDC_TIMER3_PAUSE    (BIT(23))
-#define LEDC_TIMER3_PAUSE_M  (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S)
-#define LEDC_TIMER3_PAUSE_V  0x00000001U
-#define LEDC_TIMER3_PAUSE_S  23
-/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1;
- *  Configures whether or not to reset timer 3. The counter will show 0 after
- *  reset.\\0: Not reset\\1: Reset
- */
-#define LEDC_TIMER3_RST    (BIT(24))
-#define LEDC_TIMER3_RST_M  (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S)
-#define LEDC_TIMER3_RST_V  0x00000001U
-#define LEDC_TIMER3_RST_S  24
-/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to update LEDC_CLK_DIV_TIMER3 and
- *  LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update
- */
-#define LEDC_TIMER3_PARA_UP    (BIT(26))
-#define LEDC_TIMER3_PARA_UP_M  (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S)
-#define LEDC_TIMER3_PARA_UP_V  0x00000001U
-#define LEDC_TIMER3_PARA_UP_S  26
-
-/** LEDC_TIMER3_VALUE_REG register
- *  Timer 3 current counter value register
- */
-#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc)
-/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0;
- *  Represents the current counter value of timer 3.
- */
-#define LEDC_TIMER3_CNT    0x000FFFFFU
-#define LEDC_TIMER3_CNT_M  (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S)
-#define LEDC_TIMER3_CNT_V  0x000FFFFFU
-#define LEDC_TIMER3_CNT_S  0
-
-/** LEDC_INT_RAW_REG register
- *  Interrupt raw status register
- */
-#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0)
-/** LEDC_TIMER0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the
- *  timer0 has reached its maximum counter value.
- */
-#define LEDC_TIMER0_OVF_INT_RAW    (BIT(0))
-#define LEDC_TIMER0_OVF_INT_RAW_M  (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S)
-#define LEDC_TIMER0_OVF_INT_RAW_V  0x00000001U
-#define LEDC_TIMER0_OVF_INT_RAW_S  0
-/** LEDC_TIMER1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the
- *  timer1 has reached its maximum counter value.
- */
-#define LEDC_TIMER1_OVF_INT_RAW    (BIT(1))
-#define LEDC_TIMER1_OVF_INT_RAW_M  (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S)
-#define LEDC_TIMER1_OVF_INT_RAW_V  0x00000001U
-#define LEDC_TIMER1_OVF_INT_RAW_S  1
-/** LEDC_TIMER2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the
- *  timer2 has reached its maximum counter value.
- */
-#define LEDC_TIMER2_OVF_INT_RAW    (BIT(2))
-#define LEDC_TIMER2_OVF_INT_RAW_M  (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S)
-#define LEDC_TIMER2_OVF_INT_RAW_V  0x00000001U
-#define LEDC_TIMER2_OVF_INT_RAW_S  2
-/** LEDC_TIMER3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the
- *  timer3 has reached its maximum counter value.
- */
-#define LEDC_TIMER3_OVF_INT_RAW    (BIT(3))
-#define LEDC_TIMER3_OVF_INT_RAW_M  (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S)
-#define LEDC_TIMER3_OVF_INT_RAW_V  0x00000001U
-#define LEDC_TIMER3_OVF_INT_RAW_S  3
-/** LEDC_DUTY_CHNG_END_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered
- *  when the fading of duty has finished.
- */
-#define LEDC_DUTY_CHNG_END_CH0_INT_RAW    (BIT(4))
-#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S)
-#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S  4
-/** LEDC_DUTY_CHNG_END_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered
- *  when the fading of duty has finished.
- */
-#define LEDC_DUTY_CHNG_END_CH1_INT_RAW    (BIT(5))
-#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S)
-#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S  5
-/** LEDC_DUTY_CHNG_END_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered
- *  when the fading of duty has finished.
- */
-#define LEDC_DUTY_CHNG_END_CH2_INT_RAW    (BIT(6))
-#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S)
-#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S  6
-/** LEDC_DUTY_CHNG_END_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered
- *  when the fading of duty has finished.
- */
-#define LEDC_DUTY_CHNG_END_CH3_INT_RAW    (BIT(7))
-#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S)
-#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S  7
-/** LEDC_DUTY_CHNG_END_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered
- *  when the fading of duty has finished.
- */
-#define LEDC_DUTY_CHNG_END_CH4_INT_RAW    (BIT(8))
-#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S)
-#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S  8
-/** LEDC_DUTY_CHNG_END_CH5_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered
- *  when the fading of duty has finished.
- */
-#define LEDC_DUTY_CHNG_END_CH5_INT_RAW    (BIT(9))
-#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M  (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S)
-#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S  9
-/** LEDC_OVF_CNT_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when
- *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.
- */
-#define LEDC_OVF_CNT_CH0_INT_RAW    (BIT(12))
-#define LEDC_OVF_CNT_CH0_INT_RAW_M  (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S)
-#define LEDC_OVF_CNT_CH0_INT_RAW_V  0x00000001U
-#define LEDC_OVF_CNT_CH0_INT_RAW_S  12
-/** LEDC_OVF_CNT_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when
- *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.
- */
-#define LEDC_OVF_CNT_CH1_INT_RAW    (BIT(13))
-#define LEDC_OVF_CNT_CH1_INT_RAW_M  (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S)
-#define LEDC_OVF_CNT_CH1_INT_RAW_V  0x00000001U
-#define LEDC_OVF_CNT_CH1_INT_RAW_S  13
-/** LEDC_OVF_CNT_CH2_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when
- *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.
- */
-#define LEDC_OVF_CNT_CH2_INT_RAW    (BIT(14))
-#define LEDC_OVF_CNT_CH2_INT_RAW_M  (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S)
-#define LEDC_OVF_CNT_CH2_INT_RAW_V  0x00000001U
-#define LEDC_OVF_CNT_CH2_INT_RAW_S  14
-/** LEDC_OVF_CNT_CH3_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when
- *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.
- */
-#define LEDC_OVF_CNT_CH3_INT_RAW    (BIT(15))
-#define LEDC_OVF_CNT_CH3_INT_RAW_M  (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S)
-#define LEDC_OVF_CNT_CH3_INT_RAW_V  0x00000001U
-#define LEDC_OVF_CNT_CH3_INT_RAW_S  15
-/** LEDC_OVF_CNT_CH4_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when
- *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.
- */
-#define LEDC_OVF_CNT_CH4_INT_RAW    (BIT(16))
-#define LEDC_OVF_CNT_CH4_INT_RAW_M  (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S)
-#define LEDC_OVF_CNT_CH4_INT_RAW_V  0x00000001U
-#define LEDC_OVF_CNT_CH4_INT_RAW_S  16
-/** LEDC_OVF_CNT_CH5_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when
- *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.
- */
-#define LEDC_OVF_CNT_CH5_INT_RAW    (BIT(17))
-#define LEDC_OVF_CNT_CH5_INT_RAW_M  (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S)
-#define LEDC_OVF_CNT_CH5_INT_RAW_V  0x00000001U
-#define LEDC_OVF_CNT_CH5_INT_RAW_S  17
-
-/** LEDC_INT_ST_REG register
- *  Interrupt masked status register
- */
-#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4)
-/** LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only
- *  when LEDC_TIMER0_OVF_INT_ENA is set to 1.
- */
-#define LEDC_TIMER0_OVF_INT_ST    (BIT(0))
-#define LEDC_TIMER0_OVF_INT_ST_M  (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S)
-#define LEDC_TIMER0_OVF_INT_ST_V  0x00000001U
-#define LEDC_TIMER0_OVF_INT_ST_S  0
-/** LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only
- *  when LEDC_TIMER1_OVF_INT_ENA is set to 1.
- */
-#define LEDC_TIMER1_OVF_INT_ST    (BIT(1))
-#define LEDC_TIMER1_OVF_INT_ST_M  (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S)
-#define LEDC_TIMER1_OVF_INT_ST_V  0x00000001U
-#define LEDC_TIMER1_OVF_INT_ST_S  1
-/** LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only
- *  when LEDC_TIMER2_OVF_INT_ENA is set to 1.
- */
-#define LEDC_TIMER2_OVF_INT_ST    (BIT(2))
-#define LEDC_TIMER2_OVF_INT_ST_M  (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S)
-#define LEDC_TIMER2_OVF_INT_ST_V  0x00000001U
-#define LEDC_TIMER2_OVF_INT_ST_S  2
-/** LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only
- *  when LEDC_TIMER3_OVF_INT_ENA is set to 1.
- */
-#define LEDC_TIMER3_OVF_INT_ST    (BIT(3))
-#define LEDC_TIMER3_OVF_INT_ST_M  (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S)
-#define LEDC_TIMER3_OVF_INT_ST_V  0x00000001U
-#define LEDC_TIMER3_OVF_INT_ST_S  3
-/** LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid
- *  only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.
- */
-#define LEDC_DUTY_CHNG_END_CH0_INT_ST    (BIT(4))
-#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M  (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S)
-#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S  4
-/** LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid
- *  only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.
- */
-#define LEDC_DUTY_CHNG_END_CH1_INT_ST    (BIT(5))
-#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M  (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S)
-#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S  5
-/** LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid
- *  only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.
- */
-#define LEDC_DUTY_CHNG_END_CH2_INT_ST    (BIT(6))
-#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M  (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S)
-#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S  6
-/** LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid
- *  only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.
- */
-#define LEDC_DUTY_CHNG_END_CH3_INT_ST    (BIT(7))
-#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M  (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S)
-#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S  7
-/** LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid
- *  only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.
- */
-#define LEDC_DUTY_CHNG_END_CH4_INT_ST    (BIT(8))
-#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M  (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S)
-#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S  8
-/** LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid
- *  only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.
- */
-#define LEDC_DUTY_CHNG_END_CH5_INT_ST    (BIT(9))
-#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M  (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S)
-#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S  9
-/** LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only
- *  when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
- */
-#define LEDC_OVF_CNT_CH0_INT_ST    (BIT(12))
-#define LEDC_OVF_CNT_CH0_INT_ST_M  (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S)
-#define LEDC_OVF_CNT_CH0_INT_ST_V  0x00000001U
-#define LEDC_OVF_CNT_CH0_INT_ST_S  12
-/** LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only
- *  when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
- */
-#define LEDC_OVF_CNT_CH1_INT_ST    (BIT(13))
-#define LEDC_OVF_CNT_CH1_INT_ST_M  (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S)
-#define LEDC_OVF_CNT_CH1_INT_ST_V  0x00000001U
-#define LEDC_OVF_CNT_CH1_INT_ST_S  13
-/** LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only
- *  when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
- */
-#define LEDC_OVF_CNT_CH2_INT_ST    (BIT(14))
-#define LEDC_OVF_CNT_CH2_INT_ST_M  (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S)
-#define LEDC_OVF_CNT_CH2_INT_ST_V  0x00000001U
-#define LEDC_OVF_CNT_CH2_INT_ST_S  14
-/** LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only
- *  when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
- */
-#define LEDC_OVF_CNT_CH3_INT_ST    (BIT(15))
-#define LEDC_OVF_CNT_CH3_INT_ST_M  (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S)
-#define LEDC_OVF_CNT_CH3_INT_ST_V  0x00000001U
-#define LEDC_OVF_CNT_CH3_INT_ST_S  15
-/** LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only
- *  when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
- */
-#define LEDC_OVF_CNT_CH4_INT_ST    (BIT(16))
-#define LEDC_OVF_CNT_CH4_INT_ST_M  (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S)
-#define LEDC_OVF_CNT_CH4_INT_ST_V  0x00000001U
-#define LEDC_OVF_CNT_CH4_INT_ST_S  16
-/** LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0;
- *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only
- *  when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
- */
-#define LEDC_OVF_CNT_CH5_INT_ST    (BIT(17))
-#define LEDC_OVF_CNT_CH5_INT_ST_M  (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S)
-#define LEDC_OVF_CNT_CH5_INT_ST_V  0x00000001U
-#define LEDC_OVF_CNT_CH5_INT_ST_S  17
-
-/** LEDC_INT_ENA_REG register
- *  Interrupt enable register
- */
-#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8)
-/** LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT.
- */
-#define LEDC_TIMER0_OVF_INT_ENA    (BIT(0))
-#define LEDC_TIMER0_OVF_INT_ENA_M  (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S)
-#define LEDC_TIMER0_OVF_INT_ENA_V  0x00000001U
-#define LEDC_TIMER0_OVF_INT_ENA_S  0
-/** LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT.
- */
-#define LEDC_TIMER1_OVF_INT_ENA    (BIT(1))
-#define LEDC_TIMER1_OVF_INT_ENA_M  (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S)
-#define LEDC_TIMER1_OVF_INT_ENA_V  0x00000001U
-#define LEDC_TIMER1_OVF_INT_ENA_S  1
-/** LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT.
- */
-#define LEDC_TIMER2_OVF_INT_ENA    (BIT(2))
-#define LEDC_TIMER2_OVF_INT_ENA_M  (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S)
-#define LEDC_TIMER2_OVF_INT_ENA_V  0x00000001U
-#define LEDC_TIMER2_OVF_INT_ENA_S  2
-/** LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT.
- */
-#define LEDC_TIMER3_OVF_INT_ENA    (BIT(3))
-#define LEDC_TIMER3_OVF_INT_ENA_M  (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S)
-#define LEDC_TIMER3_OVF_INT_ENA_V  0x00000001U
-#define LEDC_TIMER3_OVF_INT_ENA_S  3
-/** LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH0_INT_ENA    (BIT(4))
-#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
-#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S  4
-/** LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH1_INT_ENA    (BIT(5))
-#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S)
-#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S  5
-/** LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH2_INT_ENA    (BIT(6))
-#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S)
-#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S  6
-/** LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH3_INT_ENA    (BIT(7))
-#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S)
-#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S  7
-/** LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH4_INT_ENA    (BIT(8))
-#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S)
-#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S  8
-/** LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH5_INT_ENA    (BIT(9))
-#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M  (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S)
-#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S  9
-/** LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT.
- */
-#define LEDC_OVF_CNT_CH0_INT_ENA    (BIT(12))
-#define LEDC_OVF_CNT_CH0_INT_ENA_M  (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S)
-#define LEDC_OVF_CNT_CH0_INT_ENA_V  0x00000001U
-#define LEDC_OVF_CNT_CH0_INT_ENA_S  12
-/** LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT.
- */
-#define LEDC_OVF_CNT_CH1_INT_ENA    (BIT(13))
-#define LEDC_OVF_CNT_CH1_INT_ENA_M  (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S)
-#define LEDC_OVF_CNT_CH1_INT_ENA_V  0x00000001U
-#define LEDC_OVF_CNT_CH1_INT_ENA_S  13
-/** LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT.
- */
-#define LEDC_OVF_CNT_CH2_INT_ENA    (BIT(14))
-#define LEDC_OVF_CNT_CH2_INT_ENA_M  (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S)
-#define LEDC_OVF_CNT_CH2_INT_ENA_V  0x00000001U
-#define LEDC_OVF_CNT_CH2_INT_ENA_S  14
-/** LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT.
- */
-#define LEDC_OVF_CNT_CH3_INT_ENA    (BIT(15))
-#define LEDC_OVF_CNT_CH3_INT_ENA_M  (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S)
-#define LEDC_OVF_CNT_CH3_INT_ENA_V  0x00000001U
-#define LEDC_OVF_CNT_CH3_INT_ENA_S  15
-/** LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT.
- */
-#define LEDC_OVF_CNT_CH4_INT_ENA    (BIT(16))
-#define LEDC_OVF_CNT_CH4_INT_ENA_M  (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S)
-#define LEDC_OVF_CNT_CH4_INT_ENA_V  0x00000001U
-#define LEDC_OVF_CNT_CH4_INT_ENA_S  16
-/** LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT.
- */
-#define LEDC_OVF_CNT_CH5_INT_ENA    (BIT(17))
-#define LEDC_OVF_CNT_CH5_INT_ENA_M  (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S)
-#define LEDC_OVF_CNT_CH5_INT_ENA_V  0x00000001U
-#define LEDC_OVF_CNT_CH5_INT_ENA_S  17
-
-/** LEDC_INT_CLR_REG register
- *  Interrupt clear register
- */
-#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc)
-/** LEDC_TIMER0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT.
- */
-#define LEDC_TIMER0_OVF_INT_CLR    (BIT(0))
-#define LEDC_TIMER0_OVF_INT_CLR_M  (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S)
-#define LEDC_TIMER0_OVF_INT_CLR_V  0x00000001U
-#define LEDC_TIMER0_OVF_INT_CLR_S  0
-/** LEDC_TIMER1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT.
- */
-#define LEDC_TIMER1_OVF_INT_CLR    (BIT(1))
-#define LEDC_TIMER1_OVF_INT_CLR_M  (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S)
-#define LEDC_TIMER1_OVF_INT_CLR_V  0x00000001U
-#define LEDC_TIMER1_OVF_INT_CLR_S  1
-/** LEDC_TIMER2_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT.
- */
-#define LEDC_TIMER2_OVF_INT_CLR    (BIT(2))
-#define LEDC_TIMER2_OVF_INT_CLR_M  (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S)
-#define LEDC_TIMER2_OVF_INT_CLR_V  0x00000001U
-#define LEDC_TIMER2_OVF_INT_CLR_S  2
-/** LEDC_TIMER3_OVF_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT.
- */
-#define LEDC_TIMER3_OVF_INT_CLR    (BIT(3))
-#define LEDC_TIMER3_OVF_INT_CLR_M  (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S)
-#define LEDC_TIMER3_OVF_INT_CLR_V  0x00000001U
-#define LEDC_TIMER3_OVF_INT_CLR_S  3
-/** LEDC_DUTY_CHNG_END_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH0_INT_CLR    (BIT(4))
-#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S)
-#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S  4
-/** LEDC_DUTY_CHNG_END_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH1_INT_CLR    (BIT(5))
-#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S)
-#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S  5
-/** LEDC_DUTY_CHNG_END_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH2_INT_CLR    (BIT(6))
-#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S)
-#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S  6
-/** LEDC_DUTY_CHNG_END_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH3_INT_CLR    (BIT(7))
-#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S)
-#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S  7
-/** LEDC_DUTY_CHNG_END_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH4_INT_CLR    (BIT(8))
-#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S)
-#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S  8
-/** LEDC_DUTY_CHNG_END_CH5_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT.
- */
-#define LEDC_DUTY_CHNG_END_CH5_INT_CLR    (BIT(9))
-#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M  (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S)
-#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V  0x00000001U
-#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S  9
-/** LEDC_OVF_CNT_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT.
- */
-#define LEDC_OVF_CNT_CH0_INT_CLR    (BIT(12))
-#define LEDC_OVF_CNT_CH0_INT_CLR_M  (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S)
-#define LEDC_OVF_CNT_CH0_INT_CLR_V  0x00000001U
-#define LEDC_OVF_CNT_CH0_INT_CLR_S  12
-/** LEDC_OVF_CNT_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT.
- */
-#define LEDC_OVF_CNT_CH1_INT_CLR    (BIT(13))
-#define LEDC_OVF_CNT_CH1_INT_CLR_M  (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S)
-#define LEDC_OVF_CNT_CH1_INT_CLR_V  0x00000001U
-#define LEDC_OVF_CNT_CH1_INT_CLR_S  13
-/** LEDC_OVF_CNT_CH2_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT.
- */
-#define LEDC_OVF_CNT_CH2_INT_CLR    (BIT(14))
-#define LEDC_OVF_CNT_CH2_INT_CLR_M  (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S)
-#define LEDC_OVF_CNT_CH2_INT_CLR_V  0x00000001U
-#define LEDC_OVF_CNT_CH2_INT_CLR_S  14
-/** LEDC_OVF_CNT_CH3_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT.
- */
-#define LEDC_OVF_CNT_CH3_INT_CLR    (BIT(15))
-#define LEDC_OVF_CNT_CH3_INT_CLR_M  (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S)
-#define LEDC_OVF_CNT_CH3_INT_CLR_V  0x00000001U
-#define LEDC_OVF_CNT_CH3_INT_CLR_S  15
-/** LEDC_OVF_CNT_CH4_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT.
- */
-#define LEDC_OVF_CNT_CH4_INT_CLR    (BIT(16))
-#define LEDC_OVF_CNT_CH4_INT_CLR_M  (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S)
-#define LEDC_OVF_CNT_CH4_INT_CLR_V  0x00000001U
-#define LEDC_OVF_CNT_CH4_INT_CLR_S  16
-/** LEDC_OVF_CNT_CH5_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT.
- */
-#define LEDC_OVF_CNT_CH5_INT_CLR    (BIT(17))
-#define LEDC_OVF_CNT_CH5_INT_CLR_M  (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S)
-#define LEDC_OVF_CNT_CH5_INT_CLR_V  0x00000001U
-#define LEDC_OVF_CNT_CH5_INT_CLR_S  17
-
-/** LEDC_CH0_GAMMA_CONF_REG register
- *  Ledc ch0 gamma config register.
- */
-#define LEDC_CH0_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x100)
-/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
- *  Configures the number of duty cycle fading rages for LEDC ch0.
- */
-#define LEDC_CH0_GAMMA_ENTRY_NUM    0x0000001FU
-#define LEDC_CH0_GAMMA_ENTRY_NUM_M  (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S)
-#define LEDC_CH0_GAMMA_ENTRY_NUM_V  0x0000001FU
-#define LEDC_CH0_GAMMA_ENTRY_NUM_S  0
-/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to pause duty cycle fading of LEDC ch0.\\0: Invalid. No
- *  effect\\1: Pause
- */
-#define LEDC_CH0_GAMMA_PAUSE    (BIT(5))
-#define LEDC_CH0_GAMMA_PAUSE_M  (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S)
-#define LEDC_CH0_GAMMA_PAUSE_V  0x00000001U
-#define LEDC_CH0_GAMMA_PAUSE_S  5
-/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
- *  Configures whether or nor to resume duty cycle fading of LEDC ch0.\\0: Invalid. No
- *  effect\\1: Resume
- */
-#define LEDC_CH0_GAMMA_RESUME    (BIT(6))
-#define LEDC_CH0_GAMMA_RESUME_M  (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S)
-#define LEDC_CH0_GAMMA_RESUME_V  0x00000001U
-#define LEDC_CH0_GAMMA_RESUME_S  6
-
-/** LEDC_CH1_GAMMA_CONF_REG register
- *  Ledc ch1 gamma config register.
- */
-#define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104)
-/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
- *  Configures the number of duty cycle fading rages for LEDC ch1.
- */
-#define LEDC_CH1_GAMMA_ENTRY_NUM    0x0000001FU
-#define LEDC_CH1_GAMMA_ENTRY_NUM_M  (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S)
-#define LEDC_CH1_GAMMA_ENTRY_NUM_V  0x0000001FU
-#define LEDC_CH1_GAMMA_ENTRY_NUM_S  0
-/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No
- *  effect\\1: Pause
- */
-#define LEDC_CH1_GAMMA_PAUSE    (BIT(5))
-#define LEDC_CH1_GAMMA_PAUSE_M  (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S)
-#define LEDC_CH1_GAMMA_PAUSE_V  0x00000001U
-#define LEDC_CH1_GAMMA_PAUSE_S  5
-/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
- *  Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No
- *  effect\\1: Resume
- */
-#define LEDC_CH1_GAMMA_RESUME    (BIT(6))
-#define LEDC_CH1_GAMMA_RESUME_M  (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S)
-#define LEDC_CH1_GAMMA_RESUME_V  0x00000001U
-#define LEDC_CH1_GAMMA_RESUME_S  6
-
-/** LEDC_CH2_GAMMA_CONF_REG register
- *  Ledc ch2 gamma config register.
- */
-#define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108)
-/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
- *  Configures the number of duty cycle fading rages for LEDC ch2.
- */
-#define LEDC_CH2_GAMMA_ENTRY_NUM    0x0000001FU
-#define LEDC_CH2_GAMMA_ENTRY_NUM_M  (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S)
-#define LEDC_CH2_GAMMA_ENTRY_NUM_V  0x0000001FU
-#define LEDC_CH2_GAMMA_ENTRY_NUM_S  0
-/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No
- *  effect\\1: Pause
- */
-#define LEDC_CH2_GAMMA_PAUSE    (BIT(5))
-#define LEDC_CH2_GAMMA_PAUSE_M  (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S)
-#define LEDC_CH2_GAMMA_PAUSE_V  0x00000001U
-#define LEDC_CH2_GAMMA_PAUSE_S  5
-/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
- *  Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No
- *  effect\\1: Resume
- */
-#define LEDC_CH2_GAMMA_RESUME    (BIT(6))
-#define LEDC_CH2_GAMMA_RESUME_M  (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S)
-#define LEDC_CH2_GAMMA_RESUME_V  0x00000001U
-#define LEDC_CH2_GAMMA_RESUME_S  6
-
-/** LEDC_CH3_GAMMA_CONF_REG register
- *  Ledc ch3 gamma config register.
- */
-#define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c)
-/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
- *  Configures the number of duty cycle fading rages for LEDC ch3.
- */
-#define LEDC_CH3_GAMMA_ENTRY_NUM    0x0000001FU
-#define LEDC_CH3_GAMMA_ENTRY_NUM_M  (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S)
-#define LEDC_CH3_GAMMA_ENTRY_NUM_V  0x0000001FU
-#define LEDC_CH3_GAMMA_ENTRY_NUM_S  0
-/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No
- *  effect\\1: Pause
- */
-#define LEDC_CH3_GAMMA_PAUSE    (BIT(5))
-#define LEDC_CH3_GAMMA_PAUSE_M  (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S)
-#define LEDC_CH3_GAMMA_PAUSE_V  0x00000001U
-#define LEDC_CH3_GAMMA_PAUSE_S  5
-/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
- *  Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No
- *  effect\\1: Resume
- */
-#define LEDC_CH3_GAMMA_RESUME    (BIT(6))
-#define LEDC_CH3_GAMMA_RESUME_M  (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S)
-#define LEDC_CH3_GAMMA_RESUME_V  0x00000001U
-#define LEDC_CH3_GAMMA_RESUME_S  6
-
-/** LEDC_CH4_GAMMA_CONF_REG register
- *  Ledc ch4 gamma config register.
- */
-#define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110)
-/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
- *  Configures the number of duty cycle fading rages for LEDC ch4.
- */
-#define LEDC_CH4_GAMMA_ENTRY_NUM    0x0000001FU
-#define LEDC_CH4_GAMMA_ENTRY_NUM_M  (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S)
-#define LEDC_CH4_GAMMA_ENTRY_NUM_V  0x0000001FU
-#define LEDC_CH4_GAMMA_ENTRY_NUM_S  0
-/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No
- *  effect\\1: Pause
- */
-#define LEDC_CH4_GAMMA_PAUSE    (BIT(5))
-#define LEDC_CH4_GAMMA_PAUSE_M  (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S)
-#define LEDC_CH4_GAMMA_PAUSE_V  0x00000001U
-#define LEDC_CH4_GAMMA_PAUSE_S  5
-/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
- *  Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No
- *  effect\\1: Resume
- */
-#define LEDC_CH4_GAMMA_RESUME    (BIT(6))
-#define LEDC_CH4_GAMMA_RESUME_M  (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S)
-#define LEDC_CH4_GAMMA_RESUME_V  0x00000001U
-#define LEDC_CH4_GAMMA_RESUME_S  6
-
-/** LEDC_CH5_GAMMA_CONF_REG register
- *  Ledc ch5 gamma config register.
- */
-#define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114)
-/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0;
- *  Configures the number of duty cycle fading rages for LEDC ch5.
- */
-#define LEDC_CH5_GAMMA_ENTRY_NUM    0x0000001FU
-#define LEDC_CH5_GAMMA_ENTRY_NUM_M  (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S)
-#define LEDC_CH5_GAMMA_ENTRY_NUM_V  0x0000001FU
-#define LEDC_CH5_GAMMA_ENTRY_NUM_S  0
-/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No
- *  effect\\1: Pause
- */
-#define LEDC_CH5_GAMMA_PAUSE    (BIT(5))
-#define LEDC_CH5_GAMMA_PAUSE_M  (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S)
-#define LEDC_CH5_GAMMA_PAUSE_V  0x00000001U
-#define LEDC_CH5_GAMMA_PAUSE_S  5
-/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0;
- *  Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No
- *  effect\\1: Resume
- */
-#define LEDC_CH5_GAMMA_RESUME    (BIT(6))
-#define LEDC_CH5_GAMMA_RESUME_M  (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S)
-#define LEDC_CH5_GAMMA_RESUME_V  0x00000001U
-#define LEDC_CH5_GAMMA_RESUME_S  6
-
-/** LEDC_EVT_TASK_EN0_REG register
- *  Ledc event task enable bit register0.
- */
-#define LEDC_EVT_TASK_EN0_REG (DR_REG_LEDC_BASE + 0x120)
-/** LEDC_EVT_DUTY_CHNG_END_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_EVT_DUTY_CHNG_END_CH0_EN    (BIT(0))
-#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH0_EN_V << LEDC_EVT_DUTY_CHNG_END_CH0_EN_S)
-#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_V  0x00000001U
-#define LEDC_EVT_DUTY_CHNG_END_CH0_EN_S  0
-/** LEDC_EVT_DUTY_CHNG_END_CH1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_EVT_DUTY_CHNG_END_CH1_EN    (BIT(1))
-#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH1_EN_V << LEDC_EVT_DUTY_CHNG_END_CH1_EN_S)
-#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_V  0x00000001U
-#define LEDC_EVT_DUTY_CHNG_END_CH1_EN_S  1
-/** LEDC_EVT_DUTY_CHNG_END_CH2_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_EVT_DUTY_CHNG_END_CH2_EN    (BIT(2))
-#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH2_EN_V << LEDC_EVT_DUTY_CHNG_END_CH2_EN_S)
-#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_V  0x00000001U
-#define LEDC_EVT_DUTY_CHNG_END_CH2_EN_S  2
-/** LEDC_EVT_DUTY_CHNG_END_CH3_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_EVT_DUTY_CHNG_END_CH3_EN    (BIT(3))
-#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH3_EN_V << LEDC_EVT_DUTY_CHNG_END_CH3_EN_S)
-#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_V  0x00000001U
-#define LEDC_EVT_DUTY_CHNG_END_CH3_EN_S  3
-/** LEDC_EVT_DUTY_CHNG_END_CH4_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_EVT_DUTY_CHNG_END_CH4_EN    (BIT(4))
-#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH4_EN_V << LEDC_EVT_DUTY_CHNG_END_CH4_EN_S)
-#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_V  0x00000001U
-#define LEDC_EVT_DUTY_CHNG_END_CH4_EN_S  4
-/** LEDC_EVT_DUTY_CHNG_END_CH5_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_EVT_DUTY_CHNG_END_CH5_EN    (BIT(5))
-#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_M  (LEDC_EVT_DUTY_CHNG_END_CH5_EN_V << LEDC_EVT_DUTY_CHNG_END_CH5_EN_S)
-#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_V  0x00000001U
-#define LEDC_EVT_DUTY_CHNG_END_CH5_EN_S  5
-/** LEDC_EVT_OVF_CNT_PLS_CH0_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_OVF_CNT_PLS_CH0_EN    (BIT(8))
-#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH0_EN_V << LEDC_EVT_OVF_CNT_PLS_CH0_EN_S)
-#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_V  0x00000001U
-#define LEDC_EVT_OVF_CNT_PLS_CH0_EN_S  8
-/** LEDC_EVT_OVF_CNT_PLS_CH1_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_OVF_CNT_PLS_CH1_EN    (BIT(9))
-#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH1_EN_V << LEDC_EVT_OVF_CNT_PLS_CH1_EN_S)
-#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_V  0x00000001U
-#define LEDC_EVT_OVF_CNT_PLS_CH1_EN_S  9
-/** LEDC_EVT_OVF_CNT_PLS_CH2_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_OVF_CNT_PLS_CH2_EN    (BIT(10))
-#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH2_EN_V << LEDC_EVT_OVF_CNT_PLS_CH2_EN_S)
-#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_V  0x00000001U
-#define LEDC_EVT_OVF_CNT_PLS_CH2_EN_S  10
-/** LEDC_EVT_OVF_CNT_PLS_CH3_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_OVF_CNT_PLS_CH3_EN    (BIT(11))
-#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH3_EN_V << LEDC_EVT_OVF_CNT_PLS_CH3_EN_S)
-#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_V  0x00000001U
-#define LEDC_EVT_OVF_CNT_PLS_CH3_EN_S  11
-/** LEDC_EVT_OVF_CNT_PLS_CH4_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_OVF_CNT_PLS_CH4_EN    (BIT(12))
-#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH4_EN_V << LEDC_EVT_OVF_CNT_PLS_CH4_EN_S)
-#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_V  0x00000001U
-#define LEDC_EVT_OVF_CNT_PLS_CH4_EN_S  12
-/** LEDC_EVT_OVF_CNT_PLS_CH5_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_OVF_CNT_PLS_CH5_EN    (BIT(13))
-#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_M  (LEDC_EVT_OVF_CNT_PLS_CH5_EN_V << LEDC_EVT_OVF_CNT_PLS_CH5_EN_S)
-#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_V  0x00000001U
-#define LEDC_EVT_OVF_CNT_PLS_CH5_EN_S  13
-/** LEDC_EVT_TIME_OVF_TIMER0_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME_OVF_TIMER0_EN    (BIT(16))
-#define LEDC_EVT_TIME_OVF_TIMER0_EN_M  (LEDC_EVT_TIME_OVF_TIMER0_EN_V << LEDC_EVT_TIME_OVF_TIMER0_EN_S)
-#define LEDC_EVT_TIME_OVF_TIMER0_EN_V  0x00000001U
-#define LEDC_EVT_TIME_OVF_TIMER0_EN_S  16
-/** LEDC_EVT_TIME_OVF_TIMER1_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME_OVF_TIMER1_EN    (BIT(17))
-#define LEDC_EVT_TIME_OVF_TIMER1_EN_M  (LEDC_EVT_TIME_OVF_TIMER1_EN_V << LEDC_EVT_TIME_OVF_TIMER1_EN_S)
-#define LEDC_EVT_TIME_OVF_TIMER1_EN_V  0x00000001U
-#define LEDC_EVT_TIME_OVF_TIMER1_EN_S  17
-/** LEDC_EVT_TIME_OVF_TIMER2_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME_OVF_TIMER2_EN    (BIT(18))
-#define LEDC_EVT_TIME_OVF_TIMER2_EN_M  (LEDC_EVT_TIME_OVF_TIMER2_EN_V << LEDC_EVT_TIME_OVF_TIMER2_EN_S)
-#define LEDC_EVT_TIME_OVF_TIMER2_EN_V  0x00000001U
-#define LEDC_EVT_TIME_OVF_TIMER2_EN_S  18
-/** LEDC_EVT_TIME_OVF_TIMER3_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME_OVF_TIMER3_EN    (BIT(19))
-#define LEDC_EVT_TIME_OVF_TIMER3_EN_M  (LEDC_EVT_TIME_OVF_TIMER3_EN_V << LEDC_EVT_TIME_OVF_TIMER3_EN_S)
-#define LEDC_EVT_TIME_OVF_TIMER3_EN_V  0x00000001U
-#define LEDC_EVT_TIME_OVF_TIMER3_EN_S  19
-/** LEDC_EVT_TIME0_CMP_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME0_CMP_EN    (BIT(20))
-#define LEDC_EVT_TIME0_CMP_EN_M  (LEDC_EVT_TIME0_CMP_EN_V << LEDC_EVT_TIME0_CMP_EN_S)
-#define LEDC_EVT_TIME0_CMP_EN_V  0x00000001U
-#define LEDC_EVT_TIME0_CMP_EN_S  20
-/** LEDC_EVT_TIME1_CMP_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME1_CMP_EN    (BIT(21))
-#define LEDC_EVT_TIME1_CMP_EN_M  (LEDC_EVT_TIME1_CMP_EN_V << LEDC_EVT_TIME1_CMP_EN_S)
-#define LEDC_EVT_TIME1_CMP_EN_V  0x00000001U
-#define LEDC_EVT_TIME1_CMP_EN_S  21
-/** LEDC_EVT_TIME2_CMP_EN : R/W; bitpos: [22]; default: 0;
- *  Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME2_CMP_EN    (BIT(22))
-#define LEDC_EVT_TIME2_CMP_EN_M  (LEDC_EVT_TIME2_CMP_EN_V << LEDC_EVT_TIME2_CMP_EN_S)
-#define LEDC_EVT_TIME2_CMP_EN_V  0x00000001U
-#define LEDC_EVT_TIME2_CMP_EN_S  22
-/** LEDC_EVT_TIME3_CMP_EN : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_EVT_TIME3_CMP_EN    (BIT(23))
-#define LEDC_EVT_TIME3_CMP_EN_M  (LEDC_EVT_TIME3_CMP_EN_V << LEDC_EVT_TIME3_CMP_EN_S)
-#define LEDC_EVT_TIME3_CMP_EN_V  0x00000001U
-#define LEDC_EVT_TIME3_CMP_EN_S  23
-/** LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN : R/W; bitpos: [24]; default: 0;
- *  Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN    (BIT(24))
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S)
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_V  0x00000001U
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0_EN_S  24
-/** LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN : R/W; bitpos: [25]; default: 0;
- *  Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN    (BIT(25))
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S)
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_V  0x00000001U
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1_EN_S  25
-/** LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN : R/W; bitpos: [26]; default: 0;
- *  Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN    (BIT(26))
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S)
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_V  0x00000001U
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2_EN_S  26
-/** LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN : R/W; bitpos: [27]; default: 0;
- *  Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN    (BIT(27))
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S)
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_V  0x00000001U
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3_EN_S  27
-/** LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN    (BIT(28))
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S)
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_V  0x00000001U
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4_EN_S  28
-/** LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0:
- *  Disable\\1: Enable
- */
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN    (BIT(29))
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_M  (LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V << LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S)
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_V  0x00000001U
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5_EN_S  29
-
-/** LEDC_EVT_TASK_EN1_REG register
- *  Ledc event task enable bit register1.
- */
-#define LEDC_EVT_TASK_EN1_REG (DR_REG_LEDC_BASE + 0x124)
-/** LEDC_TASK_TIMER0_RES_UPDATE_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER0_RES_UPDATE_EN    (BIT(0))
-#define LEDC_TASK_TIMER0_RES_UPDATE_EN_M  (LEDC_TASK_TIMER0_RES_UPDATE_EN_V << LEDC_TASK_TIMER0_RES_UPDATE_EN_S)
-#define LEDC_TASK_TIMER0_RES_UPDATE_EN_V  0x00000001U
-#define LEDC_TASK_TIMER0_RES_UPDATE_EN_S  0
-/** LEDC_TASK_TIMER1_RES_UPDATE_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER1_RES_UPDATE_EN    (BIT(1))
-#define LEDC_TASK_TIMER1_RES_UPDATE_EN_M  (LEDC_TASK_TIMER1_RES_UPDATE_EN_V << LEDC_TASK_TIMER1_RES_UPDATE_EN_S)
-#define LEDC_TASK_TIMER1_RES_UPDATE_EN_V  0x00000001U
-#define LEDC_TASK_TIMER1_RES_UPDATE_EN_S  1
-/** LEDC_TASK_TIMER2_RES_UPDATE_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER2_RES_UPDATE_EN    (BIT(2))
-#define LEDC_TASK_TIMER2_RES_UPDATE_EN_M  (LEDC_TASK_TIMER2_RES_UPDATE_EN_V << LEDC_TASK_TIMER2_RES_UPDATE_EN_S)
-#define LEDC_TASK_TIMER2_RES_UPDATE_EN_V  0x00000001U
-#define LEDC_TASK_TIMER2_RES_UPDATE_EN_S  2
-/** LEDC_TASK_TIMER3_RES_UPDATE_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER3_RES_UPDATE_EN    (BIT(3))
-#define LEDC_TASK_TIMER3_RES_UPDATE_EN_M  (LEDC_TASK_TIMER3_RES_UPDATE_EN_V << LEDC_TASK_TIMER3_RES_UPDATE_EN_S)
-#define LEDC_TASK_TIMER3_RES_UPDATE_EN_V  0x00000001U
-#define LEDC_TASK_TIMER3_RES_UPDATE_EN_S  3
-/** LEDC_TASK_TIMER0_CAP_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER0_CAP_EN    (BIT(4))
-#define LEDC_TASK_TIMER0_CAP_EN_M  (LEDC_TASK_TIMER0_CAP_EN_V << LEDC_TASK_TIMER0_CAP_EN_S)
-#define LEDC_TASK_TIMER0_CAP_EN_V  0x00000001U
-#define LEDC_TASK_TIMER0_CAP_EN_S  4
-/** LEDC_TASK_TIMER1_CAP_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER1_CAP_EN    (BIT(5))
-#define LEDC_TASK_TIMER1_CAP_EN_M  (LEDC_TASK_TIMER1_CAP_EN_V << LEDC_TASK_TIMER1_CAP_EN_S)
-#define LEDC_TASK_TIMER1_CAP_EN_V  0x00000001U
-#define LEDC_TASK_TIMER1_CAP_EN_S  5
-/** LEDC_TASK_TIMER2_CAP_EN : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER2_CAP_EN    (BIT(6))
-#define LEDC_TASK_TIMER2_CAP_EN_M  (LEDC_TASK_TIMER2_CAP_EN_V << LEDC_TASK_TIMER2_CAP_EN_S)
-#define LEDC_TASK_TIMER2_CAP_EN_V  0x00000001U
-#define LEDC_TASK_TIMER2_CAP_EN_S  6
-/** LEDC_TASK_TIMER3_CAP_EN : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER3_CAP_EN    (BIT(7))
-#define LEDC_TASK_TIMER3_CAP_EN_M  (LEDC_TASK_TIMER3_CAP_EN_V << LEDC_TASK_TIMER3_CAP_EN_S)
-#define LEDC_TASK_TIMER3_CAP_EN_V  0x00000001U
-#define LEDC_TASK_TIMER3_CAP_EN_S  7
-/** LEDC_TASK_SIG_OUT_DIS_CH0_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_SIG_OUT_DIS_CH0_EN    (BIT(8))
-#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH0_EN_V << LEDC_TASK_SIG_OUT_DIS_CH0_EN_S)
-#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_V  0x00000001U
-#define LEDC_TASK_SIG_OUT_DIS_CH0_EN_S  8
-/** LEDC_TASK_SIG_OUT_DIS_CH1_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_SIG_OUT_DIS_CH1_EN    (BIT(9))
-#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH1_EN_V << LEDC_TASK_SIG_OUT_DIS_CH1_EN_S)
-#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_V  0x00000001U
-#define LEDC_TASK_SIG_OUT_DIS_CH1_EN_S  9
-/** LEDC_TASK_SIG_OUT_DIS_CH2_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_SIG_OUT_DIS_CH2_EN    (BIT(10))
-#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH2_EN_V << LEDC_TASK_SIG_OUT_DIS_CH2_EN_S)
-#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_V  0x00000001U
-#define LEDC_TASK_SIG_OUT_DIS_CH2_EN_S  10
-/** LEDC_TASK_SIG_OUT_DIS_CH3_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_SIG_OUT_DIS_CH3_EN    (BIT(11))
-#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH3_EN_V << LEDC_TASK_SIG_OUT_DIS_CH3_EN_S)
-#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_V  0x00000001U
-#define LEDC_TASK_SIG_OUT_DIS_CH3_EN_S  11
-/** LEDC_TASK_SIG_OUT_DIS_CH4_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_SIG_OUT_DIS_CH4_EN    (BIT(12))
-#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH4_EN_V << LEDC_TASK_SIG_OUT_DIS_CH4_EN_S)
-#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_V  0x00000001U
-#define LEDC_TASK_SIG_OUT_DIS_CH4_EN_S  12
-/** LEDC_TASK_SIG_OUT_DIS_CH5_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_SIG_OUT_DIS_CH5_EN    (BIT(13))
-#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_M  (LEDC_TASK_SIG_OUT_DIS_CH5_EN_V << LEDC_TASK_SIG_OUT_DIS_CH5_EN_S)
-#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_V  0x00000001U
-#define LEDC_TASK_SIG_OUT_DIS_CH5_EN_S  13
-/** LEDC_TASK_OVF_CNT_RST_CH0_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_OVF_CNT_RST_CH0_EN    (BIT(16))
-#define LEDC_TASK_OVF_CNT_RST_CH0_EN_M  (LEDC_TASK_OVF_CNT_RST_CH0_EN_V << LEDC_TASK_OVF_CNT_RST_CH0_EN_S)
-#define LEDC_TASK_OVF_CNT_RST_CH0_EN_V  0x00000001U
-#define LEDC_TASK_OVF_CNT_RST_CH0_EN_S  16
-/** LEDC_TASK_OVF_CNT_RST_CH1_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_OVF_CNT_RST_CH1_EN    (BIT(17))
-#define LEDC_TASK_OVF_CNT_RST_CH1_EN_M  (LEDC_TASK_OVF_CNT_RST_CH1_EN_V << LEDC_TASK_OVF_CNT_RST_CH1_EN_S)
-#define LEDC_TASK_OVF_CNT_RST_CH1_EN_V  0x00000001U
-#define LEDC_TASK_OVF_CNT_RST_CH1_EN_S  17
-/** LEDC_TASK_OVF_CNT_RST_CH2_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_OVF_CNT_RST_CH2_EN    (BIT(18))
-#define LEDC_TASK_OVF_CNT_RST_CH2_EN_M  (LEDC_TASK_OVF_CNT_RST_CH2_EN_V << LEDC_TASK_OVF_CNT_RST_CH2_EN_S)
-#define LEDC_TASK_OVF_CNT_RST_CH2_EN_V  0x00000001U
-#define LEDC_TASK_OVF_CNT_RST_CH2_EN_S  18
-/** LEDC_TASK_OVF_CNT_RST_CH3_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_OVF_CNT_RST_CH3_EN    (BIT(19))
-#define LEDC_TASK_OVF_CNT_RST_CH3_EN_M  (LEDC_TASK_OVF_CNT_RST_CH3_EN_V << LEDC_TASK_OVF_CNT_RST_CH3_EN_S)
-#define LEDC_TASK_OVF_CNT_RST_CH3_EN_V  0x00000001U
-#define LEDC_TASK_OVF_CNT_RST_CH3_EN_S  19
-/** LEDC_TASK_OVF_CNT_RST_CH4_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_OVF_CNT_RST_CH4_EN    (BIT(20))
-#define LEDC_TASK_OVF_CNT_RST_CH4_EN_M  (LEDC_TASK_OVF_CNT_RST_CH4_EN_V << LEDC_TASK_OVF_CNT_RST_CH4_EN_S)
-#define LEDC_TASK_OVF_CNT_RST_CH4_EN_V  0x00000001U
-#define LEDC_TASK_OVF_CNT_RST_CH4_EN_S  20
-/** LEDC_TASK_OVF_CNT_RST_CH5_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_OVF_CNT_RST_CH5_EN    (BIT(21))
-#define LEDC_TASK_OVF_CNT_RST_CH5_EN_M  (LEDC_TASK_OVF_CNT_RST_CH5_EN_V << LEDC_TASK_OVF_CNT_RST_CH5_EN_S)
-#define LEDC_TASK_OVF_CNT_RST_CH5_EN_V  0x00000001U
-#define LEDC_TASK_OVF_CNT_RST_CH5_EN_S  21
-/** LEDC_TASK_TIMER0_RST_EN : R/W; bitpos: [24]; default: 0;
- *  Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER0_RST_EN    (BIT(24))
-#define LEDC_TASK_TIMER0_RST_EN_M  (LEDC_TASK_TIMER0_RST_EN_V << LEDC_TASK_TIMER0_RST_EN_S)
-#define LEDC_TASK_TIMER0_RST_EN_V  0x00000001U
-#define LEDC_TASK_TIMER0_RST_EN_S  24
-/** LEDC_TASK_TIMER1_RST_EN : R/W; bitpos: [25]; default: 0;
- *  Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER1_RST_EN    (BIT(25))
-#define LEDC_TASK_TIMER1_RST_EN_M  (LEDC_TASK_TIMER1_RST_EN_V << LEDC_TASK_TIMER1_RST_EN_S)
-#define LEDC_TASK_TIMER1_RST_EN_V  0x00000001U
-#define LEDC_TASK_TIMER1_RST_EN_S  25
-/** LEDC_TASK_TIMER2_RST_EN : R/W; bitpos: [26]; default: 0;
- *  Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER2_RST_EN    (BIT(26))
-#define LEDC_TASK_TIMER2_RST_EN_M  (LEDC_TASK_TIMER2_RST_EN_V << LEDC_TASK_TIMER2_RST_EN_S)
-#define LEDC_TASK_TIMER2_RST_EN_V  0x00000001U
-#define LEDC_TASK_TIMER2_RST_EN_S  26
-/** LEDC_TASK_TIMER3_RST_EN : R/W; bitpos: [27]; default: 0;
- *  Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable
- */
-#define LEDC_TASK_TIMER3_RST_EN    (BIT(27))
-#define LEDC_TASK_TIMER3_RST_EN_M  (LEDC_TASK_TIMER3_RST_EN_V << LEDC_TASK_TIMER3_RST_EN_S)
-#define LEDC_TASK_TIMER3_RST_EN_V  0x00000001U
-#define LEDC_TASK_TIMER3_RST_EN_S  27
-/** LEDC_TASK_TIMER0_PAUSE_RESUME_EN : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN    (BIT(28))
-#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S)
-#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_V  0x00000001U
-#define LEDC_TASK_TIMER0_PAUSE_RESUME_EN_S  28
-/** LEDC_TASK_TIMER1_PAUSE_RESUME_EN : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN    (BIT(29))
-#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S)
-#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_V  0x00000001U
-#define LEDC_TASK_TIMER1_PAUSE_RESUME_EN_S  29
-/** LEDC_TASK_TIMER2_PAUSE_RESUME_EN : R/W; bitpos: [30]; default: 0;
- *  Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN    (BIT(30))
-#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S)
-#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_V  0x00000001U
-#define LEDC_TASK_TIMER2_PAUSE_RESUME_EN_S  30
-/** LEDC_TASK_TIMER3_PAUSE_RESUME_EN : R/W; bitpos: [31]; default: 0;
- *  Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN    (BIT(31))
-#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_M  (LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V << LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S)
-#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_V  0x00000001U
-#define LEDC_TASK_TIMER3_PAUSE_RESUME_EN_S  31
-
-/** LEDC_EVT_TASK_EN2_REG register
- *  Ledc event task enable bit register2.
- */
-#define LEDC_EVT_TASK_EN2_REG (DR_REG_LEDC_BASE + 0x128)
-/** LEDC_TASK_GAMMA_RESTART_CH0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESTART_CH0_EN    (BIT(0))
-#define LEDC_TASK_GAMMA_RESTART_CH0_EN_M  (LEDC_TASK_GAMMA_RESTART_CH0_EN_V << LEDC_TASK_GAMMA_RESTART_CH0_EN_S)
-#define LEDC_TASK_GAMMA_RESTART_CH0_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESTART_CH0_EN_S  0
-/** LEDC_TASK_GAMMA_RESTART_CH1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESTART_CH1_EN    (BIT(1))
-#define LEDC_TASK_GAMMA_RESTART_CH1_EN_M  (LEDC_TASK_GAMMA_RESTART_CH1_EN_V << LEDC_TASK_GAMMA_RESTART_CH1_EN_S)
-#define LEDC_TASK_GAMMA_RESTART_CH1_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESTART_CH1_EN_S  1
-/** LEDC_TASK_GAMMA_RESTART_CH2_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESTART_CH2_EN    (BIT(2))
-#define LEDC_TASK_GAMMA_RESTART_CH2_EN_M  (LEDC_TASK_GAMMA_RESTART_CH2_EN_V << LEDC_TASK_GAMMA_RESTART_CH2_EN_S)
-#define LEDC_TASK_GAMMA_RESTART_CH2_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESTART_CH2_EN_S  2
-/** LEDC_TASK_GAMMA_RESTART_CH3_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESTART_CH3_EN    (BIT(3))
-#define LEDC_TASK_GAMMA_RESTART_CH3_EN_M  (LEDC_TASK_GAMMA_RESTART_CH3_EN_V << LEDC_TASK_GAMMA_RESTART_CH3_EN_S)
-#define LEDC_TASK_GAMMA_RESTART_CH3_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESTART_CH3_EN_S  3
-/** LEDC_TASK_GAMMA_RESTART_CH4_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESTART_CH4_EN    (BIT(4))
-#define LEDC_TASK_GAMMA_RESTART_CH4_EN_M  (LEDC_TASK_GAMMA_RESTART_CH4_EN_V << LEDC_TASK_GAMMA_RESTART_CH4_EN_S)
-#define LEDC_TASK_GAMMA_RESTART_CH4_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESTART_CH4_EN_S  4
-/** LEDC_TASK_GAMMA_RESTART_CH5_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESTART_CH5_EN    (BIT(5))
-#define LEDC_TASK_GAMMA_RESTART_CH5_EN_M  (LEDC_TASK_GAMMA_RESTART_CH5_EN_V << LEDC_TASK_GAMMA_RESTART_CH5_EN_S)
-#define LEDC_TASK_GAMMA_RESTART_CH5_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESTART_CH5_EN_S  5
-/** LEDC_TASK_GAMMA_PAUSE_CH0_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_PAUSE_CH0_EN    (BIT(8))
-#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH0_EN_V << LEDC_TASK_GAMMA_PAUSE_CH0_EN_S)
-#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_PAUSE_CH0_EN_S  8
-/** LEDC_TASK_GAMMA_PAUSE_CH1_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_PAUSE_CH1_EN    (BIT(9))
-#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH1_EN_V << LEDC_TASK_GAMMA_PAUSE_CH1_EN_S)
-#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_PAUSE_CH1_EN_S  9
-/** LEDC_TASK_GAMMA_PAUSE_CH2_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_PAUSE_CH2_EN    (BIT(10))
-#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH2_EN_V << LEDC_TASK_GAMMA_PAUSE_CH2_EN_S)
-#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_PAUSE_CH2_EN_S  10
-/** LEDC_TASK_GAMMA_PAUSE_CH3_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_PAUSE_CH3_EN    (BIT(11))
-#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH3_EN_V << LEDC_TASK_GAMMA_PAUSE_CH3_EN_S)
-#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_PAUSE_CH3_EN_S  11
-/** LEDC_TASK_GAMMA_PAUSE_CH4_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_PAUSE_CH4_EN    (BIT(12))
-#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH4_EN_V << LEDC_TASK_GAMMA_PAUSE_CH4_EN_S)
-#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_PAUSE_CH4_EN_S  12
-/** LEDC_TASK_GAMMA_PAUSE_CH5_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_PAUSE_CH5_EN    (BIT(13))
-#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_M  (LEDC_TASK_GAMMA_PAUSE_CH5_EN_V << LEDC_TASK_GAMMA_PAUSE_CH5_EN_S)
-#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_PAUSE_CH5_EN_S  13
-/** LEDC_TASK_GAMMA_RESUME_CH0_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESUME_CH0_EN    (BIT(16))
-#define LEDC_TASK_GAMMA_RESUME_CH0_EN_M  (LEDC_TASK_GAMMA_RESUME_CH0_EN_V << LEDC_TASK_GAMMA_RESUME_CH0_EN_S)
-#define LEDC_TASK_GAMMA_RESUME_CH0_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESUME_CH0_EN_S  16
-/** LEDC_TASK_GAMMA_RESUME_CH1_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESUME_CH1_EN    (BIT(17))
-#define LEDC_TASK_GAMMA_RESUME_CH1_EN_M  (LEDC_TASK_GAMMA_RESUME_CH1_EN_V << LEDC_TASK_GAMMA_RESUME_CH1_EN_S)
-#define LEDC_TASK_GAMMA_RESUME_CH1_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESUME_CH1_EN_S  17
-/** LEDC_TASK_GAMMA_RESUME_CH2_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESUME_CH2_EN    (BIT(18))
-#define LEDC_TASK_GAMMA_RESUME_CH2_EN_M  (LEDC_TASK_GAMMA_RESUME_CH2_EN_V << LEDC_TASK_GAMMA_RESUME_CH2_EN_S)
-#define LEDC_TASK_GAMMA_RESUME_CH2_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESUME_CH2_EN_S  18
-/** LEDC_TASK_GAMMA_RESUME_CH3_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESUME_CH3_EN    (BIT(19))
-#define LEDC_TASK_GAMMA_RESUME_CH3_EN_M  (LEDC_TASK_GAMMA_RESUME_CH3_EN_V << LEDC_TASK_GAMMA_RESUME_CH3_EN_S)
-#define LEDC_TASK_GAMMA_RESUME_CH3_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESUME_CH3_EN_S  19
-/** LEDC_TASK_GAMMA_RESUME_CH4_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESUME_CH4_EN    (BIT(20))
-#define LEDC_TASK_GAMMA_RESUME_CH4_EN_M  (LEDC_TASK_GAMMA_RESUME_CH4_EN_V << LEDC_TASK_GAMMA_RESUME_CH4_EN_S)
-#define LEDC_TASK_GAMMA_RESUME_CH4_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESUME_CH4_EN_S  20
-/** LEDC_TASK_GAMMA_RESUME_CH5_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1:
- *  Enable
- */
-#define LEDC_TASK_GAMMA_RESUME_CH5_EN    (BIT(21))
-#define LEDC_TASK_GAMMA_RESUME_CH5_EN_M  (LEDC_TASK_GAMMA_RESUME_CH5_EN_V << LEDC_TASK_GAMMA_RESUME_CH5_EN_S)
-#define LEDC_TASK_GAMMA_RESUME_CH5_EN_V  0x00000001U
-#define LEDC_TASK_GAMMA_RESUME_CH5_EN_S  21
-
-/** LEDC_TIMER0_CMP_REG register
- *  Ledc timer0 compare value register.
- */
-#define LEDC_TIMER0_CMP_REG (DR_REG_LEDC_BASE + 0x140)
-/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0;
- *  Configures the comparison value for LEDC timer0.
- */
-#define LEDC_TIMER0_CMP    0x000FFFFFU
-#define LEDC_TIMER0_CMP_M  (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S)
-#define LEDC_TIMER0_CMP_V  0x000FFFFFU
-#define LEDC_TIMER0_CMP_S  0
-
-/** LEDC_TIMER1_CMP_REG register
- *  Ledc timer1 compare value register.
- */
-#define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144)
-/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0;
- *  Configures the comparison value for LEDC timer1.
- */
-#define LEDC_TIMER1_CMP    0x000FFFFFU
-#define LEDC_TIMER1_CMP_M  (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S)
-#define LEDC_TIMER1_CMP_V  0x000FFFFFU
-#define LEDC_TIMER1_CMP_S  0
-
-/** LEDC_TIMER2_CMP_REG register
- *  Ledc timer2 compare value register.
- */
-#define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148)
-/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0;
- *  Configures the comparison value for LEDC timer2.
- */
-#define LEDC_TIMER2_CMP    0x000FFFFFU
-#define LEDC_TIMER2_CMP_M  (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S)
-#define LEDC_TIMER2_CMP_V  0x000FFFFFU
-#define LEDC_TIMER2_CMP_S  0
-
-/** LEDC_TIMER3_CMP_REG register
- *  Ledc timer3 compare value register.
- */
-#define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c)
-/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0;
- *  Configures the comparison value for LEDC timer3.
- */
-#define LEDC_TIMER3_CMP    0x000FFFFFU
-#define LEDC_TIMER3_CMP_M  (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S)
-#define LEDC_TIMER3_CMP_V  0x000FFFFFU
-#define LEDC_TIMER3_CMP_S  0
-
-/** LEDC_TIMER0_CNT_CAP_REG register
- *  Ledc timer0 captured count value register.
- */
-#define LEDC_TIMER0_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x150)
-/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0;
- *  Represents the captured LEDC timer0 count value.
- */
-#define LEDC_TIMER0_CNT_CAP    0x000FFFFFU
-#define LEDC_TIMER0_CNT_CAP_M  (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S)
-#define LEDC_TIMER0_CNT_CAP_V  0x000FFFFFU
-#define LEDC_TIMER0_CNT_CAP_S  0
-
-/** LEDC_TIMER1_CNT_CAP_REG register
- *  Ledc timer1 captured count value register.
- */
-#define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154)
-/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0;
- *  Represents the captured LEDC timer1 count value.
- */
-#define LEDC_TIMER1_CNT_CAP    0x000FFFFFU
-#define LEDC_TIMER1_CNT_CAP_M  (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S)
-#define LEDC_TIMER1_CNT_CAP_V  0x000FFFFFU
-#define LEDC_TIMER1_CNT_CAP_S  0
-
-/** LEDC_TIMER2_CNT_CAP_REG register
- *  Ledc timer2 captured count value register.
- */
-#define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158)
-/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0;
- *  Represents the captured LEDC timer2 count value.
- */
-#define LEDC_TIMER2_CNT_CAP    0x000FFFFFU
-#define LEDC_TIMER2_CNT_CAP_M  (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S)
-#define LEDC_TIMER2_CNT_CAP_V  0x000FFFFFU
-#define LEDC_TIMER2_CNT_CAP_S  0
-
-/** LEDC_TIMER3_CNT_CAP_REG register
- *  Ledc timer3 captured count value register.
- */
-#define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c)
-/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0;
- *  Represents the captured LEDC timer3 count value.
- */
-#define LEDC_TIMER3_CNT_CAP    0x000FFFFFU
-#define LEDC_TIMER3_CNT_CAP_M  (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S)
-#define LEDC_TIMER3_CNT_CAP_V  0x000FFFFFU
-#define LEDC_TIMER3_CNT_CAP_S  0
-
-/** LEDC_CONF_REG register
- *  LEDC global configuration register
- */
-#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x170)
-/** LEDC_GAMMA_RAM_CLK_EN_CH0 : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock
- *  gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the
- *  clock gate for LEDC ch0 gamma ram
- */
-#define LEDC_GAMMA_RAM_CLK_EN_CH0    (BIT(2))
-#define LEDC_GAMMA_RAM_CLK_EN_CH0_M  (LEDC_GAMMA_RAM_CLK_EN_CH0_V << LEDC_GAMMA_RAM_CLK_EN_CH0_S)
-#define LEDC_GAMMA_RAM_CLK_EN_CH0_V  0x00000001U
-#define LEDC_GAMMA_RAM_CLK_EN_CH0_S  2
-/** LEDC_GAMMA_RAM_CLK_EN_CH1 : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock
- *  gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the
- *  clock gate for LEDC ch1 gamma ram
- */
-#define LEDC_GAMMA_RAM_CLK_EN_CH1    (BIT(3))
-#define LEDC_GAMMA_RAM_CLK_EN_CH1_M  (LEDC_GAMMA_RAM_CLK_EN_CH1_V << LEDC_GAMMA_RAM_CLK_EN_CH1_S)
-#define LEDC_GAMMA_RAM_CLK_EN_CH1_V  0x00000001U
-#define LEDC_GAMMA_RAM_CLK_EN_CH1_S  3
-/** LEDC_GAMMA_RAM_CLK_EN_CH2 : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock
- *  gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the
- *  clock gate for LEDC ch2 gamma ram
- */
-#define LEDC_GAMMA_RAM_CLK_EN_CH2    (BIT(4))
-#define LEDC_GAMMA_RAM_CLK_EN_CH2_M  (LEDC_GAMMA_RAM_CLK_EN_CH2_V << LEDC_GAMMA_RAM_CLK_EN_CH2_S)
-#define LEDC_GAMMA_RAM_CLK_EN_CH2_V  0x00000001U
-#define LEDC_GAMMA_RAM_CLK_EN_CH2_S  4
-/** LEDC_GAMMA_RAM_CLK_EN_CH3 : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock
- *  gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the
- *  clock gate for LEDC ch3 gamma ram
- */
-#define LEDC_GAMMA_RAM_CLK_EN_CH3    (BIT(5))
-#define LEDC_GAMMA_RAM_CLK_EN_CH3_M  (LEDC_GAMMA_RAM_CLK_EN_CH3_V << LEDC_GAMMA_RAM_CLK_EN_CH3_S)
-#define LEDC_GAMMA_RAM_CLK_EN_CH3_V  0x00000001U
-#define LEDC_GAMMA_RAM_CLK_EN_CH3_S  5
-/** LEDC_GAMMA_RAM_CLK_EN_CH4 : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock
- *  gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the
- *  clock gate for LEDC ch4 gamma ram
- */
-#define LEDC_GAMMA_RAM_CLK_EN_CH4    (BIT(6))
-#define LEDC_GAMMA_RAM_CLK_EN_CH4_M  (LEDC_GAMMA_RAM_CLK_EN_CH4_V << LEDC_GAMMA_RAM_CLK_EN_CH4_S)
-#define LEDC_GAMMA_RAM_CLK_EN_CH4_V  0x00000001U
-#define LEDC_GAMMA_RAM_CLK_EN_CH4_S  6
-/** LEDC_GAMMA_RAM_CLK_EN_CH5 : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock
- *  gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the
- *  clock gate for LEDC ch5 gamma ram
- */
-#define LEDC_GAMMA_RAM_CLK_EN_CH5    (BIT(7))
-#define LEDC_GAMMA_RAM_CLK_EN_CH5_M  (LEDC_GAMMA_RAM_CLK_EN_CH5_V << LEDC_GAMMA_RAM_CLK_EN_CH5_S)
-#define LEDC_GAMMA_RAM_CLK_EN_CH5_V  0x00000001U
-#define LEDC_GAMMA_RAM_CLK_EN_CH5_S  7
-/** LEDC_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
- *  when application writes registers\\1: Force open the clock gate for register
- */
-#define LEDC_CLK_EN    (BIT(31))
-#define LEDC_CLK_EN_M  (LEDC_CLK_EN_V << LEDC_CLK_EN_S)
-#define LEDC_CLK_EN_V  0x00000001U
-#define LEDC_CLK_EN_S  31
-
-/** LEDC_DATE_REG register
- *  Version control register
- */
-#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x174)
-/** LEDC_LEDC_DATE : R/W; bitpos: [27:0]; default: 36716928;
- *  Configures the version.
- */
-#define LEDC_LEDC_DATE    0x0FFFFFFFU
-#define LEDC_LEDC_DATE_M  (LEDC_LEDC_DATE_V << LEDC_LEDC_DATE_S)
-#define LEDC_LEDC_DATE_V  0x0FFFFFFFU
-#define LEDC_LEDC_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/ledc_struct.h b/components/soc/esp32c5/beta3/include/soc/ledc_struct.h
deleted file mode 100644
index c068877af0..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/ledc_struct.h
+++ /dev/null
@@ -1,1080 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of chn_conf0 register
- *  Configuration register 0 for channel n
- */
-typedef union {
-    struct {
-        /** timer_sel_chn : R/W; bitpos: [1:0]; default: 0;
-         *  Configures which timer is channel n selected.\\0: Select timer0\\1: Select
-         *  timer1\\2: Select timer2\\3: Select timer3
-         */
-        uint32_t timer_sel_chn:2;
-        /** sig_out_en_chn : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable signal output on channel n.\\0: Signal output
-         *  disable\\1: Signal output enable
-         */
-        uint32_t sig_out_en_chn:1;
-        /** idle_lv_chn : R/W; bitpos: [3]; default: 0;
-         *  Configures the output value when channel n is inactive. Valid only when
-         *  LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high
-         */
-        uint32_t idle_lv_chn:1;
-        /** para_up_chn : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
-         *  LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn,
-         *  LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel
-         *  n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update
-         */
-        uint32_t para_up_chn:1;
-        /** ovf_num_chn : R/W; bitpos: [14:5]; default: 0;
-         *  Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt
-         *  will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times.
-         */
-        uint32_t ovf_num_chn:10;
-        /** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable
-         */
-        uint32_t ovf_cnt_en_chn:1;
-        /** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to reset the  ovf_cnt of channel n.\\0: Invalid. No
-         *  effect\\1: Reset the ovf_cnt
-         */
-        uint32_t ovf_cnt_reset_chn:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} ledc_chn_conf0_reg_t;
-
-/** Type of chn_hpoint register
- *  High point register for channel n
- */
-typedef union {
-    struct {
-        /** hpoint_chn : R/W; bitpos: [19:0]; default: 0;
-         *  Configures high point of signal output on channel n. The output value changes to
-         *  high when the selected timers has reached the value specified by this register.
-         */
-        uint32_t hpoint_chn:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} ledc_chn_hpoint_reg_t;
-
-/** Type of chn_duty register
- *  Initial duty cycle register for channel n
- */
-typedef union {
-    struct {
-        /** duty_chn : R/W; bitpos: [24:0]; default: 0;
-         *  Configures the duty of signal output on channel n.
-         */
-        uint32_t duty_chn:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} ledc_chn_duty_reg_t;
-
-/** Type of chn_conf1 register
- *  Configuration register 1 for channel n
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** duty_start_chn : R/W/SC; bitpos: [31]; default: 0;
-         *  Configures whether the duty cycle fading configurations take effect.\\0: Not take
-         *  effect\\1: Take effect
-         */
-        uint32_t duty_start_chn:1;
-    };
-    uint32_t val;
-} ledc_chn_conf1_reg_t;
-
-/** Type of chn_duty_r register
- *  Current duty cycle register for channel n
- */
-typedef union {
-    struct {
-        /** duty_chn_r : RO; bitpos: [24:0]; default: 0;
-         *  Represents the current duty of output signal on channel n.
-         */
-        uint32_t duty_chn_r:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} ledc_chn_duty_r_reg_t;
-
-
-/** Group: timer conf */
-/** Type of timern_conf register
- *  Timer n configuration register
- */
-typedef union {
-    struct {
-        /** timern_duty_res : R/W; bitpos: [4:0]; default: 0;
-         *  Configures the range of the counter in timer n.
-         */
-        uint32_t timern_duty_res:5;
-        /** clk_div_timern : R/W; bitpos: [22:5]; default: 0;
-         *  Configures the divisor for the divider in timer n.The least significant eight bits
-         *  represent the fractional part.
-         */
-        uint32_t clk_div_timern:18;
-        /** timern_pause : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause
-         */
-        uint32_t timern_pause:1;
-        /** timern_rst : R/W; bitpos: [24]; default: 1;
-         *  Configures whether or not to reset timer n. The counter will show 0 after
-         *  reset.\\0: Not reset\\1: Reset
-         */
-        uint32_t timern_rst:1;
-        uint32_t reserved_25:1;
-        /** timern_para_up : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to update LEDC_CLK_DIV_TIMERn and
-         *  LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update
-         */
-        uint32_t timern_para_up:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} ledc_timern_conf_reg_t;
-
-/** Type of timern_value register
- *  Timer n current counter value register
- */
-typedef union {
-    struct {
-        /** timern_cnt : RO; bitpos: [19:0]; default: 0;
-         *  Represents the current counter value of timer n.
-         */
-        uint32_t timern_cnt:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} ledc_timern_value_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Interrupt raw status register
- */
-typedef union {
-    struct {
-        /** timer0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the
-         *  timer0 has reached its maximum counter value.
-         */
-        uint32_t timer0_ovf_int_raw:1;
-        /** timer1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the
-         *  timer1 has reached its maximum counter value.
-         */
-        uint32_t timer1_ovf_int_raw:1;
-        /** timer2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the
-         *  timer2 has reached its maximum counter value.
-         */
-        uint32_t timer2_ovf_int_raw:1;
-        /** timer3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the
-         *  timer3 has reached its maximum counter value.
-         */
-        uint32_t timer3_ovf_int_raw:1;
-        /** duty_chng_end_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered
-         *  when the fading of duty has finished.
-         */
-        uint32_t duty_chng_end_ch0_int_raw:1;
-        /** duty_chng_end_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered
-         *  when the fading of duty has finished.
-         */
-        uint32_t duty_chng_end_ch1_int_raw:1;
-        /** duty_chng_end_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered
-         *  when the fading of duty has finished.
-         */
-        uint32_t duty_chng_end_ch2_int_raw:1;
-        /** duty_chng_end_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered
-         *  when the fading of duty has finished.
-         */
-        uint32_t duty_chng_end_ch3_int_raw:1;
-        /** duty_chng_end_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered
-         *  when the fading of duty has finished.
-         */
-        uint32_t duty_chng_end_ch4_int_raw:1;
-        /** duty_chng_end_ch5_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered
-         *  when the fading of duty has finished.
-         */
-        uint32_t duty_chng_end_ch5_int_raw:1;
-        uint32_t reserved_10:2;
-        /** ovf_cnt_ch0_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when
-         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.
-         */
-        uint32_t ovf_cnt_ch0_int_raw:1;
-        /** ovf_cnt_ch1_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when
-         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.
-         */
-        uint32_t ovf_cnt_ch1_int_raw:1;
-        /** ovf_cnt_ch2_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when
-         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.
-         */
-        uint32_t ovf_cnt_ch2_int_raw:1;
-        /** ovf_cnt_ch3_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when
-         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.
-         */
-        uint32_t ovf_cnt_ch3_int_raw:1;
-        /** ovf_cnt_ch4_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when
-         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.
-         */
-        uint32_t ovf_cnt_ch4_int_raw:1;
-        /** ovf_cnt_ch5_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when
-         *  the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.
-         */
-        uint32_t ovf_cnt_ch5_int_raw:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} ledc_int_raw_reg_t;
-
-/** Type of int_st register
- *  Interrupt masked status register
- */
-typedef union {
-    struct {
-        /** timer0_ovf_int_st : RO; bitpos: [0]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only
-         *  when LEDC_TIMER0_OVF_INT_ENA is set to 1.
-         */
-        uint32_t timer0_ovf_int_st:1;
-        /** timer1_ovf_int_st : RO; bitpos: [1]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only
-         *  when LEDC_TIMER1_OVF_INT_ENA is set to 1.
-         */
-        uint32_t timer1_ovf_int_st:1;
-        /** timer2_ovf_int_st : RO; bitpos: [2]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only
-         *  when LEDC_TIMER2_OVF_INT_ENA is set to 1.
-         */
-        uint32_t timer2_ovf_int_st:1;
-        /** timer3_ovf_int_st : RO; bitpos: [3]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only
-         *  when LEDC_TIMER3_OVF_INT_ENA is set to 1.
-         */
-        uint32_t timer3_ovf_int_st:1;
-        /** duty_chng_end_ch0_int_st : RO; bitpos: [4]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid
-         *  only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.
-         */
-        uint32_t duty_chng_end_ch0_int_st:1;
-        /** duty_chng_end_ch1_int_st : RO; bitpos: [5]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid
-         *  only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.
-         */
-        uint32_t duty_chng_end_ch1_int_st:1;
-        /** duty_chng_end_ch2_int_st : RO; bitpos: [6]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid
-         *  only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.
-         */
-        uint32_t duty_chng_end_ch2_int_st:1;
-        /** duty_chng_end_ch3_int_st : RO; bitpos: [7]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid
-         *  only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.
-         */
-        uint32_t duty_chng_end_ch3_int_st:1;
-        /** duty_chng_end_ch4_int_st : RO; bitpos: [8]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid
-         *  only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.
-         */
-        uint32_t duty_chng_end_ch4_int_st:1;
-        /** duty_chng_end_ch5_int_st : RO; bitpos: [9]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid
-         *  only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.
-         */
-        uint32_t duty_chng_end_ch5_int_st:1;
-        uint32_t reserved_10:2;
-        /** ovf_cnt_ch0_int_st : RO; bitpos: [12]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only
-         *  when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
-         */
-        uint32_t ovf_cnt_ch0_int_st:1;
-        /** ovf_cnt_ch1_int_st : RO; bitpos: [13]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only
-         *  when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
-         */
-        uint32_t ovf_cnt_ch1_int_st:1;
-        /** ovf_cnt_ch2_int_st : RO; bitpos: [14]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only
-         *  when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
-         */
-        uint32_t ovf_cnt_ch2_int_st:1;
-        /** ovf_cnt_ch3_int_st : RO; bitpos: [15]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only
-         *  when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
-         */
-        uint32_t ovf_cnt_ch3_int_st:1;
-        /** ovf_cnt_ch4_int_st : RO; bitpos: [16]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only
-         *  when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
-         */
-        uint32_t ovf_cnt_ch4_int_st:1;
-        /** ovf_cnt_ch5_int_st : RO; bitpos: [17]; default: 0;
-         *  Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only
-         *  when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
-         */
-        uint32_t ovf_cnt_ch5_int_st:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} ledc_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable register
- */
-typedef union {
-    struct {
-        /** timer0_ovf_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT.
-         */
-        uint32_t timer0_ovf_int_ena:1;
-        /** timer1_ovf_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT.
-         */
-        uint32_t timer1_ovf_int_ena:1;
-        /** timer2_ovf_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT.
-         */
-        uint32_t timer2_ovf_int_ena:1;
-        /** timer3_ovf_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT.
-         */
-        uint32_t timer3_ovf_int_ena:1;
-        /** duty_chng_end_ch0_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT.
-         */
-        uint32_t duty_chng_end_ch0_int_ena:1;
-        /** duty_chng_end_ch1_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT.
-         */
-        uint32_t duty_chng_end_ch1_int_ena:1;
-        /** duty_chng_end_ch2_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT.
-         */
-        uint32_t duty_chng_end_ch2_int_ena:1;
-        /** duty_chng_end_ch3_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT.
-         */
-        uint32_t duty_chng_end_ch3_int_ena:1;
-        /** duty_chng_end_ch4_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT.
-         */
-        uint32_t duty_chng_end_ch4_int_ena:1;
-        /** duty_chng_end_ch5_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT.
-         */
-        uint32_t duty_chng_end_ch5_int_ena:1;
-        uint32_t reserved_10:2;
-        /** ovf_cnt_ch0_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT.
-         */
-        uint32_t ovf_cnt_ch0_int_ena:1;
-        /** ovf_cnt_ch1_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT.
-         */
-        uint32_t ovf_cnt_ch1_int_ena:1;
-        /** ovf_cnt_ch2_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT.
-         */
-        uint32_t ovf_cnt_ch2_int_ena:1;
-        /** ovf_cnt_ch3_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT.
-         */
-        uint32_t ovf_cnt_ch3_int_ena:1;
-        /** ovf_cnt_ch4_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT.
-         */
-        uint32_t ovf_cnt_ch4_int_ena:1;
-        /** ovf_cnt_ch5_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT.
-         */
-        uint32_t ovf_cnt_ch5_int_ena:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} ledc_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear register
- */
-typedef union {
-    struct {
-        /** timer0_ovf_int_clr : WT; bitpos: [0]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT.
-         */
-        uint32_t timer0_ovf_int_clr:1;
-        /** timer1_ovf_int_clr : WT; bitpos: [1]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT.
-         */
-        uint32_t timer1_ovf_int_clr:1;
-        /** timer2_ovf_int_clr : WT; bitpos: [2]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT.
-         */
-        uint32_t timer2_ovf_int_clr:1;
-        /** timer3_ovf_int_clr : WT; bitpos: [3]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT.
-         */
-        uint32_t timer3_ovf_int_clr:1;
-        /** duty_chng_end_ch0_int_clr : WT; bitpos: [4]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT.
-         */
-        uint32_t duty_chng_end_ch0_int_clr:1;
-        /** duty_chng_end_ch1_int_clr : WT; bitpos: [5]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT.
-         */
-        uint32_t duty_chng_end_ch1_int_clr:1;
-        /** duty_chng_end_ch2_int_clr : WT; bitpos: [6]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT.
-         */
-        uint32_t duty_chng_end_ch2_int_clr:1;
-        /** duty_chng_end_ch3_int_clr : WT; bitpos: [7]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT.
-         */
-        uint32_t duty_chng_end_ch3_int_clr:1;
-        /** duty_chng_end_ch4_int_clr : WT; bitpos: [8]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT.
-         */
-        uint32_t duty_chng_end_ch4_int_clr:1;
-        /** duty_chng_end_ch5_int_clr : WT; bitpos: [9]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT.
-         */
-        uint32_t duty_chng_end_ch5_int_clr:1;
-        uint32_t reserved_10:2;
-        /** ovf_cnt_ch0_int_clr : WT; bitpos: [12]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT.
-         */
-        uint32_t ovf_cnt_ch0_int_clr:1;
-        /** ovf_cnt_ch1_int_clr : WT; bitpos: [13]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT.
-         */
-        uint32_t ovf_cnt_ch1_int_clr:1;
-        /** ovf_cnt_ch2_int_clr : WT; bitpos: [14]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT.
-         */
-        uint32_t ovf_cnt_ch2_int_clr:1;
-        /** ovf_cnt_ch3_int_clr : WT; bitpos: [15]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT.
-         */
-        uint32_t ovf_cnt_ch3_int_clr:1;
-        /** ovf_cnt_ch4_int_clr : WT; bitpos: [16]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT.
-         */
-        uint32_t ovf_cnt_ch4_int_clr:1;
-        /** ovf_cnt_ch5_int_clr : WT; bitpos: [17]; default: 0;
-         *  Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT.
-         */
-        uint32_t ovf_cnt_ch5_int_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} ledc_int_clr_reg_t;
-
-
-/** Group: gamma */
-/** Type of chn_gamma_conf register
- *  Ledc chn gamma config register.
- */
-typedef union {
-    struct {
-        /** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
-         *  Configures the number of duty cycle fading rages for LEDC chn.
-         */
-        uint32_t chn_gamma_entry_num:5;
-        /** chn_gamma_pause : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No
-         *  effect\\1: Pause
-         */
-        uint32_t chn_gamma_pause:1;
-        /** chn_gamma_resume : WT; bitpos: [6]; default: 0;
-         *  Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No
-         *  effect\\1: Resume
-         */
-        uint32_t chn_gamma_resume:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} ledc_chn_gamma_conf_reg_t;
-
-
-/** Group: ledc etm */
-/** Type of evt_task_en0 register
- *  Ledc event task enable bit register0.
- */
-typedef union {
-    struct {
-        /** evt_duty_chng_end_ch0_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_duty_chng_end_ch0_en:1;
-        /** evt_duty_chng_end_ch1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_duty_chng_end_ch1_en:1;
-        /** evt_duty_chng_end_ch2_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_duty_chng_end_ch2_en:1;
-        /** evt_duty_chng_end_ch3_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_duty_chng_end_ch3_en:1;
-        /** evt_duty_chng_end_ch4_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_duty_chng_end_ch4_en:1;
-        /** evt_duty_chng_end_ch5_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_duty_chng_end_ch5_en:1;
-        uint32_t reserved_6:2;
-        /** evt_ovf_cnt_pls_ch0_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_ovf_cnt_pls_ch0_en:1;
-        /** evt_ovf_cnt_pls_ch1_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_ovf_cnt_pls_ch1_en:1;
-        /** evt_ovf_cnt_pls_ch2_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_ovf_cnt_pls_ch2_en:1;
-        /** evt_ovf_cnt_pls_ch3_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_ovf_cnt_pls_ch3_en:1;
-        /** evt_ovf_cnt_pls_ch4_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_ovf_cnt_pls_ch4_en:1;
-        /** evt_ovf_cnt_pls_ch5_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_ovf_cnt_pls_ch5_en:1;
-        uint32_t reserved_14:2;
-        /** evt_time_ovf_timer0_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time_ovf_timer0_en:1;
-        /** evt_time_ovf_timer1_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time_ovf_timer1_en:1;
-        /** evt_time_ovf_timer2_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time_ovf_timer2_en:1;
-        /** evt_time_ovf_timer3_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time_ovf_timer3_en:1;
-        /** evt_time0_cmp_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time0_cmp_en:1;
-        /** evt_time1_cmp_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time1_cmp_en:1;
-        /** evt_time2_cmp_en : R/W; bitpos: [22]; default: 0;
-         *  Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time2_cmp_en:1;
-        /** evt_time3_cmp_en : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_time3_cmp_en:1;
-        /** task_duty_scale_update_ch0_en : R/W; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_duty_scale_update_ch0_en:1;
-        /** task_duty_scale_update_ch1_en : R/W; bitpos: [25]; default: 0;
-         *  Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_duty_scale_update_ch1_en:1;
-        /** task_duty_scale_update_ch2_en : R/W; bitpos: [26]; default: 0;
-         *  Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_duty_scale_update_ch2_en:1;
-        /** task_duty_scale_update_ch3_en : R/W; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_duty_scale_update_ch3_en:1;
-        /** task_duty_scale_update_ch4_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_duty_scale_update_ch4_en:1;
-        /** task_duty_scale_update_ch5_en : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_duty_scale_update_ch5_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} ledc_evt_task_en0_reg_t;
-
-/** Type of evt_task_en1 register
- *  Ledc event task enable bit register1.
- */
-typedef union {
-    struct {
-        /** task_timer0_res_update_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer0_res_update_en:1;
-        /** task_timer1_res_update_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer1_res_update_en:1;
-        /** task_timer2_res_update_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer2_res_update_en:1;
-        /** task_timer3_res_update_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer3_res_update_en:1;
-        /** task_timer0_cap_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer0_cap_en:1;
-        /** task_timer1_cap_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer1_cap_en:1;
-        /** task_timer2_cap_en : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer2_cap_en:1;
-        /** task_timer3_cap_en : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer3_cap_en:1;
-        /** task_sig_out_dis_ch0_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_sig_out_dis_ch0_en:1;
-        /** task_sig_out_dis_ch1_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_sig_out_dis_ch1_en:1;
-        /** task_sig_out_dis_ch2_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_sig_out_dis_ch2_en:1;
-        /** task_sig_out_dis_ch3_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_sig_out_dis_ch3_en:1;
-        /** task_sig_out_dis_ch4_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_sig_out_dis_ch4_en:1;
-        /** task_sig_out_dis_ch5_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_sig_out_dis_ch5_en:1;
-        uint32_t reserved_14:2;
-        /** task_ovf_cnt_rst_ch0_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_ovf_cnt_rst_ch0_en:1;
-        /** task_ovf_cnt_rst_ch1_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_ovf_cnt_rst_ch1_en:1;
-        /** task_ovf_cnt_rst_ch2_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_ovf_cnt_rst_ch2_en:1;
-        /** task_ovf_cnt_rst_ch3_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_ovf_cnt_rst_ch3_en:1;
-        /** task_ovf_cnt_rst_ch4_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_ovf_cnt_rst_ch4_en:1;
-        /** task_ovf_cnt_rst_ch5_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_ovf_cnt_rst_ch5_en:1;
-        uint32_t reserved_22:2;
-        /** task_timer0_rst_en : R/W; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer0_rst_en:1;
-        /** task_timer1_rst_en : R/W; bitpos: [25]; default: 0;
-         *  Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer1_rst_en:1;
-        /** task_timer2_rst_en : R/W; bitpos: [26]; default: 0;
-         *  Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer2_rst_en:1;
-        /** task_timer3_rst_en : R/W; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer3_rst_en:1;
-        /** task_timer0_pause_resume_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer0_pause_resume_en:1;
-        /** task_timer1_pause_resume_en : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer1_pause_resume_en:1;
-        /** task_timer2_pause_resume_en : R/W; bitpos: [30]; default: 0;
-         *  Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer2_pause_resume_en:1;
-        /** task_timer3_pause_resume_en : R/W; bitpos: [31]; default: 0;
-         *  Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_timer3_pause_resume_en:1;
-    };
-    uint32_t val;
-} ledc_evt_task_en1_reg_t;
-
-/** Type of evt_task_en2 register
- *  Ledc event task enable bit register2.
- */
-typedef union {
-    struct {
-        /** task_gamma_restart_ch0_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_restart_ch0_en:1;
-        /** task_gamma_restart_ch1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_restart_ch1_en:1;
-        /** task_gamma_restart_ch2_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_restart_ch2_en:1;
-        /** task_gamma_restart_ch3_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_restart_ch3_en:1;
-        /** task_gamma_restart_ch4_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_restart_ch4_en:1;
-        /** task_gamma_restart_ch5_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_restart_ch5_en:1;
-        uint32_t reserved_6:2;
-        /** task_gamma_pause_ch0_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_pause_ch0_en:1;
-        /** task_gamma_pause_ch1_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_pause_ch1_en:1;
-        /** task_gamma_pause_ch2_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_pause_ch2_en:1;
-        /** task_gamma_pause_ch3_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_pause_ch3_en:1;
-        /** task_gamma_pause_ch4_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_pause_ch4_en:1;
-        /** task_gamma_pause_ch5_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_pause_ch5_en:1;
-        uint32_t reserved_14:2;
-        /** task_gamma_resume_ch0_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_resume_ch0_en:1;
-        /** task_gamma_resume_ch1_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_resume_ch1_en:1;
-        /** task_gamma_resume_ch2_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_resume_ch2_en:1;
-        /** task_gamma_resume_ch3_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_resume_ch3_en:1;
-        /** task_gamma_resume_ch4_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_resume_ch4_en:1;
-        /** task_gamma_resume_ch5_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_gamma_resume_ch5_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} ledc_evt_task_en2_reg_t;
-
-
-/** Group: timer */
-/** Type of timern_cmp register
- *  Ledc timern compare value register.
- */
-typedef union {
-    struct {
-        /** timern_cmp : R/W; bitpos: [19:0]; default: 0;
-         *  Configures the comparison value for LEDC timern.
-         */
-        uint32_t timern_cmp:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} ledc_timern_cmp_reg_t;
-
-/** Type of timern_cnt_cap register
- *  Ledc timern captured count value register.
- */
-typedef union {
-    struct {
-        /** timern_cnt_cap : RO; bitpos: [19:0]; default: 0;
-         *  Represents the captured LEDC timern count value.
-         */
-        uint32_t timern_cnt_cap:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} ledc_timern_cnt_cap_reg_t;
-
-
-/** Group: ram */
-/** Type of conf register
- *  LEDC global configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** gamma_ram_clk_en_ch0 : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock
-         *  gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the
-         *  clock gate for LEDC ch0 gamma ram
-         */
-        uint32_t gamma_ram_clk_en_ch0:1;
-        /** gamma_ram_clk_en_ch1 : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock
-         *  gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the
-         *  clock gate for LEDC ch1 gamma ram
-         */
-        uint32_t gamma_ram_clk_en_ch1:1;
-        /** gamma_ram_clk_en_ch2 : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock
-         *  gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the
-         *  clock gate for LEDC ch2 gamma ram
-         */
-        uint32_t gamma_ram_clk_en_ch2:1;
-        /** gamma_ram_clk_en_ch3 : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock
-         *  gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the
-         *  clock gate for LEDC ch3 gamma ram
-         */
-        uint32_t gamma_ram_clk_en_ch3:1;
-        /** gamma_ram_clk_en_ch4 : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock
-         *  gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the
-         *  clock gate for LEDC ch4 gamma ram
-         */
-        uint32_t gamma_ram_clk_en_ch4:1;
-        /** gamma_ram_clk_en_ch5 : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock
-         *  gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the
-         *  clock gate for LEDC ch5 gamma ram
-         */
-        uint32_t gamma_ram_clk_en_ch5:1;
-        uint32_t reserved_8:23;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
-         *  when application writes registers\\1: Force open the clock gate for register
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} ledc_conf_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** ledc_date : R/W; bitpos: [27:0]; default: 36716928;
-         *  Configures the version.
-         */
-        uint32_t ledc_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ledc_date_reg_t;
-
-typedef struct {
-    volatile ledc_chn_conf0_reg_t conf0;
-    volatile ledc_chn_hpoint_reg_t hpoint;
-    volatile ledc_chn_duty_reg_t duty;
-    volatile ledc_chn_conf1_reg_t conf1;
-    volatile ledc_chn_duty_r_reg_t duty_rd;
-} ledc_chn_reg_t;
-
-typedef struct {
-    volatile ledc_chn_reg_t channel[6];
-} ledc_ch_group_reg_t;
-
-typedef struct {
-    volatile ledc_timern_conf_reg_t conf;
-    volatile ledc_timern_value_reg_t value;
-} ledc_timerx_reg_t;
-
-typedef struct {
-    volatile ledc_timerx_reg_t timer[4];
-} ledc_timer_group_reg_t;
-
-typedef struct {
-    volatile ledc_chn_gamma_conf_reg_t gamma_conf[6];
-} ledc_ch_gamma_conf_group_reg_t;
-
-typedef struct {
-    volatile ledc_timern_cmp_reg_t cmp[4];
-} ledc_timer_cmp_group_reg_t;
-
-typedef struct {
-    volatile ledc_timern_cnt_cap_reg_t cnt_cap[4];
-} ledc_timer_cnt_cap_group_reg_t;
-
-typedef struct ledc_dev_t {
-    volatile ledc_ch_group_reg_t channel_group[1];
-    uint32_t reserved_078[10];
-    volatile ledc_timer_group_reg_t timer_group[1];
-    volatile ledc_int_raw_reg_t int_raw;
-    volatile ledc_int_st_reg_t int_st;
-    volatile ledc_int_ena_reg_t int_ena;
-    volatile ledc_int_clr_reg_t int_clr;
-    uint32_t reserved_0d0[12];
-    volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1];
-    uint32_t reserved_118[2];
-    volatile ledc_evt_task_en0_reg_t evt_task_en0;
-    volatile ledc_evt_task_en1_reg_t evt_task_en1;
-    volatile ledc_evt_task_en2_reg_t evt_task_en2;
-    uint32_t reserved_12c[5];
-    volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1];
-    volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1];
-    uint32_t reserved_160[4];
-    volatile ledc_conf_reg_t conf;
-    volatile ledc_date_reg_t date;
-} ledc_dev_t;
-
-extern ledc_dev_t LEDC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_reg.h
deleted file mode 100644
index 079aff0bd3..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_reg.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_ANA_BOD_MODE0_CNTL_REG register
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
-/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S  6
-/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_PD_RF_ENA    (BIT(7))
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_M  (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_S  7
-/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INTR_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_M  (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
-#define LP_ANA_BOD_MODE0_INTR_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_S  8
-/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_RESET_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_M  (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
-#define LP_ANA_BOD_MODE0_RESET_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_S  18
-/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_CNT_CLR    (BIT(28))
-#define LP_ANA_BOD_MODE0_CNT_CLR_M  (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
-#define LP_ANA_BOD_MODE0_CNT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CNT_CLR_S  28
-/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INTR_ENA    (BIT(29))
-#define LP_ANA_BOD_MODE0_INTR_ENA_M  (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
-#define LP_ANA_BOD_MODE0_INTR_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INTR_ENA_S  29
-/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_RESET_SEL    (BIT(30))
-#define LP_ANA_BOD_MODE0_RESET_SEL_M  (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
-#define LP_ANA_BOD_MODE0_RESET_SEL_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_SEL_S  30
-/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_RESET_ENA_M  (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
-#define LP_ANA_BOD_MODE0_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_ENA_S  31
-
-/** LP_ANA_BOD_MODE1_CNTL_REG register
- *  need_des
- */
-#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
-/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE1_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE1_RESET_ENA_M  (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
-#define LP_ANA_BOD_MODE1_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE1_RESET_ENA_S  31
-
-/** LP_ANA_CK_GLITCH_CNTL_REG register
- *  need_des
- */
-#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
-/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_CK_GLITCH_RESET_ENA    (BIT(31))
-#define LP_ANA_CK_GLITCH_RESET_ENA_M  (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
-#define LP_ANA_CK_GLITCH_RESET_ENA_V  0x00000001U
-#define LP_ANA_CK_GLITCH_RESET_ENA_S  31
-
-/** LP_ANA_FIB_ENABLE_REG register
- *  need_des
- */
-#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
-/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LP_ANA_ANA_FIB_ENA    0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_M  (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
-#define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_S  0
-
-/** LP_ANA_INT_RAW_REG register
- *  need_des
- */
-#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
-/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_RAW_M  (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_RAW_S  31
-
-/** LP_ANA_INT_ST_REG register
- *  need_des
- */
-#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
-/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ST_M  (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
-#define LP_ANA_BOD_MODE0_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ST_S  31
-
-/** LP_ANA_INT_ENA_REG register
- *  need_des
- */
-#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
-/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ENA_M  (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ENA_S  31
-
-/** LP_ANA_INT_CLR_REG register
- *  need_des
- */
-#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
-/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_CLR_M  (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_CLR_S  31
-
-/** LP_ANA_LP_INT_RAW_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
-/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_M  (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_S  31
-
-/** LP_ANA_LP_INT_ST_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
-/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ST_M  (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ST_S  31
-
-/** LP_ANA_LP_INT_ENA_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
-/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_M  (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_S  31
-
-/** LP_ANA_LP_INT_CLR_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
-/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_M  (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_S  31
-
-/** LP_ANA_DATE_REG register
- *  need_des
- */
-#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
-/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 35660384;
- *  need_des
- */
-#define LP_ANA_LP_ANA_DATE    0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_M  (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
-#define LP_ANA_LP_ANA_DATE_V  0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_S  0
-/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_CLK_EN    (BIT(31))
-#define LP_ANA_CLK_EN_M  (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
-#define LP_ANA_CLK_EN_V  0x00000001U
-#define LP_ANA_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_struct.h
deleted file mode 100644
index a9f5e7dae9..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_analog_peri_struct.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of bod_mode0_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:6;
-        /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_close_flash_ena:1;
-        /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_pd_rf_ena:1;
-        /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
-         *  need_des
-         */
-        uint32_t bod_mode0_intr_wait:10;
-        /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
-         *  need_des
-         */
-        uint32_t bod_mode0_reset_wait:10;
-        /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_cnt_clr:1;
-        /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_intr_ena:1;
-        /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_reset_sel:1;
-        /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_reset_ena:1;
-    };
-    uint32_t val;
-} lp_ana_bod_mode0_cntl_reg_t;
-
-/** Type of bod_mode1_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode1_reset_ena:1;
-    };
-    uint32_t val;
-} lp_ana_bod_mode1_cntl_reg_t;
-
-/** Type of ck_glitch_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t ck_glitch_reset_ena:1;
-    };
-    uint32_t val;
-} lp_ana_ck_glitch_cntl_reg_t;
-
-/** Type of fib_enable register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t ana_fib_ena:32;
-    };
-    uint32_t val;
-} lp_ana_fib_enable_reg_t;
-
-/** Type of int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_int_raw:1;
-    };
-    uint32_t val;
-} lp_ana_int_raw_reg_t;
-
-/** Type of int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_int_st:1;
-    };
-    uint32_t val;
-} lp_ana_int_st_reg_t;
-
-/** Type of int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_int_ena:1;
-    };
-    uint32_t val;
-} lp_ana_int_ena_reg_t;
-
-/** Type of int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_int_clr:1;
-    };
-    uint32_t val;
-} lp_ana_int_clr_reg_t;
-
-/** Type of lp_int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_lp_int_raw:1;
-    };
-    uint32_t val;
-} lp_ana_lp_int_raw_reg_t;
-
-/** Type of lp_int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_lp_int_st:1;
-    };
-    uint32_t val;
-} lp_ana_lp_int_st_reg_t;
-
-/** Type of lp_int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_lp_int_ena:1;
-    };
-    uint32_t val;
-} lp_ana_lp_int_ena_reg_t;
-
-/** Type of lp_int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t bod_mode0_lp_int_clr:1;
-    };
-    uint32_t val;
-} lp_ana_lp_int_clr_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_ana_date : R/W; bitpos: [30:0]; default: 35660384;
-         *  need_des
-         */
-        uint32_t lp_ana_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_ana_date_reg_t;
-
-
-typedef struct lp_ana_dev_t {
-    volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
-    volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
-    volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
-    volatile lp_ana_fib_enable_reg_t fib_enable;
-    volatile lp_ana_int_raw_reg_t int_raw;
-    volatile lp_ana_int_st_reg_t int_st;
-    volatile lp_ana_int_ena_reg_t int_ena;
-    volatile lp_ana_int_clr_reg_t int_clr;
-    volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
-    volatile lp_ana_lp_int_st_reg_t lp_int_st;
-    volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
-    volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
-    uint32_t reserved_030[243];
-    volatile lp_ana_date_reg_t date;
-} lp_ana_dev_t;
-
-extern lp_ana_dev_t LP_ANA_PERI;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_aon_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_aon_reg.h
deleted file mode 100644
index 39b2fb9674..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_aon_reg.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_AON_STORE0_REG register
- *  need_des
- */
-#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
-/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE0    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE0_M  (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S)
-#define LP_AON_LP_AON_STORE0_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE0_S  0
-
-/** LP_AON_STORE1_REG register
- *  need_des
- */
-#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
-/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE1    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE1_M  (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S)
-#define LP_AON_LP_AON_STORE1_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE1_S  0
-
-/** LP_AON_STORE2_REG register
- *  need_des
- */
-#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
-/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE2    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE2_M  (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S)
-#define LP_AON_LP_AON_STORE2_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE2_S  0
-
-/** LP_AON_STORE3_REG register
- *  need_des
- */
-#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
-/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE3    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE3_M  (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S)
-#define LP_AON_LP_AON_STORE3_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE3_S  0
-
-/** LP_AON_STORE4_REG register
- *  need_des
- */
-#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
-/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE4    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE4_M  (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S)
-#define LP_AON_LP_AON_STORE4_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE4_S  0
-
-/** LP_AON_STORE5_REG register
- *  need_des
- */
-#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
-/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE5    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE5_M  (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S)
-#define LP_AON_LP_AON_STORE5_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE5_S  0
-
-/** LP_AON_STORE6_REG register
- *  need_des
- */
-#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
-/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE6    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE6_M  (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S)
-#define LP_AON_LP_AON_STORE6_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE6_S  0
-
-/** LP_AON_STORE7_REG register
- *  need_des
- */
-#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
-/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE7    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE7_M  (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S)
-#define LP_AON_LP_AON_STORE7_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE7_S  0
-
-/** LP_AON_STORE8_REG register
- *  need_des
- */
-#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
-/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE8    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE8_M  (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S)
-#define LP_AON_LP_AON_STORE8_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE8_S  0
-
-/** LP_AON_STORE9_REG register
- *  need_des
- */
-#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
-/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_LP_AON_STORE9    0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE9_M  (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S)
-#define LP_AON_LP_AON_STORE9_V  0xFFFFFFFFU
-#define LP_AON_LP_AON_STORE9_S  0
-
-/** LP_AON_GPIO_MUX_REG register
- *  need_des
- */
-#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
-/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define LP_AON_GPIO_MUX_SEL    0x000000FFU
-#define LP_AON_GPIO_MUX_SEL_M  (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
-#define LP_AON_GPIO_MUX_SEL_V  0x000000FFU
-#define LP_AON_GPIO_MUX_SEL_S  0
-
-/** LP_AON_GPIO_HOLD0_REG register
- *  need_des
- */
-#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
-/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_GPIO_HOLD0    0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD0_M  (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
-#define LP_AON_GPIO_HOLD0_V  0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD0_S  0
-
-/** LP_AON_GPIO_HOLD1_REG register
- *  need_des
- */
-#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30)
-/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_AON_GPIO_HOLD1    0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD1_M  (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S)
-#define LP_AON_GPIO_HOLD1_V  0xFFFFFFFFU
-#define LP_AON_GPIO_HOLD1_S  0
-
-/** LP_AON_SYS_CFG_REG register
- *  need_des
- */
-#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
-/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AON_FORCE_DOWNLOAD_BOOT    (BIT(30))
-#define LP_AON_FORCE_DOWNLOAD_BOOT_M  (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S)
-#define LP_AON_FORCE_DOWNLOAD_BOOT_V  0x00000001U
-#define LP_AON_FORCE_DOWNLOAD_BOOT_S  30
-/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_HPSYS_SW_RESET    (BIT(31))
-#define LP_AON_HPSYS_SW_RESET_M  (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
-#define LP_AON_HPSYS_SW_RESET_V  0x00000001U
-#define LP_AON_HPSYS_SW_RESET_S  31
-
-/** LP_AON_CPUCORE0_CFG_REG register
- *  need_des
- */
-#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
-/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_SW_STALL    0x000000FFU
-#define LP_AON_CPU_CORE0_SW_STALL_M  (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
-#define LP_AON_CPU_CORE0_SW_STALL_V  0x000000FFU
-#define LP_AON_CPU_CORE0_SW_STALL_S  0
-/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_SW_RESET    (BIT(28))
-#define LP_AON_CPU_CORE0_SW_RESET_M  (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
-#define LP_AON_CPU_CORE0_SW_RESET_V  0x00000001U
-#define LP_AON_CPU_CORE0_SW_RESET_S  28
-/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET    (BIT(29))
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M  (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S)
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V  0x00000001U
-#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S  29
-/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL    (BIT(30))
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M  (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S)
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V  0x00000001U
-#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S  30
-/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_CPU_CORE0_DRESET_MASK    (BIT(31))
-#define LP_AON_CPU_CORE0_DRESET_MASK_M  (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S)
-#define LP_AON_CPU_CORE0_DRESET_MASK_V  0x00000001U
-#define LP_AON_CPU_CORE0_DRESET_MASK_S  31
-
-/** LP_AON_IO_MUX_REG register
- *  need_des
- */
-#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
-/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_IO_MUX_RESET_DISABLE    (BIT(31))
-#define LP_AON_IO_MUX_RESET_DISABLE_M  (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
-#define LP_AON_IO_MUX_RESET_DISABLE_V  0x00000001U
-#define LP_AON_IO_MUX_RESET_DISABLE_S  31
-
-/** LP_AON_EXT_WAKEUP_CNTL_REG register
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
-/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_STATUS    0x000000FFU
-#define LP_AON_EXT_WAKEUP_STATUS_M  (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
-#define LP_AON_EXT_WAKEUP_STATUS_V  0x000000FFU
-#define LP_AON_EXT_WAKEUP_STATUS_S  0
-/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_STATUS_CLR    (BIT(14))
-#define LP_AON_EXT_WAKEUP_STATUS_CLR_M  (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
-#define LP_AON_EXT_WAKEUP_STATUS_CLR_V  0x00000001U
-#define LP_AON_EXT_WAKEUP_STATUS_CLR_S  14
-/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_SEL    0x000000FFU
-#define LP_AON_EXT_WAKEUP_SEL_M  (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
-#define LP_AON_EXT_WAKEUP_SEL_V  0x000000FFU
-#define LP_AON_EXT_WAKEUP_SEL_S  15
-/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_LV    0x000000FFU
-#define LP_AON_EXT_WAKEUP_LV_M  (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
-#define LP_AON_EXT_WAKEUP_LV_V  0x000000FFU
-#define LP_AON_EXT_WAKEUP_LV_S  23
-/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_EXT_WAKEUP_FILTER    (BIT(31))
-#define LP_AON_EXT_WAKEUP_FILTER_M  (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
-#define LP_AON_EXT_WAKEUP_FILTER_V  0x00000001U
-#define LP_AON_EXT_WAKEUP_FILTER_S  31
-
-/** LP_AON_USB_REG register
- *  need_des
- */
-#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44)
-/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_USB_RESET_DISABLE    (BIT(31))
-#define LP_AON_USB_RESET_DISABLE_M  (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
-#define LP_AON_USB_RESET_DISABLE_V  0x00000001U
-#define LP_AON_USB_RESET_DISABLE_S  31
-
-/** LP_AON_LPBUS_REG register
- *  need_des
- */
-#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48)
-/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE    (BIT(28))
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M  (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S  28
-/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS    (BIT(29))
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M  (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S  29
-/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE    (BIT(30))
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M  (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S  30
-/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define LP_AON_FAST_MEM_MUX_SEL    (BIT(31))
-#define LP_AON_FAST_MEM_MUX_SEL_M  (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
-#define LP_AON_FAST_MEM_MUX_SEL_V  0x00000001U
-#define LP_AON_FAST_MEM_MUX_SEL_S  31
-
-/** LP_AON_SDIO_ACTIVE_REG register
- *  need_des
- */
-#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c)
-/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10;
- *  need_des
- */
-#define LP_AON_SDIO_ACT_DNUM    0x000003FFU
-#define LP_AON_SDIO_ACT_DNUM_M  (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S)
-#define LP_AON_SDIO_ACT_DNUM_V  0x000003FFU
-#define LP_AON_SDIO_ACT_DNUM_S  22
-
-/** LP_AON_LPCORE_REG register
- *  need_des
- */
-#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50)
-/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR    (BIT(0))
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S)
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S  0
-/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG    (BIT(1))
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M  (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S)
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V  0x00000001U
-#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S  1
-/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_LPCORE_DISABLE    (BIT(31))
-#define LP_AON_LPCORE_DISABLE_M  (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S)
-#define LP_AON_LPCORE_DISABLE_V  0x00000001U
-#define LP_AON_LPCORE_DISABLE_S  31
-
-/** LP_AON_SAR_CCT_REG register
- *  need_des
- */
-#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54)
-/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0;
- *  need_des
- */
-#define LP_AON_SAR2_PWDET_CCT    0x00000007U
-#define LP_AON_SAR2_PWDET_CCT_M  (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S)
-#define LP_AON_SAR2_PWDET_CCT_V  0x00000007U
-#define LP_AON_SAR2_PWDET_CCT_S  29
-
-/** LP_AON_MODEM_BUS_REG register
- *  need_des
- */
-#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58)
-/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_MODEM_SYNC_BRIDGE_EN    (BIT(31))
-#define LP_AON_MODEM_SYNC_BRIDGE_EN_M  (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S)
-#define LP_AON_MODEM_SYNC_BRIDGE_EN_V  0x00000001U
-#define LP_AON_MODEM_SYNC_BRIDGE_EN_S  31
-
-/** LP_AON_AUDIO_CODEC_CTRL_REG register
- *  need_des
- */
-#define LP_AON_AUDIO_CODEC_CTRL_REG (DR_REG_LP_AON_BASE + 0x5c)
-/** LP_AON_RTC_XPD_SDADC : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_AON_RTC_XPD_SDADC    (BIT(0))
-#define LP_AON_RTC_XPD_SDADC_M  (LP_AON_RTC_XPD_SDADC_V << LP_AON_RTC_XPD_SDADC_S)
-#define LP_AON_RTC_XPD_SDADC_V  0x00000001U
-#define LP_AON_RTC_XPD_SDADC_S  0
-/** LP_AON_RTC_EN_CLK_AUDIO_DAC : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_AON_RTC_EN_CLK_AUDIO_DAC    (BIT(1))
-#define LP_AON_RTC_EN_CLK_AUDIO_DAC_M  (LP_AON_RTC_EN_CLK_AUDIO_DAC_V << LP_AON_RTC_EN_CLK_AUDIO_DAC_S)
-#define LP_AON_RTC_EN_CLK_AUDIO_DAC_V  0x00000001U
-#define LP_AON_RTC_EN_CLK_AUDIO_DAC_S  1
-/** LP_AON_RTC_XPD_BIAS_AUDIO_DAC : R/W; bitpos: [2]; default: 0;
- *  need_des
- */
-#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC    (BIT(2))
-#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_M  (LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V << LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S)
-#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_V  0x00000001U
-#define LP_AON_RTC_XPD_BIAS_AUDIO_DAC_S  2
-/** LP_AON_RTC_XPD_PLLA : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define LP_AON_RTC_XPD_PLLA    (BIT(3))
-#define LP_AON_RTC_XPD_PLLA_M  (LP_AON_RTC_XPD_PLLA_V << LP_AON_RTC_XPD_PLLA_S)
-#define LP_AON_RTC_XPD_PLLA_V  0x00000001U
-#define LP_AON_RTC_XPD_PLLA_S  3
-
-/** LP_AON_SPRAM_CTRL_REG register
- *  need_des
- */
-#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60)
-/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  need_des
- */
-#define LP_AON_SPRAM_MEM_AUX_CTRL    0xFFFFFFFFU
-#define LP_AON_SPRAM_MEM_AUX_CTRL_M  (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S)
-#define LP_AON_SPRAM_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define LP_AON_SPRAM_MEM_AUX_CTRL_S  0
-
-/** LP_AON_SPRF_CTRL_REG register
- *  need_des
- */
-#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64)
-/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  need_des
- */
-#define LP_AON_SPRF_MEM_AUX_CTRL    0xFFFFFFFFU
-#define LP_AON_SPRF_MEM_AUX_CTRL_M  (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S)
-#define LP_AON_SPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define LP_AON_SPRF_MEM_AUX_CTRL_S  0
-
-/** LP_AON_DATE_REG register
- *  need_des
- */
-#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
-/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36720768;
- *  need_des
- */
-#define LP_AON_DATE    0x7FFFFFFFU
-#define LP_AON_DATE_M  (LP_AON_DATE_V << LP_AON_DATE_S)
-#define LP_AON_DATE_V  0x7FFFFFFFU
-#define LP_AON_DATE_S  0
-/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_AON_CLK_EN    (BIT(31))
-#define LP_AON_CLK_EN_M  (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
-#define LP_AON_CLK_EN_V  0x00000001U
-#define LP_AON_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_aon_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_aon_struct.h
deleted file mode 100644
index 4e3ce38a48..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_aon_struct.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of store n register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_aon_store : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_aon_store:32;
-    };
-    uint32_t val;
-} lp_aon_store_reg_t;
-
-/** Type of gpio_mux register
- *  need_des
- */
-typedef union {
-    struct {
-        /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t gpio_mux_sel:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_aon_gpio_mux_reg_t;
-
-/** Type of gpio_hold0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t gpio_hold0:32;
-    };
-    uint32_t val;
-} lp_aon_gpio_hold0_reg_t;
-
-/** Type of gpio_hold1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t gpio_hold1:32;
-    };
-    uint32_t val;
-} lp_aon_gpio_hold1_reg_t;
-
-/** Type of sys_cfg register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** force_download_boot : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t force_download_boot:1;
-        /** hpsys_sw_reset : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hpsys_sw_reset:1;
-    };
-    uint32_t val;
-} lp_aon_sys_cfg_reg_t;
-
-/** Type of cpucore0_cfg register
- *  need_des
- */
-typedef union {
-    struct {
-        /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_sw_stall:8;
-        uint32_t reserved_8:20;
-        /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_sw_reset:1;
-        /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_ocd_halt_on_reset:1;
-        /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1;
-         *  need_des
-         */
-        uint32_t cpu_core0_stat_vector_sel:1;
-        /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_core0_dreset_mask:1;
-    };
-    uint32_t val;
-} lp_aon_cpucore0_cfg_reg_t;
-
-/** Type of io_mux register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t io_mux_reset_disable:1;
-    };
-    uint32_t val;
-} lp_aon_io_mux_reg_t;
-
-/** Type of ext_wakeup_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_status:8;
-        uint32_t reserved_8:6;
-        /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_status_clr:1;
-        /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_sel:8;
-        /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_lv:8;
-        /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t ext_wakeup_filter:1;
-    };
-    uint32_t val;
-} lp_aon_ext_wakeup_cntl_reg_t;
-
-/** Type of usb register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** usb_reset_disable : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t usb_reset_disable:1;
-    };
-    uint32_t val;
-} lp_aon_usb_reg_t;
-
-/** Type of lpbus register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_fsm_idle:1;
-        /** fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_sel_status:1;
-        /** fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_sel_update:1;
-        /** fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_mem_mux_sel:1;
-    };
-    uint32_t val;
-} lp_aon_lpbus_reg_t;
-
-/** Type of sdio_active register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10;
-         *  need_des
-         */
-        uint32_t sdio_act_dnum:10;
-    };
-    uint32_t val;
-} lp_aon_sdio_active_reg_t;
-
-/** Type of lpcore register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_etm_wakeup_flag_clr:1;
-        /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_etm_wakeup_flag:1;
-        uint32_t reserved_2:29;
-        /** lpcore_disable : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_disable:1;
-    };
-    uint32_t val;
-} lp_aon_lpcore_reg_t;
-
-/** Type of sar_cct register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:29;
-        /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0;
-         *  need_des
-         */
-        uint32_t sar2_pwdet_cct:3;
-    };
-    uint32_t val;
-} lp_aon_sar_cct_reg_t;
-
-/** Type of modem_bus register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_sync_bridge_en:1;
-    };
-    uint32_t val;
-} lp_aon_modem_bus_reg_t;
-
-/** Type of audio_codec_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** rtc_xpd_sdadc : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t rtc_xpd_sdadc:1;
-        /** rtc_en_clk_audio_dac : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t rtc_en_clk_audio_dac:1;
-        /** rtc_xpd_bias_audio_dac : R/W; bitpos: [2]; default: 0;
-         *  need_des
-         */
-        uint32_t rtc_xpd_bias_audio_dac:1;
-        /** rtc_xpd_plla : R/W; bitpos: [3]; default: 1;
-         *  need_des
-         */
-        uint32_t rtc_xpd_plla:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_aon_audio_codec_ctrl_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [30:0]; default: 36720768;
-         *  need_des
-         */
-        uint32_t date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_aon_date_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of spram_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
-         *  need_des
-         */
-        uint32_t spram_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} lp_aon_spram_ctrl_reg_t;
-
-/** Type of sprf_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
-         *  need_des
-         */
-        uint32_t sprf_mem_aux_ctrl:32;
-    };
-    uint32_t val;
-} lp_aon_sprf_ctrl_reg_t;
-
-
-typedef struct lp_aon_dev_t {
-    volatile lp_aon_store_reg_t store[10];
-    volatile lp_aon_gpio_mux_reg_t gpio_mux;
-    volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
-    volatile lp_aon_gpio_hold1_reg_t gpio_hold1;
-    volatile lp_aon_sys_cfg_reg_t sys_cfg;
-    volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg;
-    volatile lp_aon_io_mux_reg_t io_mux;
-    volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
-    volatile lp_aon_usb_reg_t usb;
-    volatile lp_aon_lpbus_reg_t lpbus;
-    volatile lp_aon_sdio_active_reg_t sdio_active;
-    volatile lp_aon_lpcore_reg_t lpcore;
-    volatile lp_aon_sar_cct_reg_t sar_cct;
-    volatile lp_aon_modem_bus_reg_t modem_bus;
-    volatile lp_aon_audio_codec_ctrl_reg_t audio_codec_ctrl;
-    volatile lp_aon_spram_ctrl_reg_t spram_ctrl;
-    volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl;
-    uint32_t reserved_068[229];
-    volatile lp_aon_date_reg_t date;
-} lp_aon_dev_t;
-
-extern lp_aon_dev_t LP_AON;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_apm0_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_apm0_reg.h
deleted file mode 100644
index f2228c5ab3..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_apm0_reg.h
+++ /dev/null
@@ -1,534 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_APM0_REGION_FILTER_EN_REG register
- *  Region filter enable register
- */
-#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0)
-/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
- *  Region filter enable
- */
-#define LP_APM0_REGION_FILTER_EN    0x0000000FU
-#define LP_APM0_REGION_FILTER_EN_M  (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S)
-#define LP_APM0_REGION_FILTER_EN_V  0x0000000FU
-#define LP_APM0_REGION_FILTER_EN_S  0
-
-/** LP_APM0_REGION0_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4)
-/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region0
- */
-#define LP_APM0_REGION0_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_START_M  (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S)
-#define LP_APM0_REGION0_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_START_S  0
-
-/** LP_APM0_REGION0_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8)
-/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region0
- */
-#define LP_APM0_REGION0_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_END_M  (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S)
-#define LP_APM0_REGION0_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION0_ADDR_END_S  0
-
-/** LP_APM0_REGION0_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc)
-/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION0_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION0_R0_PMS_X_M  (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S)
-#define LP_APM0_REGION0_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION0_R0_PMS_X_S  0
-/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION0_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION0_R0_PMS_W_M  (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S)
-#define LP_APM0_REGION0_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION0_R0_PMS_W_S  1
-/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION0_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION0_R0_PMS_R_M  (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S)
-#define LP_APM0_REGION0_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION0_R0_PMS_R_S  2
-/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION0_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION0_R1_PMS_X_M  (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S)
-#define LP_APM0_REGION0_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION0_R1_PMS_X_S  4
-/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION0_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION0_R1_PMS_W_M  (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S)
-#define LP_APM0_REGION0_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION0_R1_PMS_W_S  5
-/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION0_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION0_R1_PMS_R_M  (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S)
-#define LP_APM0_REGION0_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION0_R1_PMS_R_S  6
-/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION0_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION0_R2_PMS_X_M  (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S)
-#define LP_APM0_REGION0_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION0_R2_PMS_X_S  8
-/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION0_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION0_R2_PMS_W_M  (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S)
-#define LP_APM0_REGION0_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION0_R2_PMS_W_S  9
-/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION0_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION0_R2_PMS_R_M  (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S)
-#define LP_APM0_REGION0_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION0_R2_PMS_R_S  10
-/** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define LP_APM0_REGION0_LOCK    (BIT(11))
-#define LP_APM0_REGION0_LOCK_M  (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S)
-#define LP_APM0_REGION0_LOCK_V  0x00000001U
-#define LP_APM0_REGION0_LOCK_S  11
-
-/** LP_APM0_REGION1_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10)
-/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region1
- */
-#define LP_APM0_REGION1_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_START_M  (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S)
-#define LP_APM0_REGION1_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_START_S  0
-
-/** LP_APM0_REGION1_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14)
-/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region1
- */
-#define LP_APM0_REGION1_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_END_M  (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S)
-#define LP_APM0_REGION1_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION1_ADDR_END_S  0
-
-/** LP_APM0_REGION1_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18)
-/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION1_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION1_R0_PMS_X_M  (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S)
-#define LP_APM0_REGION1_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION1_R0_PMS_X_S  0
-/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION1_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION1_R0_PMS_W_M  (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S)
-#define LP_APM0_REGION1_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION1_R0_PMS_W_S  1
-/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION1_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION1_R0_PMS_R_M  (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S)
-#define LP_APM0_REGION1_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION1_R0_PMS_R_S  2
-/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION1_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION1_R1_PMS_X_M  (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S)
-#define LP_APM0_REGION1_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION1_R1_PMS_X_S  4
-/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION1_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION1_R1_PMS_W_M  (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S)
-#define LP_APM0_REGION1_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION1_R1_PMS_W_S  5
-/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION1_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION1_R1_PMS_R_M  (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S)
-#define LP_APM0_REGION1_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION1_R1_PMS_R_S  6
-/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION1_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION1_R2_PMS_X_M  (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S)
-#define LP_APM0_REGION1_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION1_R2_PMS_X_S  8
-/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION1_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION1_R2_PMS_W_M  (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S)
-#define LP_APM0_REGION1_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION1_R2_PMS_W_S  9
-/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION1_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION1_R2_PMS_R_M  (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S)
-#define LP_APM0_REGION1_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION1_R2_PMS_R_S  10
-/** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region1 configuration
- */
-#define LP_APM0_REGION1_LOCK    (BIT(11))
-#define LP_APM0_REGION1_LOCK_M  (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S)
-#define LP_APM0_REGION1_LOCK_V  0x00000001U
-#define LP_APM0_REGION1_LOCK_S  11
-
-/** LP_APM0_REGION2_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c)
-/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region2
- */
-#define LP_APM0_REGION2_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_START_M  (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S)
-#define LP_APM0_REGION2_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_START_S  0
-
-/** LP_APM0_REGION2_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20)
-/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region2
- */
-#define LP_APM0_REGION2_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_END_M  (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S)
-#define LP_APM0_REGION2_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION2_ADDR_END_S  0
-
-/** LP_APM0_REGION2_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24)
-/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION2_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION2_R0_PMS_X_M  (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S)
-#define LP_APM0_REGION2_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION2_R0_PMS_X_S  0
-/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION2_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION2_R0_PMS_W_M  (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S)
-#define LP_APM0_REGION2_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION2_R0_PMS_W_S  1
-/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION2_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION2_R0_PMS_R_M  (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S)
-#define LP_APM0_REGION2_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION2_R0_PMS_R_S  2
-/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION2_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION2_R1_PMS_X_M  (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S)
-#define LP_APM0_REGION2_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION2_R1_PMS_X_S  4
-/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION2_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION2_R1_PMS_W_M  (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S)
-#define LP_APM0_REGION2_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION2_R1_PMS_W_S  5
-/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION2_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION2_R1_PMS_R_M  (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S)
-#define LP_APM0_REGION2_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION2_R1_PMS_R_S  6
-/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION2_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION2_R2_PMS_X_M  (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S)
-#define LP_APM0_REGION2_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION2_R2_PMS_X_S  8
-/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION2_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION2_R2_PMS_W_M  (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S)
-#define LP_APM0_REGION2_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION2_R2_PMS_W_S  9
-/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION2_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION2_R2_PMS_R_M  (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S)
-#define LP_APM0_REGION2_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION2_R2_PMS_R_S  10
-/** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region2 configuration
- */
-#define LP_APM0_REGION2_LOCK    (BIT(11))
-#define LP_APM0_REGION2_LOCK_M  (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S)
-#define LP_APM0_REGION2_LOCK_V  0x00000001U
-#define LP_APM0_REGION2_LOCK_S  11
-
-/** LP_APM0_REGION3_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28)
-/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region3
- */
-#define LP_APM0_REGION3_ADDR_START    0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_START_M  (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S)
-#define LP_APM0_REGION3_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_START_S  0
-
-/** LP_APM0_REGION3_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c)
-/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region3
- */
-#define LP_APM0_REGION3_ADDR_END    0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_END_M  (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S)
-#define LP_APM0_REGION3_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM0_REGION3_ADDR_END_S  0
-
-/** LP_APM0_REGION3_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30)
-/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM0_REGION3_R0_PMS_X    (BIT(0))
-#define LP_APM0_REGION3_R0_PMS_X_M  (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S)
-#define LP_APM0_REGION3_R0_PMS_X_V  0x00000001U
-#define LP_APM0_REGION3_R0_PMS_X_S  0
-/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM0_REGION3_R0_PMS_W    (BIT(1))
-#define LP_APM0_REGION3_R0_PMS_W_M  (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S)
-#define LP_APM0_REGION3_R0_PMS_W_V  0x00000001U
-#define LP_APM0_REGION3_R0_PMS_W_S  1
-/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM0_REGION3_R0_PMS_R    (BIT(2))
-#define LP_APM0_REGION3_R0_PMS_R_M  (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S)
-#define LP_APM0_REGION3_R0_PMS_R_V  0x00000001U
-#define LP_APM0_REGION3_R0_PMS_R_S  2
-/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM0_REGION3_R1_PMS_X    (BIT(4))
-#define LP_APM0_REGION3_R1_PMS_X_M  (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S)
-#define LP_APM0_REGION3_R1_PMS_X_V  0x00000001U
-#define LP_APM0_REGION3_R1_PMS_X_S  4
-/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM0_REGION3_R1_PMS_W    (BIT(5))
-#define LP_APM0_REGION3_R1_PMS_W_M  (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S)
-#define LP_APM0_REGION3_R1_PMS_W_V  0x00000001U
-#define LP_APM0_REGION3_R1_PMS_W_S  5
-/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM0_REGION3_R1_PMS_R    (BIT(6))
-#define LP_APM0_REGION3_R1_PMS_R_M  (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S)
-#define LP_APM0_REGION3_R1_PMS_R_V  0x00000001U
-#define LP_APM0_REGION3_R1_PMS_R_S  6
-/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM0_REGION3_R2_PMS_X    (BIT(8))
-#define LP_APM0_REGION3_R2_PMS_X_M  (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S)
-#define LP_APM0_REGION3_R2_PMS_X_V  0x00000001U
-#define LP_APM0_REGION3_R2_PMS_X_S  8
-/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM0_REGION3_R2_PMS_W    (BIT(9))
-#define LP_APM0_REGION3_R2_PMS_W_M  (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S)
-#define LP_APM0_REGION3_R2_PMS_W_V  0x00000001U
-#define LP_APM0_REGION3_R2_PMS_W_S  9
-/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM0_REGION3_R2_PMS_R    (BIT(10))
-#define LP_APM0_REGION3_R2_PMS_R_M  (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S)
-#define LP_APM0_REGION3_R2_PMS_R_V  0x00000001U
-#define LP_APM0_REGION3_R2_PMS_R_S  10
-/** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region3 configuration
- */
-#define LP_APM0_REGION3_LOCK    (BIT(11))
-#define LP_APM0_REGION3_LOCK_M  (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S)
-#define LP_APM0_REGION3_LOCK_V  0x00000001U
-#define LP_APM0_REGION3_LOCK_S  11
-
-/** LP_APM0_FUNC_CTRL_REG register
- *  PMS function control register
- */
-#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4)
-/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
- *  PMS M0 function enable
- */
-#define LP_APM0_M0_PMS_FUNC_EN    (BIT(0))
-#define LP_APM0_M0_PMS_FUNC_EN_M  (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S)
-#define LP_APM0_M0_PMS_FUNC_EN_V  0x00000001U
-#define LP_APM0_M0_PMS_FUNC_EN_S  0
-
-/** LP_APM0_M0_STATUS_REG register
- *  M0 status register
- */
-#define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8)
-/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define LP_APM0_M0_EXCEPTION_STATUS    0x00000003U
-#define LP_APM0_M0_EXCEPTION_STATUS_M  (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S)
-#define LP_APM0_M0_EXCEPTION_STATUS_V  0x00000003U
-#define LP_APM0_M0_EXCEPTION_STATUS_S  0
-
-/** LP_APM0_M0_STATUS_CLR_REG register
- *  M0 status clear register
- */
-#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc)
-/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define LP_APM0_M0_REGION_STATUS_CLR    (BIT(0))
-#define LP_APM0_M0_REGION_STATUS_CLR_M  (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S)
-#define LP_APM0_M0_REGION_STATUS_CLR_V  0x00000001U
-#define LP_APM0_M0_REGION_STATUS_CLR_S  0
-
-/** LP_APM0_M0_EXCEPTION_INFO0_REG register
- *  M0 exception_info0 register
- */
-#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0)
-/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
- *  Exception region
- */
-#define LP_APM0_M0_EXCEPTION_REGION    0x0000000FU
-#define LP_APM0_M0_EXCEPTION_REGION_M  (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S)
-#define LP_APM0_M0_EXCEPTION_REGION_V  0x0000000FU
-#define LP_APM0_M0_EXCEPTION_REGION_S  0
-/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define LP_APM0_M0_EXCEPTION_MODE    0x00000003U
-#define LP_APM0_M0_EXCEPTION_MODE_M  (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S)
-#define LP_APM0_M0_EXCEPTION_MODE_V  0x00000003U
-#define LP_APM0_M0_EXCEPTION_MODE_S  16
-/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define LP_APM0_M0_EXCEPTION_ID    0x0000001FU
-#define LP_APM0_M0_EXCEPTION_ID_M  (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S)
-#define LP_APM0_M0_EXCEPTION_ID_V  0x0000001FU
-#define LP_APM0_M0_EXCEPTION_ID_S  18
-
-/** LP_APM0_M0_EXCEPTION_INFO1_REG register
- *  M0 exception_info1 register
- */
-#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4)
-/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define LP_APM0_M0_EXCEPTION_ADDR    0xFFFFFFFFU
-#define LP_APM0_M0_EXCEPTION_ADDR_M  (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S)
-#define LP_APM0_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define LP_APM0_M0_EXCEPTION_ADDR_S  0
-
-/** LP_APM0_INT_EN_REG register
- *  APM interrupt enable register
- */
-#define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8)
-/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
- *  APM M0 interrupt enable
- */
-#define LP_APM0_M0_APM_INT_EN    (BIT(0))
-#define LP_APM0_M0_APM_INT_EN_M  (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S)
-#define LP_APM0_M0_APM_INT_EN_V  0x00000001U
-#define LP_APM0_M0_APM_INT_EN_S  0
-
-/** LP_APM0_CLOCK_GATE_REG register
- *  clock gating register
- */
-#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc)
-/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define LP_APM0_CLK_EN    (BIT(0))
-#define LP_APM0_CLK_EN_M  (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S)
-#define LP_APM0_CLK_EN_V  0x00000001U
-#define LP_APM0_CLK_EN_S  0
-
-/** LP_APM0_DATE_REG register
- *  Version register
- */
-#define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc)
-/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664;
- *  reg_date
- */
-#define LP_APM0_DATE    0x0FFFFFFFU
-#define LP_APM0_DATE_M  (LP_APM0_DATE_V << LP_APM0_DATE_S)
-#define LP_APM0_DATE_V  0x0FFFFFFFU
-#define LP_APM0_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_apm0_struct.h
deleted file mode 100644
index 72fc8a3b6a..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_apm0_struct.h
+++ /dev/null
@@ -1,515 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Region filter enable register */
-/** Type of region_filter_en register
- *  Region filter enable register
- */
-typedef union {
-    struct {
-        /** region_filter_en : R/W; bitpos: [3:0]; default: 1;
-         *  Region filter enable
-         */
-        uint32_t region_filter_en:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_apm0_region_filter_en_reg_t;
-
-
-/** Group: Region address register */
-/** Type of region0_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region0
-         */
-        uint32_t region0_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region0_addr_start_reg_t;
-
-/** Type of region0_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region0
-         */
-        uint32_t region0_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region0_addr_end_reg_t;
-
-/** Type of region1_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region1
-         */
-        uint32_t region1_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region1_addr_start_reg_t;
-
-/** Type of region1_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region1
-         */
-        uint32_t region1_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region1_addr_end_reg_t;
-
-/** Type of region2_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region2
-         */
-        uint32_t region2_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region2_addr_start_reg_t;
-
-/** Type of region2_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region2
-         */
-        uint32_t region2_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region2_addr_end_reg_t;
-
-/** Type of region3_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region3
-         */
-        uint32_t region3_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm0_region3_addr_start_reg_t;
-
-/** Type of region3_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region3
-         */
-        uint32_t region3_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm0_region3_addr_end_reg_t;
-
-
-/** Group: Region access authority attribute register */
-/** Type of region0_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_x:1;
-        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_w:1;
-        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_x:1;
-        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_w:1;
-        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_x:1;
-        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_w:1;
-        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_r:1;
-        /** region0_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region0 configuration
-         */
-        uint32_t region0_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm0_region0_pms_attr_reg_t;
-
-/** Type of region1_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_x:1;
-        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_w:1;
-        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_x:1;
-        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_w:1;
-        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_x:1;
-        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_w:1;
-        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_r:1;
-        /** region1_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region1 configuration
-         */
-        uint32_t region1_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm0_region1_pms_attr_reg_t;
-
-/** Type of region2_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_x:1;
-        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_w:1;
-        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_x:1;
-        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_w:1;
-        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_x:1;
-        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_w:1;
-        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_r:1;
-        /** region2_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region2 configuration
-         */
-        uint32_t region2_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm0_region2_pms_attr_reg_t;
-
-/** Type of region3_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_x:1;
-        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_w:1;
-        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_x:1;
-        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_w:1;
-        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_x:1;
-        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_w:1;
-        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_r:1;
-        /** region3_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region3 configuration
-         */
-        uint32_t region3_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm0_region3_pms_attr_reg_t;
-
-
-/** Group: PMS function control register */
-/** Type of func_ctrl register
- *  PMS function control register
- */
-typedef union {
-    struct {
-        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
-         *  PMS M0 function enable
-         */
-        uint32_t m0_pms_func_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_func_ctrl_reg_t;
-
-
-/** Group: M0 status register */
-/** Type of m0_status register
- *  M0 status register
- */
-typedef union {
-    struct {
-        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m0_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm0_m0_status_reg_t;
-
-
-/** Group: M0 status clear register */
-/** Type of m0_status_clr register
- *  M0 status clear register
- */
-typedef union {
-    struct {
-        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m0_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_m0_status_clr_reg_t;
-
-
-/** Group: M0 exception_info0 register */
-/** Type of m0_exception_info0 register
- *  M0 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m0_exception_region : RO; bitpos: [3:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m0_exception_region:4;
-        uint32_t reserved_4:12;
-        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m0_exception_mode:2;
-        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m0_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_apm0_m0_exception_info0_reg_t;
-
-
-/** Group: M0 exception_info1 register */
-/** Type of m0_exception_info1 register
- *  M0 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m0_exception_addr:32;
-    };
-    uint32_t val;
-} lp_apm0_m0_exception_info1_reg_t;
-
-
-/** Group: APM interrupt enable register */
-/** Type of int_en register
- *  APM interrupt enable register
- */
-typedef union {
-    struct {
-        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
-         *  APM M0 interrupt enable
-         */
-        uint32_t m0_apm_int_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_int_en_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm0_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725664;
-         *  reg_date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_apm0_date_reg_t;
-
-
-typedef struct lp_apm0_dev_t {
-    volatile lp_apm0_region_filter_en_reg_t region_filter_en;
-    volatile lp_apm0_region0_addr_start_reg_t region0_addr_start;
-    volatile lp_apm0_region0_addr_end_reg_t region0_addr_end;
-    volatile lp_apm0_region0_pms_attr_reg_t region0_pms_attr;
-    volatile lp_apm0_region1_addr_start_reg_t region1_addr_start;
-    volatile lp_apm0_region1_addr_end_reg_t region1_addr_end;
-    volatile lp_apm0_region1_pms_attr_reg_t region1_pms_attr;
-    volatile lp_apm0_region2_addr_start_reg_t region2_addr_start;
-    volatile lp_apm0_region2_addr_end_reg_t region2_addr_end;
-    volatile lp_apm0_region2_pms_attr_reg_t region2_pms_attr;
-    volatile lp_apm0_region3_addr_start_reg_t region3_addr_start;
-    volatile lp_apm0_region3_addr_end_reg_t region3_addr_end;
-    volatile lp_apm0_region3_pms_attr_reg_t region3_pms_attr;
-    uint32_t reserved_034[36];
-    volatile lp_apm0_func_ctrl_reg_t func_ctrl;
-    volatile lp_apm0_m0_status_reg_t m0_status;
-    volatile lp_apm0_m0_status_clr_reg_t m0_status_clr;
-    volatile lp_apm0_m0_exception_info0_reg_t m0_exception_info0;
-    volatile lp_apm0_m0_exception_info1_reg_t m0_exception_info1;
-    volatile lp_apm0_int_en_reg_t int_en;
-    volatile lp_apm0_clock_gate_reg_t clock_gate;
-    uint32_t reserved_0e0[455];
-    volatile lp_apm0_date_reg_t date;
-} lp_apm0_dev_t;
-
-extern lp_apm0_dev_t LP_APM0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_apm_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_apm_reg.h
deleted file mode 100644
index 17b6ef43a6..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_apm_reg.h
+++ /dev/null
@@ -1,610 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_APM_REGION_FILTER_EN_REG register
- *  Region filter enable register
- */
-#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0)
-/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1;
- *  Region filter enable
- */
-#define LP_APM_REGION_FILTER_EN    0x0000000FU
-#define LP_APM_REGION_FILTER_EN_M  (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S)
-#define LP_APM_REGION_FILTER_EN_V  0x0000000FU
-#define LP_APM_REGION_FILTER_EN_S  0
-
-/** LP_APM_REGION0_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4)
-/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region0
- */
-#define LP_APM_REGION0_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_START_M  (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S)
-#define LP_APM_REGION0_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_START_S  0
-
-/** LP_APM_REGION0_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8)
-/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region0
- */
-#define LP_APM_REGION0_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_END_M  (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S)
-#define LP_APM_REGION0_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION0_ADDR_END_S  0
-
-/** LP_APM_REGION0_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0xc)
-/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION0_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION0_R0_PMS_X_M  (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S)
-#define LP_APM_REGION0_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION0_R0_PMS_X_S  0
-/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION0_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION0_R0_PMS_W_M  (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S)
-#define LP_APM_REGION0_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION0_R0_PMS_W_S  1
-/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION0_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION0_R0_PMS_R_M  (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S)
-#define LP_APM_REGION0_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION0_R0_PMS_R_S  2
-/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION0_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION0_R1_PMS_X_M  (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S)
-#define LP_APM_REGION0_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION0_R1_PMS_X_S  4
-/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION0_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION0_R1_PMS_W_M  (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S)
-#define LP_APM_REGION0_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION0_R1_PMS_W_S  5
-/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION0_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION0_R1_PMS_R_M  (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S)
-#define LP_APM_REGION0_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION0_R1_PMS_R_S  6
-/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION0_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION0_R2_PMS_X_M  (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S)
-#define LP_APM_REGION0_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION0_R2_PMS_X_S  8
-/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION0_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION0_R2_PMS_W_M  (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S)
-#define LP_APM_REGION0_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION0_R2_PMS_W_S  9
-/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION0_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION0_R2_PMS_R_M  (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S)
-#define LP_APM_REGION0_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION0_R2_PMS_R_S  10
-/** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region0 configuration
- */
-#define LP_APM_REGION0_LOCK    (BIT(11))
-#define LP_APM_REGION0_LOCK_M  (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S)
-#define LP_APM_REGION0_LOCK_V  0x00000001U
-#define LP_APM_REGION0_LOCK_S  11
-
-/** LP_APM_REGION1_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10)
-/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region1
- */
-#define LP_APM_REGION1_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_START_M  (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S)
-#define LP_APM_REGION1_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_START_S  0
-
-/** LP_APM_REGION1_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14)
-/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region1
- */
-#define LP_APM_REGION1_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_END_M  (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S)
-#define LP_APM_REGION1_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION1_ADDR_END_S  0
-
-/** LP_APM_REGION1_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x18)
-/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION1_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION1_R0_PMS_X_M  (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S)
-#define LP_APM_REGION1_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION1_R0_PMS_X_S  0
-/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION1_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION1_R0_PMS_W_M  (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S)
-#define LP_APM_REGION1_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION1_R0_PMS_W_S  1
-/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION1_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION1_R0_PMS_R_M  (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S)
-#define LP_APM_REGION1_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION1_R0_PMS_R_S  2
-/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION1_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION1_R1_PMS_X_M  (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S)
-#define LP_APM_REGION1_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION1_R1_PMS_X_S  4
-/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION1_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION1_R1_PMS_W_M  (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S)
-#define LP_APM_REGION1_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION1_R1_PMS_W_S  5
-/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION1_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION1_R1_PMS_R_M  (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S)
-#define LP_APM_REGION1_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION1_R1_PMS_R_S  6
-/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION1_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION1_R2_PMS_X_M  (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S)
-#define LP_APM_REGION1_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION1_R2_PMS_X_S  8
-/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION1_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION1_R2_PMS_W_M  (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S)
-#define LP_APM_REGION1_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION1_R2_PMS_W_S  9
-/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION1_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION1_R2_PMS_R_M  (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S)
-#define LP_APM_REGION1_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION1_R2_PMS_R_S  10
-/** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region1 configuration
- */
-#define LP_APM_REGION1_LOCK    (BIT(11))
-#define LP_APM_REGION1_LOCK_M  (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S)
-#define LP_APM_REGION1_LOCK_V  0x00000001U
-#define LP_APM_REGION1_LOCK_S  11
-
-/** LP_APM_REGION2_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c)
-/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region2
- */
-#define LP_APM_REGION2_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_START_M  (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S)
-#define LP_APM_REGION2_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_START_S  0
-
-/** LP_APM_REGION2_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20)
-/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region2
- */
-#define LP_APM_REGION2_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_END_M  (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S)
-#define LP_APM_REGION2_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION2_ADDR_END_S  0
-
-/** LP_APM_REGION2_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION2_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x24)
-/** LP_APM_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION2_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION2_R0_PMS_X_M  (LP_APM_REGION2_R0_PMS_X_V << LP_APM_REGION2_R0_PMS_X_S)
-#define LP_APM_REGION2_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION2_R0_PMS_X_S  0
-/** LP_APM_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION2_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION2_R0_PMS_W_M  (LP_APM_REGION2_R0_PMS_W_V << LP_APM_REGION2_R0_PMS_W_S)
-#define LP_APM_REGION2_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION2_R0_PMS_W_S  1
-/** LP_APM_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION2_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION2_R0_PMS_R_M  (LP_APM_REGION2_R0_PMS_R_V << LP_APM_REGION2_R0_PMS_R_S)
-#define LP_APM_REGION2_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION2_R0_PMS_R_S  2
-/** LP_APM_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION2_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION2_R1_PMS_X_M  (LP_APM_REGION2_R1_PMS_X_V << LP_APM_REGION2_R1_PMS_X_S)
-#define LP_APM_REGION2_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION2_R1_PMS_X_S  4
-/** LP_APM_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION2_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION2_R1_PMS_W_M  (LP_APM_REGION2_R1_PMS_W_V << LP_APM_REGION2_R1_PMS_W_S)
-#define LP_APM_REGION2_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION2_R1_PMS_W_S  5
-/** LP_APM_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION2_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION2_R1_PMS_R_M  (LP_APM_REGION2_R1_PMS_R_V << LP_APM_REGION2_R1_PMS_R_S)
-#define LP_APM_REGION2_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION2_R1_PMS_R_S  6
-/** LP_APM_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION2_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION2_R2_PMS_X_M  (LP_APM_REGION2_R2_PMS_X_V << LP_APM_REGION2_R2_PMS_X_S)
-#define LP_APM_REGION2_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION2_R2_PMS_X_S  8
-/** LP_APM_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION2_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION2_R2_PMS_W_M  (LP_APM_REGION2_R2_PMS_W_V << LP_APM_REGION2_R2_PMS_W_S)
-#define LP_APM_REGION2_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION2_R2_PMS_W_S  9
-/** LP_APM_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION2_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION2_R2_PMS_R_M  (LP_APM_REGION2_R2_PMS_R_V << LP_APM_REGION2_R2_PMS_R_S)
-#define LP_APM_REGION2_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION2_R2_PMS_R_S  10
-/** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region2 configuration
- */
-#define LP_APM_REGION2_LOCK    (BIT(11))
-#define LP_APM_REGION2_LOCK_M  (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S)
-#define LP_APM_REGION2_LOCK_V  0x00000001U
-#define LP_APM_REGION2_LOCK_S  11
-
-/** LP_APM_REGION3_ADDR_START_REG register
- *  Region address register
- */
-#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28)
-/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
- *  Start address of region3
- */
-#define LP_APM_REGION3_ADDR_START    0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_START_M  (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S)
-#define LP_APM_REGION3_ADDR_START_V  0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_START_S  0
-
-/** LP_APM_REGION3_ADDR_END_REG register
- *  Region address register
- */
-#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c)
-/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
- *  End address of region3
- */
-#define LP_APM_REGION3_ADDR_END    0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_END_M  (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S)
-#define LP_APM_REGION3_ADDR_END_V  0xFFFFFFFFU
-#define LP_APM_REGION3_ADDR_END_S  0
-
-/** LP_APM_REGION3_PMS_ATTR_REG register
- *  Region access authority attribute register
- */
-#define LP_APM_REGION3_PMS_ATTR_REG (DR_REG_LP_APM_BASE + 0x30)
-/** LP_APM_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0;
- *  Region execute authority in REE_MODE0
- */
-#define LP_APM_REGION3_R0_PMS_X    (BIT(0))
-#define LP_APM_REGION3_R0_PMS_X_M  (LP_APM_REGION3_R0_PMS_X_V << LP_APM_REGION3_R0_PMS_X_S)
-#define LP_APM_REGION3_R0_PMS_X_V  0x00000001U
-#define LP_APM_REGION3_R0_PMS_X_S  0
-/** LP_APM_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0;
- *  Region write authority in REE_MODE0
- */
-#define LP_APM_REGION3_R0_PMS_W    (BIT(1))
-#define LP_APM_REGION3_R0_PMS_W_M  (LP_APM_REGION3_R0_PMS_W_V << LP_APM_REGION3_R0_PMS_W_S)
-#define LP_APM_REGION3_R0_PMS_W_V  0x00000001U
-#define LP_APM_REGION3_R0_PMS_W_S  1
-/** LP_APM_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0;
- *  Region read authority in REE_MODE0
- */
-#define LP_APM_REGION3_R0_PMS_R    (BIT(2))
-#define LP_APM_REGION3_R0_PMS_R_M  (LP_APM_REGION3_R0_PMS_R_V << LP_APM_REGION3_R0_PMS_R_S)
-#define LP_APM_REGION3_R0_PMS_R_V  0x00000001U
-#define LP_APM_REGION3_R0_PMS_R_S  2
-/** LP_APM_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0;
- *  Region execute authority in REE_MODE1
- */
-#define LP_APM_REGION3_R1_PMS_X    (BIT(4))
-#define LP_APM_REGION3_R1_PMS_X_M  (LP_APM_REGION3_R1_PMS_X_V << LP_APM_REGION3_R1_PMS_X_S)
-#define LP_APM_REGION3_R1_PMS_X_V  0x00000001U
-#define LP_APM_REGION3_R1_PMS_X_S  4
-/** LP_APM_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0;
- *  Region write authority in REE_MODE1
- */
-#define LP_APM_REGION3_R1_PMS_W    (BIT(5))
-#define LP_APM_REGION3_R1_PMS_W_M  (LP_APM_REGION3_R1_PMS_W_V << LP_APM_REGION3_R1_PMS_W_S)
-#define LP_APM_REGION3_R1_PMS_W_V  0x00000001U
-#define LP_APM_REGION3_R1_PMS_W_S  5
-/** LP_APM_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0;
- *  Region read authority in REE_MODE1
- */
-#define LP_APM_REGION3_R1_PMS_R    (BIT(6))
-#define LP_APM_REGION3_R1_PMS_R_M  (LP_APM_REGION3_R1_PMS_R_V << LP_APM_REGION3_R1_PMS_R_S)
-#define LP_APM_REGION3_R1_PMS_R_V  0x00000001U
-#define LP_APM_REGION3_R1_PMS_R_S  6
-/** LP_APM_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0;
- *  Region execute authority in REE_MODE2
- */
-#define LP_APM_REGION3_R2_PMS_X    (BIT(8))
-#define LP_APM_REGION3_R2_PMS_X_M  (LP_APM_REGION3_R2_PMS_X_V << LP_APM_REGION3_R2_PMS_X_S)
-#define LP_APM_REGION3_R2_PMS_X_V  0x00000001U
-#define LP_APM_REGION3_R2_PMS_X_S  8
-/** LP_APM_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0;
- *  Region write authority in REE_MODE2
- */
-#define LP_APM_REGION3_R2_PMS_W    (BIT(9))
-#define LP_APM_REGION3_R2_PMS_W_M  (LP_APM_REGION3_R2_PMS_W_V << LP_APM_REGION3_R2_PMS_W_S)
-#define LP_APM_REGION3_R2_PMS_W_V  0x00000001U
-#define LP_APM_REGION3_R2_PMS_W_S  9
-/** LP_APM_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0;
- *  Region read authority in REE_MODE2
- */
-#define LP_APM_REGION3_R2_PMS_R    (BIT(10))
-#define LP_APM_REGION3_R2_PMS_R_M  (LP_APM_REGION3_R2_PMS_R_V << LP_APM_REGION3_R2_PMS_R_S)
-#define LP_APM_REGION3_R2_PMS_R_V  0x00000001U
-#define LP_APM_REGION3_R2_PMS_R_S  10
-/** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0;
- *  Set 1 to lock region3 configuration
- */
-#define LP_APM_REGION3_LOCK    (BIT(11))
-#define LP_APM_REGION3_LOCK_M  (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S)
-#define LP_APM_REGION3_LOCK_V  0x00000001U
-#define LP_APM_REGION3_LOCK_S  11
-
-/** LP_APM_FUNC_CTRL_REG register
- *  PMS function control register
- */
-#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4)
-/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1;
- *  PMS M0 function enable
- */
-#define LP_APM_M0_PMS_FUNC_EN    (BIT(0))
-#define LP_APM_M0_PMS_FUNC_EN_M  (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S)
-#define LP_APM_M0_PMS_FUNC_EN_V  0x00000001U
-#define LP_APM_M0_PMS_FUNC_EN_S  0
-/** LP_APM_M1_PMS_FUNC_EN : R/W; bitpos: [1]; default: 1;
- *  PMS M1 function enable
- */
-#define LP_APM_M1_PMS_FUNC_EN    (BIT(1))
-#define LP_APM_M1_PMS_FUNC_EN_M  (LP_APM_M1_PMS_FUNC_EN_V << LP_APM_M1_PMS_FUNC_EN_S)
-#define LP_APM_M1_PMS_FUNC_EN_V  0x00000001U
-#define LP_APM_M1_PMS_FUNC_EN_S  1
-
-/** LP_APM_M0_STATUS_REG register
- *  M0 status register
- */
-#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8)
-/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define LP_APM_M0_EXCEPTION_STATUS    0x00000003U
-#define LP_APM_M0_EXCEPTION_STATUS_M  (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S)
-#define LP_APM_M0_EXCEPTION_STATUS_V  0x00000003U
-#define LP_APM_M0_EXCEPTION_STATUS_S  0
-
-/** LP_APM_M0_STATUS_CLR_REG register
- *  M0 status clear register
- */
-#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc)
-/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define LP_APM_M0_REGION_STATUS_CLR    (BIT(0))
-#define LP_APM_M0_REGION_STATUS_CLR_M  (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S)
-#define LP_APM_M0_REGION_STATUS_CLR_V  0x00000001U
-#define LP_APM_M0_REGION_STATUS_CLR_S  0
-
-/** LP_APM_M0_EXCEPTION_INFO0_REG register
- *  M0 exception_info0 register
- */
-#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0)
-/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
- *  Exception region
- */
-#define LP_APM_M0_EXCEPTION_REGION    0x0000000FU
-#define LP_APM_M0_EXCEPTION_REGION_M  (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S)
-#define LP_APM_M0_EXCEPTION_REGION_V  0x0000000FU
-#define LP_APM_M0_EXCEPTION_REGION_S  0
-/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define LP_APM_M0_EXCEPTION_MODE    0x00000003U
-#define LP_APM_M0_EXCEPTION_MODE_M  (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S)
-#define LP_APM_M0_EXCEPTION_MODE_V  0x00000003U
-#define LP_APM_M0_EXCEPTION_MODE_S  16
-/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define LP_APM_M0_EXCEPTION_ID    0x0000001FU
-#define LP_APM_M0_EXCEPTION_ID_M  (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S)
-#define LP_APM_M0_EXCEPTION_ID_V  0x0000001FU
-#define LP_APM_M0_EXCEPTION_ID_S  18
-
-/** LP_APM_M0_EXCEPTION_INFO1_REG register
- *  M0 exception_info1 register
- */
-#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4)
-/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define LP_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
-#define LP_APM_M0_EXCEPTION_ADDR_M  (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S)
-#define LP_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define LP_APM_M0_EXCEPTION_ADDR_S  0
-
-/** LP_APM_M1_STATUS_REG register
- *  M1 status register
- */
-#define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8)
-/** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
- *  Exception status
- */
-#define LP_APM_M1_EXCEPTION_STATUS    0x00000003U
-#define LP_APM_M1_EXCEPTION_STATUS_M  (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S)
-#define LP_APM_M1_EXCEPTION_STATUS_V  0x00000003U
-#define LP_APM_M1_EXCEPTION_STATUS_S  0
-
-/** LP_APM_M1_STATUS_CLR_REG register
- *  M1 status clear register
- */
-#define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc)
-/** LP_APM_M1_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0;
- *  Clear exception status
- */
-#define LP_APM_M1_REGION_STATUS_CLR    (BIT(0))
-#define LP_APM_M1_REGION_STATUS_CLR_M  (LP_APM_M1_REGION_STATUS_CLR_V << LP_APM_M1_REGION_STATUS_CLR_S)
-#define LP_APM_M1_REGION_STATUS_CLR_V  0x00000001U
-#define LP_APM_M1_REGION_STATUS_CLR_S  0
-
-/** LP_APM_M1_EXCEPTION_INFO0_REG register
- *  M1 exception_info0 register
- */
-#define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0)
-/** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0;
- *  Exception region
- */
-#define LP_APM_M1_EXCEPTION_REGION    0x0000000FU
-#define LP_APM_M1_EXCEPTION_REGION_M  (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S)
-#define LP_APM_M1_EXCEPTION_REGION_V  0x0000000FU
-#define LP_APM_M1_EXCEPTION_REGION_S  0
-/** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
- *  Exception mode
- */
-#define LP_APM_M1_EXCEPTION_MODE    0x00000003U
-#define LP_APM_M1_EXCEPTION_MODE_M  (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S)
-#define LP_APM_M1_EXCEPTION_MODE_V  0x00000003U
-#define LP_APM_M1_EXCEPTION_MODE_S  16
-/** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
- *  Exception id information
- */
-#define LP_APM_M1_EXCEPTION_ID    0x0000001FU
-#define LP_APM_M1_EXCEPTION_ID_M  (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S)
-#define LP_APM_M1_EXCEPTION_ID_V  0x0000001FU
-#define LP_APM_M1_EXCEPTION_ID_S  18
-
-/** LP_APM_M1_EXCEPTION_INFO1_REG register
- *  M1 exception_info1 register
- */
-#define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4)
-/** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Exception addr
- */
-#define LP_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
-#define LP_APM_M1_EXCEPTION_ADDR_M  (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S)
-#define LP_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
-#define LP_APM_M1_EXCEPTION_ADDR_S  0
-
-/** LP_APM_INT_EN_REG register
- *  APM interrupt enable register
- */
-#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8)
-/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
- *  APM M0 interrupt enable
- */
-#define LP_APM_M0_APM_INT_EN    (BIT(0))
-#define LP_APM_M0_APM_INT_EN_M  (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S)
-#define LP_APM_M0_APM_INT_EN_V  0x00000001U
-#define LP_APM_M0_APM_INT_EN_S  0
-/** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
- *  APM M1 interrupt enable
- */
-#define LP_APM_M1_APM_INT_EN    (BIT(1))
-#define LP_APM_M1_APM_INT_EN_M  (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S)
-#define LP_APM_M1_APM_INT_EN_V  0x00000001U
-#define LP_APM_M1_APM_INT_EN_S  1
-
-/** LP_APM_CLOCK_GATE_REG register
- *  clock gating register
- */
-#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec)
-/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define LP_APM_CLK_EN    (BIT(0))
-#define LP_APM_CLK_EN_M  (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S)
-#define LP_APM_CLK_EN_V  0x00000001U
-#define LP_APM_CLK_EN_S  0
-
-/** LP_APM_DATE_REG register
- *  Version register
- */
-#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc)
-/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664;
- *  reg_date
- */
-#define LP_APM_DATE    0x0FFFFFFFU
-#define LP_APM_DATE_M  (LP_APM_DATE_V << LP_APM_DATE_S)
-#define LP_APM_DATE_V  0x0FFFFFFFU
-#define LP_APM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_apm_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_apm_struct.h
deleted file mode 100644
index 8f7c356912..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_apm_struct.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Region filter enable register */
-/** Type of region_filter_en register
- *  Region filter enable register
- */
-typedef union {
-    struct {
-        /** region_filter_en : R/W; bitpos: [3:0]; default: 1;
-         *  Region filter enable
-         */
-        uint32_t region_filter_en:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_apm_region_filter_en_reg_t;
-
-
-/** Group: Region address register */
-/** Type of region0_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region0
-         */
-        uint32_t region0_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region0_addr_start_reg_t;
-
-/** Type of region0_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region0
-         */
-        uint32_t region0_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region0_addr_end_reg_t;
-
-/** Type of region1_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region1
-         */
-        uint32_t region1_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region1_addr_start_reg_t;
-
-/** Type of region1_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region1
-         */
-        uint32_t region1_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region1_addr_end_reg_t;
-
-/** Type of region2_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region2
-         */
-        uint32_t region2_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region2_addr_start_reg_t;
-
-/** Type of region2_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region2
-         */
-        uint32_t region2_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region2_addr_end_reg_t;
-
-/** Type of region3_addr_start register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_start : R/W; bitpos: [31:0]; default: 0;
-         *  Start address of region3
-         */
-        uint32_t region3_addr_start:32;
-    };
-    uint32_t val;
-} lp_apm_region3_addr_start_reg_t;
-
-/** Type of region3_addr_end register
- *  Region address register
- */
-typedef union {
-    struct {
-        /** region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
-         *  End address of region3
-         */
-        uint32_t region3_addr_end:32;
-    };
-    uint32_t val;
-} lp_apm_region3_addr_end_reg_t;
-
-
-/** Group: Region access authority attribute register */
-/** Type of region0_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region0_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_x:1;
-        /** region0_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_w:1;
-        /** region0_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region0_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region0_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_x:1;
-        /** region0_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_w:1;
-        /** region0_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region0_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region0_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_x:1;
-        /** region0_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_w:1;
-        /** region0_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region0_r2_pms_r:1;
-        /** region0_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region0 configuration
-         */
-        uint32_t region0_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm_region0_pms_attr_reg_t;
-
-/** Type of region1_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region1_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_x:1;
-        /** region1_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_w:1;
-        /** region1_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region1_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region1_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_x:1;
-        /** region1_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_w:1;
-        /** region1_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region1_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region1_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_x:1;
-        /** region1_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_w:1;
-        /** region1_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region1_r2_pms_r:1;
-        /** region1_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region1 configuration
-         */
-        uint32_t region1_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm_region1_pms_attr_reg_t;
-
-/** Type of region2_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region2_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_x:1;
-        /** region2_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_w:1;
-        /** region2_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region2_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region2_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_x:1;
-        /** region2_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_w:1;
-        /** region2_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region2_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region2_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_x:1;
-        /** region2_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_w:1;
-        /** region2_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region2_r2_pms_r:1;
-        /** region2_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region2 configuration
-         */
-        uint32_t region2_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm_region2_pms_attr_reg_t;
-
-/** Type of region3_pms_attr register
- *  Region access authority attribute register
- */
-typedef union {
-    struct {
-        /** region3_r0_pms_x : R/W; bitpos: [0]; default: 0;
-         *  Region execute authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_x:1;
-        /** region3_r0_pms_w : R/W; bitpos: [1]; default: 0;
-         *  Region write authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_w:1;
-        /** region3_r0_pms_r : R/W; bitpos: [2]; default: 0;
-         *  Region read authority in REE_MODE0
-         */
-        uint32_t region3_r0_pms_r:1;
-        uint32_t reserved_3:1;
-        /** region3_r1_pms_x : R/W; bitpos: [4]; default: 0;
-         *  Region execute authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_x:1;
-        /** region3_r1_pms_w : R/W; bitpos: [5]; default: 0;
-         *  Region write authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_w:1;
-        /** region3_r1_pms_r : R/W; bitpos: [6]; default: 0;
-         *  Region read authority in REE_MODE1
-         */
-        uint32_t region3_r1_pms_r:1;
-        uint32_t reserved_7:1;
-        /** region3_r2_pms_x : R/W; bitpos: [8]; default: 0;
-         *  Region execute authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_x:1;
-        /** region3_r2_pms_w : R/W; bitpos: [9]; default: 0;
-         *  Region write authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_w:1;
-        /** region3_r2_pms_r : R/W; bitpos: [10]; default: 0;
-         *  Region read authority in REE_MODE2
-         */
-        uint32_t region3_r2_pms_r:1;
-        /** region3_lock : R/W; bitpos: [11]; default: 0;
-         *  Set 1 to lock region3 configuration
-         */
-        uint32_t region3_lock:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_apm_region3_pms_attr_reg_t;
-
-
-/** Group: PMS function control register */
-/** Type of func_ctrl register
- *  PMS function control register
- */
-typedef union {
-    struct {
-        /** m0_pms_func_en : R/W; bitpos: [0]; default: 1;
-         *  PMS M0 function enable
-         */
-        uint32_t m0_pms_func_en:1;
-        /** m1_pms_func_en : R/W; bitpos: [1]; default: 1;
-         *  PMS M1 function enable
-         */
-        uint32_t m1_pms_func_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_func_ctrl_reg_t;
-
-
-/** Group: M0 status register */
-/** Type of m0_status register
- *  M0 status register
- */
-typedef union {
-    struct {
-        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m0_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_m0_status_reg_t;
-
-
-/** Group: M0 status clear register */
-/** Type of m0_status_clr register
- *  M0 status clear register
- */
-typedef union {
-    struct {
-        /** m0_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m0_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm_m0_status_clr_reg_t;
-
-
-/** Group: M0 exception_info0 register */
-/** Type of m0_exception_info0 register
- *  M0 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m0_exception_region : RO; bitpos: [3:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m0_exception_region:4;
-        uint32_t reserved_4:12;
-        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m0_exception_mode:2;
-        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m0_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_apm_m0_exception_info0_reg_t;
-
-
-/** Group: M0 exception_info1 register */
-/** Type of m0_exception_info1 register
- *  M0 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m0_exception_addr:32;
-    };
-    uint32_t val;
-} lp_apm_m0_exception_info1_reg_t;
-
-
-/** Group: M1 status register */
-/** Type of m1_status register
- *  M1 status register
- */
-typedef union {
-    struct {
-        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
-         *  Exception status
-         */
-        uint32_t m1_exception_status:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_m1_status_reg_t;
-
-
-/** Group: M1 status clear register */
-/** Type of m1_status_clr register
- *  M1 status clear register
- */
-typedef union {
-    struct {
-        /** m1_region_status_clr : WT; bitpos: [0]; default: 0;
-         *  Clear exception status
-         */
-        uint32_t m1_region_status_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm_m1_status_clr_reg_t;
-
-
-/** Group: M1 exception_info0 register */
-/** Type of m1_exception_info0 register
- *  M1 exception_info0 register
- */
-typedef union {
-    struct {
-        /** m1_exception_region : RO; bitpos: [3:0]; default: 0;
-         *  Exception region
-         */
-        uint32_t m1_exception_region:4;
-        uint32_t reserved_4:12;
-        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
-         *  Exception mode
-         */
-        uint32_t m1_exception_mode:2;
-        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
-         *  Exception id information
-         */
-        uint32_t m1_exception_id:5;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_apm_m1_exception_info0_reg_t;
-
-
-/** Group: M1 exception_info1 register */
-/** Type of m1_exception_info1 register
- *  M1 exception_info1 register
- */
-typedef union {
-    struct {
-        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
-         *  Exception addr
-         */
-        uint32_t m1_exception_addr:32;
-    };
-    uint32_t val;
-} lp_apm_m1_exception_info1_reg_t;
-
-
-/** Group: APM interrupt enable register */
-/** Type of int_en register
- *  APM interrupt enable register
- */
-typedef union {
-    struct {
-        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
-         *  APM M0 interrupt enable
-         */
-        uint32_t m0_apm_int_en:1;
-        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
-         *  APM M1 interrupt enable
-         */
-        uint32_t m1_apm_int_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} lp_apm_int_en_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_apm_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725664;
-         *  reg_date
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_apm_date_reg_t;
-
-
-typedef struct lp_apm_dev_t {
-    volatile lp_apm_region_filter_en_reg_t region_filter_en;
-    volatile lp_apm_region0_addr_start_reg_t region0_addr_start;
-    volatile lp_apm_region0_addr_end_reg_t region0_addr_end;
-    volatile lp_apm_region0_pms_attr_reg_t region0_pms_attr;
-    volatile lp_apm_region1_addr_start_reg_t region1_addr_start;
-    volatile lp_apm_region1_addr_end_reg_t region1_addr_end;
-    volatile lp_apm_region1_pms_attr_reg_t region1_pms_attr;
-    volatile lp_apm_region2_addr_start_reg_t region2_addr_start;
-    volatile lp_apm_region2_addr_end_reg_t region2_addr_end;
-    volatile lp_apm_region2_pms_attr_reg_t region2_pms_attr;
-    volatile lp_apm_region3_addr_start_reg_t region3_addr_start;
-    volatile lp_apm_region3_addr_end_reg_t region3_addr_end;
-    volatile lp_apm_region3_pms_attr_reg_t region3_pms_attr;
-    uint32_t reserved_034[36];
-    volatile lp_apm_func_ctrl_reg_t func_ctrl;
-    volatile lp_apm_m0_status_reg_t m0_status;
-    volatile lp_apm_m0_status_clr_reg_t m0_status_clr;
-    volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0;
-    volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1;
-    volatile lp_apm_m1_status_reg_t m1_status;
-    volatile lp_apm_m1_status_clr_reg_t m1_status_clr;
-    volatile lp_apm_m1_exception_info0_reg_t m1_exception_info0;
-    volatile lp_apm_m1_exception_info1_reg_t m1_exception_info1;
-    volatile lp_apm_int_en_reg_t int_en;
-    volatile lp_apm_clock_gate_reg_t clock_gate;
-    uint32_t reserved_0f0[3];
-    volatile lp_apm_date_reg_t date;
-} lp_apm_dev_t;
-
-extern lp_apm_dev_t LP_APM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_clkrst_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_clkrst_reg.h
deleted file mode 100644
index 6cd5afc503..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_clkrst_reg.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_CLKRST_LP_CLK_CONF_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
-/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_SLOW_CLK_SEL    0x00000003U
-#define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
-#define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
-#define LP_CLKRST_SLOW_CLK_SEL_S  0
-/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_FAST_CLK_SEL    0x00000003U
-#define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
-#define LP_CLKRST_FAST_CLK_SEL_V  0x00000003U
-#define LP_CLKRST_FAST_CLK_SEL_S  2
-/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_PERI_DIV_NUM    0x000000FFU
-#define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
-#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x000000FFU
-#define LP_CLKRST_LP_PERI_DIV_NUM_S  4
-
-/** LP_CLKRST_LP_CLK_PO_EN_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
-/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_AON_SLOW_OEN    (BIT(0))
-#define LP_CLKRST_AON_SLOW_OEN_M  (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
-#define LP_CLKRST_AON_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_AON_SLOW_OEN_S  0
-/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_AON_FAST_OEN    (BIT(1))
-#define LP_CLKRST_AON_FAST_OEN_M  (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
-#define LP_CLKRST_AON_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_AON_FAST_OEN_S  1
-/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_SOSC_OEN    (BIT(2))
-#define LP_CLKRST_SOSC_OEN_M  (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
-#define LP_CLKRST_SOSC_OEN_V  0x00000001U
-#define LP_CLKRST_SOSC_OEN_S  2
-/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_FOSC_OEN    (BIT(3))
-#define LP_CLKRST_FOSC_OEN_M  (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
-#define LP_CLKRST_FOSC_OEN_V  0x00000001U
-#define LP_CLKRST_FOSC_OEN_S  3
-/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_OSC32K_OEN    (BIT(4))
-#define LP_CLKRST_OSC32K_OEN_M  (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
-#define LP_CLKRST_OSC32K_OEN_V  0x00000001U
-#define LP_CLKRST_OSC32K_OEN_S  4
-/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_XTAL32K_OEN    (BIT(5))
-#define LP_CLKRST_XTAL32K_OEN_M  (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
-#define LP_CLKRST_XTAL32K_OEN_V  0x00000001U
-#define LP_CLKRST_XTAL32K_OEN_S  5
-/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_CORE_EFUSE_OEN    (BIT(6))
-#define LP_CLKRST_CORE_EFUSE_OEN_M  (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
-#define LP_CLKRST_CORE_EFUSE_OEN_V  0x00000001U
-#define LP_CLKRST_CORE_EFUSE_OEN_S  6
-/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_SLOW_OEN    (BIT(7))
-#define LP_CLKRST_SLOW_OEN_M  (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
-#define LP_CLKRST_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_SLOW_OEN_S  7
-/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_FAST_OEN    (BIT(8))
-#define LP_CLKRST_FAST_OEN_M  (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
-#define LP_CLKRST_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_FAST_OEN_S  8
-/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_RNG_OEN    (BIT(9))
-#define LP_CLKRST_RNG_OEN_M  (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
-#define LP_CLKRST_RNG_OEN_V  0x00000001U
-#define LP_CLKRST_RNG_OEN_S  9
-/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_LPBUS_OEN    (BIT(10))
-#define LP_CLKRST_LPBUS_OEN_M  (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
-#define LP_CLKRST_LPBUS_OEN_V  0x00000001U
-#define LP_CLKRST_LPBUS_OEN_S  10
-
-/** LP_CLKRST_LP_CLK_EN_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
-/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_FAST_ORI_GATE    (BIT(31))
-#define LP_CLKRST_FAST_ORI_GATE_M  (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
-#define LP_CLKRST_FAST_ORI_GATE_V  0x00000001U
-#define LP_CLKRST_FAST_ORI_GATE_S  31
-
-/** LP_CLKRST_LP_RST_EN_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
-/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HUK_RESET_EN    (BIT(27))
-#define LP_CLKRST_HUK_RESET_EN_M  (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S)
-#define LP_CLKRST_HUK_RESET_EN_V  0x00000001U
-#define LP_CLKRST_HUK_RESET_EN_S  27
-/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN    (BIT(28))
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M  (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V  0x00000001U
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S  28
-/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_TIMER_RESET_EN    (BIT(29))
-#define LP_CLKRST_LP_TIMER_RESET_EN_M  (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
-#define LP_CLKRST_LP_TIMER_RESET_EN_V  0x00000001U
-#define LP_CLKRST_LP_TIMER_RESET_EN_S  29
-/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_WDT_RESET_EN    (BIT(30))
-#define LP_CLKRST_WDT_RESET_EN_M  (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
-#define LP_CLKRST_WDT_RESET_EN_V  0x00000001U
-#define LP_CLKRST_WDT_RESET_EN_S  30
-/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_ANA_PERI_RESET_EN    (BIT(31))
-#define LP_CLKRST_ANA_PERI_RESET_EN_M  (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
-#define LP_CLKRST_ANA_PERI_RESET_EN_V  0x00000001U
-#define LP_CLKRST_ANA_PERI_RESET_EN_S  31
-
-/** LP_CLKRST_RESET_CAUSE_REG register
- *  need_des
- */
-#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
-/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RESET_CAUSE    0x0000001FU
-#define LP_CLKRST_RESET_CAUSE_M  (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
-#define LP_CLKRST_RESET_CAUSE_V  0x0000001FU
-#define LP_CLKRST_RESET_CAUSE_S  0
-/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_CORE0_RESET_FLAG    (BIT(5))
-#define LP_CLKRST_CORE0_RESET_FLAG_M  (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_S  5
-/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR    (BIT(29))
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S  29
-/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CORE0_RESET_FLAG_SET    (BIT(30))
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_M  (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_S  30
-/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR    (BIT(31))
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M  (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S  31
-
-/** LP_CLKRST_CPU_RESET_REG register
- *  need_des
- */
-#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
-/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
- *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
- *  reset feature
- */
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(21))
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S  21
-/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH    0x00000007U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M  (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V  0x00000007U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S  22
-/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN    (BIT(25))
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M  (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V  0x00000001U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S  25
-/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_CPU_STALL_WAIT    0x0000001FU
-#define LP_CLKRST_CPU_STALL_WAIT_M  (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
-#define LP_CLKRST_CPU_STALL_WAIT_V  0x0000001FU
-#define LP_CLKRST_CPU_STALL_WAIT_S  26
-/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CPU_STALL_EN    (BIT(31))
-#define LP_CLKRST_CPU_STALL_EN_M  (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
-#define LP_CLKRST_CPU_STALL_EN_V  0x00000001U
-#define LP_CLKRST_CPU_STALL_EN_S  31
-
-/** LP_CLKRST_FOSC_CNTL_REG register
- *  need_des
- */
-#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
-/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
- *  need_des
- */
-#define LP_CLKRST_FOSC_DFREQ    0x000003FFU
-#define LP_CLKRST_FOSC_DFREQ_M  (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
-#define LP_CLKRST_FOSC_DFREQ_V  0x000003FFU
-#define LP_CLKRST_FOSC_DFREQ_S  22
-
-/** LP_CLKRST_RC32K_CNTL_REG register
- *  need_des
- */
-#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
-/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
- *  need_des
- */
-#define LP_CLKRST_RC32K_DFREQ    0x000003FFU
-#define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
-#define LP_CLKRST_RC32K_DFREQ_V  0x000003FFU
-#define LP_CLKRST_RC32K_DFREQ_S  22
-
-/** LP_CLKRST_CLK_TO_HP_REG register
- *  need_des
- */
-#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
-/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
-#define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
-#define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
-#define LP_CLKRST_ICG_HP_XTAL32K_S  28
-/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
-#define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
-#define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
-#define LP_CLKRST_ICG_HP_SOSC_S  29
-/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
-#define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
-#define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
-#define LP_CLKRST_ICG_HP_OSC32K_S  30
-/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
-#define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
-#define LP_CLKRST_ICG_HP_FOSC_V  0x00000001U
-#define LP_CLKRST_ICG_HP_FOSC_S  31
-
-/** LP_CLKRST_LPMEM_FORCE_REG register
- *  need_des
- */
-#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
-/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
-
-/** LP_CLKRST_LPPERI_REG register
- *  need_des
- */
-#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28)
-/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [29]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_HUK_CLK_SEL    (BIT(29))
-#define LP_CLKRST_HUK_CLK_SEL_M  (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S)
-#define LP_CLKRST_HUK_CLK_SEL_V  0x00000001U
-#define LP_CLKRST_HUK_CLK_SEL_S  29
-/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_I2C_CLK_SEL    (BIT(30))
-#define LP_CLKRST_LP_I2C_CLK_SEL_M  (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S)
-#define LP_CLKRST_LP_I2C_CLK_SEL_V  0x00000001U
-#define LP_CLKRST_LP_I2C_CLK_SEL_S  30
-/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_UART_CLK_SEL    (BIT(31))
-#define LP_CLKRST_LP_UART_CLK_SEL_M  (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S)
-#define LP_CLKRST_LP_UART_CLK_SEL_V  0x00000001U
-#define LP_CLKRST_LP_UART_CLK_SEL_S  31
-
-/** LP_CLKRST_XTAL32K_REG register
- *  need_des
- */
-#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
-/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
- *  need_des
- */
-#define LP_CLKRST_DRES_XTAL32K    0x00000007U
-#define LP_CLKRST_DRES_XTAL32K_M  (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
-#define LP_CLKRST_DRES_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DRES_XTAL32K_S  22
-/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
- *  need_des
- */
-#define LP_CLKRST_DGM_XTAL32K    0x00000007U
-#define LP_CLKRST_DGM_XTAL32K_M  (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
-#define LP_CLKRST_DGM_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DGM_XTAL32K_S  25
-/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_DBUF_XTAL32K    (BIT(28))
-#define LP_CLKRST_DBUF_XTAL32K_M  (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
-#define LP_CLKRST_DBUF_XTAL32K_V  0x00000001U
-#define LP_CLKRST_DBUF_XTAL32K_S  28
-/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
- *  need_des
- */
-#define LP_CLKRST_DAC_XTAL32K    0x00000007U
-#define LP_CLKRST_DAC_XTAL32K_M  (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
-#define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DAC_XTAL32K_S  29
-
-/** LP_CLKRST_DATE_REG register
- *  need_des
- */
-#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
-/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36720768;
- *  need_des
- */
-#define LP_CLKRST_CLKRST_DATE    0x7FFFFFFFU
-#define LP_CLKRST_CLKRST_DATE_M  (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
-#define LP_CLKRST_CLKRST_DATE_V  0x7FFFFFFFU
-#define LP_CLKRST_CLKRST_DATE_S  0
-/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_EN    (BIT(31))
-#define LP_CLKRST_CLK_EN_M  (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
-#define LP_CLKRST_CLK_EN_V  0x00000001U
-#define LP_CLKRST_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_clkrst_struct.h
deleted file mode 100644
index 3f348c0cd5..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_clkrst_struct.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of lp_clk_conf register
- *  need_des
- */
-typedef union {
-    struct {
-        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
-         *  need_des
-         */
-        uint32_t slow_clk_sel:2;
-        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_clk_sel:2;
-        /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_peri_div_num:8;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_conf_reg_t;
-
-/** Type of lp_clk_po_en register
- *  need_des
- */
-typedef union {
-    struct {
-        /** aon_slow_oen : R/W; bitpos: [0]; default: 1;
-         *  need_des
-         */
-        uint32_t aon_slow_oen:1;
-        /** aon_fast_oen : R/W; bitpos: [1]; default: 1;
-         *  need_des
-         */
-        uint32_t aon_fast_oen:1;
-        /** sosc_oen : R/W; bitpos: [2]; default: 1;
-         *  need_des
-         */
-        uint32_t sosc_oen:1;
-        /** fosc_oen : R/W; bitpos: [3]; default: 1;
-         *  need_des
-         */
-        uint32_t fosc_oen:1;
-        /** osc32k_oen : R/W; bitpos: [4]; default: 1;
-         *  need_des
-         */
-        uint32_t osc32k_oen:1;
-        /** xtal32k_oen : R/W; bitpos: [5]; default: 1;
-         *  need_des
-         */
-        uint32_t xtal32k_oen:1;
-        /** core_efuse_oen : R/W; bitpos: [6]; default: 1;
-         *  need_des
-         */
-        uint32_t core_efuse_oen:1;
-        /** slow_oen : R/W; bitpos: [7]; default: 1;
-         *  need_des
-         */
-        uint32_t slow_oen:1;
-        /** fast_oen : R/W; bitpos: [8]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_oen:1;
-        /** rng_oen : R/W; bitpos: [9]; default: 1;
-         *  need_des
-         */
-        uint32_t rng_oen:1;
-        /** lpbus_oen : R/W; bitpos: [10]; default: 1;
-         *  need_des
-         */
-        uint32_t lpbus_oen:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_po_en_reg_t;
-
-/** Type of lp_clk_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** fast_ori_gate : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t fast_ori_gate:1;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_en_reg_t;
-
-/** Type of lp_rst_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** huk_reset_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t huk_reset_en:1;
-        /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t aon_efuse_core_reset_en:1;
-        /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_timer_reset_en:1;
-        /** wdt_reset_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_reset_en:1;
-        /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_peri_reset_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_lp_rst_en_reg_t;
-
-/** Type of reset_cause register
- *  need_des
- */
-typedef union {
-    struct {
-        /** reset_cause : RO; bitpos: [4:0]; default: 0;
-         *  need_des
-         */
-        uint32_t reset_cause:5;
-        /** core0_reset_flag : RO; bitpos: [5]; default: 1;
-         *  need_des
-         */
-        uint32_t core0_reset_flag:1;
-        uint32_t reserved_6:23;
-        /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t core0_reset_cause_clr:1;
-        /** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t core0_reset_flag_set:1;
-        /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t core0_reset_flag_clr:1;
-    };
-    uint32_t val;
-} lp_clkrst_reset_cause_reg_t;
-
-/** Type of cpu_reset register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1;
-         *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
-         *  reset feature
-         */
-        uint32_t hpcore0_lockup_reset_en:1;
-        /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
-         *  need_des
-         */
-        uint32_t rtc_wdt_cpu_reset_length:3;
-        /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t rtc_wdt_cpu_reset_en:1;
-        /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
-         *  need_des
-         */
-        uint32_t cpu_stall_wait:5;
-        /** cpu_stall_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_stall_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_cpu_reset_reg_t;
-
-/** Type of fosc_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
-         *  need_des
-         */
-        uint32_t fosc_dfreq:10;
-    };
-    uint32_t val;
-} lp_clkrst_fosc_cntl_reg_t;
-
-/** Type of rc32k_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
-         *  need_des
-         */
-        uint32_t rc32k_dfreq:10;
-    };
-    uint32_t val;
-} lp_clkrst_rc32k_cntl_reg_t;
-
-/** Type of clk_to_hp register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
-         *  need_des
-         */
-        uint32_t icg_hp_xtal32k:1;
-        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
-         *  need_des
-         */
-        uint32_t icg_hp_sosc:1;
-        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
-         *  need_des
-         */
-        uint32_t icg_hp_osc32k:1;
-        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t icg_hp_fosc:1;
-    };
-    uint32_t val;
-} lp_clkrst_clk_to_hp_reg_t;
-
-/** Type of lpmem_force register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lpmem_clk_force_on:1;
-    };
-    uint32_t val;
-} lp_clkrst_lpmem_force_reg_t;
-
-/** Type of lpperi register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:29;
-        /** huk_clk_sel : R/W; bitpos: [29]; default: 1;
-         *  need_des
-         */
-        uint32_t huk_clk_sel:1;
-        /** lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_i2c_clk_sel:1;
-        /** lp_uart_clk_sel : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_uart_clk_sel:1;
-    };
-    uint32_t val;
-} lp_clkrst_lpperi_reg_t;
-
-/** Type of xtal32k register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
-         *  need_des
-         */
-        uint32_t dres_xtal32k:3;
-        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
-         *  need_des
-         */
-        uint32_t dgm_xtal32k:3;
-        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t dbuf_xtal32k:1;
-        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
-         *  need_des
-         */
-        uint32_t dac_xtal32k:3;
-    };
-    uint32_t val;
-} lp_clkrst_xtal32k_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** clkrst_date : R/W; bitpos: [30:0]; default: 36720768;
-         *  need_des
-         */
-        uint32_t clkrst_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_date_reg_t;
-
-
-typedef struct lp_clkrst_dev_t {
-    volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
-    volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
-    volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
-    volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
-    volatile lp_clkrst_reset_cause_reg_t reset_cause;
-    volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
-    volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
-    volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
-    volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
-    volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
-    volatile lp_clkrst_lpperi_reg_t lpperi;
-    volatile lp_clkrst_xtal32k_reg_t xtal32k;
-    uint32_t reserved_030[243];
-    volatile lp_clkrst_date_reg_t date;
-} lp_clkrst_dev_t;
-
-extern lp_clkrst_dev_t LP_CLKRST;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_reg.h
deleted file mode 100644
index 5e67e185b3..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_reg.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_I2C_ANA_MST_I2C0_CTRL_REG register
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x0)
-/** LP_I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_CTRL    0x01FFFFFFU
-#define LP_I2C_ANA_MST_I2C0_CTRL_M  (LP_I2C_ANA_MST_I2C0_CTRL_V << LP_I2C_ANA_MST_I2C0_CTRL_S)
-#define LP_I2C_ANA_MST_I2C0_CTRL_V  0x01FFFFFFU
-#define LP_I2C_ANA_MST_I2C0_CTRL_S  0
-/** LP_I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_BUSY    (BIT(25))
-#define LP_I2C_ANA_MST_I2C0_BUSY_M  (LP_I2C_ANA_MST_I2C0_BUSY_V << LP_I2C_ANA_MST_I2C0_BUSY_S)
-#define LP_I2C_ANA_MST_I2C0_BUSY_V  0x00000001U
-#define LP_I2C_ANA_MST_I2C0_BUSY_S  25
-
-/** LP_I2C_ANA_MST_I2C0_CONF_REG register
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_CONF_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x4)
-/** LP_I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_CONF    0x00FFFFFFU
-#define LP_I2C_ANA_MST_I2C0_CONF_M  (LP_I2C_ANA_MST_I2C0_CONF_V << LP_I2C_ANA_MST_I2C0_CONF_S)
-#define LP_I2C_ANA_MST_I2C0_CONF_V  0x00FFFFFFU
-#define LP_I2C_ANA_MST_I2C0_CONF_S  0
-/** LP_I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 7;
- *  reserved
- */
-#define LP_I2C_ANA_MST_I2C0_STATUS    0x000000FFU
-#define LP_I2C_ANA_MST_I2C0_STATUS_M  (LP_I2C_ANA_MST_I2C0_STATUS_V << LP_I2C_ANA_MST_I2C0_STATUS_S)
-#define LP_I2C_ANA_MST_I2C0_STATUS_V  0x000000FFU
-#define LP_I2C_ANA_MST_I2C0_STATUS_S  24
-
-/** LP_I2C_ANA_MST_I2C0_DATA_REG register
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_DATA_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x8)
-/** LP_I2C_ANA_MST_I2C0_RDATA : RO; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_RDATA    0x000000FFU
-#define LP_I2C_ANA_MST_I2C0_RDATA_M  (LP_I2C_ANA_MST_I2C0_RDATA_V << LP_I2C_ANA_MST_I2C0_RDATA_S)
-#define LP_I2C_ANA_MST_I2C0_RDATA_V  0x000000FFU
-#define LP_I2C_ANA_MST_I2C0_RDATA_S  0
-/** LP_I2C_ANA_MST_I2C0_CLK_SEL : R/W; bitpos: [10:8]; default: 1;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C0_CLK_SEL    0x00000007U
-#define LP_I2C_ANA_MST_I2C0_CLK_SEL_M  (LP_I2C_ANA_MST_I2C0_CLK_SEL_V << LP_I2C_ANA_MST_I2C0_CLK_SEL_S)
-#define LP_I2C_ANA_MST_I2C0_CLK_SEL_V  0x00000007U
-#define LP_I2C_ANA_MST_I2C0_CLK_SEL_S  8
-/** LP_I2C_ANA_MST_I2C_MST_SEL : R/W; bitpos: [11]; default: 1;
- *  need  des
- */
-#define LP_I2C_ANA_MST_I2C_MST_SEL    (BIT(11))
-#define LP_I2C_ANA_MST_I2C_MST_SEL_M  (LP_I2C_ANA_MST_I2C_MST_SEL_V << LP_I2C_ANA_MST_I2C_MST_SEL_S)
-#define LP_I2C_ANA_MST_I2C_MST_SEL_V  0x00000001U
-#define LP_I2C_ANA_MST_I2C_MST_SEL_S  11
-
-/** LP_I2C_ANA_MST_ANA_CONF1_REG register
- *  need_des
- */
-#define LP_I2C_ANA_MST_ANA_CONF1_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0xc)
-/** LP_I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_ANA_CONF1    0x00FFFFFFU
-#define LP_I2C_ANA_MST_ANA_CONF1_M  (LP_I2C_ANA_MST_ANA_CONF1_V << LP_I2C_ANA_MST_ANA_CONF1_S)
-#define LP_I2C_ANA_MST_ANA_CONF1_V  0x00FFFFFFU
-#define LP_I2C_ANA_MST_ANA_CONF1_S  0
-
-/** LP_I2C_ANA_MST_NOUSE_REG register
- *  need_des
- */
-#define LP_I2C_ANA_MST_NOUSE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x10)
-/** LP_I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C_MST_NOUSE    0xFFFFFFFFU
-#define LP_I2C_ANA_MST_I2C_MST_NOUSE_M  (LP_I2C_ANA_MST_I2C_MST_NOUSE_V << LP_I2C_ANA_MST_I2C_MST_NOUSE_S)
-#define LP_I2C_ANA_MST_I2C_MST_NOUSE_V  0xFFFFFFFFU
-#define LP_I2C_ANA_MST_I2C_MST_NOUSE_S  0
-
-/** LP_I2C_ANA_MST_DEVICE_EN_REG register
- *  need_des
- */
-#define LP_I2C_ANA_MST_DEVICE_EN_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x14)
-/** LP_I2C_ANA_MST_I2C_DEVICE_EN : R/W; bitpos: [11:0]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C_DEVICE_EN    0x00000FFFU
-#define LP_I2C_ANA_MST_I2C_DEVICE_EN_M  (LP_I2C_ANA_MST_I2C_DEVICE_EN_V << LP_I2C_ANA_MST_I2C_DEVICE_EN_S)
-#define LP_I2C_ANA_MST_I2C_DEVICE_EN_V  0x00000FFFU
-#define LP_I2C_ANA_MST_I2C_DEVICE_EN_S  0
-
-/** LP_I2C_ANA_MST_DATE_REG register
- *  need_des
- */
-#define LP_I2C_ANA_MST_DATE_REG (DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc)
-/** LP_I2C_ANA_MST_I2C_MAT_DATE : R/W; bitpos: [27:0]; default: 33583873;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C_MAT_DATE    0x0FFFFFFFU
-#define LP_I2C_ANA_MST_I2C_MAT_DATE_M  (LP_I2C_ANA_MST_I2C_MAT_DATE_V << LP_I2C_ANA_MST_I2C_MAT_DATE_S)
-#define LP_I2C_ANA_MST_I2C_MAT_DATE_V  0x0FFFFFFFU
-#define LP_I2C_ANA_MST_I2C_MAT_DATE_S  0
-/** LP_I2C_ANA_MST_I2C_MAT_CLK_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN    (BIT(28))
-#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_M  (LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V << LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S)
-#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_V  0x00000001U
-#define LP_I2C_ANA_MST_I2C_MAT_CLK_EN_S  28
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_struct.h
deleted file mode 100644
index 37f45487c3..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_i2c_ana_mst_struct.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of i2c0_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
-         *  need_des
-         */
-        uint32_t i2c0_ctrl:25;
-        /** i2c0_busy : RO; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t i2c0_busy:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} lp_i2c_ana_mst_i2c0_ctrl_reg_t;
-
-/** Type of i2c0_conf register
- *  need_des
- */
-typedef union {
-    struct {
-        /** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
-         *  need_des
-         */
-        uint32_t i2c0_conf:24;
-        /** i2c0_status : RO; bitpos: [31:24]; default: 7;
-         *  reserved
-         */
-        uint32_t i2c0_status:8;
-    };
-    uint32_t val;
-} lp_i2c_ana_mst_i2c0_conf_reg_t;
-
-/** Type of i2c0_data register
- *  need_des
- */
-typedef union {
-    struct {
-        /** i2c0_rdata : RO; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t i2c0_rdata:8;
-        /** i2c0_clk_sel : R/W; bitpos: [10:8]; default: 1;
-         *  need_des
-         */
-        uint32_t i2c0_clk_sel:3;
-        /** i2c_mst_sel : R/W; bitpos: [11]; default: 1;
-         *  need  des
-         */
-        uint32_t i2c_mst_sel:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_i2c_ana_mst_i2c0_data_reg_t;
-
-/** Type of ana_conf1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_conf1:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lp_i2c_ana_mst_ana_conf1_reg_t;
-
-/** Type of nouse register
- *  need_des
- */
-typedef union {
-    struct {
-        /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t i2c_mst_nouse:32;
-    };
-    uint32_t val;
-} lp_i2c_ana_mst_nouse_reg_t;
-
-/** Type of device_en register
- *  need_des
- */
-typedef union {
-    struct {
-        /** i2c_device_en : R/W; bitpos: [11:0]; default: 0;
-         *  need_des
-         */
-        uint32_t i2c_device_en:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_i2c_ana_mst_device_en_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** i2c_mat_date : R/W; bitpos: [27:0]; default: 33583873;
-         *  need_des
-         */
-        uint32_t i2c_mat_date:28;
-        /** i2c_mat_clk_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t i2c_mat_clk_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} lp_i2c_ana_mst_date_reg_t;
-
-
-typedef struct lp_i2c_ana_mst_dev_t {
-    volatile lp_i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
-    volatile lp_i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
-    volatile lp_i2c_ana_mst_i2c0_data_reg_t i2c0_data;
-    volatile lp_i2c_ana_mst_ana_conf1_reg_t ana_conf1;
-    volatile lp_i2c_ana_mst_nouse_reg_t nouse;
-    volatile lp_i2c_ana_mst_device_en_reg_t device_en;
-    uint32_t reserved_018[249];
-    volatile lp_i2c_ana_mst_date_reg_t date;
-} lp_i2c_ana_mst_dev_t;
-
-extern lp_i2c_ana_mst_dev_t LP_I2C_ANA_MST;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_i2c_ana_mst_dev_t) == 0x400, "Invalid size of lp_i2c_ana_mst_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_reg.h
deleted file mode 100644
index fc0e24966e..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_i2c_reg.h
+++ /dev/null
@@ -1,1285 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_I2C_SCL_LOW_PERIOD_REG register
- *  Configures the low level width of the SCL
- *  Clock
- */
-#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0)
-/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  Configures the low level width of the SCL Clock.
- *  Measurement unit: i2c_sclk.
- */
-#define LP_I2C_SCL_LOW_PERIOD    0x000001FFU
-#define LP_I2C_SCL_LOW_PERIOD_M  (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S)
-#define LP_I2C_SCL_LOW_PERIOD_V  0x000001FFU
-#define LP_I2C_SCL_LOW_PERIOD_S  0
-
-/** LP_I2C_CTR_REG register
- *  Transmission setting
- */
-#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4)
-/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
- *  Configures the sample mode for SDA.
- *  1: Sample SDA data on the SCL low level.
- *
- *  0: Sample SDA data on the SCL high level.
- */
-#define LP_I2C_SAMPLE_SCL_LEVEL    (BIT(2))
-#define LP_I2C_SAMPLE_SCL_LEVEL_M  (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S)
-#define LP_I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
-#define LP_I2C_SAMPLE_SCL_LEVEL_S  2
-/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
- *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
- *  reached the threshold.
- */
-#define LP_I2C_RX_FULL_ACK_LEVEL    (BIT(3))
-#define LP_I2C_RX_FULL_ACK_LEVEL_M  (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S)
-#define LP_I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
-#define LP_I2C_RX_FULL_ACK_LEVEL_S  3
-/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0;
- *  Configures to start sending the data in txfifo for slave.
- *  0: No effect
- *
- *  1: Start
- */
-#define LP_I2C_TRANS_START    (BIT(5))
-#define LP_I2C_TRANS_START_M  (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S)
-#define LP_I2C_TRANS_START_V  0x00000001U
-#define LP_I2C_TRANS_START_S  5
-/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
- *  Configures to control the sending order for data needing to be sent.
- *  1: send data from the least significant bit,
- *
- *  0: send data from the most significant bit.
- */
-#define LP_I2C_TX_LSB_FIRST    (BIT(6))
-#define LP_I2C_TX_LSB_FIRST_M  (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S)
-#define LP_I2C_TX_LSB_FIRST_V  0x00000001U
-#define LP_I2C_TX_LSB_FIRST_S  6
-/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
- *  Configures to control the storage order for received data.
- *  1: receive data from the least significant bit
- *
- *  0: receive data from the most significant bit.
- */
-#define LP_I2C_RX_LSB_FIRST    (BIT(7))
-#define LP_I2C_RX_LSB_FIRST_M  (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S)
-#define LP_I2C_RX_LSB_FIRST_V  0x00000001U
-#define LP_I2C_RX_LSB_FIRST_S  7
-/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether to gate clock signal for registers.
- *
- *  0: Force clock on for registers
- *
- *  1: Support clock only when registers are read or written to by software.
- */
-#define LP_I2C_CLK_EN    (BIT(8))
-#define LP_I2C_CLK_EN_M  (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S)
-#define LP_I2C_CLK_EN_V  0x00000001U
-#define LP_I2C_CLK_EN_S  8
-/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
- *  Configures to enable I2C bus arbitration detection.
- *  0: No effect
- *
- *  1: Enable
- */
-#define LP_I2C_ARBITRATION_EN    (BIT(9))
-#define LP_I2C_ARBITRATION_EN_M  (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S)
-#define LP_I2C_ARBITRATION_EN_V  0x00000001U
-#define LP_I2C_ARBITRATION_EN_S  9
-/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0;
- *  Configures to reset the SCL_FSM.
- *  0: No effect
- *
- *  1: Reset
- */
-#define LP_I2C_FSM_RST    (BIT(10))
-#define LP_I2C_FSM_RST_M  (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S)
-#define LP_I2C_FSM_RST_V  0x00000001U
-#define LP_I2C_FSM_RST_S  10
-/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
- *  Configures this bit for synchronization
- *  0: No effect
- *
- *  1: Synchronize
- */
-#define LP_I2C_CONF_UPGATE    (BIT(11))
-#define LP_I2C_CONF_UPGATE_M  (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S)
-#define LP_I2C_CONF_UPGATE_V  0x00000001U
-#define LP_I2C_CONF_UPGATE_S  11
-
-/** LP_I2C_SR_REG register
- *  Describe I2C work status.
- */
-#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8)
-/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0;
- *  Represents the received ACK value in master mode or slave mode.
- *  0: ACK,
- *
- *  1: NACK.
- */
-#define LP_I2C_RESP_REC    (BIT(0))
-#define LP_I2C_RESP_REC_M  (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S)
-#define LP_I2C_RESP_REC_V  0x00000001U
-#define LP_I2C_RESP_REC_S  0
-/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
- *  Represents whether the I2C controller loses control of SCL line.
- *  0: No arbitration lost
- *
- *  1: Arbitration lost
- */
-#define LP_I2C_ARB_LOST    (BIT(3))
-#define LP_I2C_ARB_LOST_M  (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S)
-#define LP_I2C_ARB_LOST_V  0x00000001U
-#define LP_I2C_ARB_LOST_S  3
-/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
- *  Represents the I2C bus state.
- *  1: The I2C bus is busy transferring data,
- *
- *  0: The I2C bus is in idle state.
- */
-#define LP_I2C_BUS_BUSY    (BIT(4))
-#define LP_I2C_BUS_BUSY_M  (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S)
-#define LP_I2C_BUS_BUSY_V  0x00000001U
-#define LP_I2C_BUS_BUSY_S  4
-/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0;
- *  Represents the number of data bytes to be sent.
- */
-#define LP_I2C_RXFIFO_CNT    0x0000001FU
-#define LP_I2C_RXFIFO_CNT_M  (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S)
-#define LP_I2C_RXFIFO_CNT_V  0x0000001FU
-#define LP_I2C_RXFIFO_CNT_S  8
-/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0;
- *  Represents the number of data bytes received in RAM.
- */
-#define LP_I2C_TXFIFO_CNT    0x0000001FU
-#define LP_I2C_TXFIFO_CNT_M  (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S)
-#define LP_I2C_TXFIFO_CNT_V  0x0000001FU
-#define LP_I2C_TXFIFO_CNT_S  18
-/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
- *  Represents the states of the I2C module state machine.
- *  0: Idle,
- *
- *  1: Address shift,
- *
- *  2: ACK address,
- *
- *  3: Rx data,
- *
- *  4: Tx data,
- *
- *  5: Send ACK,
- *
- *  6: Wait ACK
- */
-#define LP_I2C_SCL_MAIN_STATE_LAST    0x00000007U
-#define LP_I2C_SCL_MAIN_STATE_LAST_M  (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S)
-#define LP_I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
-#define LP_I2C_SCL_MAIN_STATE_LAST_S  24
-/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
- *  Represents the states of the state machine used to produce SCL.
- *  0: Idle,
- *
- *  1: Start,
- *
- *  2: Negative edge,
- *
- *  3: Low,
- *
- *  4: Positive edge,
- *
- *  5: High,
- *
- *  6: Stop
- */
-#define LP_I2C_SCL_STATE_LAST    0x00000007U
-#define LP_I2C_SCL_STATE_LAST_M  (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S)
-#define LP_I2C_SCL_STATE_LAST_V  0x00000007U
-#define LP_I2C_SCL_STATE_LAST_S  28
-
-/** LP_I2C_TO_REG register
- *  Setting time out control for receiving data.
- */
-#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc)
-/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
- *  Configures the timeout threshold period for SCL stucking at high or low level. The
- *  actual period is 2^(reg_time_out_value).
- *  Measurement unit: i2c_sclk.
- */
-#define LP_I2C_TIME_OUT_VALUE    0x0000001FU
-#define LP_I2C_TIME_OUT_VALUE_M  (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S)
-#define LP_I2C_TIME_OUT_VALUE_V  0x0000001FU
-#define LP_I2C_TIME_OUT_VALUE_S  0
-/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
- *  Configures to enable time out control.
- *  0: No effect
- *
- *  1: Enable
- */
-#define LP_I2C_TIME_OUT_EN    (BIT(5))
-#define LP_I2C_TIME_OUT_EN_M  (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S)
-#define LP_I2C_TIME_OUT_EN_V  0x00000001U
-#define LP_I2C_TIME_OUT_EN_S  5
-
-/** LP_I2C_FIFO_ST_REG register
- *  FIFO status register.
- */
-#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14)
-/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0;
- *  Represents the offset address of the APB reading from RXFIFO
- */
-#define LP_I2C_RXFIFO_RADDR    0x0000000FU
-#define LP_I2C_RXFIFO_RADDR_M  (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S)
-#define LP_I2C_RXFIFO_RADDR_V  0x0000000FU
-#define LP_I2C_RXFIFO_RADDR_S  0
-/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0;
- *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
- */
-#define LP_I2C_RXFIFO_WADDR    0x0000000FU
-#define LP_I2C_RXFIFO_WADDR_M  (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S)
-#define LP_I2C_RXFIFO_WADDR_V  0x0000000FU
-#define LP_I2C_RXFIFO_WADDR_S  5
-/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0;
- *  Represents the offset address of i2c module reading from TXFIFO.
- */
-#define LP_I2C_TXFIFO_RADDR    0x0000000FU
-#define LP_I2C_TXFIFO_RADDR_M  (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S)
-#define LP_I2C_TXFIFO_RADDR_V  0x0000000FU
-#define LP_I2C_TXFIFO_RADDR_S  10
-/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0;
- *  Represents the offset address of APB bus writing to TXFIFO.
- */
-#define LP_I2C_TXFIFO_WADDR    0x0000000FU
-#define LP_I2C_TXFIFO_WADDR_M  (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S)
-#define LP_I2C_TXFIFO_WADDR_V  0x0000000FU
-#define LP_I2C_TXFIFO_WADDR_S  15
-
-/** LP_I2C_FIFO_CONF_REG register
- *  FIFO configuration register.
- */
-#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18)
-/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6;
- *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
- *  reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.
- */
-#define LP_I2C_RXFIFO_WM_THRHD    0x0000000FU
-#define LP_I2C_RXFIFO_WM_THRHD_M  (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S)
-#define LP_I2C_RXFIFO_WM_THRHD_V  0x0000000FU
-#define LP_I2C_RXFIFO_WM_THRHD_S  0
-/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2;
- *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
- *  reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.
- */
-#define LP_I2C_TXFIFO_WM_THRHD    0x0000000FU
-#define LP_I2C_TXFIFO_WM_THRHD_M  (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S)
-#define LP_I2C_TXFIFO_WM_THRHD_V  0x0000000FU
-#define LP_I2C_TXFIFO_WM_THRHD_S  5
-/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
- *  Configures to enable APB nonfifo access.
- */
-#define LP_I2C_NONFIFO_EN    (BIT(10))
-#define LP_I2C_NONFIFO_EN_M  (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S)
-#define LP_I2C_NONFIFO_EN_V  0x00000001U
-#define LP_I2C_NONFIFO_EN_S  10
-/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
- *  Configures to reset RXFIFO.
- *  0: No effect
- *
- *  1: Reset
- */
-#define LP_I2C_RX_FIFO_RST    (BIT(12))
-#define LP_I2C_RX_FIFO_RST_M  (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S)
-#define LP_I2C_RX_FIFO_RST_V  0x00000001U
-#define LP_I2C_RX_FIFO_RST_S  12
-/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
- *  Configures to reset TXFIFO.
- *  0: No effect
- *
- *  1: Reset
- */
-#define LP_I2C_TX_FIFO_RST    (BIT(13))
-#define LP_I2C_TX_FIFO_RST_M  (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S)
-#define LP_I2C_TX_FIFO_RST_V  0x00000001U
-#define LP_I2C_TX_FIFO_RST_S  13
-/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
- *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
- *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
- *  0: No effect
- *
- *  1: Enable
- */
-#define LP_I2C_FIFO_PRT_EN    (BIT(14))
-#define LP_I2C_FIFO_PRT_EN_M  (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S)
-#define LP_I2C_FIFO_PRT_EN_V  0x00000001U
-#define LP_I2C_FIFO_PRT_EN_S  14
-
-/** LP_I2C_DATA_REG register
- *  Rx FIFO read data.
- */
-#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c)
-/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0;
- *  Represents the value of RXFIFO read data.
- */
-#define LP_I2C_FIFO_RDATA    0x000000FFU
-#define LP_I2C_FIFO_RDATA_M  (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S)
-#define LP_I2C_FIFO_RDATA_V  0x000000FFU
-#define LP_I2C_FIFO_RDATA_S  0
-
-/** LP_I2C_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20)
-/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_RXFIFO_WM_INT_RAW    (BIT(0))
-#define LP_I2C_RXFIFO_WM_INT_RAW_M  (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S)
-#define LP_I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
-#define LP_I2C_RXFIFO_WM_INT_RAW_S  0
-/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
- *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_TXFIFO_WM_INT_RAW    (BIT(1))
-#define LP_I2C_TXFIFO_WM_INT_RAW_M  (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S)
-#define LP_I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
-#define LP_I2C_TXFIFO_WM_INT_RAW_S  1
-/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
-#define LP_I2C_RXFIFO_OVF_INT_RAW_M  (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S)
-#define LP_I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define LP_I2C_RXFIFO_OVF_INT_RAW_S  2
-/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
- *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_END_DETECT_INT_RAW    (BIT(3))
-#define LP_I2C_END_DETECT_INT_RAW_M  (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S)
-#define LP_I2C_END_DETECT_INT_RAW_V  0x00000001U
-#define LP_I2C_END_DETECT_INT_RAW_S  3
-/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
- *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
-#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M  (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S)
-#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
-#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S  4
-/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
- *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define LP_I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
-#define LP_I2C_ARBITRATION_LOST_INT_RAW_M  (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S)
-#define LP_I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
-#define LP_I2C_ARBITRATION_LOST_INT_RAW_S  5
-/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
- *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
-#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M  (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S)
-#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
-#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S  6
-/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
- *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
-#define LP_I2C_TRANS_COMPLETE_INT_RAW_M  (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S)
-#define LP_I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
-#define LP_I2C_TRANS_COMPLETE_INT_RAW_S  7
-/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
- *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
- */
-#define LP_I2C_TIME_OUT_INT_RAW    (BIT(8))
-#define LP_I2C_TIME_OUT_INT_RAW_M  (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S)
-#define LP_I2C_TIME_OUT_INT_RAW_V  0x00000001U
-#define LP_I2C_TIME_OUT_INT_RAW_S  8
-/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
- *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
- */
-#define LP_I2C_TRANS_START_INT_RAW    (BIT(9))
-#define LP_I2C_TRANS_START_INT_RAW_M  (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S)
-#define LP_I2C_TRANS_START_INT_RAW_V  0x00000001U
-#define LP_I2C_TRANS_START_INT_RAW_S  9
-/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
- *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define LP_I2C_NACK_INT_RAW    (BIT(10))
-#define LP_I2C_NACK_INT_RAW_M  (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S)
-#define LP_I2C_NACK_INT_RAW_V  0x00000001U
-#define LP_I2C_NACK_INT_RAW_S  10
-/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
- *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
-#define LP_I2C_TXFIFO_OVF_INT_RAW_M  (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S)
-#define LP_I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
-#define LP_I2C_TXFIFO_OVF_INT_RAW_S  11
-/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
- *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define LP_I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
-#define LP_I2C_RXFIFO_UDF_INT_RAW_M  (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S)
-#define LP_I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
-#define LP_I2C_RXFIFO_UDF_INT_RAW_S  12
-/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
- *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_ST_TO_INT_RAW    (BIT(13))
-#define LP_I2C_SCL_ST_TO_INT_RAW_M  (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S)
-#define LP_I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
-#define LP_I2C_SCL_ST_TO_INT_RAW_S  13
-/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
- *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
-#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M  (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S)
-#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
-#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
-/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
- *  The raw interrupt status of I2C_DET_START_INT interrupt.
- */
-#define LP_I2C_DET_START_INT_RAW    (BIT(15))
-#define LP_I2C_DET_START_INT_RAW_M  (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S)
-#define LP_I2C_DET_START_INT_RAW_V  0x00000001U
-#define LP_I2C_DET_START_INT_RAW_S  15
-
-/** LP_I2C_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24)
-/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_RXFIFO_WM_INT_CLR    (BIT(0))
-#define LP_I2C_RXFIFO_WM_INT_CLR_M  (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S)
-#define LP_I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
-#define LP_I2C_RXFIFO_WM_INT_CLR_S  0
-/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_TXFIFO_WM_INT_CLR    (BIT(1))
-#define LP_I2C_TXFIFO_WM_INT_CLR_M  (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S)
-#define LP_I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
-#define LP_I2C_TXFIFO_WM_INT_CLR_S  1
-/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
-#define LP_I2C_RXFIFO_OVF_INT_CLR_M  (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S)
-#define LP_I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define LP_I2C_RXFIFO_OVF_INT_CLR_S  2
-/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_END_DETECT_INT_CLR    (BIT(3))
-#define LP_I2C_END_DETECT_INT_CLR_M  (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S)
-#define LP_I2C_END_DETECT_INT_CLR_V  0x00000001U
-#define LP_I2C_END_DETECT_INT_CLR_S  3
-/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
-#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M  (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S)
-#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
-#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S  4
-/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define LP_I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
-#define LP_I2C_ARBITRATION_LOST_INT_CLR_M  (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S)
-#define LP_I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
-#define LP_I2C_ARBITRATION_LOST_INT_CLR_S  5
-/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
-#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M  (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S)
-#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
-#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S  6
-/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
-#define LP_I2C_TRANS_COMPLETE_INT_CLR_M  (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S)
-#define LP_I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
-#define LP_I2C_TRANS_COMPLETE_INT_CLR_S  7
-/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
- */
-#define LP_I2C_TIME_OUT_INT_CLR    (BIT(8))
-#define LP_I2C_TIME_OUT_INT_CLR_M  (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S)
-#define LP_I2C_TIME_OUT_INT_CLR_V  0x00000001U
-#define LP_I2C_TIME_OUT_INT_CLR_S  8
-/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
- */
-#define LP_I2C_TRANS_START_INT_CLR    (BIT(9))
-#define LP_I2C_TRANS_START_INT_CLR_M  (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S)
-#define LP_I2C_TRANS_START_INT_CLR_V  0x00000001U
-#define LP_I2C_TRANS_START_INT_CLR_S  9
-/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define LP_I2C_NACK_INT_CLR    (BIT(10))
-#define LP_I2C_NACK_INT_CLR_M  (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S)
-#define LP_I2C_NACK_INT_CLR_V  0x00000001U
-#define LP_I2C_NACK_INT_CLR_S  10
-/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
-#define LP_I2C_TXFIFO_OVF_INT_CLR_M  (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S)
-#define LP_I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
-#define LP_I2C_TXFIFO_OVF_INT_CLR_S  11
-/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define LP_I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
-#define LP_I2C_RXFIFO_UDF_INT_CLR_M  (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S)
-#define LP_I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
-#define LP_I2C_RXFIFO_UDF_INT_CLR_S  12
-/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_ST_TO_INT_CLR    (BIT(13))
-#define LP_I2C_SCL_ST_TO_INT_CLR_M  (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S)
-#define LP_I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
-#define LP_I2C_SCL_ST_TO_INT_CLR_S  13
-/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
-#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M  (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S)
-#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
-#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
-/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Write 1 to clear I2C_DET_START_INT interrupt.
- */
-#define LP_I2C_DET_START_INT_CLR    (BIT(15))
-#define LP_I2C_DET_START_INT_CLR_M  (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S)
-#define LP_I2C_DET_START_INT_CLR_V  0x00000001U
-#define LP_I2C_DET_START_INT_CLR_S  15
-
-/** LP_I2C_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28)
-/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to anable I2C_RXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_RXFIFO_WM_INT_ENA    (BIT(0))
-#define LP_I2C_RXFIFO_WM_INT_ENA_M  (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S)
-#define LP_I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
-#define LP_I2C_RXFIFO_WM_INT_ENA_S  0
-/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to anable I2C_TXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_TXFIFO_WM_INT_ENA    (BIT(1))
-#define LP_I2C_TXFIFO_WM_INT_ENA_M  (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S)
-#define LP_I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
-#define LP_I2C_TXFIFO_WM_INT_ENA_S  1
-/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to anable I2C_RXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
-#define LP_I2C_RXFIFO_OVF_INT_ENA_M  (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S)
-#define LP_I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define LP_I2C_RXFIFO_OVF_INT_ENA_S  2
-/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to anable the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_END_DETECT_INT_ENA    (BIT(3))
-#define LP_I2C_END_DETECT_INT_ENA_M  (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S)
-#define LP_I2C_END_DETECT_INT_ENA_V  0x00000001U
-#define LP_I2C_END_DETECT_INT_ENA_S  3
-/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Write 1 to anable the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
-#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M  (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S)
-#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
-#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S  4
-/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define LP_I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
-#define LP_I2C_ARBITRATION_LOST_INT_ENA_M  (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S)
-#define LP_I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
-#define LP_I2C_ARBITRATION_LOST_INT_ENA_S  5
-/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
-#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M  (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S)
-#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
-#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S  6
-/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
-#define LP_I2C_TRANS_COMPLETE_INT_ENA_M  (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S)
-#define LP_I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
-#define LP_I2C_TRANS_COMPLETE_INT_ENA_S  7
-/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Write 1 to anable the I2C_TIME_OUT_INT interrupt.
- */
-#define LP_I2C_TIME_OUT_INT_ENA    (BIT(8))
-#define LP_I2C_TIME_OUT_INT_ENA_M  (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S)
-#define LP_I2C_TIME_OUT_INT_ENA_V  0x00000001U
-#define LP_I2C_TIME_OUT_INT_ENA_S  8
-/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Write 1 to anable the I2C_TRANS_START_INT interrupt.
- */
-#define LP_I2C_TRANS_START_INT_ENA    (BIT(9))
-#define LP_I2C_TRANS_START_INT_ENA_M  (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S)
-#define LP_I2C_TRANS_START_INT_ENA_V  0x00000001U
-#define LP_I2C_TRANS_START_INT_ENA_S  9
-/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define LP_I2C_NACK_INT_ENA    (BIT(10))
-#define LP_I2C_NACK_INT_ENA_M  (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S)
-#define LP_I2C_NACK_INT_ENA_V  0x00000001U
-#define LP_I2C_NACK_INT_ENA_S  10
-/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Write 1 to anable I2C_TXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
-#define LP_I2C_TXFIFO_OVF_INT_ENA_M  (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S)
-#define LP_I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
-#define LP_I2C_TXFIFO_OVF_INT_ENA_S  11
-/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Write 1 to anable I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define LP_I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
-#define LP_I2C_RXFIFO_UDF_INT_ENA_M  (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S)
-#define LP_I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
-#define LP_I2C_RXFIFO_UDF_INT_ENA_S  12
-/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Write 1 to anable I2C_SCL_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_ST_TO_INT_ENA    (BIT(13))
-#define LP_I2C_SCL_ST_TO_INT_ENA_M  (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S)
-#define LP_I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
-#define LP_I2C_SCL_ST_TO_INT_ENA_S  13
-/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M  (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S)
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
-/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  Write 1 to anable I2C_DET_START_INT interrupt.
- */
-#define LP_I2C_DET_START_INT_ENA    (BIT(15))
-#define LP_I2C_DET_START_INT_ENA_M  (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S)
-#define LP_I2C_DET_START_INT_ENA_V  0x00000001U
-#define LP_I2C_DET_START_INT_ENA_S  15
-
-/** LP_I2C_INT_STATUS_REG register
- *  Status of captured I2C communication events
- */
-#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c)
-/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_RXFIFO_WM_INT_ST    (BIT(0))
-#define LP_I2C_RXFIFO_WM_INT_ST_M  (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S)
-#define LP_I2C_RXFIFO_WM_INT_ST_V  0x00000001U
-#define LP_I2C_RXFIFO_WM_INT_ST_S  0
-/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
- */
-#define LP_I2C_TXFIFO_WM_INT_ST    (BIT(1))
-#define LP_I2C_TXFIFO_WM_INT_ST_M  (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S)
-#define LP_I2C_TXFIFO_WM_INT_ST_V  0x00000001U
-#define LP_I2C_TXFIFO_WM_INT_ST_S  1
-/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_RXFIFO_OVF_INT_ST    (BIT(2))
-#define LP_I2C_RXFIFO_OVF_INT_ST_M  (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S)
-#define LP_I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define LP_I2C_RXFIFO_OVF_INT_ST_S  2
-/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_END_DETECT_INT_ST    (BIT(3))
-#define LP_I2C_END_DETECT_INT_ST_M  (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S)
-#define LP_I2C_END_DETECT_INT_ST_V  0x00000001U
-#define LP_I2C_END_DETECT_INT_ST_S  3
-/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
- */
-#define LP_I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
-#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M  (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S)
-#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
-#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S  4
-/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define LP_I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
-#define LP_I2C_ARBITRATION_LOST_INT_ST_M  (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S)
-#define LP_I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
-#define LP_I2C_ARBITRATION_LOST_INT_ST_S  5
-/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
-#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M  (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S)
-#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
-#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S  6
-/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define LP_I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
-#define LP_I2C_TRANS_COMPLETE_INT_ST_M  (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S)
-#define LP_I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
-#define LP_I2C_TRANS_COMPLETE_INT_ST_S  7
-/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
- */
-#define LP_I2C_TIME_OUT_INT_ST    (BIT(8))
-#define LP_I2C_TIME_OUT_INT_ST_M  (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S)
-#define LP_I2C_TIME_OUT_INT_ST_V  0x00000001U
-#define LP_I2C_TIME_OUT_INT_ST_S  8
-/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
- */
-#define LP_I2C_TRANS_START_INT_ST    (BIT(9))
-#define LP_I2C_TRANS_START_INT_ST_M  (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S)
-#define LP_I2C_TRANS_START_INT_ST_V  0x00000001U
-#define LP_I2C_TRANS_START_INT_ST_S  9
-/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define LP_I2C_NACK_INT_ST    (BIT(10))
-#define LP_I2C_NACK_INT_ST_M  (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S)
-#define LP_I2C_NACK_INT_ST_V  0x00000001U
-#define LP_I2C_NACK_INT_ST_S  10
-/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
- */
-#define LP_I2C_TXFIFO_OVF_INT_ST    (BIT(11))
-#define LP_I2C_TXFIFO_OVF_INT_ST_M  (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S)
-#define LP_I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
-#define LP_I2C_TXFIFO_OVF_INT_ST_S  11
-/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define LP_I2C_RXFIFO_UDF_INT_ST    (BIT(12))
-#define LP_I2C_RXFIFO_UDF_INT_ST_M  (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S)
-#define LP_I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
-#define LP_I2C_RXFIFO_UDF_INT_ST_S  12
-/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_ST_TO_INT_ST    (BIT(13))
-#define LP_I2C_SCL_ST_TO_INT_ST_M  (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S)
-#define LP_I2C_SCL_ST_TO_INT_ST_V  0x00000001U
-#define LP_I2C_SCL_ST_TO_INT_ST_S  13
-/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
- *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M  (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S)
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
-#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S  14
-/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  The masked interrupt status status of I2C_DET_START_INT interrupt.
- */
-#define LP_I2C_DET_START_INT_ST    (BIT(15))
-#define LP_I2C_DET_START_INT_ST_M  (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S)
-#define LP_I2C_DET_START_INT_ST_V  0x00000001U
-#define LP_I2C_DET_START_INT_ST_S  15
-
-/** LP_I2C_SDA_HOLD_REG register
- *  Configures the hold time after a negative SCL edge.
- */
-#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30)
-/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
- *  Configures the time to hold the data after the falling edge of SCL.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SDA_HOLD_TIME    0x000001FFU
-#define LP_I2C_SDA_HOLD_TIME_M  (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S)
-#define LP_I2C_SDA_HOLD_TIME_V  0x000001FFU
-#define LP_I2C_SDA_HOLD_TIME_S  0
-
-/** LP_I2C_SDA_SAMPLE_REG register
- *  Configures the sample time after a positive SCL edge.
- */
-#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34)
-/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
- *  Configures the sample time after a positive SCL edge.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SDA_SAMPLE_TIME    0x000001FFU
-#define LP_I2C_SDA_SAMPLE_TIME_M  (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S)
-#define LP_I2C_SDA_SAMPLE_TIME_V  0x000001FFU
-#define LP_I2C_SDA_SAMPLE_TIME_S  0
-
-/** LP_I2C_SCL_HIGH_PERIOD_REG register
- *  Configures the high level width of SCL
- */
-#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38)
-/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  Configures for how long SCL remains high in master mode.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_HIGH_PERIOD    0x000001FFU
-#define LP_I2C_SCL_HIGH_PERIOD_M  (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S)
-#define LP_I2C_SCL_HIGH_PERIOD_V  0x000001FFU
-#define LP_I2C_SCL_HIGH_PERIOD_S  0
-/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
- *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
-#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M  (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S)
-#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
-#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S  9
-
-/** LP_I2C_SCL_START_HOLD_REG register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40)
-/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the falling edge of SDA and the falling edge of SCL for
- *  a START condition.
- *  Measurement unit: i2c_sclk.
- */
-#define LP_I2C_SCL_START_HOLD_TIME    0x000001FFU
-#define LP_I2C_SCL_START_HOLD_TIME_M  (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S)
-#define LP_I2C_SCL_START_HOLD_TIME_V  0x000001FFU
-#define LP_I2C_SCL_START_HOLD_TIME_S  0
-
-/** LP_I2C_SCL_RSTART_SETUP_REG register
- *  Configures the delay between the positive
- *  edge of SCL and the negative edge of SDA
- */
-#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44)
-/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the positive edge of SCL and the negative edge of SDA
- *  for a RESTART condition.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
-#define LP_I2C_SCL_RSTART_SETUP_TIME_M  (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S)
-#define LP_I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
-#define LP_I2C_SCL_RSTART_SETUP_TIME_S  0
-
-/** LP_I2C_SCL_STOP_HOLD_REG register
- *  Configures the delay after the SCL clock
- *  edge for a stop condition
- */
-#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48)
-/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the delay after the STOP condition.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_STOP_HOLD_TIME    0x000001FFU
-#define LP_I2C_SCL_STOP_HOLD_TIME_M  (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S)
-#define LP_I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
-#define LP_I2C_SCL_STOP_HOLD_TIME_S  0
-
-/** LP_I2C_SCL_STOP_SETUP_REG register
- *  Configures the delay between the SDA and
- *  SCL positive edge for a stop condition
- */
-#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c)
-/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  Configures the time between the rising edge of SCL and the rising edge of SDA.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_STOP_SETUP_TIME    0x000001FFU
-#define LP_I2C_SCL_STOP_SETUP_TIME_M  (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S)
-#define LP_I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
-#define LP_I2C_SCL_STOP_SETUP_TIME_S  0
-
-/** LP_I2C_FILTER_CFG_REG register
- *  SCL and SDA filter configuration register
- */
-#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50)
-/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
- *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
- *  input has smaller width than this register value, the I2C controller will ignore
- *  that pulse.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_FILTER_THRES    0x0000000FU
-#define LP_I2C_SCL_FILTER_THRES_M  (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S)
-#define LP_I2C_SCL_FILTER_THRES_V  0x0000000FU
-#define LP_I2C_SCL_FILTER_THRES_S  0
-/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
- *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
- *  input has smaller width than this register value, the I2C controller will ignore
- *  that pulse.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SDA_FILTER_THRES    0x0000000FU
-#define LP_I2C_SDA_FILTER_THRES_M  (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S)
-#define LP_I2C_SDA_FILTER_THRES_V  0x0000000FU
-#define LP_I2C_SDA_FILTER_THRES_S  4
-/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
- *  Configures to enable the filter function for SCL.
- */
-#define LP_I2C_SCL_FILTER_EN    (BIT(8))
-#define LP_I2C_SCL_FILTER_EN_M  (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S)
-#define LP_I2C_SCL_FILTER_EN_V  0x00000001U
-#define LP_I2C_SCL_FILTER_EN_S  8
-/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
- *  Configures to enable the filter function for SDA.
- */
-#define LP_I2C_SDA_FILTER_EN    (BIT(9))
-#define LP_I2C_SDA_FILTER_EN_M  (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S)
-#define LP_I2C_SDA_FILTER_EN_V  0x00000001U
-#define LP_I2C_SDA_FILTER_EN_S  9
-
-/** LP_I2C_CLK_CONF_REG register
- *  I2C CLK configuration register
- */
-#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54)
-/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  the integral part of the fractional divisor for i2c module
- */
-#define LP_I2C_SCLK_DIV_NUM    0x000000FFU
-#define LP_I2C_SCLK_DIV_NUM_M  (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S)
-#define LP_I2C_SCLK_DIV_NUM_V  0x000000FFU
-#define LP_I2C_SCLK_DIV_NUM_S  0
-/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0;
- *  the numerator of the fractional part of the fractional divisor for i2c module
- */
-#define LP_I2C_SCLK_DIV_A    0x0000003FU
-#define LP_I2C_SCLK_DIV_A_M  (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S)
-#define LP_I2C_SCLK_DIV_A_V  0x0000003FU
-#define LP_I2C_SCLK_DIV_A_S  8
-/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0;
- *  the denominator of the fractional part of the fractional divisor for i2c module
- */
-#define LP_I2C_SCLK_DIV_B    0x0000003FU
-#define LP_I2C_SCLK_DIV_B_M  (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S)
-#define LP_I2C_SCLK_DIV_B_V  0x0000003FU
-#define LP_I2C_SCLK_DIV_B_S  14
-/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
- *  The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
- */
-#define LP_I2C_SCLK_SEL    (BIT(20))
-#define LP_I2C_SCLK_SEL_M  (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S)
-#define LP_I2C_SCLK_SEL_V  0x00000001U
-#define LP_I2C_SCLK_SEL_S  20
-/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1;
- *  The clock switch for i2c module
- */
-#define LP_I2C_SCLK_ACTIVE    (BIT(21))
-#define LP_I2C_SCLK_ACTIVE_M  (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S)
-#define LP_I2C_SCLK_ACTIVE_V  0x00000001U
-#define LP_I2C_SCLK_ACTIVE_S  21
-
-/** LP_I2C_COMD0_REG register
- *  I2C command register 0
- */
-#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58)
-/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 0. It consists of three parts:
- *  op_code is the command,
- *  0: RSTART,
- *  1: WRITE,
- *  2: READ,
- *  3: STOP,
- *  4: END.
- *
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more information.
- */
-#define LP_I2C_COMMAND0    0x00003FFFU
-#define LP_I2C_COMMAND0_M  (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S)
-#define LP_I2C_COMMAND0_V  0x00003FFFU
-#define LP_I2C_COMMAND0_S  0
-/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 0 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND0_DONE    (BIT(31))
-#define LP_I2C_COMMAND0_DONE_M  (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S)
-#define LP_I2C_COMMAND0_DONE_V  0x00000001U
-#define LP_I2C_COMMAND0_DONE_S  31
-
-/** LP_I2C_COMD1_REG register
- *  I2C command register 1
- */
-#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c)
-/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 1. See details in I2C_CMD0_REG[13:0].
- */
-#define LP_I2C_COMMAND1    0x00003FFFU
-#define LP_I2C_COMMAND1_M  (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S)
-#define LP_I2C_COMMAND1_V  0x00003FFFU
-#define LP_I2C_COMMAND1_S  0
-/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 1 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND1_DONE    (BIT(31))
-#define LP_I2C_COMMAND1_DONE_M  (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S)
-#define LP_I2C_COMMAND1_DONE_V  0x00000001U
-#define LP_I2C_COMMAND1_DONE_S  31
-
-/** LP_I2C_COMD2_REG register
- *  I2C command register 2
- */
-#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60)
-/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 2. See details in I2C_CMD0_REG[13:0].
- */
-#define LP_I2C_COMMAND2    0x00003FFFU
-#define LP_I2C_COMMAND2_M  (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S)
-#define LP_I2C_COMMAND2_V  0x00003FFFU
-#define LP_I2C_COMMAND2_S  0
-/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 2 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND2_DONE    (BIT(31))
-#define LP_I2C_COMMAND2_DONE_M  (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S)
-#define LP_I2C_COMMAND2_DONE_V  0x00000001U
-#define LP_I2C_COMMAND2_DONE_S  31
-
-/** LP_I2C_COMD3_REG register
- *  I2C command register 3
- */
-#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64)
-/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 3. See details in I2C_CMD0_REG[13:0].
- */
-#define LP_I2C_COMMAND3    0x00003FFFU
-#define LP_I2C_COMMAND3_M  (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S)
-#define LP_I2C_COMMAND3_V  0x00003FFFU
-#define LP_I2C_COMMAND3_S  0
-/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 3 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND3_DONE    (BIT(31))
-#define LP_I2C_COMMAND3_DONE_M  (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S)
-#define LP_I2C_COMMAND3_DONE_V  0x00000001U
-#define LP_I2C_COMMAND3_DONE_S  31
-
-/** LP_I2C_COMD4_REG register
- *  I2C command register 4
- */
-#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68)
-/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 4. See details in I2C_CMD0_REG[13:0].
- */
-#define LP_I2C_COMMAND4    0x00003FFFU
-#define LP_I2C_COMMAND4_M  (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S)
-#define LP_I2C_COMMAND4_V  0x00003FFFU
-#define LP_I2C_COMMAND4_S  0
-/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 4 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND4_DONE    (BIT(31))
-#define LP_I2C_COMMAND4_DONE_M  (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S)
-#define LP_I2C_COMMAND4_DONE_V  0x00000001U
-#define LP_I2C_COMMAND4_DONE_S  31
-
-/** LP_I2C_COMD5_REG register
- *  I2C command register 5
- */
-#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c)
-/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 5. See details in I2C_CMD0_REG[13:0].
- */
-#define LP_I2C_COMMAND5    0x00003FFFU
-#define LP_I2C_COMMAND5_M  (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S)
-#define LP_I2C_COMMAND5_V  0x00003FFFU
-#define LP_I2C_COMMAND5_S  0
-/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 5 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND5_DONE    (BIT(31))
-#define LP_I2C_COMMAND5_DONE_M  (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S)
-#define LP_I2C_COMMAND5_DONE_V  0x00000001U
-#define LP_I2C_COMMAND5_DONE_S  31
-
-/** LP_I2C_COMD6_REG register
- *  I2C command register 6
- */
-#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70)
-/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 6. See details in I2C_CMD0_REG[13:0].
- */
-#define LP_I2C_COMMAND6    0x00003FFFU
-#define LP_I2C_COMMAND6_M  (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S)
-#define LP_I2C_COMMAND6_V  0x00003FFFU
-#define LP_I2C_COMMAND6_S  0
-/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 6 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND6_DONE    (BIT(31))
-#define LP_I2C_COMMAND6_DONE_M  (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S)
-#define LP_I2C_COMMAND6_DONE_V  0x00000001U
-#define LP_I2C_COMMAND6_DONE_S  31
-
-/** LP_I2C_COMD7_REG register
- *  I2C command register 7
- */
-#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74)
-/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
- *  Configures command 7. See details in I2C_CMD0_REG[13:0].
- */
-#define LP_I2C_COMMAND7    0x00003FFFU
-#define LP_I2C_COMMAND7_M  (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S)
-#define LP_I2C_COMMAND7_V  0x00003FFFU
-#define LP_I2C_COMMAND7_S  0
-/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  Represents whether command 7 is done in I2C Master mode.
- *  0: Not done
- *
- *  1: Done
- */
-#define LP_I2C_COMMAND7_DONE    (BIT(31))
-#define LP_I2C_COMMAND7_DONE_M  (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S)
-#define LP_I2C_COMMAND7_DONE_V  0x00000001U
-#define LP_I2C_COMMAND7_DONE_S  31
-
-/** LP_I2C_SCL_ST_TIME_OUT_REG register
- *  SCL status time out register
- */
-#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78)
-/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
- *  more than 23.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_ST_TO_I2C    0x0000001FU
-#define LP_I2C_SCL_ST_TO_I2C_M  (LP_I2C_SCL_ST_TO_I2C_V << LP_I2C_SCL_ST_TO_I2C_S)
-#define LP_I2C_SCL_ST_TO_I2C_V  0x0000001FU
-#define LP_I2C_SCL_ST_TO_I2C_S  0
-
-/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register
- *  SCL main status time out register
- */
-#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c)
-/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
- *  no more than 23.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
-#define LP_I2C_SCL_MAIN_ST_TO_I2C_M  (LP_I2C_SCL_MAIN_ST_TO_I2C_V << LP_I2C_SCL_MAIN_ST_TO_I2C_S)
-#define LP_I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
-#define LP_I2C_SCL_MAIN_ST_TO_I2C_S  0
-
-/** LP_I2C_SCL_SP_CONF_REG register
- *  Power configuration register
- */
-#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80)
-/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
- *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
- *  equals to reg_scl_rst_slv_num[4:0].
- */
-#define LP_I2C_SCL_RST_SLV_EN    (BIT(0))
-#define LP_I2C_SCL_RST_SLV_EN_M  (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S)
-#define LP_I2C_SCL_RST_SLV_EN_V  0x00000001U
-#define LP_I2C_SCL_RST_SLV_EN_S  0
-/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
- *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
- *  equals to reg_scl_rst_slv_num[4:0].
- */
-#define LP_I2C_SCL_RST_SLV_NUM    0x0000001FU
-#define LP_I2C_SCL_RST_SLV_NUM_M  (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S)
-#define LP_I2C_SCL_RST_SLV_NUM_V  0x0000001FU
-#define LP_I2C_SCL_RST_SLV_NUM_S  1
-/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
- *  Configure the pulses of SCL generated in I2C master mode.
- *  Valid when reg_scl_rst_slv_en is 1.
- *  Measurement unit: i2c_sclk
- */
-#define LP_I2C_SCL_PD_EN    (BIT(6))
-#define LP_I2C_SCL_PD_EN_M  (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S)
-#define LP_I2C_SCL_PD_EN_V  0x00000001U
-#define LP_I2C_SCL_PD_EN_S  6
-/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
- *  Configures to power down the I2C output SCL line.
- *  0: Not power down.
- *
- *  1: Power down.
- *  Valid only when reg_scl_force_out is 1.
- */
-#define LP_I2C_SDA_PD_EN    (BIT(7))
-#define LP_I2C_SDA_PD_EN_M  (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S)
-#define LP_I2C_SDA_PD_EN_V  0x00000001U
-#define LP_I2C_SDA_PD_EN_S  7
-
-/** LP_I2C_DATE_REG register
- *  Version register
- */
-#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8)
-/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 35656003;
- *  Version control register.
- */
-#define LP_I2C_DATE    0xFFFFFFFFU
-#define LP_I2C_DATE_M  (LP_I2C_DATE_V << LP_I2C_DATE_S)
-#define LP_I2C_DATE_V  0xFFFFFFFFU
-#define LP_I2C_DATE_S  0
-
-/** LP_I2C_TXFIFO_START_ADDR_REG register
- *  I2C TXFIFO base address register
- */
-#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100)
-/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Represents the I2C txfifo first address.
- */
-#define LP_I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
-#define LP_I2C_TXFIFO_START_ADDR_M  (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S)
-#define LP_I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define LP_I2C_TXFIFO_START_ADDR_S  0
-
-/** LP_I2C_RXFIFO_START_ADDR_REG register
- *  I2C RXFIFO base address register
- */
-#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180)
-/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Represents the I2C rxfifo first address.
- */
-#define LP_I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
-#define LP_I2C_RXFIFO_START_ADDR_M  (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S)
-#define LP_I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define LP_I2C_RXFIFO_START_ADDR_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_i2c_struct.h
deleted file mode 100644
index ad31d58286..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_i2c_struct.h
+++ /dev/null
@@ -1,963 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Timing registers */
-/** Type of scl_low_period register
- *  Configures the low level width of the SCL
- *  Clock
- */
-typedef union {
-    struct {
-        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the low level width of the SCL Clock.
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t scl_low_period:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_i2c_scl_low_period_reg_t;
-
-/** Type of sda_hold register
- *  Configures the hold time after a negative SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the time to hold the data after the falling edge of SCL.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_i2c_sda_hold_reg_t;
-
-/** Type of sda_sample register
- *  Configures the sample time after a positive SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
-         *  Configures the sample time after a positive SCL edge.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_sample_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_i2c_sda_sample_reg_t;
-
-/** Type of scl_high_period register
- *  Configures the high level width of SCL
- */
-typedef union {
-    struct {
-        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
-         *  Configures for how long SCL remains high in master mode.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_high_period:9;
-        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
-         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_wait_high_period:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_i2c_scl_high_period_reg_t;
-
-/** Type of scl_start_hold register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-typedef union {
-    struct {
-        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
-         *  a START condition.
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t scl_start_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_i2c_scl_start_hold_reg_t;
-
-/** Type of scl_rstart_setup register
- *  Configures the delay between the positive
- *  edge of SCL and the negative edge of SDA
- */
-typedef union {
-    struct {
-        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the positive edge of SCL and the negative edge of SDA
-         *  for a RESTART condition.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_rstart_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_i2c_scl_rstart_setup_reg_t;
-
-/** Type of scl_stop_hold register
- *  Configures the delay after the SCL clock
- *  edge for a stop condition
- */
-typedef union {
-    struct {
-        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the delay after the STOP condition.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_stop_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_i2c_scl_stop_hold_reg_t;
-
-/** Type of scl_stop_setup register
- *  Configures the delay between the SDA and
- *  SCL positive edge for a stop condition
- */
-typedef union {
-    struct {
-        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  Configures the time between the rising edge of SCL and the rising edge of SDA.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_stop_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_i2c_scl_stop_setup_reg_t;
-
-/** Type of scl_st_time_out register
- *  SCL status time out register
- */
-typedef union {
-    struct {
-        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
-         *  more than 23.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lp_i2c_scl_st_time_out_reg_t;
-
-/** Type of scl_main_st_time_out register
- *  SCL main status time out register
- */
-typedef union {
-    struct {
-        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
-         *  no more than 23.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_main_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lp_i2c_scl_main_st_time_out_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of ctr register
- *  Transmission setting
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
-         *  Configures the sample mode for SDA.
-         *  1: Sample SDA data on the SCL low level.
-         *
-         *  0: Sample SDA data on the SCL high level.
-         */
-        uint32_t sample_scl_level:1;
-        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
-         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
-         *  reached the threshold.
-         */
-        uint32_t rx_full_ack_level:1;
-        uint32_t reserved_4:1;
-        /** trans_start : WT; bitpos: [5]; default: 0;
-         *  Configures to start sending the data in txfifo for slave.
-         *  0: No effect
-         *
-         *  1: Start
-         */
-        uint32_t trans_start:1;
-        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
-         *  Configures to control the sending order for data needing to be sent.
-         *  1: send data from the least significant bit,
-         *
-         *  0: send data from the most significant bit.
-         */
-        uint32_t tx_lsb_first:1;
-        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
-         *  Configures to control the storage order for received data.
-         *  1: receive data from the least significant bit
-         *
-         *  0: receive data from the most significant bit.
-         */
-        uint32_t rx_lsb_first:1;
-        /** clk_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether to gate clock signal for registers.
-         *
-         *  0: Force clock on for registers
-         *
-         *  1: Support clock only when registers are read or written to by software.
-         */
-        uint32_t clk_en:1;
-        /** arbitration_en : R/W; bitpos: [9]; default: 1;
-         *  Configures to enable I2C bus arbitration detection.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t arbitration_en:1;
-        /** fsm_rst : WT; bitpos: [10]; default: 0;
-         *  Configures to reset the SCL_FSM.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t fsm_rst:1;
-        /** conf_upgate : WT; bitpos: [11]; default: 0;
-         *  Configures this bit for synchronization
-         *  0: No effect
-         *
-         *  1: Synchronize
-         */
-        uint32_t conf_upgate:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_i2c_ctr_reg_t;
-
-/** Type of to register
- *  Setting time out control for receiving data.
- */
-typedef union {
-    struct {
-        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
-         *  Configures the timeout threshold period for SCL stucking at high or low level. The
-         *  actual period is 2^(reg_time_out_value).
-         *  Measurement unit: i2c_sclk.
-         */
-        uint32_t time_out_value:5;
-        /** time_out_en : R/W; bitpos: [5]; default: 0;
-         *  Configures to enable time out control.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t time_out_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} lp_i2c_to_reg_t;
-
-/** Type of fifo_conf register
- *  FIFO configuration register.
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_thrhd : R/W; bitpos: [3:0]; default: 6;
-         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
-         *  reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t rxfifo_wm_thrhd:4;
-        uint32_t reserved_4:1;
-        /** txfifo_wm_thrhd : R/W; bitpos: [8:5]; default: 2;
-         *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
-         *  reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t txfifo_wm_thrhd:4;
-        uint32_t reserved_9:1;
-        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
-         *  Configures to enable APB nonfifo access.
-         */
-        uint32_t nonfifo_en:1;
-        uint32_t reserved_11:1;
-        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
-         *  Configures to reset RXFIFO.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t rx_fifo_rst:1;
-        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
-         *  Configures to reset TXFIFO.
-         *  0: No effect
-         *
-         *  1: Reset
-         */
-        uint32_t tx_fifo_rst:1;
-        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
-         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
-         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
-         *  0: No effect
-         *
-         *  1: Enable
-         */
-        uint32_t fifo_prt_en:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_i2c_fifo_conf_reg_t;
-
-/** Type of filter_cfg register
- *  SCL and SDA filter configuration register
- */
-typedef union {
-    struct {
-        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
-         *  input has smaller width than this register value, the I2C controller will ignore
-         *  that pulse.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_filter_thres:4;
-        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
-         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
-         *  input has smaller width than this register value, the I2C controller will ignore
-         *  that pulse.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t sda_filter_thres:4;
-        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
-         *  Configures to enable the filter function for SCL.
-         */
-        uint32_t scl_filter_en:1;
-        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
-         *  Configures to enable the filter function for SDA.
-         */
-        uint32_t sda_filter_en:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} lp_i2c_filter_cfg_reg_t;
-
-/** Type of clk_conf register
- *  I2C CLK configuration register
- */
-typedef union {
-    struct {
-        /** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  the integral part of the fractional divisor for i2c module
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
-         *  the numerator of the fractional part of the fractional divisor for i2c module
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
-         *  the denominator of the fractional part of the fractional divisor for i2c module
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_sel : R/W; bitpos: [20]; default: 0;
-         *  The clock selection for i2c module:0-XTAL,1-CLK_8MHz.
-         */
-        uint32_t sclk_sel:1;
-        /** sclk_active : R/W; bitpos: [21]; default: 1;
-         *  The clock switch for i2c module
-         */
-        uint32_t sclk_active:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} lp_i2c_clk_conf_reg_t;
-
-/** Type of scl_sp_conf register
- *  Power configuration register
- */
-typedef union {
-    struct {
-        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
-         *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
-         *  equals to reg_scl_rst_slv_num[4:0].
-         */
-        uint32_t scl_rst_slv_en:1;
-        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
-         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
-         *  equals to reg_scl_rst_slv_num[4:0].
-         */
-        uint32_t scl_rst_slv_num:5;
-        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
-         *  Configure the pulses of SCL generated in I2C master mode.
-         *  Valid when reg_scl_rst_slv_en is 1.
-         *  Measurement unit: i2c_sclk
-         */
-        uint32_t scl_pd_en:1;
-        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
-         *  Configures to power down the I2C output SCL line.
-         *  0: Not power down.
-         *
-         *  1: Power down.
-         *  Valid only when reg_scl_force_out is 1.
-         */
-        uint32_t sda_pd_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_i2c_scl_sp_conf_reg_t;
-
-
-/** Group: Status registers */
-/** Type of sr register
- *  Describe I2C work status.
- */
-typedef union {
-    struct {
-        /** resp_rec : RO; bitpos: [0]; default: 0;
-         *  Represents the received ACK value in master mode or slave mode.
-         *  0: ACK,
-         *
-         *  1: NACK.
-         */
-        uint32_t resp_rec:1;
-        uint32_t reserved_1:2;
-        /** arb_lost : RO; bitpos: [3]; default: 0;
-         *  Represents whether the I2C controller loses control of SCL line.
-         *  0: No arbitration lost
-         *
-         *  1: Arbitration lost
-         */
-        uint32_t arb_lost:1;
-        /** bus_busy : RO; bitpos: [4]; default: 0;
-         *  Represents the I2C bus state.
-         *  1: The I2C bus is busy transferring data,
-         *
-         *  0: The I2C bus is in idle state.
-         */
-        uint32_t bus_busy:1;
-        uint32_t reserved_5:3;
-        /** rxfifo_cnt : RO; bitpos: [12:8]; default: 0;
-         *  Represents the number of data bytes to be sent.
-         */
-        uint32_t rxfifo_cnt:5;
-        uint32_t reserved_13:5;
-        /** txfifo_cnt : RO; bitpos: [22:18]; default: 0;
-         *  Represents the number of data bytes received in RAM.
-         */
-        uint32_t txfifo_cnt:5;
-        uint32_t reserved_23:1;
-        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
-         *  Represents the states of the I2C module state machine.
-         *  0: Idle,
-         *
-         *  1: Address shift,
-         *
-         *  2: ACK address,
-         *
-         *  3: Rx data,
-         *
-         *  4: Tx data,
-         *
-         *  5: Send ACK,
-         *
-         *  6: Wait ACK
-         */
-        uint32_t scl_main_state_last:3;
-        uint32_t reserved_27:1;
-        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
-         *  Represents the states of the state machine used to produce SCL.
-         *  0: Idle,
-         *
-         *  1: Start,
-         *
-         *  2: Negative edge,
-         *
-         *  3: Low,
-         *
-         *  4: Positive edge,
-         *
-         *  5: High,
-         *
-         *  6: Stop
-         */
-        uint32_t scl_state_last:3;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} lp_i2c_sr_reg_t;
-
-/** Type of fifo_st register
- *  FIFO status register.
- */
-typedef union {
-    struct {
-        /** rxfifo_raddr : RO; bitpos: [3:0]; default: 0;
-         *  Represents the offset address of the APB reading from RXFIFO
-         */
-        uint32_t rxfifo_raddr:4;
-        uint32_t reserved_4:1;
-        /** rxfifo_waddr : RO; bitpos: [8:5]; default: 0;
-         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
-         */
-        uint32_t rxfifo_waddr:4;
-        uint32_t reserved_9:1;
-        /** txfifo_raddr : RO; bitpos: [13:10]; default: 0;
-         *  Represents the offset address of i2c module reading from TXFIFO.
-         */
-        uint32_t txfifo_raddr:4;
-        uint32_t reserved_14:1;
-        /** txfifo_waddr : RO; bitpos: [18:15]; default: 0;
-         *  Represents the offset address of APB bus writing to TXFIFO.
-         */
-        uint32_t txfifo_waddr:4;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} lp_i2c_fifo_st_reg_t;
-
-/** Type of data register
- *  Rx FIFO read data.
- */
-typedef union {
-    struct {
-        /** fifo_rdata : RO; bitpos: [7:0]; default: 0;
-         *  Represents the value of RXFIFO read data.
-         */
-        uint32_t fifo_rdata:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_i2c_data_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_raw:1;
-        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
-         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
-         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_raw:1;
-        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
-         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_raw:1;
-        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
-         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_raw:1;
-        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
-         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_raw:1;
-        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
-         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_raw:1;
-        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
-         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_raw:1;
-        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
-         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_raw:1;
-        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
-         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_raw:1;
-        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
-         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_raw:1;
-        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
-         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_raw:1;
-        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
-         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_raw:1;
-        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
-         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_raw:1;
-        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
-         *  The raw interrupt status of I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_i2c_int_raw_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_clr:1;
-        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_clr:1;
-        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_clr:1;
-        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_clr:1;
-        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_clr:1;
-        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_clr:1;
-        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_clr:1;
-        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_clr:1;
-        /** nack_int_clr : WT; bitpos: [10]; default: 0;
-         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_clr:1;
-        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_clr:1;
-        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
-         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_clr:1;
-        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
-         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_clr:1;
-        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
-         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_clr:1;
-        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  Write 1 to clear I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_i2c_int_clr_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to anable I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_ena:1;
-        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to anable I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to anable I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to anable the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_ena:1;
-        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to anable the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_ena:1;
-        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_ena:1;
-        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_ena:1;
-        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_ena:1;
-        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to anable the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_ena:1;
-        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to anable the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_ena:1;
-        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_ena:1;
-        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Write 1 to anable I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_ena:1;
-        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Write 1 to anable I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_ena:1;
-        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Write 1 to anable I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_ena:1;
-        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_ena:1;
-        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Write 1 to anable I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_i2c_int_ena_reg_t;
-
-/** Type of int_status register
- *  Status of captured I2C communication events
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_st:1;
-        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_st:1;
-        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_st:1;
-        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_st:1;
-        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_st:1;
-        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_st:1;
-        /** time_out_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_st:1;
-        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_st:1;
-        /** nack_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_st:1;
-        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_st:1;
-        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_st:1;
-        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_st:1;
-        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_st:1;
-        /** det_start_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_i2c_int_status_reg_t;
-
-
-/** Group: Command registers */
-/** Type of comd register
- *  I2C command register n
- */
-typedef union {
-    struct {
-        /** command : R/W; bitpos: [13:0]; default: 0;
-         *  Configures command 0. It consists of three parts:
-         *  op_code is the command,
-         *  0: RSTART,
-         *  1: WRITE,
-         *  2: READ,
-         *  3: STOP,
-         *  4: END.
-         *
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more information.
-         */
-        uint32_t command:14;
-        uint32_t reserved_14:17;
-        /** command_done : R/W/SS; bitpos: [31]; default: 0;
-         *  Represents whether command n is done in I2C Master mode.
-         *  0: Not done
-         *
-         *  1: Done
-         */
-        uint32_t command_done:1;
-    };
-    uint32_t val;
-} lp_i2c_comd_reg_t;
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35656003;
-         *  Version control register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} lp_i2c_date_reg_t;
-
-
-/** Group: Address register */
-/** Type of txfifo_start_addr register
- *  I2C TXFIFO base address register
- */
-typedef union {
-    struct {
-        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Represents the I2C txfifo first address.
-         */
-        uint32_t txfifo_start_addr:32;
-    };
-    uint32_t val;
-} lp_i2c_txfifo_start_addr_reg_t;
-
-/** Type of rxfifo_start_addr register
- *  I2C RXFIFO base address register
- */
-typedef union {
-    struct {
-        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Represents the I2C rxfifo first address.
-         */
-        uint32_t rxfifo_start_addr:32;
-    };
-    uint32_t val;
-} lp_i2c_rxfifo_start_addr_reg_t;
-
-
-typedef struct lp_i2c_dev_t {
-    volatile lp_i2c_scl_low_period_reg_t scl_low_period;
-    volatile lp_i2c_ctr_reg_t ctr;
-    volatile lp_i2c_sr_reg_t sr;
-    volatile lp_i2c_to_reg_t to;
-    uint32_t reserved_010;
-    volatile lp_i2c_fifo_st_reg_t fifo_st;
-    volatile lp_i2c_fifo_conf_reg_t fifo_conf;
-    volatile lp_i2c_data_reg_t data;
-    volatile lp_i2c_int_raw_reg_t int_raw;
-    volatile lp_i2c_int_clr_reg_t int_clr;
-    volatile lp_i2c_int_ena_reg_t int_ena;
-    volatile lp_i2c_int_status_reg_t int_status;
-    volatile lp_i2c_sda_hold_reg_t sda_hold;
-    volatile lp_i2c_sda_sample_reg_t sda_sample;
-    volatile lp_i2c_scl_high_period_reg_t scl_high_period;
-    uint32_t reserved_03c;
-    volatile lp_i2c_scl_start_hold_reg_t scl_start_hold;
-    volatile lp_i2c_scl_rstart_setup_reg_t scl_rstart_setup;
-    volatile lp_i2c_scl_stop_hold_reg_t scl_stop_hold;
-    volatile lp_i2c_scl_stop_setup_reg_t scl_stop_setup;
-    volatile lp_i2c_filter_cfg_reg_t filter_cfg;
-    volatile lp_i2c_clk_conf_reg_t clk_conf;
-    volatile lp_i2c_comd_reg_t comd[8];
-    volatile lp_i2c_scl_st_time_out_reg_t scl_st_time_out;
-    volatile lp_i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
-    volatile lp_i2c_scl_sp_conf_reg_t scl_sp_conf;
-    uint32_t reserved_084[29];
-    volatile lp_i2c_date_reg_t date;
-    uint32_t reserved_0fc;
-    volatile lp_i2c_txfifo_start_addr_reg_t txfifo_start_addr;
-    uint32_t reserved_104[31];
-    volatile lp_i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
-} lp_i2c_dev_t;
-
-extern lp_i2c_dev_t LP_I2C;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_i2c_dev_t) == 0x184, "Invalid size of lp_i2c_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_io_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_io_reg.h
deleted file mode 100644
index 6382de6eed..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_io_reg.h
+++ /dev/null
@@ -1,1263 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_IO_OUT_DATA_REG register
- *  need des
- */
-#define LP_IO_OUT_DATA_REG (DR_REG_LP_IO_BASE + 0x0)
-/** LP_IO_LP_GPIO_OUT_DATA : R/W/WTC; bitpos: [7:0]; default: 0;
- *  set lp gpio output data
- */
-#define LP_IO_LP_GPIO_OUT_DATA    0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_M  (LP_IO_LP_GPIO_OUT_DATA_V << LP_IO_LP_GPIO_OUT_DATA_S)
-#define LP_IO_LP_GPIO_OUT_DATA_V  0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_S  0
-
-/** LP_IO_OUT_DATA_W1TS_REG register
- *  need des
- */
-#define LP_IO_OUT_DATA_W1TS_REG (DR_REG_LP_IO_BASE + 0x4)
-/** LP_IO_LP_GPIO_OUT_DATA_W1TS : WT; bitpos: [7:0]; default: 0;
- *  set one time output data
- */
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS    0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS_M  (LP_IO_LP_GPIO_OUT_DATA_W1TS_V << LP_IO_LP_GPIO_OUT_DATA_W1TS_S)
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS_V  0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TS_S  0
-
-/** LP_IO_OUT_DATA_W1TC_REG register
- *  need des
- */
-#define LP_IO_OUT_DATA_W1TC_REG (DR_REG_LP_IO_BASE + 0x8)
-/** LP_IO_LP_GPIO_OUT_DATA_W1TC : WT; bitpos: [7:0]; default: 0;
- *  clear one time output data
- */
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC    0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC_M  (LP_IO_LP_GPIO_OUT_DATA_W1TC_V << LP_IO_LP_GPIO_OUT_DATA_W1TC_S)
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC_V  0x000000FFU
-#define LP_IO_LP_GPIO_OUT_DATA_W1TC_S  0
-
-/** LP_IO_OUT_ENABLE_REG register
- *  need des
- */
-#define LP_IO_OUT_ENABLE_REG (DR_REG_LP_IO_BASE + 0xc)
-/** LP_IO_LP_GPIO_ENABLE : R/W/WTC; bitpos: [7:0]; default: 0;
- *  set lp gpio output data
- */
-#define LP_IO_LP_GPIO_ENABLE    0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_M  (LP_IO_LP_GPIO_ENABLE_V << LP_IO_LP_GPIO_ENABLE_S)
-#define LP_IO_LP_GPIO_ENABLE_V  0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_S  0
-
-/** LP_IO_OUT_ENABLE_W1TS_REG register
- *  need des
- */
-#define LP_IO_OUT_ENABLE_W1TS_REG (DR_REG_LP_IO_BASE + 0x10)
-/** LP_IO_LP_GPIO_ENABLE_W1TS : WT; bitpos: [7:0]; default: 0;
- *  set one time output data
- */
-#define LP_IO_LP_GPIO_ENABLE_W1TS    0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TS_M  (LP_IO_LP_GPIO_ENABLE_W1TS_V << LP_IO_LP_GPIO_ENABLE_W1TS_S)
-#define LP_IO_LP_GPIO_ENABLE_W1TS_V  0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TS_S  0
-
-/** LP_IO_OUT_ENABLE_W1TC_REG register
- *  need des
- */
-#define LP_IO_OUT_ENABLE_W1TC_REG (DR_REG_LP_IO_BASE + 0x14)
-/** LP_IO_LP_GPIO_ENABLE_W1TC : WT; bitpos: [7:0]; default: 0;
- *  clear one time output data
- */
-#define LP_IO_LP_GPIO_ENABLE_W1TC    0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TC_M  (LP_IO_LP_GPIO_ENABLE_W1TC_V << LP_IO_LP_GPIO_ENABLE_W1TC_S)
-#define LP_IO_LP_GPIO_ENABLE_W1TC_V  0x000000FFU
-#define LP_IO_LP_GPIO_ENABLE_W1TC_S  0
-
-/** LP_IO_STATUS_REG register
- *  need des
- */
-#define LP_IO_STATUS_REG (DR_REG_LP_IO_BASE + 0x18)
-/** LP_IO_LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [7:0]; default: 0;
- *  set lp gpio output data
- */
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT    0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_M  (LP_IO_LP_GPIO_STATUS_INTERRUPT_V << LP_IO_LP_GPIO_STATUS_INTERRUPT_S)
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_V  0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_INTERRUPT_S  0
-
-/** LP_IO_STATUS_W1TS_REG register
- *  need des
- */
-#define LP_IO_STATUS_W1TS_REG (DR_REG_LP_IO_BASE + 0x1c)
-/** LP_IO_LP_GPIO_STATUS_W1TS : WT; bitpos: [7:0]; default: 0;
- *  set one time output data
- */
-#define LP_IO_LP_GPIO_STATUS_W1TS    0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TS_M  (LP_IO_LP_GPIO_STATUS_W1TS_V << LP_IO_LP_GPIO_STATUS_W1TS_S)
-#define LP_IO_LP_GPIO_STATUS_W1TS_V  0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TS_S  0
-
-/** LP_IO_STATUS_W1TC_REG register
- *  need des
- */
-#define LP_IO_STATUS_W1TC_REG (DR_REG_LP_IO_BASE + 0x20)
-/** LP_IO_LP_GPIO_STATUS_W1TC : WT; bitpos: [7:0]; default: 0;
- *  clear one time output data
- */
-#define LP_IO_LP_GPIO_STATUS_W1TC    0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TC_M  (LP_IO_LP_GPIO_STATUS_W1TC_V << LP_IO_LP_GPIO_STATUS_W1TC_S)
-#define LP_IO_LP_GPIO_STATUS_W1TC_V  0x000000FFU
-#define LP_IO_LP_GPIO_STATUS_W1TC_S  0
-
-/** LP_IO_IN_REG register
- *  need des
- */
-#define LP_IO_IN_REG (DR_REG_LP_IO_BASE + 0x24)
-/** LP_IO_LP_GPIO_IN_DATA_NEXT : RO; bitpos: [7:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO_IN_DATA_NEXT    0x000000FFU
-#define LP_IO_LP_GPIO_IN_DATA_NEXT_M  (LP_IO_LP_GPIO_IN_DATA_NEXT_V << LP_IO_LP_GPIO_IN_DATA_NEXT_S)
-#define LP_IO_LP_GPIO_IN_DATA_NEXT_V  0x000000FFU
-#define LP_IO_LP_GPIO_IN_DATA_NEXT_S  0
-
-/** LP_IO_PIN0_REG register
- *  need des
- */
-#define LP_IO_PIN0_REG (DR_REG_LP_IO_BASE + 0x28)
-/** LP_IO_LP_GPIO0_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO0_SYNC_BYPASS_M  (LP_IO_LP_GPIO0_SYNC_BYPASS_V << LP_IO_LP_GPIO0_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO0_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO0_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO0_PAD_DRIVER_M  (LP_IO_LP_GPIO0_PAD_DRIVER_V << LP_IO_LP_GPIO0_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO0_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO0_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO0_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO0_INT_TYPE_M  (LP_IO_LP_GPIO0_INT_TYPE_V << LP_IO_LP_GPIO0_INT_TYPE_S)
-#define LP_IO_LP_GPIO0_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO0_INT_TYPE_S  7
-/** LP_IO_LP_GPIO0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO0_WAKEUP_ENABLE_V << LP_IO_LP_GPIO0_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO0_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO0_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO0_FILTER_EN_M  (LP_IO_LP_GPIO0_FILTER_EN_V << LP_IO_LP_GPIO0_FILTER_EN_S)
-#define LP_IO_LP_GPIO0_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO0_FILTER_EN_S  11
-
-/** LP_IO_PIN1_REG register
- *  need des
- */
-#define LP_IO_PIN1_REG (DR_REG_LP_IO_BASE + 0x2c)
-/** LP_IO_LP_GPIO1_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO1_SYNC_BYPASS_M  (LP_IO_LP_GPIO1_SYNC_BYPASS_V << LP_IO_LP_GPIO1_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO1_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO1_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO1_PAD_DRIVER_M  (LP_IO_LP_GPIO1_PAD_DRIVER_V << LP_IO_LP_GPIO1_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO1_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO1_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO1_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO1_INT_TYPE_M  (LP_IO_LP_GPIO1_INT_TYPE_V << LP_IO_LP_GPIO1_INT_TYPE_S)
-#define LP_IO_LP_GPIO1_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO1_INT_TYPE_S  7
-/** LP_IO_LP_GPIO1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO1_WAKEUP_ENABLE_V << LP_IO_LP_GPIO1_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO1_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO1_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO1_FILTER_EN_M  (LP_IO_LP_GPIO1_FILTER_EN_V << LP_IO_LP_GPIO1_FILTER_EN_S)
-#define LP_IO_LP_GPIO1_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO1_FILTER_EN_S  11
-
-/** LP_IO_PIN2_REG register
- *  need des
- */
-#define LP_IO_PIN2_REG (DR_REG_LP_IO_BASE + 0x30)
-/** LP_IO_LP_GPIO2_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO2_SYNC_BYPASS_M  (LP_IO_LP_GPIO2_SYNC_BYPASS_V << LP_IO_LP_GPIO2_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO2_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO2_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO2_PAD_DRIVER_M  (LP_IO_LP_GPIO2_PAD_DRIVER_V << LP_IO_LP_GPIO2_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO2_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO2_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO2_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO2_INT_TYPE_M  (LP_IO_LP_GPIO2_INT_TYPE_V << LP_IO_LP_GPIO2_INT_TYPE_S)
-#define LP_IO_LP_GPIO2_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO2_INT_TYPE_S  7
-/** LP_IO_LP_GPIO2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO2_WAKEUP_ENABLE_V << LP_IO_LP_GPIO2_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO2_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO2_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO2_FILTER_EN_M  (LP_IO_LP_GPIO2_FILTER_EN_V << LP_IO_LP_GPIO2_FILTER_EN_S)
-#define LP_IO_LP_GPIO2_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO2_FILTER_EN_S  11
-
-/** LP_IO_PIN3_REG register
- *  need des
- */
-#define LP_IO_PIN3_REG (DR_REG_LP_IO_BASE + 0x34)
-/** LP_IO_LP_GPIO3_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO3_SYNC_BYPASS_M  (LP_IO_LP_GPIO3_SYNC_BYPASS_V << LP_IO_LP_GPIO3_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO3_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO3_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO3_PAD_DRIVER_M  (LP_IO_LP_GPIO3_PAD_DRIVER_V << LP_IO_LP_GPIO3_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO3_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO3_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO3_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO3_INT_TYPE_M  (LP_IO_LP_GPIO3_INT_TYPE_V << LP_IO_LP_GPIO3_INT_TYPE_S)
-#define LP_IO_LP_GPIO3_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO3_INT_TYPE_S  7
-/** LP_IO_LP_GPIO3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO3_WAKEUP_ENABLE_V << LP_IO_LP_GPIO3_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO3_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO3_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO3_FILTER_EN_M  (LP_IO_LP_GPIO3_FILTER_EN_V << LP_IO_LP_GPIO3_FILTER_EN_S)
-#define LP_IO_LP_GPIO3_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO3_FILTER_EN_S  11
-
-/** LP_IO_PIN4_REG register
- *  need des
- */
-#define LP_IO_PIN4_REG (DR_REG_LP_IO_BASE + 0x38)
-/** LP_IO_LP_GPIO4_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO4_SYNC_BYPASS_M  (LP_IO_LP_GPIO4_SYNC_BYPASS_V << LP_IO_LP_GPIO4_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO4_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO4_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO4_PAD_DRIVER_M  (LP_IO_LP_GPIO4_PAD_DRIVER_V << LP_IO_LP_GPIO4_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO4_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO4_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO4_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO4_INT_TYPE_M  (LP_IO_LP_GPIO4_INT_TYPE_V << LP_IO_LP_GPIO4_INT_TYPE_S)
-#define LP_IO_LP_GPIO4_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO4_INT_TYPE_S  7
-/** LP_IO_LP_GPIO4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO4_WAKEUP_ENABLE_V << LP_IO_LP_GPIO4_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO4_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO4_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO4_FILTER_EN_M  (LP_IO_LP_GPIO4_FILTER_EN_V << LP_IO_LP_GPIO4_FILTER_EN_S)
-#define LP_IO_LP_GPIO4_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO4_FILTER_EN_S  11
-
-/** LP_IO_PIN5_REG register
- *  need des
- */
-#define LP_IO_PIN5_REG (DR_REG_LP_IO_BASE + 0x3c)
-/** LP_IO_LP_GPIO5_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO5_SYNC_BYPASS_M  (LP_IO_LP_GPIO5_SYNC_BYPASS_V << LP_IO_LP_GPIO5_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO5_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO5_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO5_PAD_DRIVER_M  (LP_IO_LP_GPIO5_PAD_DRIVER_V << LP_IO_LP_GPIO5_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO5_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO5_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO5_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO5_INT_TYPE_M  (LP_IO_LP_GPIO5_INT_TYPE_V << LP_IO_LP_GPIO5_INT_TYPE_S)
-#define LP_IO_LP_GPIO5_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO5_INT_TYPE_S  7
-/** LP_IO_LP_GPIO5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO5_WAKEUP_ENABLE_V << LP_IO_LP_GPIO5_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO5_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO5_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO5_FILTER_EN_M  (LP_IO_LP_GPIO5_FILTER_EN_V << LP_IO_LP_GPIO5_FILTER_EN_S)
-#define LP_IO_LP_GPIO5_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO5_FILTER_EN_S  11
-
-/** LP_IO_PIN6_REG register
- *  need des
- */
-#define LP_IO_PIN6_REG (DR_REG_LP_IO_BASE + 0x40)
-/** LP_IO_LP_GPIO6_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO6_SYNC_BYPASS_M  (LP_IO_LP_GPIO6_SYNC_BYPASS_V << LP_IO_LP_GPIO6_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO6_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO6_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO6_PAD_DRIVER_M  (LP_IO_LP_GPIO6_PAD_DRIVER_V << LP_IO_LP_GPIO6_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO6_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO6_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO6_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO6_INT_TYPE_M  (LP_IO_LP_GPIO6_INT_TYPE_V << LP_IO_LP_GPIO6_INT_TYPE_S)
-#define LP_IO_LP_GPIO6_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO6_INT_TYPE_S  7
-/** LP_IO_LP_GPIO6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO6_WAKEUP_ENABLE_V << LP_IO_LP_GPIO6_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO6_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO6_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO6_FILTER_EN_M  (LP_IO_LP_GPIO6_FILTER_EN_V << LP_IO_LP_GPIO6_FILTER_EN_S)
-#define LP_IO_LP_GPIO6_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO6_FILTER_EN_S  11
-
-/** LP_IO_PIN7_REG register
- *  need des
- */
-#define LP_IO_PIN7_REG (DR_REG_LP_IO_BASE + 0x44)
-/** LP_IO_LP_GPIO7_SYNC_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_SYNC_BYPASS    0x00000003U
-#define LP_IO_LP_GPIO7_SYNC_BYPASS_M  (LP_IO_LP_GPIO7_SYNC_BYPASS_V << LP_IO_LP_GPIO7_SYNC_BYPASS_S)
-#define LP_IO_LP_GPIO7_SYNC_BYPASS_V  0x00000003U
-#define LP_IO_LP_GPIO7_SYNC_BYPASS_S  0
-/** LP_IO_LP_GPIO7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_PAD_DRIVER    (BIT(2))
-#define LP_IO_LP_GPIO7_PAD_DRIVER_M  (LP_IO_LP_GPIO7_PAD_DRIVER_V << LP_IO_LP_GPIO7_PAD_DRIVER_S)
-#define LP_IO_LP_GPIO7_PAD_DRIVER_V  0x00000001U
-#define LP_IO_LP_GPIO7_PAD_DRIVER_S  2
-/** LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR : WT; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR    (BIT(3))
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_M  (LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V << LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S)
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_V  0x00000001U
-#define LP_IO_LP_GPIO7_EDGE_WAKEUP_CLR_S  3
-/** LP_IO_LP_GPIO7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_INT_TYPE    0x00000007U
-#define LP_IO_LP_GPIO7_INT_TYPE_M  (LP_IO_LP_GPIO7_INT_TYPE_V << LP_IO_LP_GPIO7_INT_TYPE_S)
-#define LP_IO_LP_GPIO7_INT_TYPE_V  0x00000007U
-#define LP_IO_LP_GPIO7_INT_TYPE_S  7
-/** LP_IO_LP_GPIO7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE    (BIT(10))
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_M  (LP_IO_LP_GPIO7_WAKEUP_ENABLE_V << LP_IO_LP_GPIO7_WAKEUP_ENABLE_S)
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_V  0x00000001U
-#define LP_IO_LP_GPIO7_WAKEUP_ENABLE_S  10
-/** LP_IO_LP_GPIO7_FILTER_EN : R/W; bitpos: [11]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FILTER_EN    (BIT(11))
-#define LP_IO_LP_GPIO7_FILTER_EN_M  (LP_IO_LP_GPIO7_FILTER_EN_V << LP_IO_LP_GPIO7_FILTER_EN_S)
-#define LP_IO_LP_GPIO7_FILTER_EN_V  0x00000001U
-#define LP_IO_LP_GPIO7_FILTER_EN_S  11
-
-/** LP_IO_GPIO0_REG register
- *  need des
- */
-#define LP_IO_GPIO0_REG (DR_REG_LP_IO_BASE + 0x48)
-/** LP_IO_LP_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO0_MCU_OE_M  (LP_IO_LP_GPIO0_MCU_OE_V << LP_IO_LP_GPIO0_MCU_OE_S)
-#define LP_IO_LP_GPIO0_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_OE_S  0
-/** LP_IO_LP_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO0_SLP_SEL_M  (LP_IO_LP_GPIO0_SLP_SEL_V << LP_IO_LP_GPIO0_SLP_SEL_S)
-#define LP_IO_LP_GPIO0_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO0_SLP_SEL_S  1
-/** LP_IO_LP_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO0_MCU_WPD_M  (LP_IO_LP_GPIO0_MCU_WPD_V << LP_IO_LP_GPIO0_MCU_WPD_S)
-#define LP_IO_LP_GPIO0_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_WPD_S  2
-/** LP_IO_LP_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO0_MCU_WPU_M  (LP_IO_LP_GPIO0_MCU_WPU_V << LP_IO_LP_GPIO0_MCU_WPU_S)
-#define LP_IO_LP_GPIO0_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_WPU_S  3
-/** LP_IO_LP_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO0_MCU_IE_M  (LP_IO_LP_GPIO0_MCU_IE_V << LP_IO_LP_GPIO0_MCU_IE_S)
-#define LP_IO_LP_GPIO0_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO0_MCU_IE_S  4
-/** LP_IO_LP_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO0_MCU_DRV_M  (LP_IO_LP_GPIO0_MCU_DRV_V << LP_IO_LP_GPIO0_MCU_DRV_S)
-#define LP_IO_LP_GPIO0_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO0_MCU_DRV_S  5
-/** LP_IO_LP_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO0_FUN_WPD_M  (LP_IO_LP_GPIO0_FUN_WPD_V << LP_IO_LP_GPIO0_FUN_WPD_S)
-#define LP_IO_LP_GPIO0_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO0_FUN_WPD_S  7
-/** LP_IO_LP_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO0_FUN_WPU_M  (LP_IO_LP_GPIO0_FUN_WPU_V << LP_IO_LP_GPIO0_FUN_WPU_S)
-#define LP_IO_LP_GPIO0_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO0_FUN_WPU_S  8
-/** LP_IO_LP_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO0_FUN_IE_M  (LP_IO_LP_GPIO0_FUN_IE_V << LP_IO_LP_GPIO0_FUN_IE_S)
-#define LP_IO_LP_GPIO0_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO0_FUN_IE_S  9
-/** LP_IO_LP_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO0_FUN_DRV_M  (LP_IO_LP_GPIO0_FUN_DRV_V << LP_IO_LP_GPIO0_FUN_DRV_S)
-#define LP_IO_LP_GPIO0_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO0_FUN_DRV_S  10
-/** LP_IO_LP_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO0_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO0_MCU_SEL_M  (LP_IO_LP_GPIO0_MCU_SEL_V << LP_IO_LP_GPIO0_MCU_SEL_S)
-#define LP_IO_LP_GPIO0_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO0_MCU_SEL_S  12
-
-/** LP_IO_GPIO1_REG register
- *  need des
- */
-#define LP_IO_GPIO1_REG (DR_REG_LP_IO_BASE + 0x4c)
-/** LP_IO_LP_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO1_MCU_OE_M  (LP_IO_LP_GPIO1_MCU_OE_V << LP_IO_LP_GPIO1_MCU_OE_S)
-#define LP_IO_LP_GPIO1_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_OE_S  0
-/** LP_IO_LP_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO1_SLP_SEL_M  (LP_IO_LP_GPIO1_SLP_SEL_V << LP_IO_LP_GPIO1_SLP_SEL_S)
-#define LP_IO_LP_GPIO1_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO1_SLP_SEL_S  1
-/** LP_IO_LP_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO1_MCU_WPD_M  (LP_IO_LP_GPIO1_MCU_WPD_V << LP_IO_LP_GPIO1_MCU_WPD_S)
-#define LP_IO_LP_GPIO1_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_WPD_S  2
-/** LP_IO_LP_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO1_MCU_WPU_M  (LP_IO_LP_GPIO1_MCU_WPU_V << LP_IO_LP_GPIO1_MCU_WPU_S)
-#define LP_IO_LP_GPIO1_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_WPU_S  3
-/** LP_IO_LP_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO1_MCU_IE_M  (LP_IO_LP_GPIO1_MCU_IE_V << LP_IO_LP_GPIO1_MCU_IE_S)
-#define LP_IO_LP_GPIO1_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO1_MCU_IE_S  4
-/** LP_IO_LP_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO1_MCU_DRV_M  (LP_IO_LP_GPIO1_MCU_DRV_V << LP_IO_LP_GPIO1_MCU_DRV_S)
-#define LP_IO_LP_GPIO1_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO1_MCU_DRV_S  5
-/** LP_IO_LP_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO1_FUN_WPD_M  (LP_IO_LP_GPIO1_FUN_WPD_V << LP_IO_LP_GPIO1_FUN_WPD_S)
-#define LP_IO_LP_GPIO1_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO1_FUN_WPD_S  7
-/** LP_IO_LP_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO1_FUN_WPU_M  (LP_IO_LP_GPIO1_FUN_WPU_V << LP_IO_LP_GPIO1_FUN_WPU_S)
-#define LP_IO_LP_GPIO1_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO1_FUN_WPU_S  8
-/** LP_IO_LP_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO1_FUN_IE_M  (LP_IO_LP_GPIO1_FUN_IE_V << LP_IO_LP_GPIO1_FUN_IE_S)
-#define LP_IO_LP_GPIO1_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO1_FUN_IE_S  9
-/** LP_IO_LP_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO1_FUN_DRV_M  (LP_IO_LP_GPIO1_FUN_DRV_V << LP_IO_LP_GPIO1_FUN_DRV_S)
-#define LP_IO_LP_GPIO1_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO1_FUN_DRV_S  10
-/** LP_IO_LP_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO1_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO1_MCU_SEL_M  (LP_IO_LP_GPIO1_MCU_SEL_V << LP_IO_LP_GPIO1_MCU_SEL_S)
-#define LP_IO_LP_GPIO1_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO1_MCU_SEL_S  12
-
-/** LP_IO_GPIO2_REG register
- *  need des
- */
-#define LP_IO_GPIO2_REG (DR_REG_LP_IO_BASE + 0x50)
-/** LP_IO_LP_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO2_MCU_OE_M  (LP_IO_LP_GPIO2_MCU_OE_V << LP_IO_LP_GPIO2_MCU_OE_S)
-#define LP_IO_LP_GPIO2_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_OE_S  0
-/** LP_IO_LP_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO2_SLP_SEL_M  (LP_IO_LP_GPIO2_SLP_SEL_V << LP_IO_LP_GPIO2_SLP_SEL_S)
-#define LP_IO_LP_GPIO2_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO2_SLP_SEL_S  1
-/** LP_IO_LP_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO2_MCU_WPD_M  (LP_IO_LP_GPIO2_MCU_WPD_V << LP_IO_LP_GPIO2_MCU_WPD_S)
-#define LP_IO_LP_GPIO2_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_WPD_S  2
-/** LP_IO_LP_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO2_MCU_WPU_M  (LP_IO_LP_GPIO2_MCU_WPU_V << LP_IO_LP_GPIO2_MCU_WPU_S)
-#define LP_IO_LP_GPIO2_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_WPU_S  3
-/** LP_IO_LP_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO2_MCU_IE_M  (LP_IO_LP_GPIO2_MCU_IE_V << LP_IO_LP_GPIO2_MCU_IE_S)
-#define LP_IO_LP_GPIO2_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO2_MCU_IE_S  4
-/** LP_IO_LP_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO2_MCU_DRV_M  (LP_IO_LP_GPIO2_MCU_DRV_V << LP_IO_LP_GPIO2_MCU_DRV_S)
-#define LP_IO_LP_GPIO2_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO2_MCU_DRV_S  5
-/** LP_IO_LP_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO2_FUN_WPD_M  (LP_IO_LP_GPIO2_FUN_WPD_V << LP_IO_LP_GPIO2_FUN_WPD_S)
-#define LP_IO_LP_GPIO2_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO2_FUN_WPD_S  7
-/** LP_IO_LP_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO2_FUN_WPU_M  (LP_IO_LP_GPIO2_FUN_WPU_V << LP_IO_LP_GPIO2_FUN_WPU_S)
-#define LP_IO_LP_GPIO2_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO2_FUN_WPU_S  8
-/** LP_IO_LP_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO2_FUN_IE_M  (LP_IO_LP_GPIO2_FUN_IE_V << LP_IO_LP_GPIO2_FUN_IE_S)
-#define LP_IO_LP_GPIO2_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO2_FUN_IE_S  9
-/** LP_IO_LP_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO2_FUN_DRV_M  (LP_IO_LP_GPIO2_FUN_DRV_V << LP_IO_LP_GPIO2_FUN_DRV_S)
-#define LP_IO_LP_GPIO2_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO2_FUN_DRV_S  10
-/** LP_IO_LP_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO2_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO2_MCU_SEL_M  (LP_IO_LP_GPIO2_MCU_SEL_V << LP_IO_LP_GPIO2_MCU_SEL_S)
-#define LP_IO_LP_GPIO2_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO2_MCU_SEL_S  12
-
-/** LP_IO_GPIO3_REG register
- *  need des
- */
-#define LP_IO_GPIO3_REG (DR_REG_LP_IO_BASE + 0x54)
-/** LP_IO_LP_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO3_MCU_OE_M  (LP_IO_LP_GPIO3_MCU_OE_V << LP_IO_LP_GPIO3_MCU_OE_S)
-#define LP_IO_LP_GPIO3_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_OE_S  0
-/** LP_IO_LP_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO3_SLP_SEL_M  (LP_IO_LP_GPIO3_SLP_SEL_V << LP_IO_LP_GPIO3_SLP_SEL_S)
-#define LP_IO_LP_GPIO3_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO3_SLP_SEL_S  1
-/** LP_IO_LP_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO3_MCU_WPD_M  (LP_IO_LP_GPIO3_MCU_WPD_V << LP_IO_LP_GPIO3_MCU_WPD_S)
-#define LP_IO_LP_GPIO3_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_WPD_S  2
-/** LP_IO_LP_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO3_MCU_WPU_M  (LP_IO_LP_GPIO3_MCU_WPU_V << LP_IO_LP_GPIO3_MCU_WPU_S)
-#define LP_IO_LP_GPIO3_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_WPU_S  3
-/** LP_IO_LP_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO3_MCU_IE_M  (LP_IO_LP_GPIO3_MCU_IE_V << LP_IO_LP_GPIO3_MCU_IE_S)
-#define LP_IO_LP_GPIO3_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO3_MCU_IE_S  4
-/** LP_IO_LP_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO3_MCU_DRV_M  (LP_IO_LP_GPIO3_MCU_DRV_V << LP_IO_LP_GPIO3_MCU_DRV_S)
-#define LP_IO_LP_GPIO3_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO3_MCU_DRV_S  5
-/** LP_IO_LP_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO3_FUN_WPD_M  (LP_IO_LP_GPIO3_FUN_WPD_V << LP_IO_LP_GPIO3_FUN_WPD_S)
-#define LP_IO_LP_GPIO3_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO3_FUN_WPD_S  7
-/** LP_IO_LP_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO3_FUN_WPU_M  (LP_IO_LP_GPIO3_FUN_WPU_V << LP_IO_LP_GPIO3_FUN_WPU_S)
-#define LP_IO_LP_GPIO3_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO3_FUN_WPU_S  8
-/** LP_IO_LP_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO3_FUN_IE_M  (LP_IO_LP_GPIO3_FUN_IE_V << LP_IO_LP_GPIO3_FUN_IE_S)
-#define LP_IO_LP_GPIO3_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO3_FUN_IE_S  9
-/** LP_IO_LP_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO3_FUN_DRV_M  (LP_IO_LP_GPIO3_FUN_DRV_V << LP_IO_LP_GPIO3_FUN_DRV_S)
-#define LP_IO_LP_GPIO3_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO3_FUN_DRV_S  10
-/** LP_IO_LP_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO3_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO3_MCU_SEL_M  (LP_IO_LP_GPIO3_MCU_SEL_V << LP_IO_LP_GPIO3_MCU_SEL_S)
-#define LP_IO_LP_GPIO3_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO3_MCU_SEL_S  12
-
-/** LP_IO_GPIO4_REG register
- *  need des
- */
-#define LP_IO_GPIO4_REG (DR_REG_LP_IO_BASE + 0x58)
-/** LP_IO_LP_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO4_MCU_OE_M  (LP_IO_LP_GPIO4_MCU_OE_V << LP_IO_LP_GPIO4_MCU_OE_S)
-#define LP_IO_LP_GPIO4_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_OE_S  0
-/** LP_IO_LP_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO4_SLP_SEL_M  (LP_IO_LP_GPIO4_SLP_SEL_V << LP_IO_LP_GPIO4_SLP_SEL_S)
-#define LP_IO_LP_GPIO4_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO4_SLP_SEL_S  1
-/** LP_IO_LP_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO4_MCU_WPD_M  (LP_IO_LP_GPIO4_MCU_WPD_V << LP_IO_LP_GPIO4_MCU_WPD_S)
-#define LP_IO_LP_GPIO4_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_WPD_S  2
-/** LP_IO_LP_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO4_MCU_WPU_M  (LP_IO_LP_GPIO4_MCU_WPU_V << LP_IO_LP_GPIO4_MCU_WPU_S)
-#define LP_IO_LP_GPIO4_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_WPU_S  3
-/** LP_IO_LP_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO4_MCU_IE_M  (LP_IO_LP_GPIO4_MCU_IE_V << LP_IO_LP_GPIO4_MCU_IE_S)
-#define LP_IO_LP_GPIO4_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO4_MCU_IE_S  4
-/** LP_IO_LP_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO4_MCU_DRV_M  (LP_IO_LP_GPIO4_MCU_DRV_V << LP_IO_LP_GPIO4_MCU_DRV_S)
-#define LP_IO_LP_GPIO4_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO4_MCU_DRV_S  5
-/** LP_IO_LP_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO4_FUN_WPD_M  (LP_IO_LP_GPIO4_FUN_WPD_V << LP_IO_LP_GPIO4_FUN_WPD_S)
-#define LP_IO_LP_GPIO4_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO4_FUN_WPD_S  7
-/** LP_IO_LP_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO4_FUN_WPU_M  (LP_IO_LP_GPIO4_FUN_WPU_V << LP_IO_LP_GPIO4_FUN_WPU_S)
-#define LP_IO_LP_GPIO4_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO4_FUN_WPU_S  8
-/** LP_IO_LP_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO4_FUN_IE_M  (LP_IO_LP_GPIO4_FUN_IE_V << LP_IO_LP_GPIO4_FUN_IE_S)
-#define LP_IO_LP_GPIO4_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO4_FUN_IE_S  9
-/** LP_IO_LP_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO4_FUN_DRV_M  (LP_IO_LP_GPIO4_FUN_DRV_V << LP_IO_LP_GPIO4_FUN_DRV_S)
-#define LP_IO_LP_GPIO4_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO4_FUN_DRV_S  10
-/** LP_IO_LP_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO4_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO4_MCU_SEL_M  (LP_IO_LP_GPIO4_MCU_SEL_V << LP_IO_LP_GPIO4_MCU_SEL_S)
-#define LP_IO_LP_GPIO4_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO4_MCU_SEL_S  12
-
-/** LP_IO_GPIO5_REG register
- *  need des
- */
-#define LP_IO_GPIO5_REG (DR_REG_LP_IO_BASE + 0x5c)
-/** LP_IO_LP_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO5_MCU_OE_M  (LP_IO_LP_GPIO5_MCU_OE_V << LP_IO_LP_GPIO5_MCU_OE_S)
-#define LP_IO_LP_GPIO5_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_OE_S  0
-/** LP_IO_LP_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO5_SLP_SEL_M  (LP_IO_LP_GPIO5_SLP_SEL_V << LP_IO_LP_GPIO5_SLP_SEL_S)
-#define LP_IO_LP_GPIO5_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO5_SLP_SEL_S  1
-/** LP_IO_LP_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO5_MCU_WPD_M  (LP_IO_LP_GPIO5_MCU_WPD_V << LP_IO_LP_GPIO5_MCU_WPD_S)
-#define LP_IO_LP_GPIO5_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_WPD_S  2
-/** LP_IO_LP_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO5_MCU_WPU_M  (LP_IO_LP_GPIO5_MCU_WPU_V << LP_IO_LP_GPIO5_MCU_WPU_S)
-#define LP_IO_LP_GPIO5_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_WPU_S  3
-/** LP_IO_LP_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO5_MCU_IE_M  (LP_IO_LP_GPIO5_MCU_IE_V << LP_IO_LP_GPIO5_MCU_IE_S)
-#define LP_IO_LP_GPIO5_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO5_MCU_IE_S  4
-/** LP_IO_LP_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO5_MCU_DRV_M  (LP_IO_LP_GPIO5_MCU_DRV_V << LP_IO_LP_GPIO5_MCU_DRV_S)
-#define LP_IO_LP_GPIO5_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO5_MCU_DRV_S  5
-/** LP_IO_LP_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO5_FUN_WPD_M  (LP_IO_LP_GPIO5_FUN_WPD_V << LP_IO_LP_GPIO5_FUN_WPD_S)
-#define LP_IO_LP_GPIO5_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO5_FUN_WPD_S  7
-/** LP_IO_LP_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO5_FUN_WPU_M  (LP_IO_LP_GPIO5_FUN_WPU_V << LP_IO_LP_GPIO5_FUN_WPU_S)
-#define LP_IO_LP_GPIO5_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO5_FUN_WPU_S  8
-/** LP_IO_LP_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO5_FUN_IE_M  (LP_IO_LP_GPIO5_FUN_IE_V << LP_IO_LP_GPIO5_FUN_IE_S)
-#define LP_IO_LP_GPIO5_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO5_FUN_IE_S  9
-/** LP_IO_LP_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO5_FUN_DRV_M  (LP_IO_LP_GPIO5_FUN_DRV_V << LP_IO_LP_GPIO5_FUN_DRV_S)
-#define LP_IO_LP_GPIO5_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO5_FUN_DRV_S  10
-/** LP_IO_LP_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO5_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO5_MCU_SEL_M  (LP_IO_LP_GPIO5_MCU_SEL_V << LP_IO_LP_GPIO5_MCU_SEL_S)
-#define LP_IO_LP_GPIO5_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO5_MCU_SEL_S  12
-
-/** LP_IO_GPIO6_REG register
- *  need des
- */
-#define LP_IO_GPIO6_REG (DR_REG_LP_IO_BASE + 0x60)
-/** LP_IO_LP_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO6_MCU_OE_M  (LP_IO_LP_GPIO6_MCU_OE_V << LP_IO_LP_GPIO6_MCU_OE_S)
-#define LP_IO_LP_GPIO6_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_OE_S  0
-/** LP_IO_LP_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO6_SLP_SEL_M  (LP_IO_LP_GPIO6_SLP_SEL_V << LP_IO_LP_GPIO6_SLP_SEL_S)
-#define LP_IO_LP_GPIO6_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO6_SLP_SEL_S  1
-/** LP_IO_LP_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO6_MCU_WPD_M  (LP_IO_LP_GPIO6_MCU_WPD_V << LP_IO_LP_GPIO6_MCU_WPD_S)
-#define LP_IO_LP_GPIO6_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_WPD_S  2
-/** LP_IO_LP_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO6_MCU_WPU_M  (LP_IO_LP_GPIO6_MCU_WPU_V << LP_IO_LP_GPIO6_MCU_WPU_S)
-#define LP_IO_LP_GPIO6_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_WPU_S  3
-/** LP_IO_LP_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO6_MCU_IE_M  (LP_IO_LP_GPIO6_MCU_IE_V << LP_IO_LP_GPIO6_MCU_IE_S)
-#define LP_IO_LP_GPIO6_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO6_MCU_IE_S  4
-/** LP_IO_LP_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO6_MCU_DRV_M  (LP_IO_LP_GPIO6_MCU_DRV_V << LP_IO_LP_GPIO6_MCU_DRV_S)
-#define LP_IO_LP_GPIO6_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO6_MCU_DRV_S  5
-/** LP_IO_LP_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO6_FUN_WPD_M  (LP_IO_LP_GPIO6_FUN_WPD_V << LP_IO_LP_GPIO6_FUN_WPD_S)
-#define LP_IO_LP_GPIO6_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO6_FUN_WPD_S  7
-/** LP_IO_LP_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO6_FUN_WPU_M  (LP_IO_LP_GPIO6_FUN_WPU_V << LP_IO_LP_GPIO6_FUN_WPU_S)
-#define LP_IO_LP_GPIO6_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO6_FUN_WPU_S  8
-/** LP_IO_LP_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO6_FUN_IE_M  (LP_IO_LP_GPIO6_FUN_IE_V << LP_IO_LP_GPIO6_FUN_IE_S)
-#define LP_IO_LP_GPIO6_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO6_FUN_IE_S  9
-/** LP_IO_LP_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO6_FUN_DRV_M  (LP_IO_LP_GPIO6_FUN_DRV_V << LP_IO_LP_GPIO6_FUN_DRV_S)
-#define LP_IO_LP_GPIO6_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO6_FUN_DRV_S  10
-/** LP_IO_LP_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO6_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO6_MCU_SEL_M  (LP_IO_LP_GPIO6_MCU_SEL_V << LP_IO_LP_GPIO6_MCU_SEL_S)
-#define LP_IO_LP_GPIO6_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO6_MCU_SEL_S  12
-
-/** LP_IO_GPIO7_REG register
- *  need des
- */
-#define LP_IO_GPIO7_REG (DR_REG_LP_IO_BASE + 0x64)
-/** LP_IO_LP_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_OE    (BIT(0))
-#define LP_IO_LP_GPIO7_MCU_OE_M  (LP_IO_LP_GPIO7_MCU_OE_V << LP_IO_LP_GPIO7_MCU_OE_S)
-#define LP_IO_LP_GPIO7_MCU_OE_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_OE_S  0
-/** LP_IO_LP_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_SLP_SEL    (BIT(1))
-#define LP_IO_LP_GPIO7_SLP_SEL_M  (LP_IO_LP_GPIO7_SLP_SEL_V << LP_IO_LP_GPIO7_SLP_SEL_S)
-#define LP_IO_LP_GPIO7_SLP_SEL_V  0x00000001U
-#define LP_IO_LP_GPIO7_SLP_SEL_S  1
-/** LP_IO_LP_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_WPD    (BIT(2))
-#define LP_IO_LP_GPIO7_MCU_WPD_M  (LP_IO_LP_GPIO7_MCU_WPD_V << LP_IO_LP_GPIO7_MCU_WPD_S)
-#define LP_IO_LP_GPIO7_MCU_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_WPD_S  2
-/** LP_IO_LP_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_WPU    (BIT(3))
-#define LP_IO_LP_GPIO7_MCU_WPU_M  (LP_IO_LP_GPIO7_MCU_WPU_V << LP_IO_LP_GPIO7_MCU_WPU_S)
-#define LP_IO_LP_GPIO7_MCU_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_WPU_S  3
-/** LP_IO_LP_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_IE    (BIT(4))
-#define LP_IO_LP_GPIO7_MCU_IE_M  (LP_IO_LP_GPIO7_MCU_IE_V << LP_IO_LP_GPIO7_MCU_IE_S)
-#define LP_IO_LP_GPIO7_MCU_IE_V  0x00000001U
-#define LP_IO_LP_GPIO7_MCU_IE_S  4
-/** LP_IO_LP_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_DRV    0x00000003U
-#define LP_IO_LP_GPIO7_MCU_DRV_M  (LP_IO_LP_GPIO7_MCU_DRV_V << LP_IO_LP_GPIO7_MCU_DRV_S)
-#define LP_IO_LP_GPIO7_MCU_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO7_MCU_DRV_S  5
-/** LP_IO_LP_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_WPD    (BIT(7))
-#define LP_IO_LP_GPIO7_FUN_WPD_M  (LP_IO_LP_GPIO7_FUN_WPD_V << LP_IO_LP_GPIO7_FUN_WPD_S)
-#define LP_IO_LP_GPIO7_FUN_WPD_V  0x00000001U
-#define LP_IO_LP_GPIO7_FUN_WPD_S  7
-/** LP_IO_LP_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_WPU    (BIT(8))
-#define LP_IO_LP_GPIO7_FUN_WPU_M  (LP_IO_LP_GPIO7_FUN_WPU_V << LP_IO_LP_GPIO7_FUN_WPU_S)
-#define LP_IO_LP_GPIO7_FUN_WPU_V  0x00000001U
-#define LP_IO_LP_GPIO7_FUN_WPU_S  8
-/** LP_IO_LP_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_IE    (BIT(9))
-#define LP_IO_LP_GPIO7_FUN_IE_M  (LP_IO_LP_GPIO7_FUN_IE_V << LP_IO_LP_GPIO7_FUN_IE_S)
-#define LP_IO_LP_GPIO7_FUN_IE_V  0x00000001U
-#define LP_IO_LP_GPIO7_FUN_IE_S  9
-/** LP_IO_LP_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_FUN_DRV    0x00000003U
-#define LP_IO_LP_GPIO7_FUN_DRV_M  (LP_IO_LP_GPIO7_FUN_DRV_V << LP_IO_LP_GPIO7_FUN_DRV_S)
-#define LP_IO_LP_GPIO7_FUN_DRV_V  0x00000003U
-#define LP_IO_LP_GPIO7_FUN_DRV_S  10
-/** LP_IO_LP_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0;
- *  need des
- */
-#define LP_IO_LP_GPIO7_MCU_SEL    0x00000007U
-#define LP_IO_LP_GPIO7_MCU_SEL_M  (LP_IO_LP_GPIO7_MCU_SEL_V << LP_IO_LP_GPIO7_MCU_SEL_S)
-#define LP_IO_LP_GPIO7_MCU_SEL_V  0x00000007U
-#define LP_IO_LP_GPIO7_MCU_SEL_S  12
-
-/** LP_IO_STATUS_INTERRUPT_REG register
- *  need des
- */
-#define LP_IO_STATUS_INTERRUPT_REG (DR_REG_LP_IO_BASE + 0x68)
-/** LP_IO_STATUS_INTERRUPT_NEXT : RO; bitpos: [7:0]; default: 0;
- *  need des
- */
-#define LP_IO_STATUS_INTERRUPT_NEXT    0x000000FFU
-#define LP_IO_STATUS_INTERRUPT_NEXT_M  (LP_IO_STATUS_INTERRUPT_NEXT_V << LP_IO_STATUS_INTERRUPT_NEXT_S)
-#define LP_IO_STATUS_INTERRUPT_NEXT_V  0x000000FFU
-#define LP_IO_STATUS_INTERRUPT_NEXT_S  0
-
-/** LP_IO_DEBUG_SEL0_REG register
- *  need des
- */
-#define LP_IO_DEBUG_SEL0_REG (DR_REG_LP_IO_BASE + 0x6c)
-/** LP_IO_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL0    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL0_M  (LP_IO_LP_DEBUG_SEL0_V << LP_IO_LP_DEBUG_SEL0_S)
-#define LP_IO_LP_DEBUG_SEL0_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL0_S  0
-/** LP_IO_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL1    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL1_M  (LP_IO_LP_DEBUG_SEL1_V << LP_IO_LP_DEBUG_SEL1_S)
-#define LP_IO_LP_DEBUG_SEL1_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL1_S  7
-/** LP_IO_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL2    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL2_M  (LP_IO_LP_DEBUG_SEL2_V << LP_IO_LP_DEBUG_SEL2_S)
-#define LP_IO_LP_DEBUG_SEL2_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL2_S  14
-/** LP_IO_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL3    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL3_M  (LP_IO_LP_DEBUG_SEL3_V << LP_IO_LP_DEBUG_SEL3_S)
-#define LP_IO_LP_DEBUG_SEL3_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL3_S  21
-
-/** LP_IO_DEBUG_SEL1_REG register
- *  need des
- */
-#define LP_IO_DEBUG_SEL1_REG (DR_REG_LP_IO_BASE + 0x70)
-/** LP_IO_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0;
- *  need des
- */
-#define LP_IO_LP_DEBUG_SEL4    0x0000007FU
-#define LP_IO_LP_DEBUG_SEL4_M  (LP_IO_LP_DEBUG_SEL4_V << LP_IO_LP_DEBUG_SEL4_S)
-#define LP_IO_LP_DEBUG_SEL4_V  0x0000007FU
-#define LP_IO_LP_DEBUG_SEL4_S  0
-
-/** LP_IO_LPI2C_REG register
- *  need des
- */
-#define LP_IO_LPI2C_REG (DR_REG_LP_IO_BASE + 0x74)
-/** LP_IO_LP_I2C_SDA_IE : R/W; bitpos: [30]; default: 1;
- *  need des
- */
-#define LP_IO_LP_I2C_SDA_IE    (BIT(30))
-#define LP_IO_LP_I2C_SDA_IE_M  (LP_IO_LP_I2C_SDA_IE_V << LP_IO_LP_I2C_SDA_IE_S)
-#define LP_IO_LP_I2C_SDA_IE_V  0x00000001U
-#define LP_IO_LP_I2C_SDA_IE_S  30
-/** LP_IO_LP_I2C_SCL_IE : R/W; bitpos: [31]; default: 1;
- *  need des
- */
-#define LP_IO_LP_I2C_SCL_IE    (BIT(31))
-#define LP_IO_LP_I2C_SCL_IE_M  (LP_IO_LP_I2C_SCL_IE_V << LP_IO_LP_I2C_SCL_IE_S)
-#define LP_IO_LP_I2C_SCL_IE_V  0x00000001U
-#define LP_IO_LP_I2C_SCL_IE_S  31
-
-/** LP_IO_DATE_REG register
- *  need des
- */
-#define LP_IO_DATE_REG (DR_REG_LP_IO_BASE + 0x3fc)
-/** LP_IO_LP_IO_DATE : R/W; bitpos: [30:0]; default: 35660032;
- *  need des
- */
-#define LP_IO_LP_IO_DATE    0x7FFFFFFFU
-#define LP_IO_LP_IO_DATE_M  (LP_IO_LP_IO_DATE_V << LP_IO_LP_IO_DATE_S)
-#define LP_IO_LP_IO_DATE_V  0x7FFFFFFFU
-#define LP_IO_LP_IO_DATE_S  0
-/** LP_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need des
- */
-#define LP_IO_CLK_EN    (BIT(31))
-#define LP_IO_CLK_EN_M  (LP_IO_CLK_EN_V << LP_IO_CLK_EN_S)
-#define LP_IO_CLK_EN_V  0x00000001U
-#define LP_IO_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_io_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_io_struct.h
deleted file mode 100644
index 0a8698c5f7..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_io_struct.h
+++ /dev/null
@@ -1,740 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of out_data register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_out_data : R/W/WTC; bitpos: [7:0]; default: 0;
-         *  set lp gpio output data
-         */
-        uint32_t lp_gpio_out_data:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_data_reg_t;
-
-/** Type of out_data_w1ts register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_out_data_w1ts : WT; bitpos: [7:0]; default: 0;
-         *  set one time output data
-         */
-        uint32_t lp_gpio_out_data_w1ts:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_data_w1ts_reg_t;
-
-/** Type of out_data_w1tc register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_out_data_w1tc : WT; bitpos: [7:0]; default: 0;
-         *  clear one time output data
-         */
-        uint32_t lp_gpio_out_data_w1tc:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_data_w1tc_reg_t;
-
-/** Type of out_enable register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_enable : R/W/WTC; bitpos: [7:0]; default: 0;
-         *  set lp gpio output data
-         */
-        uint32_t lp_gpio_enable:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_enable_reg_t;
-
-/** Type of out_enable_w1ts register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_enable_w1ts : WT; bitpos: [7:0]; default: 0;
-         *  set one time output data
-         */
-        uint32_t lp_gpio_enable_w1ts:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_enable_w1ts_reg_t;
-
-/** Type of out_enable_w1tc register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_enable_w1tc : WT; bitpos: [7:0]; default: 0;
-         *  clear one time output data
-         */
-        uint32_t lp_gpio_enable_w1tc:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_out_enable_w1tc_reg_t;
-
-/** Type of status register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0;
-         *  set lp gpio output data
-         */
-        uint32_t lp_gpio_status_interrupt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_reg_t;
-
-/** Type of status_w1ts register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_status_w1ts : WT; bitpos: [7:0]; default: 0;
-         *  set one time output data
-         */
-        uint32_t lp_gpio_status_w1ts:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_w1ts_reg_t;
-
-/** Type of status_w1tc register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_status_w1tc : WT; bitpos: [7:0]; default: 0;
-         *  clear one time output data
-         */
-        uint32_t lp_gpio_status_w1tc:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_w1tc_reg_t;
-
-/** Type of in register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_in_data_next : RO; bitpos: [7:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_in_data_next:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_in_reg_t;
-
-/** Type of pin n register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_sync_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_sync_bypass:2;
-        /** lp_gpio_pad_driver : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_pad_driver:1;
-        /** lp_gpio_edge_wakeup_clr : WT; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_edge_wakeup_clr:1;
-        uint32_t reserved_4:3;
-        /** lp_gpio_int_type : R/W; bitpos: [9:7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_int_type:3;
-        /** lp_gpio_wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_wakeup_enable:1;
-        /** lp_gpio_filter_en : R/W; bitpos: [11]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_filter_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_io_pin_reg_t;
-
-/** Type of gpio n register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_mcu_oe:1;
-        /** lp_gpio_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_slp_sel:1;
-        /** lp_gpio_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_mcu_wpd:1;
-        /** lp_gpio_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_mcu_wpu:1;
-        /** lp_gpio_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_mcu_ie:1;
-        /** lp_gpio_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_mcu_drv:2;
-        /** lp_gpio_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_fun_wpd:1;
-        /** lp_gpio_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_fun_wpu:1;
-        /** lp_gpio_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_fun_ie:1;
-        /** lp_gpio_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_fun_drv:2;
-        /** lp_gpio_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio_reg_t;
-
-/** Type of gpio1 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio1_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_mcu_oe:1;
-        /** lp_gpio1_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_slp_sel:1;
-        /** lp_gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_mcu_wpd:1;
-        /** lp_gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_mcu_wpu:1;
-        /** lp_gpio1_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_mcu_ie:1;
-        /** lp_gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_mcu_drv:2;
-        /** lp_gpio1_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_fun_wpd:1;
-        /** lp_gpio1_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_fun_wpu:1;
-        /** lp_gpio1_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_fun_ie:1;
-        /** lp_gpio1_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_fun_drv:2;
-        /** lp_gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio1_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio1_reg_t;
-
-/** Type of gpio2 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio2_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_mcu_oe:1;
-        /** lp_gpio2_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_slp_sel:1;
-        /** lp_gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_mcu_wpd:1;
-        /** lp_gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_mcu_wpu:1;
-        /** lp_gpio2_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_mcu_ie:1;
-        /** lp_gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_mcu_drv:2;
-        /** lp_gpio2_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_fun_wpd:1;
-        /** lp_gpio2_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_fun_wpu:1;
-        /** lp_gpio2_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_fun_ie:1;
-        /** lp_gpio2_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_fun_drv:2;
-        /** lp_gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio2_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio2_reg_t;
-
-/** Type of gpio3 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio3_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_mcu_oe:1;
-        /** lp_gpio3_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_slp_sel:1;
-        /** lp_gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_mcu_wpd:1;
-        /** lp_gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_mcu_wpu:1;
-        /** lp_gpio3_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_mcu_ie:1;
-        /** lp_gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_mcu_drv:2;
-        /** lp_gpio3_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_fun_wpd:1;
-        /** lp_gpio3_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_fun_wpu:1;
-        /** lp_gpio3_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_fun_ie:1;
-        /** lp_gpio3_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_fun_drv:2;
-        /** lp_gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio3_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio3_reg_t;
-
-/** Type of gpio4 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio4_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_mcu_oe:1;
-        /** lp_gpio4_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_slp_sel:1;
-        /** lp_gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_mcu_wpd:1;
-        /** lp_gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_mcu_wpu:1;
-        /** lp_gpio4_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_mcu_ie:1;
-        /** lp_gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_mcu_drv:2;
-        /** lp_gpio4_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_fun_wpd:1;
-        /** lp_gpio4_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_fun_wpu:1;
-        /** lp_gpio4_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_fun_ie:1;
-        /** lp_gpio4_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_fun_drv:2;
-        /** lp_gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio4_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio4_reg_t;
-
-/** Type of gpio5 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio5_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_mcu_oe:1;
-        /** lp_gpio5_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_slp_sel:1;
-        /** lp_gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_mcu_wpd:1;
-        /** lp_gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_mcu_wpu:1;
-        /** lp_gpio5_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_mcu_ie:1;
-        /** lp_gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_mcu_drv:2;
-        /** lp_gpio5_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_fun_wpd:1;
-        /** lp_gpio5_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_fun_wpu:1;
-        /** lp_gpio5_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_fun_ie:1;
-        /** lp_gpio5_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_fun_drv:2;
-        /** lp_gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio5_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio5_reg_t;
-
-/** Type of gpio6 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio6_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_mcu_oe:1;
-        /** lp_gpio6_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_slp_sel:1;
-        /** lp_gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_mcu_wpd:1;
-        /** lp_gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_mcu_wpu:1;
-        /** lp_gpio6_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_mcu_ie:1;
-        /** lp_gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_mcu_drv:2;
-        /** lp_gpio6_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_fun_wpd:1;
-        /** lp_gpio6_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_fun_wpu:1;
-        /** lp_gpio6_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_fun_ie:1;
-        /** lp_gpio6_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_fun_drv:2;
-        /** lp_gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio6_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio6_reg_t;
-
-/** Type of gpio7 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_gpio7_mcu_oe : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_mcu_oe:1;
-        /** lp_gpio7_slp_sel : R/W; bitpos: [1]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_slp_sel:1;
-        /** lp_gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_mcu_wpd:1;
-        /** lp_gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_mcu_wpu:1;
-        /** lp_gpio7_mcu_ie : R/W; bitpos: [4]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_mcu_ie:1;
-        /** lp_gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_mcu_drv:2;
-        /** lp_gpio7_fun_wpd : R/W; bitpos: [7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_fun_wpd:1;
-        /** lp_gpio7_fun_wpu : R/W; bitpos: [8]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_fun_wpu:1;
-        /** lp_gpio7_fun_ie : R/W; bitpos: [9]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_fun_ie:1;
-        /** lp_gpio7_fun_drv : R/W; bitpos: [11:10]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_fun_drv:2;
-        /** lp_gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0;
-         *  need des
-         */
-        uint32_t lp_gpio7_mcu_sel:3;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} lp_io_gpio7_reg_t;
-
-/** Type of status_interrupt register
- *  need des
- */
-typedef union {
-    struct {
-        /** status_interrupt_next : RO; bitpos: [7:0]; default: 0;
-         *  need des
-         */
-        uint32_t status_interrupt_next:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_io_status_interrupt_reg_t;
-
-/** Type of debug_sel0 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_debug_sel0:7;
-        /** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0;
-         *  need des
-         */
-        uint32_t lp_debug_sel1:7;
-        /** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0;
-         *  need des
-         */
-        uint32_t lp_debug_sel2:7;
-        /** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0;
-         *  need des
-         */
-        uint32_t lp_debug_sel3:7;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_io_debug_sel0_reg_t;
-
-/** Type of debug_sel1 register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0;
-         *  need des
-         */
-        uint32_t lp_debug_sel4:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lp_io_debug_sel1_reg_t;
-
-/** Type of lpi2c register
- *  need des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1;
-         *  need des
-         */
-        uint32_t lp_i2c_sda_ie:1;
-        /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1;
-         *  need des
-         */
-        uint32_t lp_i2c_scl_ie:1;
-    };
-    uint32_t val;
-} lp_io_lpi2c_reg_t;
-
-/** Type of date register
- *  need des
- */
-typedef union {
-    struct {
-        /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032;
-         *  need des
-         */
-        uint32_t lp_io_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_io_date_reg_t;
-
-
-typedef struct lp_io_dev_t {
-    volatile lp_io_out_data_reg_t out_data;
-    volatile lp_io_out_data_w1ts_reg_t out_data_w1ts;
-    volatile lp_io_out_data_w1tc_reg_t out_data_w1tc;
-    volatile lp_io_out_enable_reg_t out_enable;
-    volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts;
-    volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc;
-    volatile lp_io_status_reg_t status;
-    volatile lp_io_status_w1ts_reg_t status_w1ts;
-    volatile lp_io_status_w1tc_reg_t status_w1tc;
-    volatile lp_io_in_reg_t in;
-    volatile lp_io_pin_reg_t pin[8];
-    volatile lp_io_gpio_reg_t gpio[8];
-    volatile lp_io_status_interrupt_reg_t status_interrupt;
-    volatile lp_io_debug_sel0_reg_t debug_sel0;
-    volatile lp_io_debug_sel1_reg_t debug_sel1;
-    volatile lp_io_lpi2c_reg_t lpi2c;
-    uint32_t reserved_078[225];
-    volatile lp_io_date_reg_t date;
-} lp_io_dev_t;
-
-extern lp_io_dev_t LP_IO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_tee_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_tee_reg.h
deleted file mode 100644
index 872bfbbfe1..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_tee_reg.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_TEE_M0_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0)
-/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define LP_TEE_M0_MODE    0x00000003U
-#define LP_TEE_M0_MODE_M  (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S)
-#define LP_TEE_M0_MODE_V  0x00000003U
-#define LP_TEE_M0_MODE_S  0
-/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define LP_TEE_M0_LOCK    (BIT(2))
-#define LP_TEE_M0_LOCK_M  (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S)
-#define LP_TEE_M0_LOCK_V  0x00000001U
-#define LP_TEE_M0_LOCK_S  2
-
-/** LP_TEE_CLOCK_GATE_REG register
- *  Clock gating register
- */
-#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4)
-/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define LP_TEE_CLK_EN    (BIT(0))
-#define LP_TEE_CLK_EN_M  (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S)
-#define LP_TEE_CLK_EN_V  0x00000001U
-#define LP_TEE_CLK_EN_S  0
-
-/** LP_TEE_FORCE_ACC_HP_REG register
- *  need_des
- */
-#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90)
-/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_TEE_FORCE_ACC_HPMEM_EN    (BIT(0))
-#define LP_TEE_FORCE_ACC_HPMEM_EN_M  (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S)
-#define LP_TEE_FORCE_ACC_HPMEM_EN_V  0x00000001U
-#define LP_TEE_FORCE_ACC_HPMEM_EN_S  0
-
-/** LP_TEE_DATE_REG register
- *  Version register
- */
-#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc)
-/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
- *  reg_tee_date
- */
-#define LP_TEE_DATE_REG    0x0FFFFFFFU
-#define LP_TEE_DATE_REG_M  (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S)
-#define LP_TEE_DATE_REG_V  0x0FFFFFFFU
-#define LP_TEE_DATE_REG_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_tee_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_tee_struct.h
deleted file mode 100644
index 7951c479f2..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_tee_struct.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Tee mode control register */
-/** Type of m0_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m0_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m0_mode:2;
-        /** m0_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m0 tee configuration
-         */
-        uint32_t m0_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} lp_tee_m0_mode_ctrl_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  Clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_tee_clock_gate_reg_t;
-
-
-/** Group: configure_register */
-/** Type of force_acc_hp register
- *  need_des
- */
-typedef union {
-    struct {
-        /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_acc_hpmem_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_tee_force_acc_hp_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date_reg : R/W; bitpos: [27:0]; default: 35725664;
-         *  reg_tee_date
-         */
-        uint32_t date_reg:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_tee_date_reg_t;
-
-
-typedef struct lp_tee_dev_t {
-    volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
-    volatile lp_tee_clock_gate_reg_t clock_gate;
-    uint32_t reserved_008[34];
-    volatile lp_tee_force_acc_hp_reg_t force_acc_hp;
-    uint32_t reserved_094[26];
-    volatile lp_tee_date_reg_t date;
-} lp_tee_dev_t;
-
-extern lp_tee_dev_t LP_TEE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_timer_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_timer_reg.h
deleted file mode 100644
index 7628cbf7e0..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_timer_reg.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_TIMER_TAR0_LOW_REG register
- *  need_des
- */
-#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
-/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_TAR_LOW0    0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M  (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
-#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V  0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S  0
-
-/** LP_TIMER_TAR0_HIGH_REG register
- *  need_des
- */
-#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
-/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH0    0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M  (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V  0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S  0
-/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_TAR_EN0    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_TAR_EN0_M  (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
-#define LP_TIMER_MAIN_TIMER_TAR_EN0_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_TAR_EN0_S  31
-
-/** LP_TIMER_TAR1_LOW_REG register
- *  need_des
- */
-#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
-/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_TAR_LOW1    0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M  (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
-#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V  0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S  0
-
-/** LP_TIMER_TAR1_HIGH_REG register
- *  need_des
- */
-#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
-/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH1    0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M  (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V  0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S  0
-/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_TAR_EN1    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_TAR_EN1_M  (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
-#define LP_TIMER_MAIN_TIMER_TAR_EN1_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_TAR_EN1_S  31
-
-/** LP_TIMER_UPDATE_REG register
- *  need_des
- */
-#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
-/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_UPDATE    (BIT(28))
-#define LP_TIMER_MAIN_TIMER_UPDATE_M  (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
-#define LP_TIMER_MAIN_TIMER_UPDATE_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_UPDATE_S  28
-/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_XTAL_OFF    (BIT(29))
-#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M  (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
-#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S  29
-/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_SYS_STALL    (BIT(30))
-#define LP_TIMER_MAIN_TIMER_SYS_STALL_M  (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
-#define LP_TIMER_MAIN_TIMER_SYS_STALL_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_SYS_STALL_S  30
-/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_SYS_RST    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_SYS_RST_M  (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
-#define LP_TIMER_MAIN_TIMER_SYS_RST_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_SYS_RST_S  31
-
-/** LP_TIMER_MAIN_BUF0_LOW_REG register
- *  need_des
- */
-#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
-/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_BUF0_LOW    0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M  (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
-#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V  0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S  0
-
-/** LP_TIMER_MAIN_BUF0_HIGH_REG register
- *  need_des
- */
-#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
-/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_BUF0_HIGH    0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M  (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
-#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V  0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S  0
-
-/** LP_TIMER_MAIN_BUF1_LOW_REG register
- *  need_des
- */
-#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
-/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_BUF1_LOW    0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M  (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
-#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V  0xFFFFFFFFU
-#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S  0
-
-/** LP_TIMER_MAIN_BUF1_HIGH_REG register
- *  need_des
- */
-#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
-/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_BUF1_HIGH    0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M  (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
-#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V  0x0000FFFFU
-#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S  0
-
-/** LP_TIMER_MAIN_OVERFLOW_REG register
- *  need_des
- */
-#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
-/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_ALARM_LOAD    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M  (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S)
-#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S  31
-
-/** LP_TIMER_INT_RAW_REG register
- *  need_des
- */
-#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
-/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_OVERFLOW_RAW    (BIT(30))
-#define LP_TIMER_OVERFLOW_RAW_M  (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
-#define LP_TIMER_OVERFLOW_RAW_V  0x00000001U
-#define LP_TIMER_OVERFLOW_RAW_S  30
-/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_SOC_WAKEUP_INT_RAW    (BIT(31))
-#define LP_TIMER_SOC_WAKEUP_INT_RAW_M  (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
-#define LP_TIMER_SOC_WAKEUP_INT_RAW_V  0x00000001U
-#define LP_TIMER_SOC_WAKEUP_INT_RAW_S  31
-
-/** LP_TIMER_INT_ST_REG register
- *  need_des
- */
-#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
-/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_OVERFLOW_ST    (BIT(30))
-#define LP_TIMER_OVERFLOW_ST_M  (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
-#define LP_TIMER_OVERFLOW_ST_V  0x00000001U
-#define LP_TIMER_OVERFLOW_ST_S  30
-/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_SOC_WAKEUP_INT_ST    (BIT(31))
-#define LP_TIMER_SOC_WAKEUP_INT_ST_M  (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
-#define LP_TIMER_SOC_WAKEUP_INT_ST_V  0x00000001U
-#define LP_TIMER_SOC_WAKEUP_INT_ST_S  31
-
-/** LP_TIMER_INT_ENA_REG register
- *  need_des
- */
-#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30)
-/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_OVERFLOW_ENA    (BIT(30))
-#define LP_TIMER_OVERFLOW_ENA_M  (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
-#define LP_TIMER_OVERFLOW_ENA_V  0x00000001U
-#define LP_TIMER_OVERFLOW_ENA_S  30
-/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_SOC_WAKEUP_INT_ENA    (BIT(31))
-#define LP_TIMER_SOC_WAKEUP_INT_ENA_M  (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
-#define LP_TIMER_SOC_WAKEUP_INT_ENA_V  0x00000001U
-#define LP_TIMER_SOC_WAKEUP_INT_ENA_S  31
-
-/** LP_TIMER_INT_CLR_REG register
- *  need_des
- */
-#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34)
-/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_OVERFLOW_CLR    (BIT(30))
-#define LP_TIMER_OVERFLOW_CLR_M  (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
-#define LP_TIMER_OVERFLOW_CLR_V  0x00000001U
-#define LP_TIMER_OVERFLOW_CLR_S  30
-/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_SOC_WAKEUP_INT_CLR    (BIT(31))
-#define LP_TIMER_SOC_WAKEUP_INT_CLR_M  (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
-#define LP_TIMER_SOC_WAKEUP_INT_CLR_V  0x00000001U
-#define LP_TIMER_SOC_WAKEUP_INT_CLR_S  31
-
-/** LP_TIMER_LP_INT_RAW_REG register
- *  need_des
- */
-#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38)
-/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW    (BIT(30))
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S  30
-/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_LP_INT_RAW    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M  (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
-#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S  31
-
-/** LP_TIMER_LP_INT_ST_REG register
- *  need_des
- */
-#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c)
-/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST    (BIT(30))
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S  30
-/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_LP_INT_ST    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M  (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
-#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S  31
-
-/** LP_TIMER_LP_INT_ENA_REG register
- *  need_des
- */
-#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40)
-/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA    (BIT(30))
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S  30
-/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_LP_INT_ENA    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M  (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
-#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S  31
-
-/** LP_TIMER_LP_INT_CLR_REG register
- *  need_des
- */
-#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44)
-/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR    (BIT(30))
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M  (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S  30
-/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_MAIN_TIMER_LP_INT_CLR    (BIT(31))
-#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M  (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
-#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V  0x00000001U
-#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S  31
-
-/** LP_TIMER_DATE_REG register
- *  need_des
- */
-#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc)
-/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976;
- *  need_des
- */
-#define LP_TIMER_DATE    0x7FFFFFFFU
-#define LP_TIMER_DATE_M  (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
-#define LP_TIMER_DATE_V  0x7FFFFFFFU
-#define LP_TIMER_DATE_S  0
-/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_TIMER_CLK_EN    (BIT(31))
-#define LP_TIMER_CLK_EN_M  (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S)
-#define LP_TIMER_CLK_EN_V  0x00000001U
-#define LP_TIMER_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_timer_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_timer_struct.h
deleted file mode 100644
index 2af34d6a37..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_timer_struct.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of tar_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_low : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_low:32;
-    };
-    uint32_t val;
-} lp_timer_tar_low_reg_t;
-
-/** Type of tar_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_tar_high : R/W; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_high:16;
-        uint32_t reserved_16:15;
-        /** main_timer_tar_en : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_tar_en:1;
-    };
-    uint32_t val;
-} lp_timer_tar_high_reg_t;
-
-/** Type of update register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** main_timer_update : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_update:1;
-        /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_xtal_off:1;
-        /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_sys_stall:1;
-        /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_sys_rst:1;
-    };
-    uint32_t val;
-} lp_timer_update_reg_t;
-
-/** Type of main_buf_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf_low : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf_low:32;
-    };
-    uint32_t val;
-} lp_timer_main_buf_low_reg_t;
-
-/** Type of main_buf_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf_high : RO; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf_high:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_timer_main_buf_high_reg_t;
-
-/** Type of main_buf1_low register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf1_low:32;
-    };
-    uint32_t val;
-} lp_timer_main_buf1_low_reg_t;
-
-/** Type of main_buf1_high register
- *  need_des
- */
-typedef union {
-    struct {
-        /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_buf1_high:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_timer_main_buf1_high_reg_t;
-
-/** Type of main_overflow register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** main_timer_alarm_load : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_alarm_load:1;
-    };
-    uint32_t val;
-} lp_timer_main_overflow_reg_t;
-
-/** Type of int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_raw:1;
-        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_raw:1;
-    };
-    uint32_t val;
-} lp_timer_int_raw_reg_t;
-
-/** Type of int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_st:1;
-        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_st:1;
-    };
-    uint32_t val;
-} lp_timer_int_st_reg_t;
-
-/** Type of int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_ena:1;
-        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_ena:1;
-    };
-    uint32_t val;
-} lp_timer_int_ena_reg_t;
-
-/** Type of int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** overflow_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t overflow_clr:1;
-        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_clr:1;
-    };
-    uint32_t val;
-} lp_timer_int_clr_reg_t;
-
-/** Type of lp_int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_raw:1;
-        /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_raw:1;
-    };
-    uint32_t val;
-} lp_timer_lp_int_raw_reg_t;
-
-/** Type of lp_int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_st:1;
-        /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_st:1;
-    };
-    uint32_t val;
-} lp_timer_lp_int_st_reg_t;
-
-/** Type of lp_int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_ena:1;
-        /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_ena:1;
-    };
-    uint32_t val;
-} lp_timer_lp_int_ena_reg_t;
-
-/** Type of lp_int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_overflow_lp_int_clr:1;
-        /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t main_timer_lp_int_clr:1;
-    };
-    uint32_t val;
-} lp_timer_lp_int_clr_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [30:0]; default: 34672976;
-         *  need_des
-         */
-        uint32_t date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_timer_date_reg_t;
-
-typedef struct {
-    volatile lp_timer_tar_low_reg_t lo;
-    volatile lp_timer_tar_high_reg_t hi;
-} lp_timer_target_reg_t;
-
-typedef struct {
-    volatile lp_timer_main_buf_low_reg_t lo;
-    volatile lp_timer_main_buf_high_reg_t hi;
-} lp_timer_counter_reg_t;
-
-typedef struct lp_timer_dev_t {
-    volatile lp_timer_target_reg_t target[2];
-    volatile lp_timer_update_reg_t update;
-    volatile lp_timer_counter_reg_t counter[2];
-    volatile lp_timer_main_overflow_reg_t main_overflow;
-    volatile lp_timer_int_raw_reg_t int_raw;
-    volatile lp_timer_int_st_reg_t int_st;
-    volatile lp_timer_int_ena_reg_t int_ena;
-    volatile lp_timer_int_clr_reg_t int_clr;
-    volatile lp_timer_lp_int_raw_reg_t lp_int_raw;
-    volatile lp_timer_lp_int_st_reg_t lp_int_st;
-    volatile lp_timer_lp_int_ena_reg_t lp_int_ena;
-    volatile lp_timer_lp_int_clr_reg_t lp_int_clr;
-    uint32_t reserved_048[237];
-    volatile lp_timer_date_reg_t date;
-} lp_timer_dev_t;
-
-extern lp_timer_dev_t LP_TIMER;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_uart_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_uart_reg.h
deleted file mode 100644
index a23d7aeb7b..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_uart_reg.h
+++ /dev/null
@@ -1,1381 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_UART_FIFO_REG register
- *  FIFO data register
- */
-#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0)
-/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART $n accesses FIFO via this register.
- */
-#define LP_UART_RXFIFO_RD_BYTE    0x000000FFU
-#define LP_UART_RXFIFO_RD_BYTE_M  (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S)
-#define LP_UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define LP_UART_RXFIFO_RD_BYTE_S  0
-
-/** LP_UART_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4)
-/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define LP_UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_RAW_M  (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S)
-#define LP_UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_RAW_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define LP_UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_M  (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S)
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define LP_UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_RAW_M  (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S)
-#define LP_UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_RAW_S  2
-/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define LP_UART_FRM_ERR_INT_RAW    (BIT(3))
-#define LP_UART_FRM_ERR_INT_RAW_M  (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S)
-#define LP_UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_RAW_S  3
-/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define LP_UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_RAW_M  (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S)
-#define LP_UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_RAW_S  4
-/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define LP_UART_DSR_CHG_INT_RAW    (BIT(5))
-#define LP_UART_DSR_CHG_INT_RAW_M  (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S)
-#define LP_UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_RAW_S  5
-/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define LP_UART_CTS_CHG_INT_RAW    (BIT(6))
-#define LP_UART_CTS_CHG_INT_RAW_M  (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S)
-#define LP_UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_RAW_S  6
-/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define LP_UART_BRK_DET_INT_RAW    (BIT(7))
-#define LP_UART_BRK_DET_INT_RAW_M  (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S)
-#define LP_UART_BRK_DET_INT_RAW_V  0x00000001U
-#define LP_UART_BRK_DET_INT_RAW_S  7
-/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define LP_UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_RAW_M  (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S)
-#define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
-/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define LP_UART_SW_XON_INT_RAW    (BIT(9))
-#define LP_UART_SW_XON_INT_RAW_M  (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S)
-#define LP_UART_SW_XON_INT_RAW_V  0x00000001U
-#define LP_UART_SW_XON_INT_RAW_S  9
-/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define LP_UART_SW_XOFF_INT_RAW    (BIT(10))
-#define LP_UART_SW_XOFF_INT_RAW_M  (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S)
-#define LP_UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_RAW_S  10
-/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define LP_UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_RAW_M  (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S)
-#define LP_UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_RAW_S  11
-/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters after all data in Tx-FIFO are sent.
- */
-#define LP_UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_RAW_M  (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S)
-#define LP_UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_RAW_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M  (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define LP_UART_TX_DONE_INT_RAW    (BIT(14))
-#define LP_UART_TX_DONE_INT_RAW_M  (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S)
-#define LP_UART_TX_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_DONE_INT_RAW_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M  (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define LP_UART_WAKEUP_INT_RAW    (BIT(19))
-#define LP_UART_WAKEUP_INT_RAW_M  (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S)
-#define LP_UART_WAKEUP_INT_RAW_V  0x00000001U
-#define LP_UART_WAKEUP_INT_RAW_S  19
-
-/** LP_UART_INT_ST_REG register
- *  Masked interrupt status
- */
-#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8)
-/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_ST_M  (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S)
-#define LP_UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_ST_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_ST_M  (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S)
-#define LP_UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_ST_S  1
-/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define LP_UART_PARITY_ERR_INT_ST    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_ST_M  (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S)
-#define LP_UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_ST_S  2
-/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define LP_UART_FRM_ERR_INT_ST    (BIT(3))
-#define LP_UART_FRM_ERR_INT_ST_M  (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S)
-#define LP_UART_FRM_ERR_INT_ST_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_ST_S  3
-/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_ST_M  (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S)
-#define LP_UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_ST_S  4
-/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define LP_UART_DSR_CHG_INT_ST    (BIT(5))
-#define LP_UART_DSR_CHG_INT_ST_M  (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S)
-#define LP_UART_DSR_CHG_INT_ST_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_ST_S  5
-/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define LP_UART_CTS_CHG_INT_ST    (BIT(6))
-#define LP_UART_CTS_CHG_INT_ST_M  (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S)
-#define LP_UART_CTS_CHG_INT_ST_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_ST_S  6
-/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define LP_UART_BRK_DET_INT_ST    (BIT(7))
-#define LP_UART_BRK_DET_INT_ST_M  (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S)
-#define LP_UART_BRK_DET_INT_ST_V  0x00000001U
-#define LP_UART_BRK_DET_INT_ST_S  7
-/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_ST_M  (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S)
-#define LP_UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_ST_S  8
-/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define LP_UART_SW_XON_INT_ST    (BIT(9))
-#define LP_UART_SW_XON_INT_ST_M  (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S)
-#define LP_UART_SW_XON_INT_ST_V  0x00000001U
-#define LP_UART_SW_XON_INT_ST_S  9
-/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define LP_UART_SW_XOFF_INT_ST    (BIT(10))
-#define LP_UART_SW_XOFF_INT_ST_M  (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S)
-#define LP_UART_SW_XOFF_INT_ST_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_ST_S  10
-/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define LP_UART_GLITCH_DET_INT_ST    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_ST_M  (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S)
-#define LP_UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_ST_S  11
-/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define LP_UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_ST_M  (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S)
-#define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_ST_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define LP_UART_TX_DONE_INT_ST    (BIT(14))
-#define LP_UART_TX_DONE_INT_ST_M  (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S)
-#define LP_UART_TX_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_DONE_INT_ST_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M  (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define LP_UART_WAKEUP_INT_ST    (BIT(19))
-#define LP_UART_WAKEUP_INT_ST_M  (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S)
-#define LP_UART_WAKEUP_INT_ST_V  0x00000001U
-#define LP_UART_WAKEUP_INT_ST_S  19
-
-/** LP_UART_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc)
-/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define LP_UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_ENA_M  (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S)
-#define LP_UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_ENA_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_M  (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S)
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define LP_UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_ENA_M  (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S)
-#define LP_UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_ENA_S  2
-/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define LP_UART_FRM_ERR_INT_ENA    (BIT(3))
-#define LP_UART_FRM_ERR_INT_ENA_M  (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S)
-#define LP_UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_ENA_S  3
-/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define LP_UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_ENA_M  (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S)
-#define LP_UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_ENA_S  4
-/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define LP_UART_DSR_CHG_INT_ENA    (BIT(5))
-#define LP_UART_DSR_CHG_INT_ENA_M  (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S)
-#define LP_UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_ENA_S  5
-/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define LP_UART_CTS_CHG_INT_ENA    (BIT(6))
-#define LP_UART_CTS_CHG_INT_ENA_M  (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S)
-#define LP_UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_ENA_S  6
-/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define LP_UART_BRK_DET_INT_ENA    (BIT(7))
-#define LP_UART_BRK_DET_INT_ENA_M  (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S)
-#define LP_UART_BRK_DET_INT_ENA_V  0x00000001U
-#define LP_UART_BRK_DET_INT_ENA_S  7
-/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define LP_UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_ENA_M  (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S)
-#define LP_UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_ENA_S  8
-/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define LP_UART_SW_XON_INT_ENA    (BIT(9))
-#define LP_UART_SW_XON_INT_ENA_M  (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S)
-#define LP_UART_SW_XON_INT_ENA_V  0x00000001U
-#define LP_UART_SW_XON_INT_ENA_S  9
-/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define LP_UART_SW_XOFF_INT_ENA    (BIT(10))
-#define LP_UART_SW_XOFF_INT_ENA_M  (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S)
-#define LP_UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_ENA_S  10
-/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define LP_UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_ENA_M  (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S)
-#define LP_UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_ENA_S  11
-/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define LP_UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_ENA_M  (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S)
-#define LP_UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_ENA_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define LP_UART_TX_DONE_INT_ENA    (BIT(14))
-#define LP_UART_TX_DONE_INT_ENA_M  (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S)
-#define LP_UART_TX_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_DONE_INT_ENA_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M  (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define LP_UART_WAKEUP_INT_ENA    (BIT(19))
-#define LP_UART_WAKEUP_INT_ENA_M  (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S)
-#define LP_UART_WAKEUP_INT_ENA_V  0x00000001U
-#define LP_UART_WAKEUP_INT_ENA_S  19
-
-/** LP_UART_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10)
-/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_CLR_M  (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S)
-#define LP_UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_CLR_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_M  (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S)
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define LP_UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_CLR_M  (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S)
-#define LP_UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_CLR_S  2
-/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define LP_UART_FRM_ERR_INT_CLR    (BIT(3))
-#define LP_UART_FRM_ERR_INT_CLR_M  (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S)
-#define LP_UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_CLR_S  3
-/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_CLR_M  (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S)
-#define LP_UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_CLR_S  4
-/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define LP_UART_DSR_CHG_INT_CLR    (BIT(5))
-#define LP_UART_DSR_CHG_INT_CLR_M  (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S)
-#define LP_UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_CLR_S  5
-/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define LP_UART_CTS_CHG_INT_CLR    (BIT(6))
-#define LP_UART_CTS_CHG_INT_CLR_M  (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S)
-#define LP_UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_CLR_S  6
-/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define LP_UART_BRK_DET_INT_CLR    (BIT(7))
-#define LP_UART_BRK_DET_INT_CLR_M  (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S)
-#define LP_UART_BRK_DET_INT_CLR_V  0x00000001U
-#define LP_UART_BRK_DET_INT_CLR_S  7
-/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_CLR_M  (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S)
-#define LP_UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_CLR_S  8
-/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define LP_UART_SW_XON_INT_CLR    (BIT(9))
-#define LP_UART_SW_XON_INT_CLR_M  (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S)
-#define LP_UART_SW_XON_INT_CLR_V  0x00000001U
-#define LP_UART_SW_XON_INT_CLR_S  9
-/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define LP_UART_SW_XOFF_INT_CLR    (BIT(10))
-#define LP_UART_SW_XOFF_INT_CLR_M  (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S)
-#define LP_UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_CLR_S  10
-/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define LP_UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_CLR_M  (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S)
-#define LP_UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_CLR_S  11
-/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define LP_UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_CLR_M  (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S)
-#define LP_UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_CLR_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M  (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define LP_UART_TX_DONE_INT_CLR    (BIT(14))
-#define LP_UART_TX_DONE_INT_CLR_M  (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S)
-#define LP_UART_TX_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_DONE_INT_CLR_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M  (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define LP_UART_WAKEUP_INT_CLR    (BIT(19))
-#define LP_UART_WAKEUP_INT_CLR_M  (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S)
-#define LP_UART_WAKEUP_INT_CLR_V  0x00000001U
-#define LP_UART_WAKEUP_INT_CLR_S  19
-
-/** LP_UART_CLKDIV_SYNC_REG register
- *  Clock divider configuration
- */
-#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14)
-/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define LP_UART_CLKDIV    0x00000FFFU
-#define LP_UART_CLKDIV_M  (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S)
-#define LP_UART_CLKDIV_V  0x00000FFFU
-#define LP_UART_CLKDIV_S  0
-/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define LP_UART_CLKDIV_FRAG    0x0000000FU
-#define LP_UART_CLKDIV_FRAG_M  (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S)
-#define LP_UART_CLKDIV_FRAG_V  0x0000000FU
-#define LP_UART_CLKDIV_FRAG_S  20
-
-/** LP_UART_RX_FILT_REG register
- *  Rx Filter configuration
- */
-#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18)
-/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value the pulse is ignored.
- */
-#define LP_UART_GLITCH_FILT    0x000000FFU
-#define LP_UART_GLITCH_FILT_M  (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S)
-#define LP_UART_GLITCH_FILT_V  0x000000FFU
-#define LP_UART_GLITCH_FILT_S  0
-/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define LP_UART_GLITCH_FILT_EN    (BIT(8))
-#define LP_UART_GLITCH_FILT_EN_M  (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S)
-#define LP_UART_GLITCH_FILT_EN_V  0x00000001U
-#define LP_UART_GLITCH_FILT_EN_S  8
-
-/** LP_UART_STATUS_REG register
- *  UART status register
- */
-#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c)
-/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define LP_UART_RXFIFO_CNT    0x0000001FU
-#define LP_UART_RXFIFO_CNT_M  (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S)
-#define LP_UART_RXFIFO_CNT_V  0x0000001FU
-#define LP_UART_RXFIFO_CNT_S  3
-/** LP_UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define LP_UART_DSRN    (BIT(13))
-#define LP_UART_DSRN_M  (LP_UART_DSRN_V << LP_UART_DSRN_S)
-#define LP_UART_DSRN_V  0x00000001U
-#define LP_UART_DSRN_S  13
-/** LP_UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define LP_UART_CTSN    (BIT(14))
-#define LP_UART_CTSN_M  (LP_UART_CTSN_V << LP_UART_CTSN_S)
-#define LP_UART_CTSN_V  0x00000001U
-#define LP_UART_CTSN_S  14
-/** LP_UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define LP_UART_RXD    (BIT(15))
-#define LP_UART_RXD_M  (LP_UART_RXD_V << LP_UART_RXD_S)
-#define LP_UART_RXD_V  0x00000001U
-#define LP_UART_RXD_S  15
-/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define LP_UART_TXFIFO_CNT    0x0000001FU
-#define LP_UART_TXFIFO_CNT_M  (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S)
-#define LP_UART_TXFIFO_CNT_V  0x0000001FU
-#define LP_UART_TXFIFO_CNT_S  19
-/** LP_UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define LP_UART_DTRN    (BIT(29))
-#define LP_UART_DTRN_M  (LP_UART_DTRN_V << LP_UART_DTRN_S)
-#define LP_UART_DTRN_V  0x00000001U
-#define LP_UART_DTRN_S  29
-/** LP_UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define LP_UART_RTSN    (BIT(30))
-#define LP_UART_RTSN_M  (LP_UART_RTSN_V << LP_UART_RTSN_S)
-#define LP_UART_RTSN_V  0x00000001U
-#define LP_UART_RTSN_S  30
-/** LP_UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define LP_UART_TXD    (BIT(31))
-#define LP_UART_TXD_M  (LP_UART_TXD_V << LP_UART_TXD_S)
-#define LP_UART_TXD_V  0x00000001U
-#define LP_UART_TXD_S  31
-
-/** LP_UART_CONF0_SYNC_REG register
- *  Configuration register 0
- */
-#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20)
-/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define LP_UART_PARITY    (BIT(0))
-#define LP_UART_PARITY_M  (LP_UART_PARITY_V << LP_UART_PARITY_S)
-#define LP_UART_PARITY_V  0x00000001U
-#define LP_UART_PARITY_S  0
-/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define LP_UART_PARITY_EN    (BIT(1))
-#define LP_UART_PARITY_EN_M  (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S)
-#define LP_UART_PARITY_EN_V  0x00000001U
-#define LP_UART_PARITY_EN_S  1
-/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define LP_UART_BIT_NUM    0x00000003U
-#define LP_UART_BIT_NUM_M  (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S)
-#define LP_UART_BIT_NUM_V  0x00000003U
-#define LP_UART_BIT_NUM_S  2
-/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define LP_UART_STOP_BIT_NUM    0x00000003U
-#define LP_UART_STOP_BIT_NUM_M  (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S)
-#define LP_UART_STOP_BIT_NUM_V  0x00000003U
-#define LP_UART_STOP_BIT_NUM_S  4
-/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define LP_UART_TXD_BRK    (BIT(6))
-#define LP_UART_TXD_BRK_M  (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S)
-#define LP_UART_TXD_BRK_V  0x00000001U
-#define LP_UART_TXD_BRK_S  6
-/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define LP_UART_LOOPBACK    (BIT(12))
-#define LP_UART_LOOPBACK_M  (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S)
-#define LP_UART_LOOPBACK_V  0x00000001U
-#define LP_UART_LOOPBACK_S  12
-/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define LP_UART_TX_FLOW_EN    (BIT(13))
-#define LP_UART_TX_FLOW_EN_M  (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S)
-#define LP_UART_TX_FLOW_EN_V  0x00000001U
-#define LP_UART_TX_FLOW_EN_S  13
-/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define LP_UART_RXD_INV    (BIT(15))
-#define LP_UART_RXD_INV_M  (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S)
-#define LP_UART_RXD_INV_V  0x00000001U
-#define LP_UART_RXD_INV_S  15
-/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define LP_UART_TXD_INV    (BIT(16))
-#define LP_UART_TXD_INV_M  (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S)
-#define LP_UART_TXD_INV_V  0x00000001U
-#define LP_UART_TXD_INV_S  16
-/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define LP_UART_DIS_RX_DAT_OVF    (BIT(17))
-#define LP_UART_DIS_RX_DAT_OVF_M  (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S)
-#define LP_UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define LP_UART_DIS_RX_DAT_OVF_S  17
-/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define LP_UART_ERR_WR_MASK    (BIT(18))
-#define LP_UART_ERR_WR_MASK_M  (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S)
-#define LP_UART_ERR_WR_MASK_V  0x00000001U
-#define LP_UART_ERR_WR_MASK_S  18
-/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
- *  UART memory clock gate enable signal.
- */
-#define LP_UART_MEM_CLK_EN    (BIT(20))
-#define LP_UART_MEM_CLK_EN_M  (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S)
-#define LP_UART_MEM_CLK_EN_V  0x00000001U
-#define LP_UART_MEM_CLK_EN_S  20
-/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define LP_UART_SW_RTS    (BIT(21))
-#define LP_UART_SW_RTS_M  (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S)
-#define LP_UART_SW_RTS_V  0x00000001U
-#define LP_UART_SW_RTS_S  21
-/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define LP_UART_RXFIFO_RST    (BIT(22))
-#define LP_UART_RXFIFO_RST_M  (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S)
-#define LP_UART_RXFIFO_RST_V  0x00000001U
-#define LP_UART_RXFIFO_RST_S  22
-/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define LP_UART_TXFIFO_RST    (BIT(23))
-#define LP_UART_TXFIFO_RST_M  (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S)
-#define LP_UART_TXFIFO_RST_V  0x00000001U
-#define LP_UART_TXFIFO_RST_S  23
-
-/** LP_UART_CONF1_REG register
- *  Configuration register 1
- */
-#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24)
-/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define LP_UART_RXFIFO_FULL_THRHD    0x0000001FU
-#define LP_UART_RXFIFO_FULL_THRHD_M  (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S)
-#define LP_UART_RXFIFO_FULL_THRHD_V  0x0000001FU
-#define LP_UART_RXFIFO_FULL_THRHD_S  3
-/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define LP_UART_TXFIFO_EMPTY_THRHD    0x0000001FU
-#define LP_UART_TXFIFO_EMPTY_THRHD_M  (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S)
-#define LP_UART_TXFIFO_EMPTY_THRHD_V  0x0000001FU
-#define LP_UART_TXFIFO_EMPTY_THRHD_S  11
-/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define LP_UART_CTS_INV    (BIT(16))
-#define LP_UART_CTS_INV_M  (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S)
-#define LP_UART_CTS_INV_V  0x00000001U
-#define LP_UART_CTS_INV_S  16
-/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define LP_UART_DSR_INV    (BIT(17))
-#define LP_UART_DSR_INV_M  (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S)
-#define LP_UART_DSR_INV_V  0x00000001U
-#define LP_UART_DSR_INV_S  17
-/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define LP_UART_RTS_INV    (BIT(18))
-#define LP_UART_RTS_INV_M  (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S)
-#define LP_UART_RTS_INV_V  0x00000001U
-#define LP_UART_RTS_INV_S  18
-/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define LP_UART_DTR_INV    (BIT(19))
-#define LP_UART_DTR_INV_M  (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S)
-#define LP_UART_DTR_INV_V  0x00000001U
-#define LP_UART_DTR_INV_S  19
-/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define LP_UART_SW_DTR    (BIT(20))
-#define LP_UART_SW_DTR_M  (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S)
-#define LP_UART_SW_DTR_V  0x00000001U
-#define LP_UART_SW_DTR_S  20
-/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define LP_UART_CLK_EN    (BIT(21))
-#define LP_UART_CLK_EN_M  (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S)
-#define LP_UART_CLK_EN_V  0x00000001U
-#define LP_UART_CLK_EN_S  21
-
-/** LP_UART_HWFC_CONF_SYNC_REG register
- *  Hardware flow-control configuration
- */
-#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c)
-/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define LP_UART_RX_FLOW_THRHD    0x0000001FU
-#define LP_UART_RX_FLOW_THRHD_M  (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S)
-#define LP_UART_RX_FLOW_THRHD_V  0x0000001FU
-#define LP_UART_RX_FLOW_THRHD_S  3
-/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define LP_UART_RX_FLOW_EN    (BIT(8))
-#define LP_UART_RX_FLOW_EN_M  (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S)
-#define LP_UART_RX_FLOW_EN_V  0x00000001U
-#define LP_UART_RX_FLOW_EN_S  8
-
-/** LP_UART_SLEEP_CONF0_REG register
- *  UART sleep configure register 0
- */
-#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30)
-/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified wake up char1 to wake up
- */
-#define LP_UART_WK_CHAR1    0x000000FFU
-#define LP_UART_WK_CHAR1_M  (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S)
-#define LP_UART_WK_CHAR1_V  0x000000FFU
-#define LP_UART_WK_CHAR1_S  0
-/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
- *  This register restores the specified wake up char2 to wake up
- */
-#define LP_UART_WK_CHAR2    0x000000FFU
-#define LP_UART_WK_CHAR2_M  (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S)
-#define LP_UART_WK_CHAR2_V  0x000000FFU
-#define LP_UART_WK_CHAR2_S  8
-/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
- *  This register restores the specified wake up char3 to wake up
- */
-#define LP_UART_WK_CHAR3    0x000000FFU
-#define LP_UART_WK_CHAR3_M  (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S)
-#define LP_UART_WK_CHAR3_V  0x000000FFU
-#define LP_UART_WK_CHAR3_S  16
-/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
- *  This register restores the specified wake up char4 to wake up
- */
-#define LP_UART_WK_CHAR4    0x000000FFU
-#define LP_UART_WK_CHAR4_M  (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S)
-#define LP_UART_WK_CHAR4_V  0x000000FFU
-#define LP_UART_WK_CHAR4_S  24
-
-/** LP_UART_SLEEP_CONF1_REG register
- *  UART sleep configure register 1
- */
-#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34)
-/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified char0 to wake up
- */
-#define LP_UART_WK_CHAR0    0x000000FFU
-#define LP_UART_WK_CHAR0_M  (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S)
-#define LP_UART_WK_CHAR0_V  0x000000FFU
-#define LP_UART_WK_CHAR0_S  0
-
-/** LP_UART_SLEEP_CONF2_REG register
- *  UART sleep configure register 2
- */
-#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38)
-/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define LP_UART_ACTIVE_THRESHOLD    0x000003FFU
-#define LP_UART_ACTIVE_THRESHOLD_M  (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S)
-#define LP_UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define LP_UART_ACTIVE_THRESHOLD_S  0
-/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1;
- *  In wake up mode 1 this field is used to set the received data number threshold to
- *  wake up chip.
- */
-#define LP_UART_RX_WAKE_UP_THRHD    0x0000001FU
-#define LP_UART_RX_WAKE_UP_THRHD_M  (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S)
-#define LP_UART_RX_WAKE_UP_THRHD_V  0x0000001FU
-#define LP_UART_RX_WAKE_UP_THRHD_S  13
-/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
- *  This register is used to select number of wake up char.
- */
-#define LP_UART_WK_CHAR_NUM    0x00000007U
-#define LP_UART_WK_CHAR_NUM_M  (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S)
-#define LP_UART_WK_CHAR_NUM_V  0x00000007U
-#define LP_UART_WK_CHAR_NUM_S  18
-/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
- *  This register is used to mask  wake up char.
- */
-#define LP_UART_WK_CHAR_MASK    0x0000001FU
-#define LP_UART_WK_CHAR_MASK_M  (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S)
-#define LP_UART_WK_CHAR_MASK_V  0x0000001FU
-#define LP_UART_WK_CHAR_MASK_S  21
-/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
- *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
- *  received data number larger than
- */
-#define LP_UART_WK_MODE_SEL    0x00000003U
-#define LP_UART_WK_MODE_SEL_M  (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S)
-#define LP_UART_WK_MODE_SEL_V  0x00000003U
-#define LP_UART_WK_MODE_SEL_S  26
-
-/** LP_UART_SWFC_CONF0_SYNC_REG register
- *  Software flow-control character configuration
- */
-#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c)
-/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define LP_UART_XON_CHAR    0x000000FFU
-#define LP_UART_XON_CHAR_M  (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S)
-#define LP_UART_XON_CHAR_V  0x000000FFU
-#define LP_UART_XON_CHAR_S  0
-/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define LP_UART_XOFF_CHAR    0x000000FFU
-#define LP_UART_XOFF_CHAR_M  (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S)
-#define LP_UART_XOFF_CHAR_V  0x000000FFU
-#define LP_UART_XOFF_CHAR_S  8
-/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
- *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
- *  this status, UART Tx can not transmit XOFF even the received data number is larger
- *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
- *  UART Tx is disabled.
- */
-#define LP_UART_XON_XOFF_STILL_SEND    (BIT(16))
-#define LP_UART_XON_XOFF_STILL_SEND_M  (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S)
-#define LP_UART_XON_XOFF_STILL_SEND_V  0x00000001U
-#define LP_UART_XON_XOFF_STILL_SEND_S  16
-/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define LP_UART_SW_FLOW_CON_EN    (BIT(17))
-#define LP_UART_SW_FLOW_CON_EN_M  (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S)
-#define LP_UART_SW_FLOW_CON_EN_V  0x00000001U
-#define LP_UART_SW_FLOW_CON_EN_S  17
-/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define LP_UART_XONOFF_DEL    (BIT(18))
-#define LP_UART_XONOFF_DEL_M  (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S)
-#define LP_UART_XONOFF_DEL_V  0x00000001U
-#define LP_UART_XONOFF_DEL_S  18
-/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define LP_UART_FORCE_XON    (BIT(19))
-#define LP_UART_FORCE_XON_M  (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S)
-#define LP_UART_FORCE_XON_V  0x00000001U
-#define LP_UART_FORCE_XON_S  19
-/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define LP_UART_FORCE_XOFF    (BIT(20))
-#define LP_UART_FORCE_XOFF_M  (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S)
-#define LP_UART_FORCE_XOFF_V  0x00000001U
-#define LP_UART_FORCE_XOFF_S  20
-/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define LP_UART_SEND_XON    (BIT(21))
-#define LP_UART_SEND_XON_M  (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S)
-#define LP_UART_SEND_XON_V  0x00000001U
-#define LP_UART_SEND_XON_S  21
-/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define LP_UART_SEND_XOFF    (BIT(22))
-#define LP_UART_SEND_XOFF_M  (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S)
-#define LP_UART_SEND_XOFF_V  0x00000001U
-#define LP_UART_SEND_XOFF_S  22
-
-/** LP_UART_SWFC_CONF1_REG register
- *  Software flow-control character configuration
- */
-#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40)
-/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xon char.
- */
-#define LP_UART_XON_THRESHOLD    0x0000001FU
-#define LP_UART_XON_THRESHOLD_M  (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S)
-#define LP_UART_XON_THRESHOLD_V  0x0000001FU
-#define LP_UART_XON_THRESHOLD_S  3
-/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
- */
-#define LP_UART_XOFF_THRESHOLD    0x0000001FU
-#define LP_UART_XOFF_THRESHOLD_M  (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S)
-#define LP_UART_XOFF_THRESHOLD_V  0x0000001FU
-#define LP_UART_XOFF_THRESHOLD_S  11
-
-/** LP_UART_TXBRK_CONF_SYNC_REG register
- *  Tx Break character configuration
- */
-#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44)
-/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define LP_UART_TX_BRK_NUM    0x000000FFU
-#define LP_UART_TX_BRK_NUM_M  (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S)
-#define LP_UART_TX_BRK_NUM_V  0x000000FFU
-#define LP_UART_TX_BRK_NUM_S  0
-
-/** LP_UART_IDLE_CONF_SYNC_REG register
- *  Frame-end idle configuration
- */
-#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48)
-/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define LP_UART_RX_IDLE_THRHD    0x000003FFU
-#define LP_UART_RX_IDLE_THRHD_M  (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S)
-#define LP_UART_RX_IDLE_THRHD_V  0x000003FFU
-#define LP_UART_RX_IDLE_THRHD_S  0
-/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define LP_UART_TX_IDLE_NUM    0x000003FFU
-#define LP_UART_TX_IDLE_NUM_M  (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S)
-#define LP_UART_TX_IDLE_NUM_V  0x000003FFU
-#define LP_UART_TX_IDLE_NUM_S  10
-
-/** LP_UART_RS485_CONF_SYNC_REG register
- *  RS485 mode configuration
- */
-#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c)
-/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define LP_UART_DL0_EN    (BIT(1))
-#define LP_UART_DL0_EN_M  (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S)
-#define LP_UART_DL0_EN_V  0x00000001U
-#define LP_UART_DL0_EN_S  1
-/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define LP_UART_DL1_EN    (BIT(2))
-#define LP_UART_DL1_EN_M  (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S)
-#define LP_UART_DL1_EN_V  0x00000001U
-#define LP_UART_DL1_EN_S  2
-
-/** LP_UART_AT_CMD_PRECNT_SYNC_REG register
- *  Pre-sequence timing configuration
- */
-#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50)
-/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define LP_UART_PRE_IDLE_NUM    0x0000FFFFU
-#define LP_UART_PRE_IDLE_NUM_M  (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S)
-#define LP_UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define LP_UART_PRE_IDLE_NUM_S  0
-
-/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register
- *  Post-sequence timing configuration
- */
-#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54)
-/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define LP_UART_POST_IDLE_NUM    0x0000FFFFU
-#define LP_UART_POST_IDLE_NUM_M  (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S)
-#define LP_UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define LP_UART_POST_IDLE_NUM_S  0
-
-/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register
- *  Timeout configuration
- */
-#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58)
-/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define LP_UART_RX_GAP_TOUT    0x0000FFFFU
-#define LP_UART_RX_GAP_TOUT_M  (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S)
-#define LP_UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define LP_UART_RX_GAP_TOUT_S  0
-
-/** LP_UART_AT_CMD_CHAR_SYNC_REG register
- *  AT escape sequence detection configuration
- */
-#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c)
-/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define LP_UART_AT_CMD_CHAR    0x000000FFU
-#define LP_UART_AT_CMD_CHAR_M  (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S)
-#define LP_UART_AT_CMD_CHAR_V  0x000000FFU
-#define LP_UART_AT_CMD_CHAR_S  0
-/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define LP_UART_CHAR_NUM    0x000000FFU
-#define LP_UART_CHAR_NUM_M  (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S)
-#define LP_UART_CHAR_NUM_V  0x000000FFU
-#define LP_UART_CHAR_NUM_S  8
-
-/** LP_UART_MEM_CONF_REG register
- *  UART memory power configuration
- */
-#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60)
-/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define LP_UART_MEM_FORCE_PD    (BIT(25))
-#define LP_UART_MEM_FORCE_PD_M  (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S)
-#define LP_UART_MEM_FORCE_PD_V  0x00000001U
-#define LP_UART_MEM_FORCE_PD_S  25
-/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define LP_UART_MEM_FORCE_PU    (BIT(26))
-#define LP_UART_MEM_FORCE_PU_M  (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S)
-#define LP_UART_MEM_FORCE_PU_V  0x00000001U
-#define LP_UART_MEM_FORCE_PU_S  26
-
-/** LP_UART_TOUT_CONF_SYNC_REG register
- *  UART threshold and allocation configuration
- */
-#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
-/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define LP_UART_RX_TOUT_EN    (BIT(0))
-#define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
-#define LP_UART_RX_TOUT_EN_V  0x00000001U
-#define LP_UART_RX_TOUT_EN_S  0
-/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define LP_UART_RX_TOUT_FLOW_DIS    (BIT(1))
-#define LP_UART_RX_TOUT_FLOW_DIS_M  (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S)
-#define LP_UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define LP_UART_RX_TOUT_FLOW_DIS_S  1
-/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define LP_UART_RX_TOUT_THRHD    0x000003FFU
-#define LP_UART_RX_TOUT_THRHD_M  (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S)
-#define LP_UART_RX_TOUT_THRHD_V  0x000003FFU
-#define LP_UART_RX_TOUT_THRHD_S  2
-
-/** LP_UART_MEM_TX_STATUS_REG register
- *  Tx-SRAM write and read offset address.
- */
-#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68)
-/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0;
- *  This register stores the offset write address in Tx-SRAM.
- */
-#define LP_UART_TX_SRAM_WADDR    0x0000001FU
-#define LP_UART_TX_SRAM_WADDR_M  (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S)
-#define LP_UART_TX_SRAM_WADDR_V  0x0000001FU
-#define LP_UART_TX_SRAM_WADDR_S  3
-/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0;
- *  This register stores the offset read address in Tx-SRAM.
- */
-#define LP_UART_TX_SRAM_RADDR    0x0000001FU
-#define LP_UART_TX_SRAM_RADDR_M  (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S)
-#define LP_UART_TX_SRAM_RADDR_V  0x0000001FU
-#define LP_UART_TX_SRAM_RADDR_S  12
-
-/** LP_UART_MEM_RX_STATUS_REG register
- *  Rx-SRAM write and read offset address.
- */
-#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c)
-/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16;
- *  This register stores the offset read address in RX-SRAM.
- */
-#define LP_UART_RX_SRAM_RADDR    0x0000001FU
-#define LP_UART_RX_SRAM_RADDR_M  (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S)
-#define LP_UART_RX_SRAM_RADDR_V  0x0000001FU
-#define LP_UART_RX_SRAM_RADDR_S  3
-/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16;
- *  This register stores the offset write address in Rx-SRAM.
- */
-#define LP_UART_RX_SRAM_WADDR    0x0000001FU
-#define LP_UART_RX_SRAM_WADDR_M  (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S)
-#define LP_UART_RX_SRAM_WADDR_V  0x0000001FU
-#define LP_UART_RX_SRAM_WADDR_S  12
-
-/** LP_UART_FSM_STATUS_REG register
- *  UART transmit and receive status.
- */
-#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70)
-/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define LP_UART_ST_URX_OUT    0x0000000FU
-#define LP_UART_ST_URX_OUT_M  (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S)
-#define LP_UART_ST_URX_OUT_V  0x0000000FU
-#define LP_UART_ST_URX_OUT_S  0
-/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define LP_UART_ST_UTX_OUT    0x0000000FU
-#define LP_UART_ST_UTX_OUT_M  (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S)
-#define LP_UART_ST_UTX_OUT_V  0x0000000FU
-#define LP_UART_ST_UTX_OUT_S  4
-
-/** LP_UART_CLK_CONF_REG register
- *  UART core clock configuration
- */
-#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
-/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor.
- */
-#define LP_UART_SCLK_DIV_B    0x0000003FU
-#define LP_UART_SCLK_DIV_B_M  (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S)
-#define LP_UART_SCLK_DIV_B_V  0x0000003FU
-#define LP_UART_SCLK_DIV_B_S  0
-/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor.
- */
-#define LP_UART_SCLK_DIV_A    0x0000003FU
-#define LP_UART_SCLK_DIV_A_M  (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S)
-#define LP_UART_SCLK_DIV_A_V  0x0000003FU
-#define LP_UART_SCLK_DIV_A_S  6
-/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
- *  The integral part of the frequency divider factor.
- */
-#define LP_UART_SCLK_DIV_NUM    0x000000FFU
-#define LP_UART_SCLK_DIV_NUM_M  (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
-#define LP_UART_SCLK_DIV_NUM_V  0x000000FFU
-#define LP_UART_SCLK_DIV_NUM_S  12
-/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
- */
-#define LP_UART_SCLK_SEL    0x00000003U
-#define LP_UART_SCLK_SEL_M  (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S)
-#define LP_UART_SCLK_SEL_V  0x00000003U
-#define LP_UART_SCLK_SEL_S  20
-/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set this bit to enable UART Tx/Rx clock.
- */
-#define LP_UART_SCLK_EN    (BIT(22))
-#define LP_UART_SCLK_EN_M  (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S)
-#define LP_UART_SCLK_EN_V  0x00000001U
-#define LP_UART_SCLK_EN_S  22
-/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
- */
-#define LP_UART_RST_CORE    (BIT(23))
-#define LP_UART_RST_CORE_M  (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S)
-#define LP_UART_RST_CORE_V  0x00000001U
-#define LP_UART_RST_CORE_S  23
-/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
- *  Set this bit to enable UART Tx clock.
- */
-#define LP_UART_TX_SCLK_EN    (BIT(24))
-#define LP_UART_TX_SCLK_EN_M  (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S)
-#define LP_UART_TX_SCLK_EN_V  0x00000001U
-#define LP_UART_TX_SCLK_EN_S  24
-/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
- *  Set this bit to enable UART Rx clock.
- */
-#define LP_UART_RX_SCLK_EN    (BIT(25))
-#define LP_UART_RX_SCLK_EN_M  (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S)
-#define LP_UART_RX_SCLK_EN_V  0x00000001U
-#define LP_UART_RX_SCLK_EN_S  25
-/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx.
- */
-#define LP_UART_TX_RST_CORE    (BIT(26))
-#define LP_UART_TX_RST_CORE_M  (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S)
-#define LP_UART_TX_RST_CORE_V  0x00000001U
-#define LP_UART_TX_RST_CORE_S  26
-/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Rx.
- */
-#define LP_UART_RX_RST_CORE    (BIT(27))
-#define LP_UART_RX_RST_CORE_M  (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S)
-#define LP_UART_RX_RST_CORE_V  0x00000001U
-#define LP_UART_RX_RST_CORE_S  27
-
-/** LP_UART_DATE_REG register
- *  UART Version register
- */
-#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c)
-/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 35656288;
- *  This is the version register.
- */
-#define LP_UART_DATE    0xFFFFFFFFU
-#define LP_UART_DATE_M  (LP_UART_DATE_V << LP_UART_DATE_S)
-#define LP_UART_DATE_V  0xFFFFFFFFU
-#define LP_UART_DATE_S  0
-
-/** LP_UART_AFIFO_STATUS_REG register
- *  UART AFIFO Status
- */
-#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90)
-/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
- *  Full signal of APB TX AFIFO.
- */
-#define LP_UART_TX_AFIFO_FULL    (BIT(0))
-#define LP_UART_TX_AFIFO_FULL_M  (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S)
-#define LP_UART_TX_AFIFO_FULL_V  0x00000001U
-#define LP_UART_TX_AFIFO_FULL_S  0
-/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
- *  Empty signal of APB TX AFIFO.
- */
-#define LP_UART_TX_AFIFO_EMPTY    (BIT(1))
-#define LP_UART_TX_AFIFO_EMPTY_M  (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S)
-#define LP_UART_TX_AFIFO_EMPTY_V  0x00000001U
-#define LP_UART_TX_AFIFO_EMPTY_S  1
-/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
- *  Full signal of APB RX AFIFO.
- */
-#define LP_UART_RX_AFIFO_FULL    (BIT(2))
-#define LP_UART_RX_AFIFO_FULL_M  (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S)
-#define LP_UART_RX_AFIFO_FULL_V  0x00000001U
-#define LP_UART_RX_AFIFO_FULL_S  2
-/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
- *  Empty signal of APB RX AFIFO.
- */
-#define LP_UART_RX_AFIFO_EMPTY    (BIT(3))
-#define LP_UART_RX_AFIFO_EMPTY_M  (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S)
-#define LP_UART_RX_AFIFO_EMPTY_V  0x00000001U
-#define LP_UART_RX_AFIFO_EMPTY_S  3
-
-/** LP_UART_REG_UPDATE_REG register
- *  UART Registers Configuration Update register
- */
-#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98)
-/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define LP_UART_REG_UPDATE    (BIT(0))
-#define LP_UART_REG_UPDATE_M  (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S)
-#define LP_UART_REG_UPDATE_V  0x00000001U
-#define LP_UART_REG_UPDATE_S  0
-
-/** LP_UART_ID_REG register
- *  UART ID register
- */
-#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c)
-/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define LP_UART_ID    0xFFFFFFFFU
-#define LP_UART_ID_M  (LP_UART_ID_V << LP_UART_ID_S)
-#define LP_UART_ID_V  0xFFFFFFFFU
-#define LP_UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_uart_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_uart_struct.h
deleted file mode 100644
index fe19862be7..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_uart_struct.h
+++ /dev/null
@@ -1,1128 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         */
-        uint32_t rxfifo_rd_byte:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} lp_uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full_int_raw:1;
-        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty_int_raw:1;
-        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err_int_raw:1;
-        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg_int_raw:1;
-        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg_int_raw:1;
-        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det_int_raw:1;
-        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout_int_raw:1;
-        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon_int_raw:1;
-        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff_int_raw:1;
-        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det_int_raw:1;
-        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done_int_raw:1;
-        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done_int_raw:1;
-        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done_int_raw:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det_int_raw:1;
-        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup_int_raw:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full_int_st:1;
-        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty_int_st:1;
-        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err_int_st:1;
-        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg_int_st:1;
-        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg_int_st:1;
-        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det_int_st:1;
-        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout_int_st:1;
-        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon_int_st:1;
-        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff_int_st:1;
-        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det_int_st:1;
-        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done_int_st:1;
-        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done_int_st:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det_int_st:1;
-        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup_int_st:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full_int_ena:1;
-        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty_int_ena:1;
-        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err_int_ena:1;
-        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg_int_ena:1;
-        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg_int_ena:1;
-        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det_int_ena:1;
-        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout_int_ena:1;
-        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon_int_ena:1;
-        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff_int_ena:1;
-        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det_int_ena:1;
-        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done_int_ena:1;
-        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done_int_ena:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det_int_ena:1;
-        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup_int_ena:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full_int_clr:1;
-        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty_int_clr:1;
-        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err_int_clr:1;
-        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg_int_clr:1;
-        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg_int_clr:1;
-        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det_int_clr:1;
-        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout_int_clr:1;
-        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon_int_clr:1;
-        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff_int_clr:1;
-        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det_int_clr:1;
-        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done_int_clr:1;
-        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done_int_clr:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det_int_clr:1;
-        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup_int_clr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lp_uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  Configuration register 0
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        uint32_t reserved_7:5;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        uint32_t reserved_14:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        uint32_t reserved_19:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lp_uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:5;
-        uint32_t reserved_8:3;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:5;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} lp_uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow-control configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:5;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configure register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified wake up char1 to wake up
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  This register restores the specified wake up char2 to wake up
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  This register restores the specified wake up char3 to wake up
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  This register restores the specified wake up char4 to wake up
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configure register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified char0 to wake up
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configure register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        uint32_t reserved_10:3;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1;
-         *  In wake up mode 1 this field is used to set the received data number threshold to
-         *  wake up chip.
-         */
-        uint32_t rx_wake_up_thrhd:5;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  This register is used to select number of wake up char.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  This register is used to mask  wake up char.
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
-         *  received data number larger than
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
-         *  this status, UART Tx can not transmit XOFF even the received data number is larger
-         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
-         *  UART Tx is disabled.
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** xon_threshold : R/W; bitpos: [7:3]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
-         */
-        uint32_t xon_threshold:5;
-        uint32_t reserved_8:3;
-        /** xoff_threshold : R/W; bitpos: [15:11]; default: 12;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:5;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} lp_uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor.
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor.
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
-         */
-        uint32_t sclk_sel:2;
-        /** sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set this bit to enable UART Tx/Rx clock.
-         */
-        uint32_t sclk_en:1;
-        /** rst_core : R/W; bitpos: [23]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
-         */
-        uint32_t rst_core:1;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Set this bit to enable UART Tx clock.
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Set this bit to enable UART Rx clock.
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Rx.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:5;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        uint32_t reserved_16:3;
-        /** txfifo_cnt : RO; bitpos: [23:19]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:5;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} lp_uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0;
-         *  This register stores the offset write address in Tx-SRAM.
-         */
-        uint32_t tx_sram_waddr:5;
-        uint32_t reserved_8:4;
-        /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0;
-         *  This register stores the offset read address in Tx-SRAM.
-         */
-        uint32_t tx_sram_raddr:5;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16;
-         *  This register stores the offset read address in RX-SRAM.
-         */
-        uint32_t rx_sram_raddr:5;
-        uint32_t reserved_8:4;
-        /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16;
-         *  This register stores the offset write address in Rx-SRAM.
-         */
-        uint32_t rx_sram_waddr:5;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART AFIFO Status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Full signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Empty signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Full signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Empty signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t at_cmd_char:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35656288;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} lp_uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART Registers Configuration Update register
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} lp_uart_id_reg_t;
-
-
-typedef struct lp_uart_dev_t {
-    volatile lp_uart_fifo_reg_t fifo;
-    volatile lp_uart_int_raw_reg_t int_raw;
-    volatile lp_uart_int_st_reg_t int_st;
-    volatile lp_uart_int_ena_reg_t int_ena;
-    volatile lp_uart_int_clr_reg_t int_clr;
-    volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile lp_uart_rx_filt_reg_t rx_filt;
-    volatile lp_uart_status_reg_t status;
-    volatile lp_uart_conf0_sync_reg_t conf0_sync;
-    volatile lp_uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile lp_uart_sleep_conf0_reg_t sleep_conf0;
-    volatile lp_uart_sleep_conf1_reg_t sleep_conf1;
-    volatile lp_uart_sleep_conf2_reg_t sleep_conf2;
-    volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile lp_uart_swfc_conf1_reg_t swfc_conf1;
-    volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile lp_uart_mem_conf_reg_t mem_conf;
-    volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile lp_uart_mem_tx_status_reg_t mem_tx_status;
-    volatile lp_uart_mem_rx_status_reg_t mem_rx_status;
-    volatile lp_uart_fsm_status_reg_t fsm_status;
-    uint32_t reserved_074[5];
-    volatile lp_uart_clk_conf_reg_t clk_conf;
-    volatile lp_uart_date_reg_t date;
-    volatile lp_uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile lp_uart_reg_update_reg_t reg_update;
-    volatile lp_uart_id_reg_t id;
-} lp_uart_dev_t;
-
-// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h
-// extern lp_uart_dev_t LP_UART;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_wdt_reg.h b/components/soc/esp32c5/beta3/include/soc/lp_wdt_reg.h
deleted file mode 100644
index 4f7a3353f3..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_wdt_reg.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_WDT_CONFIG0_REG register
- *  need_des
- */
-#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
-/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
- *  need_des
- */
-#define LP_WDT_WDT_PAUSE_IN_SLP    (BIT(9))
-#define LP_WDT_WDT_PAUSE_IN_SLP_M  (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
-#define LP_WDT_WDT_PAUSE_IN_SLP_V  0x00000001U
-#define LP_WDT_WDT_PAUSE_IN_SLP_S  9
-/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_APPCPU_RESET_EN    (BIT(10))
-#define LP_WDT_WDT_APPCPU_RESET_EN_M  (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
-#define LP_WDT_WDT_APPCPU_RESET_EN_V  0x00000001U
-#define LP_WDT_WDT_APPCPU_RESET_EN_S  10
-/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_PROCPU_RESET_EN    (BIT(11))
-#define LP_WDT_WDT_PROCPU_RESET_EN_M  (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
-#define LP_WDT_WDT_PROCPU_RESET_EN_V  0x00000001U
-#define LP_WDT_WDT_PROCPU_RESET_EN_S  11
-/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
- *  need_des
- */
-#define LP_WDT_WDT_FLASHBOOT_MOD_EN    (BIT(12))
-#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M  (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
-#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
-#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S  12
-/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
- *  need_des
- */
-#define LP_WDT_WDT_SYS_RESET_LENGTH    0x00000007U
-#define LP_WDT_WDT_SYS_RESET_LENGTH_M  (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
-#define LP_WDT_WDT_SYS_RESET_LENGTH_V  0x00000007U
-#define LP_WDT_WDT_SYS_RESET_LENGTH_S  13
-/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
- *  need_des
- */
-#define LP_WDT_WDT_CPU_RESET_LENGTH    0x00000007U
-#define LP_WDT_WDT_CPU_RESET_LENGTH_M  (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
-#define LP_WDT_WDT_CPU_RESET_LENGTH_V  0x00000007U
-#define LP_WDT_WDT_CPU_RESET_LENGTH_S  16
-/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_STG3    0x00000007U
-#define LP_WDT_WDT_STG3_M  (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
-#define LP_WDT_WDT_STG3_V  0x00000007U
-#define LP_WDT_WDT_STG3_S  19
-/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_STG2    0x00000007U
-#define LP_WDT_WDT_STG2_M  (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
-#define LP_WDT_WDT_STG2_V  0x00000007U
-#define LP_WDT_WDT_STG2_S  22
-/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_STG1    0x00000007U
-#define LP_WDT_WDT_STG1_M  (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
-#define LP_WDT_WDT_STG1_V  0x00000007U
-#define LP_WDT_WDT_STG1_S  25
-/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_STG0    0x00000007U
-#define LP_WDT_WDT_STG0_M  (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
-#define LP_WDT_WDT_STG0_V  0x00000007U
-#define LP_WDT_WDT_STG0_S  28
-/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_EN    (BIT(31))
-#define LP_WDT_WDT_EN_M  (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
-#define LP_WDT_WDT_EN_V  0x00000001U
-#define LP_WDT_WDT_EN_S  31
-
-/** LP_WDT_CONFIG1_REG register
- *  need_des
- */
-#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
-/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
- *  need_des
- */
-#define LP_WDT_WDT_STG0_HOLD    0xFFFFFFFFU
-#define LP_WDT_WDT_STG0_HOLD_M  (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
-#define LP_WDT_WDT_STG0_HOLD_V  0xFFFFFFFFU
-#define LP_WDT_WDT_STG0_HOLD_S  0
-
-/** LP_WDT_CONFIG2_REG register
- *  need_des
- */
-#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
-/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
- *  need_des
- */
-#define LP_WDT_WDT_STG1_HOLD    0xFFFFFFFFU
-#define LP_WDT_WDT_STG1_HOLD_M  (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
-#define LP_WDT_WDT_STG1_HOLD_V  0xFFFFFFFFU
-#define LP_WDT_WDT_STG1_HOLD_S  0
-
-/** LP_WDT_CONFIG3_REG register
- *  need_des
- */
-#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
-/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
- *  need_des
- */
-#define LP_WDT_WDT_STG2_HOLD    0xFFFFFFFFU
-#define LP_WDT_WDT_STG2_HOLD_M  (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
-#define LP_WDT_WDT_STG2_HOLD_V  0xFFFFFFFFU
-#define LP_WDT_WDT_STG2_HOLD_S  0
-
-/** LP_WDT_CONFIG4_REG register
- *  need_des
- */
-#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
-/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
- *  need_des
- */
-#define LP_WDT_WDT_STG3_HOLD    0xFFFFFFFFU
-#define LP_WDT_WDT_STG3_HOLD_M  (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
-#define LP_WDT_WDT_STG3_HOLD_V  0xFFFFFFFFU
-#define LP_WDT_WDT_STG3_HOLD_S  0
-
-/** LP_WDT_FEED_REG register
- *  need_des
- */
-#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
-/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_RTC_WDT_FEED    (BIT(31))
-#define LP_WDT_RTC_WDT_FEED_M  (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S)
-#define LP_WDT_RTC_WDT_FEED_V  0x00000001U
-#define LP_WDT_RTC_WDT_FEED_S  31
-
-/** LP_WDT_WPROTECT_REG register
- *  need_des
- */
-#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
-/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_WDT_WDT_WKEY    0xFFFFFFFFU
-#define LP_WDT_WDT_WKEY_M  (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
-#define LP_WDT_WDT_WKEY_V  0xFFFFFFFFU
-#define LP_WDT_WDT_WKEY_S  0
-
-/** LP_WDT_SWD_CONFIG_REG register
- *  need_des
- */
-#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
-/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_WDT_SWD_RESET_FLAG    (BIT(0))
-#define LP_WDT_SWD_RESET_FLAG_M  (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
-#define LP_WDT_SWD_RESET_FLAG_V  0x00000001U
-#define LP_WDT_SWD_RESET_FLAG_S  0
-/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
- *  need_des
- */
-#define LP_WDT_SWD_AUTO_FEED_EN    (BIT(18))
-#define LP_WDT_SWD_AUTO_FEED_EN_M  (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
-#define LP_WDT_SWD_AUTO_FEED_EN_V  0x00000001U
-#define LP_WDT_SWD_AUTO_FEED_EN_S  18
-/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
- *  need_des
- */
-#define LP_WDT_SWD_RST_FLAG_CLR    (BIT(19))
-#define LP_WDT_SWD_RST_FLAG_CLR_M  (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
-#define LP_WDT_SWD_RST_FLAG_CLR_V  0x00000001U
-#define LP_WDT_SWD_RST_FLAG_CLR_S  19
-/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
- *  need_des
- */
-#define LP_WDT_SWD_SIGNAL_WIDTH    0x000003FFU
-#define LP_WDT_SWD_SIGNAL_WIDTH_M  (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
-#define LP_WDT_SWD_SIGNAL_WIDTH_V  0x000003FFU
-#define LP_WDT_SWD_SIGNAL_WIDTH_S  20
-/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_WDT_SWD_DISABLE    (BIT(30))
-#define LP_WDT_SWD_DISABLE_M  (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
-#define LP_WDT_SWD_DISABLE_V  0x00000001U
-#define LP_WDT_SWD_DISABLE_S  30
-/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_SWD_FEED    (BIT(31))
-#define LP_WDT_SWD_FEED_M  (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
-#define LP_WDT_SWD_FEED_V  0x00000001U
-#define LP_WDT_SWD_FEED_S  31
-
-/** LP_WDT_SWD_WPROTECT_REG register
- *  need_des
- */
-#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
-/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LP_WDT_SWD_WKEY    0xFFFFFFFFU
-#define LP_WDT_SWD_WKEY_M  (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
-#define LP_WDT_SWD_WKEY_V  0xFFFFFFFFU
-#define LP_WDT_SWD_WKEY_S  0
-
-/** LP_WDT_INT_RAW_REG register
- *  need_des
- */
-#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
-/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_WDT_SUPER_WDT_INT_RAW    (BIT(30))
-#define LP_WDT_SUPER_WDT_INT_RAW_M  (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
-#define LP_WDT_SUPER_WDT_INT_RAW_V  0x00000001U
-#define LP_WDT_SUPER_WDT_INT_RAW_S  30
-/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_LP_WDT_INT_RAW    (BIT(31))
-#define LP_WDT_LP_WDT_INT_RAW_M  (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
-#define LP_WDT_LP_WDT_INT_RAW_V  0x00000001U
-#define LP_WDT_LP_WDT_INT_RAW_S  31
-
-/** LP_WDT_INT_ST_REG register
- *  need_des
- */
-#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
-/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_WDT_SUPER_WDT_INT_ST    (BIT(30))
-#define LP_WDT_SUPER_WDT_INT_ST_M  (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
-#define LP_WDT_SUPER_WDT_INT_ST_V  0x00000001U
-#define LP_WDT_SUPER_WDT_INT_ST_S  30
-/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_LP_WDT_INT_ST    (BIT(31))
-#define LP_WDT_LP_WDT_INT_ST_M  (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
-#define LP_WDT_LP_WDT_INT_ST_V  0x00000001U
-#define LP_WDT_LP_WDT_INT_ST_S  31
-
-/** LP_WDT_INT_ENA_REG register
- *  need_des
- */
-#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
-/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_WDT_SUPER_WDT_INT_ENA    (BIT(30))
-#define LP_WDT_SUPER_WDT_INT_ENA_M  (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
-#define LP_WDT_SUPER_WDT_INT_ENA_V  0x00000001U
-#define LP_WDT_SUPER_WDT_INT_ENA_S  30
-/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_LP_WDT_INT_ENA    (BIT(31))
-#define LP_WDT_LP_WDT_INT_ENA_M  (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
-#define LP_WDT_LP_WDT_INT_ENA_V  0x00000001U
-#define LP_WDT_LP_WDT_INT_ENA_S  31
-
-/** LP_WDT_INT_CLR_REG register
- *  need_des
- */
-#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
-/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_WDT_SUPER_WDT_INT_CLR    (BIT(30))
-#define LP_WDT_SUPER_WDT_INT_CLR_M  (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
-#define LP_WDT_SUPER_WDT_INT_CLR_V  0x00000001U
-#define LP_WDT_SUPER_WDT_INT_CLR_S  30
-/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_LP_WDT_INT_CLR    (BIT(31))
-#define LP_WDT_LP_WDT_INT_CLR_M  (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
-#define LP_WDT_LP_WDT_INT_CLR_V  0x00000001U
-#define LP_WDT_LP_WDT_INT_CLR_S  31
-
-/** LP_WDT_DATE_REG register
- *  need_des
- */
-#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
-/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864;
- *  need_des
- */
-#define LP_WDT_LP_WDT_DATE    0x7FFFFFFFU
-#define LP_WDT_LP_WDT_DATE_M  (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
-#define LP_WDT_LP_WDT_DATE_V  0x7FFFFFFFU
-#define LP_WDT_LP_WDT_DATE_S  0
-/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_WDT_CLK_EN    (BIT(31))
-#define LP_WDT_CLK_EN_M  (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
-#define LP_WDT_CLK_EN_V  0x00000001U
-#define LP_WDT_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/beta3/include/soc/lp_wdt_struct.h
deleted file mode 100644
index 7772b8f88c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lp_wdt_struct.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of config0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
-         *  need_des
-         */
-        uint32_t wdt_chip_reset_width:8;
-        /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_chip_reset_en:1;
-        /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_pause_in_slp:1;
-        /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_appcpu_reset_en:1;
-        /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_procpu_reset_en:1;
-        /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_flashboot_mod_en:1;
-        /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_sys_reset_length:3;
-        /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
-         *  need_des
-         */
-        uint32_t wdt_cpu_reset_length:3;
-        /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg3:3;
-        /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg2:3;
-        /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg1:3;
-        /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_stg0:3;
-        /** wdt_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_en:1;
-    };
-    uint32_t val;
-} lp_wdt_config0_reg_t;
-
-/** Type of config1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
-         *  need_des
-         */
-        uint32_t wdt_stg0_hold:32;
-    };
-    uint32_t val;
-} lp_wdt_config1_reg_t;
-
-/** Type of config2 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
-         *  need_des
-         */
-        uint32_t wdt_stg1_hold:32;
-    };
-    uint32_t val;
-} lp_wdt_config2_reg_t;
-
-/** Type of config3 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
-         *  need_des
-         */
-        uint32_t wdt_stg2_hold:32;
-    };
-    uint32_t val;
-} lp_wdt_config3_reg_t;
-
-/** Type of config4 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
-         *  need_des
-         */
-        uint32_t wdt_stg3_hold:32;
-    };
-    uint32_t val;
-} lp_wdt_config4_reg_t;
-
-/** Type of feed register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** rtc_wdt_feed : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t rtc_wdt_feed:1;
-    };
-    uint32_t val;
-} lp_wdt_feed_reg_t;
-
-/** Type of wprotect register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t wdt_wkey:32;
-    };
-    uint32_t val;
-} lp_wdt_wprotect_reg_t;
-
-/** Type of swd_config register
- *  need_des
- */
-typedef union {
-    struct {
-        /** swd_reset_flag : RO; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_reset_flag:1;
-        uint32_t reserved_1:17;
-        /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_auto_feed_en:1;
-        /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_rst_flag_clr:1;
-        /** swd_signal_width : R/W; bitpos: [29:20]; default: 300;
-         *  need_des
-         */
-        uint32_t swd_signal_width:10;
-        /** swd_disable : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_disable:1;
-        /** swd_feed : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_feed:1;
-    };
-    uint32_t val;
-} lp_wdt_swd_config_reg_t;
-
-/** Type of swd_wprotect register
- *  need_des
- */
-typedef union {
-    struct {
-        /** swd_wkey : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t swd_wkey:32;
-    };
-    uint32_t val;
-} lp_wdt_swd_wprotect_reg_t;
-
-/** Type of int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_raw:1;
-        /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_raw:1;
-    };
-    uint32_t val;
-} lp_wdt_int_raw_reg_t;
-
-/** Type of int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_st:1;
-        /** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_st:1;
-    };
-    uint32_t val;
-} lp_wdt_int_st_reg_t;
-
-/** Type of int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_ena:1;
-        /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_ena:1;
-    };
-    uint32_t val;
-} lp_wdt_int_ena_reg_t;
-
-/** Type of int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** super_wdt_int_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t super_wdt_int_clr:1;
-        /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_wdt_int_clr:1;
-    };
-    uint32_t val;
-} lp_wdt_int_clr_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864;
-         *  need_des
-         */
-        uint32_t lp_wdt_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_wdt_date_reg_t;
-
-
-typedef struct lp_wdt_dev_t {
-    volatile lp_wdt_config0_reg_t config0;
-    volatile lp_wdt_config1_reg_t config1;
-    volatile lp_wdt_config2_reg_t config2;
-    volatile lp_wdt_config3_reg_t config3;
-    volatile lp_wdt_config4_reg_t config4;
-    volatile lp_wdt_feed_reg_t feed;
-    volatile lp_wdt_wprotect_reg_t wprotect;
-    volatile lp_wdt_swd_config_reg_t swd_config;
-    volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
-    volatile lp_wdt_int_raw_reg_t int_raw;
-    volatile lp_wdt_int_st_reg_t int_st;
-    volatile lp_wdt_int_ena_reg_t int_ena;
-    volatile lp_wdt_int_clr_reg_t int_clr;
-    uint32_t reserved_034[242];
-    volatile lp_wdt_date_reg_t date;
-} lp_wdt_dev_t;
-
-extern lp_wdt_dev_t LP_WDT;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lpperi_reg.h b/components/soc/esp32c5/beta3/include/soc/lpperi_reg.h
deleted file mode 100644
index d3d5d79bc3..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lpperi_reg.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LPPERI_CLK_EN_REG register
- *  need_des
- */
-#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
-/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
- *  need_des
- */
-#define LPPERI_RNG_CK_EN    (BIT(24))
-#define LPPERI_RNG_CK_EN_M  (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
-#define LPPERI_RNG_CK_EN_V  0x00000001U
-#define LPPERI_RNG_CK_EN_S  24
-/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
- *  need_des
- */
-#define LPPERI_OTP_DBG_CK_EN    (BIT(25))
-#define LPPERI_OTP_DBG_CK_EN_M  (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
-#define LPPERI_OTP_DBG_CK_EN_V  0x00000001U
-#define LPPERI_OTP_DBG_CK_EN_S  25
-/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1;
- *  need_des
- */
-#define LPPERI_LP_UART_CK_EN    (BIT(26))
-#define LPPERI_LP_UART_CK_EN_M  (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S)
-#define LPPERI_LP_UART_CK_EN_V  0x00000001U
-#define LPPERI_LP_UART_CK_EN_S  26
-/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
- *  need_des
- */
-#define LPPERI_LP_IO_CK_EN    (BIT(27))
-#define LPPERI_LP_IO_CK_EN_M  (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
-#define LPPERI_LP_IO_CK_EN_V  0x00000001U
-#define LPPERI_LP_IO_CK_EN_S  27
-/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1;
- *  need_des
- */
-#define LPPERI_LP_EXT_I2C_CK_EN    (BIT(28))
-#define LPPERI_LP_EXT_I2C_CK_EN_M  (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S)
-#define LPPERI_LP_EXT_I2C_CK_EN_V  0x00000001U
-#define LPPERI_LP_EXT_I2C_CK_EN_S  28
-/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1;
- *  need_des
- */
-#define LPPERI_LP_ANA_I2C_CK_EN    (BIT(29))
-#define LPPERI_LP_ANA_I2C_CK_EN_M  (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S)
-#define LPPERI_LP_ANA_I2C_CK_EN_V  0x00000001U
-#define LPPERI_LP_ANA_I2C_CK_EN_S  29
-/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define LPPERI_EFUSE_CK_EN    (BIT(30))
-#define LPPERI_EFUSE_CK_EN_M  (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
-#define LPPERI_EFUSE_CK_EN_V  0x00000001U
-#define LPPERI_EFUSE_CK_EN_S  30
-/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_CPU_CK_EN    (BIT(31))
-#define LPPERI_LP_CPU_CK_EN_M  (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S)
-#define LPPERI_LP_CPU_CK_EN_V  0x00000001U
-#define LPPERI_LP_CPU_CK_EN_S  31
-
-/** LPPERI_RESET_EN_REG register
- *  need_des
- */
-#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
-/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
- *  need_des
- */
-#define LPPERI_BUS_RESET_EN    (BIT(23))
-#define LPPERI_BUS_RESET_EN_M  (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
-#define LPPERI_BUS_RESET_EN_V  0x00000001U
-#define LPPERI_BUS_RESET_EN_S  23
-/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define LPPERI_OTP_DBG_RESET_EN    (BIT(25))
-#define LPPERI_OTP_DBG_RESET_EN_M  (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
-#define LPPERI_OTP_DBG_RESET_EN_V  0x00000001U
-#define LPPERI_OTP_DBG_RESET_EN_S  25
-/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_UART_RESET_EN    (BIT(26))
-#define LPPERI_LP_UART_RESET_EN_M  (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S)
-#define LPPERI_LP_UART_RESET_EN_V  0x00000001U
-#define LPPERI_LP_UART_RESET_EN_S  26
-/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_IO_RESET_EN    (BIT(27))
-#define LPPERI_LP_IO_RESET_EN_M  (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
-#define LPPERI_LP_IO_RESET_EN_V  0x00000001U
-#define LPPERI_LP_IO_RESET_EN_S  27
-/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_EXT_I2C_RESET_EN    (BIT(28))
-#define LPPERI_LP_EXT_I2C_RESET_EN_M  (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S)
-#define LPPERI_LP_EXT_I2C_RESET_EN_V  0x00000001U
-#define LPPERI_LP_EXT_I2C_RESET_EN_S  28
-/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_ANA_I2C_RESET_EN    (BIT(29))
-#define LPPERI_LP_ANA_I2C_RESET_EN_M  (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S)
-#define LPPERI_LP_ANA_I2C_RESET_EN_V  0x00000001U
-#define LPPERI_LP_ANA_I2C_RESET_EN_S  29
-/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LPPERI_EFUSE_RESET_EN    (BIT(30))
-#define LPPERI_EFUSE_RESET_EN_M  (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
-#define LPPERI_EFUSE_RESET_EN_V  0x00000001U
-#define LPPERI_EFUSE_RESET_EN_S  30
-/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_CPU_RESET_EN    (BIT(31))
-#define LPPERI_LP_CPU_RESET_EN_M  (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S)
-#define LPPERI_LP_CPU_RESET_EN_V  0x00000001U
-#define LPPERI_LP_CPU_RESET_EN_S  31
-
-/** LPPERI_RNG_DATA_REG register
- *  need_des
- */
-#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8)
-/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPPERI_RND_DATA    0xFFFFFFFFU
-#define LPPERI_RND_DATA_M  (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S)
-#define LPPERI_RND_DATA_V  0xFFFFFFFFU
-#define LPPERI_RND_DATA_S  0
-
-/** LPPERI_CPU_REG register
- *  need_des
- */
-#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc)
-/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define LPPERI_LPCORE_DBGM_UNAVALIABLE    (BIT(31))
-#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M  (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S)
-#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V  0x00000001U
-#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S  31
-
-/** LPPERI_BUS_TIMEOUT_REG register
- *  need_des
- */
-#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10)
-/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535;
- *  need_des
- */
-#define LPPERI_LP_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define LPPERI_LP_PERI_TIMEOUT_THRES_M  (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S)
-#define LPPERI_LP_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define LPPERI_LP_PERI_TIMEOUT_THRES_S  14
-/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR    (BIT(30))
-#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M  (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S)
-#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S  30
-/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN    (BIT(31))
-#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M  (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S)
-#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S  31
-
-/** LPPERI_BUS_TIMEOUT_ADDR_REG register
- *  need_des
- */
-#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14)
-/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define LPPERI_LP_PERI_TIMEOUT_ADDR_M  (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S)
-#define LPPERI_LP_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define LPPERI_LP_PERI_TIMEOUT_ADDR_S  0
-
-/** LPPERI_BUS_TIMEOUT_UID_REG register
- *  need_des
- */
-#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18)
-/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  need_des
- */
-#define LPPERI_LP_PERI_TIMEOUT_UID    0x0000007FU
-#define LPPERI_LP_PERI_TIMEOUT_UID_M  (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S)
-#define LPPERI_LP_PERI_TIMEOUT_UID_V  0x0000007FU
-#define LPPERI_LP_PERI_TIMEOUT_UID_S  0
-
-/** LPPERI_MEM_CTRL_REG register
- *  need_des
- */
-#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x1c)
-/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LPPERI_UART_WAKEUP_FLAG_CLR    (BIT(0))
-#define LPPERI_UART_WAKEUP_FLAG_CLR_M  (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S)
-#define LPPERI_UART_WAKEUP_FLAG_CLR_V  0x00000001U
-#define LPPERI_UART_WAKEUP_FLAG_CLR_S  0
-/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LPPERI_UART_WAKEUP_FLAG    (BIT(1))
-#define LPPERI_UART_WAKEUP_FLAG_M  (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S)
-#define LPPERI_UART_WAKEUP_FLAG_V  0x00000001U
-#define LPPERI_UART_WAKEUP_FLAG_S  1
-/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LPPERI_UART_WAKEUP_EN    (BIT(29))
-#define LPPERI_UART_WAKEUP_EN_M  (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S)
-#define LPPERI_UART_WAKEUP_EN_V  0x00000001U
-#define LPPERI_UART_WAKEUP_EN_S  29
-/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LPPERI_UART_MEM_FORCE_PD    (BIT(30))
-#define LPPERI_UART_MEM_FORCE_PD_M  (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S)
-#define LPPERI_UART_MEM_FORCE_PD_V  0x00000001U
-#define LPPERI_UART_MEM_FORCE_PD_S  30
-/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define LPPERI_UART_MEM_FORCE_PU    (BIT(31))
-#define LPPERI_UART_MEM_FORCE_PU_M  (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S)
-#define LPPERI_UART_MEM_FORCE_PU_V  0x00000001U
-#define LPPERI_UART_MEM_FORCE_PU_S  31
-
-/** LPPERI_INTERRUPT_SOURCE_REG register
- *  need_des
- */
-#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
-/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0;
- *  BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
- *  lp_io_int
- */
-#define LPPERI_LP_INTERRUPT_SOURCE    0x0000003FU
-#define LPPERI_LP_INTERRUPT_SOURCE_M  (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
-#define LPPERI_LP_INTERRUPT_SOURCE_V  0x0000003FU
-#define LPPERI_LP_INTERRUPT_SOURCE_S  0
-
-/** LPPERI_RNG_CFG_REG register
- *  need_des
- */
-#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24)
-/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
- *  need des
- */
-#define LPPERI_RNG_SAMPLE_ENABLE    (BIT(0))
-#define LPPERI_RNG_SAMPLE_ENABLE_M  (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S)
-#define LPPERI_RNG_SAMPLE_ENABLE_V  0x00000001U
-#define LPPERI_RNG_SAMPLE_ENABLE_S  0
-/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
- *  need des
- */
-#define LPPERI_RNG_TIMER_PSCALE    0x000000FFU
-#define LPPERI_RNG_TIMER_PSCALE_M  (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S)
-#define LPPERI_RNG_TIMER_PSCALE_V  0x000000FFU
-#define LPPERI_RNG_TIMER_PSCALE_S  1
-/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
- *  need des
- */
-#define LPPERI_RNG_TIMER_EN    (BIT(9))
-#define LPPERI_RNG_TIMER_EN_M  (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S)
-#define LPPERI_RNG_TIMER_EN_V  0x00000001U
-#define LPPERI_RNG_TIMER_EN_S  9
-/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
- *  need des
- */
-#define LPPERI_RNG_SAMPLE_CNT    0x000000FFU
-#define LPPERI_RNG_SAMPLE_CNT_M  (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S)
-#define LPPERI_RNG_SAMPLE_CNT_V  0x000000FFU
-#define LPPERI_RNG_SAMPLE_CNT_S  24
-
-/** LPPERI_DATE_REG register
- *  need_des
- */
-#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
-/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 36720720;
- *  need_des
- */
-#define LPPERI_LPPERI_DATE    0x7FFFFFFFU
-#define LPPERI_LPPERI_DATE_M  (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
-#define LPPERI_LPPERI_DATE_V  0x7FFFFFFFU
-#define LPPERI_LPPERI_DATE_S  0
-/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LPPERI_CLK_EN    (BIT(31))
-#define LPPERI_CLK_EN_M  (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
-#define LPPERI_CLK_EN_V  0x00000001U
-#define LPPERI_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/lpperi_struct.h b/components/soc/esp32c5/beta3/include/soc/lpperi_struct.h
deleted file mode 100644
index 06e3e023ca..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/lpperi_struct.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of clk_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** rng_ck_en : R/W; bitpos: [24]; default: 1;
-         *  need_des
-         */
-        uint32_t rng_ck_en:1;
-        /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
-         *  need_des
-         */
-        uint32_t otp_dbg_ck_en:1;
-        /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_uart_ck_en:1;
-        /** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_io_ck_en:1;
-        /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_ext_i2c_ck_en:1;
-        /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_ana_i2c_ck_en:1;
-        /** efuse_ck_en : R/W; bitpos: [30]; default: 1;
-         *  need_des
-         */
-        uint32_t efuse_ck_en:1;
-        /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_ck_en:1;
-    };
-    uint32_t val;
-} lpperi_clk_en_reg_t;
-
-/** Type of reset_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:23;
-        /** bus_reset_en : WT; bitpos: [23]; default: 0;
-         *  need_des
-         */
-        uint32_t bus_reset_en:1;
-        uint32_t reserved_24:1;
-        /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t otp_dbg_reset_en:1;
-        /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_uart_reset_en:1;
-        /** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_io_reset_en:1;
-        /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_ext_i2c_reset_en:1;
-        /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_ana_i2c_reset_en:1;
-        /** efuse_reset_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t efuse_reset_en:1;
-        /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_reset_en:1;
-    };
-    uint32_t val;
-} lpperi_reset_en_reg_t;
-
-/** Type of rng_data register
- *  need_des
- */
-typedef union {
-    struct {
-        /** rnd_data : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t rnd_data:32;
-    };
-    uint32_t val;
-} lpperi_rng_data_reg_t;
-
-/** Type of cpu register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t lpcore_dbgm_unavaliable:1;
-    };
-    uint32_t val;
-} lpperi_cpu_reg_t;
-
-/** Type of bus_timeout register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:14;
-        /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535;
-         *  need_des
-         */
-        uint32_t lp_peri_timeout_thres:16;
-        /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_peri_timeout_int_clear:1;
-        /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_peri_timeout_protect_en:1;
-    };
-    uint32_t val;
-} lpperi_bus_timeout_reg_t;
-
-/** Type of bus_timeout_addr register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} lpperi_bus_timeout_addr_reg_t;
-
-/** Type of bus_timeout_uid register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} lpperi_bus_timeout_uid_reg_t;
-
-/** Type of mem_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t uart_wakeup_flag_clr:1;
-        /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t uart_wakeup_flag:1;
-        uint32_t reserved_2:27;
-        /** uart_wakeup_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t uart_wakeup_en:1;
-        /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t uart_mem_force_pd:1;
-        /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t uart_mem_force_pu:1;
-    };
-    uint32_t val;
-} lpperi_mem_ctrl_reg_t;
-
-/** Type of interrupt_source register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0;
-         *  BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int,
-         *  lp_io_int
-         */
-        uint32_t lp_interrupt_source:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} lpperi_interrupt_source_reg_t;
-
-/** Type of rng_cfg register
- *  need_des
- */
-typedef union {
-    struct {
-        /** rng_sample_enable : R/W; bitpos: [0]; default: 0;
-         *  need des
-         */
-        uint32_t rng_sample_enable:1;
-        /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255;
-         *  need des
-         */
-        uint32_t rng_timer_pscale:8;
-        /** rng_timer_en : R/W; bitpos: [9]; default: 1;
-         *  need des
-         */
-        uint32_t rng_timer_en:1;
-        uint32_t reserved_10:14;
-        /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0;
-         *  need des
-         */
-        uint32_t rng_sample_cnt:8;
-    };
-    uint32_t val;
-} lpperi_rng_cfg_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lpperi_date : R/W; bitpos: [30:0]; default: 36720720;
-         *  need_des
-         */
-        uint32_t lpperi_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lpperi_date_reg_t;
-
-
-typedef struct lpperi_dev_t {
-    volatile lpperi_clk_en_reg_t clk_en;
-    volatile lpperi_reset_en_reg_t reset_en;
-    volatile lpperi_rng_data_reg_t rng_data;
-    volatile lpperi_cpu_reg_t cpu;
-    volatile lpperi_bus_timeout_reg_t bus_timeout;
-    volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr;
-    volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid;
-    volatile lpperi_mem_ctrl_reg_t mem_ctrl;
-    volatile lpperi_interrupt_source_reg_t interrupt_source;
-    volatile lpperi_rng_cfg_reg_t rng_cfg;
-    uint32_t reserved_028[245];
-    volatile lpperi_date_reg_t date;
-} lpperi_dev_t;
-
-extern lpperi_dev_t LPPERI;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/mcpwm_reg.h b/components/soc/esp32c5/beta3/include/soc/mcpwm_reg.h
deleted file mode 100644
index 2c5d5957a7..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/mcpwm_reg.h
+++ /dev/null
@@ -1,4514 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MCPWM_CLK_CFG_REG register
- *  PWM clock prescaler register.
- */
-#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0)
-/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
- *  (PWM_CLK_PRESCALE + 1).
- */
-#define MCPWM_CLK_PRESCALE    0x000000FFU
-#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
-#define MCPWM_CLK_PRESCALE_V  0x000000FFU
-#define MCPWM_CLK_PRESCALE_S  0
-
-/** MCPWM_TIMER0_CFG0_REG register
- *  PWM timer0 period and update method configuration register.
- */
-#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER0_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer0
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer0 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER0_CFG1_REG register
- *  PWM timer0 working mode and start/stop control register.
- */
-#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8)
-/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer0.\\0: If PWM timer0 starts, then
- *  stops at TEZ\\1: If timer0 starts, then stops at TEP\\2: PWM timer0 starts and runs
- *  on\\3: Timer0 starts and stops at the next TEZ\\4: Timer0 starts and stops at the
- *  next TEP.\\TEP here and below means the event that happens when the timer equals to
- *  period
- */
-#define MCPWM_TIMER0_START    0x00000007U
-#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
-#define MCPWM_TIMER0_START_V  0x00000007U
-#define MCPWM_TIMER0_START_S  0
-/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer0.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER0_MOD    0x00000003U
-#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
-#define MCPWM_TIMER0_MOD_V  0x00000003U
-#define MCPWM_TIMER0_MOD_S  3
-
-/** MCPWM_TIMER0_SYNC_REG register
- *  PWM timer0 sync function configuration register.
- */
-#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc)
-/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer0 reloading with phase on sync input event
- *  is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
-#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER0_SYNCI_EN_S  0
-/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
-#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER0_SYNC_SW_S  1
-/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer0 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
-#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_S  2
-/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer0 reload on sync event.
- */
-#define MCPWM_TIMER0_PHASE    0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
-#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_S  4
-/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer0's direction when timer0 mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
-#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER0_STATUS_REG register
- *  PWM timer0 status register.
- */
-#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10)
-/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer0 counter value.
- */
-#define MCPWM_TIMER0_VALUE    0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
-#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_S  0
-/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer0 counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER0_DIRECTION    (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
-#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_DIRECTION_S  16
-
-/** MCPWM_TIMER1_CFG0_REG register
- *  PWM timer1 period and update method configuration register.
- */
-#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14)
-/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER1_PRESCALE + 1)
- */
-#define MCPWM_TIMER1_PRESCALE    0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
-#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_S  0
-/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer1
- */
-#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
-#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_S  8
-/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer1 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER1_CFG1_REG register
- *  PWM timer1 working mode and start/stop control register.
- */
-#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18)
-/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer1.\\0: If PWM timer1 starts, then
- *  stops at TEZ\\1: If timer1 starts, then stops at TEP\\2: PWM timer1 starts and runs
- *  on\\3: Timer1 starts and stops at the next TEZ\\4: Timer0 starts and stops at the
- *  next TEP.\\TEP here and below means the event that happens when the timer equals to
- *  period
- */
-#define MCPWM_TIMER1_START    0x00000007U
-#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
-#define MCPWM_TIMER1_START_V  0x00000007U
-#define MCPWM_TIMER1_START_S  0
-/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer1.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER1_MOD    0x00000003U
-#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
-#define MCPWM_TIMER1_MOD_V  0x00000003U
-#define MCPWM_TIMER1_MOD_S  3
-
-/** MCPWM_TIMER1_SYNC_REG register
- *  PWM timer1 sync function configuration register.
- */
-#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c)
-/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer1 reloading with phase on sync input event
- *  is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
-#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER1_SYNCI_EN_S  0
-/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
-#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER1_SYNC_SW_S  1
-/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer1 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
-#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_S  2
-/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer1 reload on sync event.
- */
-#define MCPWM_TIMER1_PHASE    0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
-#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_S  4
-/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer1's direction when timer1 mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
-#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER1_STATUS_REG register
- *  PWM timer1 status register.
- */
-#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20)
-/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer1 counter value.
- */
-#define MCPWM_TIMER1_VALUE    0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
-#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_S  0
-/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer1 counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER1_DIRECTION    (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
-#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_DIRECTION_S  16
-
-/** MCPWM_TIMER2_CFG0_REG register
- *  PWM timer2 period and update method configuration register.
- */
-#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24)
-/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER2_PRESCALE + 1)
- */
-#define MCPWM_TIMER2_PRESCALE    0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
-#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_S  0
-/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer2
- */
-#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
-#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_S  8
-/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer2 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER2_CFG1_REG register
- *  PWM timer2 working mode and start/stop control register.
- */
-#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28)
-/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer2.\\0: If PWM timer2 starts, then
- *  stops at TEZ\\1: If timer2 starts, then stops at TEP\\2: PWM timer2 starts and runs
- *  on\\3: Timer2 starts and stops at the next TEZ\\4: Timer0 starts and stops at the
- *  next TEP.\\TEP here and below means the event that happens when the timer equals to
- *  period
- */
-#define MCPWM_TIMER2_START    0x00000007U
-#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
-#define MCPWM_TIMER2_START_V  0x00000007U
-#define MCPWM_TIMER2_START_S  0
-/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer2.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER2_MOD    0x00000003U
-#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
-#define MCPWM_TIMER2_MOD_V  0x00000003U
-#define MCPWM_TIMER2_MOD_S  3
-
-/** MCPWM_TIMER2_SYNC_REG register
- *  PWM timer2 sync function configuration register.
- */
-#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c)
-/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer2 reloading with phase on sync input event
- *  is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
-#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER2_SYNCI_EN_S  0
-/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
-#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER2_SYNC_SW_S  1
-/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer2 sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
-#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_S  2
-/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer2 reload on sync event.
- */
-#define MCPWM_TIMER2_PHASE    0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
-#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_S  4
-/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer2's direction when timer2 mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
-#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER2_STATUS_REG register
- *  PWM timer2 status register.
- */
-#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30)
-/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer2 counter value.
- */
-#define MCPWM_TIMER2_VALUE    0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
-#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_S  0
-/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer2 counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER2_DIRECTION    (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
-#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_DIRECTION_S  16
-
-/** MCPWM_TIMER_SYNCI_CFG_REG register
- *  Synchronization input selection register for PWM timers.
- */
-#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34)
-/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
- *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER0_SYNCISEL    0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
-#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_S  0
-/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
- *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER1_SYNCISEL    0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
-#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_S  3
-/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
- *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER2_SYNCISEL    0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
-#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_S  6
-/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
-/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
-/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
-
-/** MCPWM_OPERATOR_TIMERSEL_REG register
- *  PWM operator's timer select register
- */
-#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38)
-/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
-#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_S  0
-/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
-#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_S  2
-/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
-#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_S  4
-
-/** MCPWM_GEN0_STMP_CFG_REG register
- *  Generator0 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c)
-/** MCPWM_GEN0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 0 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN0_A_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_A_UPMETHOD_M  (MCPWM_GEN0_A_UPMETHOD_V << MCPWM_GEN0_A_UPMETHOD_S)
-#define MCPWM_GEN0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_A_UPMETHOD_S  0
-/** MCPWM_GEN0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 0 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN0_B_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_B_UPMETHOD_M  (MCPWM_GEN0_B_UPMETHOD_V << MCPWM_GEN0_B_UPMETHOD_S)
-#define MCPWM_GEN0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_B_UPMETHOD_S  4
-/** MCPWM_GEN0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_GEN0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_GEN0_A_SHDW_FULL_M  (MCPWM_GEN0_A_SHDW_FULL_V << MCPWM_GEN0_A_SHDW_FULL_S)
-#define MCPWM_GEN0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN0_A_SHDW_FULL_S  8
-/** MCPWM_GEN0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_GEN0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_GEN0_B_SHDW_FULL_M  (MCPWM_GEN0_B_SHDW_FULL_V << MCPWM_GEN0_B_SHDW_FULL_S)
-#define MCPWM_GEN0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN0_TSTMP_A_REG register
- *  Generator0 time stamp A's shadow register
- */
-#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40)
-/** MCPWM_GEN0_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator 0 time stamp A's shadow register.
- */
-#define MCPWM_GEN0_A    0x0000FFFFU
-#define MCPWM_GEN0_A_M  (MCPWM_GEN0_A_V << MCPWM_GEN0_A_S)
-#define MCPWM_GEN0_A_V  0x0000FFFFU
-#define MCPWM_GEN0_A_S  0
-
-/** MCPWM_GEN0_TSTMP_B_REG register
- *  Generator0 time stamp B's shadow register
- */
-#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44)
-/** MCPWM_GEN0_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator 0 time stamp B's shadow register.
- */
-#define MCPWM_GEN0_B    0x0000FFFFU
-#define MCPWM_GEN0_B_M  (MCPWM_GEN0_B_V << MCPWM_GEN0_B_S)
-#define MCPWM_GEN0_B_V  0x0000FFFFU
-#define MCPWM_GEN0_B_S  0
-
-/** MCPWM_GEN0_CFG0_REG register
- *  Generator0 fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48)
-/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator 0's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
-#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_S  0
-/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator 0 event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN0_T0_SEL    0x00000007U
-#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
-#define MCPWM_GEN0_T0_SEL_V  0x00000007U
-#define MCPWM_GEN0_T0_SEL_S  4
-/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator 0 event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN0_T1_SEL    0x00000007U
-#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
-#define MCPWM_GEN0_T1_SEL_V  0x00000007U
-#define MCPWM_GEN0_T1_SEL_S  7
-
-/** MCPWM_GEN0_FORCE_REG register
- *  Generator0 output signal force mode register.
- */
-#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c)
-/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator0.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM0 A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM0 B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for PWM0
- *  A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
-#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_A_NCIFORCE_S  10
-/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM0 A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for PWM0
- *  B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
-#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_B_NCIFORCE_S  13
-/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM0 B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN0_A_REG register
- *  PWM0 output signal A actions configuration register
- */
-#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50)
-/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM0 A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEZ    0x00000003U
-#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
-#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_UTEZ_S  0
-/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM0 A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEP    0x00000003U
-#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
-#define MCPWM_GEN0_A_UTEP_V  0x00000003U
-#define MCPWM_GEN0_A_UTEP_S  2
-/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM0 A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEA    0x00000003U
-#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
-#define MCPWM_GEN0_A_UTEA_V  0x00000003U
-#define MCPWM_GEN0_A_UTEA_S  4
-/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM0 A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEB    0x00000003U
-#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
-#define MCPWM_GEN0_A_UTEB_V  0x00000003U
-#define MCPWM_GEN0_A_UTEB_S  6
-/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM0 A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UT0    0x00000003U
-#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
-#define MCPWM_GEN0_A_UT0_V  0x00000003U
-#define MCPWM_GEN0_A_UT0_S  8
-/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM0 A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UT1    0x00000003U
-#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
-#define MCPWM_GEN0_A_UT1_V  0x00000003U
-#define MCPWM_GEN0_A_UT1_S  10
-/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM0 A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEZ    0x00000003U
-#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
-#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_DTEZ_S  12
-/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM0 A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEP    0x00000003U
-#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
-#define MCPWM_GEN0_A_DTEP_V  0x00000003U
-#define MCPWM_GEN0_A_DTEP_S  14
-/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM0 A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEA    0x00000003U
-#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
-#define MCPWM_GEN0_A_DTEA_V  0x00000003U
-#define MCPWM_GEN0_A_DTEA_S  16
-/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM0 A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEB    0x00000003U
-#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
-#define MCPWM_GEN0_A_DTEB_V  0x00000003U
-#define MCPWM_GEN0_A_DTEB_S  18
-/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM0 A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DT0    0x00000003U
-#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
-#define MCPWM_GEN0_A_DT0_V  0x00000003U
-#define MCPWM_GEN0_A_DT0_S  20
-/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM0 A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DT1    0x00000003U
-#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
-#define MCPWM_GEN0_A_DT1_V  0x00000003U
-#define MCPWM_GEN0_A_DT1_S  22
-
-/** MCPWM_GEN0_B_REG register
- *  PWM0 output signal B actions configuration register
- */
-#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54)
-/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM0 B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEZ    0x00000003U
-#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
-#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_UTEZ_S  0
-/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM0 B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEP    0x00000003U
-#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
-#define MCPWM_GEN0_B_UTEP_V  0x00000003U
-#define MCPWM_GEN0_B_UTEP_S  2
-/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM0 B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEA    0x00000003U
-#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
-#define MCPWM_GEN0_B_UTEA_V  0x00000003U
-#define MCPWM_GEN0_B_UTEA_S  4
-/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM0 B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEB    0x00000003U
-#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
-#define MCPWM_GEN0_B_UTEB_V  0x00000003U
-#define MCPWM_GEN0_B_UTEB_S  6
-/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM0 B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UT0    0x00000003U
-#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
-#define MCPWM_GEN0_B_UT0_V  0x00000003U
-#define MCPWM_GEN0_B_UT0_S  8
-/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM0 B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UT1    0x00000003U
-#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
-#define MCPWM_GEN0_B_UT1_V  0x00000003U
-#define MCPWM_GEN0_B_UT1_S  10
-/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM0 B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEZ    0x00000003U
-#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
-#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_DTEZ_S  12
-/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM0 B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEP    0x00000003U
-#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
-#define MCPWM_GEN0_B_DTEP_V  0x00000003U
-#define MCPWM_GEN0_B_DTEP_S  14
-/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM0 B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEA    0x00000003U
-#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
-#define MCPWM_GEN0_B_DTEA_V  0x00000003U
-#define MCPWM_GEN0_B_DTEA_S  16
-/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM0 B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEB    0x00000003U
-#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
-#define MCPWM_GEN0_B_DTEB_V  0x00000003U
-#define MCPWM_GEN0_B_DTEB_S  18
-/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM0 B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DT0    0x00000003U
-#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
-#define MCPWM_GEN0_B_DT0_V  0x00000003U
-#define MCPWM_GEN0_B_DT0_S  20
-/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM0 B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DT1    0x00000003U
-#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
-#define MCPWM_GEN0_B_DT1_V  0x00000003U
-#define MCPWM_GEN0_B_DT1_S  22
-
-/** MCPWM_DT0_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
-/** MCPWM_DT0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DT0_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DT0_FED_UPMETHOD_M  (MCPWM_DT0_FED_UPMETHOD_V << MCPWM_DT0_FED_UPMETHOD_S)
-#define MCPWM_DT0_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT0_FED_UPMETHOD_S  0
-/** MCPWM_DT0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DT0_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DT0_RED_UPMETHOD_M  (MCPWM_DT0_RED_UPMETHOD_V << MCPWM_DT0_RED_UPMETHOD_S)
-#define MCPWM_DT0_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT0_RED_UPMETHOD_S  4
-/** MCPWM_DT0_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DT0_DEB_MODE    (BIT(8))
-#define MCPWM_DT0_DEB_MODE_M  (MCPWM_DT0_DEB_MODE_V << MCPWM_DT0_DEB_MODE_S)
-#define MCPWM_DT0_DEB_MODE_V  0x00000001U
-#define MCPWM_DT0_DEB_MODE_S  8
-/** MCPWM_DT0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DT0_A_OUTSWAP    (BIT(9))
-#define MCPWM_DT0_A_OUTSWAP_M  (MCPWM_DT0_A_OUTSWAP_V << MCPWM_DT0_A_OUTSWAP_S)
-#define MCPWM_DT0_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DT0_A_OUTSWAP_S  9
-/** MCPWM_DT0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DT0_B_OUTSWAP    (BIT(10))
-#define MCPWM_DT0_B_OUTSWAP_M  (MCPWM_DT0_B_OUTSWAP_V << MCPWM_DT0_B_OUTSWAP_S)
-#define MCPWM_DT0_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DT0_B_OUTSWAP_S  10
-/** MCPWM_DT0_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DT0_RED_INSEL    (BIT(11))
-#define MCPWM_DT0_RED_INSEL_M  (MCPWM_DT0_RED_INSEL_V << MCPWM_DT0_RED_INSEL_S)
-#define MCPWM_DT0_RED_INSEL_V  0x00000001U
-#define MCPWM_DT0_RED_INSEL_S  11
-/** MCPWM_DT0_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DT0_FED_INSEL    (BIT(12))
-#define MCPWM_DT0_FED_INSEL_M  (MCPWM_DT0_FED_INSEL_V << MCPWM_DT0_FED_INSEL_S)
-#define MCPWM_DT0_FED_INSEL_V  0x00000001U
-#define MCPWM_DT0_FED_INSEL_S  12
-/** MCPWM_DT0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DT0_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DT0_RED_OUTINVERT_M  (MCPWM_DT0_RED_OUTINVERT_V << MCPWM_DT0_RED_OUTINVERT_S)
-#define MCPWM_DT0_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT0_RED_OUTINVERT_S  13
-/** MCPWM_DT0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DT0_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DT0_FED_OUTINVERT_M  (MCPWM_DT0_FED_OUTINVERT_V << MCPWM_DT0_FED_OUTINVERT_S)
-#define MCPWM_DT0_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT0_FED_OUTINVERT_S  14
-/** MCPWM_DT0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DT0_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DT0_A_OUTBYPASS_M  (MCPWM_DT0_A_OUTBYPASS_V << MCPWM_DT0_A_OUTBYPASS_S)
-#define MCPWM_DT0_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT0_A_OUTBYPASS_S  15
-/** MCPWM_DT0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DT0_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DT0_B_OUTBYPASS_M  (MCPWM_DT0_B_OUTBYPASS_V << MCPWM_DT0_B_OUTBYPASS_S)
-#define MCPWM_DT0_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT0_B_OUTBYPASS_S  16
-/** MCPWM_DT0_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator 0 clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DT0_CLK_SEL    (BIT(17))
-#define MCPWM_DT0_CLK_SEL_M  (MCPWM_DT0_CLK_SEL_V << MCPWM_DT0_CLK_SEL_S)
-#define MCPWM_DT0_CLK_SEL_V  0x00000001U
-#define MCPWM_DT0_CLK_SEL_S  17
-
-/** MCPWM_DT0_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
-/** MCPWM_DT0_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DT0_FED    0x0000FFFFU
-#define MCPWM_DT0_FED_M  (MCPWM_DT0_FED_V << MCPWM_DT0_FED_S)
-#define MCPWM_DT0_FED_V  0x0000FFFFU
-#define MCPWM_DT0_FED_S  0
-
-/** MCPWM_DT0_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
-/** MCPWM_DT0_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DT0_RED    0x0000FFFFU
-#define MCPWM_DT0_RED_M  (MCPWM_DT0_RED_V << MCPWM_DT0_RED_S)
-#define MCPWM_DT0_RED_V  0x0000FFFFU
-#define MCPWM_DT0_RED_S  0
-
-/** MCPWM_CARRIER0_CFG_REG register
- *  Carrier0 configuration register
- */
-#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64)
-/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier0.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CARRIER0_EN    (BIT(0))
-#define MCPWM_CARRIER0_EN_M  (MCPWM_CARRIER0_EN_V << MCPWM_CARRIER0_EN_S)
-#define MCPWM_CARRIER0_EN_V  0x00000001U
-#define MCPWM_CARRIER0_EN_S  0
-/** MCPWM_CARRIER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier0 clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CARRIER0_PRESCALE    0x0000000FU
-#define MCPWM_CARRIER0_PRESCALE_M  (MCPWM_CARRIER0_PRESCALE_V << MCPWM_CARRIER0_PRESCALE_S)
-#define MCPWM_CARRIER0_PRESCALE_V  0x0000000FU
-#define MCPWM_CARRIER0_PRESCALE_S  1
-/** MCPWM_CARRIER0_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CARRIER0_DUTY    0x00000007U
-#define MCPWM_CARRIER0_DUTY_M  (MCPWM_CARRIER0_DUTY_V << MCPWM_CARRIER0_DUTY_S)
-#define MCPWM_CARRIER0_DUTY_V  0x00000007U
-#define MCPWM_CARRIER0_DUTY_S  5
-/** MCPWM_CARRIER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CARRIER0_OSHTWTH    0x0000000FU
-#define MCPWM_CARRIER0_OSHTWTH_M  (MCPWM_CARRIER0_OSHTWTH_V << MCPWM_CARRIER0_OSHTWTH_S)
-#define MCPWM_CARRIER0_OSHTWTH_V  0x0000000FU
-#define MCPWM_CARRIER0_OSHTWTH_S  8
-/** MCPWM_CARRIER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM0 A and PWM0 B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CARRIER0_OUT_INVERT    (BIT(12))
-#define MCPWM_CARRIER0_OUT_INVERT_M  (MCPWM_CARRIER0_OUT_INVERT_V << MCPWM_CARRIER0_OUT_INVERT_S)
-#define MCPWM_CARRIER0_OUT_INVERT_V  0x00000001U
-#define MCPWM_CARRIER0_OUT_INVERT_S  12
-/** MCPWM_CARRIER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM0 A and PWM0 B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CARRIER0_IN_INVERT    (BIT(13))
-#define MCPWM_CARRIER0_IN_INVERT_M  (MCPWM_CARRIER0_IN_INVERT_V << MCPWM_CARRIER0_IN_INVERT_S)
-#define MCPWM_CARRIER0_IN_INVERT_V  0x00000001U
-#define MCPWM_CARRIER0_IN_INVERT_S  13
-
-/** MCPWM_FH0_CFG0_REG register
- *  PWM0 A and PWM0 B trip events actions configuration register
- */
-#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68)
-/** MCPWM_FH0_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_SW_CBC    (BIT(0))
-#define MCPWM_FH0_SW_CBC_M  (MCPWM_FH0_SW_CBC_V << MCPWM_FH0_SW_CBC_S)
-#define MCPWM_FH0_SW_CBC_V  0x00000001U
-#define MCPWM_FH0_SW_CBC_S  0
-/** MCPWM_FH0_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_F2_CBC    (BIT(1))
-#define MCPWM_FH0_F2_CBC_M  (MCPWM_FH0_F2_CBC_V << MCPWM_FH0_F2_CBC_S)
-#define MCPWM_FH0_F2_CBC_V  0x00000001U
-#define MCPWM_FH0_F2_CBC_S  1
-/** MCPWM_FH0_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_F1_CBC    (BIT(2))
-#define MCPWM_FH0_F1_CBC_M  (MCPWM_FH0_F1_CBC_V << MCPWM_FH0_F1_CBC_S)
-#define MCPWM_FH0_F1_CBC_V  0x00000001U
-#define MCPWM_FH0_F1_CBC_S  2
-/** MCPWM_FH0_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_F0_CBC    (BIT(3))
-#define MCPWM_FH0_F0_CBC_M  (MCPWM_FH0_F0_CBC_V << MCPWM_FH0_F0_CBC_S)
-#define MCPWM_FH0_F0_CBC_V  0x00000001U
-#define MCPWM_FH0_F0_CBC_S  3
-/** MCPWM_FH0_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_SW_OST    (BIT(4))
-#define MCPWM_FH0_SW_OST_M  (MCPWM_FH0_SW_OST_V << MCPWM_FH0_SW_OST_S)
-#define MCPWM_FH0_SW_OST_V  0x00000001U
-#define MCPWM_FH0_SW_OST_S  4
-/** MCPWM_FH0_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_F2_OST    (BIT(5))
-#define MCPWM_FH0_F2_OST_M  (MCPWM_FH0_F2_OST_V << MCPWM_FH0_F2_OST_S)
-#define MCPWM_FH0_F2_OST_V  0x00000001U
-#define MCPWM_FH0_F2_OST_S  5
-/** MCPWM_FH0_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_F1_OST    (BIT(6))
-#define MCPWM_FH0_F1_OST_M  (MCPWM_FH0_F1_OST_V << MCPWM_FH0_F1_OST_S)
-#define MCPWM_FH0_F1_OST_V  0x00000001U
-#define MCPWM_FH0_F1_OST_S  6
-/** MCPWM_FH0_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH0_F0_OST    (BIT(7))
-#define MCPWM_FH0_F0_OST_M  (MCPWM_FH0_F0_OST_V << MCPWM_FH0_F0_OST_S)
-#define MCPWM_FH0_F0_OST_V  0x00000001U
-#define MCPWM_FH0_F0_OST_S  7
-/** MCPWM_FH0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_A_CBC_D    0x00000003U
-#define MCPWM_FH0_A_CBC_D_M  (MCPWM_FH0_A_CBC_D_V << MCPWM_FH0_A_CBC_D_S)
-#define MCPWM_FH0_A_CBC_D_V  0x00000003U
-#define MCPWM_FH0_A_CBC_D_S  8
-/** MCPWM_FH0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM0 A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_A_CBC_U    0x00000003U
-#define MCPWM_FH0_A_CBC_U_M  (MCPWM_FH0_A_CBC_U_V << MCPWM_FH0_A_CBC_U_S)
-#define MCPWM_FH0_A_CBC_U_V  0x00000003U
-#define MCPWM_FH0_A_CBC_U_S  10
-/** MCPWM_FH0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM0 A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_A_OST_D    0x00000003U
-#define MCPWM_FH0_A_OST_D_M  (MCPWM_FH0_A_OST_D_V << MCPWM_FH0_A_OST_D_S)
-#define MCPWM_FH0_A_OST_D_V  0x00000003U
-#define MCPWM_FH0_A_OST_D_S  12
-/** MCPWM_FH0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM0 A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_A_OST_U    0x00000003U
-#define MCPWM_FH0_A_OST_U_M  (MCPWM_FH0_A_OST_U_V << MCPWM_FH0_A_OST_U_S)
-#define MCPWM_FH0_A_OST_U_V  0x00000003U
-#define MCPWM_FH0_A_OST_U_S  14
-/** MCPWM_FH0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_B_CBC_D    0x00000003U
-#define MCPWM_FH0_B_CBC_D_M  (MCPWM_FH0_B_CBC_D_V << MCPWM_FH0_B_CBC_D_S)
-#define MCPWM_FH0_B_CBC_D_V  0x00000003U
-#define MCPWM_FH0_B_CBC_D_S  16
-/** MCPWM_FH0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM0 B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_B_CBC_U    0x00000003U
-#define MCPWM_FH0_B_CBC_U_M  (MCPWM_FH0_B_CBC_U_V << MCPWM_FH0_B_CBC_U_S)
-#define MCPWM_FH0_B_CBC_U_V  0x00000003U
-#define MCPWM_FH0_B_CBC_U_S  18
-/** MCPWM_FH0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM0 B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_B_OST_D    0x00000003U
-#define MCPWM_FH0_B_OST_D_M  (MCPWM_FH0_B_OST_D_V << MCPWM_FH0_B_OST_D_S)
-#define MCPWM_FH0_B_OST_D_V  0x00000003U
-#define MCPWM_FH0_B_OST_D_S  20
-/** MCPWM_FH0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM0 B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH0_B_OST_U    0x00000003U
-#define MCPWM_FH0_B_OST_U_M  (MCPWM_FH0_B_OST_U_V << MCPWM_FH0_B_OST_U_S)
-#define MCPWM_FH0_B_OST_U_V  0x00000003U
-#define MCPWM_FH0_B_OST_U_S  22
-
-/** MCPWM_FH0_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c)
-/** MCPWM_FH0_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_FH0_CLR_OST    (BIT(0))
-#define MCPWM_FH0_CLR_OST_M  (MCPWM_FH0_CLR_OST_V << MCPWM_FH0_CLR_OST_S)
-#define MCPWM_FH0_CLR_OST_V  0x00000001U
-#define MCPWM_FH0_CLR_OST_S  0
-/** MCPWM_FH0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_FH0_CBCPULSE    0x00000003U
-#define MCPWM_FH0_CBCPULSE_M  (MCPWM_FH0_CBCPULSE_V << MCPWM_FH0_CBCPULSE_S)
-#define MCPWM_FH0_CBCPULSE_V  0x00000003U
-#define MCPWM_FH0_CBCPULSE_S  1
-/** MCPWM_FH0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_FH0_FORCE_CBC    (BIT(3))
-#define MCPWM_FH0_FORCE_CBC_M  (MCPWM_FH0_FORCE_CBC_V << MCPWM_FH0_FORCE_CBC_S)
-#define MCPWM_FH0_FORCE_CBC_V  0x00000001U
-#define MCPWM_FH0_FORCE_CBC_S  3
-/** MCPWM_FH0_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_FH0_FORCE_OST    (BIT(4))
-#define MCPWM_FH0_FORCE_OST_M  (MCPWM_FH0_FORCE_OST_V << MCPWM_FH0_FORCE_OST_S)
-#define MCPWM_FH0_FORCE_OST_V  0x00000001U
-#define MCPWM_FH0_FORCE_OST_S  4
-
-/** MCPWM_FH0_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70)
-/** MCPWM_FH0_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_FH0_CBC_ON    (BIT(0))
-#define MCPWM_FH0_CBC_ON_M  (MCPWM_FH0_CBC_ON_V << MCPWM_FH0_CBC_ON_S)
-#define MCPWM_FH0_CBC_ON_V  0x00000001U
-#define MCPWM_FH0_CBC_ON_S  0
-/** MCPWM_FH0_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_FH0_OST_ON    (BIT(1))
-#define MCPWM_FH0_OST_ON_M  (MCPWM_FH0_OST_ON_V << MCPWM_FH0_OST_ON_S)
-#define MCPWM_FH0_OST_ON_V  0x00000001U
-#define MCPWM_FH0_OST_ON_S  1
-
-/** MCPWM_GEN1_STMP_CFG_REG register
- *  Generator1 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74)
-/** MCPWM_GEN1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 1 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN1_A_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_A_UPMETHOD_M  (MCPWM_GEN1_A_UPMETHOD_V << MCPWM_GEN1_A_UPMETHOD_S)
-#define MCPWM_GEN1_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_A_UPMETHOD_S  0
-/** MCPWM_GEN1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 1 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN1_B_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_B_UPMETHOD_M  (MCPWM_GEN1_B_UPMETHOD_V << MCPWM_GEN1_B_UPMETHOD_S)
-#define MCPWM_GEN1_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_B_UPMETHOD_S  4
-/** MCPWM_GEN1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_GEN1_A_SHDW_FULL    (BIT(8))
-#define MCPWM_GEN1_A_SHDW_FULL_M  (MCPWM_GEN1_A_SHDW_FULL_V << MCPWM_GEN1_A_SHDW_FULL_S)
-#define MCPWM_GEN1_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN1_A_SHDW_FULL_S  8
-/** MCPWM_GEN1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_GEN1_B_SHDW_FULL    (BIT(9))
-#define MCPWM_GEN1_B_SHDW_FULL_M  (MCPWM_GEN1_B_SHDW_FULL_V << MCPWM_GEN1_B_SHDW_FULL_S)
-#define MCPWM_GEN1_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN1_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN1_TSTMP_A_REG register
- *  Generator1 time stamp A's shadow register
- */
-#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78)
-/** MCPWM_GEN1_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator 1 time stamp A's shadow register.
- */
-#define MCPWM_GEN1_A    0x0000FFFFU
-#define MCPWM_GEN1_A_M  (MCPWM_GEN1_A_V << MCPWM_GEN1_A_S)
-#define MCPWM_GEN1_A_V  0x0000FFFFU
-#define MCPWM_GEN1_A_S  0
-
-/** MCPWM_GEN1_TSTMP_B_REG register
- *  Generator1 time stamp B's shadow register
- */
-#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c)
-/** MCPWM_GEN1_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator 1 time stamp B's shadow register.
- */
-#define MCPWM_GEN1_B    0x0000FFFFU
-#define MCPWM_GEN1_B_M  (MCPWM_GEN1_B_V << MCPWM_GEN1_B_S)
-#define MCPWM_GEN1_B_V  0x0000FFFFU
-#define MCPWM_GEN1_B_S  0
-
-/** MCPWM_GEN1_CFG0_REG register
- *  Generator1 fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80)
-/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator 1's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
-#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_S  0
-/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator 1 event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN1_T0_SEL    0x00000007U
-#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
-#define MCPWM_GEN1_T0_SEL_V  0x00000007U
-#define MCPWM_GEN1_T0_SEL_S  4
-/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator 1 event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN1_T1_SEL    0x00000007U
-#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
-#define MCPWM_GEN1_T1_SEL_V  0x00000007U
-#define MCPWM_GEN1_T1_SEL_S  7
-
-/** MCPWM_GEN1_FORCE_REG register
- *  Generator1 output signal force mode register.
- */
-#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84)
-/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator1.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM1 A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM1 B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for PWM1
- *  A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
-#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_A_NCIFORCE_S  10
-/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM1 A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for PWM1
- *  B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
-#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_B_NCIFORCE_S  13
-/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM1 B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN1_A_REG register
- *  PWM1 output signal A actions configuration register
- */
-#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88)
-/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM1 A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEZ    0x00000003U
-#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
-#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_UTEZ_S  0
-/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM1 A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEP    0x00000003U
-#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
-#define MCPWM_GEN1_A_UTEP_V  0x00000003U
-#define MCPWM_GEN1_A_UTEP_S  2
-/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM1 A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEA    0x00000003U
-#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
-#define MCPWM_GEN1_A_UTEA_V  0x00000003U
-#define MCPWM_GEN1_A_UTEA_S  4
-/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM1 A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEB    0x00000003U
-#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
-#define MCPWM_GEN1_A_UTEB_V  0x00000003U
-#define MCPWM_GEN1_A_UTEB_S  6
-/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM1 A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UT0    0x00000003U
-#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
-#define MCPWM_GEN1_A_UT0_V  0x00000003U
-#define MCPWM_GEN1_A_UT0_S  8
-/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM1 A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UT1    0x00000003U
-#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
-#define MCPWM_GEN1_A_UT1_V  0x00000003U
-#define MCPWM_GEN1_A_UT1_S  10
-/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM1 A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEZ    0x00000003U
-#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
-#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_DTEZ_S  12
-/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM1 A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEP    0x00000003U
-#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
-#define MCPWM_GEN1_A_DTEP_V  0x00000003U
-#define MCPWM_GEN1_A_DTEP_S  14
-/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM1 A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEA    0x00000003U
-#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
-#define MCPWM_GEN1_A_DTEA_V  0x00000003U
-#define MCPWM_GEN1_A_DTEA_S  16
-/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM1 A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEB    0x00000003U
-#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
-#define MCPWM_GEN1_A_DTEB_V  0x00000003U
-#define MCPWM_GEN1_A_DTEB_S  18
-/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM1 A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DT0    0x00000003U
-#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
-#define MCPWM_GEN1_A_DT0_V  0x00000003U
-#define MCPWM_GEN1_A_DT0_S  20
-/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM1 A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DT1    0x00000003U
-#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
-#define MCPWM_GEN1_A_DT1_V  0x00000003U
-#define MCPWM_GEN1_A_DT1_S  22
-
-/** MCPWM_GEN1_B_REG register
- *  PWM1 output signal B actions configuration register
- */
-#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c)
-/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM1 B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEZ    0x00000003U
-#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
-#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_UTEZ_S  0
-/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM1 B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEP    0x00000003U
-#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
-#define MCPWM_GEN1_B_UTEP_V  0x00000003U
-#define MCPWM_GEN1_B_UTEP_S  2
-/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM1 B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEA    0x00000003U
-#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
-#define MCPWM_GEN1_B_UTEA_V  0x00000003U
-#define MCPWM_GEN1_B_UTEA_S  4
-/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM1 B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEB    0x00000003U
-#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
-#define MCPWM_GEN1_B_UTEB_V  0x00000003U
-#define MCPWM_GEN1_B_UTEB_S  6
-/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM1 B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UT0    0x00000003U
-#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
-#define MCPWM_GEN1_B_UT0_V  0x00000003U
-#define MCPWM_GEN1_B_UT0_S  8
-/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM1 B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UT1    0x00000003U
-#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
-#define MCPWM_GEN1_B_UT1_V  0x00000003U
-#define MCPWM_GEN1_B_UT1_S  10
-/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM1 B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEZ    0x00000003U
-#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
-#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_DTEZ_S  12
-/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM1 B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEP    0x00000003U
-#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
-#define MCPWM_GEN1_B_DTEP_V  0x00000003U
-#define MCPWM_GEN1_B_DTEP_S  14
-/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM1 B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEA    0x00000003U
-#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
-#define MCPWM_GEN1_B_DTEA_V  0x00000003U
-#define MCPWM_GEN1_B_DTEA_S  16
-/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM1 B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEB    0x00000003U
-#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
-#define MCPWM_GEN1_B_DTEB_V  0x00000003U
-#define MCPWM_GEN1_B_DTEB_S  18
-/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM1 B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DT0    0x00000003U
-#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
-#define MCPWM_GEN1_B_DT0_V  0x00000003U
-#define MCPWM_GEN1_B_DT0_S  20
-/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM1 B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DT1    0x00000003U
-#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
-#define MCPWM_GEN1_B_DT1_V  0x00000003U
-#define MCPWM_GEN1_B_DT1_S  22
-
-/** MCPWM_DT1_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
-/** MCPWM_DT1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DT1_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DT1_FED_UPMETHOD_M  (MCPWM_DT1_FED_UPMETHOD_V << MCPWM_DT1_FED_UPMETHOD_S)
-#define MCPWM_DT1_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT1_FED_UPMETHOD_S  0
-/** MCPWM_DT1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DT1_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DT1_RED_UPMETHOD_M  (MCPWM_DT1_RED_UPMETHOD_V << MCPWM_DT1_RED_UPMETHOD_S)
-#define MCPWM_DT1_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT1_RED_UPMETHOD_S  4
-/** MCPWM_DT1_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DT1_DEB_MODE    (BIT(8))
-#define MCPWM_DT1_DEB_MODE_M  (MCPWM_DT1_DEB_MODE_V << MCPWM_DT1_DEB_MODE_S)
-#define MCPWM_DT1_DEB_MODE_V  0x00000001U
-#define MCPWM_DT1_DEB_MODE_S  8
-/** MCPWM_DT1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DT1_A_OUTSWAP    (BIT(9))
-#define MCPWM_DT1_A_OUTSWAP_M  (MCPWM_DT1_A_OUTSWAP_V << MCPWM_DT1_A_OUTSWAP_S)
-#define MCPWM_DT1_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DT1_A_OUTSWAP_S  9
-/** MCPWM_DT1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DT1_B_OUTSWAP    (BIT(10))
-#define MCPWM_DT1_B_OUTSWAP_M  (MCPWM_DT1_B_OUTSWAP_V << MCPWM_DT1_B_OUTSWAP_S)
-#define MCPWM_DT1_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DT1_B_OUTSWAP_S  10
-/** MCPWM_DT1_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DT1_RED_INSEL    (BIT(11))
-#define MCPWM_DT1_RED_INSEL_M  (MCPWM_DT1_RED_INSEL_V << MCPWM_DT1_RED_INSEL_S)
-#define MCPWM_DT1_RED_INSEL_V  0x00000001U
-#define MCPWM_DT1_RED_INSEL_S  11
-/** MCPWM_DT1_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DT1_FED_INSEL    (BIT(12))
-#define MCPWM_DT1_FED_INSEL_M  (MCPWM_DT1_FED_INSEL_V << MCPWM_DT1_FED_INSEL_S)
-#define MCPWM_DT1_FED_INSEL_V  0x00000001U
-#define MCPWM_DT1_FED_INSEL_S  12
-/** MCPWM_DT1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DT1_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DT1_RED_OUTINVERT_M  (MCPWM_DT1_RED_OUTINVERT_V << MCPWM_DT1_RED_OUTINVERT_S)
-#define MCPWM_DT1_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT1_RED_OUTINVERT_S  13
-/** MCPWM_DT1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DT1_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DT1_FED_OUTINVERT_M  (MCPWM_DT1_FED_OUTINVERT_V << MCPWM_DT1_FED_OUTINVERT_S)
-#define MCPWM_DT1_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT1_FED_OUTINVERT_S  14
-/** MCPWM_DT1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DT1_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DT1_A_OUTBYPASS_M  (MCPWM_DT1_A_OUTBYPASS_V << MCPWM_DT1_A_OUTBYPASS_S)
-#define MCPWM_DT1_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT1_A_OUTBYPASS_S  15
-/** MCPWM_DT1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DT1_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DT1_B_OUTBYPASS_M  (MCPWM_DT1_B_OUTBYPASS_V << MCPWM_DT1_B_OUTBYPASS_S)
-#define MCPWM_DT1_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT1_B_OUTBYPASS_S  16
-/** MCPWM_DT1_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator 1 clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DT1_CLK_SEL    (BIT(17))
-#define MCPWM_DT1_CLK_SEL_M  (MCPWM_DT1_CLK_SEL_V << MCPWM_DT1_CLK_SEL_S)
-#define MCPWM_DT1_CLK_SEL_V  0x00000001U
-#define MCPWM_DT1_CLK_SEL_S  17
-
-/** MCPWM_DT1_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
-/** MCPWM_DT1_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DT1_FED    0x0000FFFFU
-#define MCPWM_DT1_FED_M  (MCPWM_DT1_FED_V << MCPWM_DT1_FED_S)
-#define MCPWM_DT1_FED_V  0x0000FFFFU
-#define MCPWM_DT1_FED_S  0
-
-/** MCPWM_DT1_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
-/** MCPWM_DT1_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DT1_RED    0x0000FFFFU
-#define MCPWM_DT1_RED_M  (MCPWM_DT1_RED_V << MCPWM_DT1_RED_S)
-#define MCPWM_DT1_RED_V  0x0000FFFFU
-#define MCPWM_DT1_RED_S  0
-
-/** MCPWM_CARRIER1_CFG_REG register
- *  Carrier1 configuration register
- */
-#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c)
-/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier1.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CARRIER1_EN    (BIT(0))
-#define MCPWM_CARRIER1_EN_M  (MCPWM_CARRIER1_EN_V << MCPWM_CARRIER1_EN_S)
-#define MCPWM_CARRIER1_EN_V  0x00000001U
-#define MCPWM_CARRIER1_EN_S  0
-/** MCPWM_CARRIER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier1 clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)
- */
-#define MCPWM_CARRIER1_PRESCALE    0x0000000FU
-#define MCPWM_CARRIER1_PRESCALE_M  (MCPWM_CARRIER1_PRESCALE_V << MCPWM_CARRIER1_PRESCALE_S)
-#define MCPWM_CARRIER1_PRESCALE_V  0x0000000FU
-#define MCPWM_CARRIER1_PRESCALE_S  1
-/** MCPWM_CARRIER1_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER1_DUTY / 8
- */
-#define MCPWM_CARRIER1_DUTY    0x00000007U
-#define MCPWM_CARRIER1_DUTY_M  (MCPWM_CARRIER1_DUTY_V << MCPWM_CARRIER1_DUTY_S)
-#define MCPWM_CARRIER1_DUTY_V  0x00000007U
-#define MCPWM_CARRIER1_DUTY_S  5
-/** MCPWM_CARRIER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CARRIER1_OSHTWTH    0x0000000FU
-#define MCPWM_CARRIER1_OSHTWTH_M  (MCPWM_CARRIER1_OSHTWTH_V << MCPWM_CARRIER1_OSHTWTH_S)
-#define MCPWM_CARRIER1_OSHTWTH_V  0x0000000FU
-#define MCPWM_CARRIER1_OSHTWTH_S  8
-/** MCPWM_CARRIER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM1 A and PWM1 B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CARRIER1_OUT_INVERT    (BIT(12))
-#define MCPWM_CARRIER1_OUT_INVERT_M  (MCPWM_CARRIER1_OUT_INVERT_V << MCPWM_CARRIER1_OUT_INVERT_S)
-#define MCPWM_CARRIER1_OUT_INVERT_V  0x00000001U
-#define MCPWM_CARRIER1_OUT_INVERT_S  12
-/** MCPWM_CARRIER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM1 A and PWM1 B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CARRIER1_IN_INVERT    (BIT(13))
-#define MCPWM_CARRIER1_IN_INVERT_M  (MCPWM_CARRIER1_IN_INVERT_V << MCPWM_CARRIER1_IN_INVERT_S)
-#define MCPWM_CARRIER1_IN_INVERT_V  0x00000001U
-#define MCPWM_CARRIER1_IN_INVERT_S  13
-
-/** MCPWM_FH1_CFG0_REG register
- *  PWM1 A and PWM1 B trip events actions configuration register
- */
-#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0)
-/** MCPWM_FH1_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_SW_CBC    (BIT(0))
-#define MCPWM_FH1_SW_CBC_M  (MCPWM_FH1_SW_CBC_V << MCPWM_FH1_SW_CBC_S)
-#define MCPWM_FH1_SW_CBC_V  0x00000001U
-#define MCPWM_FH1_SW_CBC_S  0
-/** MCPWM_FH1_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_F2_CBC    (BIT(1))
-#define MCPWM_FH1_F2_CBC_M  (MCPWM_FH1_F2_CBC_V << MCPWM_FH1_F2_CBC_S)
-#define MCPWM_FH1_F2_CBC_V  0x00000001U
-#define MCPWM_FH1_F2_CBC_S  1
-/** MCPWM_FH1_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_F1_CBC    (BIT(2))
-#define MCPWM_FH1_F1_CBC_M  (MCPWM_FH1_F1_CBC_V << MCPWM_FH1_F1_CBC_S)
-#define MCPWM_FH1_F1_CBC_V  0x00000001U
-#define MCPWM_FH1_F1_CBC_S  2
-/** MCPWM_FH1_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_F0_CBC    (BIT(3))
-#define MCPWM_FH1_F0_CBC_M  (MCPWM_FH1_F0_CBC_V << MCPWM_FH1_F0_CBC_S)
-#define MCPWM_FH1_F0_CBC_V  0x00000001U
-#define MCPWM_FH1_F0_CBC_S  3
-/** MCPWM_FH1_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_SW_OST    (BIT(4))
-#define MCPWM_FH1_SW_OST_M  (MCPWM_FH1_SW_OST_V << MCPWM_FH1_SW_OST_S)
-#define MCPWM_FH1_SW_OST_V  0x00000001U
-#define MCPWM_FH1_SW_OST_S  4
-/** MCPWM_FH1_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_F2_OST    (BIT(5))
-#define MCPWM_FH1_F2_OST_M  (MCPWM_FH1_F2_OST_V << MCPWM_FH1_F2_OST_S)
-#define MCPWM_FH1_F2_OST_V  0x00000001U
-#define MCPWM_FH1_F2_OST_S  5
-/** MCPWM_FH1_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_F1_OST    (BIT(6))
-#define MCPWM_FH1_F1_OST_M  (MCPWM_FH1_F1_OST_V << MCPWM_FH1_F1_OST_S)
-#define MCPWM_FH1_F1_OST_V  0x00000001U
-#define MCPWM_FH1_F1_OST_S  6
-/** MCPWM_FH1_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH1_F0_OST    (BIT(7))
-#define MCPWM_FH1_F0_OST_M  (MCPWM_FH1_F0_OST_V << MCPWM_FH1_F0_OST_S)
-#define MCPWM_FH1_F0_OST_V  0x00000001U
-#define MCPWM_FH1_F0_OST_S  7
-/** MCPWM_FH1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_A_CBC_D    0x00000003U
-#define MCPWM_FH1_A_CBC_D_M  (MCPWM_FH1_A_CBC_D_V << MCPWM_FH1_A_CBC_D_S)
-#define MCPWM_FH1_A_CBC_D_V  0x00000003U
-#define MCPWM_FH1_A_CBC_D_S  8
-/** MCPWM_FH1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM1 A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_A_CBC_U    0x00000003U
-#define MCPWM_FH1_A_CBC_U_M  (MCPWM_FH1_A_CBC_U_V << MCPWM_FH1_A_CBC_U_S)
-#define MCPWM_FH1_A_CBC_U_V  0x00000003U
-#define MCPWM_FH1_A_CBC_U_S  10
-/** MCPWM_FH1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM1 A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_A_OST_D    0x00000003U
-#define MCPWM_FH1_A_OST_D_M  (MCPWM_FH1_A_OST_D_V << MCPWM_FH1_A_OST_D_S)
-#define MCPWM_FH1_A_OST_D_V  0x00000003U
-#define MCPWM_FH1_A_OST_D_S  12
-/** MCPWM_FH1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM1 A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_A_OST_U    0x00000003U
-#define MCPWM_FH1_A_OST_U_M  (MCPWM_FH1_A_OST_U_V << MCPWM_FH1_A_OST_U_S)
-#define MCPWM_FH1_A_OST_U_V  0x00000003U
-#define MCPWM_FH1_A_OST_U_S  14
-/** MCPWM_FH1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_B_CBC_D    0x00000003U
-#define MCPWM_FH1_B_CBC_D_M  (MCPWM_FH1_B_CBC_D_V << MCPWM_FH1_B_CBC_D_S)
-#define MCPWM_FH1_B_CBC_D_V  0x00000003U
-#define MCPWM_FH1_B_CBC_D_S  16
-/** MCPWM_FH1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM1 B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_B_CBC_U    0x00000003U
-#define MCPWM_FH1_B_CBC_U_M  (MCPWM_FH1_B_CBC_U_V << MCPWM_FH1_B_CBC_U_S)
-#define MCPWM_FH1_B_CBC_U_V  0x00000003U
-#define MCPWM_FH1_B_CBC_U_S  18
-/** MCPWM_FH1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM1 B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_B_OST_D    0x00000003U
-#define MCPWM_FH1_B_OST_D_M  (MCPWM_FH1_B_OST_D_V << MCPWM_FH1_B_OST_D_S)
-#define MCPWM_FH1_B_OST_D_V  0x00000003U
-#define MCPWM_FH1_B_OST_D_S  20
-/** MCPWM_FH1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM1 B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH1_B_OST_U    0x00000003U
-#define MCPWM_FH1_B_OST_U_M  (MCPWM_FH1_B_OST_U_V << MCPWM_FH1_B_OST_U_S)
-#define MCPWM_FH1_B_OST_U_V  0x00000003U
-#define MCPWM_FH1_B_OST_U_S  22
-
-/** MCPWM_FH1_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4)
-/** MCPWM_FH1_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_FH1_CLR_OST    (BIT(0))
-#define MCPWM_FH1_CLR_OST_M  (MCPWM_FH1_CLR_OST_V << MCPWM_FH1_CLR_OST_S)
-#define MCPWM_FH1_CLR_OST_V  0x00000001U
-#define MCPWM_FH1_CLR_OST_S  0
-/** MCPWM_FH1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_FH1_CBCPULSE    0x00000003U
-#define MCPWM_FH1_CBCPULSE_M  (MCPWM_FH1_CBCPULSE_V << MCPWM_FH1_CBCPULSE_S)
-#define MCPWM_FH1_CBCPULSE_V  0x00000003U
-#define MCPWM_FH1_CBCPULSE_S  1
-/** MCPWM_FH1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_FH1_FORCE_CBC    (BIT(3))
-#define MCPWM_FH1_FORCE_CBC_M  (MCPWM_FH1_FORCE_CBC_V << MCPWM_FH1_FORCE_CBC_S)
-#define MCPWM_FH1_FORCE_CBC_V  0x00000001U
-#define MCPWM_FH1_FORCE_CBC_S  3
-/** MCPWM_FH1_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_FH1_FORCE_OST    (BIT(4))
-#define MCPWM_FH1_FORCE_OST_M  (MCPWM_FH1_FORCE_OST_V << MCPWM_FH1_FORCE_OST_S)
-#define MCPWM_FH1_FORCE_OST_V  0x00000001U
-#define MCPWM_FH1_FORCE_OST_S  4
-
-/** MCPWM_FH1_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8)
-/** MCPWM_FH1_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_FH1_CBC_ON    (BIT(0))
-#define MCPWM_FH1_CBC_ON_M  (MCPWM_FH1_CBC_ON_V << MCPWM_FH1_CBC_ON_S)
-#define MCPWM_FH1_CBC_ON_V  0x00000001U
-#define MCPWM_FH1_CBC_ON_S  0
-/** MCPWM_FH1_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_FH1_OST_ON    (BIT(1))
-#define MCPWM_FH1_OST_ON_M  (MCPWM_FH1_OST_ON_V << MCPWM_FH1_OST_ON_S)
-#define MCPWM_FH1_OST_ON_V  0x00000001U
-#define MCPWM_FH1_OST_ON_S  1
-
-/** MCPWM_GEN2_STMP_CFG_REG register
- *  Generator2 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac)
-/** MCPWM_GEN2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 2 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN2_A_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_A_UPMETHOD_M  (MCPWM_GEN2_A_UPMETHOD_V << MCPWM_GEN2_A_UPMETHOD_S)
-#define MCPWM_GEN2_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_A_UPMETHOD_S  0
-/** MCPWM_GEN2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 2 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN2_B_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_B_UPMETHOD_M  (MCPWM_GEN2_B_UPMETHOD_V << MCPWM_GEN2_B_UPMETHOD_S)
-#define MCPWM_GEN2_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_B_UPMETHOD_S  4
-/** MCPWM_GEN2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_GEN2_A_SHDW_FULL    (BIT(8))
-#define MCPWM_GEN2_A_SHDW_FULL_M  (MCPWM_GEN2_A_SHDW_FULL_V << MCPWM_GEN2_A_SHDW_FULL_S)
-#define MCPWM_GEN2_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN2_A_SHDW_FULL_S  8
-/** MCPWM_GEN2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_GEN2_B_SHDW_FULL    (BIT(9))
-#define MCPWM_GEN2_B_SHDW_FULL_M  (MCPWM_GEN2_B_SHDW_FULL_V << MCPWM_GEN2_B_SHDW_FULL_S)
-#define MCPWM_GEN2_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN2_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN2_TSTMP_A_REG register
- *  Generator2 time stamp A's shadow register
- */
-#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0)
-/** MCPWM_GEN2_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator 2 time stamp A's shadow register.
- */
-#define MCPWM_GEN2_A    0x0000FFFFU
-#define MCPWM_GEN2_A_M  (MCPWM_GEN2_A_V << MCPWM_GEN2_A_S)
-#define MCPWM_GEN2_A_V  0x0000FFFFU
-#define MCPWM_GEN2_A_S  0
-
-/** MCPWM_GEN2_TSTMP_B_REG register
- *  Generator2 time stamp B's shadow register
- */
-#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4)
-/** MCPWM_GEN2_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator 2 time stamp B's shadow register.
- */
-#define MCPWM_GEN2_B    0x0000FFFFU
-#define MCPWM_GEN2_B_M  (MCPWM_GEN2_B_V << MCPWM_GEN2_B_S)
-#define MCPWM_GEN2_B_V  0x0000FFFFU
-#define MCPWM_GEN2_B_S  0
-
-/** MCPWM_GEN2_CFG0_REG register
- *  Generator2 fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8)
-/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator 2's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
-#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_S  0
-/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator 2 event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN2_T0_SEL    0x00000007U
-#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
-#define MCPWM_GEN2_T0_SEL_V  0x00000007U
-#define MCPWM_GEN2_T0_SEL_S  4
-/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator 2 event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN2_T1_SEL    0x00000007U
-#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
-#define MCPWM_GEN2_T1_SEL_V  0x00000007U
-#define MCPWM_GEN2_T1_SEL_S  7
-
-/** MCPWM_GEN2_FORCE_REG register
- *  Generator2 output signal force mode register.
- */
-#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc)
-/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator2.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM2 A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM2 B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for PWM2
- *  A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
-#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_A_NCIFORCE_S  10
-/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM2 A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for PWM2
- *  B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
-#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_B_NCIFORCE_S  13
-/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM2 B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN2_A_REG register
- *  PWM2 output signal A actions configuration register
- */
-#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0)
-/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM2 A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEZ    0x00000003U
-#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
-#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_UTEZ_S  0
-/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM2 A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEP    0x00000003U
-#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
-#define MCPWM_GEN2_A_UTEP_V  0x00000003U
-#define MCPWM_GEN2_A_UTEP_S  2
-/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM2 A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEA    0x00000003U
-#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
-#define MCPWM_GEN2_A_UTEA_V  0x00000003U
-#define MCPWM_GEN2_A_UTEA_S  4
-/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM2 A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEB    0x00000003U
-#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
-#define MCPWM_GEN2_A_UTEB_V  0x00000003U
-#define MCPWM_GEN2_A_UTEB_S  6
-/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM2 A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UT0    0x00000003U
-#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
-#define MCPWM_GEN2_A_UT0_V  0x00000003U
-#define MCPWM_GEN2_A_UT0_S  8
-/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM2 A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UT1    0x00000003U
-#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
-#define MCPWM_GEN2_A_UT1_V  0x00000003U
-#define MCPWM_GEN2_A_UT1_S  10
-/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM2 A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEZ    0x00000003U
-#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
-#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_DTEZ_S  12
-/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM2 A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEP    0x00000003U
-#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
-#define MCPWM_GEN2_A_DTEP_V  0x00000003U
-#define MCPWM_GEN2_A_DTEP_S  14
-/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM2 A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEA    0x00000003U
-#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
-#define MCPWM_GEN2_A_DTEA_V  0x00000003U
-#define MCPWM_GEN2_A_DTEA_S  16
-/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM2 A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEB    0x00000003U
-#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
-#define MCPWM_GEN2_A_DTEB_V  0x00000003U
-#define MCPWM_GEN2_A_DTEB_S  18
-/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM2 A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DT0    0x00000003U
-#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
-#define MCPWM_GEN2_A_DT0_V  0x00000003U
-#define MCPWM_GEN2_A_DT0_S  20
-/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM2 A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DT1    0x00000003U
-#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
-#define MCPWM_GEN2_A_DT1_V  0x00000003U
-#define MCPWM_GEN2_A_DT1_S  22
-
-/** MCPWM_GEN2_B_REG register
- *  PWM2 output signal B actions configuration register
- */
-#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4)
-/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM2 B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEZ    0x00000003U
-#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
-#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_UTEZ_S  0
-/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM2 B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEP    0x00000003U
-#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
-#define MCPWM_GEN2_B_UTEP_V  0x00000003U
-#define MCPWM_GEN2_B_UTEP_S  2
-/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM2 B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEA    0x00000003U
-#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
-#define MCPWM_GEN2_B_UTEA_V  0x00000003U
-#define MCPWM_GEN2_B_UTEA_S  4
-/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM2 B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEB    0x00000003U
-#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
-#define MCPWM_GEN2_B_UTEB_V  0x00000003U
-#define MCPWM_GEN2_B_UTEB_S  6
-/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM2 B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UT0    0x00000003U
-#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
-#define MCPWM_GEN2_B_UT0_V  0x00000003U
-#define MCPWM_GEN2_B_UT0_S  8
-/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM2 B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UT1    0x00000003U
-#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
-#define MCPWM_GEN2_B_UT1_V  0x00000003U
-#define MCPWM_GEN2_B_UT1_S  10
-/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM2 B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEZ    0x00000003U
-#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
-#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_DTEZ_S  12
-/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM2 B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEP    0x00000003U
-#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
-#define MCPWM_GEN2_B_DTEP_V  0x00000003U
-#define MCPWM_GEN2_B_DTEP_S  14
-/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM2 B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEA    0x00000003U
-#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
-#define MCPWM_GEN2_B_DTEA_V  0x00000003U
-#define MCPWM_GEN2_B_DTEA_S  16
-/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM2 B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEB    0x00000003U
-#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
-#define MCPWM_GEN2_B_DTEB_V  0x00000003U
-#define MCPWM_GEN2_B_DTEB_S  18
-/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM2 B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DT0    0x00000003U
-#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
-#define MCPWM_GEN2_B_DT0_V  0x00000003U
-#define MCPWM_GEN2_B_DT0_S  20
-/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM2 B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DT1    0x00000003U
-#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
-#define MCPWM_GEN2_B_DT1_V  0x00000003U
-#define MCPWM_GEN2_B_DT1_S  22
-
-/** MCPWM_DT2_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
-/** MCPWM_DT2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DT2_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DT2_FED_UPMETHOD_M  (MCPWM_DT2_FED_UPMETHOD_V << MCPWM_DT2_FED_UPMETHOD_S)
-#define MCPWM_DT2_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT2_FED_UPMETHOD_S  0
-/** MCPWM_DT2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DT2_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DT2_RED_UPMETHOD_M  (MCPWM_DT2_RED_UPMETHOD_V << MCPWM_DT2_RED_UPMETHOD_S)
-#define MCPWM_DT2_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT2_RED_UPMETHOD_S  4
-/** MCPWM_DT2_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DT2_DEB_MODE    (BIT(8))
-#define MCPWM_DT2_DEB_MODE_M  (MCPWM_DT2_DEB_MODE_V << MCPWM_DT2_DEB_MODE_S)
-#define MCPWM_DT2_DEB_MODE_V  0x00000001U
-#define MCPWM_DT2_DEB_MODE_S  8
-/** MCPWM_DT2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DT2_A_OUTSWAP    (BIT(9))
-#define MCPWM_DT2_A_OUTSWAP_M  (MCPWM_DT2_A_OUTSWAP_V << MCPWM_DT2_A_OUTSWAP_S)
-#define MCPWM_DT2_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DT2_A_OUTSWAP_S  9
-/** MCPWM_DT2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DT2_B_OUTSWAP    (BIT(10))
-#define MCPWM_DT2_B_OUTSWAP_M  (MCPWM_DT2_B_OUTSWAP_V << MCPWM_DT2_B_OUTSWAP_S)
-#define MCPWM_DT2_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DT2_B_OUTSWAP_S  10
-/** MCPWM_DT2_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DT2_RED_INSEL    (BIT(11))
-#define MCPWM_DT2_RED_INSEL_M  (MCPWM_DT2_RED_INSEL_V << MCPWM_DT2_RED_INSEL_S)
-#define MCPWM_DT2_RED_INSEL_V  0x00000001U
-#define MCPWM_DT2_RED_INSEL_S  11
-/** MCPWM_DT2_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DT2_FED_INSEL    (BIT(12))
-#define MCPWM_DT2_FED_INSEL_M  (MCPWM_DT2_FED_INSEL_V << MCPWM_DT2_FED_INSEL_S)
-#define MCPWM_DT2_FED_INSEL_V  0x00000001U
-#define MCPWM_DT2_FED_INSEL_S  12
-/** MCPWM_DT2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DT2_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DT2_RED_OUTINVERT_M  (MCPWM_DT2_RED_OUTINVERT_V << MCPWM_DT2_RED_OUTINVERT_S)
-#define MCPWM_DT2_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT2_RED_OUTINVERT_S  13
-/** MCPWM_DT2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DT2_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DT2_FED_OUTINVERT_M  (MCPWM_DT2_FED_OUTINVERT_V << MCPWM_DT2_FED_OUTINVERT_S)
-#define MCPWM_DT2_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT2_FED_OUTINVERT_S  14
-/** MCPWM_DT2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DT2_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DT2_A_OUTBYPASS_M  (MCPWM_DT2_A_OUTBYPASS_V << MCPWM_DT2_A_OUTBYPASS_S)
-#define MCPWM_DT2_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT2_A_OUTBYPASS_S  15
-/** MCPWM_DT2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DT2_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DT2_B_OUTBYPASS_M  (MCPWM_DT2_B_OUTBYPASS_V << MCPWM_DT2_B_OUTBYPASS_S)
-#define MCPWM_DT2_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT2_B_OUTBYPASS_S  16
-/** MCPWM_DT2_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator 2 clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DT2_CLK_SEL    (BIT(17))
-#define MCPWM_DT2_CLK_SEL_M  (MCPWM_DT2_CLK_SEL_V << MCPWM_DT2_CLK_SEL_S)
-#define MCPWM_DT2_CLK_SEL_V  0x00000001U
-#define MCPWM_DT2_CLK_SEL_S  17
-
-/** MCPWM_DT2_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
-/** MCPWM_DT2_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DT2_FED    0x0000FFFFU
-#define MCPWM_DT2_FED_M  (MCPWM_DT2_FED_V << MCPWM_DT2_FED_S)
-#define MCPWM_DT2_FED_V  0x0000FFFFU
-#define MCPWM_DT2_FED_S  0
-
-/** MCPWM_DT2_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
-/** MCPWM_DT2_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DT2_RED    0x0000FFFFU
-#define MCPWM_DT2_RED_M  (MCPWM_DT2_RED_V << MCPWM_DT2_RED_S)
-#define MCPWM_DT2_RED_V  0x0000FFFFU
-#define MCPWM_DT2_RED_S  0
-
-/** MCPWM_CARRIER2_CFG_REG register
- *  Carrier2 configuration register
- */
-#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4)
-/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier2.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CARRIER2_EN    (BIT(0))
-#define MCPWM_CARRIER2_EN_M  (MCPWM_CARRIER2_EN_V << MCPWM_CARRIER2_EN_S)
-#define MCPWM_CARRIER2_EN_V  0x00000001U
-#define MCPWM_CARRIER2_EN_S  0
-/** MCPWM_CARRIER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier2 clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)
- */
-#define MCPWM_CARRIER2_PRESCALE    0x0000000FU
-#define MCPWM_CARRIER2_PRESCALE_M  (MCPWM_CARRIER2_PRESCALE_V << MCPWM_CARRIER2_PRESCALE_S)
-#define MCPWM_CARRIER2_PRESCALE_V  0x0000000FU
-#define MCPWM_CARRIER2_PRESCALE_S  1
-/** MCPWM_CARRIER2_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER2_DUTY / 8
- */
-#define MCPWM_CARRIER2_DUTY    0x00000007U
-#define MCPWM_CARRIER2_DUTY_M  (MCPWM_CARRIER2_DUTY_V << MCPWM_CARRIER2_DUTY_S)
-#define MCPWM_CARRIER2_DUTY_V  0x00000007U
-#define MCPWM_CARRIER2_DUTY_S  5
-/** MCPWM_CARRIER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CARRIER2_OSHTWTH    0x0000000FU
-#define MCPWM_CARRIER2_OSHTWTH_M  (MCPWM_CARRIER2_OSHTWTH_V << MCPWM_CARRIER2_OSHTWTH_S)
-#define MCPWM_CARRIER2_OSHTWTH_V  0x0000000FU
-#define MCPWM_CARRIER2_OSHTWTH_S  8
-/** MCPWM_CARRIER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM2 A and PWM2 B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CARRIER2_OUT_INVERT    (BIT(12))
-#define MCPWM_CARRIER2_OUT_INVERT_M  (MCPWM_CARRIER2_OUT_INVERT_V << MCPWM_CARRIER2_OUT_INVERT_S)
-#define MCPWM_CARRIER2_OUT_INVERT_V  0x00000001U
-#define MCPWM_CARRIER2_OUT_INVERT_S  12
-/** MCPWM_CARRIER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM2 A and PWM2 B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CARRIER2_IN_INVERT    (BIT(13))
-#define MCPWM_CARRIER2_IN_INVERT_M  (MCPWM_CARRIER2_IN_INVERT_V << MCPWM_CARRIER2_IN_INVERT_S)
-#define MCPWM_CARRIER2_IN_INVERT_V  0x00000001U
-#define MCPWM_CARRIER2_IN_INVERT_S  13
-
-/** MCPWM_FH2_CFG0_REG register
- *  PWM2 A and PWM2 B trip events actions configuration register
- */
-#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8)
-/** MCPWM_FH2_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_SW_CBC    (BIT(0))
-#define MCPWM_FH2_SW_CBC_M  (MCPWM_FH2_SW_CBC_V << MCPWM_FH2_SW_CBC_S)
-#define MCPWM_FH2_SW_CBC_V  0x00000001U
-#define MCPWM_FH2_SW_CBC_S  0
-/** MCPWM_FH2_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_F2_CBC    (BIT(1))
-#define MCPWM_FH2_F2_CBC_M  (MCPWM_FH2_F2_CBC_V << MCPWM_FH2_F2_CBC_S)
-#define MCPWM_FH2_F2_CBC_V  0x00000001U
-#define MCPWM_FH2_F2_CBC_S  1
-/** MCPWM_FH2_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_F1_CBC    (BIT(2))
-#define MCPWM_FH2_F1_CBC_M  (MCPWM_FH2_F1_CBC_V << MCPWM_FH2_F1_CBC_S)
-#define MCPWM_FH2_F1_CBC_V  0x00000001U
-#define MCPWM_FH2_F1_CBC_S  2
-/** MCPWM_FH2_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_F0_CBC    (BIT(3))
-#define MCPWM_FH2_F0_CBC_M  (MCPWM_FH2_F0_CBC_V << MCPWM_FH2_F0_CBC_S)
-#define MCPWM_FH2_F0_CBC_V  0x00000001U
-#define MCPWM_FH2_F0_CBC_S  3
-/** MCPWM_FH2_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_SW_OST    (BIT(4))
-#define MCPWM_FH2_SW_OST_M  (MCPWM_FH2_SW_OST_V << MCPWM_FH2_SW_OST_S)
-#define MCPWM_FH2_SW_OST_V  0x00000001U
-#define MCPWM_FH2_SW_OST_S  4
-/** MCPWM_FH2_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_F2_OST    (BIT(5))
-#define MCPWM_FH2_F2_OST_M  (MCPWM_FH2_F2_OST_V << MCPWM_FH2_F2_OST_S)
-#define MCPWM_FH2_F2_OST_V  0x00000001U
-#define MCPWM_FH2_F2_OST_S  5
-/** MCPWM_FH2_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_F1_OST    (BIT(6))
-#define MCPWM_FH2_F1_OST_M  (MCPWM_FH2_F1_OST_V << MCPWM_FH2_F1_OST_S)
-#define MCPWM_FH2_F1_OST_V  0x00000001U
-#define MCPWM_FH2_F1_OST_S  6
-/** MCPWM_FH2_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_FH2_F0_OST    (BIT(7))
-#define MCPWM_FH2_F0_OST_M  (MCPWM_FH2_F0_OST_V << MCPWM_FH2_F0_OST_S)
-#define MCPWM_FH2_F0_OST_V  0x00000001U
-#define MCPWM_FH2_F0_OST_S  7
-/** MCPWM_FH2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_A_CBC_D    0x00000003U
-#define MCPWM_FH2_A_CBC_D_M  (MCPWM_FH2_A_CBC_D_V << MCPWM_FH2_A_CBC_D_S)
-#define MCPWM_FH2_A_CBC_D_V  0x00000003U
-#define MCPWM_FH2_A_CBC_D_S  8
-/** MCPWM_FH2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM2 A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_A_CBC_U    0x00000003U
-#define MCPWM_FH2_A_CBC_U_M  (MCPWM_FH2_A_CBC_U_V << MCPWM_FH2_A_CBC_U_S)
-#define MCPWM_FH2_A_CBC_U_V  0x00000003U
-#define MCPWM_FH2_A_CBC_U_S  10
-/** MCPWM_FH2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM2 A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_A_OST_D    0x00000003U
-#define MCPWM_FH2_A_OST_D_M  (MCPWM_FH2_A_OST_D_V << MCPWM_FH2_A_OST_D_S)
-#define MCPWM_FH2_A_OST_D_V  0x00000003U
-#define MCPWM_FH2_A_OST_D_S  12
-/** MCPWM_FH2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM2 A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_A_OST_U    0x00000003U
-#define MCPWM_FH2_A_OST_U_M  (MCPWM_FH2_A_OST_U_V << MCPWM_FH2_A_OST_U_S)
-#define MCPWM_FH2_A_OST_U_V  0x00000003U
-#define MCPWM_FH2_A_OST_U_S  14
-/** MCPWM_FH2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_B_CBC_D    0x00000003U
-#define MCPWM_FH2_B_CBC_D_M  (MCPWM_FH2_B_CBC_D_V << MCPWM_FH2_B_CBC_D_S)
-#define MCPWM_FH2_B_CBC_D_V  0x00000003U
-#define MCPWM_FH2_B_CBC_D_S  16
-/** MCPWM_FH2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM2 B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_B_CBC_U    0x00000003U
-#define MCPWM_FH2_B_CBC_U_M  (MCPWM_FH2_B_CBC_U_V << MCPWM_FH2_B_CBC_U_S)
-#define MCPWM_FH2_B_CBC_U_V  0x00000003U
-#define MCPWM_FH2_B_CBC_U_S  18
-/** MCPWM_FH2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM2 B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_B_OST_D    0x00000003U
-#define MCPWM_FH2_B_OST_D_M  (MCPWM_FH2_B_OST_D_V << MCPWM_FH2_B_OST_D_S)
-#define MCPWM_FH2_B_OST_D_V  0x00000003U
-#define MCPWM_FH2_B_OST_D_S  20
-/** MCPWM_FH2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM2 B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_FH2_B_OST_U    0x00000003U
-#define MCPWM_FH2_B_OST_U_M  (MCPWM_FH2_B_OST_U_V << MCPWM_FH2_B_OST_U_S)
-#define MCPWM_FH2_B_OST_U_V  0x00000003U
-#define MCPWM_FH2_B_OST_U_S  22
-
-/** MCPWM_FH2_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc)
-/** MCPWM_FH2_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_FH2_CLR_OST    (BIT(0))
-#define MCPWM_FH2_CLR_OST_M  (MCPWM_FH2_CLR_OST_V << MCPWM_FH2_CLR_OST_S)
-#define MCPWM_FH2_CLR_OST_V  0x00000001U
-#define MCPWM_FH2_CLR_OST_S  0
-/** MCPWM_FH2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_FH2_CBCPULSE    0x00000003U
-#define MCPWM_FH2_CBCPULSE_M  (MCPWM_FH2_CBCPULSE_V << MCPWM_FH2_CBCPULSE_S)
-#define MCPWM_FH2_CBCPULSE_V  0x00000003U
-#define MCPWM_FH2_CBCPULSE_S  1
-/** MCPWM_FH2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_FH2_FORCE_CBC    (BIT(3))
-#define MCPWM_FH2_FORCE_CBC_M  (MCPWM_FH2_FORCE_CBC_V << MCPWM_FH2_FORCE_CBC_S)
-#define MCPWM_FH2_FORCE_CBC_V  0x00000001U
-#define MCPWM_FH2_FORCE_CBC_S  3
-/** MCPWM_FH2_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_FH2_FORCE_OST    (BIT(4))
-#define MCPWM_FH2_FORCE_OST_M  (MCPWM_FH2_FORCE_OST_V << MCPWM_FH2_FORCE_OST_S)
-#define MCPWM_FH2_FORCE_OST_V  0x00000001U
-#define MCPWM_FH2_FORCE_OST_S  4
-
-/** MCPWM_FH2_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0)
-/** MCPWM_FH2_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_FH2_CBC_ON    (BIT(0))
-#define MCPWM_FH2_CBC_ON_M  (MCPWM_FH2_CBC_ON_V << MCPWM_FH2_CBC_ON_S)
-#define MCPWM_FH2_CBC_ON_V  0x00000001U
-#define MCPWM_FH2_CBC_ON_S  0
-/** MCPWM_FH2_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_FH2_OST_ON    (BIT(1))
-#define MCPWM_FH2_OST_ON_M  (MCPWM_FH2_OST_ON_V << MCPWM_FH2_OST_ON_S)
-#define MCPWM_FH2_OST_ON_V  0x00000001U
-#define MCPWM_FH2_OST_ON_S  1
-
-/** MCPWM_FAULT_DETECT_REG register
- *  Fault detection configuration and status register
- */
-#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4)
-/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F0_EN    (BIT(0))
-#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
-#define MCPWM_F0_EN_V  0x00000001U
-#define MCPWM_F0_EN_S  0
-/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F1_EN    (BIT(1))
-#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
-#define MCPWM_F1_EN_V  0x00000001U
-#define MCPWM_F1_EN_S  1
-/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F2_EN    (BIT(2))
-#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
-#define MCPWM_F2_EN_V  0x00000001U
-#define MCPWM_F2_EN_S  2
-/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
- *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F0_POLE    (BIT(3))
-#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
-#define MCPWM_F0_POLE_V  0x00000001U
-#define MCPWM_F0_POLE_S  3
-/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
- *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F1_POLE    (BIT(4))
-#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
-#define MCPWM_F1_POLE_V  0x00000001U
-#define MCPWM_F1_POLE_S  4
-/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
- *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F2_POLE    (BIT(5))
-#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
-#define MCPWM_F2_POLE_V  0x00000001U
-#define MCPWM_F2_POLE_S  5
-/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
- *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F0    (BIT(6))
-#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
-#define MCPWM_EVENT_F0_V  0x00000001U
-#define MCPWM_EVENT_F0_S  6
-/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
- *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F1    (BIT(7))
-#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
-#define MCPWM_EVENT_F1_V  0x00000001U
-#define MCPWM_EVENT_F1_S  7
-/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
- *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F2    (BIT(8))
-#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
-#define MCPWM_EVENT_F2_V  0x00000001U
-#define MCPWM_EVENT_F2_S  8
-
-/** MCPWM_CAP_TIMER_CFG_REG register
- *  Capture timer configuration register
- */
-#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8)
-/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP_TIMER_EN    (BIT(0))
-#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
-#define MCPWM_CAP_TIMER_EN_V  0x00000001U
-#define MCPWM_CAP_TIMER_EN_S  0
-/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP_SYNCI_EN    (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
-#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
-#define MCPWM_CAP_SYNCI_EN_S  1
-/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
- *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
- *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
- *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
- */
-#define MCPWM_CAP_SYNCI_SEL    0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
-#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_S  2
-/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
- *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
- *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
- *  value in phase register
- */
-#define MCPWM_CAP_SYNC_SW    (BIT(5))
-#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
-#define MCPWM_CAP_SYNC_SW_V  0x00000001U
-#define MCPWM_CAP_SYNC_SW_S  5
-
-/** MCPWM_CAP_TIMER_PHASE_REG register
- *  Capture timer sync phase register
- */
-#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec)
-/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
- *  Configures phase value for capture timer sync operation.
- */
-#define MCPWM_CAP_PHASE    0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
-#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_S  0
-
-/** MCPWM_CAP_CH0_CFG_REG register
- *  Capture channel 0 configuration register
- */
-#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 0 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP0. Prescale value =
- *  PWM_CAP0_PRESCALE + 1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 0
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH1_CFG_REG register
- *  Capture channel 1 configuration register
- */
-#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
-/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP1_EN    (BIT(0))
-#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
-#define MCPWM_CAP1_EN_V  0x00000001U
-#define MCPWM_CAP1_EN_S  0
-/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 1 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP1_MODE    0x00000003U
-#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
-#define MCPWM_CAP1_MODE_V  0x00000003U
-#define MCPWM_CAP1_MODE_S  1
-/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP1. Prescale value =
- *  PWM_CAP1_PRESCALE + 1
- */
-#define MCPWM_CAP1_PRESCALE    0x000000FFU
-#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
-#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP1_PRESCALE_S  3
-/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP1_IN_INVERT    (BIT(11))
-#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
-#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP1_IN_INVERT_S  11
-/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 1
- */
-#define MCPWM_CAP1_SW    (BIT(12))
-#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
-#define MCPWM_CAP1_SW_V  0x00000001U
-#define MCPWM_CAP1_SW_S  12
-
-/** MCPWM_CAP_CH2_CFG_REG register
- *  Capture channel 2 configuration register
- */
-#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8)
-/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP2_EN    (BIT(0))
-#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
-#define MCPWM_CAP2_EN_V  0x00000001U
-#define MCPWM_CAP2_EN_S  0
-/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 2 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP2_MODE    0x00000003U
-#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
-#define MCPWM_CAP2_MODE_V  0x00000003U
-#define MCPWM_CAP2_MODE_S  1
-/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP2. Prescale value =
- *  PWM_CAP2_PRESCALE + 1
- */
-#define MCPWM_CAP2_PRESCALE    0x000000FFU
-#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
-#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP2_PRESCALE_S  3
-/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP2_IN_INVERT    (BIT(11))
-#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
-#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP2_IN_INVERT_S  11
-/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 2
- */
-#define MCPWM_CAP2_SW    (BIT(12))
-#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
-#define MCPWM_CAP2_SW_V  0x00000001U
-#define MCPWM_CAP2_SW_S  12
-
-/** MCPWM_CAP_CH0_REG register
- *  CAP0 capture value register
- */
-#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP0
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH1_REG register
- *  CAP1 capture value register
- */
-#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100)
-/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP1
- */
-#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
-#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_S  0
-
-/** MCPWM_CAP_CH2_REG register
- *  CAP2 capture value register
- */
-#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104)
-/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP2
- */
-#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
-#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_S  0
-
-/** MCPWM_CAP_STATUS_REG register
- *  Last capture trigger edge information register
- */
-#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108)
-/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
- *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP0_EDGE    (BIT(0))
-#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
-#define MCPWM_CAP0_EDGE_V  0x00000001U
-#define MCPWM_CAP0_EDGE_S  0
-/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
- *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP1_EDGE    (BIT(1))
-#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
-#define MCPWM_CAP1_EDGE_V  0x00000001U
-#define MCPWM_CAP1_EDGE_S  1
-/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
- *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP2_EDGE    (BIT(2))
-#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
-#define MCPWM_CAP2_EDGE_V  0x00000001U
-#define MCPWM_CAP2_EDGE_S  2
-
-/** MCPWM_UPDATE_CFG_REG register
- *  Generator Update configuration register
- */
-#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c)
-/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
- *  Configures whether or not to enable global update for all active registers in MCPWM
- *  module.\\0: Disable\\1: Enable
- */
-#define MCPWM_GLOBAL_UP_EN    (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
-#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
-#define MCPWM_GLOBAL_UP_EN_S  0
-/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of global forced update for all active registers in MCPWM
- *  module. A toggle (software invert its value) will trigger a global forced update.
- *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
- */
-#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
-#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
-#define MCPWM_GLOBAL_FORCE_UP_S  1
-/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP0_UP_EN    (BIT(2))
-#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
-#define MCPWM_OP0_UP_EN_V  0x00000001U
-#define MCPWM_OP0_UP_EN_S  2
-/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator0. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
- */
-#define MCPWM_OP0_FORCE_UP    (BIT(3))
-#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
-#define MCPWM_OP0_FORCE_UP_V  0x00000001U
-#define MCPWM_OP0_FORCE_UP_S  3
-/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP1_UP_EN    (BIT(4))
-#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
-#define MCPWM_OP1_UP_EN_V  0x00000001U
-#define MCPWM_OP1_UP_EN_S  4
-/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator1. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
- */
-#define MCPWM_OP1_FORCE_UP    (BIT(5))
-#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
-#define MCPWM_OP1_FORCE_UP_V  0x00000001U
-#define MCPWM_OP1_FORCE_UP_S  5
-/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP2_UP_EN    (BIT(6))
-#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
-#define MCPWM_OP2_UP_EN_V  0x00000001U
-#define MCPWM_OP2_UP_EN_S  6
-/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator2. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
- */
-#define MCPWM_OP2_FORCE_UP    (BIT(7))
-#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
-#define MCPWM_OP2_FORCE_UP_V  0x00000001U
-#define MCPWM_OP2_FORCE_UP_S  7
-
-/** MCPWM_INT_ENA_REG register
- *  Interrupt enable register
- */
-#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110)
-/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
-#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ENA_S  0
-/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
-#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ENA_S  1
-/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
-#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ENA_S  2
-/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
-#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
-/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
-#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
-/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
-#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
-/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
-#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ENA_S  6
-/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
-#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ENA_S  7
-/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
-#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ENA_S  8
-/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ENA    (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
-#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_INT_ENA_S  9
-/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ENA    (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
-#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_INT_ENA_S  10
-/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ENA    (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
-#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_INT_ENA_S  11
-/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
-#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ENA_S  12
-/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
-#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ENA_S  13
-/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
-#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ENA_S  14
-/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
- */
-#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
-#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ENA_S  15
-/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
- */
-#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
-#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ENA_S  16
-/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
- */
-#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
-#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ENA_S  17
-/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
- */
-#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
-#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ENA_S  18
-/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
- */
-#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
-#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ENA_S  19
-/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
- */
-#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
-#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ENA_S  20
-/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
-#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ENA_S  21
-/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
-#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ENA_S  22
-/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
-#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ENA_S  23
-/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
-#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ENA_S  24
-/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
-#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ENA_S  25
-/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
-#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ENA_S  26
-/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
- */
-#define MCPWM_CAP0_INT_ENA    (BIT(27))
-#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
-#define MCPWM_CAP0_INT_ENA_V  0x00000001U
-#define MCPWM_CAP0_INT_ENA_S  27
-/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
- */
-#define MCPWM_CAP1_INT_ENA    (BIT(28))
-#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
-#define MCPWM_CAP1_INT_ENA_V  0x00000001U
-#define MCPWM_CAP1_INT_ENA_S  28
-/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
- */
-#define MCPWM_CAP2_INT_ENA    (BIT(29))
-#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
-#define MCPWM_CAP2_INT_ENA_V  0x00000001U
-#define MCPWM_CAP2_INT_ENA_S  29
-
-/** MCPWM_INT_RAW_REG register
- *  Interrupt raw status register
- */
-#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114)
-/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
-#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_RAW_S  0
-/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
-#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_RAW_S  1
-/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
-#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_RAW_S  2
-/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
-#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
-/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
-#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
-/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
-#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
-/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
-#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_RAW_S  6
-/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
-#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_RAW_S  7
-/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
-#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_RAW_S  8
-/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
- *  starts.
- */
-#define MCPWM_FAULT0_INT_RAW    (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
-#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_INT_RAW_S  9
-/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
- *  starts.
- */
-#define MCPWM_FAULT1_INT_RAW    (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
-#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_INT_RAW_S  10
-/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
- *  starts.
- */
-#define MCPWM_FAULT2_INT_RAW    (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
-#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_INT_RAW_S  11
-/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
- *  clears.
- */
-#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
-#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_RAW_S  12
-/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
- *  clears.
- */
-#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
-#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_RAW_S  13
-/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
- *  clears.
- */
-#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
-#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_RAW_S  14
-/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
-#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_RAW_S  15
-/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
-#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_RAW_S  16
-/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
-#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_RAW_S  17
-/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
-#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_RAW_S  18
-/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
-#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_RAW_S  19
-/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
-#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_RAW_S  20
-/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
-#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_RAW_S  21
-/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
-#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_RAW_S  22
-/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
-#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_RAW_S  23
-/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
-#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
-#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_RAW_S  24
-/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
-#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
-#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_RAW_S  25
-/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
-#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
-#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_RAW_S  26
-/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP0.
- */
-#define MCPWM_CAP0_INT_RAW    (BIT(27))
-#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
-#define MCPWM_CAP0_INT_RAW_V  0x00000001U
-#define MCPWM_CAP0_INT_RAW_S  27
-/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP1.
- */
-#define MCPWM_CAP1_INT_RAW    (BIT(28))
-#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
-#define MCPWM_CAP1_INT_RAW_V  0x00000001U
-#define MCPWM_CAP1_INT_RAW_S  28
-/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP2.
- */
-#define MCPWM_CAP2_INT_RAW    (BIT(29))
-#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
-#define MCPWM_CAP2_INT_RAW_V  0x00000001U
-#define MCPWM_CAP2_INT_RAW_S  29
-
-/** MCPWM_INT_ST_REG register
- *  Interrupt masked status register
- */
-#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118)
-/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
-#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ST_S  0
-/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
-#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ST_S  1
-/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
-#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ST_S  2
-/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
-#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ST_S  3
-/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
-#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ST_S  4
-/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
-#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ST_S  5
-/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
-#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ST_S  6
-/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
-#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ST_S  7
-/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
-#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ST_S  8
-/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ST    (BIT(9))
-#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
-#define MCPWM_FAULT0_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_INT_ST_S  9
-/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ST    (BIT(10))
-#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
-#define MCPWM_FAULT1_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_INT_ST_S  10
-/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ST    (BIT(11))
-#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
-#define MCPWM_FAULT2_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_INT_ST_S  11
-/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
-#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ST_S  12
-/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
-#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ST_S  13
-/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
-#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ST_S  14
-/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
-#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ST_S  15
-/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
-#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ST_S  16
-/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
-#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ST_S  17
-/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
-#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ST_S  18
-/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
-#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ST_S  19
-/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
-#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ST_S  20
-/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
-#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ST_S  21
-/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
-#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ST_S  22
-/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
-#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ST_S  23
-/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
-#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ST_S  24
-/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
-#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ST_S  25
-/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
-#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ST_S  26
-/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP0.
- */
-#define MCPWM_CAP0_INT_ST    (BIT(27))
-#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
-#define MCPWM_CAP0_INT_ST_V  0x00000001U
-#define MCPWM_CAP0_INT_ST_S  27
-/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP1.
- */
-#define MCPWM_CAP1_INT_ST    (BIT(28))
-#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
-#define MCPWM_CAP1_INT_ST_V  0x00000001U
-#define MCPWM_CAP1_INT_ST_S  28
-/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP2.
- */
-#define MCPWM_CAP2_INT_ST    (BIT(29))
-#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
-#define MCPWM_CAP2_INT_ST_V  0x00000001U
-#define MCPWM_CAP2_INT_ST_S  29
-
-/** MCPWM_INT_CLR_REG register
- *  Interrupt clear register
- */
-#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c)
-/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
-#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_CLR_S  0
-/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
-#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_CLR_S  1
-/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
-#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_CLR_S  2
-/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
-#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
-/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
-#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
-/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
-#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
-/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
-#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_CLR_S  6
-/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
-#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_CLR_S  7
-/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
-#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_CLR_S  8
-/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_CLR    (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
-#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_INT_CLR_S  9
-/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_CLR    (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
-#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_INT_CLR_S  10
-/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_CLR    (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
-#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_INT_CLR_S  11
-/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
-#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_CLR_S  12
-/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
-#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_CLR_S  13
-/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
-#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_CLR_S  14
-/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
-#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_CLR_S  15
-/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
-#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_CLR_S  16
-/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
-#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_CLR_S  17
-/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
-#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_CLR_S  18
-/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
-#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_CLR_S  19
-/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
-#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_CLR_S  20
-/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
-#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_CLR_S  21
-/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
-#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_CLR_S  22
-/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
-#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_CLR_S  23
-/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
-#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
-#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_CLR_S  24
-/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
-#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
-#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_CLR_S  25
-/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
-#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
-#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_CLR_S  26
-/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
- */
-#define MCPWM_CAP0_INT_CLR    (BIT(27))
-#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
-#define MCPWM_CAP0_INT_CLR_V  0x00000001U
-#define MCPWM_CAP0_INT_CLR_S  27
-/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
- */
-#define MCPWM_CAP1_INT_CLR    (BIT(28))
-#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
-#define MCPWM_CAP1_INT_CLR_V  0x00000001U
-#define MCPWM_CAP1_INT_CLR_S  28
-/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
- */
-#define MCPWM_CAP2_INT_CLR    (BIT(29))
-#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
-#define MCPWM_CAP2_INT_CLR_V  0x00000001U
-#define MCPWM_CAP2_INT_CLR_S  29
-
-/** MCPWM_EVT_EN_REG register
- *  Event enable register
- */
-#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120)
-/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
-#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
-#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_STOP_EN_S  0
-/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
-#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
-#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_STOP_EN_S  1
-/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
-#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
-#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_STOP_EN_S  2
-/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable timer0 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
-#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
-#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
-/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable timer1 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
-#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
-#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
-/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable timer2 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
-#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
-#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
-/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable timer0 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
-#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
-#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEP_EN_S  6
-/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable timer1 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
-#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
-#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEP_EN_S  7
-/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable timer2 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
-#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
-#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEP_EN_S  8
-/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
-#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
-#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEA_EN_S  9
-/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
-#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
-#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEA_EN_S  10
-/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
-#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
-#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEA_EN_S  11
-/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
-#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
-#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEB_EN_S  12
-/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
-#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
-#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEB_EN_S  13
-/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
-#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
-#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEB_EN_S  14
-/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F0_EN    (BIT(15))
-#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
-#define MCPWM_EVT_F0_EN_V  0x00000001U
-#define MCPWM_EVT_F0_EN_S  15
-/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F1_EN    (BIT(16))
-#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
-#define MCPWM_EVT_F1_EN_V  0x00000001U
-#define MCPWM_EVT_F1_EN_S  16
-/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F2_EN    (BIT(17))
-#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
-#define MCPWM_EVT_F2_EN_V  0x00000001U
-#define MCPWM_EVT_F2_EN_S  17
-/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
-#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
-#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F0_CLR_EN_S  18
-/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
-#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
-#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F1_CLR_EN_S  19
-/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
-#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
-#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F2_CLR_EN_S  20
-/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
-#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
-#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_CBC_EN_S  21
-/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
-#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
-#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_CBC_EN_S  22
-/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
-#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
-#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_CBC_EN_S  23
-/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
- *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
-#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
-#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_OST_EN_S  24
-/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
- *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
-#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
-#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_OST_EN_S  25
-/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
- *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
-#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
-#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_OST_EN_S  26
-/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
- *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP0_EN    (BIT(27))
-#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
-#define MCPWM_EVT_CAP0_EN_V  0x00000001U
-#define MCPWM_EVT_CAP0_EN_S  27
-/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP1_EN    (BIT(28))
-#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
-#define MCPWM_EVT_CAP1_EN_V  0x00000001U
-#define MCPWM_EVT_CAP1_EN_S  28
-/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP2_EN    (BIT(29))
-#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
-#define MCPWM_EVT_CAP2_EN_V  0x00000001U
-#define MCPWM_EVT_CAP2_EN_S  29
-
-/** MCPWM_TASK_EN_REG register
- *  Task enable register
- */
-#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124)
-/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
-#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
-#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
-/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
-#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
-#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
-/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
-#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
-#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
-/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
-#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
-#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
-/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
-#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
-#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
-/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
-#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
-#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
-/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable all PWM generate stop task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
-#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
-#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
-#define MCPWM_TASK_GEN_STOP_EN_S  6
-/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
-#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
-#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
-/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
-#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
-#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
-/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
-#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
-#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
-/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable timer0 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
-/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable timer1 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
-/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable timer2 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
-/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
-#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
-#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ0_OST_EN_S  13
-/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
- *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
-#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
-#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ1_OST_EN_S  14
-/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
-#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
-#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ2_OST_EN_S  15
-/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
-#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
-#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR0_OST_EN_S  16
-/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
-#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
-#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR1_OST_EN_S  17
-/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
-#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
-#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR2_OST_EN_S  18
-/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP0_EN    (BIT(19))
-#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
-#define MCPWM_TASK_CAP0_EN_V  0x00000001U
-#define MCPWM_TASK_CAP0_EN_S  19
-/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP1_EN    (BIT(20))
-#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
-#define MCPWM_TASK_CAP1_EN_V  0x00000001U
-#define MCPWM_TASK_CAP1_EN_S  20
-/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP2_EN    (BIT(21))
-#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
-#define MCPWM_TASK_CAP2_EN_V  0x00000001U
-#define MCPWM_TASK_CAP2_EN_S  21
-
-/** MCPWM_EVT_EN2_REG register
- *  Event enable register2
- */
-#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x128)
-/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEE1_EN    (BIT(0))
-#define MCPWM_EVT_OP0_TEE1_EN_M  (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S)
-#define MCPWM_EVT_OP0_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEE1_EN_S  0
-/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEE1_EN    (BIT(1))
-#define MCPWM_EVT_OP1_TEE1_EN_M  (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S)
-#define MCPWM_EVT_OP1_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEE1_EN_S  1
-/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEE1_EN    (BIT(2))
-#define MCPWM_EVT_OP2_TEE1_EN_M  (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S)
-#define MCPWM_EVT_OP2_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEE1_EN_S  2
-/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEE2_EN    (BIT(3))
-#define MCPWM_EVT_OP0_TEE2_EN_M  (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S)
-#define MCPWM_EVT_OP0_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEE2_EN_S  3
-/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEE2_EN    (BIT(4))
-#define MCPWM_EVT_OP1_TEE2_EN_M  (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S)
-#define MCPWM_EVT_OP1_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEE2_EN_S  4
-/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEE2_EN    (BIT(5))
-#define MCPWM_EVT_OP2_TEE2_EN_M  (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S)
-#define MCPWM_EVT_OP2_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEE2_EN_S  5
-
-/** MCPWM_OP0_TSTMP_E1_REG register
- *  Generator0 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x12c)
-/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator0 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
-#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_S  0
-
-/** MCPWM_OP0_TSTMP_E2_REG register
- *  Generator0 timer stamp E2 value register
- */
-#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x130)
-/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator0 timer stamp E2 value register
- */
-#define MCPWM_OP0_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E2_M  (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S)
-#define MCPWM_OP0_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E2_S  0
-
-/** MCPWM_OP1_TSTMP_E1_REG register
- *  Generator1 timer stamp E1 value register
- */
-#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x134)
-/** MCPWM_OP1_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator1 timer stamp E1 value register
- */
-#define MCPWM_OP1_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E1_M  (MCPWM_OP1_TSTMP_E1_V << MCPWM_OP1_TSTMP_E1_S)
-#define MCPWM_OP1_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E1_S  0
-
-/** MCPWM_OP1_TSTMP_E2_REG register
- *  Generator1 timer stamp E2 value register
- */
-#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x138)
-/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator1 timer stamp E2 value register
- */
-#define MCPWM_OP1_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E2_M  (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S)
-#define MCPWM_OP1_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E2_S  0
-
-/** MCPWM_OP2_TSTMP_E1_REG register
- *  Generator2 timer stamp E1 value register
- */
-#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x13c)
-/** MCPWM_OP2_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator2 timer stamp E1 value register
- */
-#define MCPWM_OP2_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E1_M  (MCPWM_OP2_TSTMP_E1_V << MCPWM_OP2_TSTMP_E1_S)
-#define MCPWM_OP2_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E1_S  0
-
-/** MCPWM_OP2_TSTMP_E2_REG register
- *  Generator2 timer stamp E2 value register
- */
-#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x140)
-/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator2 timer stamp E2 value register
- */
-#define MCPWM_OP2_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E2_M  (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S)
-#define MCPWM_OP2_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E2_S  0
-
-/** MCPWM_CLK_REG register
- *  Global configuration register
- */
-#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x144)
-/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
- *  when application writes registers\\1: Force open the clock gate for register
- */
-#define MCPWM_CLK_EN    (BIT(0))
-#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
-#define MCPWM_CLK_EN_V  0x00000001U
-#define MCPWM_CLK_EN_S  0
-
-/** MCPWM_VERSION_REG register
- *  Version register.
- */
-#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x148)
-/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968;
- *  Configures the version.
- */
-#define MCPWM_DATE    0x0FFFFFFFU
-#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
-#define MCPWM_DATE_V  0x0FFFFFFFU
-#define MCPWM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/mcpwm_struct.h b/components/soc/esp32c5/beta3/include/soc/mcpwm_struct.h
deleted file mode 100644
index dde07979a8..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/mcpwm_struct.h
+++ /dev/null
@@ -1,2031 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration register */
-/** Type of clk_cfg register
- *  PWM clock prescaler register.
- */
-typedef union {
-    struct {
-        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
-         *  (PWM_CLK_PRESCALE + 1).
-         */
-        uint32_t clk_prescale:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_clk_cfg_reg_t;
-
-/** Type of timern_cfg0 register
- *  PWM timern period and update method configuration register.
- */
-typedef union {
-    struct {
-        /** timern_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the prescaler value of timern, so that the period of PT0_clk = Period of
-         *  PWM_clk * (PWM_TIMERn_PRESCALE + 1)
-         */
-        uint32_t timern_prescale:8;
-        /** timern_period : R/W; bitpos: [23:8]; default: 255;
-         *  Configures the period shadow of PWM timern
-         */
-        uint32_t timern_period:16;
-        /** timern_period_upmethod : R/W; bitpos: [25:24]; default: 0;
-         *  Configures the update method for active register of PWM timern period.\\0:
-         *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
-         *  zero event
-         */
-        uint32_t timern_period_upmethod:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} mcpwm_timern_cfg0_reg_t;
-
-/** Type of timern_cfg1 register
- *  PWM timern working mode and start/stop control register.
- */
-typedef union {
-    struct {
-        /** timern_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  Configures whether or not to start/stop PWM timern.\\0: If PWM timern starts, then
-         *  stops at TEZ\\1: If timern starts, then stops at TEP\\2: PWM timern starts and runs
-         *  on\\3: Timern starts and stops at the next TEZ\\4: Timer0 starts and stops at the
-         *  next TEP.\\TEP here and below means the event that happens when the timer equals to
-         *  period
-         */
-        uint32_t timern_start:3;
-        /** timern_mod : R/W; bitpos: [4:3]; default: 0;
-         *  Configures the working mode of PWM timern.\\0: Freeze\\1: Increase mode\\2:
-         *  Decrease mode\\3: Up-down mode
-         */
-        uint32_t timern_mod:2;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_timern_cfg1_reg_t;
-
-/** Type of timern_sync register
- *  PWM timern sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timern_synci_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timern reloading with phase on sync input event
-         *  is enabled.\\0: Disable\\1: Enable
-         */
-        uint32_t timern_synci_en:1;
-        /** timern_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of software sync. Toggling this bit will trigger a
-         *  software sync.
-         */
-        uint32_t timern_sync_sw:1;
-        /** timern_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures the selection of PWM timern sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
-         *  Invalid, sync_out selects noting
-         */
-        uint32_t timern_synco_sel:2;
-        /** timern_phase : R/W; bitpos: [19:4]; default: 0;
-         *  Configures the phase for timern reload on sync event.
-         */
-        uint32_t timern_phase:16;
-        /** timern_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configures the PWM timern's direction when timern mode is up-down mode.\\0:
-         *  Increase\\1: Decrease
-         */
-        uint32_t timern_phase_direction:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} mcpwm_timern_sync_reg_t;
-
-/** Type of timern_status register
- *  PWM timern status register.
- */
-typedef union {
-    struct {
-        /** timern_value : RO; bitpos: [15:0]; default: 0;
-         *  Represents current PWM timern counter value.
-         */
-        uint32_t timern_value:16;
-        /** timern_direction : RO; bitpos: [16]; default: 0;
-         *  Represents current PWM timern counter direction.\\0: Increment\\1: Decrement
-         */
-        uint32_t timern_direction:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} mcpwm_timern_status_reg_t;
-
-/** Type of timer_synci_cfg register
- *  Synchronization input selection register for PWM timers.
- */
-typedef union {
-    struct {
-        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
-         *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer0_syncisel:3;
-        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
-         *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer1_syncisel:3;
-        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
-         *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer2_syncisel:3;
-        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci0_invert:1;
-        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci1_invert:1;
-        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci2_invert:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} mcpwm_timer_synci_cfg_reg_t;
-
-/** Type of operator_timersel register
- *  PWM operator's timer select register
- */
-typedef union {
-    struct {
-        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator0_timersel:2;
-        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator1_timersel:2;
-        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator2_timersel:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_operator_timersel_reg_t;
-
-
-/** Group: cfgrep */
-/** Type of genn_stmp_cfg register
- *  Generatorn time stamp registers A and B transfer status and update method register
- */
-typedef union {
-    struct {
-        /** genn_a_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the update method for PWM generator n time stamp A's active
-         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
-         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t genn_a_upmethod:4;
-        /** genn_b_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Configures the update method for PWM generator n time stamp B's active
-         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
-         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t genn_b_upmethod:4;
-        /** genn_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
-         *  Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0:
-         *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
-         *  reg is filled and waiting to be transferred to A's active reg
-         */
-        uint32_t genn_a_shdw_full:1;
-        /** genn_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
-         *  Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0:
-         *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
-         *  reg is filled and waiting to be transferred to B's active reg
-         */
-        uint32_t genn_b_shdw_full:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_genn_stmp_cfg_reg_t;
-
-/** Type of genn_tstmp_a register
- *  Generatorn time stamp A's shadow register
- */
-typedef union {
-    struct {
-        /** genn_a : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the value of PWM generator n time stamp A's shadow register.
-         */
-        uint32_t genn_a:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_genn_tstmp_a_reg_t;
-
-/** Type of genn_tstmp_b register
- *  Generatorn time stamp B's shadow register
- */
-typedef union {
-    struct {
-        /** genn_b : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the value of PWM generator n time stamp B's shadow register.
-         */
-        uint32_t genn_b:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_genn_tstmp_b_reg_t;
-
-/** Type of genn_cfg0 register
- *  Generatorn fault event T0 and T1 configuration register
- */
-typedef union {
-    struct {
-        /** genn_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures update method for PWM generator n's active register.\\0:
-         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t genn_cfg_upmethod:4;
-        /** genn_t0_sel : R/W; bitpos: [6:4]; default: 0;
-         *  Configures source selection for PWM generator n event_t0, take effect
-         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
-         *  Invalid, Select nothing
-         */
-        uint32_t genn_t0_sel:3;
-        /** genn_t1_sel : R/W; bitpos: [9:7]; default: 0;
-         *  Configures source selection for PWM generator n event_t1, take effect
-         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
-         *  Invalid, Select nothing
-         */
-        uint32_t genn_t1_sel:3;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_genn_cfg0_reg_t;
-
-/** Type of genn_force register
- *  Generatorn output signal force mode register.
- */
-typedef union {
-    struct {
-        /** genn_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
-         *  Configures update method for continuous software force of PWM generatorn.\\0:
-         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
-         *  update. TEA/B here and below means an event generated when the timer's value equals
-         *  to that of register A/B.
-         */
-        uint32_t genn_cntuforce_upmethod:6;
-        /** genn_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
-         *  Configures continuous software force mode for PWMn A.\\0: Disabled\\1: Low\\2:
-         *  High\\3: Disabled
-         */
-        uint32_t genn_a_cntuforce_mode:2;
-        /** genn_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
-         *  Configures continuous software force mode for PWMn B.\\0: Disabled\\1: Low\\2:
-         *  High\\3: Disabled
-         */
-        uint32_t genn_b_cntuforce_mode:2;
-        /** genn_a_nciforce : R/W; bitpos: [10]; default: 0;
-         *  Configures the generation of non-continuous immediate software-force event for PWMn
-         *  A, a toggle will trigger a force event.
-         */
-        uint32_t genn_a_nciforce:1;
-        /** genn_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
-         *  Configures non-continuous immediate software force mode for PWMn A.\\0:
-         *  Disabled\\1: Low\\2: High\\3: Disabled
-         */
-        uint32_t genn_a_nciforce_mode:2;
-        /** genn_b_nciforce : R/W; bitpos: [13]; default: 0;
-         *  Configures the generation of non-continuous immediate software-force event for PWMn
-         *  B, a toggle will trigger a force event.
-         */
-        uint32_t genn_b_nciforce:1;
-        /** genn_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
-         *  Configures non-continuous immediate software force mode for PWMn B.\\0:
-         *  Disabled\\1: Low\\2: High\\3: Disabled
-         */
-        uint32_t genn_b_nciforce_mode:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_genn_force_reg_t;
-
-/** Type of genn_a register
- *  PWMn output signal A actions configuration register
- */
-typedef union {
-    struct {
-        /** genn_a_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Configures action on PWMn A triggered by event TEZ when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_utez:2;
-        /** genn_a_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Configures action on PWMn A triggered by event TEP when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_utep:2;
-        /** genn_a_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Configures action on PWMn A triggered by event TEA when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_utea:2;
-        /** genn_a_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Configures action on PWMn A triggered by event TEB when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_uteb:2;
-        /** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Configures action on PWMn A triggered by event_t0 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_ut0:2;
-        /** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Configures action on PWMn A triggered by event_t1 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_ut1:2;
-        /** genn_a_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Configures action on PWMn A triggered by event TEZ when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_dtez:2;
-        /** genn_a_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Configures action on PWMn A triggered by event TEP when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_dtep:2;
-        /** genn_a_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Configures action on PWMn A triggered by event TEA when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_dtea:2;
-        /** genn_a_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Configures action on PWMn A triggered by event TEB when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_dteb:2;
-        /** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Configures action on PWMn A triggered by event_t0 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_dt0:2;
-        /** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Configures action on PWMn A triggered by event_t1 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_a_dt1:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_genn_a_reg_t;
-
-/** Type of genn_b register
- *  PWMn output signal B actions configuration register
- */
-typedef union {
-    struct {
-        /** genn_b_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Configures action on PWMn B triggered by event TEZ when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_utez:2;
-        /** genn_b_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Configures action on PWMn B triggered by event TEP when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_utep:2;
-        /** genn_b_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Configures action on PWMn B triggered by event TEA when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_utea:2;
-        /** genn_b_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Configures action on PWMn B triggered by event TEB when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_uteb:2;
-        /** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Configures action on PWMn B triggered by event_t0 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_ut0:2;
-        /** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Configures action on PWMn B triggered by event_t1 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_ut1:2;
-        /** genn_b_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Configures action on PWMn B triggered by event TEZ when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_dtez:2;
-        /** genn_b_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Configures action on PWMn B triggered by event TEP when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_dtep:2;
-        /** genn_b_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Configures action on PWMn B triggered by event TEA when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_dtea:2;
-        /** genn_b_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Configures action on PWMn B triggered by event TEB when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_dteb:2;
-        /** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Configures action on PWMn B triggered by event_t0 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_dt0:2;
-        /** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Configures action on PWMn B triggered by event_t1 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t genn_b_dt1:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_genn_b_reg_t;
-
-/** Type of dtn_cfg register
- *  Dead time configuration register
- */
-typedef union {
-    struct {
-        /** dtn_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures update method for FED (Falling edge delay) active register.\\0:
-         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t dtn_fed_upmethod:4;
-        /** dtn_red_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Configures update method for RED (rising edge delay) active register.\\0:
-         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t dtn_red_upmethod:4;
-        /** dtn_deb_mode : R/W; bitpos: [8]; default: 0;
-         *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
-         *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
-         */
-        uint32_t dtn_deb_mode:1;
-        /** dtn_a_outswap : R/W; bitpos: [9]; default: 0;
-         *  Configures S6 in table.
-         */
-        uint32_t dtn_a_outswap:1;
-        /** dtn_b_outswap : R/W; bitpos: [10]; default: 0;
-         *  Configures S7 in table.
-         */
-        uint32_t dtn_b_outswap:1;
-        /** dtn_red_insel : R/W; bitpos: [11]; default: 0;
-         *  Configures S4 in table.
-         */
-        uint32_t dtn_red_insel:1;
-        /** dtn_fed_insel : R/W; bitpos: [12]; default: 0;
-         *  Configures S5 in table.
-         */
-        uint32_t dtn_fed_insel:1;
-        /** dtn_red_outinvert : R/W; bitpos: [13]; default: 0;
-         *  Configures S2 in table.
-         */
-        uint32_t dtn_red_outinvert:1;
-        /** dtn_fed_outinvert : R/W; bitpos: [14]; default: 0;
-         *  Configures S3 in table.
-         */
-        uint32_t dtn_fed_outinvert:1;
-        /** dtn_a_outbypass : R/W; bitpos: [15]; default: 1;
-         *  Configures S1 in table.
-         */
-        uint32_t dtn_a_outbypass:1;
-        /** dtn_b_outbypass : R/W; bitpos: [16]; default: 1;
-         *  Configures S0 in table.
-         */
-        uint32_t dtn_b_outbypass:1;
-        /** dtn_clk_sel : R/W; bitpos: [17]; default: 0;
-         *  Configures dead time generator n clock selection.\\0: PWM_clk\\1: PT_clk
-         */
-        uint32_t dtn_clk_sel:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} mcpwm_dtn_cfg_reg_t;
-
-/** Type of dtn_fed_cfg register
- *  Falling edge delay (FED) shadow register
- */
-typedef union {
-    struct {
-        /** dtn_fed : R/W; bitpos: [15:0]; default: 0;
-         *  Configures shadow register for FED.
-         */
-        uint32_t dtn_fed:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dtn_fed_cfg_reg_t;
-
-/** Type of dtn_red_cfg register
- *  Rising edge delay (RED) shadow register
- */
-typedef union {
-    struct {
-        /** dtn_red : R/W; bitpos: [15:0]; default: 0;
-         *  Configures shadow register for RED.
-         */
-        uint32_t dtn_red:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dtn_red_cfg_reg_t;
-
-/** Type of carriern_cfg register
- *  Carriern configuration register
- */
-typedef union {
-    struct {
-        /** carriern_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable carriern.\\0: Bypassed\\1: Enabled
-         */
-        uint32_t carriern_en:1;
-        /** carriern_prescale : R/W; bitpos: [4:1]; default: 0;
-         *  Configures the prescale value of PWM carriern clock (PC_clk), so that period of
-         *  PC_clk = period of PWM_clk * (PWM_CARRIERn_PRESCALE + 1)
-         */
-        uint32_t carriern_prescale:4;
-        /** carriern_duty : R/W; bitpos: [7:5]; default: 0;
-         *  Configures carrier duty. Duty = PWM_CARRIERn_DUTY / 8
-         */
-        uint32_t carriern_duty:3;
-        /** carriern_oshtwth : R/W; bitpos: [11:8]; default: 0;
-         *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
-         */
-        uint32_t carriern_oshtwth:4;
-        /** carriern_out_invert : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to invert the output of PWMn A and PWMn B for this
-         *  submodule.\\0: Normal\\1: Invert
-         */
-        uint32_t carriern_out_invert:1;
-        /** carriern_in_invert : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to invert the input of PWMn A and PWMn B for this
-         *  submodule.\\0: Normal\\1: Invert
-         */
-        uint32_t carriern_in_invert:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} mcpwm_carriern_cfg_reg_t;
-
-/** Type of fhn_cfg0 register
- *  PWMn A and PWMn B trip events actions configuration register
- */
-typedef union {
-    struct {
-        /** fhn_sw_cbc : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_sw_cbc:1;
-        /** fhn_f2_cbc : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_f2_cbc:1;
-        /** fhn_f1_cbc : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_f1_cbc:1;
-        /** fhn_f0_cbc : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_f0_cbc:1;
-        /** fhn_sw_ost : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable software force one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_sw_ost:1;
-        /** fhn_f2_ost : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_f2_ost:1;
-        /** fhn_f1_ost : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_f1_ost:1;
-        /** fhn_f0_ost : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t fhn_f0_ost:1;
-        /** fhn_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer
-         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_a_cbc_d:2;
-        /** fhn_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWMn A when fault event occurs and timer
-         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_a_cbc_u:2;
-        /** fhn_a_ost_d : R/W; bitpos: [13:12]; default: 0;
-         *  Configures one-shot mode action on PWMn A when fault event occurs and timer is
-         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_a_ost_d:2;
-        /** fhn_a_ost_u : R/W; bitpos: [15:14]; default: 0;
-         *  Configures one-shot mode action on PWMn A when fault event occurs and timer is
-         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_a_ost_u:2;
-        /** fhn_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer
-         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_b_cbc_d:2;
-        /** fhn_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWMn B when fault event occurs and timer
-         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_b_cbc_u:2;
-        /** fhn_b_ost_d : R/W; bitpos: [21:20]; default: 0;
-         *  Configures one-shot mode action on PWMn B when fault event occurs and timer is
-         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_b_ost_d:2;
-        /** fhn_b_ost_u : R/W; bitpos: [23:22]; default: 0;
-         *  Configures one-shot mode action on PWMn B when fault event occurs and timer is
-         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t fhn_b_ost_u:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_fhn_cfg0_reg_t;
-
-/** Type of fhn_cfg1 register
- *  Software triggers for fault handler actions configuration register
- */
-typedef union {
-    struct {
-        /** fhn_clr_ost : R/W; bitpos: [0]; default: 0;
-         *  Configures the generation of software one-shot mode action clear. A toggle
-         *  (software negate its value) triggers a clear for on going one-shot mode action.
-         */
-        uint32_t fhn_clr_ost:1;
-        /** fhn_cbcpulse : R/W; bitpos: [2:1]; default: 0;
-         *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
-         *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
-         */
-        uint32_t fhn_cbcpulse:2;
-        /** fhn_force_cbc : R/W; bitpos: [3]; default: 0;
-         *  Configures the generation of software cycle-by-cycle mode action. A toggle
-         *  (software negate its value) triggers a cycle-by-cycle mode action.
-         */
-        uint32_t fhn_force_cbc:1;
-        /** fhn_force_ost : R/W; bitpos: [4]; default: 0;
-         *  Configures the generation of software one-shot mode action. A toggle (software
-         *  negate its value) triggers a one-shot mode action.
-         */
-        uint32_t fhn_force_ost:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_fhn_cfg1_reg_t;
-
-/** Type of fhn_status register
- *  Fault events status register
- */
-typedef union {
-    struct {
-        /** fhn_cbc_on : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
-         *  action\\1: On going
-         */
-        uint32_t fhn_cbc_on:1;
-        /** fhn_ost_on : RO; bitpos: [1]; default: 0;
-         *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
-         *  going
-         */
-        uint32_t fhn_ost_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mcpwm_fhn_status_reg_t;
-
-
-/** Group: fault det */
-/** Type of fault_detect register
- *  Fault detection configuration and status register
- */
-typedef union {
-    struct {
-        /** f0_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f0_en:1;
-        /** f1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f1_en:1;
-        /** f2_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f2_en:1;
-        /** f0_pole : R/W; bitpos: [3]; default: 0;
-         *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f0_pole:1;
-        /** f1_pole : R/W; bitpos: [4]; default: 0;
-         *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f1_pole:1;
-        /** f2_pole : R/W; bitpos: [5]; default: 0;
-         *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f2_pole:1;
-        /** event_f0 : RO; bitpos: [6]; default: 0;
-         *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f0:1;
-        /** event_f1 : RO; bitpos: [7]; default: 0;
-         *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f1:1;
-        /** event_f2 : RO; bitpos: [8]; default: 0;
-         *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f2:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} mcpwm_fault_detect_reg_t;
-
-
-/** Group: sync */
-/** Type of cap_timer_cfg register
- *  Capture timer configuration register
- */
-typedef union {
-    struct {
-        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
-         */
-        uint32_t cap_timer_en:1;
-        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
-         */
-        uint32_t cap_synci_en:1;
-        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
-         *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
-         *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
-         *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
-         */
-        uint32_t cap_synci_sel:3;
-        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
-         *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
-         *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
-         *  value in phase register
-         */
-        uint32_t cap_sync_sw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_cfg_reg_t;
-
-
-/** Group: phase */
-/** Type of cap_timer_phase register
- *  Capture timer sync phase register
- */
-typedef union {
-    struct {
-        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
-         *  Configures phase value for capture timer sync operation.
-         */
-        uint32_t cap_phase:32;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_phase_reg_t;
-
-
-/** Group: cap_cfg */
-/** Type of cap_chn_cfg register
- *  Capture channel n configuration register
- */
-typedef union {
-    struct {
-        /** capn_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable
-         */
-        uint32_t capn_en:1;
-        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
-         *  Configures which edge of capture on channel n after prescaling is used.\\0:
-         *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
-         *  Enable capture on the positive edge
-         */
-        uint32_t capn_mode:2;
-        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Configures prescale value on possitive edge of CAPn. Prescale value =
-         *  PWM_CAPn_PRESCALE + 1
-         */
-        uint32_t capn_prescale:8;
-        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0:
-         *  Normal\\1: Invert
-         */
-        uint32_t capn_in_invert:1;
-        /** capn_sw : WT; bitpos: [12]; default: 0;
-         *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
-         *  software forced capture on channel n
-         */
-        uint32_t capn_sw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_cfg_reg_t;
-
-
-/** Group: cap_ch */
-/** Type of cap_chn register
- *  CAPn capture value register
- */
-typedef union {
-    struct {
-        /** capn_value : RO; bitpos: [31:0]; default: 0;
-         *  Represents value of last capture on CAPn
-         */
-        uint32_t capn_value:32;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_reg_t;
-
-
-/** Group: edge */
-/** Type of cap_status register
- *  Last capture trigger edge information register
- */
-typedef union {
-    struct {
-        /** cap0_edge : RO; bitpos: [0]; default: 0;
-         *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap0_edge:1;
-        /** cap1_edge : RO; bitpos: [1]; default: 0;
-         *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap1_edge:1;
-        /** cap2_edge : RO; bitpos: [2]; default: 0;
-         *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap2_edge:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} mcpwm_cap_status_reg_t;
-
-
-/** Group: update */
-/** Type of update_cfg register
- *  Generator Update configuration register
- */
-typedef union {
-    struct {
-        /** global_up_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether or not to enable global update for all active registers in MCPWM
-         *  module.\\0: Disable\\1: Enable
-         */
-        uint32_t global_up_en:1;
-        /** global_force_up : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of global forced update for all active registers in MCPWM
-         *  module. A toggle (software invert its value) will trigger a global forced update.
-         *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
-         */
-        uint32_t global_force_up:1;
-        /** op0_up_en : R/W; bitpos: [2]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op0_up_en:1;
-        /** op0_force_up : R/W; bitpos: [3]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator0. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
-         */
-        uint32_t op0_force_up:1;
-        /** op1_up_en : R/W; bitpos: [4]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op1_up_en:1;
-        /** op1_force_up : R/W; bitpos: [5]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator1. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
-         */
-        uint32_t op1_force_up:1;
-        /** op2_up_en : R/W; bitpos: [6]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op2_up_en:1;
-        /** op2_force_up : R/W; bitpos: [7]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator2. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
-         */
-        uint32_t op2_force_up:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_update_cfg_reg_t;
-
-
-/** Group: Interrupt register */
-/** Type of int_ena register
- *  Interrupt enable register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_ena:1;
-        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_ena:1;
-        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_ena:1;
-        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_ena:1;
-        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_ena:1;
-        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_ena:1;
-        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_ena:1;
-        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_ena:1;
-        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_ena:1;
-        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_ena:1;
-        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_ena:1;
-        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_ena:1;
-        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
-         */
-        uint32_t fault0_clr_int_ena:1;
-        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
-         */
-        uint32_t fault1_clr_int_ena:1;
-        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
-         */
-        uint32_t fault2_clr_int_ena:1;
-        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
-         */
-        uint32_t cmpr0_tea_int_ena:1;
-        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
-         */
-        uint32_t cmpr1_tea_int_ena:1;
-        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
-         */
-        uint32_t cmpr2_tea_int_ena:1;
-        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
-         */
-        uint32_t cmpr0_teb_int_ena:1;
-        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
-         */
-        uint32_t cmpr1_teb_int_ena:1;
-        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
-         */
-        uint32_t cmpr2_teb_int_ena:1;
-        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM0.
-         */
-        uint32_t tz0_cbc_int_ena:1;
-        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM1.
-         */
-        uint32_t tz1_cbc_int_ena:1;
-        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM2.
-         */
-        uint32_t tz2_cbc_int_ena:1;
-        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_ost_int_ena:1;
-        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_ost_int_ena:1;
-        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_ost_int_ena:1;
-        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
-         */
-        uint32_t cap0_int_ena:1;
-        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
-         */
-        uint32_t cap1_int_ena:1;
-        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
-         */
-        uint32_t cap2_int_ena:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Interrupt raw status register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  0 stops.
-         */
-        uint32_t timer0_stop_int_raw:1;
-        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  1 stops.
-         */
-        uint32_t timer1_stop_int_raw:1;
-        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  2 stops.
-         */
-        uint32_t timer2_stop_int_raw:1;
-        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  0 TEZ event.
-         */
-        uint32_t timer0_tez_int_raw:1;
-        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  1 TEZ event.
-         */
-        uint32_t timer1_tez_int_raw:1;
-        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  2 TEZ event.
-         */
-        uint32_t timer2_tez_int_raw:1;
-        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  0 TEP event.
-         */
-        uint32_t timer0_tep_int_raw:1;
-        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  1 TEP event.
-         */
-        uint32_t timer1_tep_int_raw:1;
-        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  2 TEP event.
-         */
-        uint32_t timer2_tep_int_raw:1;
-        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
-         *  starts.
-         */
-        uint32_t fault0_int_raw:1;
-        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
-         *  starts.
-         */
-        uint32_t fault1_int_raw:1;
-        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
-         *  starts.
-         */
-        uint32_t fault2_int_raw:1;
-        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
-         *  clears.
-         */
-        uint32_t fault0_clr_int_raw:1;
-        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
-         *  clears.
-         */
-        uint32_t fault1_clr_int_raw:1;
-        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
-         *  clears.
-         */
-        uint32_t fault2_clr_int_raw:1;
-        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_raw:1;
-        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_raw:1;
-        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_raw:1;
-        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_raw:1;
-        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_raw:1;
-        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_raw:1;
-        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_raw:1;
-        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_raw:1;
-        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_raw:1;
-        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_raw:1;
-        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_raw:1;
-        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_raw:1;
-        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP0.
-         */
-        uint32_t cap0_int_raw:1;
-        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP1.
-         */
-        uint32_t cap1_int_raw:1;
-        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP2.
-         */
-        uint32_t cap2_int_raw:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_raw_reg_t;
-
-/** Type of int_st register
- *  Interrupt masked status register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 0 stops.
-         */
-        uint32_t timer0_stop_int_st:1;
-        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 1 stops.
-         */
-        uint32_t timer1_stop_int_st:1;
-        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 2 stops.
-         */
-        uint32_t timer2_stop_int_st:1;
-        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_st:1;
-        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_st:1;
-        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_st:1;
-        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_st:1;
-        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_st:1;
-        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_st:1;
-        /** fault0_int_st : RO; bitpos: [9]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f0 starts.
-         */
-        uint32_t fault0_int_st:1;
-        /** fault1_int_st : RO; bitpos: [10]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f1 starts.
-         */
-        uint32_t fault1_int_st:1;
-        /** fault2_int_st : RO; bitpos: [11]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f2 starts.
-         */
-        uint32_t fault2_int_st:1;
-        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f0 clears.
-         */
-        uint32_t fault0_clr_int_st:1;
-        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f1 clears.
-         */
-        uint32_t fault1_clr_int_st:1;
-        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f2 clears.
-         */
-        uint32_t fault2_clr_int_st:1;
-        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_st:1;
-        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_st:1;
-        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_st:1;
-        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_st:1;
-        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_st:1;
-        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_st:1;
-        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_st:1;
-        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_st:1;
-        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_st:1;
-        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_st:1;
-        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_st:1;
-        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_st:1;
-        /** cap0_int_st : RO; bitpos: [27]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP0.
-         */
-        uint32_t cap0_int_st:1;
-        /** cap1_int_st : RO; bitpos: [28]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP1.
-         */
-        uint32_t cap1_int_st:1;
-        /** cap2_int_st : RO; bitpos: [29]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP2.
-         */
-        uint32_t cap2_int_st:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_st_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_clr:1;
-        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_clr:1;
-        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_clr:1;
-        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_clr:1;
-        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_clr:1;
-        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_clr:1;
-        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_clr:1;
-        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_clr:1;
-        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_clr:1;
-        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_clr:1;
-        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_clr:1;
-        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_clr:1;
-        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
-         */
-        uint32_t fault0_clr_int_clr:1;
-        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
-         */
-        uint32_t fault1_clr_int_clr:1;
-        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
-         */
-        uint32_t fault2_clr_int_clr:1;
-        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_clr:1;
-        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_clr:1;
-        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_clr:1;
-        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_clr:1;
-        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_clr:1;
-        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_clr:1;
-        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM0.
-         */
-        uint32_t tz0_cbc_int_clr:1;
-        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM1.
-         */
-        uint32_t tz1_cbc_int_clr:1;
-        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM2.
-         */
-        uint32_t tz2_cbc_int_clr:1;
-        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_ost_int_clr:1;
-        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_ost_int_clr:1;
-        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_ost_int_clr:1;
-        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
-         */
-        uint32_t cap0_int_clr:1;
-        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
-         */
-        uint32_t cap1_int_clr:1;
-        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
-         */
-        uint32_t cap2_int_clr:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_clr_reg_t;
-
-
-/** Group: etm */
-/** Type of evt_en register
- *  Event enable register
- */
-typedef union {
-    struct {
-        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer0_stop_en:1;
-        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer1_stop_en:1;
-        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer2_stop_en:1;
-        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable timer0 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer0_tez_en:1;
-        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable timer1 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer1_tez_en:1;
-        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable timer2 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer2_tez_en:1;
-        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable timer0 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer0_tep_en:1;
-        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable timer1 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer1_tep_en:1;
-        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable timer2 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer2_tep_en:1;
-        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tea_en:1;
-        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tea_en:1;
-        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tea_en:1;
-        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_teb_en:1;
-        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_teb_en:1;
-        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_teb_en:1;
-        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f0_en:1;
-        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f1_en:1;
-        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f2_en:1;
-        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f0_clr_en:1;
-        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f1_clr_en:1;
-        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f2_clr_en:1;
-        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz0_cbc_en:1;
-        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz1_cbc_en:1;
-        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz2_cbc_en:1;
-        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz0_ost_en:1;
-        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
-         *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz1_ost_en:1;
-        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
-         *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz2_ost_en:1;
-        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap0_en:1;
-        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap1_en:1;
-        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap2_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_evt_en_reg_t;
-
-/** Type of task_en register
- *  Task enable register
- */
-typedef union {
-    struct {
-        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr0_a_up_en:1;
-        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr1_a_up_en:1;
-        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr2_a_up_en:1;
-        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr0_b_up_en:1;
-        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr1_b_up_en:1;
-        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr2_b_up_en:1;
-        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable all PWM generate stop task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_gen_stop_en:1;
-        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer0_sync_en:1;
-        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer1_sync_en:1;
-        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer2_sync_en:1;
-        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable timer0 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer0_period_up_en:1;
-        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable timer1 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer1_period_up_en:1;
-        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable timer2 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer2_period_up_en:1;
-        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz0_ost_en:1;
-        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz1_ost_en:1;
-        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz2_ost_en:1;
-        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr0_ost_en:1;
-        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr1_ost_en:1;
-        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr2_ost_en:1;
-        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap0_en:1;
-        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap1_en:1;
-        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap2_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} mcpwm_task_en_reg_t;
-
-/** Type of evt_en2 register
- *  Event enable register2
- */
-typedef union {
-    struct {
-        /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tee1_en:1;
-        /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tee1_en:1;
-        /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tee1_en:1;
-        /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tee2_en:1;
-        /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tee2_en:1;
-        /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tee2_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_evt_en2_reg_t;
-
-
-/** Group: tstmp */
-/** Type of opn_tstmp_e1 register
- *  Generatorn timer stamp E1 value register
- */
-typedef union {
-    struct {
-        /** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures generatorn timer stamp E1 value register
-         */
-        uint32_t opn_tstmp_e1:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_opn_tstmp_e1_reg_t;
-
-/** Type of opn_tstmp_e2 register
- *  Generatorn timer stamp E2 value register
- */
-typedef union {
-    struct {
-        /** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures generatorn timer stamp E2 value register
-         */
-        uint32_t opn_tstmp_e2:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_opn_tstmp_e2_reg_t;
-
-/** Type of clk register
- *  Global configuration register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
-         *  when application writes registers\\1: Force open the clock gate for register
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mcpwm_clk_reg_t;
-
-
-/** Group: Version register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725968;
-         *  Configures the version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mcpwm_version_reg_t;
-
-
-typedef struct mcpwm_dev_t {
-    volatile mcpwm_clk_cfg_reg_t clk_cfg;
-    volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
-    volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;
-    volatile mcpwm_timern_sync_reg_t timer0_sync;
-    volatile mcpwm_timern_status_reg_t timer0_status;
-    volatile mcpwm_timern_cfg0_reg_t timer1_cfg0;
-    volatile mcpwm_timern_cfg1_reg_t timer1_cfg1;
-    volatile mcpwm_timern_sync_reg_t timer1_sync;
-    volatile mcpwm_timern_status_reg_t timer1_status;
-    volatile mcpwm_timern_cfg0_reg_t timer2_cfg0;
-    volatile mcpwm_timern_cfg1_reg_t timer2_cfg1;
-    volatile mcpwm_timern_sync_reg_t timer2_sync;
-    volatile mcpwm_timern_status_reg_t timer2_status;
-    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
-    volatile mcpwm_operator_timersel_reg_t operator_timersel;
-    volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg;
-    volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a;
-    volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b;
-    volatile mcpwm_genn_cfg0_reg_t gen0_cfg0;
-    volatile mcpwm_genn_force_reg_t gen0_force;
-    volatile mcpwm_genn_a_reg_t gen0_a;
-    volatile mcpwm_genn_b_reg_t gen0_b;
-    volatile mcpwm_dtn_cfg_reg_t dt0_cfg;
-    volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg;
-    volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg;
-    volatile mcpwm_carriern_cfg_reg_t carrier0_cfg;
-    volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0;
-    volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1;
-    volatile mcpwm_fhn_status_reg_t fh0_status;
-    volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg;
-    volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a;
-    volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b;
-    volatile mcpwm_genn_cfg0_reg_t gen1_cfg0;
-    volatile mcpwm_genn_force_reg_t gen1_force;
-    volatile mcpwm_genn_a_reg_t gen1_a;
-    volatile mcpwm_genn_b_reg_t gen1_b;
-    volatile mcpwm_dtn_cfg_reg_t dt1_cfg;
-    volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg;
-    volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg;
-    volatile mcpwm_carriern_cfg_reg_t carrier1_cfg;
-    volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0;
-    volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1;
-    volatile mcpwm_fhn_status_reg_t fh1_status;
-    volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg;
-    volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a;
-    volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b;
-    volatile mcpwm_genn_cfg0_reg_t gen2_cfg0;
-    volatile mcpwm_genn_force_reg_t gen2_force;
-    volatile mcpwm_genn_a_reg_t gen2_a;
-    volatile mcpwm_genn_b_reg_t gen2_b;
-    volatile mcpwm_dtn_cfg_reg_t dt2_cfg;
-    volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg;
-    volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg;
-    volatile mcpwm_carriern_cfg_reg_t carrier2_cfg;
-    volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0;
-    volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1;
-    volatile mcpwm_fhn_status_reg_t fh2_status;
-    volatile mcpwm_fault_detect_reg_t fault_detect;
-    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
-    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
-    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
-    volatile mcpwm_cap_chn_reg_t cap_chn[3];
-    volatile mcpwm_cap_status_reg_t cap_status;
-    volatile mcpwm_update_cfg_reg_t update_cfg;
-    volatile mcpwm_int_ena_reg_t int_ena;
-    volatile mcpwm_int_raw_reg_t int_raw;
-    volatile mcpwm_int_st_reg_t int_st;
-    volatile mcpwm_int_clr_reg_t int_clr;
-    volatile mcpwm_evt_en_reg_t evt_en;
-    volatile mcpwm_task_en_reg_t task_en;
-    volatile mcpwm_evt_en2_reg_t evt_en2;
-    volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1;
-    volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2;
-    volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1;
-    volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2;
-    volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1;
-    volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2;
-    volatile mcpwm_clk_reg_t clk;
-    volatile mcpwm_version_reg_t version;
-} mcpwm_dev_t;
-
-extern mcpwm_dev_t MCPWM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/mem_monitor_reg.h b/components/soc/esp32c5/beta3/include/soc/mem_monitor_reg.h
deleted file mode 100644
index acda025df2..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/mem_monitor_reg.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MEM_MONITOR_LOG_SETTING_REG register
- *  log config regsiter
- */
-#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
-/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
- *  enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA
- */
-#define MEM_MONITOR_LOG_ENA    0x00000007U
-#define MEM_MONITOR_LOG_ENA_M  (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
-#define MEM_MONITOR_LOG_ENA_V  0x00000007U
-#define MEM_MONITOR_LOG_ENA_S  0
-/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
- *  Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE
- *  monitor
- */
-#define MEM_MONITOR_LOG_MODE    0x0000000FU
-#define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
-#define MEM_MONITOR_LOG_MODE_V  0x0000000FU
-#define MEM_MONITOR_LOG_MODE_S  3
-/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
- *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
- */
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(7))
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
-
-/** MEM_MONITOR_LOG_CHECK_DATA_REG register
- *  check data regsiter
- */
-#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
-/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The special check data, when write this special data, it will trigger logging.
- */
-#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
-#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_CHECK_DATA_S  0
-
-/** MEM_MONITOR_LOG_DATA_MASK_REG register
- *  check data mask register
- */
-#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
-/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
- *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
- *  mask second byte, and so on.
- */
-#define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
-#define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
-#define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
-#define MEM_MONITOR_LOG_DATA_MASK_S  0
-
-/** MEM_MONITOR_LOG_MIN_REG register
- *  log boundary regsiter
- */
-#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
-/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
- *  the min address of log range
- */
-#define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
-#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MIN_S  0
-
-/** MEM_MONITOR_LOG_MAX_REG register
- *  log boundary regsiter
- */
-#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
-/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
- *  the max address of log range
- */
-#define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
-#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MAX_S  0
-
-/** MEM_MONITOR_LOG_MEM_START_REG register
- *  log message store range register
- */
-#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
-/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
- *  the start address of writing logging message
- */
-#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
-#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_START_S  0
-
-/** MEM_MONITOR_LOG_MEM_END_REG register
- *  log message store range register
- */
-#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
-/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
- *  the end address of writing logging message
- */
-#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
-#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_END_S  0
-
-/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
- *  current writing address.
- */
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
-/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  means next writing address
- */
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
-
-/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
- *  writing address update
- */
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
-/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
- *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
- *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
- */
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
-
-/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
- *  full flag status register
- */
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
-/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
- *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
- */
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
-/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
- *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
- */
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
-
-/** MEM_MONITOR_CLOCK_GATE_REG register
- *  clock gate force on register
- */
-#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
-/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to force on the clk of mem_monitor register
- */
-#define MEM_MONITOR_CLK_EN    (BIT(0))
-#define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
-#define MEM_MONITOR_CLK_EN_V  0x00000001U
-#define MEM_MONITOR_CLK_EN_S  0
-
-/** MEM_MONITOR_DATE_REG register
- *  version register
- */
-#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
-/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34632336;
- *  version register
- */
-#define MEM_MONITOR_DATE    0x0FFFFFFFU
-#define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
-#define MEM_MONITOR_DATE_V  0x0FFFFFFFU
-#define MEM_MONITOR_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/beta3/include/soc/mem_monitor_struct.h
deleted file mode 100644
index 51f731b5ec..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/mem_monitor_struct.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configuration registers */
-/** Type of log_setting register
- *  log config regsiter
- */
-typedef union {
-    struct {
-        /** log_ena : R/W; bitpos: [2:0]; default: 0;
-         *  enable bus log, BIT0: hp cpu, BIT1: lp cpu, BIT2: DMA
-         */
-        uint32_t log_ena:3;
-        /** log_mode : R/W; bitpos: [6:3]; default: 0;
-         *  Bit[0] : WR monitor; BIT[1]: WORD monitor; BIT[2]: HALFWORD monitor; BIT[3]: BYTE
-         *  monitor
-         */
-        uint32_t log_mode:4;
-        /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
-         *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
-         */
-        uint32_t log_mem_loop_enable:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mem_monitor_log_setting_reg_t;
-
-/** Type of log_check_data register
- *  check data regsiter
- */
-typedef union {
-    struct {
-        /** log_check_data : R/W; bitpos: [31:0]; default: 0;
-         *  The special check data, when write this special data, it will trigger logging.
-         */
-        uint32_t log_check_data:32;
-    };
-    uint32_t val;
-} mem_monitor_log_check_data_reg_t;
-
-/** Type of log_data_mask register
- *  check data mask register
- */
-typedef union {
-    struct {
-        /** log_data_mask : R/W; bitpos: [3:0]; default: 0;
-         *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
-         *  mask second byte, and so on.
-         */
-        uint32_t log_data_mask:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} mem_monitor_log_data_mask_reg_t;
-
-/** Type of log_min register
- *  log boundary regsiter
- */
-typedef union {
-    struct {
-        /** log_min : R/W; bitpos: [31:0]; default: 0;
-         *  the min address of log range
-         */
-        uint32_t log_min:32;
-    };
-    uint32_t val;
-} mem_monitor_log_min_reg_t;
-
-/** Type of log_max register
- *  log boundary regsiter
- */
-typedef union {
-    struct {
-        /** log_max : R/W; bitpos: [31:0]; default: 0;
-         *  the max address of log range
-         */
-        uint32_t log_max:32;
-    };
-    uint32_t val;
-} mem_monitor_log_max_reg_t;
-
-/** Type of log_mem_start register
- *  log message store range register
- */
-typedef union {
-    struct {
-        /** log_mem_start : R/W; bitpos: [31:0]; default: 0;
-         *  the start address of writing logging message
-         */
-        uint32_t log_mem_start:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_start_reg_t;
-
-/** Type of log_mem_end register
- *  log message store range register
- */
-typedef union {
-    struct {
-        /** log_mem_end : R/W; bitpos: [31:0]; default: 0;
-         *  the end address of writing logging message
-         */
-        uint32_t log_mem_end:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_end_reg_t;
-
-/** Type of log_mem_current_addr register
- *  current writing address.
- */
-typedef union {
-    struct {
-        /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
-         *  means next writing address
-         */
-        uint32_t log_mem_current_addr:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_current_addr_reg_t;
-
-/** Type of log_mem_addr_update register
- *  writing address update
- */
-typedef union {
-    struct {
-        /** log_mem_addr_update : WT; bitpos: [0]; default: 0;
-         *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
-         *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
-         */
-        uint32_t log_mem_addr_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_addr_update_reg_t;
-
-/** Type of log_mem_full_flag register
- *  full flag status register
- */
-typedef union {
-    struct {
-        /** log_mem_full_flag : RO; bitpos: [0]; default: 0;
-         *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
-         */
-        uint32_t log_mem_full_flag:1;
-        /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
-         *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
-         */
-        uint32_t clr_log_mem_full_flag:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_full_flag_reg_t;
-
-
-/** Group: clk register */
-/** Type of clock_gate register
- *  clock gate force on register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to force on the clk of mem_monitor register
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mem_monitor_clock_gate_reg_t;
-
-
-/** Group: version register */
-/** Type of date register
- *  version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 34632336;
-         *  version register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mem_monitor_date_reg_t;
-
-
-typedef struct mem_monitor_dev_t {
-    volatile mem_monitor_log_setting_reg_t log_setting;
-    volatile mem_monitor_log_check_data_reg_t log_check_data;
-    volatile mem_monitor_log_data_mask_reg_t log_data_mask;
-    volatile mem_monitor_log_min_reg_t log_min;
-    volatile mem_monitor_log_max_reg_t log_max;
-    volatile mem_monitor_log_mem_start_reg_t log_mem_start;
-    volatile mem_monitor_log_mem_end_reg_t log_mem_end;
-    volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
-    volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
-    volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
-    volatile mem_monitor_clock_gate_reg_t clock_gate;
-    uint32_t reserved_02c[244];
-    volatile mem_monitor_date_reg_t date;
-} mem_monitor_dev_t;
-
-extern mem_monitor_dev_t MEM_MONITOR;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/otp_debug_reg.h b/components/soc/esp32c5/beta3/include/soc/otp_debug_reg.h
deleted file mode 100644
index 7dfe5342f8..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/otp_debug_reg.h
+++ /dev/null
@@ -1,1600 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** OTP_DEBUG_WR_DIS_REG register
- *  Otp debuger block0 data register1.
- */
-#define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0)
-/** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 write disable data.
- */
-#define OTP_DEBUG_BLOCK0_WR_DIS    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_WR_DIS_M  (OTP_DEBUG_BLOCK0_WR_DIS_V << OTP_DEBUG_BLOCK0_WR_DIS_S)
-#define OTP_DEBUG_BLOCK0_WR_DIS_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_WR_DIS_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W1_REG register
- *  Otp debuger block0 data register2.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1_M  (OTP_DEBUG_BLOCK0_BACKUP1_W1_V << OTP_DEBUG_BLOCK0_BACKUP1_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W2_REG register
- *  Otp debuger block0 data register3.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2_M  (OTP_DEBUG_BLOCK0_BACKUP1_W2_V << OTP_DEBUG_BLOCK0_BACKUP1_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W3_REG register
- *  Otp debuger block0 data register4.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3_M  (OTP_DEBUG_BLOCK0_BACKUP1_W3_V << OTP_DEBUG_BLOCK0_BACKUP1_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W4_REG register
- *  Otp debuger block0 data register5.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4_M  (OTP_DEBUG_BLOCK0_BACKUP1_W4_V << OTP_DEBUG_BLOCK0_BACKUP1_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP1_W5_REG register
- *  Otp debuger block0 data register6.
- */
-#define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14)
-/** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5_M  (OTP_DEBUG_BLOCK0_BACKUP1_W5_V << OTP_DEBUG_BLOCK0_BACKUP1_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP1_W5_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W1_REG register
- *  Otp debuger block0 data register7.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1_M  (OTP_DEBUG_BLOCK0_BACKUP2_W1_V << OTP_DEBUG_BLOCK0_BACKUP2_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W2_REG register
- *  Otp debuger block0 data register8.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2_M  (OTP_DEBUG_BLOCK0_BACKUP2_W2_V << OTP_DEBUG_BLOCK0_BACKUP2_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W3_REG register
- *  Otp debuger block0 data register9.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3_M  (OTP_DEBUG_BLOCK0_BACKUP2_W3_V << OTP_DEBUG_BLOCK0_BACKUP2_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W4_REG register
- *  Otp debuger block0 data register10.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4_M  (OTP_DEBUG_BLOCK0_BACKUP2_W4_V << OTP_DEBUG_BLOCK0_BACKUP2_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP2_W5_REG register
- *  Otp debuger block0 data register11.
- */
-#define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28)
-/** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5_M  (OTP_DEBUG_BLOCK0_BACKUP2_W5_V << OTP_DEBUG_BLOCK0_BACKUP2_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP2_W5_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W1_REG register
- *  Otp debuger block0 data register12.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1_M  (OTP_DEBUG_BLOCK0_BACKUP3_W1_V << OTP_DEBUG_BLOCK0_BACKUP3_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W2_REG register
- *  Otp debuger block0 data register13.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2_M  (OTP_DEBUG_BLOCK0_BACKUP3_W2_V << OTP_DEBUG_BLOCK0_BACKUP3_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W3_REG register
- *  Otp debuger block0 data register14.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3_M  (OTP_DEBUG_BLOCK0_BACKUP3_W3_V << OTP_DEBUG_BLOCK0_BACKUP3_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W4_REG register
- *  Otp debuger block0 data register15.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4_M  (OTP_DEBUG_BLOCK0_BACKUP3_W4_V << OTP_DEBUG_BLOCK0_BACKUP3_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP3_W5_REG register
- *  Otp debuger block0 data register16.
- */
-#define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c)
-/** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5_M  (OTP_DEBUG_BLOCK0_BACKUP3_W5_V << OTP_DEBUG_BLOCK0_BACKUP3_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP3_W5_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W1_REG register
- *  Otp debuger block0 data register17.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word1 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1_M  (OTP_DEBUG_BLOCK0_BACKUP4_W1_V << OTP_DEBUG_BLOCK0_BACKUP4_W1_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W1_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W2_REG register
- *  Otp debuger block0 data register18.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word2 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2_M  (OTP_DEBUG_BLOCK0_BACKUP4_W2_V << OTP_DEBUG_BLOCK0_BACKUP4_W2_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W2_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W3_REG register
- *  Otp debuger block0 data register19.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word3 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3_M  (OTP_DEBUG_BLOCK0_BACKUP4_W3_V << OTP_DEBUG_BLOCK0_BACKUP4_W3_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W3_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W4_REG register
- *  Otp debuger block0 data register20.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word4 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4_M  (OTP_DEBUG_BLOCK0_BACKUP4_W4_V << OTP_DEBUG_BLOCK0_BACKUP4_W4_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W4_S  0
-
-/** OTP_DEBUG_BLK0_BACKUP4_W5_REG register
- *  Otp debuger block0 data register21.
- */
-#define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50)
-/** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word5 data.
- */
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5_M  (OTP_DEBUG_BLOCK0_BACKUP4_W5_V << OTP_DEBUG_BLOCK0_BACKUP4_W5_S)
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK0_BACKUP4_W5_S  0
-
-/** OTP_DEBUG_BLK1_W1_REG register
- *  Otp debuger block1 data register1.
- */
-#define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54)
-/** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word1 data.
- */
-#define OTP_DEBUG_BLOCK1_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W1_M  (OTP_DEBUG_BLOCK1_W1_V << OTP_DEBUG_BLOCK1_W1_S)
-#define OTP_DEBUG_BLOCK1_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W1_S  0
-
-/** OTP_DEBUG_BLK1_W2_REG register
- *  Otp debuger block1 data register2.
- */
-#define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58)
-/** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word2 data.
- */
-#define OTP_DEBUG_BLOCK1_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W2_M  (OTP_DEBUG_BLOCK1_W2_V << OTP_DEBUG_BLOCK1_W2_S)
-#define OTP_DEBUG_BLOCK1_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W2_S  0
-
-/** OTP_DEBUG_BLK1_W3_REG register
- *  Otp debuger block1 data register3.
- */
-#define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c)
-/** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word3 data.
- */
-#define OTP_DEBUG_BLOCK1_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W3_M  (OTP_DEBUG_BLOCK1_W3_V << OTP_DEBUG_BLOCK1_W3_S)
-#define OTP_DEBUG_BLOCK1_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W3_S  0
-
-/** OTP_DEBUG_BLK1_W4_REG register
- *  Otp debuger block1 data register4.
- */
-#define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60)
-/** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word4 data.
- */
-#define OTP_DEBUG_BLOCK1_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W4_M  (OTP_DEBUG_BLOCK1_W4_V << OTP_DEBUG_BLOCK1_W4_S)
-#define OTP_DEBUG_BLOCK1_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W4_S  0
-
-/** OTP_DEBUG_BLK1_W5_REG register
- *  Otp debuger block1 data register5.
- */
-#define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64)
-/** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word5 data.
- */
-#define OTP_DEBUG_BLOCK1_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W5_M  (OTP_DEBUG_BLOCK1_W5_V << OTP_DEBUG_BLOCK1_W5_S)
-#define OTP_DEBUG_BLOCK1_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W5_S  0
-
-/** OTP_DEBUG_BLK1_W6_REG register
- *  Otp debuger block1 data register6.
- */
-#define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68)
-/** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word6 data.
- */
-#define OTP_DEBUG_BLOCK1_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W6_M  (OTP_DEBUG_BLOCK1_W6_V << OTP_DEBUG_BLOCK1_W6_S)
-#define OTP_DEBUG_BLOCK1_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W6_S  0
-
-/** OTP_DEBUG_BLK1_W7_REG register
- *  Otp debuger block1 data register7.
- */
-#define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c)
-/** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word7 data.
- */
-#define OTP_DEBUG_BLOCK1_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W7_M  (OTP_DEBUG_BLOCK1_W7_V << OTP_DEBUG_BLOCK1_W7_S)
-#define OTP_DEBUG_BLOCK1_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W7_S  0
-
-/** OTP_DEBUG_BLK1_W8_REG register
- *  Otp debuger block1 data register8.
- */
-#define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70)
-/** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word8 data.
- */
-#define OTP_DEBUG_BLOCK1_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W8_M  (OTP_DEBUG_BLOCK1_W8_V << OTP_DEBUG_BLOCK1_W8_S)
-#define OTP_DEBUG_BLOCK1_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W8_S  0
-
-/** OTP_DEBUG_BLK1_W9_REG register
- *  Otp debuger block1 data register9.
- */
-#define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74)
-/** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word9 data.
- */
-#define OTP_DEBUG_BLOCK1_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W9_M  (OTP_DEBUG_BLOCK1_W9_V << OTP_DEBUG_BLOCK1_W9_S)
-#define OTP_DEBUG_BLOCK1_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK1_W9_S  0
-
-/** OTP_DEBUG_BLK2_W1_REG register
- *  Otp debuger block2 data register1.
- */
-#define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78)
-/** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word1 data.
- */
-#define OTP_DEBUG_BLOCK2_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W1_M  (OTP_DEBUG_BLOCK2_W1_V << OTP_DEBUG_BLOCK2_W1_S)
-#define OTP_DEBUG_BLOCK2_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W1_S  0
-
-/** OTP_DEBUG_BLK2_W2_REG register
- *  Otp debuger block2 data register2.
- */
-#define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c)
-/** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word2 data.
- */
-#define OTP_DEBUG_BLOCK2_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W2_M  (OTP_DEBUG_BLOCK2_W2_V << OTP_DEBUG_BLOCK2_W2_S)
-#define OTP_DEBUG_BLOCK2_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W2_S  0
-
-/** OTP_DEBUG_BLK2_W3_REG register
- *  Otp debuger block2 data register3.
- */
-#define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80)
-/** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word3 data.
- */
-#define OTP_DEBUG_BLOCK2_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W3_M  (OTP_DEBUG_BLOCK2_W3_V << OTP_DEBUG_BLOCK2_W3_S)
-#define OTP_DEBUG_BLOCK2_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W3_S  0
-
-/** OTP_DEBUG_BLK2_W4_REG register
- *  Otp debuger block2 data register4.
- */
-#define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84)
-/** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word4 data.
- */
-#define OTP_DEBUG_BLOCK2_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W4_M  (OTP_DEBUG_BLOCK2_W4_V << OTP_DEBUG_BLOCK2_W4_S)
-#define OTP_DEBUG_BLOCK2_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W4_S  0
-
-/** OTP_DEBUG_BLK2_W5_REG register
- *  Otp debuger block2 data register5.
- */
-#define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88)
-/** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word5 data.
- */
-#define OTP_DEBUG_BLOCK2_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W5_M  (OTP_DEBUG_BLOCK2_W5_V << OTP_DEBUG_BLOCK2_W5_S)
-#define OTP_DEBUG_BLOCK2_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W5_S  0
-
-/** OTP_DEBUG_BLK2_W6_REG register
- *  Otp debuger block2 data register6.
- */
-#define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c)
-/** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word6 data.
- */
-#define OTP_DEBUG_BLOCK2_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W6_M  (OTP_DEBUG_BLOCK2_W6_V << OTP_DEBUG_BLOCK2_W6_S)
-#define OTP_DEBUG_BLOCK2_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W6_S  0
-
-/** OTP_DEBUG_BLK2_W7_REG register
- *  Otp debuger block2 data register7.
- */
-#define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90)
-/** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word7 data.
- */
-#define OTP_DEBUG_BLOCK2_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W7_M  (OTP_DEBUG_BLOCK2_W7_V << OTP_DEBUG_BLOCK2_W7_S)
-#define OTP_DEBUG_BLOCK2_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W7_S  0
-
-/** OTP_DEBUG_BLK2_W8_REG register
- *  Otp debuger block2 data register8.
- */
-#define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94)
-/** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word8 data.
- */
-#define OTP_DEBUG_BLOCK2_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W8_M  (OTP_DEBUG_BLOCK2_W8_V << OTP_DEBUG_BLOCK2_W8_S)
-#define OTP_DEBUG_BLOCK2_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W8_S  0
-
-/** OTP_DEBUG_BLK2_W9_REG register
- *  Otp debuger block2 data register9.
- */
-#define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98)
-/** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word9 data.
- */
-#define OTP_DEBUG_BLOCK2_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W9_M  (OTP_DEBUG_BLOCK2_W9_V << OTP_DEBUG_BLOCK2_W9_S)
-#define OTP_DEBUG_BLOCK2_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W9_S  0
-
-/** OTP_DEBUG_BLK2_W10_REG register
- *  Otp debuger block2 data register10.
- */
-#define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c)
-/** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word10 data.
- */
-#define OTP_DEBUG_BLOCK2_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W10_M  (OTP_DEBUG_BLOCK2_W10_V << OTP_DEBUG_BLOCK2_W10_S)
-#define OTP_DEBUG_BLOCK2_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W10_S  0
-
-/** OTP_DEBUG_BLK2_W11_REG register
- *  Otp debuger block2 data register11.
- */
-#define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0)
-/** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word11 data.
- */
-#define OTP_DEBUG_BLOCK2_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W11_M  (OTP_DEBUG_BLOCK2_W11_V << OTP_DEBUG_BLOCK2_W11_S)
-#define OTP_DEBUG_BLOCK2_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK2_W11_S  0
-
-/** OTP_DEBUG_BLK3_W1_REG register
- *  Otp debuger block3 data register1.
- */
-#define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4)
-/** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word1 data.
- */
-#define OTP_DEBUG_BLOCK3_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W1_M  (OTP_DEBUG_BLOCK3_W1_V << OTP_DEBUG_BLOCK3_W1_S)
-#define OTP_DEBUG_BLOCK3_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W1_S  0
-
-/** OTP_DEBUG_BLK3_W2_REG register
- *  Otp debuger block3 data register2.
- */
-#define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8)
-/** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word2 data.
- */
-#define OTP_DEBUG_BLOCK3_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W2_M  (OTP_DEBUG_BLOCK3_W2_V << OTP_DEBUG_BLOCK3_W2_S)
-#define OTP_DEBUG_BLOCK3_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W2_S  0
-
-/** OTP_DEBUG_BLK3_W3_REG register
- *  Otp debuger block3 data register3.
- */
-#define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac)
-/** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word3 data.
- */
-#define OTP_DEBUG_BLOCK3_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W3_M  (OTP_DEBUG_BLOCK3_W3_V << OTP_DEBUG_BLOCK3_W3_S)
-#define OTP_DEBUG_BLOCK3_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W3_S  0
-
-/** OTP_DEBUG_BLK3_W4_REG register
- *  Otp debuger block3 data register4.
- */
-#define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0)
-/** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word4 data.
- */
-#define OTP_DEBUG_BLOCK3_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W4_M  (OTP_DEBUG_BLOCK3_W4_V << OTP_DEBUG_BLOCK3_W4_S)
-#define OTP_DEBUG_BLOCK3_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W4_S  0
-
-/** OTP_DEBUG_BLK3_W5_REG register
- *  Otp debuger block3 data register5.
- */
-#define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4)
-/** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word5 data.
- */
-#define OTP_DEBUG_BLOCK3_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W5_M  (OTP_DEBUG_BLOCK3_W5_V << OTP_DEBUG_BLOCK3_W5_S)
-#define OTP_DEBUG_BLOCK3_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W5_S  0
-
-/** OTP_DEBUG_BLK3_W6_REG register
- *  Otp debuger block3 data register6.
- */
-#define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8)
-/** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word6 data.
- */
-#define OTP_DEBUG_BLOCK3_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W6_M  (OTP_DEBUG_BLOCK3_W6_V << OTP_DEBUG_BLOCK3_W6_S)
-#define OTP_DEBUG_BLOCK3_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W6_S  0
-
-/** OTP_DEBUG_BLK3_W7_REG register
- *  Otp debuger block3 data register7.
- */
-#define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc)
-/** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word7 data.
- */
-#define OTP_DEBUG_BLOCK3_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W7_M  (OTP_DEBUG_BLOCK3_W7_V << OTP_DEBUG_BLOCK3_W7_S)
-#define OTP_DEBUG_BLOCK3_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W7_S  0
-
-/** OTP_DEBUG_BLK3_W8_REG register
- *  Otp debuger block3 data register8.
- */
-#define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0)
-/** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word8 data.
- */
-#define OTP_DEBUG_BLOCK3_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W8_M  (OTP_DEBUG_BLOCK3_W8_V << OTP_DEBUG_BLOCK3_W8_S)
-#define OTP_DEBUG_BLOCK3_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W8_S  0
-
-/** OTP_DEBUG_BLK3_W9_REG register
- *  Otp debuger block3 data register9.
- */
-#define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4)
-/** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word9 data.
- */
-#define OTP_DEBUG_BLOCK3_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W9_M  (OTP_DEBUG_BLOCK3_W9_V << OTP_DEBUG_BLOCK3_W9_S)
-#define OTP_DEBUG_BLOCK3_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W9_S  0
-
-/** OTP_DEBUG_BLK3_W10_REG register
- *  Otp debuger block3 data register10.
- */
-#define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8)
-/** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word10 data.
- */
-#define OTP_DEBUG_BLOCK3_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W10_M  (OTP_DEBUG_BLOCK3_W10_V << OTP_DEBUG_BLOCK3_W10_S)
-#define OTP_DEBUG_BLOCK3_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W10_S  0
-
-/** OTP_DEBUG_BLK3_W11_REG register
- *  Otp debuger block3 data register11.
- */
-#define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc)
-/** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word11 data.
- */
-#define OTP_DEBUG_BLOCK3_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W11_M  (OTP_DEBUG_BLOCK3_W11_V << OTP_DEBUG_BLOCK3_W11_S)
-#define OTP_DEBUG_BLOCK3_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK3_W11_S  0
-
-/** OTP_DEBUG_BLK4_W1_REG register
- *  Otp debuger block4 data register1.
- */
-#define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0)
-/** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word1 data.
- */
-#define OTP_DEBUG_BLOCK4_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W1_M  (OTP_DEBUG_BLOCK4_W1_V << OTP_DEBUG_BLOCK4_W1_S)
-#define OTP_DEBUG_BLOCK4_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W1_S  0
-
-/** OTP_DEBUG_BLK4_W2_REG register
- *  Otp debuger block4 data register2.
- */
-#define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4)
-/** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word2 data.
- */
-#define OTP_DEBUG_BLOCK4_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W2_M  (OTP_DEBUG_BLOCK4_W2_V << OTP_DEBUG_BLOCK4_W2_S)
-#define OTP_DEBUG_BLOCK4_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W2_S  0
-
-/** OTP_DEBUG_BLK4_W3_REG register
- *  Otp debuger block4 data register3.
- */
-#define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8)
-/** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word3 data.
- */
-#define OTP_DEBUG_BLOCK4_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W3_M  (OTP_DEBUG_BLOCK4_W3_V << OTP_DEBUG_BLOCK4_W3_S)
-#define OTP_DEBUG_BLOCK4_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W3_S  0
-
-/** OTP_DEBUG_BLK4_W4_REG register
- *  Otp debuger block4 data register4.
- */
-#define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc)
-/** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word4 data.
- */
-#define OTP_DEBUG_BLOCK4_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W4_M  (OTP_DEBUG_BLOCK4_W4_V << OTP_DEBUG_BLOCK4_W4_S)
-#define OTP_DEBUG_BLOCK4_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W4_S  0
-
-/** OTP_DEBUG_BLK4_W5_REG register
- *  Otp debuger block4 data register5.
- */
-#define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0)
-/** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word5 data.
- */
-#define OTP_DEBUG_BLOCK4_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W5_M  (OTP_DEBUG_BLOCK4_W5_V << OTP_DEBUG_BLOCK4_W5_S)
-#define OTP_DEBUG_BLOCK4_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W5_S  0
-
-/** OTP_DEBUG_BLK4_W6_REG register
- *  Otp debuger block4 data register6.
- */
-#define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4)
-/** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word6 data.
- */
-#define OTP_DEBUG_BLOCK4_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W6_M  (OTP_DEBUG_BLOCK4_W6_V << OTP_DEBUG_BLOCK4_W6_S)
-#define OTP_DEBUG_BLOCK4_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W6_S  0
-
-/** OTP_DEBUG_BLK4_W7_REG register
- *  Otp debuger block4 data register7.
- */
-#define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8)
-/** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word7 data.
- */
-#define OTP_DEBUG_BLOCK4_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W7_M  (OTP_DEBUG_BLOCK4_W7_V << OTP_DEBUG_BLOCK4_W7_S)
-#define OTP_DEBUG_BLOCK4_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W7_S  0
-
-/** OTP_DEBUG_BLK4_W8_REG register
- *  Otp debuger block4 data register8.
- */
-#define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec)
-/** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word8 data.
- */
-#define OTP_DEBUG_BLOCK4_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W8_M  (OTP_DEBUG_BLOCK4_W8_V << OTP_DEBUG_BLOCK4_W8_S)
-#define OTP_DEBUG_BLOCK4_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W8_S  0
-
-/** OTP_DEBUG_BLK4_W9_REG register
- *  Otp debuger block4 data register9.
- */
-#define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0)
-/** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word9 data.
- */
-#define OTP_DEBUG_BLOCK4_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W9_M  (OTP_DEBUG_BLOCK4_W9_V << OTP_DEBUG_BLOCK4_W9_S)
-#define OTP_DEBUG_BLOCK4_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W9_S  0
-
-/** OTP_DEBUG_BLK4_W10_REG register
- *  Otp debuger block4 data registe10.
- */
-#define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4)
-/** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word10 data.
- */
-#define OTP_DEBUG_BLOCK4_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W10_M  (OTP_DEBUG_BLOCK4_W10_V << OTP_DEBUG_BLOCK4_W10_S)
-#define OTP_DEBUG_BLOCK4_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W10_S  0
-
-/** OTP_DEBUG_BLK4_W11_REG register
- *  Otp debuger block4 data register11.
- */
-#define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8)
-/** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word11 data.
- */
-#define OTP_DEBUG_BLOCK4_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W11_M  (OTP_DEBUG_BLOCK4_W11_V << OTP_DEBUG_BLOCK4_W11_S)
-#define OTP_DEBUG_BLOCK4_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK4_W11_S  0
-
-/** OTP_DEBUG_BLK5_W1_REG register
- *  Otp debuger block5 data register1.
- */
-#define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc)
-/** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word1 data.
- */
-#define OTP_DEBUG_BLOCK5_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W1_M  (OTP_DEBUG_BLOCK5_W1_V << OTP_DEBUG_BLOCK5_W1_S)
-#define OTP_DEBUG_BLOCK5_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W1_S  0
-
-/** OTP_DEBUG_BLK5_W2_REG register
- *  Otp debuger block5 data register2.
- */
-#define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100)
-/** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word2 data.
- */
-#define OTP_DEBUG_BLOCK5_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W2_M  (OTP_DEBUG_BLOCK5_W2_V << OTP_DEBUG_BLOCK5_W2_S)
-#define OTP_DEBUG_BLOCK5_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W2_S  0
-
-/** OTP_DEBUG_BLK5_W3_REG register
- *  Otp debuger block5 data register3.
- */
-#define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104)
-/** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word3 data.
- */
-#define OTP_DEBUG_BLOCK5_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W3_M  (OTP_DEBUG_BLOCK5_W3_V << OTP_DEBUG_BLOCK5_W3_S)
-#define OTP_DEBUG_BLOCK5_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W3_S  0
-
-/** OTP_DEBUG_BLK5_W4_REG register
- *  Otp debuger block5 data register4.
- */
-#define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108)
-/** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word4 data.
- */
-#define OTP_DEBUG_BLOCK5_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W4_M  (OTP_DEBUG_BLOCK5_W4_V << OTP_DEBUG_BLOCK5_W4_S)
-#define OTP_DEBUG_BLOCK5_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W4_S  0
-
-/** OTP_DEBUG_BLK5_W5_REG register
- *  Otp debuger block5 data register5.
- */
-#define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c)
-/** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word5 data.
- */
-#define OTP_DEBUG_BLOCK5_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W5_M  (OTP_DEBUG_BLOCK5_W5_V << OTP_DEBUG_BLOCK5_W5_S)
-#define OTP_DEBUG_BLOCK5_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W5_S  0
-
-/** OTP_DEBUG_BLK5_W6_REG register
- *  Otp debuger block5 data register6.
- */
-#define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110)
-/** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word6 data.
- */
-#define OTP_DEBUG_BLOCK5_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W6_M  (OTP_DEBUG_BLOCK5_W6_V << OTP_DEBUG_BLOCK5_W6_S)
-#define OTP_DEBUG_BLOCK5_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W6_S  0
-
-/** OTP_DEBUG_BLK5_W7_REG register
- *  Otp debuger block5 data register7.
- */
-#define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114)
-/** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word7 data.
- */
-#define OTP_DEBUG_BLOCK5_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W7_M  (OTP_DEBUG_BLOCK5_W7_V << OTP_DEBUG_BLOCK5_W7_S)
-#define OTP_DEBUG_BLOCK5_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W7_S  0
-
-/** OTP_DEBUG_BLK5_W8_REG register
- *  Otp debuger block5 data register8.
- */
-#define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118)
-/** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word8 data.
- */
-#define OTP_DEBUG_BLOCK5_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W8_M  (OTP_DEBUG_BLOCK5_W8_V << OTP_DEBUG_BLOCK5_W8_S)
-#define OTP_DEBUG_BLOCK5_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W8_S  0
-
-/** OTP_DEBUG_BLK5_W9_REG register
- *  Otp debuger block5 data register9.
- */
-#define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c)
-/** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word9 data.
- */
-#define OTP_DEBUG_BLOCK5_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W9_M  (OTP_DEBUG_BLOCK5_W9_V << OTP_DEBUG_BLOCK5_W9_S)
-#define OTP_DEBUG_BLOCK5_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W9_S  0
-
-/** OTP_DEBUG_BLK5_W10_REG register
- *  Otp debuger block5 data register10.
- */
-#define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120)
-/** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word10 data.
- */
-#define OTP_DEBUG_BLOCK5_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W10_M  (OTP_DEBUG_BLOCK5_W10_V << OTP_DEBUG_BLOCK5_W10_S)
-#define OTP_DEBUG_BLOCK5_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W10_S  0
-
-/** OTP_DEBUG_BLK5_W11_REG register
- *  Otp debuger block5 data register11.
- */
-#define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124)
-/** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word11 data.
- */
-#define OTP_DEBUG_BLOCK5_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W11_M  (OTP_DEBUG_BLOCK5_W11_V << OTP_DEBUG_BLOCK5_W11_S)
-#define OTP_DEBUG_BLOCK5_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK5_W11_S  0
-
-/** OTP_DEBUG_BLK6_W1_REG register
- *  Otp debuger block6 data register1.
- */
-#define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128)
-/** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word1 data.
- */
-#define OTP_DEBUG_BLOCK6_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W1_M  (OTP_DEBUG_BLOCK6_W1_V << OTP_DEBUG_BLOCK6_W1_S)
-#define OTP_DEBUG_BLOCK6_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W1_S  0
-
-/** OTP_DEBUG_BLK6_W2_REG register
- *  Otp debuger block6 data register2.
- */
-#define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c)
-/** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word2 data.
- */
-#define OTP_DEBUG_BLOCK6_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W2_M  (OTP_DEBUG_BLOCK6_W2_V << OTP_DEBUG_BLOCK6_W2_S)
-#define OTP_DEBUG_BLOCK6_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W2_S  0
-
-/** OTP_DEBUG_BLK6_W3_REG register
- *  Otp debuger block6 data register3.
- */
-#define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130)
-/** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word3 data.
- */
-#define OTP_DEBUG_BLOCK6_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W3_M  (OTP_DEBUG_BLOCK6_W3_V << OTP_DEBUG_BLOCK6_W3_S)
-#define OTP_DEBUG_BLOCK6_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W3_S  0
-
-/** OTP_DEBUG_BLK6_W4_REG register
- *  Otp debuger block6 data register4.
- */
-#define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134)
-/** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word4 data.
- */
-#define OTP_DEBUG_BLOCK6_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W4_M  (OTP_DEBUG_BLOCK6_W4_V << OTP_DEBUG_BLOCK6_W4_S)
-#define OTP_DEBUG_BLOCK6_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W4_S  0
-
-/** OTP_DEBUG_BLK6_W5_REG register
- *  Otp debuger block6 data register5.
- */
-#define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138)
-/** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word5 data.
- */
-#define OTP_DEBUG_BLOCK6_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W5_M  (OTP_DEBUG_BLOCK6_W5_V << OTP_DEBUG_BLOCK6_W5_S)
-#define OTP_DEBUG_BLOCK6_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W5_S  0
-
-/** OTP_DEBUG_BLK6_W6_REG register
- *  Otp debuger block6 data register6.
- */
-#define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c)
-/** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word6 data.
- */
-#define OTP_DEBUG_BLOCK6_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W6_M  (OTP_DEBUG_BLOCK6_W6_V << OTP_DEBUG_BLOCK6_W6_S)
-#define OTP_DEBUG_BLOCK6_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W6_S  0
-
-/** OTP_DEBUG_BLK6_W7_REG register
- *  Otp debuger block6 data register7.
- */
-#define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140)
-/** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word7 data.
- */
-#define OTP_DEBUG_BLOCK6_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W7_M  (OTP_DEBUG_BLOCK6_W7_V << OTP_DEBUG_BLOCK6_W7_S)
-#define OTP_DEBUG_BLOCK6_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W7_S  0
-
-/** OTP_DEBUG_BLK6_W8_REG register
- *  Otp debuger block6 data register8.
- */
-#define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144)
-/** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word8 data.
- */
-#define OTP_DEBUG_BLOCK6_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W8_M  (OTP_DEBUG_BLOCK6_W8_V << OTP_DEBUG_BLOCK6_W8_S)
-#define OTP_DEBUG_BLOCK6_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W8_S  0
-
-/** OTP_DEBUG_BLK6_W9_REG register
- *  Otp debuger block6 data register9.
- */
-#define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148)
-/** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word9 data.
- */
-#define OTP_DEBUG_BLOCK6_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W9_M  (OTP_DEBUG_BLOCK6_W9_V << OTP_DEBUG_BLOCK6_W9_S)
-#define OTP_DEBUG_BLOCK6_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W9_S  0
-
-/** OTP_DEBUG_BLK6_W10_REG register
- *  Otp debuger block6 data register10.
- */
-#define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c)
-/** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word10 data.
- */
-#define OTP_DEBUG_BLOCK6_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W10_M  (OTP_DEBUG_BLOCK6_W10_V << OTP_DEBUG_BLOCK6_W10_S)
-#define OTP_DEBUG_BLOCK6_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W10_S  0
-
-/** OTP_DEBUG_BLK6_W11_REG register
- *  Otp debuger block6 data register11.
- */
-#define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150)
-/** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word11 data.
- */
-#define OTP_DEBUG_BLOCK6_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W11_M  (OTP_DEBUG_BLOCK6_W11_V << OTP_DEBUG_BLOCK6_W11_S)
-#define OTP_DEBUG_BLOCK6_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK6_W11_S  0
-
-/** OTP_DEBUG_BLK7_W1_REG register
- *  Otp debuger block7 data register1.
- */
-#define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154)
-/** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word1 data.
- */
-#define OTP_DEBUG_BLOCK7_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W1_M  (OTP_DEBUG_BLOCK7_W1_V << OTP_DEBUG_BLOCK7_W1_S)
-#define OTP_DEBUG_BLOCK7_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W1_S  0
-
-/** OTP_DEBUG_BLK7_W2_REG register
- *  Otp debuger block7 data register2.
- */
-#define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158)
-/** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word2 data.
- */
-#define OTP_DEBUG_BLOCK7_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W2_M  (OTP_DEBUG_BLOCK7_W2_V << OTP_DEBUG_BLOCK7_W2_S)
-#define OTP_DEBUG_BLOCK7_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W2_S  0
-
-/** OTP_DEBUG_BLK7_W3_REG register
- *  Otp debuger block7 data register3.
- */
-#define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c)
-/** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word3 data.
- */
-#define OTP_DEBUG_BLOCK7_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W3_M  (OTP_DEBUG_BLOCK7_W3_V << OTP_DEBUG_BLOCK7_W3_S)
-#define OTP_DEBUG_BLOCK7_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W3_S  0
-
-/** OTP_DEBUG_BLK7_W4_REG register
- *  Otp debuger block7 data register4.
- */
-#define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160)
-/** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word4 data.
- */
-#define OTP_DEBUG_BLOCK7_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W4_M  (OTP_DEBUG_BLOCK7_W4_V << OTP_DEBUG_BLOCK7_W4_S)
-#define OTP_DEBUG_BLOCK7_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W4_S  0
-
-/** OTP_DEBUG_BLK7_W5_REG register
- *  Otp debuger block7 data register5.
- */
-#define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164)
-/** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word5 data.
- */
-#define OTP_DEBUG_BLOCK7_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W5_M  (OTP_DEBUG_BLOCK7_W5_V << OTP_DEBUG_BLOCK7_W5_S)
-#define OTP_DEBUG_BLOCK7_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W5_S  0
-
-/** OTP_DEBUG_BLK7_W6_REG register
- *  Otp debuger block7 data register6.
- */
-#define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168)
-/** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word6 data.
- */
-#define OTP_DEBUG_BLOCK7_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W6_M  (OTP_DEBUG_BLOCK7_W6_V << OTP_DEBUG_BLOCK7_W6_S)
-#define OTP_DEBUG_BLOCK7_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W6_S  0
-
-/** OTP_DEBUG_BLK7_W7_REG register
- *  Otp debuger block7 data register7.
- */
-#define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c)
-/** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word7 data.
- */
-#define OTP_DEBUG_BLOCK7_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W7_M  (OTP_DEBUG_BLOCK7_W7_V << OTP_DEBUG_BLOCK7_W7_S)
-#define OTP_DEBUG_BLOCK7_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W7_S  0
-
-/** OTP_DEBUG_BLK7_W8_REG register
- *  Otp debuger block7 data register8.
- */
-#define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170)
-/** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word8 data.
- */
-#define OTP_DEBUG_BLOCK7_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W8_M  (OTP_DEBUG_BLOCK7_W8_V << OTP_DEBUG_BLOCK7_W8_S)
-#define OTP_DEBUG_BLOCK7_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W8_S  0
-
-/** OTP_DEBUG_BLK7_W9_REG register
- *  Otp debuger block7 data register9.
- */
-#define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174)
-/** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word9 data.
- */
-#define OTP_DEBUG_BLOCK7_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W9_M  (OTP_DEBUG_BLOCK7_W9_V << OTP_DEBUG_BLOCK7_W9_S)
-#define OTP_DEBUG_BLOCK7_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W9_S  0
-
-/** OTP_DEBUG_BLK7_W10_REG register
- *  Otp debuger block7 data register10.
- */
-#define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178)
-/** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word10 data.
- */
-#define OTP_DEBUG_BLOCK7_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W10_M  (OTP_DEBUG_BLOCK7_W10_V << OTP_DEBUG_BLOCK7_W10_S)
-#define OTP_DEBUG_BLOCK7_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W10_S  0
-
-/** OTP_DEBUG_BLK7_W11_REG register
- *  Otp debuger block7 data register11.
- */
-#define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c)
-/** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word11 data.
- */
-#define OTP_DEBUG_BLOCK7_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W11_M  (OTP_DEBUG_BLOCK7_W11_V << OTP_DEBUG_BLOCK7_W11_S)
-#define OTP_DEBUG_BLOCK7_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK7_W11_S  0
-
-/** OTP_DEBUG_BLK8_W1_REG register
- *  Otp debuger block8 data register1.
- */
-#define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180)
-/** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word1 data.
- */
-#define OTP_DEBUG_BLOCK8_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W1_M  (OTP_DEBUG_BLOCK8_W1_V << OTP_DEBUG_BLOCK8_W1_S)
-#define OTP_DEBUG_BLOCK8_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W1_S  0
-
-/** OTP_DEBUG_BLK8_W2_REG register
- *  Otp debuger block8 data register2.
- */
-#define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184)
-/** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word2 data.
- */
-#define OTP_DEBUG_BLOCK8_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W2_M  (OTP_DEBUG_BLOCK8_W2_V << OTP_DEBUG_BLOCK8_W2_S)
-#define OTP_DEBUG_BLOCK8_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W2_S  0
-
-/** OTP_DEBUG_BLK8_W3_REG register
- *  Otp debuger block8 data register3.
- */
-#define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188)
-/** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word3 data.
- */
-#define OTP_DEBUG_BLOCK8_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W3_M  (OTP_DEBUG_BLOCK8_W3_V << OTP_DEBUG_BLOCK8_W3_S)
-#define OTP_DEBUG_BLOCK8_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W3_S  0
-
-/** OTP_DEBUG_BLK8_W4_REG register
- *  Otp debuger block8 data register4.
- */
-#define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c)
-/** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word4 data.
- */
-#define OTP_DEBUG_BLOCK8_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W4_M  (OTP_DEBUG_BLOCK8_W4_V << OTP_DEBUG_BLOCK8_W4_S)
-#define OTP_DEBUG_BLOCK8_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W4_S  0
-
-/** OTP_DEBUG_BLK8_W5_REG register
- *  Otp debuger block8 data register5.
- */
-#define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190)
-/** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word5 data.
- */
-#define OTP_DEBUG_BLOCK8_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W5_M  (OTP_DEBUG_BLOCK8_W5_V << OTP_DEBUG_BLOCK8_W5_S)
-#define OTP_DEBUG_BLOCK8_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W5_S  0
-
-/** OTP_DEBUG_BLK8_W6_REG register
- *  Otp debuger block8 data register6.
- */
-#define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194)
-/** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word6 data.
- */
-#define OTP_DEBUG_BLOCK8_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W6_M  (OTP_DEBUG_BLOCK8_W6_V << OTP_DEBUG_BLOCK8_W6_S)
-#define OTP_DEBUG_BLOCK8_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W6_S  0
-
-/** OTP_DEBUG_BLK8_W7_REG register
- *  Otp debuger block8 data register7.
- */
-#define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198)
-/** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word7 data.
- */
-#define OTP_DEBUG_BLOCK8_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W7_M  (OTP_DEBUG_BLOCK8_W7_V << OTP_DEBUG_BLOCK8_W7_S)
-#define OTP_DEBUG_BLOCK8_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W7_S  0
-
-/** OTP_DEBUG_BLK8_W8_REG register
- *  Otp debuger block8 data register8.
- */
-#define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c)
-/** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word8 data.
- */
-#define OTP_DEBUG_BLOCK8_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W8_M  (OTP_DEBUG_BLOCK8_W8_V << OTP_DEBUG_BLOCK8_W8_S)
-#define OTP_DEBUG_BLOCK8_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W8_S  0
-
-/** OTP_DEBUG_BLK8_W9_REG register
- *  Otp debuger block8 data register9.
- */
-#define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0)
-/** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word9 data.
- */
-#define OTP_DEBUG_BLOCK8_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W9_M  (OTP_DEBUG_BLOCK8_W9_V << OTP_DEBUG_BLOCK8_W9_S)
-#define OTP_DEBUG_BLOCK8_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W9_S  0
-
-/** OTP_DEBUG_BLK8_W10_REG register
- *  Otp debuger block8 data register10.
- */
-#define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4)
-/** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word10 data.
- */
-#define OTP_DEBUG_BLOCK8_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W10_M  (OTP_DEBUG_BLOCK8_W10_V << OTP_DEBUG_BLOCK8_W10_S)
-#define OTP_DEBUG_BLOCK8_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W10_S  0
-
-/** OTP_DEBUG_BLK8_W11_REG register
- *  Otp debuger block8 data register11.
- */
-#define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8)
-/** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word11 data.
- */
-#define OTP_DEBUG_BLOCK8_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W11_M  (OTP_DEBUG_BLOCK8_W11_V << OTP_DEBUG_BLOCK8_W11_S)
-#define OTP_DEBUG_BLOCK8_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK8_W11_S  0
-
-/** OTP_DEBUG_BLK9_W1_REG register
- *  Otp debuger block9 data register1.
- */
-#define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac)
-/** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word1 data.
- */
-#define OTP_DEBUG_BLOCK9_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W1_M  (OTP_DEBUG_BLOCK9_W1_V << OTP_DEBUG_BLOCK9_W1_S)
-#define OTP_DEBUG_BLOCK9_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W1_S  0
-
-/** OTP_DEBUG_BLK9_W2_REG register
- *  Otp debuger block9 data register2.
- */
-#define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0)
-/** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word2 data.
- */
-#define OTP_DEBUG_BLOCK9_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W2_M  (OTP_DEBUG_BLOCK9_W2_V << OTP_DEBUG_BLOCK9_W2_S)
-#define OTP_DEBUG_BLOCK9_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W2_S  0
-
-/** OTP_DEBUG_BLK9_W3_REG register
- *  Otp debuger block9 data register3.
- */
-#define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4)
-/** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word3 data.
- */
-#define OTP_DEBUG_BLOCK9_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W3_M  (OTP_DEBUG_BLOCK9_W3_V << OTP_DEBUG_BLOCK9_W3_S)
-#define OTP_DEBUG_BLOCK9_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W3_S  0
-
-/** OTP_DEBUG_BLK9_W4_REG register
- *  Otp debuger block9 data register4.
- */
-#define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8)
-/** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word4 data.
- */
-#define OTP_DEBUG_BLOCK9_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W4_M  (OTP_DEBUG_BLOCK9_W4_V << OTP_DEBUG_BLOCK9_W4_S)
-#define OTP_DEBUG_BLOCK9_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W4_S  0
-
-/** OTP_DEBUG_BLK9_W5_REG register
- *  Otp debuger block9 data register5.
- */
-#define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc)
-/** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word5 data.
- */
-#define OTP_DEBUG_BLOCK9_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W5_M  (OTP_DEBUG_BLOCK9_W5_V << OTP_DEBUG_BLOCK9_W5_S)
-#define OTP_DEBUG_BLOCK9_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W5_S  0
-
-/** OTP_DEBUG_BLK9_W6_REG register
- *  Otp debuger block9 data register6.
- */
-#define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0)
-/** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word6 data.
- */
-#define OTP_DEBUG_BLOCK9_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W6_M  (OTP_DEBUG_BLOCK9_W6_V << OTP_DEBUG_BLOCK9_W6_S)
-#define OTP_DEBUG_BLOCK9_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W6_S  0
-
-/** OTP_DEBUG_BLK9_W7_REG register
- *  Otp debuger block9 data register7.
- */
-#define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4)
-/** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word7 data.
- */
-#define OTP_DEBUG_BLOCK9_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W7_M  (OTP_DEBUG_BLOCK9_W7_V << OTP_DEBUG_BLOCK9_W7_S)
-#define OTP_DEBUG_BLOCK9_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W7_S  0
-
-/** OTP_DEBUG_BLK9_W8_REG register
- *  Otp debuger block9 data register8.
- */
-#define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8)
-/** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word8 data.
- */
-#define OTP_DEBUG_BLOCK9_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W8_M  (OTP_DEBUG_BLOCK9_W8_V << OTP_DEBUG_BLOCK9_W8_S)
-#define OTP_DEBUG_BLOCK9_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W8_S  0
-
-/** OTP_DEBUG_BLK9_W9_REG register
- *  Otp debuger block9 data register9.
- */
-#define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc)
-/** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word9 data.
- */
-#define OTP_DEBUG_BLOCK9_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W9_M  (OTP_DEBUG_BLOCK9_W9_V << OTP_DEBUG_BLOCK9_W9_S)
-#define OTP_DEBUG_BLOCK9_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W9_S  0
-
-/** OTP_DEBUG_BLK9_W10_REG register
- *  Otp debuger block9 data register10.
- */
-#define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0)
-/** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word10 data.
- */
-#define OTP_DEBUG_BLOCK9_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W10_M  (OTP_DEBUG_BLOCK9_W10_V << OTP_DEBUG_BLOCK9_W10_S)
-#define OTP_DEBUG_BLOCK9_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W10_S  0
-
-/** OTP_DEBUG_BLK9_W11_REG register
- *  Otp debuger block9 data register11.
- */
-#define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4)
-/** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word11 data.
- */
-#define OTP_DEBUG_BLOCK9_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W11_M  (OTP_DEBUG_BLOCK9_W11_V << OTP_DEBUG_BLOCK9_W11_S)
-#define OTP_DEBUG_BLOCK9_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK9_W11_S  0
-
-/** OTP_DEBUG_BLK10_W1_REG register
- *  Otp debuger block10 data register1.
- */
-#define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8)
-/** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word1 data.
- */
-#define OTP_DEBUG_BLOCK10_W1    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W1_M  (OTP_DEBUG_BLOCK10_W1_V << OTP_DEBUG_BLOCK10_W1_S)
-#define OTP_DEBUG_BLOCK10_W1_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W1_S  0
-
-/** OTP_DEBUG_BLK10_W2_REG register
- *  Otp debuger block10 data register2.
- */
-#define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc)
-/** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word2 data.
- */
-#define OTP_DEBUG_BLOCK10_W2    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W2_M  (OTP_DEBUG_BLOCK10_W2_V << OTP_DEBUG_BLOCK10_W2_S)
-#define OTP_DEBUG_BLOCK10_W2_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W2_S  0
-
-/** OTP_DEBUG_BLK10_W3_REG register
- *  Otp debuger block10 data register3.
- */
-#define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0)
-/** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word3 data.
- */
-#define OTP_DEBUG_BLOCK10_W3    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W3_M  (OTP_DEBUG_BLOCK10_W3_V << OTP_DEBUG_BLOCK10_W3_S)
-#define OTP_DEBUG_BLOCK10_W3_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W3_S  0
-
-/** OTP_DEBUG_BLK10_W4_REG register
- *  Otp debuger block10 data register4.
- */
-#define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4)
-/** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word4 data.
- */
-#define OTP_DEBUG_BLOCK10_W4    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W4_M  (OTP_DEBUG_BLOCK10_W4_V << OTP_DEBUG_BLOCK10_W4_S)
-#define OTP_DEBUG_BLOCK10_W4_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W4_S  0
-
-/** OTP_DEBUG_BLK10_W5_REG register
- *  Otp debuger block10 data register5.
- */
-#define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8)
-/** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word5 data.
- */
-#define OTP_DEBUG_BLOCK10_W5    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W5_M  (OTP_DEBUG_BLOCK10_W5_V << OTP_DEBUG_BLOCK10_W5_S)
-#define OTP_DEBUG_BLOCK10_W5_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W5_S  0
-
-/** OTP_DEBUG_BLK10_W6_REG register
- *  Otp debuger block10 data register6.
- */
-#define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec)
-/** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word6 data.
- */
-#define OTP_DEBUG_BLOCK10_W6    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W6_M  (OTP_DEBUG_BLOCK10_W6_V << OTP_DEBUG_BLOCK10_W6_S)
-#define OTP_DEBUG_BLOCK10_W6_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W6_S  0
-
-/** OTP_DEBUG_BLK10_W7_REG register
- *  Otp debuger block10 data register7.
- */
-#define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0)
-/** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word7 data.
- */
-#define OTP_DEBUG_BLOCK10_W7    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W7_M  (OTP_DEBUG_BLOCK10_W7_V << OTP_DEBUG_BLOCK10_W7_S)
-#define OTP_DEBUG_BLOCK10_W7_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W7_S  0
-
-/** OTP_DEBUG_BLK10_W8_REG register
- *  Otp debuger block10 data register8.
- */
-#define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4)
-/** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word8 data.
- */
-#define OTP_DEBUG_BLOCK10_W8    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W8_M  (OTP_DEBUG_BLOCK10_W8_V << OTP_DEBUG_BLOCK10_W8_S)
-#define OTP_DEBUG_BLOCK10_W8_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W8_S  0
-
-/** OTP_DEBUG_BLK10_W9_REG register
- *  Otp debuger block10 data register9.
- */
-#define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8)
-/** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word9 data.
- */
-#define OTP_DEBUG_BLOCK10_W9    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W9_M  (OTP_DEBUG_BLOCK10_W9_V << OTP_DEBUG_BLOCK10_W9_S)
-#define OTP_DEBUG_BLOCK10_W9_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W9_S  0
-
-/** OTP_DEBUG_BLK10_W10_REG register
- *  Otp debuger block10 data register10.
- */
-#define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc)
-/** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word10 data.
- */
-#define OTP_DEBUG_BLOCK19_W10    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK19_W10_M  (OTP_DEBUG_BLOCK19_W10_V << OTP_DEBUG_BLOCK19_W10_S)
-#define OTP_DEBUG_BLOCK19_W10_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK19_W10_S  0
-
-/** OTP_DEBUG_BLK10_W11_REG register
- *  Otp debuger block10 data register11.
- */
-#define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200)
-/** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word11 data.
- */
-#define OTP_DEBUG_BLOCK10_W11    0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W11_M  (OTP_DEBUG_BLOCK10_W11_V << OTP_DEBUG_BLOCK10_W11_S)
-#define OTP_DEBUG_BLOCK10_W11_V  0xFFFFFFFFU
-#define OTP_DEBUG_BLOCK10_W11_S  0
-
-/** OTP_DEBUG_CLK_REG register
- *  Otp debuger clk_en configuration register.
- */
-#define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204)
-/** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Force clock on for this register file.
- */
-#define OTP_DEBUG_CLK_EN    (BIT(0))
-#define OTP_DEBUG_CLK_EN_M  (OTP_DEBUG_CLK_EN_V << OTP_DEBUG_CLK_EN_S)
-#define OTP_DEBUG_CLK_EN_V  0x00000001U
-#define OTP_DEBUG_CLK_EN_S  0
-
-/** OTP_DEBUG_APB2OTP_EN_REG register
- *  Otp_debuger apb2otp enable configuration register.
- */
-#define OTP_DEBUG_APB2OTP_EN_REG (DR_REG_OTP_DEBUG_BASE + 0x208)
-/** OTP_DEBUG_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
- *  Debug mode enable signal.
- */
-#define OTP_DEBUG_APB2OTP_EN    (BIT(0))
-#define OTP_DEBUG_APB2OTP_EN_M  (OTP_DEBUG_APB2OTP_EN_V << OTP_DEBUG_APB2OTP_EN_S)
-#define OTP_DEBUG_APB2OTP_EN_V  0x00000001U
-#define OTP_DEBUG_APB2OTP_EN_S  0
-
-/** OTP_DEBUG_DATE_REG register
- *  eFuse version register.
- */
-#define OTP_DEBUG_DATE_REG (DR_REG_OTP_DEBUG_BASE + 0x20c)
-/** OTP_DEBUG_DATE : R/W; bitpos: [27:0]; default: 539037736;
- *  Stores otp_debug version.
- */
-#define OTP_DEBUG_DATE    0x0FFFFFFFU
-#define OTP_DEBUG_DATE_M  (OTP_DEBUG_DATE_V << OTP_DEBUG_DATE_S)
-#define OTP_DEBUG_DATE_V  0x0FFFFFFFU
-#define OTP_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/otp_debug_struct.h b/components/soc/esp32c5/beta3/include/soc/otp_debug_struct.h
deleted file mode 100644
index 6afed4ae33..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/otp_debug_struct.h
+++ /dev/null
@@ -1,2137 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: OTP_DEBUG Block0 Write Disable Data */
-/** Type of wr_dis register
- *  Otp debuger block0 data register1.
- */
-typedef union {
-    struct {
-        /** block0_wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 write disable data.
-         */
-        uint32_t block0_wr_dis:32;
-    };
-    uint32_t val;
-} otp_debug_wr_dis_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word1 Data */
-/** Type of blk0_backup1_w1 register
- *  Otp debuger block0 data register2.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word1 data.
-         */
-        uint32_t block0_backup1_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word2 Data */
-/** Type of blk0_backup1_w2 register
- *  Otp debuger block0 data register3.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word2 data.
-         */
-        uint32_t block0_backup1_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word3 Data */
-/** Type of blk0_backup1_w3 register
- *  Otp debuger block0 data register4.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word3 data.
-         */
-        uint32_t block0_backup1_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word4 Data */
-/** Type of blk0_backup1_w4 register
- *  Otp debuger block0 data register5.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word4 data.
-         */
-        uint32_t block0_backup1_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup1 Word5 Data */
-/** Type of blk0_backup1_w5 register
- *  Otp debuger block0 data register6.
- */
-typedef union {
-    struct {
-        /** block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word5 data.
-         */
-        uint32_t block0_backup1_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup1_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word1 Data */
-/** Type of blk0_backup2_w1 register
- *  Otp debuger block0 data register7.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word1 data.
-         */
-        uint32_t block0_backup2_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word2 Data */
-/** Type of blk0_backup2_w2 register
- *  Otp debuger block0 data register8.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word2 data.
-         */
-        uint32_t block0_backup2_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word3 Data */
-/** Type of blk0_backup2_w3 register
- *  Otp debuger block0 data register9.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word3 data.
-         */
-        uint32_t block0_backup2_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word4 Data */
-/** Type of blk0_backup2_w4 register
- *  Otp debuger block0 data register10.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word4 data.
-         */
-        uint32_t block0_backup2_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup2 Word5 Data */
-/** Type of blk0_backup2_w5 register
- *  Otp debuger block0 data register11.
- */
-typedef union {
-    struct {
-        /** block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word5 data.
-         */
-        uint32_t block0_backup2_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup2_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word1 Data */
-/** Type of blk0_backup3_w1 register
- *  Otp debuger block0 data register12.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word1 data.
-         */
-        uint32_t block0_backup3_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word2 Data */
-/** Type of blk0_backup3_w2 register
- *  Otp debuger block0 data register13.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word2 data.
-         */
-        uint32_t block0_backup3_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word3 Data */
-/** Type of blk0_backup3_w3 register
- *  Otp debuger block0 data register14.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word3 data.
-         */
-        uint32_t block0_backup3_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word4 Data */
-/** Type of blk0_backup3_w4 register
- *  Otp debuger block0 data register15.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word4 data.
-         */
-        uint32_t block0_backup3_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup3 Word5 Data */
-/** Type of blk0_backup3_w5 register
- *  Otp debuger block0 data register16.
- */
-typedef union {
-    struct {
-        /** block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word5 data.
-         */
-        uint32_t block0_backup3_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup3_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word1 Data */
-/** Type of blk0_backup4_w1 register
- *  Otp debuger block0 data register17.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word1 data.
-         */
-        uint32_t block0_backup4_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word2 Data */
-/** Type of blk0_backup4_w2 register
- *  Otp debuger block0 data register18.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word2 data.
-         */
-        uint32_t block0_backup4_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word3 Data */
-/** Type of blk0_backup4_w3 register
- *  Otp debuger block0 data register19.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word3 data.
-         */
-        uint32_t block0_backup4_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word4 Data */
-/** Type of blk0_backup4_w4 register
- *  Otp debuger block0 data register20.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word4 data.
-         */
-        uint32_t block0_backup4_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block0 Backup4 Word5 Data */
-/** Type of blk0_backup4_w5 register
- *  Otp debuger block0 data register21.
- */
-typedef union {
-    struct {
-        /** block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word5 data.
-         */
-        uint32_t block0_backup4_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk0_backup4_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word1 Data */
-/** Type of blk1_w1 register
- *  Otp debuger block1 data register1.
- */
-typedef union {
-    struct {
-        /** block1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word1 data.
-         */
-        uint32_t block1_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word2 Data */
-/** Type of blk1_w2 register
- *  Otp debuger block1 data register2.
- */
-typedef union {
-    struct {
-        /** block1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word2 data.
-         */
-        uint32_t block1_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word3 Data */
-/** Type of blk1_w3 register
- *  Otp debuger block1 data register3.
- */
-typedef union {
-    struct {
-        /** block1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word3 data.
-         */
-        uint32_t block1_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word4 Data */
-/** Type of blk1_w4 register
- *  Otp debuger block1 data register4.
- */
-typedef union {
-    struct {
-        /** block1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word4 data.
-         */
-        uint32_t block1_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word5 Data */
-/** Type of blk1_w5 register
- *  Otp debuger block1 data register5.
- */
-typedef union {
-    struct {
-        /** block1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word5 data.
-         */
-        uint32_t block1_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word6 Data */
-/** Type of blk1_w6 register
- *  Otp debuger block1 data register6.
- */
-typedef union {
-    struct {
-        /** block1_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word6 data.
-         */
-        uint32_t block1_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word7 Data */
-/** Type of blk1_w7 register
- *  Otp debuger block1 data register7.
- */
-typedef union {
-    struct {
-        /** block1_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word7 data.
-         */
-        uint32_t block1_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word8 Data */
-/** Type of blk1_w8 register
- *  Otp debuger block1 data register8.
- */
-typedef union {
-    struct {
-        /** block1_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word8 data.
-         */
-        uint32_t block1_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block1 Word9 Data */
-/** Type of blk1_w9 register
- *  Otp debuger block1 data register9.
- */
-typedef union {
-    struct {
-        /** block1_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word9 data.
-         */
-        uint32_t block1_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk1_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word1 Data */
-/** Type of blk2_w1 register
- *  Otp debuger block2 data register1.
- */
-typedef union {
-    struct {
-        /** block2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word1 data.
-         */
-        uint32_t block2_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word2 Data */
-/** Type of blk2_w2 register
- *  Otp debuger block2 data register2.
- */
-typedef union {
-    struct {
-        /** block2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word2 data.
-         */
-        uint32_t block2_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word3 Data */
-/** Type of blk2_w3 register
- *  Otp debuger block2 data register3.
- */
-typedef union {
-    struct {
-        /** block2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word3 data.
-         */
-        uint32_t block2_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word4 Data */
-/** Type of blk2_w4 register
- *  Otp debuger block2 data register4.
- */
-typedef union {
-    struct {
-        /** block2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word4 data.
-         */
-        uint32_t block2_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word5 Data */
-/** Type of blk2_w5 register
- *  Otp debuger block2 data register5.
- */
-typedef union {
-    struct {
-        /** block2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word5 data.
-         */
-        uint32_t block2_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word6 Data */
-/** Type of blk2_w6 register
- *  Otp debuger block2 data register6.
- */
-typedef union {
-    struct {
-        /** block2_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word6 data.
-         */
-        uint32_t block2_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word7 Data */
-/** Type of blk2_w7 register
- *  Otp debuger block2 data register7.
- */
-typedef union {
-    struct {
-        /** block2_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word7 data.
-         */
-        uint32_t block2_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word8 Data */
-/** Type of blk2_w8 register
- *  Otp debuger block2 data register8.
- */
-typedef union {
-    struct {
-        /** block2_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word8 data.
-         */
-        uint32_t block2_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word9 Data */
-/** Type of blk2_w9 register
- *  Otp debuger block2 data register9.
- */
-typedef union {
-    struct {
-        /** block2_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word9 data.
-         */
-        uint32_t block2_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word10 Data */
-/** Type of blk2_w10 register
- *  Otp debuger block2 data register10.
- */
-typedef union {
-    struct {
-        /** block2_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word10 data.
-         */
-        uint32_t block2_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block2 Word11 Data */
-/** Type of blk2_w11 register
- *  Otp debuger block2 data register11.
- */
-typedef union {
-    struct {
-        /** block2_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word11 data.
-         */
-        uint32_t block2_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk2_w11_reg_t;
-
-/** Type of blk10_w11 register
- *  Otp debuger block10 data register11.
- */
-typedef union {
-    struct {
-        /** block10_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word11 data.
-         */
-        uint32_t block10_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word1 Data */
-/** Type of blk3_w1 register
- *  Otp debuger block3 data register1.
- */
-typedef union {
-    struct {
-        /** block3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word1 data.
-         */
-        uint32_t block3_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word2 Data */
-/** Type of blk3_w2 register
- *  Otp debuger block3 data register2.
- */
-typedef union {
-    struct {
-        /** block3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word2 data.
-         */
-        uint32_t block3_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word3 Data */
-/** Type of blk3_w3 register
- *  Otp debuger block3 data register3.
- */
-typedef union {
-    struct {
-        /** block3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word3 data.
-         */
-        uint32_t block3_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word4 Data */
-/** Type of blk3_w4 register
- *  Otp debuger block3 data register4.
- */
-typedef union {
-    struct {
-        /** block3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word4 data.
-         */
-        uint32_t block3_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word5 Data */
-/** Type of blk3_w5 register
- *  Otp debuger block3 data register5.
- */
-typedef union {
-    struct {
-        /** block3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word5 data.
-         */
-        uint32_t block3_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word6 Data */
-/** Type of blk3_w6 register
- *  Otp debuger block3 data register6.
- */
-typedef union {
-    struct {
-        /** block3_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word6 data.
-         */
-        uint32_t block3_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word7 Data */
-/** Type of blk3_w7 register
- *  Otp debuger block3 data register7.
- */
-typedef union {
-    struct {
-        /** block3_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word7 data.
-         */
-        uint32_t block3_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word8 Data */
-/** Type of blk3_w8 register
- *  Otp debuger block3 data register8.
- */
-typedef union {
-    struct {
-        /** block3_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word8 data.
-         */
-        uint32_t block3_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word9 Data */
-/** Type of blk3_w9 register
- *  Otp debuger block3 data register9.
- */
-typedef union {
-    struct {
-        /** block3_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word9 data.
-         */
-        uint32_t block3_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word10 Data */
-/** Type of blk3_w10 register
- *  Otp debuger block3 data register10.
- */
-typedef union {
-    struct {
-        /** block3_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word10 data.
-         */
-        uint32_t block3_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block3 Word11 Data */
-/** Type of blk3_w11 register
- *  Otp debuger block3 data register11.
- */
-typedef union {
-    struct {
-        /** block3_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word11 data.
-         */
-        uint32_t block3_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk3_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word1 Data */
-/** Type of blk4_w1 register
- *  Otp debuger block4 data register1.
- */
-typedef union {
-    struct {
-        /** block4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word1 data.
-         */
-        uint32_t block4_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word2 Data */
-/** Type of blk4_w2 register
- *  Otp debuger block4 data register2.
- */
-typedef union {
-    struct {
-        /** block4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word2 data.
-         */
-        uint32_t block4_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word3 Data */
-/** Type of blk4_w3 register
- *  Otp debuger block4 data register3.
- */
-typedef union {
-    struct {
-        /** block4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word3 data.
-         */
-        uint32_t block4_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word4 Data */
-/** Type of blk4_w4 register
- *  Otp debuger block4 data register4.
- */
-typedef union {
-    struct {
-        /** block4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word4 data.
-         */
-        uint32_t block4_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word5 Data */
-/** Type of blk4_w5 register
- *  Otp debuger block4 data register5.
- */
-typedef union {
-    struct {
-        /** block4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word5 data.
-         */
-        uint32_t block4_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word6 Data */
-/** Type of blk4_w6 register
- *  Otp debuger block4 data register6.
- */
-typedef union {
-    struct {
-        /** block4_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word6 data.
-         */
-        uint32_t block4_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word7 Data */
-/** Type of blk4_w7 register
- *  Otp debuger block4 data register7.
- */
-typedef union {
-    struct {
-        /** block4_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word7 data.
-         */
-        uint32_t block4_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word8 Data */
-/** Type of blk4_w8 register
- *  Otp debuger block4 data register8.
- */
-typedef union {
-    struct {
-        /** block4_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word8 data.
-         */
-        uint32_t block4_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word9 Data */
-/** Type of blk4_w9 register
- *  Otp debuger block4 data register9.
- */
-typedef union {
-    struct {
-        /** block4_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word9 data.
-         */
-        uint32_t block4_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word10 Data */
-/** Type of blk4_w10 register
- *  Otp debuger block4 data registe10.
- */
-typedef union {
-    struct {
-        /** block4_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word10 data.
-         */
-        uint32_t block4_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block4 Word11 Data */
-/** Type of blk4_w11 register
- *  Otp debuger block4 data register11.
- */
-typedef union {
-    struct {
-        /** block4_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word11 data.
-         */
-        uint32_t block4_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk4_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word1 Data */
-/** Type of blk5_w1 register
- *  Otp debuger block5 data register1.
- */
-typedef union {
-    struct {
-        /** block5_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word1 data.
-         */
-        uint32_t block5_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word2 Data */
-/** Type of blk5_w2 register
- *  Otp debuger block5 data register2.
- */
-typedef union {
-    struct {
-        /** block5_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word2 data.
-         */
-        uint32_t block5_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word3 Data */
-/** Type of blk5_w3 register
- *  Otp debuger block5 data register3.
- */
-typedef union {
-    struct {
-        /** block5_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word3 data.
-         */
-        uint32_t block5_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word4 Data */
-/** Type of blk5_w4 register
- *  Otp debuger block5 data register4.
- */
-typedef union {
-    struct {
-        /** block5_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word4 data.
-         */
-        uint32_t block5_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word5 Data */
-/** Type of blk5_w5 register
- *  Otp debuger block5 data register5.
- */
-typedef union {
-    struct {
-        /** block5_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word5 data.
-         */
-        uint32_t block5_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word6 Data */
-/** Type of blk5_w6 register
- *  Otp debuger block5 data register6.
- */
-typedef union {
-    struct {
-        /** block5_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word6 data.
-         */
-        uint32_t block5_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word7 Data */
-/** Type of blk5_w7 register
- *  Otp debuger block5 data register7.
- */
-typedef union {
-    struct {
-        /** block5_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word7 data.
-         */
-        uint32_t block5_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word8 Data */
-/** Type of blk5_w8 register
- *  Otp debuger block5 data register8.
- */
-typedef union {
-    struct {
-        /** block5_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word8 data.
-         */
-        uint32_t block5_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word9 Data */
-/** Type of blk5_w9 register
- *  Otp debuger block5 data register9.
- */
-typedef union {
-    struct {
-        /** block5_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word9 data.
-         */
-        uint32_t block5_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word10 Data */
-/** Type of blk5_w10 register
- *  Otp debuger block5 data register10.
- */
-typedef union {
-    struct {
-        /** block5_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word10 data.
-         */
-        uint32_t block5_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block5 Word11 Data */
-/** Type of blk5_w11 register
- *  Otp debuger block5 data register11.
- */
-typedef union {
-    struct {
-        /** block5_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word11 data.
-         */
-        uint32_t block5_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk5_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word1 Data */
-/** Type of blk6_w1 register
- *  Otp debuger block6 data register1.
- */
-typedef union {
-    struct {
-        /** block6_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word1 data.
-         */
-        uint32_t block6_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word2 Data */
-/** Type of blk6_w2 register
- *  Otp debuger block6 data register2.
- */
-typedef union {
-    struct {
-        /** block6_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word2 data.
-         */
-        uint32_t block6_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word3 Data */
-/** Type of blk6_w3 register
- *  Otp debuger block6 data register3.
- */
-typedef union {
-    struct {
-        /** block6_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word3 data.
-         */
-        uint32_t block6_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word4 Data */
-/** Type of blk6_w4 register
- *  Otp debuger block6 data register4.
- */
-typedef union {
-    struct {
-        /** block6_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word4 data.
-         */
-        uint32_t block6_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word5 Data */
-/** Type of blk6_w5 register
- *  Otp debuger block6 data register5.
- */
-typedef union {
-    struct {
-        /** block6_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word5 data.
-         */
-        uint32_t block6_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word6 Data */
-/** Type of blk6_w6 register
- *  Otp debuger block6 data register6.
- */
-typedef union {
-    struct {
-        /** block6_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word6 data.
-         */
-        uint32_t block6_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word7 Data */
-/** Type of blk6_w7 register
- *  Otp debuger block6 data register7.
- */
-typedef union {
-    struct {
-        /** block6_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word7 data.
-         */
-        uint32_t block6_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word8 Data */
-/** Type of blk6_w8 register
- *  Otp debuger block6 data register8.
- */
-typedef union {
-    struct {
-        /** block6_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word8 data.
-         */
-        uint32_t block6_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word9 Data */
-/** Type of blk6_w9 register
- *  Otp debuger block6 data register9.
- */
-typedef union {
-    struct {
-        /** block6_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word9 data.
-         */
-        uint32_t block6_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word10 Data */
-/** Type of blk6_w10 register
- *  Otp debuger block6 data register10.
- */
-typedef union {
-    struct {
-        /** block6_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word10 data.
-         */
-        uint32_t block6_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block6 Word11 Data */
-/** Type of blk6_w11 register
- *  Otp debuger block6 data register11.
- */
-typedef union {
-    struct {
-        /** block6_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word11 data.
-         */
-        uint32_t block6_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk6_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word1 Data */
-/** Type of blk7_w1 register
- *  Otp debuger block7 data register1.
- */
-typedef union {
-    struct {
-        /** block7_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word1 data.
-         */
-        uint32_t block7_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word2 Data */
-/** Type of blk7_w2 register
- *  Otp debuger block7 data register2.
- */
-typedef union {
-    struct {
-        /** block7_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word2 data.
-         */
-        uint32_t block7_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word3 Data */
-/** Type of blk7_w3 register
- *  Otp debuger block7 data register3.
- */
-typedef union {
-    struct {
-        /** block7_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word3 data.
-         */
-        uint32_t block7_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word4 Data */
-/** Type of blk7_w4 register
- *  Otp debuger block7 data register4.
- */
-typedef union {
-    struct {
-        /** block7_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word4 data.
-         */
-        uint32_t block7_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word5 Data */
-/** Type of blk7_w5 register
- *  Otp debuger block7 data register5.
- */
-typedef union {
-    struct {
-        /** block7_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word5 data.
-         */
-        uint32_t block7_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word6 Data */
-/** Type of blk7_w6 register
- *  Otp debuger block7 data register6.
- */
-typedef union {
-    struct {
-        /** block7_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word6 data.
-         */
-        uint32_t block7_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word7 Data */
-/** Type of blk7_w7 register
- *  Otp debuger block7 data register7.
- */
-typedef union {
-    struct {
-        /** block7_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word7 data.
-         */
-        uint32_t block7_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word8 Data */
-/** Type of blk7_w8 register
- *  Otp debuger block7 data register8.
- */
-typedef union {
-    struct {
-        /** block7_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word8 data.
-         */
-        uint32_t block7_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word9 Data */
-/** Type of blk7_w9 register
- *  Otp debuger block7 data register9.
- */
-typedef union {
-    struct {
-        /** block7_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word9 data.
-         */
-        uint32_t block7_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word10 Data */
-/** Type of blk7_w10 register
- *  Otp debuger block7 data register10.
- */
-typedef union {
-    struct {
-        /** block7_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word10 data.
-         */
-        uint32_t block7_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block7 Word11 Data */
-/** Type of blk7_w11 register
- *  Otp debuger block7 data register11.
- */
-typedef union {
-    struct {
-        /** block7_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word11 data.
-         */
-        uint32_t block7_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk7_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word1 Data */
-/** Type of blk8_w1 register
- *  Otp debuger block8 data register1.
- */
-typedef union {
-    struct {
-        /** block8_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word1 data.
-         */
-        uint32_t block8_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word2 Data */
-/** Type of blk8_w2 register
- *  Otp debuger block8 data register2.
- */
-typedef union {
-    struct {
-        /** block8_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word2 data.
-         */
-        uint32_t block8_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word3 Data */
-/** Type of blk8_w3 register
- *  Otp debuger block8 data register3.
- */
-typedef union {
-    struct {
-        /** block8_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word3 data.
-         */
-        uint32_t block8_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word4 Data */
-/** Type of blk8_w4 register
- *  Otp debuger block8 data register4.
- */
-typedef union {
-    struct {
-        /** block8_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word4 data.
-         */
-        uint32_t block8_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word5 Data */
-/** Type of blk8_w5 register
- *  Otp debuger block8 data register5.
- */
-typedef union {
-    struct {
-        /** block8_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word5 data.
-         */
-        uint32_t block8_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word6 Data */
-/** Type of blk8_w6 register
- *  Otp debuger block8 data register6.
- */
-typedef union {
-    struct {
-        /** block8_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word6 data.
-         */
-        uint32_t block8_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word7 Data */
-/** Type of blk8_w7 register
- *  Otp debuger block8 data register7.
- */
-typedef union {
-    struct {
-        /** block8_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word7 data.
-         */
-        uint32_t block8_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word8 Data */
-/** Type of blk8_w8 register
- *  Otp debuger block8 data register8.
- */
-typedef union {
-    struct {
-        /** block8_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word8 data.
-         */
-        uint32_t block8_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word9 Data */
-/** Type of blk8_w9 register
- *  Otp debuger block8 data register9.
- */
-typedef union {
-    struct {
-        /** block8_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word9 data.
-         */
-        uint32_t block8_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word10 Data */
-/** Type of blk8_w10 register
- *  Otp debuger block8 data register10.
- */
-typedef union {
-    struct {
-        /** block8_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word10 data.
-         */
-        uint32_t block8_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block8 Word11 Data */
-/** Type of blk8_w11 register
- *  Otp debuger block8 data register11.
- */
-typedef union {
-    struct {
-        /** block8_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word11 data.
-         */
-        uint32_t block8_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk8_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word1 Data */
-/** Type of blk9_w1 register
- *  Otp debuger block9 data register1.
- */
-typedef union {
-    struct {
-        /** block9_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word1 data.
-         */
-        uint32_t block9_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word2 Data */
-/** Type of blk9_w2 register
- *  Otp debuger block9 data register2.
- */
-typedef union {
-    struct {
-        /** block9_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word2 data.
-         */
-        uint32_t block9_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word3 Data */
-/** Type of blk9_w3 register
- *  Otp debuger block9 data register3.
- */
-typedef union {
-    struct {
-        /** block9_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word3 data.
-         */
-        uint32_t block9_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word4 Data */
-/** Type of blk9_w4 register
- *  Otp debuger block9 data register4.
- */
-typedef union {
-    struct {
-        /** block9_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word4 data.
-         */
-        uint32_t block9_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word5 Data */
-/** Type of blk9_w5 register
- *  Otp debuger block9 data register5.
- */
-typedef union {
-    struct {
-        /** block9_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word5 data.
-         */
-        uint32_t block9_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word6 Data */
-/** Type of blk9_w6 register
- *  Otp debuger block9 data register6.
- */
-typedef union {
-    struct {
-        /** block9_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word6 data.
-         */
-        uint32_t block9_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word7 Data */
-/** Type of blk9_w7 register
- *  Otp debuger block9 data register7.
- */
-typedef union {
-    struct {
-        /** block9_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word7 data.
-         */
-        uint32_t block9_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word8 Data */
-/** Type of blk9_w8 register
- *  Otp debuger block9 data register8.
- */
-typedef union {
-    struct {
-        /** block9_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word8 data.
-         */
-        uint32_t block9_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word9 Data */
-/** Type of blk9_w9 register
- *  Otp debuger block9 data register9.
- */
-typedef union {
-    struct {
-        /** block9_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word9 data.
-         */
-        uint32_t block9_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word10 Data */
-/** Type of blk9_w10 register
- *  Otp debuger block9 data register10.
- */
-typedef union {
-    struct {
-        /** block9_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word10 data.
-         */
-        uint32_t block9_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Block9 Word11 Data */
-/** Type of blk9_w11 register
- *  Otp debuger block9 data register11.
- */
-typedef union {
-    struct {
-        /** block9_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word11 data.
-         */
-        uint32_t block9_w11:32;
-    };
-    uint32_t val;
-} otp_debug_blk9_w11_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word1 Data */
-/** Type of blk10_w1 register
- *  Otp debuger block10 data register1.
- */
-typedef union {
-    struct {
-        /** block10_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word1 data.
-         */
-        uint32_t block10_w1:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w1_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word2 Data */
-/** Type of blk10_w2 register
- *  Otp debuger block10 data register2.
- */
-typedef union {
-    struct {
-        /** block10_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word2 data.
-         */
-        uint32_t block10_w2:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w2_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word3 Data */
-/** Type of blk10_w3 register
- *  Otp debuger block10 data register3.
- */
-typedef union {
-    struct {
-        /** block10_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word3 data.
-         */
-        uint32_t block10_w3:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w3_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word4 Data */
-/** Type of blk10_w4 register
- *  Otp debuger block10 data register4.
- */
-typedef union {
-    struct {
-        /** block10_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word4 data.
-         */
-        uint32_t block10_w4:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w4_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word5 Data */
-/** Type of blk10_w5 register
- *  Otp debuger block10 data register5.
- */
-typedef union {
-    struct {
-        /** block10_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word5 data.
-         */
-        uint32_t block10_w5:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w5_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word6 Data */
-/** Type of blk10_w6 register
- *  Otp debuger block10 data register6.
- */
-typedef union {
-    struct {
-        /** block10_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word6 data.
-         */
-        uint32_t block10_w6:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w6_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word7 Data */
-/** Type of blk10_w7 register
- *  Otp debuger block10 data register7.
- */
-typedef union {
-    struct {
-        /** block10_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word7 data.
-         */
-        uint32_t block10_w7:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w7_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word8 Data */
-/** Type of blk10_w8 register
- *  Otp debuger block10 data register8.
- */
-typedef union {
-    struct {
-        /** block10_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word8 data.
-         */
-        uint32_t block10_w8:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w8_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word9 Data */
-/** Type of blk10_w9 register
- *  Otp debuger block10 data register9.
- */
-typedef union {
-    struct {
-        /** block10_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word9 data.
-         */
-        uint32_t block10_w9:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w9_reg_t;
-
-
-/** Group: OTP_DEBUG Block10 Word10 Data */
-/** Type of blk10_w10 register
- *  Otp debuger block10 data register10.
- */
-typedef union {
-    struct {
-        /** block19_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word10 data.
-         */
-        uint32_t block19_w10:32;
-    };
-    uint32_t val;
-} otp_debug_blk10_w10_reg_t;
-
-
-/** Group: OTP_DEBUG Clock_en Configuration Register */
-/** Type of clk register
- *  Otp debuger clk_en configuration register.
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Force clock on for this register file.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} otp_debug_clk_reg_t;
-
-
-/** Group: OTP_DEBUG Apb2otp Enable Singal */
-/** Type of apb2otp_en register
- *  Otp_debuger apb2otp enable configuration register.
- */
-typedef union {
-    struct {
-        /** apb2otp_en : R/W; bitpos: [0]; default: 0;
-         *  Debug mode enable signal.
-         */
-        uint32_t apb2otp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} otp_debug_apb2otp_en_reg_t;
-
-
-/** Group: OTP_DEBUG Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 539037736;
-         *  Stores otp_debug version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} otp_debug_date_reg_t;
-
-
-typedef struct otp_debug_dev_t {
-    volatile otp_debug_wr_dis_reg_t wr_dis;
-    volatile otp_debug_blk0_backup1_w1_reg_t blk0_backup1_w1;
-    volatile otp_debug_blk0_backup1_w2_reg_t blk0_backup1_w2;
-    volatile otp_debug_blk0_backup1_w3_reg_t blk0_backup1_w3;
-    volatile otp_debug_blk0_backup1_w4_reg_t blk0_backup1_w4;
-    volatile otp_debug_blk0_backup1_w5_reg_t blk0_backup1_w5;
-    volatile otp_debug_blk0_backup2_w1_reg_t blk0_backup2_w1;
-    volatile otp_debug_blk0_backup2_w2_reg_t blk0_backup2_w2;
-    volatile otp_debug_blk0_backup2_w3_reg_t blk0_backup2_w3;
-    volatile otp_debug_blk0_backup2_w4_reg_t blk0_backup2_w4;
-    volatile otp_debug_blk0_backup2_w5_reg_t blk0_backup2_w5;
-    volatile otp_debug_blk0_backup3_w1_reg_t blk0_backup3_w1;
-    volatile otp_debug_blk0_backup3_w2_reg_t blk0_backup3_w2;
-    volatile otp_debug_blk0_backup3_w3_reg_t blk0_backup3_w3;
-    volatile otp_debug_blk0_backup3_w4_reg_t blk0_backup3_w4;
-    volatile otp_debug_blk0_backup3_w5_reg_t blk0_backup3_w5;
-    volatile otp_debug_blk0_backup4_w1_reg_t blk0_backup4_w1;
-    volatile otp_debug_blk0_backup4_w2_reg_t blk0_backup4_w2;
-    volatile otp_debug_blk0_backup4_w3_reg_t blk0_backup4_w3;
-    volatile otp_debug_blk0_backup4_w4_reg_t blk0_backup4_w4;
-    volatile otp_debug_blk0_backup4_w5_reg_t blk0_backup4_w5;
-    volatile otp_debug_blk1_w1_reg_t blk1_w1;
-    volatile otp_debug_blk1_w2_reg_t blk1_w2;
-    volatile otp_debug_blk1_w3_reg_t blk1_w3;
-    volatile otp_debug_blk1_w4_reg_t blk1_w4;
-    volatile otp_debug_blk1_w5_reg_t blk1_w5;
-    volatile otp_debug_blk1_w6_reg_t blk1_w6;
-    volatile otp_debug_blk1_w7_reg_t blk1_w7;
-    volatile otp_debug_blk1_w8_reg_t blk1_w8;
-    volatile otp_debug_blk1_w9_reg_t blk1_w9;
-    volatile otp_debug_blk2_w1_reg_t blk2_w1;
-    volatile otp_debug_blk2_w2_reg_t blk2_w2;
-    volatile otp_debug_blk2_w3_reg_t blk2_w3;
-    volatile otp_debug_blk2_w4_reg_t blk2_w4;
-    volatile otp_debug_blk2_w5_reg_t blk2_w5;
-    volatile otp_debug_blk2_w6_reg_t blk2_w6;
-    volatile otp_debug_blk2_w7_reg_t blk2_w7;
-    volatile otp_debug_blk2_w8_reg_t blk2_w8;
-    volatile otp_debug_blk2_w9_reg_t blk2_w9;
-    volatile otp_debug_blk2_w10_reg_t blk2_w10;
-    volatile otp_debug_blk2_w11_reg_t blk2_w11;
-    volatile otp_debug_blk3_w1_reg_t blk3_w1;
-    volatile otp_debug_blk3_w2_reg_t blk3_w2;
-    volatile otp_debug_blk3_w3_reg_t blk3_w3;
-    volatile otp_debug_blk3_w4_reg_t blk3_w4;
-    volatile otp_debug_blk3_w5_reg_t blk3_w5;
-    volatile otp_debug_blk3_w6_reg_t blk3_w6;
-    volatile otp_debug_blk3_w7_reg_t blk3_w7;
-    volatile otp_debug_blk3_w8_reg_t blk3_w8;
-    volatile otp_debug_blk3_w9_reg_t blk3_w9;
-    volatile otp_debug_blk3_w10_reg_t blk3_w10;
-    volatile otp_debug_blk3_w11_reg_t blk3_w11;
-    volatile otp_debug_blk4_w1_reg_t blk4_w1;
-    volatile otp_debug_blk4_w2_reg_t blk4_w2;
-    volatile otp_debug_blk4_w3_reg_t blk4_w3;
-    volatile otp_debug_blk4_w4_reg_t blk4_w4;
-    volatile otp_debug_blk4_w5_reg_t blk4_w5;
-    volatile otp_debug_blk4_w6_reg_t blk4_w6;
-    volatile otp_debug_blk4_w7_reg_t blk4_w7;
-    volatile otp_debug_blk4_w8_reg_t blk4_w8;
-    volatile otp_debug_blk4_w9_reg_t blk4_w9;
-    volatile otp_debug_blk4_w10_reg_t blk4_w10;
-    volatile otp_debug_blk4_w11_reg_t blk4_w11;
-    volatile otp_debug_blk5_w1_reg_t blk5_w1;
-    volatile otp_debug_blk5_w2_reg_t blk5_w2;
-    volatile otp_debug_blk5_w3_reg_t blk5_w3;
-    volatile otp_debug_blk5_w4_reg_t blk5_w4;
-    volatile otp_debug_blk5_w5_reg_t blk5_w5;
-    volatile otp_debug_blk5_w6_reg_t blk5_w6;
-    volatile otp_debug_blk5_w7_reg_t blk5_w7;
-    volatile otp_debug_blk5_w8_reg_t blk5_w8;
-    volatile otp_debug_blk5_w9_reg_t blk5_w9;
-    volatile otp_debug_blk5_w10_reg_t blk5_w10;
-    volatile otp_debug_blk5_w11_reg_t blk5_w11;
-    volatile otp_debug_blk6_w1_reg_t blk6_w1;
-    volatile otp_debug_blk6_w2_reg_t blk6_w2;
-    volatile otp_debug_blk6_w3_reg_t blk6_w3;
-    volatile otp_debug_blk6_w4_reg_t blk6_w4;
-    volatile otp_debug_blk6_w5_reg_t blk6_w5;
-    volatile otp_debug_blk6_w6_reg_t blk6_w6;
-    volatile otp_debug_blk6_w7_reg_t blk6_w7;
-    volatile otp_debug_blk6_w8_reg_t blk6_w8;
-    volatile otp_debug_blk6_w9_reg_t blk6_w9;
-    volatile otp_debug_blk6_w10_reg_t blk6_w10;
-    volatile otp_debug_blk6_w11_reg_t blk6_w11;
-    volatile otp_debug_blk7_w1_reg_t blk7_w1;
-    volatile otp_debug_blk7_w2_reg_t blk7_w2;
-    volatile otp_debug_blk7_w3_reg_t blk7_w3;
-    volatile otp_debug_blk7_w4_reg_t blk7_w4;
-    volatile otp_debug_blk7_w5_reg_t blk7_w5;
-    volatile otp_debug_blk7_w6_reg_t blk7_w6;
-    volatile otp_debug_blk7_w7_reg_t blk7_w7;
-    volatile otp_debug_blk7_w8_reg_t blk7_w8;
-    volatile otp_debug_blk7_w9_reg_t blk7_w9;
-    volatile otp_debug_blk7_w10_reg_t blk7_w10;
-    volatile otp_debug_blk7_w11_reg_t blk7_w11;
-    volatile otp_debug_blk8_w1_reg_t blk8_w1;
-    volatile otp_debug_blk8_w2_reg_t blk8_w2;
-    volatile otp_debug_blk8_w3_reg_t blk8_w3;
-    volatile otp_debug_blk8_w4_reg_t blk8_w4;
-    volatile otp_debug_blk8_w5_reg_t blk8_w5;
-    volatile otp_debug_blk8_w6_reg_t blk8_w6;
-    volatile otp_debug_blk8_w7_reg_t blk8_w7;
-    volatile otp_debug_blk8_w8_reg_t blk8_w8;
-    volatile otp_debug_blk8_w9_reg_t blk8_w9;
-    volatile otp_debug_blk8_w10_reg_t blk8_w10;
-    volatile otp_debug_blk8_w11_reg_t blk8_w11;
-    volatile otp_debug_blk9_w1_reg_t blk9_w1;
-    volatile otp_debug_blk9_w2_reg_t blk9_w2;
-    volatile otp_debug_blk9_w3_reg_t blk9_w3;
-    volatile otp_debug_blk9_w4_reg_t blk9_w4;
-    volatile otp_debug_blk9_w5_reg_t blk9_w5;
-    volatile otp_debug_blk9_w6_reg_t blk9_w6;
-    volatile otp_debug_blk9_w7_reg_t blk9_w7;
-    volatile otp_debug_blk9_w8_reg_t blk9_w8;
-    volatile otp_debug_blk9_w9_reg_t blk9_w9;
-    volatile otp_debug_blk9_w10_reg_t blk9_w10;
-    volatile otp_debug_blk9_w11_reg_t blk9_w11;
-    volatile otp_debug_blk10_w1_reg_t blk10_w1;
-    volatile otp_debug_blk10_w2_reg_t blk10_w2;
-    volatile otp_debug_blk10_w3_reg_t blk10_w3;
-    volatile otp_debug_blk10_w4_reg_t blk10_w4;
-    volatile otp_debug_blk10_w5_reg_t blk10_w5;
-    volatile otp_debug_blk10_w6_reg_t blk10_w6;
-    volatile otp_debug_blk10_w7_reg_t blk10_w7;
-    volatile otp_debug_blk10_w8_reg_t blk10_w8;
-    volatile otp_debug_blk10_w9_reg_t blk10_w9;
-    volatile otp_debug_blk10_w10_reg_t blk10_w10;
-    volatile otp_debug_blk10_w11_reg_t blk10_w11;
-    volatile otp_debug_clk_reg_t clk;
-    volatile otp_debug_apb2otp_en_reg_t apb2otp_en;
-    volatile otp_debug_date_reg_t date;
-} otp_debug_dev_t;
-
-extern otp_debug_dev_t OTP_DEBUG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(otp_debug_dev_t) == 0x210, "Invalid size of otp_debug_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/parl_io_reg.h b/components/soc/esp32c5/beta3/include/soc/parl_io_reg.h
deleted file mode 100644
index 74a528017d..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/parl_io_reg.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PARL_IO_RX_MODE_CFG_REG register
- *  Parallel RX Sampling mode configuration register.
- */
-#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
-/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
- *  Configures rx external enable signal selection from IO PAD.
- */
-#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
-#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_S  21
-/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
- *  Set this bit to enable data sampling by software.
- */
-#define PARL_IO_RX_SW_EN    (BIT(25))
-#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
-#define PARL_IO_RX_SW_EN_V  0x00000001U
-#define PARL_IO_RX_SW_EN_S  25
-/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
- *  Set this bit to invert the external enable signal.
- */
-#define PARL_IO_RX_EXT_EN_INV    (BIT(26))
-#define PARL_IO_RX_EXT_EN_INV_M  (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
-#define PARL_IO_RX_EXT_EN_INV_V  0x00000001U
-#define PARL_IO_RX_EXT_EN_INV_S  26
-/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
- *  Configures the rxd pulse sampling submode.
- *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
- *  included)
- *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
- *  excluded)
- *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  included)
- *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  excluded)
- *  4'd4: positive pulse start(data bit included) && length end
- *  4'd5: positive pulse start(data bit excluded) && length end
- */
-#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x00000007U
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x00000007U
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  27
-/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
- *  Configures the rxd sampling mode.
- *  2'b00: external level enable mode
- *  2'b01: external pulse enable mode
- *  2'b10: internal software enable mode
- */
-#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
-#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_S  30
-
-/** PARL_IO_RX_DATA_CFG_REG register
- *  Parallel RX data configuration register.
- */
-#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
-/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
- *  Configures expected byte number of received data.
- */
-#define PARL_IO_RX_BITLEN    0x0007FFFFU
-#define PARL_IO_RX_BITLEN_M  (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
-#define PARL_IO_RX_BITLEN_V  0x0007FFFFU
-#define PARL_IO_RX_BITLEN_S  9
-/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
- *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
- */
-#define PARL_IO_RX_DATA_ORDER_INV    (BIT(28))
-#define PARL_IO_RX_DATA_ORDER_INV_M  (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
-#define PARL_IO_RX_DATA_ORDER_INV_V  0x00000001U
-#define PARL_IO_RX_DATA_ORDER_INV_S  28
-/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
- *  Configures the rxd bus width.
- *  3'd0: bus width is 1.
- *  3'd1: bus width is 2.
- *  3'd2: bus width is 4.
- *  3'd3: bus width is 8.
- */
-#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
-#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_S  29
-
-/** PARL_IO_RX_GENRL_CFG_REG register
- *  Parallel RX general configuration register.
- */
-#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
-/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable the clock gating of output rx clock.
- */
-#define PARL_IO_RX_GATING_EN    (BIT(12))
-#define PARL_IO_RX_GATING_EN_M  (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
-#define PARL_IO_RX_GATING_EN_V  0x00000001U
-#define PARL_IO_RX_GATING_EN_S  12
-/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
- *  Configures threshold of timeout counter.
- */
-#define PARL_IO_RX_TIMEOUT_THRES    0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRES_M  (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
-#define PARL_IO_RX_TIMEOUT_THRES_V  0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRES_S  13
-/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
- *  Set this bit to enable timeout function to generate error eof.
- */
-#define PARL_IO_RX_TIMEOUT_EN    (BIT(29))
-#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
-#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
-#define PARL_IO_RX_TIMEOUT_EN_S  29
-/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
- *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
- *  1'b1: eof generated by external enable signal.
- */
-#define PARL_IO_RX_EOF_GEN_SEL    (BIT(30))
-#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
-#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
-#define PARL_IO_RX_EOF_GEN_SEL_S  30
-
-/** PARL_IO_RX_START_CFG_REG register
- *  Parallel RX Start configuration register.
- */
-#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
-/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start rx data sampling.
- */
-#define PARL_IO_RX_START    (BIT(31))
-#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
-#define PARL_IO_RX_START_V  0x00000001U
-#define PARL_IO_RX_START_S  31
-
-/** PARL_IO_TX_DATA_CFG_REG register
- *  Parallel TX data configuration register.
- */
-#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
-/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
- *  Configures expected byte number of sent data.
- */
-#define PARL_IO_TX_BITLEN    0x0007FFFFU
-#define PARL_IO_TX_BITLEN_M  (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
-#define PARL_IO_TX_BITLEN_V  0x0007FFFFU
-#define PARL_IO_TX_BITLEN_S  9
-/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
- *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
- */
-#define PARL_IO_TX_DATA_ORDER_INV    (BIT(28))
-#define PARL_IO_TX_DATA_ORDER_INV_M  (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
-#define PARL_IO_TX_DATA_ORDER_INV_V  0x00000001U
-#define PARL_IO_TX_DATA_ORDER_INV_S  28
-/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
- *  Configures the txd bus width.
- *  3'd0: bus width is 1.
- *  3'd1: bus width is 2.
- *  3'd2: bus width is 4.
- *  3'd3: bus width is 8.
- */
-#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
-#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_S  29
-
-/** PARL_IO_TX_START_CFG_REG register
- *  Parallel TX Start configuration register.
- */
-#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
-/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start tx data transmit.
- */
-#define PARL_IO_TX_START    (BIT(31))
-#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
-#define PARL_IO_TX_START_V  0x00000001U
-#define PARL_IO_TX_START_S  31
-
-/** PARL_IO_TX_GENRL_CFG_REG register
- *  Parallel TX general configuration register.
- */
-#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
-/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
- *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
- *  1'b1: eof generated by DMA eof.
- */
-#define PARL_IO_TX_EOF_GEN_SEL    (BIT(13))
-#define PARL_IO_TX_EOF_GEN_SEL_M  (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
-#define PARL_IO_TX_EOF_GEN_SEL_V  0x00000001U
-#define PARL_IO_TX_EOF_GEN_SEL_S  13
-/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
- *  Configures bus value of transmitter in IDLE state.
- */
-#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
-#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_S  14
-/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
- *  Set this bit to enable the clock gating of output tx clock.
- */
-#define PARL_IO_TX_GATING_EN    (BIT(30))
-#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
-#define PARL_IO_TX_GATING_EN_V  0x00000001U
-#define PARL_IO_TX_GATING_EN_S  30
-/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
- *  Set this bit to enable the output of tx data valid signal.
- */
-#define PARL_IO_TX_VALID_OUTPUT_EN    (BIT(31))
-#define PARL_IO_TX_VALID_OUTPUT_EN_M  (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
-#define PARL_IO_TX_VALID_OUTPUT_EN_V  0x00000001U
-#define PARL_IO_TX_VALID_OUTPUT_EN_S  31
-
-/** PARL_IO_FIFO_CFG_REG register
- *  Parallel IO FIFO configuration register.
- */
-#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
-/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
- *  Set this bit to reset async fifo in tx module.
- */
-#define PARL_IO_TX_FIFO_SRST    (BIT(30))
-#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
-#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_TX_FIFO_SRST_S  30
-/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
- *  Set this bit to reset async fifo in rx module.
- */
-#define PARL_IO_RX_FIFO_SRST    (BIT(31))
-#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
-#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_RX_FIFO_SRST_S  31
-
-/** PARL_IO_REG_UPDATE_REG register
- *  Parallel IO FIFO configuration register.
- */
-#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
-/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
- *  Set this bit to update rx register configuration.
- */
-#define PARL_IO_RX_REG_UPDATE    (BIT(31))
-#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
-#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
-#define PARL_IO_RX_REG_UPDATE_S  31
-
-/** PARL_IO_ST_REG register
- *  Parallel IO module status register0.
- */
-#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
-/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
- *  Represents the status that tx is ready to transmit.
- */
-#define PARL_IO_TX_READY    (BIT(31))
-#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
-#define PARL_IO_TX_READY_V  0x00000001U
-#define PARL_IO_TX_READY_S  31
-
-/** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
- */
-#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M  (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S  1
-/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
-#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ENA_S  2
-
-/** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
- */
-#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
-/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status of TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status of RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M  (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S  1
-/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status of TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
-#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
-#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_RAW_S  2
-
-/** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
- */
-#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status of TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status of RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_ST    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_M  (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_S  1
-/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status of TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
-#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ST_S  2
-
-/** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
-/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M  (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S  1
-/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
-#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
-#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_CLR_S  2
-
-/** PARL_IO_RX_ST0_REG register
- *  Parallel IO RX status register0
- */
-#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
-/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
- *  Indicates the cycle number of reading Rx FIFO.
- */
-#define PARL_IO_RX_CNT    0x0000001FU
-#define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
-#define PARL_IO_RX_CNT_V  0x0000001FU
-#define PARL_IO_RX_CNT_S  8
-/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current written bit number into Rx FIFO.
- */
-#define PARL_IO_RX_FIFO_WR_BIT_CNT    0x0007FFFFU
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_M  (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_S  13
-
-/** PARL_IO_RX_ST1_REG register
- *  Parallel IO RX status register1
- */
-#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
-/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current read bit number from Rx FIFO.
- */
-#define PARL_IO_RX_FIFO_RD_BIT_CNT    0x0007FFFFU
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_M  (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_S  13
-
-/** PARL_IO_TX_ST0_REG register
- *  Parallel IO TX status register0
- */
-#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
-/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
- *  Indicates the cycle number of reading Tx FIFO.
- */
-#define PARL_IO_TX_CNT    0x0000007FU
-#define PARL_IO_TX_CNT_M  (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
-#define PARL_IO_TX_CNT_V  0x0000007FU
-#define PARL_IO_TX_CNT_S  6
-/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current read bit number from Tx FIFO.
- */
-#define PARL_IO_TX_FIFO_RD_BIT_CNT    0x0007FFFFU
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_M  (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_S  13
-
-/** PARL_IO_RX_CLK_CFG_REG register
- *  Parallel IO RX clk configuration register
- */
-#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
-/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
- *  Set this bit to invert the input Rx core clock.
- */
-#define PARL_IO_RX_CLK_I_INV    (BIT(30))
-#define PARL_IO_RX_CLK_I_INV_M  (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
-#define PARL_IO_RX_CLK_I_INV_V  0x00000001U
-#define PARL_IO_RX_CLK_I_INV_S  30
-/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
- *  Set this bit to invert the output Rx core clock.
- */
-#define PARL_IO_RX_CLK_O_INV    (BIT(31))
-#define PARL_IO_RX_CLK_O_INV_M  (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
-#define PARL_IO_RX_CLK_O_INV_V  0x00000001U
-#define PARL_IO_RX_CLK_O_INV_S  31
-
-/** PARL_IO_TX_CLK_CFG_REG register
- *  Parallel IO TX clk configuration register
- */
-#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
-/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
- *  Set this bit to invert the input Tx core clock.
- */
-#define PARL_IO_TX_CLK_I_INV    (BIT(30))
-#define PARL_IO_TX_CLK_I_INV_M  (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
-#define PARL_IO_TX_CLK_I_INV_V  0x00000001U
-#define PARL_IO_TX_CLK_I_INV_S  30
-/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
- *  Set this bit to invert the output Tx core clock.
- */
-#define PARL_IO_TX_CLK_O_INV    (BIT(31))
-#define PARL_IO_TX_CLK_O_INV_M  (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
-#define PARL_IO_TX_CLK_O_INV_V  0x00000001U
-#define PARL_IO_TX_CLK_O_INV_S  31
-
-/** PARL_IO_CLK_REG register
- *  Parallel IO clk configuration register
- */
-#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
-/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Force clock on for this register file
- */
-#define PARL_IO_CLK_EN    (BIT(31))
-#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
-#define PARL_IO_CLK_EN_V  0x00000001U
-#define PARL_IO_CLK_EN_S  31
-
-/** PARL_IO_VERSION_REG register
- *  Version register.
- */
-#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
-/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
- *  Version of this register file
- */
-#define PARL_IO_DATE    0x0FFFFFFFU
-#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
-#define PARL_IO_DATE_V  0x0FFFFFFFU
-#define PARL_IO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/parl_io_struct.h b/components/soc/esp32c5/beta3/include/soc/parl_io_struct.h
deleted file mode 100644
index aea2cb383b..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/parl_io_struct.h
+++ /dev/null
@@ -1,509 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PARL_IO RX  Mode Configuration */
-/** Type of rx_mode_cfg register
- *  Parallel RX Sampling mode configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
-         *  Configures rx external enable signal selection from IO PAD.
-         */
-        uint32_t rx_ext_en_sel:4;
-        /** rx_sw_en : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to enable data sampling by software.
-         */
-        uint32_t rx_sw_en:1;
-        /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to invert the external enable signal.
-         */
-        uint32_t rx_ext_en_inv:1;
-        /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
-         *  Configures the rxd pulse sampling submode.
-         *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
-         *  included)
-         *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
-         *  excluded)
-         *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  included)
-         *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  excluded)
-         *  4'd4: positive pulse start(data bit included) && length end
-         *  4'd5: positive pulse start(data bit excluded) && length end
-         */
-        uint32_t rx_pulse_submode_sel:3;
-        /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
-         *  Configures the rxd sampling mode.
-         *  2'b00: external level enable mode
-         *  2'b01: external pulse enable mode
-         *  2'b10: internal software enable mode
-         */
-        uint32_t rx_smp_mode_sel:2;
-    };
-    uint32_t val;
-} parl_io_rx_mode_cfg_reg_t;
-
-
-/** Group: PARL_IO RX Data Configuration */
-/** Type of rx_data_cfg register
- *  Parallel RX data configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
-         *  Configures expected byte number of received data.
-         */
-        uint32_t rx_bitlen:19;
-        /** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
-         */
-        uint32_t rx_data_order_inv:1;
-        /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
-         *  Configures the rxd bus width.
-         *  3'd0: bus width is 1.
-         *  3'd1: bus width is 2.
-         *  3'd2: bus width is 4.
-         *  3'd3: bus width is 8.
-         */
-        uint32_t rx_bus_wid_sel:3;
-    };
-    uint32_t val;
-} parl_io_rx_data_cfg_reg_t;
-
-
-/** Group: PARL_IO RX General Configuration */
-/** Type of rx_genrl_cfg register
- *  Parallel RX general configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** rx_gating_en : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable the clock gating of output rx clock.
-         */
-        uint32_t rx_gating_en:1;
-        /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
-         *  Configures threshold of timeout counter.
-         */
-        uint32_t rx_timeout_thres:16;
-        /** rx_timeout_en : R/W; bitpos: [29]; default: 1;
-         *  Set this bit to enable timeout function to generate error eof.
-         */
-        uint32_t rx_timeout_en:1;
-        /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
-         *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
-         *  1'b1: eof generated by external enable signal.
-         */
-        uint32_t rx_eof_gen_sel:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} parl_io_rx_genrl_cfg_reg_t;
-
-
-/** Group: PARL_IO RX Start Configuration */
-/** Type of rx_start_cfg register
- *  Parallel RX Start configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** rx_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start rx data sampling.
-         */
-        uint32_t rx_start:1;
-    };
-    uint32_t val;
-} parl_io_rx_start_cfg_reg_t;
-
-
-/** Group: PARL_IO TX Data Configuration */
-/** Type of tx_data_cfg register
- *  Parallel TX data configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
-         *  Configures expected byte number of sent data.
-         */
-        uint32_t tx_bitlen:19;
-        /** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
-         */
-        uint32_t tx_data_order_inv:1;
-        /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
-         *  Configures the txd bus width.
-         *  3'd0: bus width is 1.
-         *  3'd1: bus width is 2.
-         *  3'd2: bus width is 4.
-         *  3'd3: bus width is 8.
-         */
-        uint32_t tx_bus_wid_sel:3;
-    };
-    uint32_t val;
-} parl_io_tx_data_cfg_reg_t;
-
-
-/** Group: PARL_IO TX Start Configuration */
-/** Type of tx_start_cfg register
- *  Parallel TX Start configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start tx data transmit.
-         */
-        uint32_t tx_start:1;
-    };
-    uint32_t val;
-} parl_io_tx_start_cfg_reg_t;
-
-
-/** Group: PARL_IO TX General Configuration */
-/** Type of tx_genrl_cfg register
- *  Parallel TX general configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:13;
-        /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
-         *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
-         *  1'b1: eof generated by DMA eof.
-         */
-        uint32_t tx_eof_gen_sel:1;
-        /** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
-         *  Configures bus value of transmitter in IDLE state.
-         */
-        uint32_t tx_idle_value:16;
-        /** tx_gating_en : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to enable the clock gating of output tx clock.
-         */
-        uint32_t tx_gating_en:1;
-        /** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to enable the output of tx data valid signal.
-         */
-        uint32_t tx_valid_output_en:1;
-    };
-    uint32_t val;
-} parl_io_tx_genrl_cfg_reg_t;
-
-
-/** Group: PARL_IO FIFO Configuration */
-/** Type of fifo_cfg register
- *  Parallel IO FIFO configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to reset async fifo in tx module.
-         */
-        uint32_t tx_fifo_srst:1;
-        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to reset async fifo in rx module.
-         */
-        uint32_t rx_fifo_srst:1;
-    };
-    uint32_t val;
-} parl_io_fifo_cfg_reg_t;
-
-
-/** Group: PARL_IO Register Update Configuration */
-/** Type of reg_update register
- *  Parallel IO FIFO configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** rx_reg_update : WT; bitpos: [31]; default: 0;
-         *  Set this bit to update rx register configuration.
-         */
-        uint32_t rx_reg_update:1;
-    };
-    uint32_t val;
-} parl_io_reg_update_reg_t;
-
-
-/** Group: PARL_IO Status */
-/** Type of st register
- *  Parallel IO module status register0.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_ready : RO; bitpos: [31]; default: 0;
-         *  Represents the status that tx is ready to transmit.
-         */
-        uint32_t tx_ready:1;
-    };
-    uint32_t val;
-} parl_io_st_reg_t;
-
-
-/** Group: PARL_IO Interrupt Configuration and Status */
-/** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_ena:1;
-        /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_ena:1;
-        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to enable TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_raw:1;
-        /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status of RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_raw:1;
-        /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_raw_reg_t;
-
-/** Type of int_st register
- *  Parallel IO interrupt singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status of TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_st:1;
-        /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status of RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_st:1;
-        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status of TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_st_reg_t;
-
-/** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_clr:1;
-        /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_clr:1;
-        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_clr_reg_t;
-
-
-/** Group: PARL_IO Rx Status0 */
-/** Type of rx_st0 register
- *  Parallel IO RX status register0
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** rx_cnt : RO; bitpos: [12:8]; default: 0;
-         *  Indicates the cycle number of reading Rx FIFO.
-         */
-        uint32_t rx_cnt:5;
-        /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current written bit number into Rx FIFO.
-         */
-        uint32_t rx_fifo_wr_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_rx_st0_reg_t;
-
-
-/** Group: PARL_IO Rx Status1 */
-/** Type of rx_st1 register
- *  Parallel IO RX status register1
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:13;
-        /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current read bit number from Rx FIFO.
-         */
-        uint32_t rx_fifo_rd_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_rx_st1_reg_t;
-
-
-/** Group: PARL_IO Tx Status0 */
-/** Type of tx_st0 register
- *  Parallel IO TX status register0
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:6;
-        /** tx_cnt : RO; bitpos: [12:6]; default: 0;
-         *  Indicates the cycle number of reading Tx FIFO.
-         */
-        uint32_t tx_cnt:7;
-        /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current read bit number from Tx FIFO.
-         */
-        uint32_t tx_fifo_rd_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_tx_st0_reg_t;
-
-
-/** Group: PARL_IO Rx Clock Configuration */
-/** Type of rx_clk_cfg register
- *  Parallel IO RX clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to invert the input Rx core clock.
-         */
-        uint32_t rx_clk_i_inv:1;
-        /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to invert the output Rx core clock.
-         */
-        uint32_t rx_clk_o_inv:1;
-    };
-    uint32_t val;
-} parl_io_rx_clk_cfg_reg_t;
-
-
-/** Group: PARL_IO Tx Clock Configuration */
-/** Type of tx_clk_cfg register
- *  Parallel IO TX clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to invert the input Tx core clock.
-         */
-        uint32_t tx_clk_i_inv:1;
-        /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to invert the output Tx core clock.
-         */
-        uint32_t tx_clk_o_inv:1;
-    };
-    uint32_t val;
-} parl_io_tx_clk_cfg_reg_t;
-
-
-/** Group: PARL_IO Clock Configuration */
-/** Type of clk register
- *  Parallel IO clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Force clock on for this register file
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} parl_io_clk_reg_t;
-
-
-/** Group: PARL_IO Version Register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725920;
-         *  Version of this register file
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} parl_io_version_reg_t;
-
-
-typedef struct parl_io_dev_t {
-    volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
-    volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
-    volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
-    volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
-    volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
-    volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
-    volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
-    volatile parl_io_fifo_cfg_reg_t fifo_cfg;
-    volatile parl_io_reg_update_reg_t reg_update;
-    volatile parl_io_st_reg_t st;
-    volatile parl_io_int_ena_reg_t int_ena;
-    volatile parl_io_int_raw_reg_t int_raw;
-    volatile parl_io_int_st_reg_t int_st;
-    volatile parl_io_int_clr_reg_t int_clr;
-    volatile parl_io_rx_st0_reg_t rx_st0;
-    volatile parl_io_rx_st1_reg_t rx_st1;
-    volatile parl_io_tx_st0_reg_t tx_st0;
-    volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
-    volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
-    uint32_t reserved_04c[53];
-    volatile parl_io_clk_reg_t clk;
-    uint32_t reserved_124[182];
-    volatile parl_io_version_reg_t version;
-} parl_io_dev_t;
-
-extern parl_io_dev_t PARL_IO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pau_reg.h b/components/soc/esp32c5/beta3/include/soc/pau_reg.h
deleted file mode 100644
index 207f797c02..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pau_reg.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PAU_REGDMA_CONF_REG register
- *  Peri backup control register
- */
-#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
-/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
- *  backup error type
- */
-#define PAU_FLOW_ERR    0x00000007U
-#define PAU_FLOW_ERR_M  (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
-#define PAU_FLOW_ERR_V  0x00000007U
-#define PAU_FLOW_ERR_S  0
-/** PAU_START : WT; bitpos: [3]; default: 0;
- *  backup start signal
- */
-#define PAU_START    (BIT(3))
-#define PAU_START_M  (PAU_START_V << PAU_START_S)
-#define PAU_START_V  0x00000001U
-#define PAU_START_S  3
-/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
- *  backup direction(reg to mem / mem to reg)
- */
-#define PAU_TO_MEM    (BIT(4))
-#define PAU_TO_MEM_M  (PAU_TO_MEM_V << PAU_TO_MEM_S)
-#define PAU_TO_MEM_V  0x00000001U
-#define PAU_TO_MEM_S  4
-/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
- *  Link select
- */
-#define PAU_LINK_SEL    0x00000003U
-#define PAU_LINK_SEL_M  (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
-#define PAU_LINK_SEL_V  0x00000003U
-#define PAU_LINK_SEL_S  5
-/** PAU_START_MAC : WT; bitpos: [7]; default: 0;
- *  mac sw backup start signal
- */
-#define PAU_START_MAC    (BIT(7))
-#define PAU_START_MAC_M  (PAU_START_MAC_V << PAU_START_MAC_S)
-#define PAU_START_MAC_V  0x00000001U
-#define PAU_START_MAC_S  7
-/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
- *  mac sw backup direction(reg to mem / mem to reg)
- */
-#define PAU_TO_MEM_MAC    (BIT(8))
-#define PAU_TO_MEM_MAC_M  (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
-#define PAU_TO_MEM_MAC_V  0x00000001U
-#define PAU_TO_MEM_MAC_S  8
-/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
- *  mac hw/sw select
- */
-#define PAU_SEL_MAC    (BIT(9))
-#define PAU_SEL_MAC_M  (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
-#define PAU_SEL_MAC_V  0x00000001U
-#define PAU_SEL_MAC_S  9
-
-/** PAU_REGDMA_CLK_CONF_REG register
- *  Clock control register
- */
-#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
-/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  clock enable
- */
-#define PAU_CLK_EN    (BIT(0))
-#define PAU_CLK_EN_M  (PAU_CLK_EN_V << PAU_CLK_EN_S)
-#define PAU_CLK_EN_V  0x00000001U
-#define PAU_CLK_EN_S  0
-
-/** PAU_REGDMA_ETM_CTRL_REG register
- *  ETM start ctrl reg
- */
-#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
-/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
- *  etm_start_0 reg
- */
-#define PAU_ETM_START_0    (BIT(0))
-#define PAU_ETM_START_0_M  (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
-#define PAU_ETM_START_0_V  0x00000001U
-#define PAU_ETM_START_0_S  0
-/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
- *  etm_start_1 reg
- */
-#define PAU_ETM_START_1    (BIT(1))
-#define PAU_ETM_START_1_M  (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
-#define PAU_ETM_START_1_V  0x00000001U
-#define PAU_ETM_START_1_S  1
-/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
- *  etm_start_2 reg
- */
-#define PAU_ETM_START_2    (BIT(2))
-#define PAU_ETM_START_2_M  (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
-#define PAU_ETM_START_2_V  0x00000001U
-#define PAU_ETM_START_2_S  2
-/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
- *  etm_start_3 reg
- */
-#define PAU_ETM_START_3    (BIT(3))
-#define PAU_ETM_START_3_M  (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
-#define PAU_ETM_START_3_V  0x00000001U
-#define PAU_ETM_START_3_S  3
-
-/** PAU_REGDMA_LINK_0_ADDR_REG register
- *  link_0_addr
- */
-#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
-/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
- *  link_0_addr reg
- */
-#define PAU_LINK_ADDR_0    0xFFFFFFFFU
-#define PAU_LINK_ADDR_0_M  (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
-#define PAU_LINK_ADDR_0_V  0xFFFFFFFFU
-#define PAU_LINK_ADDR_0_S  0
-
-/** PAU_REGDMA_LINK_1_ADDR_REG register
- *  Link_1_addr
- */
-#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
-/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
- *  Link_1_addr reg
- */
-#define PAU_LINK_ADDR_1    0xFFFFFFFFU
-#define PAU_LINK_ADDR_1_M  (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
-#define PAU_LINK_ADDR_1_V  0xFFFFFFFFU
-#define PAU_LINK_ADDR_1_S  0
-
-/** PAU_REGDMA_LINK_2_ADDR_REG register
- *  Link_2_addr
- */
-#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
-/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
- *  Link_2_addr reg
- */
-#define PAU_LINK_ADDR_2    0xFFFFFFFFU
-#define PAU_LINK_ADDR_2_M  (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
-#define PAU_LINK_ADDR_2_V  0xFFFFFFFFU
-#define PAU_LINK_ADDR_2_S  0
-
-/** PAU_REGDMA_LINK_3_ADDR_REG register
- *  Link_3_addr
- */
-#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
-/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
- *  Link_3_addr reg
- */
-#define PAU_LINK_ADDR_3    0xFFFFFFFFU
-#define PAU_LINK_ADDR_3_M  (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
-#define PAU_LINK_ADDR_3_V  0xFFFFFFFFU
-#define PAU_LINK_ADDR_3_S  0
-
-/** PAU_REGDMA_LINK_MAC_ADDR_REG register
- *  Link_mac_addr
- */
-#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
-/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
- *  Link_mac_addr reg
- */
-#define PAU_LINK_ADDR_MAC    0xFFFFFFFFU
-#define PAU_LINK_ADDR_MAC_M  (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
-#define PAU_LINK_ADDR_MAC_V  0xFFFFFFFFU
-#define PAU_LINK_ADDR_MAC_S  0
-
-/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
- *  current link addr
- */
-#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
-/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
- *  current link addr reg
- */
-#define PAU_CURRENT_LINK_ADDR    0xFFFFFFFFU
-#define PAU_CURRENT_LINK_ADDR_M  (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
-#define PAU_CURRENT_LINK_ADDR_V  0xFFFFFFFFU
-#define PAU_CURRENT_LINK_ADDR_S  0
-
-/** PAU_REGDMA_BACKUP_ADDR_REG register
- *  Backup addr
- */
-#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
-/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
- *  backup addr reg
- */
-#define PAU_BACKUP_ADDR    0xFFFFFFFFU
-#define PAU_BACKUP_ADDR_M  (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
-#define PAU_BACKUP_ADDR_V  0xFFFFFFFFU
-#define PAU_BACKUP_ADDR_S  0
-
-/** PAU_REGDMA_MEM_ADDR_REG register
- *  mem addr
- */
-#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
-/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
- *  mem addr reg
- */
-#define PAU_MEM_ADDR    0xFFFFFFFFU
-#define PAU_MEM_ADDR_M  (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
-#define PAU_MEM_ADDR_V  0xFFFFFFFFU
-#define PAU_MEM_ADDR_S  0
-
-/** PAU_REGDMA_BKP_CONF_REG register
- *  backup config
- */
-#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
-/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
- *  Link read_interval
- */
-#define PAU_READ_INTERVAL    0x0000007FU
-#define PAU_READ_INTERVAL_M  (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
-#define PAU_READ_INTERVAL_V  0x0000007FU
-#define PAU_READ_INTERVAL_S  0
-/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
- *  link wait timeout threshold
- */
-#define PAU_LINK_TOUT_THRES    0x000003FFU
-#define PAU_LINK_TOUT_THRES_M  (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
-#define PAU_LINK_TOUT_THRES_V  0x000003FFU
-#define PAU_LINK_TOUT_THRES_S  7
-/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
- *  burst limit
- */
-#define PAU_BURST_LIMIT    0x0000001FU
-#define PAU_BURST_LIMIT_M  (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
-#define PAU_BURST_LIMIT_V  0x0000001FU
-#define PAU_BURST_LIMIT_S  17
-/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
- *  Backup timeout threshold
- */
-#define PAU_BACKUP_TOUT_THRES    0x000003FFU
-#define PAU_BACKUP_TOUT_THRES_M  (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
-#define PAU_BACKUP_TOUT_THRES_V  0x000003FFU
-#define PAU_BACKUP_TOUT_THRES_S  22
-
-/** PAU_INT_ENA_REG register
- *  Read only register for error and done
- */
-#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30)
-/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  backup done flag
- */
-#define PAU_DONE_INT_ENA    (BIT(0))
-#define PAU_DONE_INT_ENA_M  (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
-#define PAU_DONE_INT_ENA_V  0x00000001U
-#define PAU_DONE_INT_ENA_S  0
-/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  error flag
- */
-#define PAU_ERROR_INT_ENA    (BIT(1))
-#define PAU_ERROR_INT_ENA_M  (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
-#define PAU_ERROR_INT_ENA_V  0x00000001U
-#define PAU_ERROR_INT_ENA_S  1
-
-/** PAU_INT_RAW_REG register
- *  Read only register for error and done
- */
-#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34)
-/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  backup done flag
- */
-#define PAU_DONE_INT_RAW    (BIT(0))
-#define PAU_DONE_INT_RAW_M  (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
-#define PAU_DONE_INT_RAW_V  0x00000001U
-#define PAU_DONE_INT_RAW_S  0
-/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  error flag
- */
-#define PAU_ERROR_INT_RAW    (BIT(1))
-#define PAU_ERROR_INT_RAW_M  (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
-#define PAU_ERROR_INT_RAW_V  0x00000001U
-#define PAU_ERROR_INT_RAW_S  1
-
-/** PAU_INT_CLR_REG register
- *  Read only register for error and done
- */
-#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38)
-/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  backup done flag
- */
-#define PAU_DONE_INT_CLR    (BIT(0))
-#define PAU_DONE_INT_CLR_M  (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
-#define PAU_DONE_INT_CLR_V  0x00000001U
-#define PAU_DONE_INT_CLR_S  0
-/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
- *  error flag
- */
-#define PAU_ERROR_INT_CLR    (BIT(1))
-#define PAU_ERROR_INT_CLR_M  (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
-#define PAU_ERROR_INT_CLR_V  0x00000001U
-#define PAU_ERROR_INT_CLR_S  1
-
-/** PAU_INT_ST_REG register
- *  Read only register for error and done
- */
-#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c)
-/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  backup done flag
- */
-#define PAU_DONE_INT_ST    (BIT(0))
-#define PAU_DONE_INT_ST_M  (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
-#define PAU_DONE_INT_ST_V  0x00000001U
-#define PAU_DONE_INT_ST_S  0
-/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
- *  error flag
- */
-#define PAU_ERROR_INT_ST    (BIT(1))
-#define PAU_ERROR_INT_ST_M  (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
-#define PAU_ERROR_INT_ST_V  0x00000001U
-#define PAU_ERROR_INT_ST_S  1
-
-/** PAU_DATE_REG register
- *  Date register.
- */
-#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
-/** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608;
- *  REGDMA date information/ REGDMA version information.
- */
-#define PAU_DATE    0x0FFFFFFFU
-#define PAU_DATE_M  (PAU_DATE_V << PAU_DATE_S)
-#define PAU_DATE_V  0x0FFFFFFFU
-#define PAU_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pau_struct.h b/components/soc/esp32c5/beta3/include/soc/pau_struct.h
deleted file mode 100644
index 16c9c62767..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pau_struct.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of regdma_conf register
- *  Peri backup control register
- */
-typedef union {
-    struct {
-        /** flow_err : RO; bitpos: [2:0]; default: 0;
-         *  backup error type
-         */
-        uint32_t flow_err:3;
-        /** start : WT; bitpos: [3]; default: 0;
-         *  backup start signal
-         */
-        uint32_t start:1;
-        /** to_mem : R/W; bitpos: [4]; default: 0;
-         *  backup direction(reg to mem / mem to reg)
-         */
-        uint32_t to_mem:1;
-        /** link_sel : R/W; bitpos: [6:5]; default: 0;
-         *  Link select
-         */
-        uint32_t link_sel:2;
-        /** start_mac : WT; bitpos: [7]; default: 0;
-         *  mac sw backup start signal
-         */
-        uint32_t start_mac:1;
-        /** to_mem_mac : R/W; bitpos: [8]; default: 0;
-         *  mac sw backup direction(reg to mem / mem to reg)
-         */
-        uint32_t to_mem_mac:1;
-        /** sel_mac : R/W; bitpos: [9]; default: 0;
-         *  mac hw/sw select
-         */
-        uint32_t sel_mac:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} pau_regdma_conf_reg_t;
-
-/** Type of regdma_clk_conf register
- *  Clock control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  clock enable
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} pau_regdma_clk_conf_reg_t;
-
-/** Type of regdma_etm_ctrl register
- *  ETM start ctrl reg
- */
-typedef union {
-    struct {
-        /** etm_start_0 : WT; bitpos: [0]; default: 0;
-         *  etm_start_0 reg
-         */
-        uint32_t etm_start_0:1;
-        /** etm_start_1 : WT; bitpos: [1]; default: 0;
-         *  etm_start_1 reg
-         */
-        uint32_t etm_start_1:1;
-        /** etm_start_2 : WT; bitpos: [2]; default: 0;
-         *  etm_start_2 reg
-         */
-        uint32_t etm_start_2:1;
-        /** etm_start_3 : WT; bitpos: [3]; default: 0;
-         *  etm_start_3 reg
-         */
-        uint32_t etm_start_3:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pau_regdma_etm_ctrl_reg_t;
-
-/** Type of regdma_link_0_addr register
- *  link_0_addr
- */
-typedef union {
-    struct {
-        /** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
-         *  link_0_addr reg
-         */
-        uint32_t link_addr_0:32;
-    };
-    uint32_t val;
-} pau_regdma_link_0_addr_reg_t;
-
-/** Type of regdma_link_1_addr register
- *  Link_1_addr
- */
-typedef union {
-    struct {
-        /** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Link_1_addr reg
-         */
-        uint32_t link_addr_1:32;
-    };
-    uint32_t val;
-} pau_regdma_link_1_addr_reg_t;
-
-/** Type of regdma_link_2_addr register
- *  Link_2_addr
- */
-typedef union {
-    struct {
-        /** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Link_2_addr reg
-         */
-        uint32_t link_addr_2:32;
-    };
-    uint32_t val;
-} pau_regdma_link_2_addr_reg_t;
-
-/** Type of regdma_link_3_addr register
- *  Link_3_addr
- */
-typedef union {
-    struct {
-        /** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Link_3_addr reg
-         */
-        uint32_t link_addr_3:32;
-    };
-    uint32_t val;
-} pau_regdma_link_3_addr_reg_t;
-
-/** Type of regdma_link_mac_addr register
- *  Link_mac_addr
- */
-typedef union {
-    struct {
-        /** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
-         *  Link_mac_addr reg
-         */
-        uint32_t link_addr_mac:32;
-    };
-    uint32_t val;
-} pau_regdma_link_mac_addr_reg_t;
-
-/** Type of regdma_current_link_addr register
- *  current link addr
- */
-typedef union {
-    struct {
-        /** current_link_addr : RO; bitpos: [31:0]; default: 0;
-         *  current link addr reg
-         */
-        uint32_t current_link_addr:32;
-    };
-    uint32_t val;
-} pau_regdma_current_link_addr_reg_t;
-
-/** Type of regdma_backup_addr register
- *  Backup addr
- */
-typedef union {
-    struct {
-        /** backup_addr : RO; bitpos: [31:0]; default: 0;
-         *  backup addr reg
-         */
-        uint32_t backup_addr:32;
-    };
-    uint32_t val;
-} pau_regdma_backup_addr_reg_t;
-
-/** Type of regdma_mem_addr register
- *  mem addr
- */
-typedef union {
-    struct {
-        /** mem_addr : RO; bitpos: [31:0]; default: 0;
-         *  mem addr reg
-         */
-        uint32_t mem_addr:32;
-    };
-    uint32_t val;
-} pau_regdma_mem_addr_reg_t;
-
-/** Type of regdma_bkp_conf register
- *  backup config
- */
-typedef union {
-    struct {
-        /** read_interval : R/W; bitpos: [6:0]; default: 32;
-         *  Link read_interval
-         */
-        uint32_t read_interval:7;
-        /** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
-         *  link wait timeout threshold
-         */
-        uint32_t link_tout_thres:10;
-        /** burst_limit : R/W; bitpos: [21:17]; default: 8;
-         *  burst limit
-         */
-        uint32_t burst_limit:5;
-        /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
-         *  Backup timeout threshold
-         */
-        uint32_t backup_tout_thres:10;
-    };
-    uint32_t val;
-} pau_regdma_bkp_conf_reg_t;
-
-/** Type of int_ena register
- *  Read only register for error and done
- */
-typedef union {
-    struct {
-        /** done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  backup done flag
-         */
-        uint32_t done_int_ena:1;
-        /** error_int_ena : R/W; bitpos: [1]; default: 0;
-         *  error flag
-         */
-        uint32_t error_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pau_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Read only register for error and done
- */
-typedef union {
-    struct {
-        /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  backup done flag
-         */
-        uint32_t done_int_raw:1;
-        /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  error flag
-         */
-        uint32_t error_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pau_int_raw_reg_t;
-
-/** Type of int_clr register
- *  Read only register for error and done
- */
-typedef union {
-    struct {
-        /** done_int_clr : WT; bitpos: [0]; default: 0;
-         *  backup done flag
-         */
-        uint32_t done_int_clr:1;
-        /** error_int_clr : WT; bitpos: [1]; default: 0;
-         *  error flag
-         */
-        uint32_t error_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pau_int_clr_reg_t;
-
-/** Type of int_st register
- *  Read only register for error and done
- */
-typedef union {
-    struct {
-        /** done_int_st : RO; bitpos: [0]; default: 0;
-         *  backup done flag
-         */
-        uint32_t done_int_st:1;
-        /** error_int_st : RO; bitpos: [1]; default: 0;
-         *  error flag
-         */
-        uint32_t error_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pau_int_st_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36708608;
-         *  REGDMA date information/ REGDMA version information.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pau_date_reg_t;
-
-
-typedef struct pau_dev_t {
-    volatile pau_regdma_conf_reg_t regdma_conf;
-    volatile pau_regdma_clk_conf_reg_t regdma_clk_conf;
-    volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl;
-    volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr;
-    volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr;
-    volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr;
-    volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr;
-    volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr;
-    volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr;
-    volatile pau_regdma_backup_addr_reg_t regdma_backup_addr;
-    volatile pau_regdma_mem_addr_reg_t regdma_mem_addr;
-    volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf;
-    volatile pau_int_ena_reg_t int_ena;
-    volatile pau_int_raw_reg_t int_raw;
-    volatile pau_int_clr_reg_t int_clr;
-    volatile pau_int_st_reg_t int_st;
-    uint32_t reserved_040[239];
-    volatile pau_date_reg_t date;
-} pau_dev_t;
-
-extern pau_dev_t PAU;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pcnt_reg.h b/components/soc/esp32c5/beta3/include/soc/pcnt_reg.h
deleted file mode 100644
index 7cbfedda60..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pcnt_reg.h
+++ /dev/null
@@ -1,1346 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PCNT_U0_CONF0_REG register
- *  Configuration register 0 for unit 0
- */
-#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0)
-/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16;
- *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
- *
- *  Any pulses with width less than this will be ignored when the filter is enabled.
- */
-#define PCNT_FILTER_THRES_U0    0x000003FFU
-#define PCNT_FILTER_THRES_U0_M  (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S)
-#define PCNT_FILTER_THRES_U0_V  0x000003FFU
-#define PCNT_FILTER_THRES_U0_S  0
-/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1;
- *  This is the enable bit for unit 0's input filter.
- */
-#define PCNT_FILTER_EN_U0    (BIT(10))
-#define PCNT_FILTER_EN_U0_M  (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S)
-#define PCNT_FILTER_EN_U0_V  0x00000001U
-#define PCNT_FILTER_EN_U0_S  10
-/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1;
- *  This is the enable bit for unit 0's zero comparator.
- */
-#define PCNT_THR_ZERO_EN_U0    (BIT(11))
-#define PCNT_THR_ZERO_EN_U0_M  (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S)
-#define PCNT_THR_ZERO_EN_U0_V  0x00000001U
-#define PCNT_THR_ZERO_EN_U0_S  11
-/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1;
- *  This is the enable bit for unit 0's thr_h_lim comparator. Configures it to enable
- *  the high limit interrupt.
- */
-#define PCNT_THR_H_LIM_EN_U0    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U0_M  (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S)
-#define PCNT_THR_H_LIM_EN_U0_V  0x00000001U
-#define PCNT_THR_H_LIM_EN_U0_S  12
-/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1;
- *  This is the enable bit for unit 0's thr_l_lim comparator. Configures it to enable
- *  the low limit interrupt.
- */
-#define PCNT_THR_L_LIM_EN_U0    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U0_M  (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S)
-#define PCNT_THR_L_LIM_EN_U0_V  0x00000001U
-#define PCNT_THR_L_LIM_EN_U0_S  13
-/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for unit 0's thres0 comparator.
- */
-#define PCNT_THR_THRES0_EN_U0    (BIT(14))
-#define PCNT_THR_THRES0_EN_U0_M  (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S)
-#define PCNT_THR_THRES0_EN_U0_V  0x00000001U
-#define PCNT_THR_THRES0_EN_U0_S  14
-/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for unit 0's thres1 comparator.
- */
-#define PCNT_THR_THRES1_EN_U0    (BIT(15))
-#define PCNT_THR_THRES1_EN_U0_M  (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S)
-#define PCNT_THR_THRES1_EN_U0_V  0x00000001U
-#define PCNT_THR_THRES1_EN_U0_S  15
-/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  negative edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_NEG_MODE_U0    0x00000003U
-#define PCNT_CH0_NEG_MODE_U0_M  (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S)
-#define PCNT_CH0_NEG_MODE_U0_V  0x00000003U
-#define PCNT_CH0_NEG_MODE_U0_S  16
-/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  positive edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_POS_MODE_U0    0x00000003U
-#define PCNT_CH0_POS_MODE_U0_M  (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S)
-#define PCNT_CH0_POS_MODE_U0_V  0x00000003U
-#define PCNT_CH0_POS_MODE_U0_S  18
-/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0;
- *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_HCTRL_MODE_U0    0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U0_M  (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S)
-#define PCNT_CH0_HCTRL_MODE_U0_V  0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U0_S  20
-/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0;
- *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_LCTRL_MODE_U0    0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U0_M  (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S)
-#define PCNT_CH0_LCTRL_MODE_U0_V  0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U0_S  22
-/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  negative edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_NEG_MODE_U0    0x00000003U
-#define PCNT_CH1_NEG_MODE_U0_M  (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S)
-#define PCNT_CH1_NEG_MODE_U0_V  0x00000003U
-#define PCNT_CH1_NEG_MODE_U0_S  24
-/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  positive edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_POS_MODE_U0    0x00000003U
-#define PCNT_CH1_POS_MODE_U0_M  (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S)
-#define PCNT_CH1_POS_MODE_U0_V  0x00000003U
-#define PCNT_CH1_POS_MODE_U0_S  26
-/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0;
- *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_HCTRL_MODE_U0    0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U0_M  (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S)
-#define PCNT_CH1_HCTRL_MODE_U0_V  0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U0_S  28
-/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0;
- *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_LCTRL_MODE_U0    0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U0_M  (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S)
-#define PCNT_CH1_LCTRL_MODE_U0_V  0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U0_S  30
-
-/** PCNT_U0_CONF1_REG register
- *  Configuration register 1 for unit 0
- */
-#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4)
-/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thres0 value for unit 0.
- */
-#define PCNT_CNT_THRES0_U0    0x0000FFFFU
-#define PCNT_CNT_THRES0_U0_M  (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S)
-#define PCNT_CNT_THRES0_U0_V  0x0000FFFFU
-#define PCNT_CNT_THRES0_U0_S  0
-/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thres1 value for unit 0.
- */
-#define PCNT_CNT_THRES1_U0    0x0000FFFFU
-#define PCNT_CNT_THRES1_U0_M  (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S)
-#define PCNT_CNT_THRES1_U0_V  0x0000FFFFU
-#define PCNT_CNT_THRES1_U0_S  16
-
-/** PCNT_U0_CONF2_REG register
- *  Configuration register 2 for unit 0
- */
-#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8)
-/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thr_h_lim value for unit 0. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_H_LIM_U0    0x0000FFFFU
-#define PCNT_CNT_H_LIM_U0_M  (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S)
-#define PCNT_CNT_H_LIM_U0_V  0x0000FFFFU
-#define PCNT_CNT_H_LIM_U0_S  0
-/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thr_l_lim value for unit 0. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_L_LIM_U0    0x0000FFFFU
-#define PCNT_CNT_L_LIM_U0_M  (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S)
-#define PCNT_CNT_L_LIM_U0_V  0x0000FFFFU
-#define PCNT_CNT_L_LIM_U0_S  16
-
-/** PCNT_U1_CONF0_REG register
- *  Configuration register 0 for unit 1
- */
-#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc)
-/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16;
- *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
- *
- *  Any pulses with width less than this will be ignored when the filter is enabled.
- */
-#define PCNT_FILTER_THRES_U1    0x000003FFU
-#define PCNT_FILTER_THRES_U1_M  (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S)
-#define PCNT_FILTER_THRES_U1_V  0x000003FFU
-#define PCNT_FILTER_THRES_U1_S  0
-/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1;
- *  This is the enable bit for unit 1's input filter.
- */
-#define PCNT_FILTER_EN_U1    (BIT(10))
-#define PCNT_FILTER_EN_U1_M  (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S)
-#define PCNT_FILTER_EN_U1_V  0x00000001U
-#define PCNT_FILTER_EN_U1_S  10
-/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1;
- *  This is the enable bit for unit 1's zero comparator.
- */
-#define PCNT_THR_ZERO_EN_U1    (BIT(11))
-#define PCNT_THR_ZERO_EN_U1_M  (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S)
-#define PCNT_THR_ZERO_EN_U1_V  0x00000001U
-#define PCNT_THR_ZERO_EN_U1_S  11
-/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1;
- *  This is the enable bit for unit 1's thr_h_lim comparator. Configures it to enable
- *  the high limit interrupt.
- */
-#define PCNT_THR_H_LIM_EN_U1    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U1_M  (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S)
-#define PCNT_THR_H_LIM_EN_U1_V  0x00000001U
-#define PCNT_THR_H_LIM_EN_U1_S  12
-/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1;
- *  This is the enable bit for unit 1's thr_l_lim comparator. Configures it to enable
- *  the low limit interrupt.
- */
-#define PCNT_THR_L_LIM_EN_U1    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U1_M  (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S)
-#define PCNT_THR_L_LIM_EN_U1_V  0x00000001U
-#define PCNT_THR_L_LIM_EN_U1_S  13
-/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for unit 1's thres0 comparator.
- */
-#define PCNT_THR_THRES0_EN_U1    (BIT(14))
-#define PCNT_THR_THRES0_EN_U1_M  (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S)
-#define PCNT_THR_THRES0_EN_U1_V  0x00000001U
-#define PCNT_THR_THRES0_EN_U1_S  14
-/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for unit 1's thres1 comparator.
- */
-#define PCNT_THR_THRES1_EN_U1    (BIT(15))
-#define PCNT_THR_THRES1_EN_U1_M  (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S)
-#define PCNT_THR_THRES1_EN_U1_V  0x00000001U
-#define PCNT_THR_THRES1_EN_U1_S  15
-/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  negative edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_NEG_MODE_U1    0x00000003U
-#define PCNT_CH0_NEG_MODE_U1_M  (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S)
-#define PCNT_CH0_NEG_MODE_U1_V  0x00000003U
-#define PCNT_CH0_NEG_MODE_U1_S  16
-/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  positive edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_POS_MODE_U1    0x00000003U
-#define PCNT_CH0_POS_MODE_U1_M  (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S)
-#define PCNT_CH0_POS_MODE_U1_V  0x00000003U
-#define PCNT_CH0_POS_MODE_U1_S  18
-/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0;
- *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_HCTRL_MODE_U1    0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U1_M  (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S)
-#define PCNT_CH0_HCTRL_MODE_U1_V  0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U1_S  20
-/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0;
- *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_LCTRL_MODE_U1    0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U1_M  (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S)
-#define PCNT_CH0_LCTRL_MODE_U1_V  0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U1_S  22
-/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  negative edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_NEG_MODE_U1    0x00000003U
-#define PCNT_CH1_NEG_MODE_U1_M  (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S)
-#define PCNT_CH1_NEG_MODE_U1_V  0x00000003U
-#define PCNT_CH1_NEG_MODE_U1_S  24
-/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  positive edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_POS_MODE_U1    0x00000003U
-#define PCNT_CH1_POS_MODE_U1_M  (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S)
-#define PCNT_CH1_POS_MODE_U1_V  0x00000003U
-#define PCNT_CH1_POS_MODE_U1_S  26
-/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0;
- *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_HCTRL_MODE_U1    0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U1_M  (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S)
-#define PCNT_CH1_HCTRL_MODE_U1_V  0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U1_S  28
-/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0;
- *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_LCTRL_MODE_U1    0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U1_M  (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S)
-#define PCNT_CH1_LCTRL_MODE_U1_V  0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U1_S  30
-
-/** PCNT_U1_CONF1_REG register
- *  Configuration register 1 for unit 1
- */
-#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10)
-/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thres0 value for unit 1.
- */
-#define PCNT_CNT_THRES0_U1    0x0000FFFFU
-#define PCNT_CNT_THRES0_U1_M  (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S)
-#define PCNT_CNT_THRES0_U1_V  0x0000FFFFU
-#define PCNT_CNT_THRES0_U1_S  0
-/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thres1 value for unit 1.
- */
-#define PCNT_CNT_THRES1_U1    0x0000FFFFU
-#define PCNT_CNT_THRES1_U1_M  (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S)
-#define PCNT_CNT_THRES1_U1_V  0x0000FFFFU
-#define PCNT_CNT_THRES1_U1_S  16
-
-/** PCNT_U1_CONF2_REG register
- *  Configuration register 2 for unit 1
- */
-#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14)
-/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thr_h_lim value for unit 1. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_H_LIM_U1    0x0000FFFFU
-#define PCNT_CNT_H_LIM_U1_M  (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S)
-#define PCNT_CNT_H_LIM_U1_V  0x0000FFFFU
-#define PCNT_CNT_H_LIM_U1_S  0
-/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thr_l_lim value for unit 1. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_L_LIM_U1    0x0000FFFFU
-#define PCNT_CNT_L_LIM_U1_M  (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S)
-#define PCNT_CNT_L_LIM_U1_V  0x0000FFFFU
-#define PCNT_CNT_L_LIM_U1_S  16
-
-/** PCNT_U2_CONF0_REG register
- *  Configuration register 0 for unit 2
- */
-#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18)
-/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16;
- *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
- *
- *  Any pulses with width less than this will be ignored when the filter is enabled.
- */
-#define PCNT_FILTER_THRES_U2    0x000003FFU
-#define PCNT_FILTER_THRES_U2_M  (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S)
-#define PCNT_FILTER_THRES_U2_V  0x000003FFU
-#define PCNT_FILTER_THRES_U2_S  0
-/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1;
- *  This is the enable bit for unit 2's input filter.
- */
-#define PCNT_FILTER_EN_U2    (BIT(10))
-#define PCNT_FILTER_EN_U2_M  (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S)
-#define PCNT_FILTER_EN_U2_V  0x00000001U
-#define PCNT_FILTER_EN_U2_S  10
-/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1;
- *  This is the enable bit for unit 2's zero comparator.
- */
-#define PCNT_THR_ZERO_EN_U2    (BIT(11))
-#define PCNT_THR_ZERO_EN_U2_M  (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S)
-#define PCNT_THR_ZERO_EN_U2_V  0x00000001U
-#define PCNT_THR_ZERO_EN_U2_S  11
-/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1;
- *  This is the enable bit for unit 2's thr_h_lim comparator. Configures it to enable
- *  the high limit interrupt.
- */
-#define PCNT_THR_H_LIM_EN_U2    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U2_M  (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S)
-#define PCNT_THR_H_LIM_EN_U2_V  0x00000001U
-#define PCNT_THR_H_LIM_EN_U2_S  12
-/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1;
- *  This is the enable bit for unit 2's thr_l_lim comparator. Configures it to enable
- *  the low limit interrupt.
- */
-#define PCNT_THR_L_LIM_EN_U2    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U2_M  (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S)
-#define PCNT_THR_L_LIM_EN_U2_V  0x00000001U
-#define PCNT_THR_L_LIM_EN_U2_S  13
-/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for unit 2's thres0 comparator.
- */
-#define PCNT_THR_THRES0_EN_U2    (BIT(14))
-#define PCNT_THR_THRES0_EN_U2_M  (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S)
-#define PCNT_THR_THRES0_EN_U2_V  0x00000001U
-#define PCNT_THR_THRES0_EN_U2_S  14
-/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for unit 2's thres1 comparator.
- */
-#define PCNT_THR_THRES1_EN_U2    (BIT(15))
-#define PCNT_THR_THRES1_EN_U2_M  (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S)
-#define PCNT_THR_THRES1_EN_U2_V  0x00000001U
-#define PCNT_THR_THRES1_EN_U2_S  15
-/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  negative edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_NEG_MODE_U2    0x00000003U
-#define PCNT_CH0_NEG_MODE_U2_M  (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S)
-#define PCNT_CH0_NEG_MODE_U2_V  0x00000003U
-#define PCNT_CH0_NEG_MODE_U2_S  16
-/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  positive edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_POS_MODE_U2    0x00000003U
-#define PCNT_CH0_POS_MODE_U2_M  (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S)
-#define PCNT_CH0_POS_MODE_U2_V  0x00000003U
-#define PCNT_CH0_POS_MODE_U2_S  18
-/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0;
- *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_HCTRL_MODE_U2    0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U2_M  (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S)
-#define PCNT_CH0_HCTRL_MODE_U2_V  0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U2_S  20
-/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0;
- *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_LCTRL_MODE_U2    0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U2_M  (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S)
-#define PCNT_CH0_LCTRL_MODE_U2_V  0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U2_S  22
-/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  negative edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_NEG_MODE_U2    0x00000003U
-#define PCNT_CH1_NEG_MODE_U2_M  (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S)
-#define PCNT_CH1_NEG_MODE_U2_V  0x00000003U
-#define PCNT_CH1_NEG_MODE_U2_S  24
-/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  positive edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_POS_MODE_U2    0x00000003U
-#define PCNT_CH1_POS_MODE_U2_M  (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S)
-#define PCNT_CH1_POS_MODE_U2_V  0x00000003U
-#define PCNT_CH1_POS_MODE_U2_S  26
-/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0;
- *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_HCTRL_MODE_U2    0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U2_M  (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S)
-#define PCNT_CH1_HCTRL_MODE_U2_V  0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U2_S  28
-/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0;
- *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_LCTRL_MODE_U2    0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U2_M  (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S)
-#define PCNT_CH1_LCTRL_MODE_U2_V  0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U2_S  30
-
-/** PCNT_U2_CONF1_REG register
- *  Configuration register 1 for unit 2
- */
-#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c)
-/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thres0 value for unit 2.
- */
-#define PCNT_CNT_THRES0_U2    0x0000FFFFU
-#define PCNT_CNT_THRES0_U2_M  (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S)
-#define PCNT_CNT_THRES0_U2_V  0x0000FFFFU
-#define PCNT_CNT_THRES0_U2_S  0
-/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thres1 value for unit 2.
- */
-#define PCNT_CNT_THRES1_U2    0x0000FFFFU
-#define PCNT_CNT_THRES1_U2_M  (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S)
-#define PCNT_CNT_THRES1_U2_V  0x0000FFFFU
-#define PCNT_CNT_THRES1_U2_S  16
-
-/** PCNT_U2_CONF2_REG register
- *  Configuration register 2 for unit 2
- */
-#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20)
-/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thr_h_lim value for unit 2. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_H_LIM_U2    0x0000FFFFU
-#define PCNT_CNT_H_LIM_U2_M  (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S)
-#define PCNT_CNT_H_LIM_U2_V  0x0000FFFFU
-#define PCNT_CNT_H_LIM_U2_S  0
-/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thr_l_lim value for unit 2. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_L_LIM_U2    0x0000FFFFU
-#define PCNT_CNT_L_LIM_U2_M  (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S)
-#define PCNT_CNT_L_LIM_U2_V  0x0000FFFFU
-#define PCNT_CNT_L_LIM_U2_S  16
-
-/** PCNT_U3_CONF0_REG register
- *  Configuration register 0 for unit 3
- */
-#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24)
-/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16;
- *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
- *
- *  Any pulses with width less than this will be ignored when the filter is enabled.
- */
-#define PCNT_FILTER_THRES_U3    0x000003FFU
-#define PCNT_FILTER_THRES_U3_M  (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S)
-#define PCNT_FILTER_THRES_U3_V  0x000003FFU
-#define PCNT_FILTER_THRES_U3_S  0
-/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1;
- *  This is the enable bit for unit 3's input filter.
- */
-#define PCNT_FILTER_EN_U3    (BIT(10))
-#define PCNT_FILTER_EN_U3_M  (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S)
-#define PCNT_FILTER_EN_U3_V  0x00000001U
-#define PCNT_FILTER_EN_U3_S  10
-/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1;
- *  This is the enable bit for unit 3's zero comparator.
- */
-#define PCNT_THR_ZERO_EN_U3    (BIT(11))
-#define PCNT_THR_ZERO_EN_U3_M  (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S)
-#define PCNT_THR_ZERO_EN_U3_V  0x00000001U
-#define PCNT_THR_ZERO_EN_U3_S  11
-/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1;
- *  This is the enable bit for unit 3's thr_h_lim comparator. Configures it to enable
- *  the high limit interrupt.
- */
-#define PCNT_THR_H_LIM_EN_U3    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U3_M  (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S)
-#define PCNT_THR_H_LIM_EN_U3_V  0x00000001U
-#define PCNT_THR_H_LIM_EN_U3_S  12
-/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1;
- *  This is the enable bit for unit 3's thr_l_lim comparator. Configures it to enable
- *  the low limit interrupt.
- */
-#define PCNT_THR_L_LIM_EN_U3    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U3_M  (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S)
-#define PCNT_THR_L_LIM_EN_U3_V  0x00000001U
-#define PCNT_THR_L_LIM_EN_U3_S  13
-/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for unit 3's thres0 comparator.
- */
-#define PCNT_THR_THRES0_EN_U3    (BIT(14))
-#define PCNT_THR_THRES0_EN_U3_M  (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S)
-#define PCNT_THR_THRES0_EN_U3_V  0x00000001U
-#define PCNT_THR_THRES0_EN_U3_S  14
-/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for unit 3's thres1 comparator.
- */
-#define PCNT_THR_THRES1_EN_U3    (BIT(15))
-#define PCNT_THR_THRES1_EN_U3_M  (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S)
-#define PCNT_THR_THRES1_EN_U3_V  0x00000001U
-#define PCNT_THR_THRES1_EN_U3_S  15
-/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  negative edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_NEG_MODE_U3    0x00000003U
-#define PCNT_CH0_NEG_MODE_U3_M  (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S)
-#define PCNT_CH0_NEG_MODE_U3_V  0x00000003U
-#define PCNT_CH0_NEG_MODE_U3_S  16
-/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0;
- *  This register sets the behavior when the signal input of channel 0 detects a
- *  positive edge.
- *
- *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
- */
-#define PCNT_CH0_POS_MODE_U3    0x00000003U
-#define PCNT_CH0_POS_MODE_U3_M  (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S)
-#define PCNT_CH0_POS_MODE_U3_V  0x00000003U
-#define PCNT_CH0_POS_MODE_U3_S  18
-/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0;
- *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_HCTRL_MODE_U3    0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U3_M  (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S)
-#define PCNT_CH0_HCTRL_MODE_U3_V  0x00000003U
-#define PCNT_CH0_HCTRL_MODE_U3_S  20
-/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0;
- *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH0_LCTRL_MODE_U3    0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U3_M  (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S)
-#define PCNT_CH0_LCTRL_MODE_U3_V  0x00000003U
-#define PCNT_CH0_LCTRL_MODE_U3_S  22
-/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  negative edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_NEG_MODE_U3    0x00000003U
-#define PCNT_CH1_NEG_MODE_U3_M  (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S)
-#define PCNT_CH1_NEG_MODE_U3_V  0x00000003U
-#define PCNT_CH1_NEG_MODE_U3_S  24
-/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0;
- *  This register sets the behavior when the signal input of channel 1 detects a
- *  positive edge.
- *
- *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
- */
-#define PCNT_CH1_POS_MODE_U3    0x00000003U
-#define PCNT_CH1_POS_MODE_U3_M  (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S)
-#define PCNT_CH1_POS_MODE_U3_V  0x00000003U
-#define PCNT_CH1_POS_MODE_U3_S  26
-/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0;
- *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
- *  modified when the control signal is high.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_HCTRL_MODE_U3    0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U3_M  (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S)
-#define PCNT_CH1_HCTRL_MODE_U3_V  0x00000003U
-#define PCNT_CH1_HCTRL_MODE_U3_S  28
-/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0;
- *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
- *  modified when the control signal is low.
- *
- *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
- *  increase).2, 3: Inhibit counter modification
- */
-#define PCNT_CH1_LCTRL_MODE_U3    0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U3_M  (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S)
-#define PCNT_CH1_LCTRL_MODE_U3_V  0x00000003U
-#define PCNT_CH1_LCTRL_MODE_U3_S  30
-
-/** PCNT_U3_CONF1_REG register
- *  Configuration register 1 for unit 3
- */
-#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28)
-/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thres0 value for unit 3.
- */
-#define PCNT_CNT_THRES0_U3    0x0000FFFFU
-#define PCNT_CNT_THRES0_U3_M  (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S)
-#define PCNT_CNT_THRES0_U3_V  0x0000FFFFU
-#define PCNT_CNT_THRES0_U3_S  0
-/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thres1 value for unit 3.
- */
-#define PCNT_CNT_THRES1_U3    0x0000FFFFU
-#define PCNT_CNT_THRES1_U3_M  (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S)
-#define PCNT_CNT_THRES1_U3_V  0x0000FFFFU
-#define PCNT_CNT_THRES1_U3_S  16
-
-/** PCNT_U3_CONF2_REG register
- *  Configuration register 2 for unit 3
- */
-#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c)
-/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0;
- *  This register is used to configure the thr_h_lim value for unit 3. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_H_LIM_U3    0x0000FFFFU
-#define PCNT_CNT_H_LIM_U3_M  (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S)
-#define PCNT_CNT_H_LIM_U3_V  0x0000FFFFU
-#define PCNT_CNT_H_LIM_U3_S  0
-/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0;
- *  This register is used to configure the thr_l_lim value for unit 3. When pcnt
- *  reaches this value, the counter will be cleared to 0.
- */
-#define PCNT_CNT_L_LIM_U3    0x0000FFFFU
-#define PCNT_CNT_L_LIM_U3_M  (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S)
-#define PCNT_CNT_L_LIM_U3_V  0x0000FFFFU
-#define PCNT_CNT_L_LIM_U3_S  16
-
-/** PCNT_U0_CNT_REG register
- *  Counter value for unit 0
- */
-#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30)
-/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0;
- *  This register stores the current pulse count value for unit 0.
- */
-#define PCNT_PULSE_CNT_U0    0x0000FFFFU
-#define PCNT_PULSE_CNT_U0_M  (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S)
-#define PCNT_PULSE_CNT_U0_V  0x0000FFFFU
-#define PCNT_PULSE_CNT_U0_S  0
-
-/** PCNT_U1_CNT_REG register
- *  Counter value for unit 1
- */
-#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34)
-/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0;
- *  This register stores the current pulse count value for unit 1.
- */
-#define PCNT_PULSE_CNT_U1    0x0000FFFFU
-#define PCNT_PULSE_CNT_U1_M  (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S)
-#define PCNT_PULSE_CNT_U1_V  0x0000FFFFU
-#define PCNT_PULSE_CNT_U1_S  0
-
-/** PCNT_U2_CNT_REG register
- *  Counter value for unit 2
- */
-#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38)
-/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0;
- *  This register stores the current pulse count value for unit 2.
- */
-#define PCNT_PULSE_CNT_U2    0x0000FFFFU
-#define PCNT_PULSE_CNT_U2_M  (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S)
-#define PCNT_PULSE_CNT_U2_V  0x0000FFFFU
-#define PCNT_PULSE_CNT_U2_S  0
-
-/** PCNT_U3_CNT_REG register
- *  Counter value for unit 3
- */
-#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c)
-/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0;
- *  This register stores the current pulse count value for unit 3.
- */
-#define PCNT_PULSE_CNT_U3    0x0000FFFFU
-#define PCNT_PULSE_CNT_U3_M  (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S)
-#define PCNT_PULSE_CNT_U3_V  0x0000FFFFU
-#define PCNT_PULSE_CNT_U3_S  0
-
-/** PCNT_INT_RAW_REG register
- *  Interrupt raw status register
- */
-#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40)
-/** PCNT_CNT_THR_EVENT_U0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S)
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S  0
-/** PCNT_CNT_THR_EVENT_U1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S)
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
-/** PCNT_CNT_THR_EVENT_U2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S)
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
-/** PCNT_CNT_THR_EVENT_U3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S)
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
-
-/** PCNT_INT_ST_REG register
- *  Interrupt status register
- */
-#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44)
-/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U0_INT_ST    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S)
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_S  0
-/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U1_INT_ST    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S)
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
-/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U2_INT_ST    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S)
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
-/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U3_INT_ST    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S)
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
-
-/** PCNT_INT_ENA_REG register
- *  Interrupt enable register
- */
-#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48)
-/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S)
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S  0
-/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S)
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
-/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S)
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
-/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S)
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
-
-/** PCNT_INT_CLR_REG register
- *  Interrupt clear register
- */
-#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c)
-/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S)
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S  0
-/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S)
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
-/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S)
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
-/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
- */
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S)
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x00000001U
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
-
-/** PCNT_U0_STATUS_REG register
- *  PNCT UNIT0 status register
- */
-#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50)
-/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0;
- *  The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases
- *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
- *  is negative. 3: pulse counter is positive.
- */
-#define PCNT_CNT_THR_ZERO_MODE_U0    0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U0_M  (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S)
-#define PCNT_CNT_THR_ZERO_MODE_U0_V  0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U0_S  0
-/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0;
- *  The latched value of thres1 event of PCNT_U0 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES1_LAT_U0    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U0_M  (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S)
-#define PCNT_CNT_THR_THRES1_LAT_U0_V  0x00000001U
-#define PCNT_CNT_THR_THRES1_LAT_U0_S  2
-/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0;
- *  The latched value of thres0 event of PCNT_U0 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES0_LAT_U0    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U0_M  (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S)
-#define PCNT_CNT_THR_THRES0_LAT_U0_V  0x00000001U
-#define PCNT_CNT_THR_THRES0_LAT_U0_S  3
-/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0;
- *  The latched value of low limit event of PCNT_U0 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_L_LIM_LAT_U0    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U0_M  (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S)
-#define PCNT_CNT_THR_L_LIM_LAT_U0_V  0x00000001U
-#define PCNT_CNT_THR_L_LIM_LAT_U0_S  4
-/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0;
- *  The latched value of high limit event of PCNT_U0 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_H_LIM_LAT_U0    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U0_M  (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S)
-#define PCNT_CNT_THR_H_LIM_LAT_U0_V  0x00000001U
-#define PCNT_CNT_THR_H_LIM_LAT_U0_S  5
-/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0;
- *  The latched value of zero threshold event of PCNT_U0 when threshold event interrupt
- *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_ZERO_LAT_U0    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U0_M  (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S)
-#define PCNT_CNT_THR_ZERO_LAT_U0_V  0x00000001U
-#define PCNT_CNT_THR_ZERO_LAT_U0_S  6
-
-/** PCNT_U1_STATUS_REG register
- *  PNCT UNIT1 status register
- */
-#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54)
-/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0;
- *  The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases
- *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
- *  is negative. 3: pulse counter is positive.
- */
-#define PCNT_CNT_THR_ZERO_MODE_U1    0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U1_M  (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S)
-#define PCNT_CNT_THR_ZERO_MODE_U1_V  0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U1_S  0
-/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0;
- *  The latched value of thres1 event of PCNT_U1 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES1_LAT_U1    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U1_M  (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S)
-#define PCNT_CNT_THR_THRES1_LAT_U1_V  0x00000001U
-#define PCNT_CNT_THR_THRES1_LAT_U1_S  2
-/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0;
- *  The latched value of thres0 event of PCNT_U1 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES0_LAT_U1    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U1_M  (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S)
-#define PCNT_CNT_THR_THRES0_LAT_U1_V  0x00000001U
-#define PCNT_CNT_THR_THRES0_LAT_U1_S  3
-/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0;
- *  The latched value of low limit event of PCNT_U1 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_L_LIM_LAT_U1    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U1_M  (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S)
-#define PCNT_CNT_THR_L_LIM_LAT_U1_V  0x00000001U
-#define PCNT_CNT_THR_L_LIM_LAT_U1_S  4
-/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0;
- *  The latched value of high limit event of PCNT_U1 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_H_LIM_LAT_U1    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U1_M  (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S)
-#define PCNT_CNT_THR_H_LIM_LAT_U1_V  0x00000001U
-#define PCNT_CNT_THR_H_LIM_LAT_U1_S  5
-/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0;
- *  The latched value of zero threshold event of PCNT_U1 when threshold event interrupt
- *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_ZERO_LAT_U1    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U1_M  (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S)
-#define PCNT_CNT_THR_ZERO_LAT_U1_V  0x00000001U
-#define PCNT_CNT_THR_ZERO_LAT_U1_S  6
-
-/** PCNT_U2_STATUS_REG register
- *  PNCT UNIT2 status register
- */
-#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58)
-/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0;
- *  The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases
- *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
- *  is negative. 3: pulse counter is positive.
- */
-#define PCNT_CNT_THR_ZERO_MODE_U2    0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U2_M  (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S)
-#define PCNT_CNT_THR_ZERO_MODE_U2_V  0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U2_S  0
-/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0;
- *  The latched value of thres1 event of PCNT_U2 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES1_LAT_U2    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U2_M  (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S)
-#define PCNT_CNT_THR_THRES1_LAT_U2_V  0x00000001U
-#define PCNT_CNT_THR_THRES1_LAT_U2_S  2
-/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0;
- *  The latched value of thres0 event of PCNT_U2 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES0_LAT_U2    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U2_M  (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S)
-#define PCNT_CNT_THR_THRES0_LAT_U2_V  0x00000001U
-#define PCNT_CNT_THR_THRES0_LAT_U2_S  3
-/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0;
- *  The latched value of low limit event of PCNT_U2 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_L_LIM_LAT_U2    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U2_M  (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S)
-#define PCNT_CNT_THR_L_LIM_LAT_U2_V  0x00000001U
-#define PCNT_CNT_THR_L_LIM_LAT_U2_S  4
-/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0;
- *  The latched value of high limit event of PCNT_U2 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_H_LIM_LAT_U2    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U2_M  (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S)
-#define PCNT_CNT_THR_H_LIM_LAT_U2_V  0x00000001U
-#define PCNT_CNT_THR_H_LIM_LAT_U2_S  5
-/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0;
- *  The latched value of zero threshold event of PCNT_U2 when threshold event interrupt
- *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_ZERO_LAT_U2    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U2_M  (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S)
-#define PCNT_CNT_THR_ZERO_LAT_U2_V  0x00000001U
-#define PCNT_CNT_THR_ZERO_LAT_U2_S  6
-
-/** PCNT_U3_STATUS_REG register
- *  PNCT UNIT3 status register
- */
-#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c)
-/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0;
- *  The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases
- *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
- *  is negative. 3: pulse counter is positive.
- */
-#define PCNT_CNT_THR_ZERO_MODE_U3    0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U3_M  (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S)
-#define PCNT_CNT_THR_ZERO_MODE_U3_V  0x00000003U
-#define PCNT_CNT_THR_ZERO_MODE_U3_S  0
-/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0;
- *  The latched value of thres1 event of PCNT_U3 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES1_LAT_U3    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U3_M  (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S)
-#define PCNT_CNT_THR_THRES1_LAT_U3_V  0x00000001U
-#define PCNT_CNT_THR_THRES1_LAT_U3_S  2
-/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0;
- *  The latched value of thres0 event of PCNT_U3 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
- *  others
- */
-#define PCNT_CNT_THR_THRES0_LAT_U3    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U3_M  (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S)
-#define PCNT_CNT_THR_THRES0_LAT_U3_V  0x00000001U
-#define PCNT_CNT_THR_THRES0_LAT_U3_S  3
-/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0;
- *  The latched value of low limit event of PCNT_U3 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_L_LIM_LAT_U3    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U3_M  (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S)
-#define PCNT_CNT_THR_L_LIM_LAT_U3_V  0x00000001U
-#define PCNT_CNT_THR_L_LIM_LAT_U3_S  4
-/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0;
- *  The latched value of high limit event of PCNT_U3 when threshold event interrupt is
- *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_H_LIM_LAT_U3    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U3_M  (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S)
-#define PCNT_CNT_THR_H_LIM_LAT_U3_V  0x00000001U
-#define PCNT_CNT_THR_H_LIM_LAT_U3_S  5
-/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0;
- *  The latched value of zero threshold event of PCNT_U3 when threshold event interrupt
- *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
- *  valid. 0: others
- */
-#define PCNT_CNT_THR_ZERO_LAT_U3    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U3_M  (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S)
-#define PCNT_CNT_THR_ZERO_LAT_U3_V  0x00000001U
-#define PCNT_CNT_THR_ZERO_LAT_U3_S  6
-
-/** PCNT_CTRL_REG register
- *  Control register for all counters
- */
-#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60)
-/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1;
- *  Set this bit to clear unit 0's counter.
- */
-#define PCNT_PULSE_CNT_RST_U0    (BIT(0))
-#define PCNT_PULSE_CNT_RST_U0_M  (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S)
-#define PCNT_PULSE_CNT_RST_U0_V  0x00000001U
-#define PCNT_PULSE_CNT_RST_U0_S  0
-/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0;
- *  Set this bit to freeze unit 0's counter.
- */
-#define PCNT_CNT_PAUSE_U0    (BIT(1))
-#define PCNT_CNT_PAUSE_U0_M  (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S)
-#define PCNT_CNT_PAUSE_U0_V  0x00000001U
-#define PCNT_CNT_PAUSE_U0_S  1
-/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1;
- *  Set this bit to clear unit 1's counter.
- */
-#define PCNT_PULSE_CNT_RST_U1    (BIT(2))
-#define PCNT_PULSE_CNT_RST_U1_M  (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S)
-#define PCNT_PULSE_CNT_RST_U1_V  0x00000001U
-#define PCNT_PULSE_CNT_RST_U1_S  2
-/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0;
- *  Set this bit to freeze unit 1's counter.
- */
-#define PCNT_CNT_PAUSE_U1    (BIT(3))
-#define PCNT_CNT_PAUSE_U1_M  (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S)
-#define PCNT_CNT_PAUSE_U1_V  0x00000001U
-#define PCNT_CNT_PAUSE_U1_S  3
-/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1;
- *  Set this bit to clear unit 2's counter.
- */
-#define PCNT_PULSE_CNT_RST_U2    (BIT(4))
-#define PCNT_PULSE_CNT_RST_U2_M  (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S)
-#define PCNT_PULSE_CNT_RST_U2_V  0x00000001U
-#define PCNT_PULSE_CNT_RST_U2_S  4
-/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0;
- *  Set this bit to freeze unit 2's counter.
- */
-#define PCNT_CNT_PAUSE_U2    (BIT(5))
-#define PCNT_CNT_PAUSE_U2_M  (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S)
-#define PCNT_CNT_PAUSE_U2_V  0x00000001U
-#define PCNT_CNT_PAUSE_U2_S  5
-/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1;
- *  Set this bit to clear unit 3's counter.
- */
-#define PCNT_PULSE_CNT_RST_U3    (BIT(6))
-#define PCNT_PULSE_CNT_RST_U3_M  (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S)
-#define PCNT_PULSE_CNT_RST_U3_V  0x00000001U
-#define PCNT_PULSE_CNT_RST_U3_S  6
-/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0;
- *  Set this bit to freeze unit 3's counter.
- */
-#define PCNT_CNT_PAUSE_U3    (BIT(7))
-#define PCNT_CNT_PAUSE_U3_M  (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S)
-#define PCNT_CNT_PAUSE_U3_V  0x00000001U
-#define PCNT_CNT_PAUSE_U3_S  7
-/** PCNT_DALTA_CHANGE_EN_U0 : R/W; bitpos: [8]; default: 0;
- *  Configures this bit to enable unit 0's step comparator.
- */
-#define PCNT_DALTA_CHANGE_EN_U0    (BIT(8))
-#define PCNT_DALTA_CHANGE_EN_U0_M  (PCNT_DALTA_CHANGE_EN_U0_V << PCNT_DALTA_CHANGE_EN_U0_S)
-#define PCNT_DALTA_CHANGE_EN_U0_V  0x00000001U
-#define PCNT_DALTA_CHANGE_EN_U0_S  8
-/** PCNT_DALTA_CHANGE_EN_U1 : R/W; bitpos: [9]; default: 0;
- *  Configures this bit to enable unit 1's step comparator.
- */
-#define PCNT_DALTA_CHANGE_EN_U1    (BIT(9))
-#define PCNT_DALTA_CHANGE_EN_U1_M  (PCNT_DALTA_CHANGE_EN_U1_V << PCNT_DALTA_CHANGE_EN_U1_S)
-#define PCNT_DALTA_CHANGE_EN_U1_V  0x00000001U
-#define PCNT_DALTA_CHANGE_EN_U1_S  9
-/** PCNT_DALTA_CHANGE_EN_U2 : R/W; bitpos: [10]; default: 0;
- *  Configures this bit to enable unit 2's step comparator.
- */
-#define PCNT_DALTA_CHANGE_EN_U2    (BIT(10))
-#define PCNT_DALTA_CHANGE_EN_U2_M  (PCNT_DALTA_CHANGE_EN_U2_V << PCNT_DALTA_CHANGE_EN_U2_S)
-#define PCNT_DALTA_CHANGE_EN_U2_V  0x00000001U
-#define PCNT_DALTA_CHANGE_EN_U2_S  10
-/** PCNT_DALTA_CHANGE_EN_U3 : R/W; bitpos: [11]; default: 0;
- *  Configures this bit to enable unit 3's step comparator.
- */
-#define PCNT_DALTA_CHANGE_EN_U3    (BIT(11))
-#define PCNT_DALTA_CHANGE_EN_U3_M  (PCNT_DALTA_CHANGE_EN_U3_V << PCNT_DALTA_CHANGE_EN_U3_S)
-#define PCNT_DALTA_CHANGE_EN_U3_V  0x00000001U
-#define PCNT_DALTA_CHANGE_EN_U3_S  11
-/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
- *  and written by application. 0: the registers can not be read or written by
- *  application
- */
-#define PCNT_CLK_EN    (BIT(16))
-#define PCNT_CLK_EN_M  (PCNT_CLK_EN_V << PCNT_CLK_EN_S)
-#define PCNT_CLK_EN_V  0x00000001U
-#define PCNT_CLK_EN_S  16
-
-/** PCNT_U3_CHANGE_CONF_REG register
- *  Configuration register for unit $n's step value.
- */
-#define PCNT_U3_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x64)
-/** PCNT_CNT_STEP_U3 : R/W; bitpos: [15:0]; default: 0;
- *  Configures the step value for unit 3.
- */
-#define PCNT_CNT_STEP_U3    0x0000FFFFU
-#define PCNT_CNT_STEP_U3_M  (PCNT_CNT_STEP_U3_V << PCNT_CNT_STEP_U3_S)
-#define PCNT_CNT_STEP_U3_V  0x0000FFFFU
-#define PCNT_CNT_STEP_U3_S  0
-/** PCNT_CNT_STEP_LIM_U3 : R/W; bitpos: [31:16]; default: 0;
- *  Configures the step limit value for unit 3.
- */
-#define PCNT_CNT_STEP_LIM_U3    0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U3_M  (PCNT_CNT_STEP_LIM_U3_V << PCNT_CNT_STEP_LIM_U3_S)
-#define PCNT_CNT_STEP_LIM_U3_V  0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U3_S  16
-
-/** PCNT_U2_CHANGE_CONF_REG register
- *  Configuration register for unit $n's step value.
- */
-#define PCNT_U2_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x68)
-/** PCNT_CNT_STEP_U2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures the step value for unit 2.
- */
-#define PCNT_CNT_STEP_U2    0x0000FFFFU
-#define PCNT_CNT_STEP_U2_M  (PCNT_CNT_STEP_U2_V << PCNT_CNT_STEP_U2_S)
-#define PCNT_CNT_STEP_U2_V  0x0000FFFFU
-#define PCNT_CNT_STEP_U2_S  0
-/** PCNT_CNT_STEP_LIM_U2 : R/W; bitpos: [31:16]; default: 0;
- *  Configures the step limit value for unit 2.
- */
-#define PCNT_CNT_STEP_LIM_U2    0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U2_M  (PCNT_CNT_STEP_LIM_U2_V << PCNT_CNT_STEP_LIM_U2_S)
-#define PCNT_CNT_STEP_LIM_U2_V  0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U2_S  16
-
-/** PCNT_U1_CHANGE_CONF_REG register
- *  Configuration register for unit $n's step value.
- */
-#define PCNT_U1_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x6c)
-/** PCNT_CNT_STEP_U1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures the step value for unit 1.
- */
-#define PCNT_CNT_STEP_U1    0x0000FFFFU
-#define PCNT_CNT_STEP_U1_M  (PCNT_CNT_STEP_U1_V << PCNT_CNT_STEP_U1_S)
-#define PCNT_CNT_STEP_U1_V  0x0000FFFFU
-#define PCNT_CNT_STEP_U1_S  0
-/** PCNT_CNT_STEP_LIM_U1 : R/W; bitpos: [31:16]; default: 0;
- *  Configures the step limit value for unit 1.
- */
-#define PCNT_CNT_STEP_LIM_U1    0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U1_M  (PCNT_CNT_STEP_LIM_U1_V << PCNT_CNT_STEP_LIM_U1_S)
-#define PCNT_CNT_STEP_LIM_U1_V  0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U1_S  16
-
-/** PCNT_U0_CHANGE_CONF_REG register
- *  Configuration register for unit $n's step value.
- */
-#define PCNT_U0_CHANGE_CONF_REG (DR_REG_PCNT_BASE + 0x70)
-/** PCNT_CNT_STEP_U0 : R/W; bitpos: [15:0]; default: 0;
- *  Configures the step value for unit 0.
- */
-#define PCNT_CNT_STEP_U0    0x0000FFFFU
-#define PCNT_CNT_STEP_U0_M  (PCNT_CNT_STEP_U0_V << PCNT_CNT_STEP_U0_S)
-#define PCNT_CNT_STEP_U0_V  0x0000FFFFU
-#define PCNT_CNT_STEP_U0_S  0
-/** PCNT_CNT_STEP_LIM_U0 : R/W; bitpos: [31:16]; default: 0;
- *  Configures the step limit value for unit 0.
- */
-#define PCNT_CNT_STEP_LIM_U0    0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U0_M  (PCNT_CNT_STEP_LIM_U0_V << PCNT_CNT_STEP_LIM_U0_S)
-#define PCNT_CNT_STEP_LIM_U0_V  0x0000FFFFU
-#define PCNT_CNT_STEP_LIM_U0_S  16
-
-/** PCNT_DATE_REG register
- *  PCNT version control register
- */
-#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc)
-/** PCNT_DATE : R/W; bitpos: [31:0]; default: 571021568;
- *  This is the PCNT version control register.
- */
-#define PCNT_DATE    0xFFFFFFFFU
-#define PCNT_DATE_M  (PCNT_DATE_V << PCNT_DATE_S)
-#define PCNT_DATE_V  0xFFFFFFFFU
-#define PCNT_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pcnt_struct.h b/components/soc/esp32c5/beta3/include/soc/pcnt_struct.h
deleted file mode 100644
index a724547e8e..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pcnt_struct.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of un_conf0 register
- *  Configuration register 0 for unit n
- */
-typedef union {
-    struct {
-        /** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
-         *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
-         *
-         *  Any pulses with width less than this will be ignored when the filter is enabled.
-         */
-        uint32_t filter_thres_un:10;
-        /** filter_en_un : R/W; bitpos: [10]; default: 1;
-         *  This is the enable bit for unit n's input filter.
-         */
-        uint32_t filter_en_un:1;
-        /** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
-         *  This is the enable bit for unit n's zero comparator.
-         */
-        uint32_t thr_zero_en_un:1;
-        /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
-         *  This is the enable bit for unit n's thr_h_lim comparator. Configures it to enable
-         *  the high limit interrupt.
-         */
-        uint32_t thr_h_lim_en_un:1;
-        /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
-         *  This is the enable bit for unit n's thr_l_lim comparator. Configures it to enable
-         *  the low limit interrupt.
-         */
-        uint32_t thr_l_lim_en_un:1;
-        /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for unit n's thres0 comparator.
-         */
-        uint32_t thr_thres0_en_un:1;
-        /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
-         *  This is the enable bit for unit n's thres1 comparator.
-         */
-        uint32_t thr_thres1_en_un:1;
-        /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
-         *  This register sets the behavior when the signal input of channel 0 detects a
-         *  negative edge.
-         *
-         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
-         */
-        uint32_t ch0_neg_mode_un:2;
-        /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
-         *  This register sets the behavior when the signal input of channel 0 detects a
-         *  positive edge.
-         *
-         *  1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter
-         */
-        uint32_t ch0_pos_mode_un:2;
-        /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
-         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
-         *  modified when the control signal is high.
-         *
-         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
-         *  increase).2, 3: Inhibit counter modification
-         */
-        uint32_t ch0_hctrl_mode_un:2;
-        /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
-         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
-         *  modified when the control signal is low.
-         *
-         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
-         *  increase).2, 3: Inhibit counter modification
-         */
-        uint32_t ch0_lctrl_mode_un:2;
-        /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
-         *  This register sets the behavior when the signal input of channel 1 detects a
-         *  negative edge.
-         *
-         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
-         */
-        uint32_t ch1_neg_mode_un:2;
-        /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
-         *  This register sets the behavior when the signal input of channel 1 detects a
-         *  positive edge.
-         *
-         *  1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter
-         */
-        uint32_t ch1_pos_mode_un:2;
-        /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
-         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
-         *  modified when the control signal is high.
-         *
-         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
-         *  increase).2, 3: Inhibit counter modification
-         */
-        uint32_t ch1_hctrl_mode_un:2;
-        /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
-         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
-         *  modified when the control signal is low.
-         *
-         *  0: No modification.1: Invert behavior (increase -> decrease, decrease ->
-         *  increase).2, 3: Inhibit counter modification
-         */
-        uint32_t ch1_lctrl_mode_un:2;
-    };
-    uint32_t val;
-} pcnt_un_conf0_reg_t;
-
-/** Type of un_conf1 register
- *  Configuration register 1 for unit n
- */
-typedef union {
-    struct {
-        /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
-         *  This register is used to configure the thres0 value for unit n.
-         */
-        uint32_t cnt_thres0_un:16;
-        /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
-         *  This register is used to configure the thres1 value for unit n.
-         */
-        uint32_t cnt_thres1_un:16;
-    };
-    uint32_t val;
-} pcnt_un_conf1_reg_t;
-
-/** Type of un_conf2 register
- *  Configuration register 2 for unit n
- */
-typedef union {
-    struct {
-        /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
-         *  This register is used to configure the thr_h_lim value for unit n. When pcnt
-         *  reaches this value, the counter will be cleared to 0.
-         */
-        uint32_t cnt_h_lim_un:16;
-        /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
-         *  This register is used to configure the thr_l_lim value for unit n. When pcnt
-         *  reaches this value, the counter will be cleared to 0.
-         */
-        uint32_t cnt_l_lim_un:16;
-    };
-    uint32_t val;
-} pcnt_un_conf2_reg_t;
-
-/** Type of ctrl register
- *  Control register for all counters
- */
-typedef union {
-    struct {
-        /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
-         *  Set this bit to clear unit 0's counter.
-         */
-        uint32_t pulse_cnt_rst_u0:1;
-        /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to freeze unit 0's counter.
-         */
-        uint32_t cnt_pause_u0:1;
-        /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
-         *  Set this bit to clear unit 1's counter.
-         */
-        uint32_t pulse_cnt_rst_u1:1;
-        /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to freeze unit 1's counter.
-         */
-        uint32_t cnt_pause_u1:1;
-        /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to clear unit 2's counter.
-         */
-        uint32_t pulse_cnt_rst_u2:1;
-        /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
-         *  Set this bit to freeze unit 2's counter.
-         */
-        uint32_t cnt_pause_u2:1;
-        /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
-         *  Set this bit to clear unit 3's counter.
-         */
-        uint32_t pulse_cnt_rst_u3:1;
-        /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to freeze unit 3's counter.
-         */
-        uint32_t cnt_pause_u3:1;
-        /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0;
-         *  Configures this bit to enable unit 0's step comparator.
-         */
-        uint32_t dalta_change_en_u0:1;
-        /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0;
-         *  Configures this bit to enable unit 1's step comparator.
-         */
-        uint32_t dalta_change_en_u1:1;
-        /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0;
-         *  Configures this bit to enable unit 2's step comparator.
-         */
-        uint32_t dalta_change_en_u2:1;
-        /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0;
-         *  Configures this bit to enable unit 3's step comparator.
-         */
-        uint32_t dalta_change_en_u3:1;
-        uint32_t reserved_12:4;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
-         *  and written by application. 0: the registers can not be read or written by
-         *  application
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} pcnt_ctrl_reg_t;
-
-/** Type of change_conf register
- *  Configuration register for unit $n's step value.
- */
-typedef union {
-    struct {
-        /** cnt_step : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the step value for unit 3.
-         */
-        uint32_t cnt_step:16;
-        /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0;
-         *  Configures the step limit value for unit 3.
-         */
-        uint32_t cnt_step_lim:16;
-    };
-    uint32_t val;
-} pcnt_un_change_conf_reg_t;
-
-/** Group: Status Register */
-/** Type of un_cnt register
- *  Counter value for unit n
- */
-typedef union {
-    struct {
-        /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
-         *  This register stores the current pulse count value for unit n.
-         */
-        uint32_t pulse_cnt_un:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcnt_un_cnt_reg_t;
-
-/** Type of un_status register
- *  PNCT UNITn status register
- */
-typedef union {
-    struct {
-        /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
-         *  The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
-         *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
-         *  is negative. 3: pulse counter is positive.
-         */
-        uint32_t cnt_thr_zero_mode_un:2;
-        /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
-         *  The latched value of thres1 event of PCNT_Un when threshold event interrupt is
-         *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
-         *  others
-         */
-        uint32_t cnt_thr_thres1_lat_un:1;
-        /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
-         *  The latched value of thres0 event of PCNT_Un when threshold event interrupt is
-         *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
-         *  others
-         */
-        uint32_t cnt_thr_thres0_lat_un:1;
-        /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
-         *  The latched value of low limit event of PCNT_Un when threshold event interrupt is
-         *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
-         *  valid. 0: others
-         */
-        uint32_t cnt_thr_l_lim_lat_un:1;
-        /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
-         *  The latched value of high limit event of PCNT_Un when threshold event interrupt is
-         *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
-         *  valid. 0: others
-         */
-        uint32_t cnt_thr_h_lim_lat_un:1;
-        /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
-         *  The latched value of zero threshold event of PCNT_Un when threshold event interrupt
-         *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
-         *  valid. 0: others
-         */
-        uint32_t cnt_thr_zero_lat_un:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} pcnt_un_status_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Interrupt raw status register
- */
-typedef union {
-    struct {
-        /** cnt_thr_event_u0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u0_int_raw:1;
-        /** cnt_thr_event_u1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u1_int_raw:1;
-        /** cnt_thr_event_u2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u2_int_raw:1;
-        /** cnt_thr_event_u3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u3_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcnt_int_raw_reg_t;
-
-/** Type of int_st register
- *  Interrupt status register
- */
-typedef union {
-    struct {
-        /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u0_int_st:1;
-        /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u1_int_st:1;
-        /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u2_int_st:1;
-        /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u3_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcnt_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable register
- */
-typedef union {
-    struct {
-        /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u0_int_ena:1;
-        /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u1_int_ena:1;
-        /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u2_int_ena:1;
-        /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u3_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcnt_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear register
- */
-typedef union {
-    struct {
-        /** cnt_thr_event_u0_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u0_int_clr:1;
-        /** cnt_thr_event_u1_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u1_int_clr:1;
-        /** cnt_thr_event_u2_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u2_int_clr:1;
-        /** cnt_thr_event_u3_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
-         */
-        uint32_t cnt_thr_event_u3_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcnt_int_clr_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  PCNT version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 571021568;
-         *  This is the PCNT version control register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} pcnt_date_reg_t;
-
-
-typedef struct pcnt_dev_t {
-    volatile struct {
-        pcnt_un_conf0_reg_t conf0;
-        pcnt_un_conf1_reg_t conf1;
-        pcnt_un_conf2_reg_t conf2;
-    } conf_unit[4];
-    volatile pcnt_un_cnt_reg_t cnt_unit[4];
-    volatile pcnt_int_raw_reg_t int_raw;
-    volatile pcnt_int_st_reg_t int_st;
-    volatile pcnt_int_ena_reg_t int_ena;
-    volatile pcnt_int_clr_reg_t int_clr;
-    volatile pcnt_un_status_reg_t status_unit[4];
-    volatile pcnt_ctrl_reg_t ctrl;
-    volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210
-    uint32_t reserved_074[34];
-    volatile pcnt_date_reg_t date;
-} pcnt_dev_t;
-
-extern pcnt_dev_t PCNT;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pcr_reg.h b/components/soc/esp32c5/beta3/include/soc/pcr_reg.h
deleted file mode 100644
index cab98fdda2..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pcr_reg.h
+++ /dev/null
@@ -1,2551 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PCR_UART0_CONF_REG register
- *  UART0 configuration register
- */
-#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
-/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart0 apb clock
- */
-#define PCR_UART0_CLK_EN    (BIT(0))
-#define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
-#define PCR_UART0_CLK_EN_V  0x00000001U
-#define PCR_UART0_CLK_EN_S  0
-/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart0 module
- */
-#define PCR_UART0_RST_EN    (BIT(1))
-#define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
-#define PCR_UART0_RST_EN_V  0x00000001U
-#define PCR_UART0_RST_EN_S  1
-/** PCR_UART0_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset uart0 module
- */
-#define PCR_UART0_READY    (BIT(2))
-#define PCR_UART0_READY_M  (PCR_UART0_READY_V << PCR_UART0_READY_S)
-#define PCR_UART0_READY_V  0x00000001U
-#define PCR_UART0_READY_S  2
-
-/** PCR_UART0_SCLK_CONF_REG register
- *  UART0_SCLK configuration register
- */
-#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
-/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_A    0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
-#define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_S  0
-/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_B    0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
-#define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_S  6
-/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
-#define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_S  12
-/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz
- */
-#define PCR_UART0_SCLK_SEL    0x00000003U
-#define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
-#define PCR_UART0_SCLK_SEL_V  0x00000003U
-#define PCR_UART0_SCLK_SEL_S  20
-/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART0_SCLK_EN    (BIT(22))
-#define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
-#define PCR_UART0_SCLK_EN_V  0x00000001U
-#define PCR_UART0_SCLK_EN_S  22
-
-/** PCR_UART0_PD_CTRL_REG register
- *  UART0 power control register
- */
-#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
-/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
-#define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PU_S  1
-/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
-#define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PD_S  2
-
-/** PCR_UART1_CONF_REG register
- *  UART1 configuration register
- */
-#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
-/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart1 apb clock
- */
-#define PCR_UART1_CLK_EN    (BIT(0))
-#define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
-#define PCR_UART1_CLK_EN_V  0x00000001U
-#define PCR_UART1_CLK_EN_S  0
-/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart1 module
- */
-#define PCR_UART1_RST_EN    (BIT(1))
-#define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
-#define PCR_UART1_RST_EN_V  0x00000001U
-#define PCR_UART1_RST_EN_S  1
-/** PCR_UART1_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset uart1 module
- */
-#define PCR_UART1_READY    (BIT(2))
-#define PCR_UART1_READY_M  (PCR_UART1_READY_V << PCR_UART1_READY_S)
-#define PCR_UART1_READY_V  0x00000001U
-#define PCR_UART1_READY_S  2
-
-/** PCR_UART1_SCLK_CONF_REG register
- *  UART1_SCLK configuration register
- */
-#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
-/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_A    0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
-#define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_S  0
-/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_B    0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
-#define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_S  6
-/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
-#define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_S  12
-/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz
- */
-#define PCR_UART1_SCLK_SEL    0x00000003U
-#define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
-#define PCR_UART1_SCLK_SEL_V  0x00000003U
-#define PCR_UART1_SCLK_SEL_S  20
-/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART1_SCLK_EN    (BIT(22))
-#define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
-#define PCR_UART1_SCLK_EN_V  0x00000001U
-#define PCR_UART1_SCLK_EN_S  22
-
-/** PCR_UART1_PD_CTRL_REG register
- *  UART1 power control register
- */
-#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
-/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
-#define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PU_S  1
-/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
-#define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PD_S  2
-
-/** PCR_MSPI_CONF_REG register
- *  MSPI configuration register
- */
-#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
-/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mspi apb clock and mspi pll clock
- */
-#define PCR_MSPI_CLK_EN    (BIT(0))
-#define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
-#define PCR_MSPI_CLK_EN_V  0x00000001U
-#define PCR_MSPI_CLK_EN_S  0
-/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mspi module
- */
-#define PCR_MSPI_RST_EN    (BIT(1))
-#define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
-#define PCR_MSPI_RST_EN_V  0x00000001U
-#define PCR_MSPI_RST_EN_S  1
-/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable mspi pll clock
- */
-#define PCR_MSPI_PLL_CLK_EN    (BIT(2))
-#define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
-#define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
-#define PCR_MSPI_PLL_CLK_EN_S  2
-/** PCR_MSPI_READY : RO; bitpos: [3]; default: 1;
- *  Query this field after reset mspi module
- */
-#define PCR_MSPI_READY    (BIT(3))
-#define PCR_MSPI_READY_M  (PCR_MSPI_READY_V << PCR_MSPI_READY_S)
-#define PCR_MSPI_READY_V  0x00000001U
-#define PCR_MSPI_READY_S  3
-
-/** PCR_MSPI_CLK_CONF_REG register
- *  MSPI_CLK configuration register
- */
-#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
-/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
- *  low-speed clock-source such as XTAL/FOSC.
- */
-#define PCR_MSPI_FAST_DIV_NUM    0x000000FFU
-#define PCR_MSPI_FAST_DIV_NUM_M  (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S)
-#define PCR_MSPI_FAST_DIV_NUM_V  0x000000FFU
-#define PCR_MSPI_FAST_DIV_NUM_S  0
-/** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0;
- *  set this field to select clock-source.
- */
-#define PCR_MSPI_FUNC_CLK_SEL    0x00000003U
-#define PCR_MSPI_FUNC_CLK_SEL_M  (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S)
-#define PCR_MSPI_FUNC_CLK_SEL_V  0x00000003U
-#define PCR_MSPI_FUNC_CLK_SEL_S  8
-/** PCR_MSPI_FUNC_CLK_EN : R/W; bitpos: [10]; default: 1;
- *  Set 1 to enable mspi func clock
- */
-#define PCR_MSPI_FUNC_CLK_EN    (BIT(10))
-#define PCR_MSPI_FUNC_CLK_EN_M  (PCR_MSPI_FUNC_CLK_EN_V << PCR_MSPI_FUNC_CLK_EN_S)
-#define PCR_MSPI_FUNC_CLK_EN_V  0x00000001U
-#define PCR_MSPI_FUNC_CLK_EN_S  10
-/** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0;
- *  Set 0 to reset axi_clock domain of mspi module
- */
-#define PCR_MSPI_AXI_RST_EN    (BIT(11))
-#define PCR_MSPI_AXI_RST_EN_M  (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S)
-#define PCR_MSPI_AXI_RST_EN_V  0x00000001U
-#define PCR_MSPI_AXI_RST_EN_S  11
-
-/** PCR_I2C_CONF_REG register
- *  I2C configuration register
- */
-#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20)
-/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2c apb clock
- */
-#define PCR_I2C_CLK_EN    (BIT(0))
-#define PCR_I2C_CLK_EN_M  (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S)
-#define PCR_I2C_CLK_EN_V  0x00000001U
-#define PCR_I2C_CLK_EN_S  0
-/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2c module
- */
-#define PCR_I2C_RST_EN    (BIT(1))
-#define PCR_I2C_RST_EN_M  (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S)
-#define PCR_I2C_RST_EN_V  0x00000001U
-#define PCR_I2C_RST_EN_S  1
-
-/** PCR_I2C_SCLK_CONF_REG register
- *  I2C_SCLK configuration register
- */
-#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
-/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_A    0x0000003FU
-#define PCR_I2C_SCLK_DIV_A_M  (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S)
-#define PCR_I2C_SCLK_DIV_A_V  0x0000003FU
-#define PCR_I2C_SCLK_DIV_A_S  0
-/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_B    0x0000003FU
-#define PCR_I2C_SCLK_DIV_B_M  (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S)
-#define PCR_I2C_SCLK_DIV_B_V  0x0000003FU
-#define PCR_I2C_SCLK_DIV_B_S  6
-/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_NUM    0x000000FFU
-#define PCR_I2C_SCLK_DIV_NUM_M  (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S)
-#define PCR_I2C_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_I2C_SCLK_DIV_NUM_S  12
-/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_I2C_SCLK_SEL    (BIT(20))
-#define PCR_I2C_SCLK_SEL_M  (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S)
-#define PCR_I2C_SCLK_SEL_V  0x00000001U
-#define PCR_I2C_SCLK_SEL_S  20
-/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2c function clock
- */
-#define PCR_I2C_SCLK_EN    (BIT(22))
-#define PCR_I2C_SCLK_EN_M  (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S)
-#define PCR_I2C_SCLK_EN_V  0x00000001U
-#define PCR_I2C_SCLK_EN_S  22
-
-/** PCR_TWAI0_CONF_REG register
- *  TWAI0 configuration register
- */
-#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x28)
-/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable twai0 apb clock
- */
-#define PCR_TWAI0_CLK_EN    (BIT(0))
-#define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
-#define PCR_TWAI0_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_CLK_EN_S  0
-/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset twai0 module
- */
-#define PCR_TWAI0_RST_EN    (BIT(1))
-#define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
-#define PCR_TWAI0_RST_EN_V  0x00000001U
-#define PCR_TWAI0_RST_EN_S  1
-/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset twai0 module
- */
-#define PCR_TWAI0_READY    (BIT(2))
-#define PCR_TWAI0_READY_M  (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S)
-#define PCR_TWAI0_READY_V  0x00000001U
-#define PCR_TWAI0_READY_S  2
-
-/** PCR_TWAI0_FUNC_CLK_CONF_REG register
- *  TWAI0_FUNC_CLK configuration register
- */
-#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x2c)
-/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
-#define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
-#define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_SEL_S  20
-/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable twai0 function clock
- */
-#define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
-#define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
-#define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_EN_S  22
-
-/** PCR_TWAI1_CONF_REG register
- *  TWAI1 configuration register
- */
-#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x30)
-/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable twai1 apb clock
- */
-#define PCR_TWAI1_CLK_EN    (BIT(0))
-#define PCR_TWAI1_CLK_EN_M  (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S)
-#define PCR_TWAI1_CLK_EN_V  0x00000001U
-#define PCR_TWAI1_CLK_EN_S  0
-/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset twai1 module
- */
-#define PCR_TWAI1_RST_EN    (BIT(1))
-#define PCR_TWAI1_RST_EN_M  (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S)
-#define PCR_TWAI1_RST_EN_V  0x00000001U
-#define PCR_TWAI1_RST_EN_S  1
-/** PCR_TWAI1_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset twai1 module
- */
-#define PCR_TWAI1_READY    (BIT(2))
-#define PCR_TWAI1_READY_M  (PCR_TWAI1_READY_V << PCR_TWAI1_READY_S)
-#define PCR_TWAI1_READY_V  0x00000001U
-#define PCR_TWAI1_READY_S  2
-
-/** PCR_TWAI1_FUNC_CLK_CONF_REG register
- *  TWAI1_FUNC_CLK configuration register
- */
-#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x34)
-/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_TWAI1_FUNC_CLK_SEL    (BIT(20))
-#define PCR_TWAI1_FUNC_CLK_SEL_M  (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S)
-#define PCR_TWAI1_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_TWAI1_FUNC_CLK_SEL_S  20
-/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable twai1 function clock
- */
-#define PCR_TWAI1_FUNC_CLK_EN    (BIT(22))
-#define PCR_TWAI1_FUNC_CLK_EN_M  (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S)
-#define PCR_TWAI1_FUNC_CLK_EN_V  0x00000001U
-#define PCR_TWAI1_FUNC_CLK_EN_S  22
-
-/** PCR_UHCI_CONF_REG register
- *  UHCI configuration register
- */
-#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x38)
-/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uhci clock
- */
-#define PCR_UHCI_CLK_EN    (BIT(0))
-#define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
-#define PCR_UHCI_CLK_EN_V  0x00000001U
-#define PCR_UHCI_CLK_EN_S  0
-/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uhci module
- */
-#define PCR_UHCI_RST_EN    (BIT(1))
-#define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
-#define PCR_UHCI_RST_EN_V  0x00000001U
-#define PCR_UHCI_RST_EN_S  1
-/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset uhci module
- */
-#define PCR_UHCI_READY    (BIT(2))
-#define PCR_UHCI_READY_M  (PCR_UHCI_READY_V << PCR_UHCI_READY_S)
-#define PCR_UHCI_READY_V  0x00000001U
-#define PCR_UHCI_READY_S  2
-
-/** PCR_RMT_CONF_REG register
- *  RMT configuration register
- */
-#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x3c)
-/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rmt apb clock
- */
-#define PCR_RMT_CLK_EN    (BIT(0))
-#define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
-#define PCR_RMT_CLK_EN_V  0x00000001U
-#define PCR_RMT_CLK_EN_S  0
-/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rmt module
- */
-#define PCR_RMT_RST_EN    (BIT(1))
-#define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
-#define PCR_RMT_RST_EN_V  0x00000001U
-#define PCR_RMT_RST_EN_S  1
-
-/** PCR_RMT_SCLK_CONF_REG register
- *  RMT_SCLK configuration register
- */
-#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
-/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_A    0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
-#define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_S  0
-/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_B    0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
-#define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_S  6
-/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
- *  The integral part of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
-#define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_S  12
-/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1;
- *  set this field to select clock-source. 0: XTAL, 1(default):  FOSC, 2: 80MHz
- */
-#define PCR_RMT_SCLK_SEL    0x00000003U
-#define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
-#define PCR_RMT_SCLK_SEL_V  0x00000003U
-#define PCR_RMT_SCLK_SEL_S  20
-/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable rmt function clock
- */
-#define PCR_RMT_SCLK_EN    (BIT(22))
-#define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
-#define PCR_RMT_SCLK_EN_V  0x00000001U
-#define PCR_RMT_SCLK_EN_S  22
-
-/** PCR_LEDC_CONF_REG register
- *  LEDC configuration register
- */
-#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x44)
-/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ledc apb clock
- */
-#define PCR_LEDC_CLK_EN    (BIT(0))
-#define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
-#define PCR_LEDC_CLK_EN_V  0x00000001U
-#define PCR_LEDC_CLK_EN_S  0
-/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ledc module
- */
-#define PCR_LEDC_RST_EN    (BIT(1))
-#define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
-#define PCR_LEDC_RST_EN_V  0x00000001U
-#define PCR_LEDC_RST_EN_S  1
-/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ledc module
- */
-#define PCR_LEDC_READY    (BIT(2))
-#define PCR_LEDC_READY_M  (PCR_LEDC_READY_V << PCR_LEDC_READY_S)
-#define PCR_LEDC_READY_V  0x00000001U
-#define PCR_LEDC_READY_S  2
-
-/** PCR_LEDC_SCLK_CONF_REG register
- *  LEDC_SCLK configuration register
- */
-#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x48)
-/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  80MHz, 2: FOSC, 3: XTAL.
- */
-#define PCR_LEDC_SCLK_SEL    0x00000003U
-#define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
-#define PCR_LEDC_SCLK_SEL_V  0x00000003U
-#define PCR_LEDC_SCLK_SEL_S  20
-/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable ledc function clock
- */
-#define PCR_LEDC_SCLK_EN    (BIT(22))
-#define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
-#define PCR_LEDC_SCLK_EN_V  0x00000001U
-#define PCR_LEDC_SCLK_EN_S  22
-
-/** PCR_TIMERGROUP0_CONF_REG register
- *  TIMERGROUP0 configuration register
- */
-#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x4c)
-/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group0 apb clock
- */
-#define PCR_TG0_CLK_EN    (BIT(0))
-#define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
-#define PCR_TG0_CLK_EN_V  0x00000001U
-#define PCR_TG0_CLK_EN_S  0
-/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group0 module
- */
-#define PCR_TG0_RST_EN    (BIT(1))
-#define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
-#define PCR_TG0_RST_EN_V  0x00000001U
-#define PCR_TG0_RST_EN_S  1
-/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset timer_group0 wdt module
- */
-#define PCR_TG0_WDT_READY    (BIT(2))
-#define PCR_TG0_WDT_READY_M  (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S)
-#define PCR_TG0_WDT_READY_V  0x00000001U
-#define PCR_TG0_WDT_READY_S  2
-/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1;
- *  Query this field after reset timer_group0 timer0 module
- */
-#define PCR_TG0_TIMER0_READY    (BIT(3))
-#define PCR_TG0_TIMER0_READY_M  (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S)
-#define PCR_TG0_TIMER0_READY_V  0x00000001U
-#define PCR_TG0_TIMER0_READY_S  3
-/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1;
- *  reserved
- */
-#define PCR_TG0_TIMER1_READY    (BIT(4))
-#define PCR_TG0_TIMER1_READY_M  (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S)
-#define PCR_TG0_TIMER1_READY_V  0x00000001U
-#define PCR_TG0_TIMER1_READY_S  4
-
-/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
- *  TIMERGROUP0_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50)
-/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
-#define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_S  20
-/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 timer clock
- */
-#define PCR_TG0_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
-#define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG0_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
- *  TIMERGROUP0_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54)
-/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_WDT_CLK_SEL    0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
-#define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_S  20
-/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG0_WDT_CLK_EN    (BIT(22))
-#define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
-#define PCR_TG0_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG0_WDT_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_CONF_REG register
- *  TIMERGROUP1 configuration register
- */
-#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x58)
-/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group1 apb clock
- */
-#define PCR_TG1_CLK_EN    (BIT(0))
-#define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
-#define PCR_TG1_CLK_EN_V  0x00000001U
-#define PCR_TG1_CLK_EN_S  0
-/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group1 module
- */
-#define PCR_TG1_RST_EN    (BIT(1))
-#define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
-#define PCR_TG1_RST_EN_V  0x00000001U
-#define PCR_TG1_RST_EN_S  1
-/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset timer_group1 wdt module
- */
-#define PCR_TG1_WDT_READY    (BIT(2))
-#define PCR_TG1_WDT_READY_M  (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S)
-#define PCR_TG1_WDT_READY_V  0x00000001U
-#define PCR_TG1_WDT_READY_S  2
-/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1;
- *  Query this field after reset timer_group1 timer0 module
- */
-#define PCR_TG1_TIMER0_READY    (BIT(3))
-#define PCR_TG1_TIMER0_READY_M  (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S)
-#define PCR_TG1_TIMER0_READY_V  0x00000001U
-#define PCR_TG1_TIMER0_READY_S  3
-/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1;
- *  reserved
- */
-#define PCR_TG1_TIMER1_READY    (BIT(4))
-#define PCR_TG1_TIMER1_READY_M  (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S)
-#define PCR_TG1_TIMER1_READY_V  0x00000001U
-#define PCR_TG1_TIMER1_READY_S  4
-
-/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
- *  TIMERGROUP1_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c)
-/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
-#define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_S  20
-/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group1 timer clock
- */
-#define PCR_TG1_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
-#define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG1_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
- *  TIMERGROUP1_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
-/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_WDT_CLK_SEL    0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
-#define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_S  20
-/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG1_WDT_CLK_EN    (BIT(22))
-#define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
-#define PCR_TG1_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG1_WDT_CLK_EN_S  22
-
-/** PCR_SYSTIMER_CONF_REG register
- *  SYSTIMER configuration register
- */
-#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x64)
-/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable systimer apb clock
- */
-#define PCR_SYSTIMER_CLK_EN    (BIT(0))
-#define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
-#define PCR_SYSTIMER_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_CLK_EN_S  0
-/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset systimer module
- */
-#define PCR_SYSTIMER_RST_EN    (BIT(1))
-#define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
-#define PCR_SYSTIMER_RST_EN_V  0x00000001U
-#define PCR_SYSTIMER_RST_EN_S  1
-/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset systimer module
- */
-#define PCR_SYSTIMER_READY    (BIT(2))
-#define PCR_SYSTIMER_READY_M  (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S)
-#define PCR_SYSTIMER_READY_V  0x00000001U
-#define PCR_SYSTIMER_READY_S  2
-
-/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
- *  SYSTIMER_FUNC_CLK configuration register
- */
-#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
-/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
-#define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
-#define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
-/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable systimer function clock
- */
-#define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
-#define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
-#define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_EN_S  22
-
-/** PCR_I2S_CONF_REG register
- *  I2S configuration register
- */
-#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
-/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2s apb clock
- */
-#define PCR_I2S_CLK_EN    (BIT(0))
-#define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
-#define PCR_I2S_CLK_EN_V  0x00000001U
-#define PCR_I2S_CLK_EN_S  0
-/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2s module
- */
-#define PCR_I2S_RST_EN    (BIT(1))
-#define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
-#define PCR_I2S_RST_EN_V  0x00000001U
-#define PCR_I2S_RST_EN_S  1
-/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1;
- *  Query this field before using i2s rx function, after reset i2s module
- */
-#define PCR_I2S_RX_READY    (BIT(2))
-#define PCR_I2S_RX_READY_M  (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S)
-#define PCR_I2S_RX_READY_V  0x00000001U
-#define PCR_I2S_RX_READY_S  2
-/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1;
- *  Query this field before using i2s tx function, after reset i2s module
- */
-#define PCR_I2S_TX_READY    (BIT(3))
-#define PCR_I2S_TX_READY_M  (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S)
-#define PCR_I2S_TX_READY_V  0x00000001U
-#define PCR_I2S_TX_READY_S  3
-
-/** PCR_I2S_TX_CLKM_CONF_REG register
- *  I2S_TX_CLKM configuration register
- */
-#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
-/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
- *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
- *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
- *  (n+1)-div] + y * (n+1)-div.
- */
-#define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
-#define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
- *  I2S_MCLK_in.
- */
-#define PCR_I2S_TX_CLKM_SEL    0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
-#define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_S  20
-/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_tx function clock
- */
-#define PCR_I2S_TX_CLKM_EN    (BIT(22))
-#define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
-#define PCR_I2S_TX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_TX_CLKM_EN_S  22
-
-/** PCR_I2S_TX_CLKM_DIV_CONF_REG register
- *  I2S_TX_CLKM_DIV configuration register
- */
-#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
-/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
-#define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_S  0
-/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
-#define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_S  9
-/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
-#define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_S  18
-/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
-#define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_TX_CLKM_DIV_YN1_S  27
-
-/** PCR_I2S_RX_CLKM_CONF_REG register
- *  I2S_RX_CLKM configuration register
- */
-#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
-/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S clock divider value
- */
-#define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
-#define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
- */
-#define PCR_I2S_RX_CLKM_SEL    0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
-#define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_S  20
-/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_rx function clock
- */
-#define PCR_I2S_RX_CLKM_EN    (BIT(22))
-#define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
-#define PCR_I2S_RX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_RX_CLKM_EN_S  22
-/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
- *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
- */
-#define PCR_I2S_MCLK_SEL    (BIT(23))
-#define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
-#define PCR_I2S_MCLK_SEL_V  0x00000001U
-#define PCR_I2S_MCLK_SEL_S  23
-
-/** PCR_I2S_RX_CLKM_DIV_CONF_REG register
- *  I2S_RX_CLKM_DIV configuration register
- */
-#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
-/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
-#define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_S  0
-/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
-#define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_S  9
-/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
-#define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_S  18
-/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
-#define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_RX_CLKM_DIV_YN1_S  27
-
-/** PCR_SARADC_CONF_REG register
- *  SARADC configuration register
- */
-#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
-/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  no use
- */
-#define PCR_SARADC_CLK_EN    (BIT(0))
-#define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
-#define PCR_SARADC_CLK_EN_V  0x00000001U
-#define PCR_SARADC_CLK_EN_S  0
-/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset function_register of saradc module
- */
-#define PCR_SARADC_RST_EN    (BIT(1))
-#define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
-#define PCR_SARADC_RST_EN_V  0x00000001U
-#define PCR_SARADC_RST_EN_S  1
-/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable saradc apb clock
- */
-#define PCR_SARADC_REG_CLK_EN    (BIT(2))
-#define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
-#define PCR_SARADC_REG_CLK_EN_V  0x00000001U
-#define PCR_SARADC_REG_CLK_EN_S  2
-/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
- *  Set 0 to reset apb_register of saradc module
- */
-#define PCR_SARADC_REG_RST_EN    (BIT(3))
-#define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
-#define PCR_SARADC_REG_RST_EN_V  0x00000001U
-#define PCR_SARADC_REG_RST_EN_S  3
-
-/** PCR_SARADC_CLKM_CONF_REG register
- *  SARADC_CLKM configuration register
- */
-#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
-/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_A    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
-#define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_S  0
-/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_B    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
-#define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_S  6
-/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
-#define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_S  12
-/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SARADC_CLKM_SEL    0x00000003U
-#define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
-#define PCR_SARADC_CLKM_SEL_V  0x00000003U
-#define PCR_SARADC_CLKM_SEL_S  20
-/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable saradc function clock
- */
-#define PCR_SARADC_CLKM_EN    (BIT(22))
-#define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
-#define PCR_SARADC_CLKM_EN_V  0x00000001U
-#define PCR_SARADC_CLKM_EN_S  22
-
-/** PCR_TSENS_CLK_CONF_REG register
- *  TSENS_CLK configuration register
- */
-#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
-/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
- */
-#define PCR_TSENS_CLK_SEL    (BIT(20))
-#define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
-#define PCR_TSENS_CLK_SEL_V  0x00000001U
-#define PCR_TSENS_CLK_SEL_S  20
-/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable tsens clock
- */
-#define PCR_TSENS_CLK_EN    (BIT(22))
-#define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
-#define PCR_TSENS_CLK_EN_V  0x00000001U
-#define PCR_TSENS_CLK_EN_S  22
-/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
- *  Set 0 to reset tsens module
- */
-#define PCR_TSENS_RST_EN    (BIT(23))
-#define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
-#define PCR_TSENS_RST_EN_V  0x00000001U
-#define PCR_TSENS_RST_EN_S  23
-
-/** PCR_USB_DEVICE_CONF_REG register
- *  USB_DEVICE configuration register
- */
-#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
-/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable usb_device clock
- */
-#define PCR_USB_DEVICE_CLK_EN    (BIT(0))
-#define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
-#define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
-#define PCR_USB_DEVICE_CLK_EN_S  0
-/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset usb_device module
- */
-#define PCR_USB_DEVICE_RST_EN    (BIT(1))
-#define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
-#define PCR_USB_DEVICE_RST_EN_V  0x00000001U
-#define PCR_USB_DEVICE_RST_EN_S  1
-/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset usb_device module
- */
-#define PCR_USB_DEVICE_READY    (BIT(2))
-#define PCR_USB_DEVICE_READY_M  (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S)
-#define PCR_USB_DEVICE_READY_V  0x00000001U
-#define PCR_USB_DEVICE_READY_S  2
-
-/** PCR_INTMTX_CONF_REG register
- *  INTMTX configuration register
- */
-#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
-/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable intmtx clock
- */
-#define PCR_INTMTX_CLK_EN    (BIT(0))
-#define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
-#define PCR_INTMTX_CLK_EN_V  0x00000001U
-#define PCR_INTMTX_CLK_EN_S  0
-/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset intmtx module
- */
-#define PCR_INTMTX_RST_EN    (BIT(1))
-#define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
-#define PCR_INTMTX_RST_EN_V  0x00000001U
-#define PCR_INTMTX_RST_EN_S  1
-/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset intmtx module
- */
-#define PCR_INTMTX_READY    (BIT(2))
-#define PCR_INTMTX_READY_M  (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S)
-#define PCR_INTMTX_READY_V  0x00000001U
-#define PCR_INTMTX_READY_S  2
-
-/** PCR_PCNT_CONF_REG register
- *  PCNT configuration register
- */
-#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
-/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pcnt clock
- */
-#define PCR_PCNT_CLK_EN    (BIT(0))
-#define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
-#define PCR_PCNT_CLK_EN_V  0x00000001U
-#define PCR_PCNT_CLK_EN_S  0
-/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pcnt module
- */
-#define PCR_PCNT_RST_EN    (BIT(1))
-#define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
-#define PCR_PCNT_RST_EN_V  0x00000001U
-#define PCR_PCNT_RST_EN_S  1
-/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset pcnt module
- */
-#define PCR_PCNT_READY    (BIT(2))
-#define PCR_PCNT_READY_M  (PCR_PCNT_READY_V << PCR_PCNT_READY_S)
-#define PCR_PCNT_READY_V  0x00000001U
-#define PCR_PCNT_READY_S  2
-
-/** PCR_ETM_CONF_REG register
- *  ETM configuration register
- */
-#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
-/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable etm clock
- */
-#define PCR_ETM_CLK_EN    (BIT(0))
-#define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
-#define PCR_ETM_CLK_EN_V  0x00000001U
-#define PCR_ETM_CLK_EN_S  0
-/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset etm module
- */
-#define PCR_ETM_RST_EN    (BIT(1))
-#define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
-#define PCR_ETM_RST_EN_V  0x00000001U
-#define PCR_ETM_RST_EN_S  1
-/** PCR_ETM_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset etm module
- */
-#define PCR_ETM_READY    (BIT(2))
-#define PCR_ETM_READY_M  (PCR_ETM_READY_V << PCR_ETM_READY_S)
-#define PCR_ETM_READY_V  0x00000001U
-#define PCR_ETM_READY_S  2
-
-/** PCR_PWM_CONF_REG register
- *  PWM configuration register
- */
-#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
-/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pwm clock
- */
-#define PCR_PWM_CLK_EN    (BIT(0))
-#define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
-#define PCR_PWM_CLK_EN_V  0x00000001U
-#define PCR_PWM_CLK_EN_S  0
-/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pwm module
- */
-#define PCR_PWM_RST_EN    (BIT(1))
-#define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
-#define PCR_PWM_RST_EN_V  0x00000001U
-#define PCR_PWM_RST_EN_S  1
-/** PCR_PWM_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset pwm module
- */
-#define PCR_PWM_READY    (BIT(2))
-#define PCR_PWM_READY_M  (PCR_PWM_READY_V << PCR_PWM_READY_S)
-#define PCR_PWM_READY_V  0x00000001U
-#define PCR_PWM_READY_S  2
-
-/** PCR_PWM_CLK_CONF_REG register
- *  PWM_CLK configuration register
- */
-#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
-/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the pwm function clock.
- */
-#define PCR_PWM_DIV_NUM    0x000000FFU
-#define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
-#define PCR_PWM_DIV_NUM_V  0x000000FFU
-#define PCR_PWM_DIV_NUM_S  12
-/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  160MHz, 2: XTAL, 3: FOSC.
- */
-#define PCR_PWM_CLKM_SEL    0x00000003U
-#define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
-#define PCR_PWM_CLKM_SEL_V  0x00000003U
-#define PCR_PWM_CLKM_SEL_S  20
-/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  set this field as 1 to activate pwm clkm.
- */
-#define PCR_PWM_CLKM_EN    (BIT(22))
-#define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
-#define PCR_PWM_CLKM_EN_V  0x00000001U
-#define PCR_PWM_CLKM_EN_S  22
-
-/** PCR_PARL_IO_CONF_REG register
- *  PARL_IO configuration register
- */
-#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
-/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable parl apb clock
- */
-#define PCR_PARL_CLK_EN    (BIT(0))
-#define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
-#define PCR_PARL_CLK_EN_V  0x00000001U
-#define PCR_PARL_CLK_EN_S  0
-/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset parl apb reg
- */
-#define PCR_PARL_RST_EN    (BIT(1))
-#define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
-#define PCR_PARL_RST_EN_V  0x00000001U
-#define PCR_PARL_RST_EN_S  1
-/** PCR_PARL_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset parl module
- */
-#define PCR_PARL_READY    (BIT(2))
-#define PCR_PARL_READY_M  (PCR_PARL_READY_V << PCR_PARL_READY_S)
-#define PCR_PARL_READY_V  0x00000001U
-#define PCR_PARL_READY_S  2
-
-/** PCR_PARL_CLK_RX_CONF_REG register
- *  PARL_CLK_RX configuration register
- */
-#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
-/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl rx clock.
- */
-#define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
-#define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_S  0
-/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_RX_SEL    0x00000003U
-#define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
-#define PCR_PARL_CLK_RX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_RX_SEL_S  16
-/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl rx clock
- */
-#define PCR_PARL_CLK_RX_EN    (BIT(18))
-#define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
-#define PCR_PARL_CLK_RX_EN_V  0x00000001U
-#define PCR_PARL_CLK_RX_EN_S  18
-/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl rx module
- */
-#define PCR_PARL_RX_RST_EN    (BIT(19))
-#define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
-#define PCR_PARL_RX_RST_EN_V  0x00000001U
-#define PCR_PARL_RX_RST_EN_S  19
-
-/** PCR_PARL_CLK_TX_CONF_REG register
- *  PARL_CLK_TX configuration register
- */
-#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
-/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl tx clock.
- */
-#define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
-#define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_S  0
-/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_TX_SEL    0x00000003U
-#define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
-#define PCR_PARL_CLK_TX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_TX_SEL_S  16
-/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl tx clock
- */
-#define PCR_PARL_CLK_TX_EN    (BIT(18))
-#define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
-#define PCR_PARL_CLK_TX_EN_V  0x00000001U
-#define PCR_PARL_CLK_TX_EN_S  18
-/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl tx module
- */
-#define PCR_PARL_TX_RST_EN    (BIT(19))
-#define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
-#define PCR_PARL_TX_RST_EN_V  0x00000001U
-#define PCR_PARL_TX_RST_EN_S  19
-
-/** PCR_PVT_MONITOR_CONF_REG register
- *  PVT_MONITOR configuration register
- */
-#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0)
-/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable apb clock of pvt module
- */
-#define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
-#define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
-#define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_CLK_EN_S  0
-/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset all pvt monitor module
- */
-#define PCR_PVT_MONITOR_RST_EN    (BIT(1))
-#define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
-#define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_RST_EN_S  1
-/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable function clock of modem pvt module
- */
-#define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
-/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  Set 1 to enable function clock of cpu pvt module
- */
-#define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
-/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  Set 1 to enable function clock of hp_peri pvt module
- */
-#define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
-
-/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
- *  PVT_MONITOR function clock configuration register
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4)
-/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
- *  The integral part of the frequency divider factor of the pvt_monitor function clock.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
-/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
- *  divided by 3.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
-/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable source clock of pvt sitex
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
-
-/** PCR_GDMA_CONF_REG register
- *  GDMA configuration register
- */
-#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8)
-/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable gdma clock
- */
-#define PCR_GDMA_CLK_EN    (BIT(0))
-#define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
-#define PCR_GDMA_CLK_EN_V  0x00000001U
-#define PCR_GDMA_CLK_EN_S  0
-/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset gdma module
- */
-#define PCR_GDMA_RST_EN    (BIT(1))
-#define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
-#define PCR_GDMA_RST_EN_V  0x00000001U
-#define PCR_GDMA_RST_EN_S  1
-
-/** PCR_SPI2_CONF_REG register
- *  SPI2 configuration register
- */
-#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc)
-/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable spi2 apb clock
- */
-#define PCR_SPI2_CLK_EN    (BIT(0))
-#define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
-#define PCR_SPI2_CLK_EN_V  0x00000001U
-#define PCR_SPI2_CLK_EN_S  0
-/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset spi2 module
- */
-#define PCR_SPI2_RST_EN    (BIT(1))
-#define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
-#define PCR_SPI2_RST_EN_V  0x00000001U
-#define PCR_SPI2_RST_EN_S  1
-/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset spi2 module
- */
-#define PCR_SPI2_READY    (BIT(2))
-#define PCR_SPI2_READY_M  (PCR_SPI2_READY_V << PCR_SPI2_READY_S)
-#define PCR_SPI2_READY_V  0x00000001U
-#define PCR_SPI2_READY_S  2
-
-/** PCR_SPI2_CLKM_CONF_REG register
- *  SPI2_CLKM configuration register
- */
-#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0)
-/** PCR_SPI2_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the spi2_mst clock.
- */
-#define PCR_SPI2_CLKM_DIV_NUM    0x000000FFU
-#define PCR_SPI2_CLKM_DIV_NUM_M  (PCR_SPI2_CLKM_DIV_NUM_V << PCR_SPI2_CLKM_DIV_NUM_S)
-#define PCR_SPI2_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_SPI2_CLKM_DIV_NUM_S  12
-/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SPI2_CLKM_SEL    0x00000003U
-#define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
-#define PCR_SPI2_CLKM_SEL_V  0x00000003U
-#define PCR_SPI2_CLKM_SEL_S  20
-/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable spi2 function clock
- */
-#define PCR_SPI2_CLKM_EN    (BIT(22))
-#define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
-#define PCR_SPI2_CLKM_EN_V  0x00000001U
-#define PCR_SPI2_CLKM_EN_S  22
-
-/** PCR_AES_CONF_REG register
- *  AES configuration register
- */
-#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4)
-/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable aes clock
- */
-#define PCR_AES_CLK_EN    (BIT(0))
-#define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
-#define PCR_AES_CLK_EN_V  0x00000001U
-#define PCR_AES_CLK_EN_S  0
-/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset aes module
- */
-#define PCR_AES_RST_EN    (BIT(1))
-#define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
-#define PCR_AES_RST_EN_V  0x00000001U
-#define PCR_AES_RST_EN_S  1
-/** PCR_AES_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset aes module
- */
-#define PCR_AES_READY    (BIT(2))
-#define PCR_AES_READY_M  (PCR_AES_READY_V << PCR_AES_READY_S)
-#define PCR_AES_READY_V  0x00000001U
-#define PCR_AES_READY_S  2
-
-/** PCR_SHA_CONF_REG register
- *  SHA configuration register
- */
-#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8)
-/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable sha clock
- */
-#define PCR_SHA_CLK_EN    (BIT(0))
-#define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
-#define PCR_SHA_CLK_EN_V  0x00000001U
-#define PCR_SHA_CLK_EN_S  0
-/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset sha module
- */
-#define PCR_SHA_RST_EN    (BIT(1))
-#define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
-#define PCR_SHA_RST_EN_V  0x00000001U
-#define PCR_SHA_RST_EN_S  1
-/** PCR_SHA_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset sha module
- */
-#define PCR_SHA_READY    (BIT(2))
-#define PCR_SHA_READY_M  (PCR_SHA_READY_V << PCR_SHA_READY_S)
-#define PCR_SHA_READY_V  0x00000001U
-#define PCR_SHA_READY_S  2
-
-/** PCR_RSA_CONF_REG register
- *  RSA configuration register
- */
-#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
-/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rsa clock
- */
-#define PCR_RSA_CLK_EN    (BIT(0))
-#define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
-#define PCR_RSA_CLK_EN_V  0x00000001U
-#define PCR_RSA_CLK_EN_S  0
-/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rsa module
- */
-#define PCR_RSA_RST_EN    (BIT(1))
-#define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
-#define PCR_RSA_RST_EN_V  0x00000001U
-#define PCR_RSA_RST_EN_S  1
-/** PCR_RSA_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset rsa module
- */
-#define PCR_RSA_READY    (BIT(2))
-#define PCR_RSA_READY_M  (PCR_RSA_READY_V << PCR_RSA_READY_S)
-#define PCR_RSA_READY_V  0x00000001U
-#define PCR_RSA_READY_S  2
-
-/** PCR_RSA_PD_CTRL_REG register
- *  RSA power control register
- */
-#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0)
-/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down rsa internal memory.
- */
-#define PCR_RSA_MEM_PD    (BIT(0))
-#define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
-#define PCR_RSA_MEM_PD_V  0x00000001U
-#define PCR_RSA_MEM_PD_S  0
-/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up rsa internal memory
- */
-#define PCR_RSA_MEM_FORCE_PU    (BIT(1))
-#define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
-#define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PU_S  1
-/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down rsa internal memory.
- */
-#define PCR_RSA_MEM_FORCE_PD    (BIT(2))
-#define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
-#define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PD_S  2
-
-/** PCR_ECC_CONF_REG register
- *  ECC configuration register
- */
-#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4)
-/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ecc clock
- */
-#define PCR_ECC_CLK_EN    (BIT(0))
-#define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
-#define PCR_ECC_CLK_EN_V  0x00000001U
-#define PCR_ECC_CLK_EN_S  0
-/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ecc module
- */
-#define PCR_ECC_RST_EN    (BIT(1))
-#define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
-#define PCR_ECC_RST_EN_V  0x00000001U
-#define PCR_ECC_RST_EN_S  1
-/** PCR_ECC_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ecc module
- */
-#define PCR_ECC_READY    (BIT(2))
-#define PCR_ECC_READY_M  (PCR_ECC_READY_V << PCR_ECC_READY_S)
-#define PCR_ECC_READY_V  0x00000001U
-#define PCR_ECC_READY_S  2
-
-/** PCR_ECC_PD_CTRL_REG register
- *  ECC power control register
- */
-#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8)
-/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down ecc internal memory.
- */
-#define PCR_ECC_MEM_PD    (BIT(0))
-#define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
-#define PCR_ECC_MEM_PD_V  0x00000001U
-#define PCR_ECC_MEM_PD_S  0
-/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up ecc internal memory
- */
-#define PCR_ECC_MEM_FORCE_PU    (BIT(1))
-#define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
-#define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PU_S  1
-/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down ecc internal memory.
- */
-#define PCR_ECC_MEM_FORCE_PD    (BIT(2))
-#define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
-#define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PD_S  2
-
-/** PCR_DS_CONF_REG register
- *  DS configuration register
- */
-#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc)
-/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ds clock
- */
-#define PCR_DS_CLK_EN    (BIT(0))
-#define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
-#define PCR_DS_CLK_EN_V  0x00000001U
-#define PCR_DS_CLK_EN_S  0
-/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ds module
- */
-#define PCR_DS_RST_EN    (BIT(1))
-#define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
-#define PCR_DS_RST_EN_V  0x00000001U
-#define PCR_DS_RST_EN_S  1
-/** PCR_DS_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ds module
- */
-#define PCR_DS_READY    (BIT(2))
-#define PCR_DS_READY_M  (PCR_DS_READY_V << PCR_DS_READY_S)
-#define PCR_DS_READY_V  0x00000001U
-#define PCR_DS_READY_S  2
-
-/** PCR_HMAC_CONF_REG register
- *  HMAC configuration register
- */
-#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0)
-/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable hmac clock
- */
-#define PCR_HMAC_CLK_EN    (BIT(0))
-#define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
-#define PCR_HMAC_CLK_EN_V  0x00000001U
-#define PCR_HMAC_CLK_EN_S  0
-/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset hmac module
- */
-#define PCR_HMAC_RST_EN    (BIT(1))
-#define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
-#define PCR_HMAC_RST_EN_V  0x00000001U
-#define PCR_HMAC_RST_EN_S  1
-/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset hmac module
- */
-#define PCR_HMAC_READY    (BIT(2))
-#define PCR_HMAC_READY_M  (PCR_HMAC_READY_V << PCR_HMAC_READY_S)
-#define PCR_HMAC_READY_V  0x00000001U
-#define PCR_HMAC_READY_S  2
-
-/** PCR_ECDSA_CONF_REG register
- *  ECDSA configuration register
- */
-#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4)
-/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ecdsa clock
- */
-#define PCR_ECDSA_CLK_EN    (BIT(0))
-#define PCR_ECDSA_CLK_EN_M  (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S)
-#define PCR_ECDSA_CLK_EN_V  0x00000001U
-#define PCR_ECDSA_CLK_EN_S  0
-/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ecdsa module
- */
-#define PCR_ECDSA_RST_EN    (BIT(1))
-#define PCR_ECDSA_RST_EN_M  (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S)
-#define PCR_ECDSA_RST_EN_V  0x00000001U
-#define PCR_ECDSA_RST_EN_S  1
-/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ecdsa module
- */
-#define PCR_ECDSA_READY    (BIT(2))
-#define PCR_ECDSA_READY_M  (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S)
-#define PCR_ECDSA_READY_V  0x00000001U
-#define PCR_ECDSA_READY_S  2
-
-/** PCR_IOMUX_CONF_REG register
- *  IOMUX configuration register
- */
-#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
-/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable iomux apb clock
- */
-#define PCR_IOMUX_CLK_EN    (BIT(0))
-#define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
-#define PCR_IOMUX_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_CLK_EN_S  0
-/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset iomux module
- */
-#define PCR_IOMUX_RST_EN    (BIT(1))
-#define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
-#define PCR_IOMUX_RST_EN_V  0x00000001U
-#define PCR_IOMUX_RST_EN_S  1
-
-/** PCR_IOMUX_CLK_CONF_REG register
- *  IOMUX_CLK configuration register
- */
-#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
-/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
-#define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_S  20
-/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable iomux function clock
- */
-#define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
-#define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
-#define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_FUNC_CLK_EN_S  22
-
-/** PCR_MEM_MONITOR_CONF_REG register
- *  MEM_MONITOR configuration register
- */
-#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
-/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mem_monitor clock
- */
-#define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
-#define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
-#define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_CLK_EN_S  0
-/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mem_monitor module
- */
-#define PCR_MEM_MONITOR_RST_EN    (BIT(1))
-#define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
-#define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_RST_EN_S  1
-/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset mem_monitor module
- */
-#define PCR_MEM_MONITOR_READY    (BIT(2))
-#define PCR_MEM_MONITOR_READY_M  (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S)
-#define PCR_MEM_MONITOR_READY_V  0x00000001U
-#define PCR_MEM_MONITOR_READY_S  2
-
-/** PCR_REGDMA_CONF_REG register
- *  REGDMA configuration register
- */
-#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
-/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable regdma clock
- */
-#define PCR_REGDMA_CLK_EN    (BIT(0))
-#define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
-#define PCR_REGDMA_CLK_EN_V  0x00000001U
-#define PCR_REGDMA_CLK_EN_S  0
-/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset regdma module
- */
-#define PCR_REGDMA_RST_EN    (BIT(1))
-#define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
-#define PCR_REGDMA_RST_EN_V  0x00000001U
-#define PCR_REGDMA_RST_EN_S  1
-
-/** PCR_TRACE_CONF_REG register
- *  TRACE configuration register
- */
-#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8)
-/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable trace clock
- */
-#define PCR_TRACE_CLK_EN    (BIT(0))
-#define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
-#define PCR_TRACE_CLK_EN_V  0x00000001U
-#define PCR_TRACE_CLK_EN_S  0
-/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset trace module
- */
-#define PCR_TRACE_RST_EN    (BIT(1))
-#define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
-#define PCR_TRACE_RST_EN_V  0x00000001U
-#define PCR_TRACE_RST_EN_S  1
-
-/** PCR_ASSIST_CONF_REG register
- *  ASSIST configuration register
- */
-#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc)
-/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable assist clock
- */
-#define PCR_ASSIST_CLK_EN    (BIT(0))
-#define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
-#define PCR_ASSIST_CLK_EN_V  0x00000001U
-#define PCR_ASSIST_CLK_EN_S  0
-/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset assist module
- */
-#define PCR_ASSIST_RST_EN    (BIT(1))
-#define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
-#define PCR_ASSIST_RST_EN_V  0x00000001U
-#define PCR_ASSIST_RST_EN_S  1
-
-/** PCR_CACHE_CONF_REG register
- *  CACHE configuration register
- */
-#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100)
-/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable cache clock
- */
-#define PCR_CACHE_CLK_EN    (BIT(0))
-#define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
-#define PCR_CACHE_CLK_EN_V  0x00000001U
-#define PCR_CACHE_CLK_EN_S  0
-/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cache module
- */
-#define PCR_CACHE_RST_EN    (BIT(1))
-#define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
-#define PCR_CACHE_RST_EN_V  0x00000001U
-#define PCR_CACHE_RST_EN_S  1
-
-/** PCR_MODEM_CONF_REG register
- *  MODEM_APB configuration register
- */
-#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104)
-/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set this file as 1 to reset modem-subsystem.
- */
-#define PCR_MODEM_RST_EN    (BIT(2))
-#define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
-#define PCR_MODEM_RST_EN_V  0x00000001U
-#define PCR_MODEM_RST_EN_S  2
-
-/** PCR_TIMEOUT_CONF_REG register
- *  TIMEOUT configuration register
- */
-#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108)
-/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cpu_peri timeout module
- */
-#define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
-#define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
-#define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_CPU_TIMEOUT_RST_EN_S  1
-/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
- */
-#define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
-#define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
-#define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_HP_TIMEOUT_RST_EN_S  2
-
-/** PCR_SYSCLK_CONF_REG register
- *  SYSCLK configuration register
- */
-#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c)
-/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
- *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
- *  clock-source such as XTAL/FOSC.
- */
-#define PCR_LS_DIV_NUM    0x000000FFU
-#define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
-#define PCR_LS_DIV_NUM_V  0x000000FFU
-#define PCR_LS_DIV_NUM_S  0
-/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
- *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
- */
-#define PCR_HS_DIV_NUM    0x000000FFU
-#define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
-#define PCR_HS_DIV_NUM_V  0x000000FFU
-#define PCR_HS_DIV_NUM_S  8
-/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  This field is used to select clock source. 0: XTAL, 1: FOSC, 2: 160M_PLL, 3:
- *  240M_PLL.
- */
-#define PCR_SOC_CLK_SEL    0x00000003U
-#define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
-#define PCR_SOC_CLK_SEL_V  0x00000003U
-#define PCR_SOC_CLK_SEL_S  16
-/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40;
- *  This field indicates the frequency(MHz) of XTAL.
- */
-#define PCR_CLK_XTAL_FREQ    0x0000007FU
-#define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
-#define PCR_CLK_XTAL_FREQ_V  0x0000007FU
-#define PCR_CLK_XTAL_FREQ_S  24
-
-/** PCR_CPU_WAITI_CONF_REG register
- *  CPU_WAITI configuration register
- */
-#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110)
-/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
- */
-#define PCR_CPUPERIOD_SEL    0x00000003U
-#define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
-#define PCR_CPUPERIOD_SEL_V  0x00000003U
-#define PCR_CPUPERIOD_SEL_S  0
-/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
- */
-#define PCR_PLL_FREQ_SEL    (BIT(2))
-#define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
-#define PCR_PLL_FREQ_SEL_V  0x00000001U
-#define PCR_PLL_FREQ_SEL_S  2
-/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
- *  Set 1 to force cpu_waiti_clk enable.
- */
-#define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
-#define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
-#define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
-#define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
-/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
- *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
- *  will close
- */
-#define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
-#define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_S  4
-
-/** PCR_CPU_FREQ_CONF_REG register
- *  CPU_FREQ configuration register
- */
-#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114)
-/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
- *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
- */
-#define PCR_CPU_DIV_NUM    0x000000FFU
-#define PCR_CPU_DIV_NUM_M  (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S)
-#define PCR_CPU_DIV_NUM_V  0x000000FFU
-#define PCR_CPU_DIV_NUM_S  0
-
-/** PCR_AHB_FREQ_CONF_REG register
- *  AHB_FREQ configuration register
- */
-#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
-/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
- *  low-speed clock-source such as XTAL/FOSC, and should be used together with
- *  PCR_CPU_DIV_NUM.
- */
-#define PCR_AHB_DIV_NUM    0x000000FFU
-#define PCR_AHB_DIV_NUM_M  (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S)
-#define PCR_AHB_DIV_NUM_V  0x000000FFU
-#define PCR_AHB_DIV_NUM_S  0
-
-/** PCR_APB_FREQ_CONF_REG register
- *  APB_FREQ configuration register
- */
-#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
-/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
- *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
- *  recover to the previous frequency when a new access appears on apb-bus. Set as one
- *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
- *  that enable this function will reduce performance. Users can set this field as zero
- *  to disable the auto-decrease-apb-freq function. By default, this function is
- *  disable.
- */
-#define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
-#define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_S  0
-/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
- *  div1(default)/div2/div4 of clk_ahb.
- */
-#define PCR_APB_DIV_NUM    0x000000FFU
-#define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
-#define PCR_APB_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DIV_NUM_S  8
-
-/** PCR_SYSCLK_FREQ_QUERY_0_REG register
- *  SYSCLK frequency query 0 register
- */
-#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120)
-/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8;
- *  This field indicates the frequency(MHz) of FOSC.
- */
-#define PCR_FOSC_FREQ    0x000000FFU
-#define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
-#define PCR_FOSC_FREQ_V  0x000000FFU
-#define PCR_FOSC_FREQ_S  0
-/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96;
- *  This field indicates the frequency(MHz) of SPLL.
- */
-#define PCR_PLL_FREQ    0x000003FFU
-#define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
-#define PCR_PLL_FREQ_V  0x000003FFU
-#define PCR_PLL_FREQ_S  8
-
-/** PCR_PLL_DIV_CLK_EN_REG register
- *  SPLL DIV clock-gating configuration register
- */
-#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124)
-/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_240M_CLK_EN    (BIT(0))
-#define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
-#define PCR_PLL_240M_CLK_EN_V  0x00000001U
-#define PCR_PLL_240M_CLK_EN_S  0
-/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_160M_CLK_EN    (BIT(1))
-#define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
-#define PCR_PLL_160M_CLK_EN_V  0x00000001U
-#define PCR_PLL_160M_CLK_EN_S  1
-/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_120M_CLK_EN    (BIT(2))
-#define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
-#define PCR_PLL_120M_CLK_EN_V  0x00000001U
-#define PCR_PLL_120M_CLK_EN_S  2
-/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_80M_CLK_EN    (BIT(3))
-#define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
-#define PCR_PLL_80M_CLK_EN_V  0x00000001U
-#define PCR_PLL_80M_CLK_EN_S  3
-/** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_60M_CLK_EN    (BIT(4))
-#define PCR_PLL_60M_CLK_EN_M  (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S)
-#define PCR_PLL_60M_CLK_EN_V  0x00000001U
-#define PCR_PLL_60M_CLK_EN_S  4
-/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_48M_CLK_EN    (BIT(5))
-#define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
-#define PCR_PLL_48M_CLK_EN_V  0x00000001U
-#define PCR_PLL_48M_CLK_EN_S  5
-/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_40M_CLK_EN    (BIT(6))
-#define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
-#define PCR_PLL_40M_CLK_EN_V  0x00000001U
-#define PCR_PLL_40M_CLK_EN_S  6
-/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1;
- *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_20M_CLK_EN    (BIT(7))
-#define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
-#define PCR_PLL_20M_CLK_EN_V  0x00000001U
-#define PCR_PLL_20M_CLK_EN_S  7
-/** PCR_PLL_12M_CLK_EN : R/W; bitpos: [8]; default: 1;
- *  This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_12M_CLK_EN    (BIT(8))
-#define PCR_PLL_12M_CLK_EN_M  (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S)
-#define PCR_PLL_12M_CLK_EN_V  0x00000001U
-#define PCR_PLL_12M_CLK_EN_S  8
-
-/** PCR_CTRL_CLK_OUT_EN_REG register
- *  CLK_OUT_EN configuration register
- */
-#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128)
-/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable 20m clock
- */
-#define PCR_CLK20_OEN    (BIT(0))
-#define PCR_CLK20_OEN_M  (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S)
-#define PCR_CLK20_OEN_V  0x00000001U
-#define PCR_CLK20_OEN_S  0
-/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1;
- *  Set 1 to enable 22m clock
- */
-#define PCR_CLK22_OEN    (BIT(1))
-#define PCR_CLK22_OEN_M  (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S)
-#define PCR_CLK22_OEN_V  0x00000001U
-#define PCR_CLK22_OEN_S  1
-/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable 44m clock
- */
-#define PCR_CLK44_OEN    (BIT(2))
-#define PCR_CLK44_OEN_M  (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S)
-#define PCR_CLK44_OEN_V  0x00000001U
-#define PCR_CLK44_OEN_S  2
-/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1;
- *  Set 1 to enable bb clock
- */
-#define PCR_CLK_BB_OEN    (BIT(3))
-#define PCR_CLK_BB_OEN_M  (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S)
-#define PCR_CLK_BB_OEN_V  0x00000001U
-#define PCR_CLK_BB_OEN_S  3
-/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1;
- *  Set 1 to enable 80m clock
- */
-#define PCR_CLK80_OEN    (BIT(4))
-#define PCR_CLK80_OEN_M  (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S)
-#define PCR_CLK80_OEN_V  0x00000001U
-#define PCR_CLK80_OEN_S  4
-/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1;
- *  Set 1 to enable 160m clock
- */
-#define PCR_CLK160_OEN    (BIT(5))
-#define PCR_CLK160_OEN_M  (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S)
-#define PCR_CLK160_OEN_V  0x00000001U
-#define PCR_CLK160_OEN_S  5
-/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1;
- *  Set 1 to enable 320m clock
- */
-#define PCR_CLK_320M_OEN    (BIT(6))
-#define PCR_CLK_320M_OEN_M  (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S)
-#define PCR_CLK_320M_OEN_V  0x00000001U
-#define PCR_CLK_320M_OEN_S  6
-/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_ADC_INF_OEN    (BIT(7))
-#define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
-#define PCR_CLK_ADC_INF_OEN_V  0x00000001U
-#define PCR_CLK_ADC_INF_OEN_S  7
-/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_DAC_CPU_OEN    (BIT(8))
-#define PCR_CLK_DAC_CPU_OEN_M  (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S)
-#define PCR_CLK_DAC_CPU_OEN_V  0x00000001U
-#define PCR_CLK_DAC_CPU_OEN_S  8
-/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1;
- *  Reserved
- */
-#define PCR_CLK40X_BB_OEN    (BIT(9))
-#define PCR_CLK40X_BB_OEN_M  (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S)
-#define PCR_CLK40X_BB_OEN_V  0x00000001U
-#define PCR_CLK40X_BB_OEN_S  9
-/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1;
- *  Set 1 to enable xtal clock
- */
-#define PCR_CLK_XTAL_OEN    (BIT(10))
-#define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
-#define PCR_CLK_XTAL_OEN_V  0x00000001U
-#define PCR_CLK_XTAL_OEN_S  10
-
-/** PCR_CTRL_TICK_CONF_REG register
- *  TICK configuration register
- */
-#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c)
-/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
- *  ******* Description ***********
- */
-#define PCR_XTAL_TICK_NUM    0x000000FFU
-#define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
-#define PCR_XTAL_TICK_NUM_V  0x000000FFU
-#define PCR_XTAL_TICK_NUM_S  0
-/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
- *  ******* Description ***********
- */
-#define PCR_FOSC_TICK_NUM    0x000000FFU
-#define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
-#define PCR_FOSC_TICK_NUM_V  0x000000FFU
-#define PCR_FOSC_TICK_NUM_S  8
-/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
- *  ******* Description ***********
- */
-#define PCR_TICK_ENABLE    (BIT(16))
-#define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
-#define PCR_TICK_ENABLE_V  0x00000001U
-#define PCR_TICK_ENABLE_S  16
-/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
- *  ******* Description ***********
- */
-#define PCR_RST_TICK_CNT    (BIT(17))
-#define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
-#define PCR_RST_TICK_CNT_V  0x00000001U
-#define PCR_RST_TICK_CNT_S  17
-
-/** PCR_CTRL_32K_CONF_REG register
- *  32KHz clock configuration register
- */
-#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130)
-/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
- *  This field indicates which one 32KHz clock will be used by timergroup. 0:
- *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
- */
-#define PCR_32K_SEL    0x00000003U
-#define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
-#define PCR_32K_SEL_V  0x00000003U
-#define PCR_32K_SEL_S  0
-
-/** PCR_SRAM_POWER_CONF_0_REG register
- *  HP SRAM/ROM configuration register
- */
-#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134)
-/** PCR_ROM_FORCE_PU : R/W; bitpos: [2:0]; default: 7;
- *  Set this bit to force power up ROM
- */
-#define PCR_ROM_FORCE_PU    0x00000007U
-#define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
-#define PCR_ROM_FORCE_PU_V  0x00000007U
-#define PCR_ROM_FORCE_PU_S  0
-/** PCR_ROM_FORCE_PD : R/W; bitpos: [5:3]; default: 0;
- *  Set this bit to force power down ROM.
- */
-#define PCR_ROM_FORCE_PD    0x00000007U
-#define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
-#define PCR_ROM_FORCE_PD_V  0x00000007U
-#define PCR_ROM_FORCE_PD_S  3
-/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [8:6]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
- *  gate-clock will be used when accessing the ROM.
- */
-#define PCR_ROM_CLKGATE_FORCE_ON    0x00000007U
-#define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
-#define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000007U
-#define PCR_ROM_CLKGATE_FORCE_ON_S  6
-
-/** PCR_SRAM_POWER_CONF_1_REG register
- *  HP SRAM/ROM configuration register
- */
-#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138)
-/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15;
- *  Set this bit to force power up SRAM
- */
-#define PCR_SRAM_FORCE_PU    0x0000000FU
-#define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
-#define PCR_SRAM_FORCE_PU_V  0x0000000FU
-#define PCR_SRAM_FORCE_PU_S  0
-/** PCR_SRAM_FORCE_PD : R/W; bitpos: [13:10]; default: 0;
- *  Set this bit to force power down SRAM.
- */
-#define PCR_SRAM_FORCE_PD    0x0000000FU
-#define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
-#define PCR_SRAM_FORCE_PD_V  0x0000000FU
-#define PCR_SRAM_FORCE_PD_S  10
-/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [23:20]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
- *  gate-clock will be used when accessing the SRAM.
- */
-#define PCR_SRAM_CLKGATE_FORCE_ON    0x0000000FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
-#define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000000FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_S  20
-
-/** PCR_SEC_CONF_REG register
- *  xxxx
- */
-#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c)
-/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
- *  xxxx
- */
-#define PCR_SEC_CLK_SEL    0x00000003U
-#define PCR_SEC_CLK_SEL_M  (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S)
-#define PCR_SEC_CLK_SEL_V  0x00000003U
-#define PCR_SEC_CLK_SEL_S  0
-/** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set 0 to reset sec module
- */
-#define PCR_SEC_RST_EN    (BIT(2))
-#define PCR_SEC_RST_EN_M  (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S)
-#define PCR_SEC_RST_EN_V  0x00000001U
-#define PCR_SEC_RST_EN_S  2
-
-/** PCR_ADC_DAC_INV_PHASE_CONF_REG register
- *  xxxx
- */
-#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140)
-/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
- *  xxxx
- */
-#define PCR_CLK_RX_ADC_INV_PHASE_ENA    (BIT(0))
-#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M  (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S)
-#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V  0x00000001U
-#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S  0
-/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0;
- *  xxxx
- */
-#define PCR_CLK_TX_DAC_INV_PHASE_ENA    (BIT(1))
-#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M  (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S)
-#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V  0x00000001U
-#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S  1
-/** PCR_CLK_PWDET_ADC_INV_PHASE_ENA : R/W; bitpos: [2]; default: 0;
- *  xxxx
- */
-#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA    (BIT(2))
-#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_M  (PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V << PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S)
-#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_V  0x00000001U
-#define PCR_CLK_PWDET_ADC_INV_PHASE_ENA_S  2
-
-/** PCR_BUS_CLK_UPDATE_REG register
- *  xxxx
- */
-#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148)
-/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0;
- *  xxxx
- */
-#define PCR_BUS_CLOCK_UPDATE    (BIT(0))
-#define PCR_BUS_CLOCK_UPDATE_M  (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S)
-#define PCR_BUS_CLOCK_UPDATE_V  0x00000001U
-#define PCR_BUS_CLOCK_UPDATE_S  0
-
-/** PCR_SAR_CLK_DIV_REG register
- *  xxxx
- */
-#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c)
-/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
- *  xxxx
- */
-#define PCR_SAR2_CLK_DIV_NUM    0x000000FFU
-#define PCR_SAR2_CLK_DIV_NUM_M  (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S)
-#define PCR_SAR2_CLK_DIV_NUM_V  0x000000FFU
-#define PCR_SAR2_CLK_DIV_NUM_S  0
-/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
- *  xxxx
- */
-#define PCR_SAR1_CLK_DIV_NUM    0x000000FFU
-#define PCR_SAR1_CLK_DIV_NUM_M  (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S)
-#define PCR_SAR1_CLK_DIV_NUM_V  0x000000FFU
-#define PCR_SAR1_CLK_DIV_NUM_S  8
-
-/** PCR_PWDET_SAR_CLK_CONF_REG register
- *  xxxx
- */
-#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150)
-/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7;
- *  xxxx
- */
-#define PCR_PWDET_SAR_CLK_DIV_NUM    0x000000FFU
-#define PCR_PWDET_SAR_CLK_DIV_NUM_M  (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S)
-#define PCR_PWDET_SAR_CLK_DIV_NUM_V  0x000000FFU
-#define PCR_PWDET_SAR_CLK_DIV_NUM_S  0
-/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1;
- *  xxxx
- */
-#define PCR_PWDET_SAR_CLK_EN    (BIT(8))
-#define PCR_PWDET_SAR_CLK_EN_M  (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S)
-#define PCR_PWDET_SAR_CLK_EN_V  0x00000001U
-#define PCR_PWDET_SAR_CLK_EN_S  8
-
-/** PCR_SDIO_SLAVE_CONF_REG register
- *  SDIO_SLAVE configuration register
- */
-#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x154)
-/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable sdio_slave clock
- */
-#define PCR_SDIO_SLAVE_CLK_EN    (BIT(0))
-#define PCR_SDIO_SLAVE_CLK_EN_M  (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S)
-#define PCR_SDIO_SLAVE_CLK_EN_V  0x00000001U
-#define PCR_SDIO_SLAVE_CLK_EN_S  0
-/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset sdio_slave module
- */
-#define PCR_SDIO_SLAVE_RST_EN    (BIT(1))
-#define PCR_SDIO_SLAVE_RST_EN_M  (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S)
-#define PCR_SDIO_SLAVE_RST_EN_V  0x00000001U
-#define PCR_SDIO_SLAVE_RST_EN_S  1
-
-/** PCR_USB_OTG_CONF_REG register
- *  USB_OTG configuration register
- */
-#define PCR_USB_OTG_CONF_REG (DR_REG_PCR_BASE + 0x158)
-/** PCR_USB_OTG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable usb_otg bus clock
- */
-#define PCR_USB_OTG_CLK_EN    (BIT(0))
-#define PCR_USB_OTG_CLK_EN_M  (PCR_USB_OTG_CLK_EN_V << PCR_USB_OTG_CLK_EN_S)
-#define PCR_USB_OTG_CLK_EN_V  0x00000001U
-#define PCR_USB_OTG_CLK_EN_S  0
-/** PCR_USB_OTG_ADP_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset usb_otg core adp
- */
-#define PCR_USB_OTG_ADP_RST_EN    (BIT(1))
-#define PCR_USB_OTG_ADP_RST_EN_M  (PCR_USB_OTG_ADP_RST_EN_V << PCR_USB_OTG_ADP_RST_EN_S)
-#define PCR_USB_OTG_ADP_RST_EN_V  0x00000001U
-#define PCR_USB_OTG_ADP_RST_EN_S  1
-/** PCR_USB_OTG_MISC_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set 0 to reset usb_otg misc
- */
-#define PCR_USB_OTG_MISC_RST_EN    (BIT(2))
-#define PCR_USB_OTG_MISC_RST_EN_M  (PCR_USB_OTG_MISC_RST_EN_V << PCR_USB_OTG_MISC_RST_EN_S)
-#define PCR_USB_OTG_MISC_RST_EN_V  0x00000001U
-#define PCR_USB_OTG_MISC_RST_EN_S  2
-/** PCR_USB_OTG_GLOBAL_RST_EN : R/W; bitpos: [3]; default: 0;
- *  Set 0 to reset usb_otg module
- */
-#define PCR_USB_OTG_GLOBAL_RST_EN    (BIT(3))
-#define PCR_USB_OTG_GLOBAL_RST_EN_M  (PCR_USB_OTG_GLOBAL_RST_EN_V << PCR_USB_OTG_GLOBAL_RST_EN_S)
-#define PCR_USB_OTG_GLOBAL_RST_EN_V  0x00000001U
-#define PCR_USB_OTG_GLOBAL_RST_EN_S  3
-
-/** PCR_USB_OTG_CLK_CONF_REG register
- *  USB_OTG func clk configuration register
- */
-#define PCR_USB_OTG_CLK_CONF_REG (DR_REG_PCR_BASE + 0x15c)
-/** PCR_USB_OTG_PHY_REFCLK_SEL : R/W; bitpos: [20]; default: 1;
- *  Set 1 to sel 12m pll clock, set 0 to sel pad clock
- */
-#define PCR_USB_OTG_PHY_REFCLK_SEL    (BIT(20))
-#define PCR_USB_OTG_PHY_REFCLK_SEL_M  (PCR_USB_OTG_PHY_REFCLK_SEL_V << PCR_USB_OTG_PHY_REFCLK_SEL_S)
-#define PCR_USB_OTG_PHY_REFCLK_SEL_V  0x00000001U
-#define PCR_USB_OTG_PHY_REFCLK_SEL_S  20
-/** PCR_USB_OTG_PHY_REFCLK_EN : R/W; bitpos: [21]; default: 1;
- *  Set 1 to enable usb_otg_phy_refclk clock
- */
-#define PCR_USB_OTG_PHY_REFCLK_EN    (BIT(21))
-#define PCR_USB_OTG_PHY_REFCLK_EN_M  (PCR_USB_OTG_PHY_REFCLK_EN_V << PCR_USB_OTG_PHY_REFCLK_EN_S)
-#define PCR_USB_OTG_PHY_REFCLK_EN_V  0x00000001U
-#define PCR_USB_OTG_PHY_REFCLK_EN_S  21
-/** PCR_USB_OTG_ADP_CLK_SEL : R/W; bitpos: [23:22]; default: 0;
- *  Set 0 to sel clock from gpio_matrix, set 1 to sel osc32k, set 2 to sel xtal32k, set
- *  3 to sel ext32k
- */
-#define PCR_USB_OTG_ADP_CLK_SEL    0x00000003U
-#define PCR_USB_OTG_ADP_CLK_SEL_M  (PCR_USB_OTG_ADP_CLK_SEL_V << PCR_USB_OTG_ADP_CLK_SEL_S)
-#define PCR_USB_OTG_ADP_CLK_SEL_V  0x00000003U
-#define PCR_USB_OTG_ADP_CLK_SEL_S  22
-/** PCR_USB_OTG_ADP_CLK_EN : R/W; bitpos: [24]; default: 1;
- *  Set 1 to enable usb_otg_adp_clk clock
- */
-#define PCR_USB_OTG_ADP_CLK_EN    (BIT(24))
-#define PCR_USB_OTG_ADP_CLK_EN_M  (PCR_USB_OTG_ADP_CLK_EN_V << PCR_USB_OTG_ADP_CLK_EN_S)
-#define PCR_USB_OTG_ADP_CLK_EN_V  0x00000001U
-#define PCR_USB_OTG_ADP_CLK_EN_S  24
-
-/** PCR_BS_CONF_REG register
- *  BS configuration register
- */
-#define PCR_BS_CONF_REG (DR_REG_PCR_BASE + 0x160)
-/** PCR_BS_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable bs clock
- */
-#define PCR_BS_CLK_EN    (BIT(0))
-#define PCR_BS_CLK_EN_M  (PCR_BS_CLK_EN_V << PCR_BS_CLK_EN_S)
-#define PCR_BS_CLK_EN_V  0x00000001U
-#define PCR_BS_CLK_EN_S  0
-/** PCR_BS_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset bs module
- */
-#define PCR_BS_RST_EN    (BIT(1))
-#define PCR_BS_RST_EN_M  (PCR_BS_RST_EN_V << PCR_BS_RST_EN_S)
-#define PCR_BS_RST_EN_V  0x00000001U
-#define PCR_BS_RST_EN_S  1
-
-/** PCR_BS_FUNC_CONF_REG register
- *  BS_FUNC_CLK configuration register
- */
-#define PCR_BS_FUNC_CONF_REG (DR_REG_PCR_BASE + 0x164)
-/** PCR_BS_TX_RST_EN : R/W; bitpos: [23]; default: 0;
- *  Set 0 to reset bs tx module
- */
-#define PCR_BS_TX_RST_EN    (BIT(23))
-#define PCR_BS_TX_RST_EN_M  (PCR_BS_TX_RST_EN_V << PCR_BS_TX_RST_EN_S)
-#define PCR_BS_TX_RST_EN_V  0x00000001U
-#define PCR_BS_TX_RST_EN_S  23
-/** PCR_BS_RX_RST_EN : R/W; bitpos: [24]; default: 0;
- *  Set 0 to reset bs rx module
- */
-#define PCR_BS_RX_RST_EN    (BIT(24))
-#define PCR_BS_RX_RST_EN_M  (PCR_BS_RX_RST_EN_V << PCR_BS_RX_RST_EN_S)
-#define PCR_BS_RX_RST_EN_V  0x00000001U
-#define PCR_BS_RX_RST_EN_S  24
-
-/** PCR_TIMERGROUP_WDT_CONF_REG register
- *  TIMERGROUP_WDT configuration register
- */
-#define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x168)
-/** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0;
- *  Set 0 to reset timer_group0 wdt module
- */
-#define PCR_TG0_WDT_RST_EN    (BIT(0))
-#define PCR_TG0_WDT_RST_EN_M  (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S)
-#define PCR_TG0_WDT_RST_EN_V  0x00000001U
-#define PCR_TG0_WDT_RST_EN_S  0
-/** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group1 wdt module
- */
-#define PCR_TG1_WDT_RST_EN    (BIT(1))
-#define PCR_TG1_WDT_RST_EN_M  (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S)
-#define PCR_TG1_WDT_RST_EN_V  0x00000001U
-#define PCR_TG1_WDT_RST_EN_S  1
-
-/** PCR_TIMERGROUP_XTAL_CONF_REG register
- *  TIMERGROUP1 configuration register
- */
-#define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x16c)
-/** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0;
- *  Set 0 to reset timer_group0 xtal clock domain
- */
-#define PCR_TG0_XTAL_RST_EN    (BIT(0))
-#define PCR_TG0_XTAL_RST_EN_M  (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S)
-#define PCR_TG0_XTAL_RST_EN_V  0x00000001U
-#define PCR_TG0_XTAL_RST_EN_S  0
-/** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group1 xtal clock domain
- */
-#define PCR_TG1_XTAL_RST_EN    (BIT(1))
-#define PCR_TG1_XTAL_RST_EN_M  (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S)
-#define PCR_TG1_XTAL_RST_EN_V  0x00000001U
-#define PCR_TG1_XTAL_RST_EN_S  1
-
-/** PCR_KM_CONF_REG register
- *  Key Manager configuration register
- */
-#define PCR_KM_CONF_REG (DR_REG_PCR_BASE + 0x170)
-/** PCR_KM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable km clock
- */
-#define PCR_KM_CLK_EN    (BIT(0))
-#define PCR_KM_CLK_EN_M  (PCR_KM_CLK_EN_V << PCR_KM_CLK_EN_S)
-#define PCR_KM_CLK_EN_V  0x00000001U
-#define PCR_KM_CLK_EN_S  0
-/** PCR_KM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset km module
- */
-#define PCR_KM_RST_EN    (BIT(1))
-#define PCR_KM_RST_EN_M  (PCR_KM_RST_EN_V << PCR_KM_RST_EN_S)
-#define PCR_KM_RST_EN_V  0x00000001U
-#define PCR_KM_RST_EN_S  1
-/** PCR_KM_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset km module
- */
-#define PCR_KM_READY    (BIT(2))
-#define PCR_KM_READY_M  (PCR_KM_READY_V << PCR_KM_READY_S)
-#define PCR_KM_READY_V  0x00000001U
-#define PCR_KM_READY_S  2
-
-/** PCR_RESET_EVENT_BYPASS_REG register
- *  reset event bypass backdoor configuration register
- */
-#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
-/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
- *  This field is used to control reset event relationship for
- *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
- *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
- *  will not only be reset by power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
-#define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
-#define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_APM_S  0
-/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
- *  This field is used to control reset event relationship for system-bus. 1: system
- *  bus (including arbiter/router) will only be reset by power-reset. some reset event
- *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
- *  power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS    (BIT(1))
-#define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
-#define PCR_RESET_EVENT_BYPASS_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_S  1
-
-/** PCR_FPGA_DEBUG_REG register
- *  fpga debug register
- */
-#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
-/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
- *  Only used in fpga debug.
- */
-#define PCR_FPGA_DEBUG    0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
-#define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_S  0
-
-/** PCR_CLOCK_GATE_REG register
- *  PCR clock gating configure register
- */
-#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
-/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to force on clock gating.
- */
-#define PCR_CLK_EN    (BIT(0))
-#define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
-#define PCR_CLK_EN_V  0x00000001U
-#define PCR_CLK_EN_S  0
-
-/** PCR_DATE_REG register
- *  Date register.
- */
-#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
-/** PCR_DATE : R/W; bitpos: [27:0]; default: 36720976;
- *  PCR version information.
- */
-#define PCR_DATE    0x0FFFFFFFU
-#define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
-#define PCR_DATE_V  0x0FFFFFFFU
-#define PCR_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pcr_struct.h b/components/soc/esp32c5/beta3/include/soc/pcr_struct.h
deleted file mode 100644
index 41c20e12b5..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pcr_struct.h
+++ /dev/null
@@ -1,2239 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of uart0_conf register
- *  UART0 configuration register
- */
-typedef union {
-    struct {
-        /** uart0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uart0 apb clock
-         */
-        uint32_t uart0_clk_en:1;
-        /** uart0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uart0 module
-         */
-        uint32_t uart0_rst_en:1;
-        /** uart0_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset uart0 module
-         */
-        uint32_t uart0_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart0_conf_reg_t;
-
-/** Type of uart0_sclk_conf register
- *  UART0_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_a:6;
-        /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_b:6;
-        /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_num:8;
-        /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz
-         */
-        uint32_t uart0_sclk_sel:2;
-        /** uart0_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable uart0 function clock
-         */
-        uint32_t uart0_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_uart0_sclk_conf_reg_t;
-
-/** Type of uart0_pd_ctrl register
- *  UART0 power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power down UART0 memory.
-         */
-        uint32_t uart0_mem_force_pu:1;
-        /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power up UART0 memory.
-         */
-        uint32_t uart0_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart0_pd_ctrl_reg_t;
-
-/** Type of uart1_conf register
- *  UART1 configuration register
- */
-typedef union {
-    struct {
-        /** uart1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uart1 apb clock
-         */
-        uint32_t uart1_clk_en:1;
-        /** uart1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uart1 module
-         */
-        uint32_t uart1_rst_en:1;
-        /** uart1_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset uart1 module
-         */
-        uint32_t uart1_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart1_conf_reg_t;
-
-/** Type of uart1_sclk_conf register
- *  UART1_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_a:6;
-        /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_b:6;
-        /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_num:8;
-        /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1: fosc, 2: 80MHz
-         */
-        uint32_t uart1_sclk_sel:2;
-        /** uart1_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable uart0 function clock
-         */
-        uint32_t uart1_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_uart1_sclk_conf_reg_t;
-
-/** Type of uart1_pd_ctrl register
- *  UART1 power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power down UART1 memory.
-         */
-        uint32_t uart1_mem_force_pu:1;
-        /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power up UART1 memory.
-         */
-        uint32_t uart1_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart1_pd_ctrl_reg_t;
-
-/** Type of mspi_conf register
- *  MSPI configuration register
- */
-typedef union {
-    struct {
-        /** mspi_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable mspi apb clock and mspi pll clock
-         */
-        uint32_t mspi_clk_en:1;
-        /** mspi_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset mspi module
-         */
-        uint32_t mspi_rst_en:1;
-        /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable mspi pll clock
-         */
-        uint32_t mspi_pll_clk_en:1;
-        /** mspi_ready : RO; bitpos: [3]; default: 1;
-         *  Query this field after reset mspi module
-         */
-        uint32_t mspi_ready:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_mspi_conf_reg_t;
-
-/** Type of mspi_clk_conf register
- *  MSPI_CLK configuration register
- */
-typedef union {
-    struct {
-        /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
-         *  low-speed clock-source such as XTAL/FOSC.
-         */
-        uint32_t mspi_fast_div_num:8;
-        /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0;
-         *  set this field to select clock-source.
-         */
-        uint32_t mspi_func_clk_sel:2;
-        /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1;
-         *  Set 1 to enable mspi func clock
-         */
-        uint32_t mspi_func_clk_en:1;
-        /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0;
-         *  Set 0 to reset axi_clock domain of mspi module
-         */
-        uint32_t mspi_axi_rst_en:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} pcr_mspi_clk_conf_reg_t;
-
-/** Type of i2c_conf register
- *  I2C configuration register
- */
-typedef union {
-    struct {
-        /** i2c_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable i2c apb clock
-         */
-        uint32_t i2c_clk_en:1;
-        /** i2c_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset i2c module
-         */
-        uint32_t i2c_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_i2c_conf_reg_t;
-
-/** Type of i2c_sclk_conf register
- *  I2C_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_a:6;
-        /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_b:6;
-        /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_num:8;
-        /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t i2c_sclk_sel:1;
-        uint32_t reserved_21:1;
-        /** i2c_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2c function clock
-         */
-        uint32_t i2c_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_i2c_sclk_conf_reg_t;
-
-/** Type of twai0_conf register
- *  TWAI0 configuration register
- */
-typedef union {
-    struct {
-        /** twai0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable twai0 apb clock
-         */
-        uint32_t twai0_clk_en:1;
-        /** twai0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset twai0 module
-         */
-        uint32_t twai0_rst_en:1;
-        /** twai0_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset twai0 module
-         */
-        uint32_t twai0_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_twai0_conf_reg_t;
-
-/** Type of twai0_func_clk_conf register
- *  TWAI0_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t twai0_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable twai0 function clock
-         */
-        uint32_t twai0_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_twai0_func_clk_conf_reg_t;
-
-/** Type of twai1_conf register
- *  TWAI1 configuration register
- */
-typedef union {
-    struct {
-        /** twai1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable twai1 apb clock
-         */
-        uint32_t twai1_clk_en:1;
-        /** twai1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset twai1 module
-         */
-        uint32_t twai1_rst_en:1;
-        /** twai1_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset twai1 module
-         */
-        uint32_t twai1_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_twai1_conf_reg_t;
-
-/** Type of twai1_func_clk_conf register
- *  TWAI1_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t twai1_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** twai1_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable twai1 function clock
-         */
-        uint32_t twai1_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_twai1_func_clk_conf_reg_t;
-
-/** Type of uhci_conf register
- *  UHCI configuration register
- */
-typedef union {
-    struct {
-        /** uhci_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uhci clock
-         */
-        uint32_t uhci_clk_en:1;
-        /** uhci_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uhci module
-         */
-        uint32_t uhci_rst_en:1;
-        /** uhci_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset uhci module
-         */
-        uint32_t uhci_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uhci_conf_reg_t;
-
-/** Type of rmt_conf register
- *  RMT configuration register
- */
-typedef union {
-    struct {
-        /** rmt_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable rmt apb clock
-         */
-        uint32_t rmt_clk_en:1;
-        /** rmt_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset rmt module
-         */
-        uint32_t rmt_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_rmt_conf_reg_t;
-
-/** Type of rmt_sclk_conf register
- *  RMT_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_a:6;
-        /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_b:6;
-        /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_num:8;
-        /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1;
-         *  set this field to select clock-source. 0: XTAL, 1(default):  FOSC, 2: 80MHz
-         */
-        uint32_t rmt_sclk_sel:2;
-        /** rmt_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable rmt function clock
-         */
-        uint32_t rmt_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_rmt_sclk_conf_reg_t;
-
-/** Type of ledc_conf register
- *  LEDC configuration register
- */
-typedef union {
-    struct {
-        /** ledc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ledc apb clock
-         */
-        uint32_t ledc_clk_en:1;
-        /** ledc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ledc module
-         */
-        uint32_t ledc_rst_en:1;
-        /** ledc_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ledc module
-         */
-        uint32_t ledc_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ledc_conf_reg_t;
-
-/** Type of ledc_sclk_conf register
- *  LEDC_SCLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
-         *  80MHz, 2: FOSC, 3: XTAL.
-         */
-        uint32_t ledc_sclk_sel:2;
-        /** ledc_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable ledc function clock
-         */
-        uint32_t ledc_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_ledc_sclk_conf_reg_t;
-
-/** Type of timergroup0_conf register
- *  TIMERGROUP0 configuration register
- */
-typedef union {
-    struct {
-        /** tg0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable timer_group0 apb clock
-         */
-        uint32_t tg0_clk_en:1;
-        /** tg0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group0 module
-         */
-        uint32_t tg0_rst_en:1;
-        /** tg0_wdt_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset timer_group0 wdt module
-         */
-        uint32_t tg0_wdt_ready:1;
-        /** tg0_timer0_ready : RO; bitpos: [3]; default: 1;
-         *  Query this field after reset timer_group0 timer0 module
-         */
-        uint32_t tg0_timer0_ready:1;
-        /** tg0_timer1_ready : RO; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t tg0_timer1_ready:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} pcr_timergroup0_conf_reg_t;
-
-/** Type of timergroup0_timer_clk_conf register
- *  TIMERGROUP0_TIMER_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg0_timer_clk_sel:2;
-        /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 timer clock
-         */
-        uint32_t tg0_timer_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup0_timer_clk_conf_reg_t;
-
-/** Type of timergroup0_wdt_clk_conf register
- *  TIMERGROUP0_WDT_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg0_wdt_clk_sel:2;
-        /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 wdt clock
-         */
-        uint32_t tg0_wdt_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup0_wdt_clk_conf_reg_t;
-
-/** Type of timergroup1_conf register
- *  TIMERGROUP1 configuration register
- */
-typedef union {
-    struct {
-        /** tg1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable timer_group1 apb clock
-         */
-        uint32_t tg1_clk_en:1;
-        /** tg1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group1 module
-         */
-        uint32_t tg1_rst_en:1;
-        /** tg1_wdt_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset timer_group1 wdt module
-         */
-        uint32_t tg1_wdt_ready:1;
-        /** tg1_timer0_ready : RO; bitpos: [3]; default: 1;
-         *  Query this field after reset timer_group1 timer0 module
-         */
-        uint32_t tg1_timer0_ready:1;
-        /** tg1_timer1_ready : RO; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t tg1_timer1_ready:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} pcr_timergroup1_conf_reg_t;
-
-/** Type of timergroup1_timer_clk_conf register
- *  TIMERGROUP1_TIMER_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg1_timer_clk_sel:2;
-        /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group1 timer clock
-         */
-        uint32_t tg1_timer_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup1_timer_clk_conf_reg_t;
-
-/** Type of timergroup1_wdt_clk_conf register
- *  TIMERGROUP1_WDT_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg1_wdt_clk_sel:2;
-        /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 wdt clock
-         */
-        uint32_t tg1_wdt_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup1_wdt_clk_conf_reg_t;
-
-/** Type of systimer_conf register
- *  SYSTIMER configuration register
- */
-typedef union {
-    struct {
-        /** systimer_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable systimer apb clock
-         */
-        uint32_t systimer_clk_en:1;
-        /** systimer_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset systimer module
-         */
-        uint32_t systimer_rst_en:1;
-        /** systimer_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset systimer module
-         */
-        uint32_t systimer_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_systimer_conf_reg_t;
-
-/** Type of systimer_func_clk_conf register
- *  SYSTIMER_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t systimer_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable systimer function clock
-         */
-        uint32_t systimer_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_systimer_func_clk_conf_reg_t;
-
-/** Type of i2s_conf register
- *  I2S configuration register
- */
-typedef union {
-    struct {
-        /** i2s_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable i2s apb clock
-         */
-        uint32_t i2s_clk_en:1;
-        /** i2s_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset i2s module
-         */
-        uint32_t i2s_rst_en:1;
-        /** i2s_rx_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field before using i2s rx function, after reset i2s module
-         */
-        uint32_t i2s_rx_ready:1;
-        /** i2s_tx_ready : RO; bitpos: [3]; default: 1;
-         *  Query this field before using i2s tx function, after reset i2s module
-         */
-        uint32_t i2s_tx_ready:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_i2s_conf_reg_t;
-
-/** Type of i2s_tx_clkm_conf register
- *  I2S_TX_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
-         *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
-         *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
-         *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
-         *  (n+1)-div] + y * (n+1)-div.
-         */
-        uint32_t i2s_tx_clkm_div_num:8;
-        /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
-         *  I2S_MCLK_in.
-         */
-        uint32_t i2s_tx_clkm_sel:2;
-        /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2s_tx function clock
-         */
-        uint32_t i2s_tx_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_i2s_tx_clkm_conf_reg_t;
-
-/** Type of i2s_tx_clkm_div_conf register
- *  I2S_TX_CLKM_DIV configuration register
- */
-typedef union {
-    struct {
-        /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_Z is (a-b).
-         */
-        uint32_t i2s_tx_clkm_div_z:9;
-        /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
-         */
-        uint32_t i2s_tx_clkm_div_y:9;
-        /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
-         *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
-         */
-        uint32_t i2s_tx_clkm_div_x:9;
-        /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_YN1 is 1.
-         */
-        uint32_t i2s_tx_clkm_div_yn1:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_i2s_tx_clkm_div_conf_reg_t;
-
-/** Type of i2s_rx_clkm_conf register
- *  I2S_RX_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
-         *  Integral I2S clock divider value
-         */
-        uint32_t i2s_rx_clkm_div_num:8;
-        /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
-         */
-        uint32_t i2s_rx_clkm_sel:2;
-        /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2s_rx function clock
-         */
-        uint32_t i2s_rx_clkm_en:1;
-        /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0;
-         *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
-         */
-        uint32_t i2s_mclk_sel:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} pcr_i2s_rx_clkm_conf_reg_t;
-
-/** Type of i2s_rx_clkm_div_conf register
- *  I2S_RX_CLKM_DIV configuration register
- */
-typedef union {
-    struct {
-        /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_Z is (a-b).
-         */
-        uint32_t i2s_rx_clkm_div_z:9;
-        /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
-         */
-        uint32_t i2s_rx_clkm_div_y:9;
-        /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
-         *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
-         */
-        uint32_t i2s_rx_clkm_div_x:9;
-        /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_YN1 is 1.
-         */
-        uint32_t i2s_rx_clkm_div_yn1:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_i2s_rx_clkm_div_conf_reg_t;
-
-/** Type of saradc_conf register
- *  SARADC configuration register
- */
-typedef union {
-    struct {
-        /** saradc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  no use
-         */
-        uint32_t saradc_clk_en:1;
-        /** saradc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset function_register of saradc module
-         */
-        uint32_t saradc_rst_en:1;
-        /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable saradc apb clock
-         */
-        uint32_t saradc_reg_clk_en:1;
-        /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0;
-         *  Set 0 to reset apb_register of saradc module
-         */
-        uint32_t saradc_reg_rst_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_saradc_conf_reg_t;
-
-/** Type of saradc_clkm_conf register
- *  SARADC_CLKM configuration register
- */
-typedef union {
-    struct {
-        /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_a:6;
-        /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_b:6;
-        /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4;
-         *  The integral part of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_num:8;
-        /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t saradc_clkm_sel:2;
-        /** saradc_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable saradc function clock
-         */
-        uint32_t saradc_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_saradc_clkm_conf_reg_t;
-
-/** Type of tsens_clk_conf register
- *  TSENS_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tsens_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
-         */
-        uint32_t tsens_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** tsens_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable tsens clock
-         */
-        uint32_t tsens_clk_en:1;
-        /** tsens_rst_en : R/W; bitpos: [23]; default: 0;
-         *  Set 0 to reset tsens module
-         */
-        uint32_t tsens_rst_en:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} pcr_tsens_clk_conf_reg_t;
-
-/** Type of usb_device_conf register
- *  USB_DEVICE configuration register
- */
-typedef union {
-    struct {
-        /** usb_device_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable usb_device clock
-         */
-        uint32_t usb_device_clk_en:1;
-        /** usb_device_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset usb_device module
-         */
-        uint32_t usb_device_rst_en:1;
-        /** usb_device_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset usb_device module
-         */
-        uint32_t usb_device_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_usb_device_conf_reg_t;
-
-/** Type of intmtx_conf register
- *  INTMTX configuration register
- */
-typedef union {
-    struct {
-        /** intmtx_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable intmtx clock
-         */
-        uint32_t intmtx_clk_en:1;
-        /** intmtx_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset intmtx module
-         */
-        uint32_t intmtx_rst_en:1;
-        /** intmtx_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset intmtx module
-         */
-        uint32_t intmtx_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_intmtx_conf_reg_t;
-
-/** Type of pcnt_conf register
- *  PCNT configuration register
- */
-typedef union {
-    struct {
-        /** pcnt_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable pcnt clock
-         */
-        uint32_t pcnt_clk_en:1;
-        /** pcnt_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset pcnt module
-         */
-        uint32_t pcnt_rst_en:1;
-        /** pcnt_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset pcnt module
-         */
-        uint32_t pcnt_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_pcnt_conf_reg_t;
-
-/** Type of etm_conf register
- *  ETM configuration register
- */
-typedef union {
-    struct {
-        /** etm_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable etm clock
-         */
-        uint32_t etm_clk_en:1;
-        /** etm_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset etm module
-         */
-        uint32_t etm_rst_en:1;
-        /** etm_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset etm module
-         */
-        uint32_t etm_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_etm_conf_reg_t;
-
-/** Type of pwm_conf register
- *  PWM configuration register
- */
-typedef union {
-    struct {
-        /** pwm_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable pwm clock
-         */
-        uint32_t pwm_clk_en:1;
-        /** pwm_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset pwm module
-         */
-        uint32_t pwm_rst_en:1;
-        /** pwm_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset pwm module
-         */
-        uint32_t pwm_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_pwm_conf_reg_t;
-
-/** Type of pwm_clk_conf register
- *  PWM_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** pwm_div_num : R/W; bitpos: [19:12]; default: 4;
-         *  The integral part of the frequency divider factor of the pwm function clock.
-         */
-        uint32_t pwm_div_num:8;
-        /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
-         *  160MHz, 2: XTAL, 3: FOSC.
-         */
-        uint32_t pwm_clkm_sel:2;
-        /** pwm_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  set this field as 1 to activate pwm clkm.
-         */
-        uint32_t pwm_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_pwm_clk_conf_reg_t;
-
-/** Type of parl_io_conf register
- *  PARL_IO configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable parl apb clock
-         */
-        uint32_t parl_clk_en:1;
-        /** parl_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset parl apb reg
-         */
-        uint32_t parl_rst_en:1;
-        /** parl_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset parl module
-         */
-        uint32_t parl_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_parl_io_conf_reg_t;
-
-/** Type of parl_clk_rx_conf register
- *  PARL_CLK_RX configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0;
-         *  The integral part of the frequency divider factor of the parl rx clock.
-         */
-        uint32_t parl_clk_rx_div_num:16;
-        /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  user clock from pad.
-         */
-        uint32_t parl_clk_rx_sel:2;
-        /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1;
-         *  Set 1 to enable parl rx clock
-         */
-        uint32_t parl_clk_rx_en:1;
-        /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0;
-         *  Set 0 to reset parl rx module
-         */
-        uint32_t parl_rx_rst_en:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} pcr_parl_clk_rx_conf_reg_t;
-
-/** Type of parl_clk_tx_conf register
- *  PARL_CLK_TX configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0;
-         *  The integral part of the frequency divider factor of the parl tx clock.
-         */
-        uint32_t parl_clk_tx_div_num:16;
-        /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  user clock from pad.
-         */
-        uint32_t parl_clk_tx_sel:2;
-        /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1;
-         *  Set 1 to enable parl tx clock
-         */
-        uint32_t parl_clk_tx_en:1;
-        /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0;
-         *  Set 0 to reset parl tx module
-         */
-        uint32_t parl_tx_rst_en:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} pcr_parl_clk_tx_conf_reg_t;
-
-/** Type of pvt_monitor_conf register
- *  PVT_MONITOR configuration register
- */
-typedef union {
-    struct {
-        /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable apb clock of pvt module
-         */
-        uint32_t pvt_monitor_clk_en:1;
-        /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset all pvt monitor module
-         */
-        uint32_t pvt_monitor_rst_en:1;
-        /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable function clock of modem pvt module
-         */
-        uint32_t pvt_monitor_site1_clk_en:1;
-        /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to enable function clock of cpu pvt module
-         */
-        uint32_t pvt_monitor_site2_clk_en:1;
-        /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1;
-         *  Set 1 to enable function clock of hp_peri pvt module
-         */
-        uint32_t pvt_monitor_site3_clk_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} pcr_pvt_monitor_conf_reg_t;
-
-/** Type of pvt_monitor_func_clk_conf register
- *  PVT_MONITOR function clock configuration register
- */
-typedef union {
-    struct {
-        /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0;
-         *  The integral part of the frequency divider factor of the pvt_monitor function clock.
-         */
-        uint32_t pvt_monitor_func_clk_div_num:4;
-        uint32_t reserved_4:16;
-        /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
-         *  divided by 3.
-         */
-        uint32_t pvt_monitor_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable source clock of pvt sitex
-         */
-        uint32_t pvt_monitor_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_pvt_monitor_func_clk_conf_reg_t;
-
-/** Type of gdma_conf register
- *  GDMA configuration register
- */
-typedef union {
-    struct {
-        /** gdma_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable gdma clock
-         */
-        uint32_t gdma_clk_en:1;
-        /** gdma_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset gdma module
-         */
-        uint32_t gdma_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_gdma_conf_reg_t;
-
-/** Type of spi2_conf register
- *  SPI2 configuration register
- */
-typedef union {
-    struct {
-        /** spi2_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable spi2 apb clock
-         */
-        uint32_t spi2_clk_en:1;
-        /** spi2_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset spi2 module
-         */
-        uint32_t spi2_rst_en:1;
-        /** spi2_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset spi2 module
-         */
-        uint32_t spi2_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_spi2_conf_reg_t;
-
-/** Type of spi2_clkm_conf register
- *  SPI2_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** spi2_clkm_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the spi2_mst clock.
-         */
-        uint32_t spi2_clkm_div_num:8;
-        /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t spi2_clkm_sel:2;
-        /** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable spi2 function clock
-         */
-        uint32_t spi2_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_spi2_clkm_conf_reg_t;
-
-/** Type of aes_conf register
- *  AES configuration register
- */
-typedef union {
-    struct {
-        /** aes_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable aes clock
-         */
-        uint32_t aes_clk_en:1;
-        /** aes_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset aes module
-         */
-        uint32_t aes_rst_en:1;
-        /** aes_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset aes module
-         */
-        uint32_t aes_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_aes_conf_reg_t;
-
-/** Type of sha_conf register
- *  SHA configuration register
- */
-typedef union {
-    struct {
-        /** sha_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable sha clock
-         */
-        uint32_t sha_clk_en:1;
-        /** sha_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset sha module
-         */
-        uint32_t sha_rst_en:1;
-        /** sha_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset sha module
-         */
-        uint32_t sha_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_sha_conf_reg_t;
-
-/** Type of rsa_conf register
- *  RSA configuration register
- */
-typedef union {
-    struct {
-        /** rsa_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable rsa clock
-         */
-        uint32_t rsa_clk_en:1;
-        /** rsa_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset rsa module
-         */
-        uint32_t rsa_rst_en:1;
-        /** rsa_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset rsa module
-         */
-        uint32_t rsa_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_rsa_conf_reg_t;
-
-/** Type of rsa_pd_ctrl register
- *  RSA power control register
- */
-typedef union {
-    struct {
-        /** rsa_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down rsa internal memory.
-         */
-        uint32_t rsa_mem_pd:1;
-        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up rsa internal memory
-         */
-        uint32_t rsa_mem_force_pu:1;
-        /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down rsa internal memory.
-         */
-        uint32_t rsa_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_rsa_pd_ctrl_reg_t;
-
-/** Type of ecc_conf register
- *  ECC configuration register
- */
-typedef union {
-    struct {
-        /** ecc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ecc clock
-         */
-        uint32_t ecc_clk_en:1;
-        /** ecc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ecc module
-         */
-        uint32_t ecc_rst_en:1;
-        /** ecc_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ecc module
-         */
-        uint32_t ecc_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ecc_conf_reg_t;
-
-/** Type of ecc_pd_ctrl register
- *  ECC power control register
- */
-typedef union {
-    struct {
-        /** ecc_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down ecc internal memory.
-         */
-        uint32_t ecc_mem_pd:1;
-        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up ecc internal memory
-         */
-        uint32_t ecc_mem_force_pu:1;
-        /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down ecc internal memory.
-         */
-        uint32_t ecc_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ecc_pd_ctrl_reg_t;
-
-/** Type of ds_conf register
- *  DS configuration register
- */
-typedef union {
-    struct {
-        /** ds_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ds clock
-         */
-        uint32_t ds_clk_en:1;
-        /** ds_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ds module
-         */
-        uint32_t ds_rst_en:1;
-        /** ds_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ds module
-         */
-        uint32_t ds_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ds_conf_reg_t;
-
-/** Type of hmac_conf register
- *  HMAC configuration register
- */
-typedef union {
-    struct {
-        /** hmac_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable hmac clock
-         */
-        uint32_t hmac_clk_en:1;
-        /** hmac_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset hmac module
-         */
-        uint32_t hmac_rst_en:1;
-        /** hmac_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset hmac module
-         */
-        uint32_t hmac_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_hmac_conf_reg_t;
-
-/** Type of ecdsa_conf register
- *  ECDSA configuration register
- */
-typedef union {
-    struct {
-        /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ecdsa clock
-         */
-        uint32_t ecdsa_clk_en:1;
-        /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ecdsa module
-         */
-        uint32_t ecdsa_rst_en:1;
-        /** ecdsa_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ecdsa module
-         */
-        uint32_t ecdsa_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ecdsa_conf_reg_t;
-
-/** Type of iomux_conf register
- *  IOMUX configuration register
- */
-typedef union {
-    struct {
-        /** iomux_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable iomux apb clock
-         */
-        uint32_t iomux_clk_en:1;
-        /** iomux_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset iomux module
-         */
-        uint32_t iomux_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_iomux_conf_reg_t;
-
-/** Type of iomux_clk_conf register
- *  IOMUX_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
-         *  FOSC, 3(default): XTAL.
-         */
-        uint32_t iomux_func_clk_sel:2;
-        /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable iomux function clock
-         */
-        uint32_t iomux_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_iomux_clk_conf_reg_t;
-
-/** Type of mem_monitor_conf register
- *  MEM_MONITOR configuration register
- */
-typedef union {
-    struct {
-        /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable mem_monitor clock
-         */
-        uint32_t mem_monitor_clk_en:1;
-        /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset mem_monitor module
-         */
-        uint32_t mem_monitor_rst_en:1;
-        /** mem_monitor_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset mem_monitor module
-         */
-        uint32_t mem_monitor_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_mem_monitor_conf_reg_t;
-
-/** Type of regdma_conf register
- *  REGDMA configuration register
- */
-typedef union {
-    struct {
-        /** regdma_clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable regdma clock
-         */
-        uint32_t regdma_clk_en:1;
-        /** regdma_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset regdma module
-         */
-        uint32_t regdma_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_regdma_conf_reg_t;
-
-/** Type of trace_conf register
- *  TRACE configuration register
- */
-typedef union {
-    struct {
-        /** trace_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable trace clock
-         */
-        uint32_t trace_clk_en:1;
-        /** trace_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset trace module
-         */
-        uint32_t trace_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_trace_conf_reg_t;
-
-/** Type of assist_conf register
- *  ASSIST configuration register
- */
-typedef union {
-    struct {
-        /** assist_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable assist clock
-         */
-        uint32_t assist_clk_en:1;
-        /** assist_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset assist module
-         */
-        uint32_t assist_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_assist_conf_reg_t;
-
-/** Type of cache_conf register
- *  CACHE configuration register
- */
-typedef union {
-    struct {
-        /** cache_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable cache clock
-         */
-        uint32_t cache_clk_en:1;
-        /** cache_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset cache module
-         */
-        uint32_t cache_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_cache_conf_reg_t;
-
-/** Type of modem_conf register
- *  MODEM_APB configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** modem_rst_en : R/W; bitpos: [2]; default: 0;
-         *  Set this file as 1 to reset modem-subsystem.
-         */
-        uint32_t modem_rst_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_modem_conf_reg_t;
-
-/** Type of timeout_conf register
- *  TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset cpu_peri timeout module
-         */
-        uint32_t cpu_timeout_rst_en:1;
-        /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0;
-         *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
-         */
-        uint32_t hp_timeout_rst_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_timeout_conf_reg_t;
-
-/** Type of sysclk_conf register
- *  SYSCLK configuration register
- */
-typedef union {
-    struct {
-        /** ls_div_num : HRO; bitpos: [7:0]; default: 0;
-         *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
-         *  clock-source such as XTAL/FOSC.
-         */
-        uint32_t ls_div_num:8;
-        /** hs_div_num : HRO; bitpos: [15:8]; default: 2;
-         *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
-         */
-        uint32_t hs_div_num:8;
-        /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
-         *  This field is used to select clock source. 0: XTAL, 1: FOSC, 2: 160M_PLL, 3:
-         *  240M_PLL.
-         */
-        uint32_t soc_clk_sel:2;
-        uint32_t reserved_18:6;
-        /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40;
-         *  This field indicates the frequency(MHz) of XTAL.
-         */
-        uint32_t clk_xtal_freq:7;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} pcr_sysclk_conf_reg_t;
-
-/** Type of cpu_waiti_conf register
- *  CPU_WAITI configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to force cpu_waiti_clk enable.
-         */
-        uint32_t cpu_wait_mode_force_on:1;
-        /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0;
-         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
-         *  will close
-         */
-        uint32_t cpu_waiti_delay_num:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_cpu_waiti_conf_reg_t;
-
-/** Type of cpu_freq_conf register
- *  CPU_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** cpu_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
-         *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
-         */
-        uint32_t cpu_div_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_cpu_freq_conf_reg_t;
-
-/** Type of ahb_freq_conf register
- *  AHB_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** ahb_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
-         *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
-         *  low-speed clock-source such as XTAL/FOSC, and should be used together with
-         *  PCR_CPU_DIV_NUM.
-         */
-        uint32_t ahb_div_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_ahb_freq_conf_reg_t;
-
-/** Type of apb_freq_conf register
- *  APB_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
-         *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
-         *  recover to the previous frequency when a new access appears on apb-bus. Set as one
-         *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
-         *  that enable this function will reduce performance. Users can set this field as zero
-         *  to disable the auto-decrease-apb-freq function. By default, this function is
-         *  disable.
-         */
-        uint32_t apb_decrease_div_num:8;
-        /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
-         *  div1(default)/div2/div4 of clk_ahb.
-         */
-        uint32_t apb_div_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcr_apb_freq_conf_reg_t;
-
-/** Type of pll_div_clk_en register
- *  SPLL DIV clock-gating configuration register
- */
-typedef union {
-    struct {
-        /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_240m_clk_en:1;
-        /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
-         *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_160m_clk_en:1;
-        /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
-         *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_120m_clk_en:1;
-        /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
-         *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_80m_clk_en:1;
-        /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_60m_clk_en:1;
-        /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_48m_clk_en:1;
-        /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1;
-         *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_40m_clk_en:1;
-        /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1;
-         *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_20m_clk_en:1;
-        /** pll_12m_clk_en : R/W; bitpos: [8]; default: 1;
-         *  This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_12m_clk_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} pcr_pll_div_clk_en_reg_t;
-
-/** Type of ctrl_clk_out_en register
- *  CLK_OUT_EN configuration register
- */
-typedef union {
-    struct {
-        /** clk20_oen : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable 20m clock
-         */
-        uint32_t clk20_oen:1;
-        /** clk22_oen : R/W; bitpos: [1]; default: 1;
-         *  Set 1 to enable 22m clock
-         */
-        uint32_t clk22_oen:1;
-        /** clk44_oen : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable 44m clock
-         */
-        uint32_t clk44_oen:1;
-        /** clk_bb_oen : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to enable bb clock
-         */
-        uint32_t clk_bb_oen:1;
-        /** clk80_oen : R/W; bitpos: [4]; default: 1;
-         *  Set 1 to enable 80m clock
-         */
-        uint32_t clk80_oen:1;
-        /** clk160_oen : R/W; bitpos: [5]; default: 1;
-         *  Set 1 to enable 160m clock
-         */
-        uint32_t clk160_oen:1;
-        /** clk_320m_oen : R/W; bitpos: [6]; default: 1;
-         *  Set 1 to enable 320m clock
-         */
-        uint32_t clk_320m_oen:1;
-        /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk_adc_inf_oen:1;
-        /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk_dac_cpu_oen:1;
-        /** clk40x_bb_oen : R/W; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk40x_bb_oen:1;
-        /** clk_xtal_oen : R/W; bitpos: [10]; default: 1;
-         *  Set 1 to enable xtal clock
-         */
-        uint32_t clk_xtal_oen:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} pcr_ctrl_clk_out_en_reg_t;
-
-/** Type of ctrl_tick_conf register
- *  TICK configuration register
- */
-typedef union {
-    struct {
-        /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39;
-         *  ******* Description ***********
-         */
-        uint32_t xtal_tick_num:8;
-        /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7;
-         *  ******* Description ***********
-         */
-        uint32_t fosc_tick_num:8;
-        /** tick_enable : R/W; bitpos: [16]; default: 1;
-         *  ******* Description ***********
-         */
-        uint32_t tick_enable:1;
-        /** rst_tick_cnt : R/W; bitpos: [17]; default: 0;
-         *  ******* Description ***********
-         */
-        uint32_t rst_tick_cnt:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} pcr_ctrl_tick_conf_reg_t;
-
-/** Type of ctrl_32k_conf register
- *  32KHz clock configuration register
- */
-typedef union {
-    struct {
-        /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0;
-         *  This field indicates which one 32KHz clock will be used by timergroup. 0:
-         *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
-         */
-        uint32_t clk_32k_sel:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_ctrl_32k_conf_reg_t;
-
-/** Type of sram_power_conf_0 register
- *  HP SRAM/ROM configuration register
- */
-typedef union {
-    struct {
-        /** rom_force_pu : R/W; bitpos: [2:0]; default: 7;
-         *  Set this bit to force power up ROM
-         */
-        uint32_t rom_force_pu:3;
-        /** rom_force_pd : R/W; bitpos: [5:3]; default: 0;
-         *  Set this bit to force power down ROM.
-         */
-        uint32_t rom_force_pd:3;
-        /** rom_clkgate_force_on : R/W; bitpos: [8:6]; default: 0;
-         *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
-         *  gate-clock will be used when accessing the ROM.
-         */
-        uint32_t rom_clkgate_force_on:3;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} pcr_sram_power_conf_0_reg_t;
-
-/** Type of sram_power_conf_1 register
- *  HP SRAM/ROM configuration register
- */
-typedef union {
-    struct {
-        /** sram_force_pu : R/W; bitpos: [3:0]; default: 15;
-         *  Set this bit to force power up SRAM
-         */
-        uint32_t sram_force_pu:4;
-        uint32_t reserved_4:6;
-        /** sram_force_pd : R/W; bitpos: [13:10]; default: 0;
-         *  Set this bit to force power down SRAM.
-         */
-        uint32_t sram_force_pd:4;
-        uint32_t reserved_14:6;
-        /** sram_clkgate_force_on : R/W; bitpos: [23:20]; default: 0;
-         *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
-         *  gate-clock will be used when accessing the SRAM.
-         */
-        uint32_t sram_clkgate_force_on:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} pcr_sram_power_conf_1_reg_t;
-
-/** Type of sec_conf register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0;
-         *  xxxx
-         */
-        uint32_t sec_clk_sel:2;
-        /** sec_rst_en : R/W; bitpos: [2]; default: 0;
-         *  Set 0 to reset sec module
-         */
-        uint32_t sec_rst_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_sec_conf_reg_t;
-
-/** Type of bus_clk_update register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0;
-         *  xxxx
-         */
-        uint32_t bus_clock_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} pcr_bus_clk_update_reg_t;
-
-/** Type of sar_clk_div register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4;
-         *  xxxx
-         */
-        uint32_t sar2_clk_div_num:8;
-        /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4;
-         *  xxxx
-         */
-        uint32_t sar1_clk_div_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcr_sar_clk_div_reg_t;
-
-/** Type of pwdet_sar_clk_conf register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7;
-         *  xxxx
-         */
-        uint32_t pwdet_sar_clk_div_num:8;
-        /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1;
-         *  xxxx
-         */
-        uint32_t pwdet_sar_clk_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} pcr_pwdet_sar_clk_conf_reg_t;
-
-/** Type of sdio_slave_conf register
- *  SDIO_SLAVE configuration register
- */
-typedef union {
-    struct {
-        /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable sdio_slave clock
-         */
-        uint32_t sdio_slave_clk_en:1;
-        /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset sdio_slave module
-         */
-        uint32_t sdio_slave_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_sdio_slave_conf_reg_t;
-
-/** Type of usb_otg_conf register
- *  USB_OTG configuration register
- */
-typedef union {
-    struct {
-        /** usb_otg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable usb_otg bus clock
-         */
-        uint32_t usb_otg_clk_en:1;
-        /** usb_otg_adp_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset usb_otg core adp
-         */
-        uint32_t usb_otg_adp_rst_en:1;
-        /** usb_otg_misc_rst_en : R/W; bitpos: [2]; default: 0;
-         *  Set 0 to reset usb_otg misc
-         */
-        uint32_t usb_otg_misc_rst_en:1;
-        /** usb_otg_global_rst_en : R/W; bitpos: [3]; default: 0;
-         *  Set 0 to reset usb_otg module
-         */
-        uint32_t usb_otg_global_rst_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_usb_otg_conf_reg_t;
-
-/** Type of usb_otg_clk_conf register
- *  USB_OTG func clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** usb_otg_phy_refclk_sel : R/W; bitpos: [20]; default: 1;
-         *  Set 1 to sel 12m pll clock, set 0 to sel pad clock
-         */
-        uint32_t usb_otg_phy_refclk_sel:1;
-        /** usb_otg_phy_refclk_en : R/W; bitpos: [21]; default: 1;
-         *  Set 1 to enable usb_otg_phy_refclk clock
-         */
-        uint32_t usb_otg_phy_refclk_en:1;
-        /** usb_otg_adp_clk_sel : R/W; bitpos: [23:22]; default: 0;
-         *  Set 0 to sel clock from gpio_matrix, set 1 to sel osc32k, set 2 to sel xtal32k, set
-         *  3 to sel ext32k
-         */
-        uint32_t usb_otg_adp_clk_sel:2;
-        /** usb_otg_adp_clk_en : R/W; bitpos: [24]; default: 1;
-         *  Set 1 to enable usb_otg_adp_clk clock
-         */
-        uint32_t usb_otg_adp_clk_en:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} pcr_usb_otg_clk_conf_reg_t;
-
-/** Type of bs_conf register
- *  BS configuration register
- */
-typedef union {
-    struct {
-        /** bs_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable bs clock
-         */
-        uint32_t bs_clk_en:1;
-        /** bs_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset bs module
-         */
-        uint32_t bs_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_bs_conf_reg_t;
-
-/** Type of bs_func_conf register
- *  BS_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:23;
-        /** bs_tx_rst_en : R/W; bitpos: [23]; default: 0;
-         *  Set 0 to reset bs tx module
-         */
-        uint32_t bs_tx_rst_en:1;
-        /** bs_rx_rst_en : R/W; bitpos: [24]; default: 0;
-         *  Set 0 to reset bs rx module
-         */
-        uint32_t bs_rx_rst_en:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} pcr_bs_func_conf_reg_t;
-
-/** Type of timergroup_wdt_conf register
- *  TIMERGROUP_WDT configuration register
- */
-typedef union {
-    struct {
-        /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0;
-         *  Set 0 to reset timer_group0 wdt module
-         */
-        uint32_t tg0_wdt_rst_en:1;
-        /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group1 wdt module
-         */
-        uint32_t tg1_wdt_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_timergroup_wdt_conf_reg_t;
-
-/** Type of timergroup_xtal_conf register
- *  TIMERGROUP1 configuration register
- */
-typedef union {
-    struct {
-        /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0;
-         *  Set 0 to reset timer_group0 xtal clock domain
-         */
-        uint32_t tg0_xtal_rst_en:1;
-        /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group1 xtal clock domain
-         */
-        uint32_t tg1_xtal_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_timergroup_xtal_conf_reg_t;
-
-/** Type of km_conf register
- *  Key Manager configuration register
- */
-typedef union {
-    struct {
-        /** km_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable km clock
-         */
-        uint32_t km_clk_en:1;
-        /** km_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset km module
-         */
-        uint32_t km_rst_en:1;
-        /** km_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset km module
-         */
-        uint32_t km_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_km_conf_reg_t;
-
-
-/** Group: Frequency Statistics Register */
-/** Type of sysclk_freq_query_0 register
- *  SYSCLK frequency query 0 register
- */
-typedef union {
-    struct {
-        /** fosc_freq : HRO; bitpos: [7:0]; default: 8;
-         *  This field indicates the frequency(MHz) of FOSC.
-         */
-        uint32_t fosc_freq:8;
-        /** pll_freq : HRO; bitpos: [17:8]; default: 96;
-         *  This field indicates the frequency(MHz) of SPLL.
-         */
-        uint32_t pll_freq:10;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} pcr_sysclk_freq_query_0_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720976;
-         *  PCR version information.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_date_reg_t;
-
-/**
- * @brief The struct of I2C configuration registers
- */
-typedef struct {
-    pcr_i2c_conf_reg_t i2c_conf;
-    pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
-} pcr_i2c_reg_t;
-
-typedef struct pcr_dev_t {
-    volatile pcr_uart0_conf_reg_t uart0_conf;
-    volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
-    volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl;
-    volatile pcr_uart1_conf_reg_t uart1_conf;
-    volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf;
-    volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
-    volatile pcr_mspi_conf_reg_t mspi_conf;
-    volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
-    volatile pcr_i2c_reg_t i2c[1];
-    volatile pcr_twai0_conf_reg_t twai0_conf;
-    volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf;
-    volatile pcr_twai1_conf_reg_t twai1_conf;
-    volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf;
-    volatile pcr_uhci_conf_reg_t uhci_conf;
-    volatile pcr_rmt_conf_reg_t rmt_conf;
-    volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf;
-    volatile pcr_ledc_conf_reg_t ledc_conf;
-    volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf;
-    volatile pcr_timergroup0_conf_reg_t timergroup0_conf;
-    volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf;
-    volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf;
-    volatile pcr_timergroup1_conf_reg_t timergroup1_conf;
-    volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf;
-    volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf;
-    volatile pcr_systimer_conf_reg_t systimer_conf;
-    volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf;
-    volatile pcr_i2s_conf_reg_t i2s_conf;
-    volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf;
-    volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf;
-    volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf;
-    volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf;
-    volatile pcr_saradc_conf_reg_t saradc_conf;
-    volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf;
-    volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf;
-    volatile pcr_usb_device_conf_reg_t usb_device_conf;
-    volatile pcr_intmtx_conf_reg_t intmtx_conf;
-    volatile pcr_pcnt_conf_reg_t pcnt_conf;
-    volatile pcr_etm_conf_reg_t etm_conf;
-    volatile pcr_pwm_conf_reg_t pwm_conf;
-    volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf;
-    volatile pcr_parl_io_conf_reg_t parl_io_conf;
-    volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf;
-    volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf;
-    volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf;
-    volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf;
-    volatile pcr_gdma_conf_reg_t gdma_conf;
-    volatile pcr_spi2_conf_reg_t spi2_conf;
-    volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf;
-    volatile pcr_aes_conf_reg_t aes_conf;
-    volatile pcr_sha_conf_reg_t sha_conf;
-    volatile pcr_rsa_conf_reg_t rsa_conf;
-    volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
-    volatile pcr_ecc_conf_reg_t ecc_conf;
-    volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
-    volatile pcr_ds_conf_reg_t ds_conf;
-    volatile pcr_hmac_conf_reg_t hmac_conf;
-    volatile pcr_ecdsa_conf_reg_t ecdsa_conf;
-    volatile pcr_iomux_conf_reg_t iomux_conf;
-    volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf;
-    volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf;
-    volatile pcr_regdma_conf_reg_t regdma_conf;
-    volatile pcr_trace_conf_reg_t trace_conf;
-    volatile pcr_assist_conf_reg_t assist_conf;
-    volatile pcr_cache_conf_reg_t cache_conf;
-    volatile pcr_modem_conf_reg_t modem_conf;
-    volatile pcr_timeout_conf_reg_t timeout_conf;
-    volatile pcr_sysclk_conf_reg_t sysclk_conf;
-    volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf;
-    volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf;
-    volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf;
-    volatile pcr_apb_freq_conf_reg_t apb_freq_conf;
-    volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0;
-    volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en;
-    volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en;
-    volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf;
-    volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf;
-    volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0;
-    volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1;
-    volatile pcr_sec_conf_reg_t sec_conf;
-    uint32_t reserved_140[2];
-    volatile pcr_bus_clk_update_reg_t bus_clk_update;
-    volatile pcr_sar_clk_div_reg_t sar_clk_div;
-    volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf;
-    volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf;
-    volatile pcr_usb_otg_conf_reg_t usb_otg_conf;
-    volatile pcr_usb_otg_clk_conf_reg_t usb_otg_clk_conf;
-    volatile pcr_bs_conf_reg_t bs_conf;
-    volatile pcr_bs_func_conf_reg_t bs_func_conf;
-    volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf;
-    volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf;
-    volatile pcr_km_conf_reg_t km_conf;
-    uint32_t reserved_174[930];
-    volatile pcr_date_reg_t date;
-} pcr_dev_t;
-
-extern pcr_dev_t PCR;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/periph_defs.h b/components/soc/esp32c5/beta3/include/soc/periph_defs.h
deleted file mode 100644
index 99aca9c24b..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/periph_defs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/interrupts.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// TODO: [ESP32C5-PERIPH] (inherit from C6)
-
-typedef enum {
-    /* HP peripherals */
-    PERIPH_LEDC_MODULE = 0,
-    PERIPH_UART0_MODULE,
-    PERIPH_UART1_MODULE,
-    PERIPH_USB_DEVICE_MODULE,  // USB Serial Jtag
-    PERIPH_I2C0_MODULE,
-    PERIPH_I2C1_MODULE,
-    PERIPH_I2S1_MODULE,
-    PERIPH_TIMG0_MODULE,
-    PERIPH_TIMG1_MODULE,
-    PERIPH_UHCI0_MODULE,
-    PERIPH_RMT_MODULE,
-    PERIPH_PCNT_MODULE,
-    PERIPH_MSPI0_MODULE,  //SPI0
-    PERIPH_MSPI1_MODULE,  //SPI1
-    PERIPH_GPSPI2_MODULE, //SPI2
-    PERIPH_TWAI0_MODULE,
-    PERIPH_TWAI1_MODULE,
-    PERIPH_RNG_MODULE,
-    PERIPH_RSA_MODULE,
-    PERIPH_AES_MODULE,
-    PERIPH_SHA_MODULE,
-    PERIPH_ECC_MODULE,
-    PERIPH_HMAC_MODULE,
-    PERIPH_DS_MODULE,
-    PERIPH_GDMA_MODULE,
-    PERIPH_MCPWM0_MODULE,
-    PERIPH_ETM_MODULE,
-    PERIPH_PARLIO_MODULE,
-    PERIPH_SYSTIMER_MODULE,
-    PERIPH_SARADC_MODULE,
-    PERIPH_TEMPSENSOR_MODULE,
-    PERIPH_ASSIST_DEBUG_MODULE,
-    PERIPH_INT_MATRIX_MODULE,
-    PERIPH_PVT_MONITOR_MODULE,
-    PERIPH_BITSCRAMBLER_MODULE,
-    PERIPH_KEY_MANAGE_MODULE,
-    PERIPH_ECDSA_MODULE,
-    PERIPH_MEM_MONITOR_MODULE,
-    PERIPH_TEE_MODULE,
-    PERIPH_HP_APM_MODULE,
-    /* LP peripherals */
-    PERIPH_LP_I2C0_MODULE,
-    PERIPH_LP_UART0_MODULE,
-    PERIPH_LP_TEE_MODULE,
-    PERIPH_LP_APM_MODULE,
-    PERIPH_LP_ANA_PERI_MODULE,
-    PERIPH_LP_PERI_MODULE,
-    PERIPH_HUK_MODULE,
-    PERIPH_OTP_DEBUG_MODULE,
-    /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
-    PERIPH_WIFI_MODULE,
-    PERIPH_BT_MODULE,
-    PERIPH_IEEE802154_MODULE,
-    PERIPH_COEX_MODULE,
-    PERIPH_PHY_MODULE,
-    PERIPH_ANA_I2C_MASTER_MODULE,
-    PERIPH_MODEM_ETM_MODULE,
-    PERIPH_MODEM_ADC_COMMON_FE_MODULE,
-    PERIPH_MODULE_MAX
-    /*  !!! Don't append soc modules here !!! */
-} periph_module_t;
-
-#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
-#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
-#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
-#define IS_MODEM_MODULE(periph)  ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pmu_icg_mapping.h b/components/soc/esp32c5/beta3/include/soc/pmu_icg_mapping.h
deleted file mode 100644
index c4b995c52a..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pmu_icg_mapping.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_ICG_MAP_H_
-#define _SOC_ICG_MAP_H_
-
-#define PMU_ICG_APB_ENA_CAN0                               18
-#define PMU_ICG_APB_ENA_CAN1                               19
-#define PMU_ICG_APB_ENA_GDMA                               1
-#define PMU_ICG_APB_ENA_I2C                                13
-#define PMU_ICG_APB_ENA_I2S                                4
-#define PMU_ICG_APB_ENA_INTMTX                             3
-#define PMU_ICG_APB_ENA_IOMUX                              26
-#define PMU_ICG_APB_ENA_LEDC                               14
-#define PMU_ICG_APB_ENA_MEM_MONITOR                        25
-#define PMU_ICG_APB_ENA_MSPI                               5
-#define PMU_ICG_APB_ENA_PARL                               23
-#define PMU_ICG_APB_ENA_PCNT                               20
-#define PMU_ICG_APB_ENA_PVT_MONITOR                        27
-#define PMU_ICG_APB_ENA_PWM                                21
-#define PMU_ICG_APB_ENA_REGDMA                             24
-#define PMU_ICG_APB_ENA_RMT                                15
-#define PMU_ICG_APB_ENA_SARADC                             9
-#define PMU_ICG_APB_ENA_SEC                                0
-#define PMU_ICG_APB_ENA_SOC_ETM                            22
-#define PMU_ICG_APB_ENA_SPI2                               2
-#define PMU_ICG_APB_ENA_SYSTIMER                           16
-#define PMU_ICG_APB_ENA_TG0                                11
-#define PMU_ICG_APB_ENA_TG1                                12
-#define PMU_ICG_APB_ENA_UART0                              6
-#define PMU_ICG_APB_ENA_UART1                              7
-#define PMU_ICG_APB_ENA_UHCI                               8
-#define PMU_ICG_APB_ENA_USB_DEVICE                         17
-#define PMU_ICG_FUNC_ENA_CAN0                              31
-#define PMU_ICG_FUNC_ENA_CAN1                              30
-#define PMU_ICG_FUNC_ENA_I2C                               29
-#define PMU_ICG_FUNC_ENA_I2S_RX                            2
-#define PMU_ICG_FUNC_ENA_I2S_TX                            7
-#define PMU_ICG_FUNC_ENA_IOMUX                             28
-#define PMU_ICG_FUNC_ENA_LEDC                              27
-#define PMU_ICG_FUNC_ENA_MEM_MONITOR                       10
-#define PMU_ICG_FUNC_ENA_MSPI                              26
-#define PMU_ICG_FUNC_ENA_PARL_RX                           25
-#define PMU_ICG_FUNC_ENA_PARL_TX                           24
-#define PMU_ICG_FUNC_ENA_PVT_MONITOR                       23
-#define PMU_ICG_FUNC_ENA_PWM                               22
-#define PMU_ICG_FUNC_ENA_RMT                               21
-#define PMU_ICG_FUNC_ENA_SARADC                            20
-#define PMU_ICG_FUNC_ENA_SEC                               19
-#define PMU_ICG_FUNC_ENA_SPI2                              1
-#define PMU_ICG_FUNC_ENA_SYSTIMER                          18
-#define PMU_ICG_FUNC_ENA_TG0                               14
-#define PMU_ICG_FUNC_ENA_TG1                               13
-#define PMU_ICG_FUNC_ENA_TSENS                             12
-#define PMU_ICG_FUNC_ENA_UART0                             3
-#define PMU_ICG_FUNC_ENA_UART1                             4
-#define PMU_ICG_FUNC_ENA_USB_DEVICE                        6
-#define PMU_ICG_FUNC_ENA_GDMA                              0
-#define PMU_ICG_FUNC_ENA_SOC_ETM                           16
-#define PMU_ICG_FUNC_ENA_REGDMA                            8
-#define PMU_ICG_FUNC_ENA_RETENTION                         9
-#define PMU_ICG_FUNC_ENA_SDIO_SLAVE                        11
-#define PMU_ICG_FUNC_ENA_UHCI                              5
-#define PMU_ICG_FUNC_ENA_HPCORE                            17
-#define PMU_ICG_FUNC_ENA_HPBUS                             15
-#endif  /* _SOC_ICG_MAP_H_ */
diff --git a/components/soc/esp32c5/beta3/include/soc/pmu_reg.h b/components/soc/esp32c5/beta3/include/soc/pmu_reg.h
deleted file mode 100644
index 0713f07ed4..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pmu_reg.h
+++ /dev/null
@@ -1,3359 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PMU_HP_ACTIVE_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0)
-/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_VDD_SPI_PD_EN    (BIT(21))
-#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M  (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S)
-#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S  21
-/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_MEM_DSLP    (BIT(22))
-#define PMU_HP_ACTIVE_HP_MEM_DSLP_M  (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S)
-#define PMU_HP_ACTIVE_HP_MEM_DSLP_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_MEM_DSLP_S  22
-/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN    0x0000000FU
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V  0x0000000FU
-#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S  23
-/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN    (BIT(27))
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S  27
-/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN    (BIT(29))
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S  29
-/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN    (BIT(30))
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M  (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S  30
-/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN    (BIT(31))
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M  (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S)
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S  31
-
-/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4)
-/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S)
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S  0
-
-/** PMU_HP_ACTIVE_ICG_HP_APB_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8)
-/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN    0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M  (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S)
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V  0xFFFFFFFFU
-#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S  0
-
-/** PMU_HP_ACTIVE_ICG_MODEM_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc)
-/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE    0x00000003U
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M  (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S)
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V  0x00000003U
-#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S  30
-
-/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10)
-/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN    (BIT(24))
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M  (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S)
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S  24
-/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL    (BIT(25))
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S)
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S  25
-/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL    (BIT(26))
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M  (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S)
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S  26
-/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL    (BIT(27))
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M  (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S)
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S  27
-/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT    (BIT(28))
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M  (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S)
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S  28
-/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_CPU_STALL    (BIT(29))
-#define PMU_HP_ACTIVE_DIG_CPU_STALL_M  (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S)
-#define PMU_HP_ACTIVE_DIG_CPU_STALL_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_CPU_STALL_S  29
-
-/** PMU_HP_ACTIVE_HP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14)
-/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_I2C_ISO_EN    (BIT(26))
-#define PMU_HP_ACTIVE_I2C_ISO_EN_M  (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S)
-#define PMU_HP_ACTIVE_I2C_ISO_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_I2C_ISO_EN_S  26
-/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_I2C_RETENTION    (BIT(27))
-#define PMU_HP_ACTIVE_I2C_RETENTION_M  (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S)
-#define PMU_HP_ACTIVE_I2C_RETENTION_V  0x00000001U
-#define PMU_HP_ACTIVE_I2C_RETENTION_S  27
-/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BB_I2C    (BIT(28))
-#define PMU_HP_ACTIVE_XPD_BB_I2C_M  (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S)
-#define PMU_HP_ACTIVE_XPD_BB_I2C_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BB_I2C_S  28
-/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C    (BIT(29))
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M  (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S)
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S  29
-/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BBPLL    (BIT(30))
-#define PMU_HP_ACTIVE_XPD_BBPLL_M  (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S)
-#define PMU_HP_ACTIVE_XPD_BBPLL_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BBPLL_S  30
-
-/** PMU_HP_ACTIVE_BIAS_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18)
-/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_BIAS    (BIT(25))
-#define PMU_HP_ACTIVE_XPD_BIAS_M  (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S)
-#define PMU_HP_ACTIVE_XPD_BIAS_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_BIAS_S  25
-/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DBG_ATTEN    0x0000000FU
-#define PMU_HP_ACTIVE_DBG_ATTEN_M  (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S)
-#define PMU_HP_ACTIVE_DBG_ATTEN_V  0x0000000FU
-#define PMU_HP_ACTIVE_DBG_ATTEN_S  26
-/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_PD_CUR    (BIT(30))
-#define PMU_HP_ACTIVE_PD_CUR_M  (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S)
-#define PMU_HP_ACTIVE_PD_CUR_V  0x00000001U
-#define PMU_HP_ACTIVE_PD_CUR_S  30
-/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_BIAS_SLEEP    (BIT(31))
-#define PMU_HP_ACTIVE_BIAS_SLEEP_M  (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S)
-#define PMU_HP_ACTIVE_BIAS_SLEEP_V  0x00000001U
-#define PMU_HP_ACTIVE_BIAS_SLEEP_S  31
-
-/** PMU_HP_ACTIVE_BACKUP_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c)
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S  4
-/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S  6
-/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_RETENTION_MODE    (BIT(10))
-#define PMU_HP_ACTIVE_RETENTION_MODE_M  (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S)
-#define PMU_HP_ACTIVE_RETENTION_MODE_V  0x00000001U
-#define PMU_HP_ACTIVE_RETENTION_MODE_S  10
-/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN    (BIT(11))
-#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M  (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S)
-#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V  0x00000001U
-#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S  11
-/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_RETENTION_EN    (BIT(12))
-#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M  (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S)
-#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V  0x00000001U
-#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S  12
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S  14
-/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S  16
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE    0x00000007U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V  0x00000007U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S  20
-/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE    0x00000007U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M  (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V  0x00000007U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S  23
-/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN    (BIT(29))
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M  (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S)
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V  0x00000001U
-#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S  29
-/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN    (BIT(30))
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M  (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S)
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V  0x00000001U
-#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S  30
-
-/** PMU_HP_ACTIVE_BACKUP_CLK_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20)
-/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M  (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S)
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S  0
-
-/** PMU_HP_ACTIVE_SYSCLK_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24)
-/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV    (BIT(26))
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S)
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V  0x00000001U
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S  26
-/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN    (BIT(27))
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M  (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S)
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V  0x00000001U
-#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S  27
-/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL    (BIT(28))
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M  (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S)
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V  0x00000001U
-#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S  28
-/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_ICG_SLP_SEL    (BIT(29))
-#define PMU_HP_ACTIVE_ICG_SLP_SEL_M  (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S)
-#define PMU_HP_ACTIVE_ICG_SLP_SEL_V  0x00000001U
-#define PMU_HP_ACTIVE_ICG_SLP_SEL_S  29
-/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL    0x00000003U
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M  (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S)
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V  0x00000003U
-#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S  30
-
-/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28)
-/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24;
- *  need_des
- */
-#define PMU_LP_DBIAS_VOL    0x0000001FU
-#define PMU_LP_DBIAS_VOL_M  (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S)
-#define PMU_LP_DBIAS_VOL_V  0x0000001FU
-#define PMU_LP_DBIAS_VOL_S  4
-/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24;
- *  need_des
- */
-#define PMU_HP_DBIAS_VOL    0x0000001FU
-#define PMU_HP_DBIAS_VOL_M  (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S)
-#define PMU_HP_DBIAS_VOL_V  0x0000001FU
-#define PMU_HP_DBIAS_VOL_S  9
-/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1;
- *  need_des
- */
-#define PMU_DIG_REGULATOR0_DBIAS_SEL    (BIT(14))
-#define PMU_DIG_REGULATOR0_DBIAS_SEL_M  (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S)
-#define PMU_DIG_REGULATOR0_DBIAS_SEL_V  0x00000001U
-#define PMU_DIG_REGULATOR0_DBIAS_SEL_S  14
-/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0;
- *  need_des
- */
-#define PMU_DIG_DBIAS_INIT    (BIT(15))
-#define PMU_DIG_DBIAS_INIT_M  (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S)
-#define PMU_DIG_DBIAS_INIT_V  0x00000001U
-#define PMU_DIG_DBIAS_INIT_S  15
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S  16
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S  17
-/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD    (BIT(18))
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M  (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V  0x00000001U
-#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S  18
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S  19
-/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
-/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M  (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S  27
-
-/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c)
-/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B    0x00FFFFFFU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M  (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S)
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V  0x00FFFFFFU
-#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S  8
-
-/** PMU_HP_ACTIVE_XTAL_REG register
- *  need_des
- */
-#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30)
-/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_HP_ACTIVE_XPD_XTAL    (BIT(31))
-#define PMU_HP_ACTIVE_XPD_XTAL_M  (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S)
-#define PMU_HP_ACTIVE_XPD_XTAL_V  0x00000001U
-#define PMU_HP_ACTIVE_XPD_XTAL_S  31
-
-/** PMU_HP_MODEM_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34)
-/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_VDD_SPI_PD_EN    (BIT(21))
-#define PMU_HP_MODEM_VDD_SPI_PD_EN_M  (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S)
-#define PMU_HP_MODEM_VDD_SPI_PD_EN_V  0x00000001U
-#define PMU_HP_MODEM_VDD_SPI_PD_EN_S  21
-/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_MEM_DSLP    (BIT(22))
-#define PMU_HP_MODEM_HP_MEM_DSLP_M  (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S)
-#define PMU_HP_MODEM_HP_MEM_DSLP_V  0x00000001U
-#define PMU_HP_MODEM_HP_MEM_DSLP_S  22
-/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_PD_HP_MEM_PD_EN    0x0000000FU
-#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M  (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S)
-#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V  0x0000000FU
-#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S  23
-/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN    (BIT(27))
-#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M  (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S)
-#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V  0x00000001U
-#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S  27
-/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_PD_HP_CPU_PD_EN    (BIT(29))
-#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M  (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S)
-#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V  0x00000001U
-#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S  29
-/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_PD_HP_AON_PD_EN    (BIT(30))
-#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M  (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S)
-#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V  0x00000001U
-#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S  30
-/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_PD_TOP_PD_EN    (BIT(31))
-#define PMU_HP_MODEM_PD_TOP_PD_EN_M  (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S)
-#define PMU_HP_MODEM_PD_TOP_PD_EN_V  0x00000001U
-#define PMU_HP_MODEM_PD_TOP_PD_EN_S  31
-
-/** PMU_HP_MODEM_ICG_HP_FUNC_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38)
-/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M  (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S)
-#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S  0
-
-/** PMU_HP_MODEM_ICG_HP_APB_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c)
-/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_ICG_APB_EN    0xFFFFFFFFU
-#define PMU_HP_MODEM_DIG_ICG_APB_EN_M  (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S)
-#define PMU_HP_MODEM_DIG_ICG_APB_EN_V  0xFFFFFFFFU
-#define PMU_HP_MODEM_DIG_ICG_APB_EN_S  0
-
-/** PMU_HP_MODEM_ICG_MODEM_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40)
-/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE    0x00000003U
-#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M  (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S)
-#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V  0x00000003U
-#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S  30
-
-/** PMU_HP_MODEM_HP_SYS_CNTL_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44)
-/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_UART_WAKEUP_EN    (BIT(24))
-#define PMU_HP_MODEM_UART_WAKEUP_EN_M  (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S)
-#define PMU_HP_MODEM_UART_WAKEUP_EN_V  0x00000001U
-#define PMU_HP_MODEM_UART_WAKEUP_EN_S  24
-/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_LP_PAD_HOLD_ALL    (BIT(25))
-#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M  (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S)
-#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S  25
-/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_PAD_HOLD_ALL    (BIT(26))
-#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M  (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S)
-#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S  26
-/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_PAD_SLP_SEL    (BIT(27))
-#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M  (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S)
-#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V  0x00000001U
-#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S  27
-/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_PAUSE_WDT    (BIT(28))
-#define PMU_HP_MODEM_DIG_PAUSE_WDT_M  (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S)
-#define PMU_HP_MODEM_DIG_PAUSE_WDT_V  0x00000001U
-#define PMU_HP_MODEM_DIG_PAUSE_WDT_S  28
-/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_CPU_STALL    (BIT(29))
-#define PMU_HP_MODEM_DIG_CPU_STALL_M  (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S)
-#define PMU_HP_MODEM_DIG_CPU_STALL_V  0x00000001U
-#define PMU_HP_MODEM_DIG_CPU_STALL_S  29
-
-/** PMU_HP_MODEM_HP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48)
-/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_I2C_ISO_EN    (BIT(26))
-#define PMU_HP_MODEM_I2C_ISO_EN_M  (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S)
-#define PMU_HP_MODEM_I2C_ISO_EN_V  0x00000001U
-#define PMU_HP_MODEM_I2C_ISO_EN_S  26
-/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_I2C_RETENTION    (BIT(27))
-#define PMU_HP_MODEM_I2C_RETENTION_M  (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S)
-#define PMU_HP_MODEM_I2C_RETENTION_V  0x00000001U
-#define PMU_HP_MODEM_I2C_RETENTION_S  27
-/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_XPD_BB_I2C    (BIT(28))
-#define PMU_HP_MODEM_XPD_BB_I2C_M  (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S)
-#define PMU_HP_MODEM_XPD_BB_I2C_V  0x00000001U
-#define PMU_HP_MODEM_XPD_BB_I2C_S  28
-/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_XPD_BBPLL_I2C    (BIT(29))
-#define PMU_HP_MODEM_XPD_BBPLL_I2C_M  (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S)
-#define PMU_HP_MODEM_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_HP_MODEM_XPD_BBPLL_I2C_S  29
-/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_XPD_BBPLL    (BIT(30))
-#define PMU_HP_MODEM_XPD_BBPLL_M  (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S)
-#define PMU_HP_MODEM_XPD_BBPLL_V  0x00000001U
-#define PMU_HP_MODEM_XPD_BBPLL_S  30
-
-/** PMU_HP_MODEM_BIAS_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c)
-/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_XPD_BIAS    (BIT(25))
-#define PMU_HP_MODEM_XPD_BIAS_M  (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S)
-#define PMU_HP_MODEM_XPD_BIAS_V  0x00000001U
-#define PMU_HP_MODEM_XPD_BIAS_S  25
-/** PMU_HP_MODEM_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_DBG_ATTEN    0x0000000FU
-#define PMU_HP_MODEM_DBG_ATTEN_M  (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S)
-#define PMU_HP_MODEM_DBG_ATTEN_V  0x0000000FU
-#define PMU_HP_MODEM_DBG_ATTEN_S  26
-/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_PD_CUR    (BIT(30))
-#define PMU_HP_MODEM_PD_CUR_M  (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S)
-#define PMU_HP_MODEM_PD_CUR_V  0x00000001U
-#define PMU_HP_MODEM_PD_CUR_S  30
-/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_BIAS_SLEEP    (BIT(31))
-#define PMU_HP_MODEM_BIAS_SLEEP_M  (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S)
-#define PMU_HP_MODEM_BIAS_SLEEP_V  0x00000001U
-#define PMU_HP_MODEM_BIAS_SLEEP_S  31
-
-/** PMU_HP_MODEM_BACKUP_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50)
-/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S  4
-/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_RETENTION_MODE    (BIT(10))
-#define PMU_HP_MODEM_RETENTION_MODE_M  (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S)
-#define PMU_HP_MODEM_RETENTION_MODE_V  0x00000001U
-#define PMU_HP_MODEM_RETENTION_MODE_S  10
-/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2MODEM_RETENTION_EN    (BIT(11))
-#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M  (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S)
-#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V  0x00000001U
-#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S  11
-/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M  (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S)
-#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S  14
-/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODE    0x00000007U
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M  (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S)
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V  0x00000007U
-#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S  20
-/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP2MODEM_BACKUP_EN    (BIT(29))
-#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M  (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S)
-#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V  0x00000001U
-#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S  29
-
-/** PMU_HP_MODEM_BACKUP_CLK_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54)
-/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M  (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S)
-#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S  0
-
-/** PMU_HP_MODEM_SYSCLK_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58)
-/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV    (BIT(26))
-#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S)
-#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V  0x00000001U
-#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S  26
-/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN    (BIT(27))
-#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M  (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S)
-#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V  0x00000001U
-#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S  27
-/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_SYS_CLK_SLP_SEL    (BIT(28))
-#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M  (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S)
-#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V  0x00000001U
-#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S  28
-/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_ICG_SLP_SEL    (BIT(29))
-#define PMU_HP_MODEM_ICG_SLP_SEL_M  (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S)
-#define PMU_HP_MODEM_ICG_SLP_SEL_V  0x00000001U
-#define PMU_HP_MODEM_ICG_SLP_SEL_S  29
-/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_DIG_SYS_CLK_SEL    0x00000003U
-#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M  (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S)
-#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V  0x00000003U
-#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S  30
-
-/** PMU_HP_MODEM_HP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c)
-/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S)
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S  16
-/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S)
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S  17
-/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR_XPD    (BIT(18))
-#define PMU_HP_MODEM_HP_REGULATOR_XPD_M  (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S)
-#define PMU_HP_MODEM_HP_REGULATOR_XPD_V  0x00000001U
-#define PMU_HP_MODEM_HP_REGULATOR_XPD_S  18
-/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S)
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S  19
-/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
-#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
-/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M  (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S)
-#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S  27
-
-/** PMU_HP_MODEM_HP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60)
-/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM_HP_REGULATOR_DRV_B    0x00FFFFFFU
-#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M  (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S)
-#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V  0x00FFFFFFU
-#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S  8
-
-/** PMU_HP_MODEM_XTAL_REG register
- *  need_des
- */
-#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64)
-/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_HP_MODEM_XPD_XTAL    (BIT(31))
-#define PMU_HP_MODEM_XPD_XTAL_M  (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S)
-#define PMU_HP_MODEM_XPD_XTAL_V  0x00000001U
-#define PMU_HP_MODEM_XPD_XTAL_S  31
-
-/** PMU_HP_SLEEP_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68)
-/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_VDD_SPI_PD_EN    (BIT(21))
-#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M  (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S)
-#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S  21
-/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_MEM_DSLP    (BIT(22))
-#define PMU_HP_SLEEP_HP_MEM_DSLP_M  (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S)
-#define PMU_HP_SLEEP_HP_MEM_DSLP_V  0x00000001U
-#define PMU_HP_SLEEP_HP_MEM_DSLP_S  22
-/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN    0x0000000FU
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M  (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V  0x0000000FU
-#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S  23
-/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN    (BIT(27))
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M  (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S  27
-/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN    (BIT(29))
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M  (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S  29
-/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN    (BIT(30))
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M  (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S)
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S  30
-/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_TOP_PD_EN    (BIT(31))
-#define PMU_HP_SLEEP_PD_TOP_PD_EN_M  (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S)
-#define PMU_HP_SLEEP_PD_TOP_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_TOP_PD_EN_S  31
-
-/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c)
-/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M  (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S)
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S  0
-
-/** PMU_HP_SLEEP_ICG_HP_APB_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70)
-/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN    0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M  (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S)
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V  0xFFFFFFFFU
-#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S  0
-
-/** PMU_HP_SLEEP_ICG_MODEM_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74)
-/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE    0x00000003U
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M  (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S)
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V  0x00000003U
-#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S  30
-
-/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78)
-/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_UART_WAKEUP_EN    (BIT(24))
-#define PMU_HP_SLEEP_UART_WAKEUP_EN_M  (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S)
-#define PMU_HP_SLEEP_UART_WAKEUP_EN_V  0x00000001U
-#define PMU_HP_SLEEP_UART_WAKEUP_EN_S  24
-/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL    (BIT(25))
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S)
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S  25
-/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL    (BIT(26))
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M  (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S)
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S  26
-/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL    (BIT(27))
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M  (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S)
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S  27
-/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT    (BIT(28))
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M  (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S)
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S  28
-/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_CPU_STALL    (BIT(29))
-#define PMU_HP_SLEEP_DIG_CPU_STALL_M  (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S)
-#define PMU_HP_SLEEP_DIG_CPU_STALL_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_CPU_STALL_S  29
-
-/** PMU_HP_SLEEP_HP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c)
-/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_I2C_ISO_EN    (BIT(26))
-#define PMU_HP_SLEEP_I2C_ISO_EN_M  (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S)
-#define PMU_HP_SLEEP_I2C_ISO_EN_V  0x00000001U
-#define PMU_HP_SLEEP_I2C_ISO_EN_S  26
-/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_I2C_RETENTION    (BIT(27))
-#define PMU_HP_SLEEP_I2C_RETENTION_M  (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S)
-#define PMU_HP_SLEEP_I2C_RETENTION_V  0x00000001U
-#define PMU_HP_SLEEP_I2C_RETENTION_S  27
-/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BB_I2C    (BIT(28))
-#define PMU_HP_SLEEP_XPD_BB_I2C_M  (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S)
-#define PMU_HP_SLEEP_XPD_BB_I2C_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BB_I2C_S  28
-/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C    (BIT(29))
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M  (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S)
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S  29
-/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BBPLL    (BIT(30))
-#define PMU_HP_SLEEP_XPD_BBPLL_M  (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S)
-#define PMU_HP_SLEEP_XPD_BBPLL_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BBPLL_S  30
-
-/** PMU_HP_SLEEP_BIAS_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80)
-/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_BIAS    (BIT(25))
-#define PMU_HP_SLEEP_XPD_BIAS_M  (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S)
-#define PMU_HP_SLEEP_XPD_BIAS_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_BIAS_S  25
-/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DBG_ATTEN    0x0000000FU
-#define PMU_HP_SLEEP_DBG_ATTEN_M  (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S)
-#define PMU_HP_SLEEP_DBG_ATTEN_V  0x0000000FU
-#define PMU_HP_SLEEP_DBG_ATTEN_S  26
-/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_CUR    (BIT(30))
-#define PMU_HP_SLEEP_PD_CUR_M  (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S)
-#define PMU_HP_SLEEP_PD_CUR_V  0x00000001U
-#define PMU_HP_SLEEP_PD_CUR_S  30
-/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_BIAS_SLEEP    (BIT(31))
-#define PMU_HP_SLEEP_BIAS_SLEEP_M  (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S)
-#define PMU_HP_SLEEP_BIAS_SLEEP_V  0x00000001U
-#define PMU_HP_SLEEP_BIAS_SLEEP_S  31
-
-/** PMU_HP_SLEEP_BACKUP_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84)
-/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S  6
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE    0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V  0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S  8
-/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_RETENTION_MODE    (BIT(10))
-#define PMU_HP_SLEEP_RETENTION_MODE_M  (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S)
-#define PMU_HP_SLEEP_RETENTION_MODE_V  0x00000001U
-#define PMU_HP_SLEEP_RETENTION_MODE_S  10
-/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_RETENTION_EN    (BIT(12))
-#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M  (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S)
-#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V  0x00000001U
-#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S  12
-/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN    (BIT(13))
-#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M  (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S)
-#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V  0x00000001U
-#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S  13
-/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S  16
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL    0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V  0x00000003U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S  18
-/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE    0x00000007U
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M  (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V  0x00000007U
-#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S  23
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE    0x00000007U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V  0x00000007U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S  26
-/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN    (BIT(30))
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M  (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S)
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V  0x00000001U
-#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S  30
-/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN    (BIT(31))
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M  (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S)
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V  0x00000001U
-#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S  31
-
-/** PMU_HP_SLEEP_BACKUP_CLK_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88)
-/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN    0xFFFFFFFFU
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M  (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S)
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V  0xFFFFFFFFU
-#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S  0
-
-/** PMU_HP_SLEEP_SYSCLK_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c)
-/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV    (BIT(26))
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M  (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S)
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V  0x00000001U
-#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S  26
-/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN    (BIT(27))
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M  (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S)
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V  0x00000001U
-#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S  27
-/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL    (BIT(28))
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M  (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S)
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V  0x00000001U
-#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S  28
-/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_ICG_SLP_SEL    (BIT(29))
-#define PMU_HP_SLEEP_ICG_SLP_SEL_M  (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S)
-#define PMU_HP_SLEEP_ICG_SLP_SEL_V  0x00000001U
-#define PMU_HP_SLEEP_ICG_SLP_SEL_S  29
-/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL    0x00000003U
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M  (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S)
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V  0x00000003U
-#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S  30
-
-/** PMU_HP_SLEEP_HP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90)
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD    (BIT(16))
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S  16
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD    (BIT(17))
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S  17
-/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD    (BIT(18))
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M  (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S  18
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS    0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V  0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S  19
-/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS    0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V  0x0000000FU
-#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S  23
-/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S  27
-
-/** PMU_HP_SLEEP_HP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94)
-/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B    0x00FFFFFFU
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S)
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V  0x00FFFFFFU
-#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S  8
-
-/** PMU_HP_SLEEP_XTAL_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98)
-/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_XTAL    (BIT(31))
-#define PMU_HP_SLEEP_XPD_XTAL_M  (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S)
-#define PMU_HP_SLEEP_XPD_XTAL_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_XTAL_S  31
-
-/** PMU_HP_SLEEP_LP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c)
-/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
-/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M  (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
-#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S  22
-/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
-/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S  27
-
-/** PMU_HP_SLEEP_LP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0)
-/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B    0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S)
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000000FU
-#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S  28
-
-/** PMU_HP_SLEEP_LP_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8)
-/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_MEM_DSLP    (BIT(30))
-#define PMU_HP_SLEEP_LP_MEM_DSLP_M  (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S)
-#define PMU_HP_SLEEP_LP_MEM_DSLP_V  0x00000001U
-#define PMU_HP_SLEEP_LP_MEM_DSLP_S  30
-/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S)
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
-#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S  31
-
-/** PMU_HP_SLEEP_LP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac)
-/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_XTAL32K    (BIT(28))
-#define PMU_HP_SLEEP_XPD_XTAL32K_M  (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S)
-#define PMU_HP_SLEEP_XPD_XTAL32K_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_XTAL32K_S  28
-/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_RC32K    (BIT(29))
-#define PMU_HP_SLEEP_XPD_RC32K_M  (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S)
-#define PMU_HP_SLEEP_XPD_RC32K_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_RC32K_S  29
-/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_HP_SLEEP_XPD_FOSC_CLK    (BIT(30))
-#define PMU_HP_SLEEP_XPD_FOSC_CLK_M  (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S)
-#define PMU_HP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
-#define PMU_HP_SLEEP_XPD_FOSC_CLK_S  30
-/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SLEEP_PD_OSC_CLK    (BIT(31))
-#define PMU_HP_SLEEP_PD_OSC_CLK_M  (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S)
-#define PMU_HP_SLEEP_PD_OSC_CLK_V  0x00000001U
-#define PMU_HP_SLEEP_PD_OSC_CLK_S  31
-
-/** PMU_LP_SLEEP_LP_REGULATOR0_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4)
-/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD    (BIT(21))
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V  0x00000001U
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S  21
-/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD    (BIT(22))
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M  (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V  0x00000001U
-#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S  22
-/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS    0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V  0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S  23
-/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS    0x0000001FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M  (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V  0x0000001FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S  27
-
-/** PMU_LP_SLEEP_LP_REGULATOR1_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8)
-/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B    0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M  (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S)
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V  0x0000000FU
-#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S  28
-
-/** PMU_LP_SLEEP_XTAL_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc)
-/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_XTAL    (BIT(31))
-#define PMU_LP_SLEEP_XPD_XTAL_M  (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S)
-#define PMU_LP_SLEEP_XPD_XTAL_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_XTAL_S  31
-
-/** PMU_LP_SLEEP_LP_DIG_POWER_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0)
-/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_MEM_DSLP    (BIT(30))
-#define PMU_LP_SLEEP_LP_MEM_DSLP_M  (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S)
-#define PMU_LP_SLEEP_LP_MEM_DSLP_V  0x00000001U
-#define PMU_LP_SLEEP_LP_MEM_DSLP_S  30
-/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN    (BIT(31))
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M  (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S)
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V  0x00000001U
-#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S  31
-
-/** PMU_LP_SLEEP_LP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4)
-/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_XTAL32K    (BIT(28))
-#define PMU_LP_SLEEP_XPD_XTAL32K_M  (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S)
-#define PMU_LP_SLEEP_XPD_XTAL32K_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_XTAL32K_S  28
-/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_RC32K    (BIT(29))
-#define PMU_LP_SLEEP_XPD_RC32K_M  (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S)
-#define PMU_LP_SLEEP_XPD_RC32K_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_RC32K_S  29
-/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_FOSC_CLK    (BIT(30))
-#define PMU_LP_SLEEP_XPD_FOSC_CLK_M  (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S)
-#define PMU_LP_SLEEP_XPD_FOSC_CLK_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_FOSC_CLK_S  30
-/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_PD_OSC_CLK    (BIT(31))
-#define PMU_LP_SLEEP_PD_OSC_CLK_M  (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S)
-#define PMU_LP_SLEEP_PD_OSC_CLK_V  0x00000001U
-#define PMU_LP_SLEEP_PD_OSC_CLK_S  31
-
-/** PMU_LP_SLEEP_BIAS_REG register
- *  need_des
- */
-#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8)
-/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_XPD_BIAS    (BIT(25))
-#define PMU_LP_SLEEP_XPD_BIAS_M  (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S)
-#define PMU_LP_SLEEP_XPD_BIAS_V  0x00000001U
-#define PMU_LP_SLEEP_XPD_BIAS_S  25
-/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_DBG_ATTEN    0x0000000FU
-#define PMU_LP_SLEEP_DBG_ATTEN_M  (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S)
-#define PMU_LP_SLEEP_DBG_ATTEN_V  0x0000000FU
-#define PMU_LP_SLEEP_DBG_ATTEN_S  26
-/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_PD_CUR    (BIT(30))
-#define PMU_LP_SLEEP_PD_CUR_M  (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S)
-#define PMU_LP_SLEEP_PD_CUR_V  0x00000001U
-#define PMU_LP_SLEEP_PD_CUR_S  30
-/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_SLEEP_BIAS_SLEEP    (BIT(31))
-#define PMU_LP_SLEEP_BIAS_SLEEP_M  (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S)
-#define PMU_LP_SLEEP_BIAS_SLEEP_V  0x00000001U
-#define PMU_LP_SLEEP_BIAS_SLEEP_S  31
-
-/** PMU_IMM_HP_CK_POWER_REG register
- *  need_des
- */
-#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc)
-/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG    (BIT(0))
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M  (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S)
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V  0x00000001U
-#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S  0
-/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG    (BIT(1))
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M  (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S)
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V  0x00000001U
-#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S  1
-/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_I2C_RETENTION    (BIT(2))
-#define PMU_TIE_LOW_I2C_RETENTION_M  (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S)
-#define PMU_TIE_LOW_I2C_RETENTION_V  0x00000001U
-#define PMU_TIE_LOW_I2C_RETENTION_S  2
-/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_BB_I2C    (BIT(3))
-#define PMU_TIE_LOW_XPD_BB_I2C_M  (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S)
-#define PMU_TIE_LOW_XPD_BB_I2C_V  0x00000001U
-#define PMU_TIE_LOW_XPD_BB_I2C_S  3
-/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_BBPLL_I2C    (BIT(4))
-#define PMU_TIE_LOW_XPD_BBPLL_I2C_M  (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S)
-#define PMU_TIE_LOW_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_TIE_LOW_XPD_BBPLL_I2C_S  4
-/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_BBPLL    (BIT(5))
-#define PMU_TIE_LOW_XPD_BBPLL_M  (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S)
-#define PMU_TIE_LOW_XPD_BBPLL_V  0x00000001U
-#define PMU_TIE_LOW_XPD_BBPLL_S  5
-/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_XPD_XTAL    (BIT(6))
-#define PMU_TIE_LOW_XPD_XTAL_M  (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S)
-#define PMU_TIE_LOW_XPD_XTAL_V  0x00000001U
-#define PMU_TIE_LOW_XPD_XTAL_S  6
-/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG    (BIT(25))
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M  (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S)
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V  0x00000001U
-#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S  25
-/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG    (BIT(26))
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M  (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S)
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V  0x00000001U
-#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S  26
-/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_I2C_RETENTION    (BIT(27))
-#define PMU_TIE_HIGH_I2C_RETENTION_M  (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S)
-#define PMU_TIE_HIGH_I2C_RETENTION_V  0x00000001U
-#define PMU_TIE_HIGH_I2C_RETENTION_S  27
-/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_BB_I2C    (BIT(28))
-#define PMU_TIE_HIGH_XPD_BB_I2C_M  (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S)
-#define PMU_TIE_HIGH_XPD_BB_I2C_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_BB_I2C_S  28
-/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C    (BIT(29))
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M  (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S)
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S  29
-/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_BBPLL    (BIT(30))
-#define PMU_TIE_HIGH_XPD_BBPLL_M  (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S)
-#define PMU_TIE_HIGH_XPD_BBPLL_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_BBPLL_S  30
-/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_XPD_XTAL    (BIT(31))
-#define PMU_TIE_HIGH_XPD_XTAL_M  (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S)
-#define PMU_TIE_HIGH_XPD_XTAL_V  0x00000001U
-#define PMU_TIE_HIGH_XPD_XTAL_S  31
-
-/** PMU_IMM_SLEEP_SYSCLK_REG register
- *  need_des
- */
-#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0)
-/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_SWITCH    (BIT(28))
-#define PMU_UPDATE_DIG_ICG_SWITCH_M  (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S)
-#define PMU_UPDATE_DIG_ICG_SWITCH_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_SWITCH_S  28
-/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_ICG_SLP_SEL    (BIT(29))
-#define PMU_TIE_LOW_ICG_SLP_SEL_M  (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S)
-#define PMU_TIE_LOW_ICG_SLP_SEL_V  0x00000001U
-#define PMU_TIE_LOW_ICG_SLP_SEL_S  29
-/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_ICG_SLP_SEL    (BIT(30))
-#define PMU_TIE_HIGH_ICG_SLP_SEL_M  (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S)
-#define PMU_TIE_HIGH_ICG_SLP_SEL_V  0x00000001U
-#define PMU_TIE_HIGH_ICG_SLP_SEL_S  30
-/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_SYS_CLK_SEL    (BIT(31))
-#define PMU_UPDATE_DIG_SYS_CLK_SEL_M  (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S)
-#define PMU_UPDATE_DIG_SYS_CLK_SEL_V  0x00000001U
-#define PMU_UPDATE_DIG_SYS_CLK_SEL_S  31
-
-/** PMU_IMM_HP_FUNC_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4)
-/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_FUNC_EN    (BIT(31))
-#define PMU_UPDATE_DIG_ICG_FUNC_EN_M  (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S)
-#define PMU_UPDATE_DIG_ICG_FUNC_EN_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_FUNC_EN_S  31
-
-/** PMU_IMM_HP_APB_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8)
-/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_APB_EN    (BIT(31))
-#define PMU_UPDATE_DIG_ICG_APB_EN_M  (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S)
-#define PMU_UPDATE_DIG_ICG_APB_EN_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_APB_EN_S  31
-
-/** PMU_IMM_MODEM_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc)
-/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_UPDATE_DIG_ICG_MODEM_EN    (BIT(31))
-#define PMU_UPDATE_DIG_ICG_MODEM_EN_M  (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S)
-#define PMU_UPDATE_DIG_ICG_MODEM_EN_V  0x00000001U
-#define PMU_UPDATE_DIG_ICG_MODEM_EN_S  31
-
-/** PMU_IMM_LP_ICG_REG register
- *  need_des
- */
-#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0)
-/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL    (BIT(30))
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M  (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S)
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V  0x00000001U
-#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S  30
-/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL    (BIT(31))
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M  (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S)
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V  0x00000001U
-#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S  31
-
-/** PMU_IMM_PAD_HOLD_ALL_REG register
- *  need_des
- */
-#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4)
-/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL    (BIT(28))
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S)
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S  28
-/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL    (BIT(29))
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S)
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S  29
-/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL    (BIT(30))
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M  (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S)
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S  30
-/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL    (BIT(31))
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M  (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S)
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V  0x00000001U
-#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S  31
-
-/** PMU_IMM_I2C_ISO_REG register
- *  need_des
- */
-#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8)
-/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_TIE_HIGH_I2C_ISO_EN    (BIT(30))
-#define PMU_TIE_HIGH_I2C_ISO_EN_M  (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S)
-#define PMU_TIE_HIGH_I2C_ISO_EN_V  0x00000001U
-#define PMU_TIE_HIGH_I2C_ISO_EN_S  30
-/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_TIE_LOW_I2C_ISO_EN    (BIT(31))
-#define PMU_TIE_LOW_I2C_ISO_EN_M  (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S)
-#define PMU_TIE_LOW_I2C_ISO_EN_V  0x00000001U
-#define PMU_TIE_LOW_I2C_ISO_EN_S  31
-
-/** PMU_POWER_WAIT_TIMER0_REG register
- *  need_des
- */
-#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec)
-/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_POWERDOWN_TIMER    0x000001FFU
-#define PMU_DG_HP_POWERDOWN_TIMER_M  (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S)
-#define PMU_DG_HP_POWERDOWN_TIMER_V  0x000001FFU
-#define PMU_DG_HP_POWERDOWN_TIMER_S  5
-/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_POWERUP_TIMER    0x000001FFU
-#define PMU_DG_HP_POWERUP_TIMER_M  (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S)
-#define PMU_DG_HP_POWERUP_TIMER_V  0x000001FFU
-#define PMU_DG_HP_POWERUP_TIMER_S  14
-/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
- *  need_des
- */
-#define PMU_DG_HP_WAIT_TIMER    0x000001FFU
-#define PMU_DG_HP_WAIT_TIMER_M  (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S)
-#define PMU_DG_HP_WAIT_TIMER_V  0x000001FFU
-#define PMU_DG_HP_WAIT_TIMER_S  23
-
-/** PMU_POWER_WAIT_TIMER1_REG register
- *  need_des
- */
-#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0)
-/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255;
- *  need_des
- */
-#define PMU_DG_LP_POWERDOWN_TIMER    0x0000007FU
-#define PMU_DG_LP_POWERDOWN_TIMER_M  (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S)
-#define PMU_DG_LP_POWERDOWN_TIMER_V  0x0000007FU
-#define PMU_DG_LP_POWERDOWN_TIMER_S  9
-/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255;
- *  need_des
- */
-#define PMU_DG_LP_POWERUP_TIMER    0x0000007FU
-#define PMU_DG_LP_POWERUP_TIMER_M  (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S)
-#define PMU_DG_LP_POWERUP_TIMER_V  0x0000007FU
-#define PMU_DG_LP_POWERUP_TIMER_S  16
-/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255;
- *  need_des
- */
-#define PMU_DG_LP_WAIT_TIMER    0x000001FFU
-#define PMU_DG_LP_WAIT_TIMER_M  (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S)
-#define PMU_DG_LP_WAIT_TIMER_V  0x000001FFU
-#define PMU_DG_LP_WAIT_TIMER_S  23
-
-/** PMU_POWER_PD_TOP_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4)
-/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_TOP_RESET    (BIT(0))
-#define PMU_FORCE_TOP_RESET_M  (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S)
-#define PMU_FORCE_TOP_RESET_V  0x00000001U
-#define PMU_FORCE_TOP_RESET_S  0
-/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_TOP_ISO    (BIT(1))
-#define PMU_FORCE_TOP_ISO_M  (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S)
-#define PMU_FORCE_TOP_ISO_V  0x00000001U
-#define PMU_FORCE_TOP_ISO_S  1
-/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_TOP_PU    (BIT(2))
-#define PMU_FORCE_TOP_PU_M  (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S)
-#define PMU_FORCE_TOP_PU_V  0x00000001U
-#define PMU_FORCE_TOP_PU_S  2
-/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_TOP_NO_RESET    (BIT(3))
-#define PMU_FORCE_TOP_NO_RESET_M  (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S)
-#define PMU_FORCE_TOP_NO_RESET_V  0x00000001U
-#define PMU_FORCE_TOP_NO_RESET_S  3
-/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_TOP_NO_ISO    (BIT(4))
-#define PMU_FORCE_TOP_NO_ISO_M  (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S)
-#define PMU_FORCE_TOP_NO_ISO_V  0x00000001U
-#define PMU_FORCE_TOP_NO_ISO_S  4
-/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_TOP_PD    (BIT(5))
-#define PMU_FORCE_TOP_PD_M  (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S)
-#define PMU_FORCE_TOP_PD_V  0x00000001U
-#define PMU_FORCE_TOP_PD_S  5
-/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_TOP_MASK    0x0000001FU
-#define PMU_PD_TOP_MASK_M  (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S)
-#define PMU_PD_TOP_MASK_V  0x0000001FU
-#define PMU_PD_TOP_MASK_S  6
-/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_TOP_PD_MASK    0x0000001FU
-#define PMU_PD_TOP_PD_MASK_M  (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S)
-#define PMU_PD_TOP_PD_MASK_V  0x0000001FU
-#define PMU_PD_TOP_PD_MASK_S  27
-
-/** PMU_POWER_PD_HPAON_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8)
-/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_RESET    (BIT(0))
-#define PMU_FORCE_HP_AON_RESET_M  (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S)
-#define PMU_FORCE_HP_AON_RESET_V  0x00000001U
-#define PMU_FORCE_HP_AON_RESET_S  0
-/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_ISO    (BIT(1))
-#define PMU_FORCE_HP_AON_ISO_M  (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S)
-#define PMU_FORCE_HP_AON_ISO_V  0x00000001U
-#define PMU_FORCE_HP_AON_ISO_S  1
-/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_PU    (BIT(2))
-#define PMU_FORCE_HP_AON_PU_M  (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S)
-#define PMU_FORCE_HP_AON_PU_V  0x00000001U
-#define PMU_FORCE_HP_AON_PU_S  2
-/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_NO_RESET    (BIT(3))
-#define PMU_FORCE_HP_AON_NO_RESET_M  (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S)
-#define PMU_FORCE_HP_AON_NO_RESET_V  0x00000001U
-#define PMU_FORCE_HP_AON_NO_RESET_S  3
-/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_NO_ISO    (BIT(4))
-#define PMU_FORCE_HP_AON_NO_ISO_M  (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S)
-#define PMU_FORCE_HP_AON_NO_ISO_V  0x00000001U
-#define PMU_FORCE_HP_AON_NO_ISO_S  4
-/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_AON_PD    (BIT(5))
-#define PMU_FORCE_HP_AON_PD_M  (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S)
-#define PMU_FORCE_HP_AON_PD_V  0x00000001U
-#define PMU_FORCE_HP_AON_PD_S  5
-/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_AON_MASK    0x0000001FU
-#define PMU_PD_HP_AON_MASK_M  (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S)
-#define PMU_PD_HP_AON_MASK_V  0x0000001FU
-#define PMU_PD_HP_AON_MASK_S  6
-/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_AON_PD_MASK    0x0000001FU
-#define PMU_PD_HP_AON_PD_MASK_M  (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S)
-#define PMU_PD_HP_AON_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_AON_PD_MASK_S  27
-
-/** PMU_POWER_PD_HPCPU_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc)
-/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_RESET    (BIT(0))
-#define PMU_FORCE_HP_CPU_RESET_M  (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S)
-#define PMU_FORCE_HP_CPU_RESET_V  0x00000001U
-#define PMU_FORCE_HP_CPU_RESET_S  0
-/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_ISO    (BIT(1))
-#define PMU_FORCE_HP_CPU_ISO_M  (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S)
-#define PMU_FORCE_HP_CPU_ISO_V  0x00000001U
-#define PMU_FORCE_HP_CPU_ISO_S  1
-/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_PU    (BIT(2))
-#define PMU_FORCE_HP_CPU_PU_M  (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S)
-#define PMU_FORCE_HP_CPU_PU_V  0x00000001U
-#define PMU_FORCE_HP_CPU_PU_S  2
-/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_NO_RESET    (BIT(3))
-#define PMU_FORCE_HP_CPU_NO_RESET_M  (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S)
-#define PMU_FORCE_HP_CPU_NO_RESET_V  0x00000001U
-#define PMU_FORCE_HP_CPU_NO_RESET_S  3
-/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_NO_ISO    (BIT(4))
-#define PMU_FORCE_HP_CPU_NO_ISO_M  (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S)
-#define PMU_FORCE_HP_CPU_NO_ISO_V  0x00000001U
-#define PMU_FORCE_HP_CPU_NO_ISO_S  4
-/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_CPU_PD    (BIT(5))
-#define PMU_FORCE_HP_CPU_PD_M  (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S)
-#define PMU_FORCE_HP_CPU_PD_V  0x00000001U
-#define PMU_FORCE_HP_CPU_PD_S  5
-/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_CPU_MASK    0x0000001FU
-#define PMU_PD_HP_CPU_MASK_M  (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S)
-#define PMU_PD_HP_CPU_MASK_V  0x0000001FU
-#define PMU_PD_HP_CPU_MASK_S  6
-/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_CPU_PD_MASK    0x0000001FU
-#define PMU_PD_HP_CPU_PD_MASK_M  (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S)
-#define PMU_PD_HP_CPU_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_CPU_PD_MASK_S  27
-
-/** PMU_POWER_PD_HPWIFI_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104)
-/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_RESET    (BIT(0))
-#define PMU_FORCE_HP_WIFI_RESET_M  (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S)
-#define PMU_FORCE_HP_WIFI_RESET_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_RESET_S  0
-/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_ISO    (BIT(1))
-#define PMU_FORCE_HP_WIFI_ISO_M  (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S)
-#define PMU_FORCE_HP_WIFI_ISO_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_ISO_S  1
-/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_PU    (BIT(2))
-#define PMU_FORCE_HP_WIFI_PU_M  (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S)
-#define PMU_FORCE_HP_WIFI_PU_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_PU_S  2
-/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_NO_RESET    (BIT(3))
-#define PMU_FORCE_HP_WIFI_NO_RESET_M  (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S)
-#define PMU_FORCE_HP_WIFI_NO_RESET_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_NO_RESET_S  3
-/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_NO_ISO    (BIT(4))
-#define PMU_FORCE_HP_WIFI_NO_ISO_M  (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S)
-#define PMU_FORCE_HP_WIFI_NO_ISO_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_NO_ISO_S  4
-/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_WIFI_PD    (BIT(5))
-#define PMU_FORCE_HP_WIFI_PD_M  (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S)
-#define PMU_FORCE_HP_WIFI_PD_V  0x00000001U
-#define PMU_FORCE_HP_WIFI_PD_S  5
-/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_WIFI_MASK    0x0000001FU
-#define PMU_PD_HP_WIFI_MASK_M  (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S)
-#define PMU_PD_HP_WIFI_MASK_V  0x0000001FU
-#define PMU_PD_HP_WIFI_MASK_S  6
-/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_WIFI_PD_MASK    0x0000001FU
-#define PMU_PD_HP_WIFI_PD_MASK_M  (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S)
-#define PMU_PD_HP_WIFI_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_WIFI_PD_MASK_S  27
-
-/** PMU_POWER_PD_LPPERI_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108)
-/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_RESET    (BIT(0))
-#define PMU_FORCE_LP_PERI_RESET_M  (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S)
-#define PMU_FORCE_LP_PERI_RESET_V  0x00000001U
-#define PMU_FORCE_LP_PERI_RESET_S  0
-/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_ISO    (BIT(1))
-#define PMU_FORCE_LP_PERI_ISO_M  (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S)
-#define PMU_FORCE_LP_PERI_ISO_V  0x00000001U
-#define PMU_FORCE_LP_PERI_ISO_S  1
-/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_PU    (BIT(2))
-#define PMU_FORCE_LP_PERI_PU_M  (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S)
-#define PMU_FORCE_LP_PERI_PU_V  0x00000001U
-#define PMU_FORCE_LP_PERI_PU_S  2
-/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_NO_RESET    (BIT(3))
-#define PMU_FORCE_LP_PERI_NO_RESET_M  (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S)
-#define PMU_FORCE_LP_PERI_NO_RESET_V  0x00000001U
-#define PMU_FORCE_LP_PERI_NO_RESET_S  3
-/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_NO_ISO    (BIT(4))
-#define PMU_FORCE_LP_PERI_NO_ISO_M  (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S)
-#define PMU_FORCE_LP_PERI_NO_ISO_V  0x00000001U
-#define PMU_FORCE_LP_PERI_NO_ISO_S  4
-/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_LP_PERI_PD    (BIT(5))
-#define PMU_FORCE_LP_PERI_PD_M  (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S)
-#define PMU_FORCE_LP_PERI_PD_V  0x00000001U
-#define PMU_FORCE_LP_PERI_PD_S  5
-
-/** PMU_POWER_PD_MEM_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c)
-/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_ISO    0x0000000FU
-#define PMU_FORCE_HP_MEM_ISO_M  (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S)
-#define PMU_FORCE_HP_MEM_ISO_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_ISO_S  0
-/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_PD    0x0000000FU
-#define PMU_FORCE_HP_MEM_PD_M  (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S)
-#define PMU_FORCE_HP_MEM_PD_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_PD_S  4
-/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_NO_ISO    0x0000000FU
-#define PMU_FORCE_HP_MEM_NO_ISO_M  (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S)
-#define PMU_FORCE_HP_MEM_NO_ISO_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_NO_ISO_S  24
-/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15;
- *  need_des
- */
-#define PMU_FORCE_HP_MEM_PU    0x0000000FU
-#define PMU_FORCE_HP_MEM_PU_M  (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S)
-#define PMU_FORCE_HP_MEM_PU_V  0x0000000FU
-#define PMU_FORCE_HP_MEM_PU_S  28
-
-/** PMU_POWER_PD_MEM_MASK_REG register
- *  need_des
- */
-#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110)
-/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM2_PD_MASK    0x0000001FU
-#define PMU_PD_HP_MEM2_PD_MASK_M  (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S)
-#define PMU_PD_HP_MEM2_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM2_PD_MASK_S  0
-/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM1_PD_MASK    0x0000001FU
-#define PMU_PD_HP_MEM1_PD_MASK_M  (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S)
-#define PMU_PD_HP_MEM1_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM1_PD_MASK_S  5
-/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM0_PD_MASK    0x0000001FU
-#define PMU_PD_HP_MEM0_PD_MASK_M  (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S)
-#define PMU_PD_HP_MEM0_PD_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM0_PD_MASK_S  10
-/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM2_MASK    0x0000001FU
-#define PMU_PD_HP_MEM2_MASK_M  (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S)
-#define PMU_PD_HP_MEM2_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM2_MASK_S  17
-/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM1_MASK    0x0000001FU
-#define PMU_PD_HP_MEM1_MASK_M  (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S)
-#define PMU_PD_HP_MEM1_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM1_MASK_S  22
-/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0;
- *  need_des
- */
-#define PMU_PD_HP_MEM0_MASK    0x0000001FU
-#define PMU_PD_HP_MEM0_MASK_M  (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S)
-#define PMU_PD_HP_MEM0_MASK_V  0x0000001FU
-#define PMU_PD_HP_MEM0_MASK_S  27
-
-/** PMU_POWER_HP_PAD_REG register
- *  need_des
- */
-#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114)
-/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL    (BIT(0))
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M  (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S)
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V  0x00000001U
-#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S  0
-/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_FORCE_HP_PAD_ISO_ALL    (BIT(1))
-#define PMU_FORCE_HP_PAD_ISO_ALL_M  (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S)
-#define PMU_FORCE_HP_PAD_ISO_ALL_V  0x00000001U
-#define PMU_FORCE_HP_PAD_ISO_ALL_S  1
-
-/** PMU_POWER_VDD_SPI_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118)
-/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255;
- *  need_des
- */
-#define PMU_VDD_SPI_PWR_WAIT    0x000007FFU
-#define PMU_VDD_SPI_PWR_WAIT_M  (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S)
-#define PMU_VDD_SPI_PWR_WAIT_V  0x000007FFU
-#define PMU_VDD_SPI_PWR_WAIT_S  18
-/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3;
- *  need_des
- */
-#define PMU_VDD_SPI_PWR_SW    0x00000003U
-#define PMU_VDD_SPI_PWR_SW_M  (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S)
-#define PMU_VDD_SPI_PWR_SW_V  0x00000003U
-#define PMU_VDD_SPI_PWR_SW_S  29
-/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_VDD_SPI_PWR_SEL_SW    (BIT(31))
-#define PMU_VDD_SPI_PWR_SEL_SW_M  (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S)
-#define PMU_VDD_SPI_PWR_SEL_SW_V  0x00000001U
-#define PMU_VDD_SPI_PWR_SEL_SW_S  31
-
-/** PMU_POWER_CK_WAIT_CNTL_REG register
- *  need_des
- */
-#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c)
-/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256;
- *  need_des
- */
-#define PMU_WAIT_XTL_STABLE    0x0000FFFFU
-#define PMU_WAIT_XTL_STABLE_M  (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S)
-#define PMU_WAIT_XTL_STABLE_V  0x0000FFFFU
-#define PMU_WAIT_XTL_STABLE_S  0
-/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256;
- *  need_des
- */
-#define PMU_WAIT_PLL_STABLE    0x0000FFFFU
-#define PMU_WAIT_PLL_STABLE_M  (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S)
-#define PMU_WAIT_PLL_STABLE_V  0x0000FFFFU
-#define PMU_WAIT_PLL_STABLE_S  16
-
-/** PMU_SLP_WAKEUP_CNTL0_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120)
-/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_REQ    (BIT(31))
-#define PMU_SLEEP_REQ_M  (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S)
-#define PMU_SLEEP_REQ_V  0x00000001U
-#define PMU_SLEEP_REQ_S  31
-
-/** PMU_SLP_WAKEUP_CNTL1_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124)
-/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_REJECT_ENA    0x7FFFFFFFU
-#define PMU_SLEEP_REJECT_ENA_M  (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S)
-#define PMU_SLEEP_REJECT_ENA_V  0x7FFFFFFFU
-#define PMU_SLEEP_REJECT_ENA_S  0
-/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SLP_REJECT_EN    (BIT(31))
-#define PMU_SLP_REJECT_EN_M  (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S)
-#define PMU_SLP_REJECT_EN_V  0x00000001U
-#define PMU_SLP_REJECT_EN_S  31
-
-/** PMU_SLP_WAKEUP_CNTL2_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128)
-/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_WAKEUP_ENA    0xFFFFFFFFU
-#define PMU_WAKEUP_ENA_M  (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S)
-#define PMU_WAKEUP_ENA_V  0xFFFFFFFFU
-#define PMU_WAKEUP_ENA_S  0
-
-/** PMU_SLP_WAKEUP_CNTL3_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c)
-/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0;
- *  need_des
- */
-#define PMU_LP_MIN_SLP_VAL    0x000000FFU
-#define PMU_LP_MIN_SLP_VAL_M  (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S)
-#define PMU_LP_MIN_SLP_VAL_V  0x000000FFU
-#define PMU_LP_MIN_SLP_VAL_S  0
-/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0;
- *  need_des
- */
-#define PMU_HP_MIN_SLP_VAL    0x000000FFU
-#define PMU_HP_MIN_SLP_VAL_M  (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S)
-#define PMU_HP_MIN_SLP_VAL_V  0x000000FFU
-#define PMU_HP_MIN_SLP_VAL_S  8
-/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_PRT_SEL    0x00000003U
-#define PMU_SLEEP_PRT_SEL_M  (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S)
-#define PMU_SLEEP_PRT_SEL_V  0x00000003U
-#define PMU_SLEEP_PRT_SEL_S  16
-
-/** PMU_SLP_WAKEUP_CNTL4_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130)
-/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SLP_REJECT_CAUSE_CLR    (BIT(31))
-#define PMU_SLP_REJECT_CAUSE_CLR_M  (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S)
-#define PMU_SLP_REJECT_CAUSE_CLR_V  0x00000001U
-#define PMU_SLP_REJECT_CAUSE_CLR_S  31
-
-/** PMU_SLP_WAKEUP_CNTL5_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134)
-/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128;
- *  need_des
- */
-#define PMU_MODEM_WAIT_TARGET    0x000FFFFFU
-#define PMU_MODEM_WAIT_TARGET_M  (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S)
-#define PMU_MODEM_WAIT_TARGET_V  0x000FFFFFU
-#define PMU_MODEM_WAIT_TARGET_S  0
-/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1;
- *  need_des
- */
-#define PMU_LP_ANA_WAIT_TARGET    0x000000FFU
-#define PMU_LP_ANA_WAIT_TARGET_M  (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S)
-#define PMU_LP_ANA_WAIT_TARGET_V  0x000000FFU
-#define PMU_LP_ANA_WAIT_TARGET_S  24
-
-/** PMU_SLP_WAKEUP_CNTL6_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138)
-/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_WAIT    0x000FFFFFU
-#define PMU_SOC_WAKEUP_WAIT_M  (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S)
-#define PMU_SOC_WAKEUP_WAIT_V  0x000FFFFFU
-#define PMU_SOC_WAKEUP_WAIT_S  0
-/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_WAIT_CFG    0x00000003U
-#define PMU_SOC_WAKEUP_WAIT_CFG_M  (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S)
-#define PMU_SOC_WAKEUP_WAIT_CFG_V  0x00000003U
-#define PMU_SOC_WAKEUP_WAIT_CFG_S  30
-
-/** PMU_SLP_WAKEUP_CNTL7_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c)
-/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1;
- *  need_des
- */
-#define PMU_ANA_WAIT_TARGET    0x0000FFFFU
-#define PMU_ANA_WAIT_TARGET_M  (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S)
-#define PMU_ANA_WAIT_TARGET_V  0x0000FFFFU
-#define PMU_ANA_WAIT_TARGET_S  16
-
-/** PMU_SLP_WAKEUP_STATUS0_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140)
-/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_WAKEUP_CAUSE    0xFFFFFFFFU
-#define PMU_WAKEUP_CAUSE_M  (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S)
-#define PMU_WAKEUP_CAUSE_V  0xFFFFFFFFU
-#define PMU_WAKEUP_CAUSE_S  0
-
-/** PMU_SLP_WAKEUP_STATUS1_REG register
- *  need_des
- */
-#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144)
-/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define PMU_REJECT_CAUSE    0xFFFFFFFFU
-#define PMU_REJECT_CAUSE_M  (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S)
-#define PMU_REJECT_CAUSE_V  0xFFFFFFFFU
-#define PMU_REJECT_CAUSE_S  0
-
-/** PMU_HP_CK_POWERON_REG register
- *  need_des
- */
-#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148)
-/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50;
- *  need_des
- */
-#define PMU_I2C_POR_WAIT_TARGET    0x000000FFU
-#define PMU_I2C_POR_WAIT_TARGET_M  (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S)
-#define PMU_I2C_POR_WAIT_TARGET_V  0x000000FFU
-#define PMU_I2C_POR_WAIT_TARGET_S  0
-
-/** PMU_HP_CK_CNTL_REG register
- *  need_des
- */
-#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c)
-/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10;
- *  need_des
- */
-#define PMU_MODIFY_ICG_CNTL_WAIT    0x000000FFU
-#define PMU_MODIFY_ICG_CNTL_WAIT_M  (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S)
-#define PMU_MODIFY_ICG_CNTL_WAIT_V  0x000000FFU
-#define PMU_MODIFY_ICG_CNTL_WAIT_S  0
-/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10;
- *  need_des
- */
-#define PMU_SWITCH_ICG_CNTL_WAIT    0x000000FFU
-#define PMU_SWITCH_ICG_CNTL_WAIT_M  (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S)
-#define PMU_SWITCH_ICG_CNTL_WAIT_V  0x000000FFU
-#define PMU_SWITCH_ICG_CNTL_WAIT_S  8
-
-/** PMU_POR_STATUS_REG register
- *  need_des
- */
-#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150)
-/** PMU_POR_DONE : RO; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_POR_DONE    (BIT(31))
-#define PMU_POR_DONE_M  (PMU_POR_DONE_V << PMU_POR_DONE_S)
-#define PMU_POR_DONE_V  0x00000001U
-#define PMU_POR_DONE_S  31
-
-/** PMU_RF_PWC_REG register
- *  need_des
- */
-#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154)
-/** PMU_XPD_TC5G_I2C : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_XPD_TC5G_I2C    (BIT(24))
-#define PMU_XPD_TC5G_I2C_M  (PMU_XPD_TC5G_I2C_V << PMU_XPD_TC5G_I2C_S)
-#define PMU_XPD_TC5G_I2C_V  0x00000001U
-#define PMU_XPD_TC5G_I2C_S  24
-/** PMU_XPD_RX5G_I2C : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_XPD_RX5G_I2C    (BIT(25))
-#define PMU_XPD_RX5G_I2C_M  (PMU_XPD_RX5G_I2C_V << PMU_XPD_RX5G_I2C_S)
-#define PMU_XPD_RX5G_I2C_V  0x00000001U
-#define PMU_XPD_RX5G_I2C_S  25
-/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_PERIF_I2C_RSTB    (BIT(26))
-#define PMU_PERIF_I2C_RSTB_M  (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S)
-#define PMU_PERIF_I2C_RSTB_V  0x00000001U
-#define PMU_PERIF_I2C_RSTB_S  26
-/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1;
- *  need_des
- */
-#define PMU_XPD_PERIF_I2C    (BIT(27))
-#define PMU_XPD_PERIF_I2C_M  (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S)
-#define PMU_XPD_PERIF_I2C_V  0x00000001U
-#define PMU_XPD_PERIF_I2C_S  27
-/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_XPD_TXRF_I2C    (BIT(28))
-#define PMU_XPD_TXRF_I2C_M  (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S)
-#define PMU_XPD_TXRF_I2C_V  0x00000001U
-#define PMU_XPD_TXRF_I2C_S  28
-/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_XPD_RFRX_PBUS    (BIT(29))
-#define PMU_XPD_RFRX_PBUS_M  (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S)
-#define PMU_XPD_RFRX_PBUS_V  0x00000001U
-#define PMU_XPD_RFRX_PBUS_S  29
-/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_XPD_CKGEN_I2C    (BIT(30))
-#define PMU_XPD_CKGEN_I2C_M  (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S)
-#define PMU_XPD_CKGEN_I2C_V  0x00000001U
-#define PMU_XPD_CKGEN_I2C_S  30
-/** PMU_XPD_PLL_I2C : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_XPD_PLL_I2C    (BIT(31))
-#define PMU_XPD_PLL_I2C_M  (PMU_XPD_PLL_I2C_V << PMU_XPD_PLL_I2C_S)
-#define PMU_XPD_PLL_I2C_V  0x00000001U
-#define PMU_XPD_PLL_I2C_S  31
-
-/** PMU_BACKUP_CFG_REG register
- *  need_des
- */
-#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x158)
-/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1;
- *  need_des
- */
-#define PMU_BACKUP_SYS_CLK_NO_DIV    (BIT(31))
-#define PMU_BACKUP_SYS_CLK_NO_DIV_M  (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S)
-#define PMU_BACKUP_SYS_CLK_NO_DIV_V  0x00000001U
-#define PMU_BACKUP_SYS_CLK_NO_DIV_S  31
-
-/** PMU_INT_RAW_REG register
- *  need_des
- */
-#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x15c)
-/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_RAW    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_RAW_M  (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S)
-#define PMU_LP_CPU_EXC_INT_RAW_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_RAW_S  27
-/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_RAW    (BIT(28))
-#define PMU_SDIO_IDLE_INT_RAW_M  (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S)
-#define PMU_SDIO_IDLE_INT_RAW_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_RAW_S  28
-/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_RAW    (BIT(29))
-#define PMU_SW_INT_RAW_M  (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S)
-#define PMU_SW_INT_RAW_V  0x00000001U
-#define PMU_SW_INT_RAW_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_RAW    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_RAW_M  (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S)
-#define PMU_SOC_SLEEP_REJECT_INT_RAW_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_RAW_S  30
-/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_RAW    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_RAW_M  (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S)
-#define PMU_SOC_WAKEUP_INT_RAW_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_RAW_S  31
-
-/** PMU_HP_INT_ST_REG register
- *  need_des
- */
-#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x160)
-/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_ST    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_ST_M  (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S)
-#define PMU_LP_CPU_EXC_INT_ST_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_ST_S  27
-/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_ST    (BIT(28))
-#define PMU_SDIO_IDLE_INT_ST_M  (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S)
-#define PMU_SDIO_IDLE_INT_ST_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_ST_S  28
-/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_ST    (BIT(29))
-#define PMU_SW_INT_ST_M  (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S)
-#define PMU_SW_INT_ST_V  0x00000001U
-#define PMU_SW_INT_ST_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_ST    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_ST_M  (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S)
-#define PMU_SOC_SLEEP_REJECT_INT_ST_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_ST_S  30
-/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_ST    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_ST_M  (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S)
-#define PMU_SOC_WAKEUP_INT_ST_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_ST_S  31
-
-/** PMU_HP_INT_ENA_REG register
- *  need_des
- */
-#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x164)
-/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_ENA    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_ENA_M  (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S)
-#define PMU_LP_CPU_EXC_INT_ENA_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_ENA_S  27
-/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_ENA    (BIT(28))
-#define PMU_SDIO_IDLE_INT_ENA_M  (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S)
-#define PMU_SDIO_IDLE_INT_ENA_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_ENA_S  28
-/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_ENA    (BIT(29))
-#define PMU_SW_INT_ENA_M  (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S)
-#define PMU_SW_INT_ENA_V  0x00000001U
-#define PMU_SW_INT_ENA_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_ENA    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_ENA_M  (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S)
-#define PMU_SOC_SLEEP_REJECT_INT_ENA_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_ENA_S  30
-/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_ENA    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_ENA_M  (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S)
-#define PMU_SOC_WAKEUP_INT_ENA_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_ENA_S  31
-
-/** PMU_HP_INT_CLR_REG register
- *  need_des
- */
-#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x168)
-/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_EXC_INT_CLR    (BIT(27))
-#define PMU_LP_CPU_EXC_INT_CLR_M  (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S)
-#define PMU_LP_CPU_EXC_INT_CLR_V  0x00000001U
-#define PMU_LP_CPU_EXC_INT_CLR_S  27
-/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SDIO_IDLE_INT_CLR    (BIT(28))
-#define PMU_SDIO_IDLE_INT_CLR_M  (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S)
-#define PMU_SDIO_IDLE_INT_CLR_V  0x00000001U
-#define PMU_SDIO_IDLE_INT_CLR_S  28
-/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_SW_INT_CLR    (BIT(29))
-#define PMU_SW_INT_CLR_M  (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S)
-#define PMU_SW_INT_CLR_V  0x00000001U
-#define PMU_SW_INT_CLR_S  29
-/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_SOC_SLEEP_REJECT_INT_CLR    (BIT(30))
-#define PMU_SOC_SLEEP_REJECT_INT_CLR_M  (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S)
-#define PMU_SOC_SLEEP_REJECT_INT_CLR_V  0x00000001U
-#define PMU_SOC_SLEEP_REJECT_INT_CLR_S  30
-/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_SOC_WAKEUP_INT_CLR    (BIT(31))
-#define PMU_SOC_WAKEUP_INT_CLR_M  (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S)
-#define PMU_SOC_WAKEUP_INT_CLR_V  0x00000001U
-#define PMU_SOC_WAKEUP_INT_CLR_S  31
-
-/** PMU_LP_INT_RAW_REG register
- *  need_des
- */
-#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x16c)
-/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_RAW    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_RAW_M  (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S)
-#define PMU_LP_CPU_WAKEUP_INT_RAW_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_RAW_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S  30
-/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_RAW    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_RAW_M  (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S)
-#define PMU_HP_SW_TRIGGER_INT_RAW_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_RAW_S  31
-
-/** PMU_LP_INT_ST_REG register
- *  need_des
- */
-#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x170)
-/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_ST    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_ST_M  (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S)
-#define PMU_LP_CPU_WAKEUP_INT_ST_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_ST_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S  30
-/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_ST    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_ST_M  (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S)
-#define PMU_HP_SW_TRIGGER_INT_ST_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_ST_S  31
-
-/** PMU_LP_INT_ENA_REG register
- *  need_des
- */
-#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x174)
-/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_ENA    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_ENA_M  (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S)
-#define PMU_LP_CPU_WAKEUP_INT_ENA_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_ENA_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S  30
-/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_ENA    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_ENA_M  (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S)
-#define PMU_HP_SW_TRIGGER_INT_ENA_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_ENA_S  31
-
-/** PMU_LP_INT_CLR_REG register
- *  need_des
- */
-#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x178)
-/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_INT_CLR    (BIT(20))
-#define PMU_LP_CPU_WAKEUP_INT_CLR_M  (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S)
-#define PMU_LP_CPU_WAKEUP_INT_CLR_V  0x00000001U
-#define PMU_LP_CPU_WAKEUP_INT_CLR_S  20
-/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR    (BIT(21))
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M  (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S)
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S  21
-/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR    (BIT(22))
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S  22
-/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR    (BIT(23))
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M  (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S  23
-/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR    (BIT(24))
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M  (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S)
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S  24
-/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR    (BIT(25))
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S  25
-/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR    (BIT(26))
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M  (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S)
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S  26
-/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR    (BIT(27))
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M  (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S  27
-/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR    (BIT(28))
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M  (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S)
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V  0x00000001U
-#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S  28
-/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR    (BIT(29))
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M  (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S)
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V  0x00000001U
-#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S  29
-/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR    (BIT(30))
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M  (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S)
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V  0x00000001U
-#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S  30
-/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_SW_TRIGGER_INT_CLR    (BIT(31))
-#define PMU_HP_SW_TRIGGER_INT_CLR_M  (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S)
-#define PMU_HP_SW_TRIGGER_INT_CLR_V  0x00000001U
-#define PMU_HP_SW_TRIGGER_INT_CLR_S  31
-
-/** PMU_LP_CPU_PWR0_REG register
- *  need_des
- */
-#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x17c)
-/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAITI_RDY    (BIT(0))
-#define PMU_LP_CPU_WAITI_RDY_M  (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S)
-#define PMU_LP_CPU_WAITI_RDY_V  0x00000001U
-#define PMU_LP_CPU_WAITI_RDY_S  0
-/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_STALL_RDY    (BIT(1))
-#define PMU_LP_CPU_STALL_RDY_M  (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S)
-#define PMU_LP_CPU_STALL_RDY_V  0x00000001U
-#define PMU_LP_CPU_STALL_RDY_S  1
-/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_FORCE_STALL    (BIT(18))
-#define PMU_LP_CPU_FORCE_STALL_M  (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S)
-#define PMU_LP_CPU_FORCE_STALL_V  0x00000001U
-#define PMU_LP_CPU_FORCE_STALL_S  18
-/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN    (BIT(19))
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M  (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S)
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S  19
-/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN    (BIT(20))
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M  (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S)
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S  20
-/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_STALL_WAIT    0x000000FFU
-#define PMU_LP_CPU_SLP_STALL_WAIT_M  (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S)
-#define PMU_LP_CPU_SLP_STALL_WAIT_V  0x000000FFU
-#define PMU_LP_CPU_SLP_STALL_WAIT_S  21
-/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_STALL_EN    (BIT(29))
-#define PMU_LP_CPU_SLP_STALL_EN_M  (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S)
-#define PMU_LP_CPU_SLP_STALL_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_STALL_EN_S  29
-/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_RESET_EN    (BIT(30))
-#define PMU_LP_CPU_SLP_RESET_EN_M  (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S)
-#define PMU_LP_CPU_SLP_RESET_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_RESET_EN_S  30
-/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN    (BIT(31))
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M  (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S)
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V  0x00000001U
-#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S  31
-
-/** PMU_LP_CPU_PWR1_REG register
- *  need_des
- */
-#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x180)
-/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_WAKEUP_EN    0x0000FFFFU
-#define PMU_LP_CPU_WAKEUP_EN_M  (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S)
-#define PMU_LP_CPU_WAKEUP_EN_V  0x0000FFFFU
-#define PMU_LP_CPU_WAKEUP_EN_S  0
-/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_LP_CPU_SLEEP_REQ    (BIT(31))
-#define PMU_LP_CPU_SLEEP_REQ_M  (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S)
-#define PMU_LP_CPU_SLEEP_REQ_V  0x00000001U
-#define PMU_LP_CPU_SLEEP_REQ_S  31
-
-/** PMU_HP_LP_CPU_COMM_REG register
- *  need_des
- */
-#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x184)
-/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_LP_TRIGGER_HP    (BIT(30))
-#define PMU_LP_TRIGGER_HP_M  (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S)
-#define PMU_LP_TRIGGER_HP_V  0x00000001U
-#define PMU_LP_TRIGGER_HP_S  30
-/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_HP_TRIGGER_LP    (BIT(31))
-#define PMU_HP_TRIGGER_LP_M  (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S)
-#define PMU_HP_TRIGGER_LP_V  0x00000001U
-#define PMU_HP_TRIGGER_LP_S  31
-
-/** PMU_HP_REGULATOR_CFG_REG register
- *  need_des
- */
-#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x188)
-/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_DIG_REGULATOR_EN_CAL    (BIT(31))
-#define PMU_DIG_REGULATOR_EN_CAL_M  (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S)
-#define PMU_DIG_REGULATOR_EN_CAL_V  0x00000001U
-#define PMU_DIG_REGULATOR_EN_CAL_S  31
-
-/** PMU_MAIN_STATE_REG register
- *  need_des
- */
-#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x18c)
-/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1;
- *  need_des
- */
-#define PMU_MAIN_LAST_ST_STATE    0x0000007FU
-#define PMU_MAIN_LAST_ST_STATE_M  (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S)
-#define PMU_MAIN_LAST_ST_STATE_V  0x0000007FU
-#define PMU_MAIN_LAST_ST_STATE_S  11
-/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4;
- *  need_des
- */
-#define PMU_MAIN_TAR_ST_STATE    0x0000007FU
-#define PMU_MAIN_TAR_ST_STATE_M  (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S)
-#define PMU_MAIN_TAR_ST_STATE_V  0x0000007FU
-#define PMU_MAIN_TAR_ST_STATE_S  18
-/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4;
- *  need_des
- */
-#define PMU_MAIN_CUR_ST_STATE    0x0000007FU
-#define PMU_MAIN_CUR_ST_STATE_M  (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S)
-#define PMU_MAIN_CUR_ST_STATE_V  0x0000007FU
-#define PMU_MAIN_CUR_ST_STATE_S  25
-
-/** PMU_PWR_STATE_REG register
- *  need_des
- */
-#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x190)
-/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1;
- *  need_des
- */
-#define PMU_BACKUP_ST_STATE    0x0000001FU
-#define PMU_BACKUP_ST_STATE_M  (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S)
-#define PMU_BACKUP_ST_STATE_V  0x0000001FU
-#define PMU_BACKUP_ST_STATE_S  13
-/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0;
- *  need_des
- */
-#define PMU_LP_PWR_ST_STATE    0x0000001FU
-#define PMU_LP_PWR_ST_STATE_M  (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S)
-#define PMU_LP_PWR_ST_STATE_V  0x0000001FU
-#define PMU_LP_PWR_ST_STATE_S  18
-/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1;
- *  need_des
- */
-#define PMU_HP_PWR_ST_STATE    0x000001FFU
-#define PMU_HP_PWR_ST_STATE_M  (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S)
-#define PMU_HP_PWR_ST_STATE_V  0x000001FFU
-#define PMU_HP_PWR_ST_STATE_S  23
-
-/** PMU_CLK_STATE0_REG register
- *  need_des
- */
-#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x194)
-/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1;
- *  need_des
- */
-#define PMU_STABLE_XPD_BBPLL_STATE    (BIT(0))
-#define PMU_STABLE_XPD_BBPLL_STATE_M  (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S)
-#define PMU_STABLE_XPD_BBPLL_STATE_V  0x00000001U
-#define PMU_STABLE_XPD_BBPLL_STATE_S  0
-/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1;
- *  need_des
- */
-#define PMU_STABLE_XPD_XTAL_STATE    (BIT(1))
-#define PMU_STABLE_XPD_XTAL_STATE_M  (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S)
-#define PMU_STABLE_XPD_XTAL_STATE_V  0x00000001U
-#define PMU_STABLE_XPD_XTAL_STATE_S  1
-/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0;
- *  need_des
- */
-#define PMU_SYS_CLK_SLP_SEL_STATE    (BIT(15))
-#define PMU_SYS_CLK_SLP_SEL_STATE_M  (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S)
-#define PMU_SYS_CLK_SLP_SEL_STATE_V  0x00000001U
-#define PMU_SYS_CLK_SLP_SEL_STATE_S  15
-/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0;
- *  need_des
- */
-#define PMU_SYS_CLK_SEL_STATE    0x00000003U
-#define PMU_SYS_CLK_SEL_STATE_M  (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S)
-#define PMU_SYS_CLK_SEL_STATE_V  0x00000003U
-#define PMU_SYS_CLK_SEL_STATE_S  16
-/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0;
- *  need_des
- */
-#define PMU_SYS_CLK_NO_DIV_STATE    (BIT(18))
-#define PMU_SYS_CLK_NO_DIV_STATE_M  (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S)
-#define PMU_SYS_CLK_NO_DIV_STATE_V  0x00000001U
-#define PMU_SYS_CLK_NO_DIV_STATE_S  18
-/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0;
- *  need_des
- */
-#define PMU_ICG_SYS_CLK_EN_STATE    (BIT(19))
-#define PMU_ICG_SYS_CLK_EN_STATE_M  (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S)
-#define PMU_ICG_SYS_CLK_EN_STATE_V  0x00000001U
-#define PMU_ICG_SYS_CLK_EN_STATE_S  19
-/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0;
- *  need_des
- */
-#define PMU_ICG_MODEM_SWITCH_STATE    (BIT(20))
-#define PMU_ICG_MODEM_SWITCH_STATE_M  (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S)
-#define PMU_ICG_MODEM_SWITCH_STATE_V  0x00000001U
-#define PMU_ICG_MODEM_SWITCH_STATE_S  20
-/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0;
- *  need_des
- */
-#define PMU_ICG_MODEM_CODE_STATE    0x00000003U
-#define PMU_ICG_MODEM_CODE_STATE_M  (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S)
-#define PMU_ICG_MODEM_CODE_STATE_V  0x00000003U
-#define PMU_ICG_MODEM_CODE_STATE_S  21
-/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0;
- *  need_des
- */
-#define PMU_ICG_SLP_SEL_STATE    (BIT(23))
-#define PMU_ICG_SLP_SEL_STATE_M  (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S)
-#define PMU_ICG_SLP_SEL_STATE_V  0x00000001U
-#define PMU_ICG_SLP_SEL_STATE_S  23
-/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0;
- *  need_des
- */
-#define PMU_ICG_GLOBAL_XTAL_STATE    (BIT(24))
-#define PMU_ICG_GLOBAL_XTAL_STATE_M  (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S)
-#define PMU_ICG_GLOBAL_XTAL_STATE_V  0x00000001U
-#define PMU_ICG_GLOBAL_XTAL_STATE_S  24
-/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0;
- *  need_des
- */
-#define PMU_ICG_GLOBAL_PLL_STATE    (BIT(25))
-#define PMU_ICG_GLOBAL_PLL_STATE_M  (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S)
-#define PMU_ICG_GLOBAL_PLL_STATE_V  0x00000001U
-#define PMU_ICG_GLOBAL_PLL_STATE_S  25
-/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0;
- *  need_des
- */
-#define PMU_ANA_I2C_ISO_EN_STATE    (BIT(26))
-#define PMU_ANA_I2C_ISO_EN_STATE_M  (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S)
-#define PMU_ANA_I2C_ISO_EN_STATE_V  0x00000001U
-#define PMU_ANA_I2C_ISO_EN_STATE_S  26
-/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0;
- *  need_des
- */
-#define PMU_ANA_I2C_RETENTION_STATE    (BIT(27))
-#define PMU_ANA_I2C_RETENTION_STATE_M  (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S)
-#define PMU_ANA_I2C_RETENTION_STATE_V  0x00000001U
-#define PMU_ANA_I2C_RETENTION_STATE_S  27
-/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0;
- *  need_des
- */
-#define PMU_ANA_XPD_BB_I2C_STATE    (BIT(28))
-#define PMU_ANA_XPD_BB_I2C_STATE_M  (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S)
-#define PMU_ANA_XPD_BB_I2C_STATE_V  0x00000001U
-#define PMU_ANA_XPD_BB_I2C_STATE_S  28
-/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0;
- *  need_des
- */
-#define PMU_ANA_XPD_BBPLL_I2C_STATE    (BIT(29))
-#define PMU_ANA_XPD_BBPLL_I2C_STATE_M  (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S)
-#define PMU_ANA_XPD_BBPLL_I2C_STATE_V  0x00000001U
-#define PMU_ANA_XPD_BBPLL_I2C_STATE_S  29
-/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0;
- *  need_des
- */
-#define PMU_ANA_XPD_BBPLL_STATE    (BIT(30))
-#define PMU_ANA_XPD_BBPLL_STATE_M  (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S)
-#define PMU_ANA_XPD_BBPLL_STATE_V  0x00000001U
-#define PMU_ANA_XPD_BBPLL_STATE_S  30
-/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_ANA_XPD_XTAL_STATE    (BIT(31))
-#define PMU_ANA_XPD_XTAL_STATE_M  (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S)
-#define PMU_ANA_XPD_XTAL_STATE_V  0x00000001U
-#define PMU_ANA_XPD_XTAL_STATE_S  31
-
-/** PMU_CLK_STATE1_REG register
- *  need_des
- */
-#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x198)
-/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_ICG_FUNC_EN_STATE    0xFFFFFFFFU
-#define PMU_ICG_FUNC_EN_STATE_M  (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S)
-#define PMU_ICG_FUNC_EN_STATE_V  0xFFFFFFFFU
-#define PMU_ICG_FUNC_EN_STATE_S  0
-
-/** PMU_CLK_STATE2_REG register
- *  need_des
- */
-#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x19c)
-/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define PMU_ICG_APB_EN_STATE    0xFFFFFFFFU
-#define PMU_ICG_APB_EN_STATE_M  (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S)
-#define PMU_ICG_APB_EN_STATE_V  0xFFFFFFFFU
-#define PMU_ICG_APB_EN_STATE_S  0
-
-/** PMU_VDD_SPI_STATUS_REG register
- *  need_des
- */
-#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a0)
-/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_STABLE_VDD_SPI_PWR_DRV    (BIT(31))
-#define PMU_STABLE_VDD_SPI_PWR_DRV_M  (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S)
-#define PMU_STABLE_VDD_SPI_PWR_DRV_V  0x00000001U
-#define PMU_STABLE_VDD_SPI_PWR_DRV_S  31
-
-/** PMU_DATE_REG register
- *  need_des
- */
-#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc)
-/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35664432;
- *  need_des
- */
-#define PMU_PMU_DATE    0x7FFFFFFFU
-#define PMU_PMU_DATE_M  (PMU_PMU_DATE_V << PMU_PMU_DATE_S)
-#define PMU_PMU_DATE_V  0x7FFFFFFFU
-#define PMU_PMU_DATE_S  0
-/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define PMU_CLK_EN    (BIT(31))
-#define PMU_CLK_EN_M  (PMU_CLK_EN_V << PMU_CLK_EN_S)
-#define PMU_CLK_EN_V  0x00000001U
-#define PMU_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/pmu_struct.h b/components/soc/esp32c5/beta3/include/soc/pmu_struct.h
deleted file mode 100644
index 2cd967c42c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/pmu_struct.h
+++ /dev/null
@@ -1,758 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc.h"
-#include "soc/pmu_reg.h"
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 21;
-        uint32_t vdd_spi_pd_en: 1;
-        uint32_t mem_dslp     : 1;
-        uint32_t mem_pd_en    : 4;
-        uint32_t wifi_pd_en   : 1;
-        uint32_t reserved1    : 1;
-        uint32_t cpu_pd_en    : 1;
-        uint32_t aon_pd_en    : 1;
-        uint32_t top_pd_en    : 1;
-    };
-    uint32_t val;
-} pmu_hp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 30;
-        uint32_t code     : 2;
-    };
-    uint32_t val;
-} pmu_hp_icg_modem_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 24;
-        uint32_t uart_wakeup_en : 1;
-        uint32_t lp_pad_hold_all: 1;
-        uint32_t hp_pad_hold_all: 1;
-        uint32_t dig_pad_slp_sel: 1;
-        uint32_t dig_pause_wdt  : 1;
-        uint32_t dig_cpu_stall  : 1;
-        uint32_t reserved1      : 2;
-    };
-    uint32_t val;
-} pmu_hp_sys_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 26;
-        uint32_t i2c_iso_en   : 1;
-        uint32_t i2c_retention: 1;
-        uint32_t xpd_bb_i2c   : 1;
-        uint32_t xpd_bbpll_i2c: 1;
-        uint32_t xpd_bbpll    : 1;
-        uint32_t reserved1    : 1;
-    };
-    uint32_t val;
-} pmu_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_hp_bias_reg_t;
-
-typedef union {
-    struct {    /* HP: Active State */
-        uint32_t reserved0                            : 4;
-        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
-        uint32_t hp_modem2active_backup_modem_clk_code: 2;
-        uint32_t reserved1                            : 2;
-        uint32_t hp_active_retention_mode             : 1;
-        uint32_t hp_sleep2active_retention_en         : 1;
-        uint32_t hp_modem2active_retention_en         : 1;
-        uint32_t reserved2                            : 1;
-        uint32_t hp_sleep2active_backup_clk_sel       : 2;
-        uint32_t hp_modem2active_backup_clk_sel       : 2;
-        uint32_t reserved3                            : 2;
-        uint32_t hp_sleep2active_backup_mode          : 3;
-        uint32_t hp_modem2active_backup_mode          : 3;
-        uint32_t reserved4                            : 3;
-        uint32_t hp_sleep2active_backup_en            : 1;
-        uint32_t hp_modem2active_backup_en            : 1;
-        uint32_t reserved5                            : 1;
-    };
-    struct {    /* HP: Modem State */
-        uint32_t reserved6                            : 4;
-        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
-        uint32_t reserved7                            : 4;
-        uint32_t hp_modem_retention_mode              : 1;
-        uint32_t hp_sleep2modem_retention_en          : 1;
-        uint32_t reserved8                            : 2;
-        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
-        uint32_t reserved9                            : 4;
-        uint32_t hp_sleep2modem_backup_mode           : 3;
-        uint32_t reserved10                           : 6;
-        uint32_t hp_sleep2modem_backup_en             : 1;
-        uint32_t reserved11                           : 2;
-    };
-    struct {    /* HP: Sleep State */
-        uint32_t reserved12                           : 6;
-        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
-        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
-        uint32_t hp_sleep_retention_mode              : 1;
-        uint32_t reserved13                           : 1;
-        uint32_t hp_modem2sleep_retention_en          : 1;
-        uint32_t hp_active2sleep_retention_en         : 1;
-        uint32_t reserved14                           : 2;
-        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
-        uint32_t hp_active2sleep_backup_clk_sel       : 2;
-        uint32_t reserved15                           : 3;
-        uint32_t hp_modem2sleep_backup_mode           : 3;
-        uint32_t hp_active2sleep_backup_mode          : 3;
-        uint32_t reserved16                           : 1;
-        uint32_t hp_modem2sleep_backup_en             : 1;
-        uint32_t hp_active2sleep_backup_en            : 1;
-    };
-    uint32_t val;
-} pmu_hp_backup_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 26;
-        uint32_t dig_sysclk_nodiv: 1;
-        uint32_t icg_sysclk_en   : 1;
-        uint32_t sysclk_slp_sel  : 1;
-        uint32_t icg_slp_sel     : 1;
-        uint32_t dig_sysclk_sel  : 2;
-    };
-    uint32_t val;
-} pmu_hp_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t slp_mem_xpd    : 1;
-        uint32_t slp_logic_xpd  : 1;
-        uint32_t xpd            : 1;
-        uint32_t slp_mem_dbias  : 4;
-        uint32_t slp_logic_dbias: 4;
-        uint32_t dbias          : 5;
-    };
-    uint32_t val;
-} pmu_hp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 8;
-        uint32_t drv_b    : 24;
-    };
-    uint32_t val;
-} pmu_hp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_hp_xtal_reg_t;
-
-typedef struct pmu_hp_hw_regmap_t{
-    pmu_hp_dig_power_reg_t     dig_power;
-    uint32_t                   icg_func;
-    uint32_t                   icg_apb;
-    pmu_hp_icg_modem_reg_t     icg_modem;
-    pmu_hp_sys_cntl_reg_t      syscntl;
-    pmu_hp_clk_power_reg_t     clk_power;
-    pmu_hp_bias_reg_t          bias;
-    pmu_hp_backup_reg_t        backup;
-    uint32_t                   backup_clk;
-    pmu_hp_sysclk_reg_t        sysclk;
-    pmu_hp_regulator0_reg_t    regulator0;
-    pmu_hp_regulator1_reg_t    regulator1;
-    pmu_hp_xtal_reg_t          xtal;
-} pmu_hp_hw_regmap_t;
-
-/** */
-typedef union {
-    struct {
-        uint32_t reserved0: 21;
-        uint32_t slp_xpd  : 1;
-        uint32_t xpd	  : 1;
-        uint32_t slp_dbias: 4;
-        uint32_t dbias    : 5;
-    };
-    uint32_t val;
-} pmu_lp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 28;
-        uint32_t drv_b    : 4;
-    };
-    uint32_t val;
-} pmu_lp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_lp_xtal_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 30;
-        uint32_t mem_dslp  : 1;
-        uint32_t peri_pd_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0  : 28;
-        uint32_t xpd_xtal32k: 1;
-        uint32_t xpd_rc32k  : 1;
-        uint32_t xpd_fosc   : 1;
-        uint32_t pd_osc     : 1;
-    };
-    uint32_t val;
-} pmu_lp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_lp_bias_reg_t;
-
-typedef struct pmu_lp_hw_regmap_t{
-    pmu_lp_regulator0_reg_t    regulator0;
-    pmu_lp_regulator1_reg_t    regulator1;
-    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
-    pmu_lp_dig_power_reg_t     dig_power;
-    pmu_lp_clk_power_reg_t     clk_power;
-    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
-} pmu_lp_hw_regmap_t;
-
-
-typedef union {
-    struct {
-        uint32_t tie_low_global_bbpll_icg : 1;
-        uint32_t tie_low_global_xtal_icg  : 1;
-        uint32_t tie_low_i2c_retention    : 1;
-        uint32_t tie_low_xpd_bb_i2c       : 1;
-        uint32_t tie_low_xpd_bbpll_i2c    : 1;
-        uint32_t tie_low_xpd_bbpll        : 1;
-        uint32_t tie_low_xpd_xtal         : 1;
-        uint32_t reserved0                : 18;
-        uint32_t tie_high_global_bbpll_icg: 1;
-        uint32_t tie_high_global_xtal_icg : 1;
-        uint32_t tie_high_i2c_retention   : 1;
-        uint32_t tie_high_xpd_bb_i2c      : 1;
-        uint32_t tie_high_xpd_bbpll_i2c   : 1;
-        uint32_t tie_high_xpd_bbpll       : 1;
-        uint32_t tie_high_xpd_xtal        : 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 28;
-        uint32_t update_dig_icg_switch: 1;
-        uint32_t tie_low_icg_slp_sel  : 1;
-        uint32_t tie_high_icg_slp_sel : 1;
-        uint32_t update_dig_sysclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_sleep_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0             : 31;
-        uint32_t update_dig_icg_func_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_func_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 31;
-        uint32_t update_dig_icg_apb_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_apb_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 31;
-        uint32_t update_dig_icg_modem_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_modem_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 30;
-        uint32_t tie_low_lp_rootclk_sel : 1;
-        uint32_t tie_high_lp_rootclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_lp_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0               : 28;
-        uint32_t tie_high_lp_pad_hold_all: 1;
-        uint32_t tie_low_lp_pad_hold_all : 1;
-        uint32_t tie_high_hp_pad_hold_all: 1;
-        uint32_t tie_low_hp_pad_hold_all : 1;
-    };
-    uint32_t val;
-} pmu_imm_pad_hold_all_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 30;
-        uint32_t tie_high_i2c_iso_en: 1;
-        uint32_t tie_low_i2c_iso_en : 1;
-    };
-    uint32_t val;
-} pmu_imm_i2c_isolate_reg_t;
-
-typedef struct pmu_imm_hw_regmap_t{
-    pmu_imm_hp_clk_power_reg_t     clk_power;
-    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
-    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
-    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
-    pmu_imm_modem_icg_reg_t        modem_icg;
-    pmu_imm_lp_icg_reg_t           lp_icg;
-    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
-    pmu_imm_i2c_isolate_reg_t      i2c_iso;
-} pmu_imm_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 5;
-        uint32_t powerdown_timer: 9;
-        uint32_t powerup_timer  : 9;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 9;
-        uint32_t powerdown_timer: 7;
-        uint32_t powerup_timer  : 7;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_reset   : 1;
-        uint32_t force_iso     : 1;
-        uint32_t force_pu      : 1;
-        uint32_t force_no_reset: 1;
-        uint32_t force_no_iso  : 1;
-        uint32_t force_pd      : 1;
-        uint32_t mask          : 5;     /* Invalid of lp peripherals */
-        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
-        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
-    };
-    uint32_t val;
-} pmu_power_domain_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_mem_iso   : 4;
-        uint32_t force_hp_mem_pd    : 4;
-        uint32_t reserved0          : 16;
-        uint32_t force_hp_mem_no_iso: 4;
-        uint32_t force_hp_mem_pu    : 4;
-    };
-    uint32_t val;
-} pmu_power_memory_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t mem2_pd_mask: 5;
-        uint32_t mem1_pd_mask: 5;
-        uint32_t mem0_pd_mask: 5;
-        uint32_t reserved0   : 2;
-        uint32_t mem2_mask   : 5;
-        uint32_t mem1_mask   : 5;
-        uint32_t mem0_mask   : 5;
-    };
-    uint32_t val;
-} pmu_power_memory_mask_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_pad_no_iso_all: 1;
-        uint32_t force_hp_pad_iso_all   : 1;
-        uint32_t reserved0              : 30;
-    };
-    uint32_t val;
-} pmu_power_hp_pad_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 18;
-        uint32_t pwr_wait  : 11;
-        uint32_t pwr_sw    : 2;
-        uint32_t pwr_sel_sw: 1;
-    };
-    uint32_t val;
-} pmu_power_vdd_spi_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wait_xtal_stable: 16;
-        uint32_t wait_pll_stable : 16;
-    };
-    uint32_t val;
-} pmu_power_clk_wait_cntl_reg_t;
-
-typedef struct pmu_power_hw_regmap_t{
-    pmu_power_wait_timer0_reg_t    wait_timer0;
-    pmu_power_wait_timer1_reg_t    wait_timer1;
-    pmu_power_domain_cntl_reg_t    hp_pd[5];
-    pmu_power_domain_cntl_reg_t    lp_peri;
-    pmu_power_memory_cntl_reg_t    mem_cntl;
-    pmu_power_memory_mask_reg_t    mem_mask;
-    pmu_power_hp_pad_reg_t         hp_pad;
-    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
-    pmu_power_clk_wait_cntl_reg_t  clk_wait;
-} pmu_power_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject_ena: 31;
-        uint32_t slp_reject_en   : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_min_slp_val: 8;
-        uint32_t hp_min_slp_val: 8;
-        uint32_t sleep_prt_sel : 2;
-        uint32_t reserved0     : 14;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl3_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0           : 31;
-        uint32_t slp_reject_cause_clr: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl4_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modem_wait_target : 20;
-        uint32_t reserved0         : 4;
-        uint32_t lp_ana_wait_target: 8;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl5_reg_t;
-
-typedef union {
-    struct {
-        uint32_t soc_wakeup_wait    : 20;
-        uint32_t reserved0          : 10;
-        uint32_t soc_wakeup_wait_cfg: 2;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl6_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 16;
-        uint32_t ana_wait_target: 16;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl7_reg_t;
-
-typedef struct pmu_wakeup_hw_regmap_t{
-    pmu_slp_wakeup_cntl0_reg_t     cntl0;
-    pmu_slp_wakeup_cntl1_reg_t     cntl1;
-    uint32_t                       cntl2;
-    pmu_slp_wakeup_cntl3_reg_t     cntl3;
-    pmu_slp_wakeup_cntl4_reg_t     cntl4;
-    pmu_slp_wakeup_cntl5_reg_t     cntl5;
-    pmu_slp_wakeup_cntl6_reg_t     cntl6;
-    pmu_slp_wakeup_cntl7_reg_t     cntl7;
-    uint32_t                       status0;
-    uint32_t                       status1;
-} pmu_wakeup_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t i2c_por_wait_target: 8;
-        uint32_t reserved0          : 24;
-    };
-    uint32_t val;
-} pmu_hp_clk_poweron_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modify_icg_cntl_wait: 8;
-        uint32_t switch_icg_cntl_wait: 8;
-        uint32_t reserved0           : 16;
-    };
-    uint32_t val;
-} pmu_hp_clk_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t por_done : 1;
-    };
-    uint32_t val;
-} pmu_por_status_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0     : 24;
-        uint32_t xpd_tc5g_i2c  : 1;
-        uint32_t xpd_rx5g_i2c  : 1;
-        uint32_t perif_i2c_rstb: 1;
-        uint32_t xpd_perif_i2c : 1;
-        uint32_t xpd_txrf_i2c  : 1;
-        uint32_t xpd_rfrx_pbus : 1;
-        uint32_t xpd_ckgen_i2c : 1;
-        uint32_t xpd_pll_i2c   : 1;
-    };
-    uint32_t val;
-} pmu_rf_pwc_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 31;
-        uint32_t backup_sysclk_nodiv: 1;
-    };
-    uint32_t val;
-} pmu_backup_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 27;
-        uint32_t lp_cpu_exc: 1;
-        uint32_t sdio_idle : 1;
-        uint32_t sw        : 1;
-        uint32_t reject    : 1;
-        uint32_t wakeup    : 1;
-    };
-    uint32_t val;
-} pmu_hp_intr_reg_t;
-
-typedef struct pmu_hp_ext_hw_regmap_t{
-    pmu_hp_clk_poweron_reg_t   clk_poweron;
-    pmu_hp_clk_cntl_reg_t      clk_cntl;
-    pmu_por_status_reg_t       por_status;
-    pmu_rf_pwc_reg_t           rf_pwc;
-    pmu_backup_cfg_reg_t       backup_cfg;
-    pmu_hp_intr_reg_t          int_raw;
-    pmu_hp_intr_reg_t          int_st;
-    pmu_hp_intr_reg_t          int_ena;
-    pmu_hp_intr_reg_t          int_clr;
-} pmu_hp_ext_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0                : 20;
-        uint32_t lp_cpu_wakeup            : 1;
-        uint32_t modem_switch_active_end  : 1;
-        uint32_t sleep_switch_active_end  : 1;
-        uint32_t sleep_switch_modem_end   : 1;
-        uint32_t modem_switch_sleep_end   : 1;
-        uint32_t active_swtich_sleep_end  : 1;
-        uint32_t modem_switch_active_start: 1;
-        uint32_t sleep_switch_active_start: 1;
-        uint32_t sleep_switch_modem_start : 1;
-        uint32_t modem_switch_sleep_start : 1;
-        uint32_t active_switch_sleep_start: 1;
-        uint32_t sw_trigger               : 1;
-    };
-    uint32_t val;
-} pmu_lp_intr_reg_t;
-
-typedef union {
-    struct {
-        uint32_t waiti_rdy         : 1;
-        uint32_t stall_rdy         : 1;
-        uint32_t reserved0         : 16;
-        uint32_t force_stall       : 1;
-        uint32_t slp_waiti_flag_en : 1;
-        uint32_t slp_stall_flag_en : 1;
-        uint32_t slp_stall_wait    : 8;
-        uint32_t slp_stall_en      : 1;
-        uint32_t slp_reset_en      : 1;
-        uint32_t slp_bypass_intr_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_en: 16;
-        uint32_t reserved0: 15;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr1_reg_t;
-
-typedef struct pmu_lp_ext_hw_regmap_t{
-    pmu_lp_intr_reg_t          int_raw;
-    pmu_lp_intr_reg_t          int_st;
-    pmu_lp_intr_reg_t          int_ena;
-    pmu_lp_intr_reg_t          int_clr;
-    pmu_lp_cpu_pwr0_reg_t      pwr0;
-    pmu_lp_cpu_pwr1_reg_t      pwr1;
-} pmu_lp_ext_hw_regmap_t;
-
-typedef struct pmu_dev_t{
-    volatile pmu_hp_hw_regmap_t     hp_sys[3];
-    volatile pmu_lp_hw_regmap_t     lp_sys[2];
-    volatile pmu_imm_hw_regmap_t    imm;
-    volatile pmu_power_hw_regmap_t  power;
-    volatile pmu_wakeup_hw_regmap_t wakeup;
-    volatile pmu_hp_ext_hw_regmap_t hp_ext;
-    volatile pmu_lp_ext_hw_regmap_t lp_ext;
-
-    union {
-        struct {
-            uint32_t reserved0    : 30;
-            volatile uint32_t lp_trigger_hp: 1;
-            volatile uint32_t hp_trigger_lp: 1;
-        };
-        volatile uint32_t val;
-    } hp_lp_cpu_comm;
-
-    union {
-        struct {
-            uint32_t reserved0           : 31;
-            volatile uint32_t dig_regulator_en_cal: 1;
-        };
-        volatile uint32_t val;
-    } hp_regulator_cfg;
-
-    union {
-        struct {
-            uint32_t reserved0 : 11;
-            volatile uint32_t last_st   : 7;
-            volatile uint32_t target_st : 7;
-            volatile uint32_t current_st: 7;
-        };
-        volatile uint32_t val;
-    } main_state;
-
-    union {
-        struct {
-            uint32_t reserved0: 13;
-            volatile uint32_t backup_st: 5;
-            volatile uint32_t lp_pwr_st: 5;
-            volatile uint32_t hp_pwr_st: 9;
-        };
-        volatile uint32_t val;
-    } pwr_state;
-
-    union {
-        struct {
-            volatile uint32_t stable_xpd_bbpll : 1;
-            volatile uint32_t stable_xpd_xtal  : 1;
-            volatile uint32_t reserved0        : 13;
-            volatile uint32_t sysclk_slp_sel   : 1;
-            volatile uint32_t sysclk_sel       : 2;
-            volatile uint32_t sysclk_nodiv     : 1;
-            volatile uint32_t icg_sysclk_en    : 1;
-            volatile uint32_t icg_modem_switch : 1;
-            volatile uint32_t icg_modem_code   : 2;
-            volatile uint32_t icg_slp_sel      : 1;
-            volatile uint32_t icg_global_xtal  : 1;
-            volatile uint32_t icg_global_pll   : 1;
-            volatile uint32_t ana_i2c_iso_en   : 1;
-            volatile uint32_t ana_i2c_retention: 1;
-            volatile uint32_t ana_xpd_bb_i2c   : 1;
-            volatile uint32_t ana_xpd_bbpll_i2c: 1;
-            volatile uint32_t ana_xpd_bbpll    : 1;
-            volatile uint32_t ana_xpd_xtal     : 1;
-        };
-        volatile uint32_t val;
-    } clk_state0;
-
-    volatile uint32_t clk_state1;
-    volatile uint32_t clk_state2;
-
-    union {
-        struct {
-            uint32_t reserved0             : 31;
-            volatile uint32_t stable_vdd_spi_pwr_drv: 1;
-        };
-        volatile uint32_t val;
-    } vdd_spi_status;
-
-    uint32_t reserved[150];
-
-    union {
-        struct {
-            volatile uint32_t pmu_date: 31;
-            volatile uint32_t clk_en  : 1;
-        };
-        volatile uint32_t val;
-    } date;
-} pmu_dev_t;
-
-extern pmu_dev_t PMU;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
-
-_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/reg_base.h b/components/soc/esp32c5/beta3/include/soc/reg_base.h
deleted file mode 100644
index c530cdf6bc..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/reg_base.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Peripheral 0 Modules
- *
- */
-#define DR_REG_UART0_BASE                         0x60000000
-#define DR_REG_UART1_BASE                         0x60001000
-#define DR_REG_SPIMEM0_BASE                       0x60002000
-#define DR_REG_SPIMEM1_BASE                       0x60003000
-#define DR_REG_I2C0_BASE                          0x60004000
-#define DR_REG_UHCI_BASE                          0x60005000
-#define DR_REG_RMT_BASE                           0x60006000
-#define DR_REG_LEDC_BASE                          0x60007000
-#define DR_REG_TIMERG0_BASE                       0x60008000
-#define DR_REG_TIMERG1_BASE                       0x60009000
-#define DR_REG_SYSTIMER_BASE                      0x6000A000
-#define DR_REG_TWAI0_BASE                         0x6000B000
-#define DR_REG_I2S_BASE                           0x6000C000
-#define DR_REG_TWAI1_BASE                         0x6000D000
-#define DR_REG_APB_SARADC_BASE                    0x6000E000
-#define DR_REG_USB_SERIAL_JTAG_BASE               0x6000F000
-#define DR_REG_INTERRUPT_MATRIX_BASE              0x60010000
-#define DR_REG_INTERRUPT_CORE0_BASE               DR_REG_INTERRUPT_MATRIX_BASE
-#define DR_REG_I2C1_BASE                          0x60011000
-#define DR_REG_PCNT_BASE                          0x60012000
-#define DR_REG_SOC_ETM_BASE                       0x60013000
-#define DR_REG_MCPWM_BASE                         0x60014000
-#define DR_REG_PARL_IO_BASE                       0x60015000
-#define DR_REG_PVT_MONITOR_BASE                   0x60019000
-
-/**
- * @brief Peripheral 1 Modules
- *
- */
-#define DR_REG_GDMA_BASE                          0x60080000
-#define DR_REG_GPSPI2_BASE                        0x60081000
-#define DR_REG_BITSCRAMBLER_BASE                  0x60082000
-#define DR_REG_KEYMNG_BASE                        0x60087000
-#define DR_REG_AES_BASE                           0x60088000
-#define DR_REG_SHA_BASE                           0x60089000
-#define DR_REG_RSA_BASE                           0x6008A000
-#define DR_REG_ECC_MULT_BASE                      0x6008B000
-#define DR_REG_DS_BASE                            0x6008C000
-#define DR_REG_HMAC_BASE                          0x6008D000
-#define DR_REG_ECDSA_BASE                         0x6008E000
-
-/**
- * @brief HP Top Peripheral Modules
- *
- */
-#define DR_REG_IO_MUX_BASE                        0x60090000
-#define DR_REG_GPIO_BASE                          0x60091000
-#define DR_REG_MEM_MONITOR_BASE                   0x60092000
-#define DR_REG_PAU_BASE                           0x60093000
-#define DR_REG_HP_SYS_BASE                        0x60095000
-#define DR_REG_PCR_BASE                           0x60096000
-#define DR_REG_TEE_BASE                           0x60098000
-#define DR_REG_HP_APM_BASE                        0x60099000
-#define DR_REG_LP_APM0_BASE                       0x60099800
-#define DR_REG_MISC_BASE                          0x6009F000
-
-/**
- * @brief Modem Module
- *
- */
-#define DR_REG_MODEM_BASE                         0x600A4000
-#define DR_REG_MODEM_PWR_BASE                     0x600AD000
-#define DR_REG_I2C_ANA_MST_BASE                   0x600AF800
-
-#define PWDET_CONF_REG                            0x600A0810
-/**
- * @brief LP System (RTC) Modules
- *
- */
-#define DR_REG_PMU_BASE                           0x600B0000
-#define DR_REG_LP_CLKRST_BASE                     0x600B0400
-#define DR_REG_EFUSE_BASE                         0x600B0800
-#define DR_REG_LP_TIMER_BASE                      0x600B0C00
-#define DR_REG_LP_AON_BASE                        0x600B1000
-#define DR_REG_LP_UART_BASE                       0x600B1400
-#define DR_REG_LP_I2C_BASE                        0x600B1800
-#define DR_REG_LP_WDT_BASE                        0x600B1C00
-#define DR_REG_LP_IO_BASE                         0x600B2000
-#define DR_REG_LP_I2C_ANA_MST_BASE                0x600B2400
-#define DR_REG_LPPERI_BASE                        0x600B2800
-#define DR_REG_LP_ANA_BASE                        0x600B2C00
-#define DR_REG_HUK_BASE                           0x600B3000
-#define DR_REG_LP_TEE_BASE                        0x600B3400
-#define DR_REG_LP_APM_BASE                        0x600B3800
-#define DR_REG_OTP_DEBUG_BASE                     0x600B3C00
-
-/**
- * @brief CPU Peripheral Modules
- *
- */
-#define DR_REG_TRACE_BASE                         0x600C0000
-#define DR_REG_ASSIST_DEBUG_BASE                  0x600C2000
-#define DR_REG_INTPRI_BASE                        0x600C5000
-#define DR_REG_CACHE_BASE                         0x600C8000  // CACHE_CONFIG/EXTMEM
-#define DR_REG_CLINT_M_BASE                       0x20000000
diff --git a/components/soc/esp32c5/beta3/include/soc/regi2c_bbpll.h b/components/soc/esp32c5/beta3/include/soc/regi2c_bbpll.h
deleted file mode 100644
index 0a5b39a36c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/regi2c_bbpll.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @file regi2c_bbpll.h
- * @brief Register definitions for digital PLL (BBPLL)
- *
- * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
- * rtc_clk_cpu_freq_set function in rtc_clk.c.
- */
-
-#define I2C_BBPLL           0x66
-#define I2C_BBPLL_HOSTID    0
-
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    5
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    5
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    6
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    6
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    7
-#define I2C_BBPLL_IR_CAL_START_LSB    7
-
-
-
-#define I2C_BBPLL_OC_REF_DIV        2
-#define I2C_BBPLL_OC_REF_DIV_MSB    3
-#define I2C_BBPLL_OC_REF_DIV_LSB    0
-
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        2
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
-#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
-#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
-
-#define I2C_BBPLL_OC_DLREF_SEL        6
-#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
-#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    3
-#define I2C_BBPLL_OR_LOCK_LSB    3
-
-#define I2C_BBPLL_OC_VCO_DBIAS        9
-#define I2C_BBPLL_OC_VCO_DBIAS_MSB    2
-#define I2C_BBPLL_OC_VCO_DBIAS_LSB    0
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
diff --git a/components/soc/esp32c5/beta3/include/soc/regi2c_defs.h b/components/soc/esp32c5/beta3/include/soc/regi2c_defs.h
deleted file mode 100644
index 295fda22cf..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/regi2c_defs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "esp_bit_defs.h"
-
-// TODO: [ESP32C5] IDF-8824
-/* Analog function control register */
-#define I2C_MST_ANA_CONF0_REG          0x600AF818
-#define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
-#define I2C_MST_BBPLL_STOP_FORCE_LOW   (BIT(3))
-#define I2C_MST_BBPLL_CAL_DONE         (BIT(24))
-
-
-#define ANA_CONFIG_REG  0x600AF81C
-#define ANA_CONFIG_S    (8)
-#define ANA_CONFIG_M    (0x3FF)
-
-#define ANA_I2C_SAR_FORCE_PD BIT(18)
-#define ANA_I2C_BBPLL_M      BIT(17) /* Clear to enable BBPLL */
-
-
-#define ANA_CONFIG2_REG  0x600AF820
-#define ANA_CONFIG2_M    BIT(18)
-
-#define ANA_I2C_SAR_FORCE_PU BIT(16)
diff --git a/components/soc/esp32c5/beta3/include/soc/regi2c_dig_reg.h b/components/soc/esp32c5/beta3/include/soc/regi2c_dig_reg.h
deleted file mode 100644
index 8b277dfcd6..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/regi2c_dig_reg.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @file regi2c_dig_reg.h
- * @brief Register definitions for digital to get rtc voltage & digital voltage
- *        by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
- */
-
-#define I2C_DIG_REG 0x6D
-#define I2C_DIG_REG_HOSTID 0
-
-#define I2C_DIG_REG_EXT_RTC_DREG    4
-#define I2C_DIG_REG_EXT_RTC_DREG_MSB    4
-#define I2C_DIG_REG_EXT_RTC_DREG_LSB    0
-
-#define I2C_DIG_REG_ENX_RTC_DREG    4
-#define I2C_DIG_REG_ENX_RTC_DREG_MSB    7
-#define I2C_DIG_REG_ENX_RTC_DREG_LSB    7
-
-#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP    5
-#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB    4
-#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB    0
-
-#define I2C_DIG_REG_ENIF_RTC_DREG    5
-#define I2C_DIG_REG_ENIF_RTC_DREG_MSB    7
-#define I2C_DIG_REG_ENIF_RTC_DREG_LSB    7
-
-#define I2C_DIG_REG_EXT_DIG_DREG    6
-#define I2C_DIG_REG_EXT_DIG_DREG_MSB    4
-#define I2C_DIG_REG_EXT_DIG_DREG_LSB    0
-
-#define I2C_DIG_REG_ENX_DIG_DREG    6
-#define I2C_DIG_REG_ENX_DIG_DREG_MSB    7
-#define I2C_DIG_REG_ENX_DIG_DREG_LSB    7
-
-#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP    7
-#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB    4
-#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB    0
-
-#define I2C_DIG_REG_ENIF_DIG_DREG    7
-#define I2C_DIG_REG_ENIF_DIG_DREG_MSB    7
-#define I2C_DIG_REG_ENIF_DIG_DREG_LSB    7
-
-#define I2C_DIG_REG_OR_EN_CONT_CAL 9
-#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
-#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
-
-#define I2C_DIG_REG_XPD_RTC_REG 13
-#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
-#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
-
-#define I2C_DIG_REG_XPD_DIG_REG 13
-#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
-#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
-
-#define I2C_DIG_REG_SCK_DCAP	14
-#define I2C_DIG_REG_SCK_DCAP_MSB	7
-#define I2C_DIG_REG_SCK_DCAP_LSB	0
diff --git a/components/soc/esp32c5/beta3/include/soc/reset_reasons.h b/components/soc/esp32c5/beta3/include/soc/reset_reasons.h
deleted file mode 100644
index e061e4bfb4..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/reset_reasons.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-//+-----------------------------------------------Terminology---------------------------------------------+
-//|                                                                                                       |
-//| CPU Reset:    Reset CPU core only, once reset done, CPU will execute from reset vector                |
-//|                                                                                                       |
-//| Core Reset:   Reset the whole digital system except RTC sub-system                                    |
-//|                                                                                                       |
-//| System Reset: Reset the whole digital system, including RTC sub-system                                |
-//|                                                                                                       |
-//| Chip Reset:   Reset the whole chip, including the analog part                                         |
-//|                                                                                                       |
-//+-------------------------------------------------------------------------------------------------------+
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**
- * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
- * @note refer to TRM: <Reset and Clock> chapter
- */
-typedef enum {
-    RESET_REASON_CHIP_POWER_ON   = 0x01, // Power on reset
-    RESET_REASON_CHIP_BROWN_OUT  = 0x01, // VDD voltage is not stable and resets the chip
-    RESET_REASON_CORE_SW         = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
-    RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system)
-    RESET_REASON_CORE_MWDT0      = 0x07, // Main watch dog 0 resets digital core (hp system)
-    RESET_REASON_CORE_MWDT1      = 0x08, // Main watch dog 1 resets digital core (hp system)
-    RESET_REASON_CORE_RTC_WDT    = 0x09, // RTC watch dog resets digital core (hp system)
-    RESET_REASON_CPU0_MWDT0      = 0x0B, // Main watch dog 0 resets CPU 0
-    RESET_REASON_CPU0_SW         = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET
-    RESET_REASON_CPU0_RTC_WDT    = 0x0D, // RTC watch dog resets CPU 0
-    RESET_REASON_SYS_BROWN_OUT   = 0x0F, // VDD voltage is not stable and resets the digital core
-    RESET_REASON_SYS_RTC_WDT     = 0x10, // RTC watch dog resets digital core and rtc module
-    RESET_REASON_CPU0_MWDT1      = 0x11, // Main watch dog 1 resets CPU 0
-    RESET_REASON_SYS_SUPER_WDT   = 0x12, // Super watch dog resets the digital core and rtc module
-    RESET_REASON_CORE_EFUSE_CRC  = 0x14, // eFuse CRC error resets the digital core (hp system)
-    RESET_REASON_CORE_USB_UART   = 0x15, // USB UART resets the digital core (hp system)
-    RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core (hp system)
-    RESET_REASON_CPU0_JTAG       = 0x18, // JTAG resets the CPU 0
-    RESET_REASON_CORE_PWR_GLITCH = 0x19, // Glitch on power resets the digital core and rtc module
-    RESET_REASON_CPU0_LOCKUP     = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this)
-} soc_reset_reason_t;
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/retention_periph_defs.h b/components/soc/esp32c5/beta3/include/soc/retention_periph_defs.h
deleted file mode 100644
index 47b3396017..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/retention_periph_defs.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include "esp_bit_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum periph_retention_module {
-    SLEEP_RETENTION_MODULE_MIN          = 0,
-    /* clock module, which includes system and modem */
-    SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
-    SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
-    /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
-    SLEEP_RETENTION_MODULE_SYS_PERIPH   = 3,
-    /* Timer Group by target*/
-    SLEEP_RETENTION_MODULE_TG0_WDT     = 4,
-    SLEEP_RETENTION_MODULE_TG1_WDT      = 5,
-    SLEEP_RETENTION_MODULE_TG0_TIMER    = 6,
-    SLEEP_RETENTION_MODULE_TG1_TIMER    = 7,
-    /* GDMA by channel */
-    SLEEP_RETENTION_MODULE_GDMA_CH0     = 8,
-    SLEEP_RETENTION_MODULE_GDMA_CH1     = 9,
-    SLEEP_RETENTION_MODULE_GDMA_CH2     = 10,
-    /* MISC Peripherals */
-    SLEEP_RETENTION_MODULE_ADC          = 11,
-    SLEEP_RETENTION_MODULE_I2C0         = 12,
-    SLEEP_RETENTION_MODULE_RMT0         = 13,
-
-    /* Modem module, which includes WiFi, BLE and 802.15.4 */
-    SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
-    SLEEP_RETENTION_MODULE_WIFI_BB      = 27,
-    SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
-    SLEEP_RETENTION_MODULE_BT_BB        = 29,
-    SLEEP_RETENTION_MODULE_802154_MAC   = 30,
-    SLEEP_RETENTION_MODULE_MAX          = 31
-} periph_retention_module_t;
-
-typedef enum periph_retention_module_bitmap {
-    /* clock module, which includes system and modem */
-    SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
-    SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM  = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
-    /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
-     * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
-    SLEEP_RETENTION_MODULE_BM_SYS_PERIPH   = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
-    /* Timer Group by target*/
-    SLEEP_RETENTION_MODULE_BM_TASK_WDT     = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
-    SLEEP_RETENTION_MODULE_BM_INT_WDT      = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
-    SLEEP_RETENTION_MODULE_BM_TG0_TIMER    = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
-    SLEEP_RETENTION_MODULE_BM_TG1_TIMER    = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
-    /* GDMA by channel */
-    SLEEP_RETENTION_MODULE_BM_GDMA_CH0     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
-    SLEEP_RETENTION_MODULE_BM_GDMA_CH1     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
-    SLEEP_RETENTION_MODULE_BM_GDMA_CH2     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH2),
-    /* MISC Peripherals */
-    SLEEP_RETENTION_MODULE_BM_ADC          = BIT(SLEEP_RETENTION_MODULE_ADC),
-    SLEEP_RETENTION_MODULE_BM_I2C0         = BIT(SLEEP_RETENTION_MODULE_I2C0),
-    SLEEP_RETENTION_MODULE_BM_RMT0         = BIT(SLEEP_RETENTION_MODULE_RMT0),
-    /* modem module, which includes WiFi, BLE and 802.15.4 */
-    SLEEP_RETENTION_MODULE_BM_WIFI_MAC     = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
-    SLEEP_RETENTION_MODULE_BM_WIFI_BB      = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
-    SLEEP_RETENTION_MODULE_BM_BLE_MAC      = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
-    SLEEP_RETENTION_MODULE_BM_BT_BB        = BIT(SLEEP_RETENTION_MODULE_BT_BB),
-    SLEEP_RETENTION_MODULE_BM_802154_MAC   = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
-    SLEEP_RETENTION_MODULE_BM_ALL          = (uint32_t)-1
-} periph_retention_module_bitmap_t;
-
-#define TOP_DOMAIN_PERIPHERALS_BM  (SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM  \
-                                    | SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM \
-                                    | SLEEP_RETENTION_MODULE_BM_SYS_PERIPH  \
-                                    | SLEEP_RETENTION_MODULE_BM_TASK_WDT    \
-                                    | SLEEP_RETENTION_MODULE_BM_INT_WDT     \
-                                    | SLEEP_RETENTION_MODULE_BM_TG0_TIMER   \
-                                    | SLEEP_RETENTION_MODULE_BM_TG1_TIMER   \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH0    \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH1    \
-                                    | SLEEP_RETENTION_MODULE_BM_GDMA_CH2    \
-                                    | SLEEP_RETENTION_MODULE_BM_ADC         \
-                                    | SLEEP_RETENTION_MODULE_BM_I2C0        \
-                                    | SLEEP_RETENTION_MODULE_BM_RMT0)
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/rmt_reg.h b/components/soc/esp32c5/beta3/include/soc/rmt_reg.h
deleted file mode 100644
index 785086a1ef..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/rmt_reg.h
+++ /dev/null
@@ -1,1491 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** RMT_CH0DATA_REG register
- *  The read and write  data register for CHANNEL0 by apb fifo access.
- */
-#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0)
-/** RMT_CH0DATA : HRO; bitpos: [31:0]; default: 0;
- *  Read and write data for channel 0 via APB FIFO.
- */
-#define RMT_CH0DATA    0xFFFFFFFFU
-#define RMT_CH0DATA_M  (RMT_CH0DATA_V << RMT_CH0DATA_S)
-#define RMT_CH0DATA_V  0xFFFFFFFFU
-#define RMT_CH0DATA_S  0
-
-/** RMT_CH1DATA_REG register
- *  The read and write  data register for CHANNEL1 by apb fifo access.
- */
-#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4)
-/** RMT_CH1DATA : HRO; bitpos: [31:0]; default: 0;
- *  Read and write data for channel 1 via APB FIFO.
- */
-#define RMT_CH1DATA    0xFFFFFFFFU
-#define RMT_CH1DATA_M  (RMT_CH1DATA_V << RMT_CH1DATA_S)
-#define RMT_CH1DATA_V  0xFFFFFFFFU
-#define RMT_CH1DATA_S  0
-
-/** RMT_CH2DATA_REG register
- *  The read and write  data register for CHANNEL2 by apb fifo access.
- */
-#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8)
-/** RMT_CH2DATA : HRO; bitpos: [31:0]; default: 0;
- *  Read and write data for channel 2 via APB FIFO.
- */
-#define RMT_CH2DATA    0xFFFFFFFFU
-#define RMT_CH2DATA_M  (RMT_CH2DATA_V << RMT_CH2DATA_S)
-#define RMT_CH2DATA_V  0xFFFFFFFFU
-#define RMT_CH2DATA_S  0
-
-/** RMT_CH3DATA_REG register
- *  The read and write  data register for CHANNEL3 by apb fifo access.
- */
-#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc)
-/** RMT_CH3DATA : HRO; bitpos: [31:0]; default: 0;
- *  Read and write data for channel 3 via APB FIFO.
- */
-#define RMT_CH3DATA    0xFFFFFFFFU
-#define RMT_CH3DATA_M  (RMT_CH3DATA_V << RMT_CH3DATA_S)
-#define RMT_CH3DATA_V  0xFFFFFFFFU
-#define RMT_CH3DATA_S  0
-
-/** RMT_CH0CONF0_REG register
- *  Channel 0 configure register 0
- */
-#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x10)
-/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0;
- *  Set this bit to start sending data on CHANNEL0.
- */
-#define RMT_TX_START_CH0    (BIT(0))
-#define RMT_TX_START_CH0_M  (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S)
-#define RMT_TX_START_CH0_V  0x00000001U
-#define RMT_TX_START_CH0_S  0
-/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset read ram address for CHANNEL0 by accessing transmitter.
- */
-#define RMT_MEM_RD_RST_CH0    (BIT(1))
-#define RMT_MEM_RD_RST_CH0_M  (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S)
-#define RMT_MEM_RD_RST_CH0_V  0x00000001U
-#define RMT_MEM_RD_RST_CH0_S  1
-/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0;
- *  Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo.
- */
-#define RMT_APB_MEM_RST_CH0    (BIT(2))
-#define RMT_APB_MEM_RST_CH0_M  (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S)
-#define RMT_APB_MEM_RST_CH0_V  0x00000001U
-#define RMT_APB_MEM_RST_CH0_S  2
-/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0;
- *  Set this bit to restart transmission  from the first data to the last data in
- *  CHANNEL0.
- */
-#define RMT_TX_CONTI_MODE_CH0    (BIT(3))
-#define RMT_TX_CONTI_MODE_CH0_M  (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S)
-#define RMT_TX_CONTI_MODE_CH0_V  0x00000001U
-#define RMT_TX_CONTI_MODE_CH0_S  3
-/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0;
- *  This is the channel 0 enable bit for wraparound mode: it will resume sending at the
- *  start when the data to be sent is more than its memory size.
- */
-#define RMT_MEM_TX_WRAP_EN_CH0    (BIT(4))
-#define RMT_MEM_TX_WRAP_EN_CH0_M  (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S)
-#define RMT_MEM_TX_WRAP_EN_CH0_V  0x00000001U
-#define RMT_MEM_TX_WRAP_EN_CH0_S  4
-/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0;
- *  This bit configures the level of output signal in CHANNEL0 when the latter is in
- *  IDLE state.
- */
-#define RMT_IDLE_OUT_LV_CH0    (BIT(5))
-#define RMT_IDLE_OUT_LV_CH0_M  (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S)
-#define RMT_IDLE_OUT_LV_CH0_V  0x00000001U
-#define RMT_IDLE_OUT_LV_CH0_S  5
-/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0;
- *  This is the output enable-control bit for CHANNEL0 in IDLE state.
- */
-#define RMT_IDLE_OUT_EN_CH0    (BIT(6))
-#define RMT_IDLE_OUT_EN_CH0_M  (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S)
-#define RMT_IDLE_OUT_EN_CH0_V  0x00000001U
-#define RMT_IDLE_OUT_EN_CH0_S  6
-/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0;
- *  Set this bit to stop the transmitter of CHANNEL0 sending data out.
- */
-#define RMT_TX_STOP_CH0    (BIT(7))
-#define RMT_TX_STOP_CH0_M  (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S)
-#define RMT_TX_STOP_CH0_V  0x00000001U
-#define RMT_TX_STOP_CH0_S  7
-/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2;
- *  This register is used to configure the divider for clock of CHANNEL0.
- */
-#define RMT_DIV_CNT_CH0    0x000000FFU
-#define RMT_DIV_CNT_CH0_M  (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S)
-#define RMT_DIV_CNT_CH0_V  0x000000FFU
-#define RMT_DIV_CNT_CH0_S  8
-/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [18:16]; default: 1;
- *  This register is used to configure the maximum size of memory allocated to CHANNEL0.
- */
-#define RMT_MEM_SIZE_CH0    0x00000007U
-#define RMT_MEM_SIZE_CH0_M  (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S)
-#define RMT_MEM_SIZE_CH0_V  0x00000007U
-#define RMT_MEM_SIZE_CH0_S  16
-/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1;
- *  1: Add carrier modulation on the output signal only at the send data state for
- *  CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0.
- *  Only valid when RMT_CARRIER_EN_CH0 is 1.
- */
-#define RMT_CARRIER_EFF_EN_CH0    (BIT(20))
-#define RMT_CARRIER_EFF_EN_CH0_M  (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S)
-#define RMT_CARRIER_EFF_EN_CH0_V  0x00000001U
-#define RMT_CARRIER_EFF_EN_CH0_S  20
-/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1;
- *  This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier
- *  modulation in the output signal. 0: No carrier modulation in sig_out.
- */
-#define RMT_CARRIER_EN_CH0    (BIT(21))
-#define RMT_CARRIER_EN_CH0_M  (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S)
-#define RMT_CARRIER_EN_CH0_V  0x00000001U
-#define RMT_CARRIER_EN_CH0_S  21
-/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1;
- *  This bit is used to configure the position of carrier wave for CHANNEL0.
- *
- *  1'h0: add carrier wave on low level.
- *
- *  1'h1: add carrier wave on high level.
- */
-#define RMT_CARRIER_OUT_LV_CH0    (BIT(22))
-#define RMT_CARRIER_OUT_LV_CH0_M  (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S)
-#define RMT_CARRIER_OUT_LV_CH0_V  0x00000001U
-#define RMT_CARRIER_OUT_LV_CH0_S  22
-/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0;
- *  synchronization bit for CHANNEL0
- */
-#define RMT_CONF_UPDATE_CH0    (BIT(24))
-#define RMT_CONF_UPDATE_CH0_M  (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S)
-#define RMT_CONF_UPDATE_CH0_V  0x00000001U
-#define RMT_CONF_UPDATE_CH0_S  24
-
-/** RMT_CH1CONF0_REG register
- *  Channel 1 configure register 0
- */
-#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x14)
-/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0;
- *  Set this bit to start sending data on CHANNEL1.
- */
-#define RMT_TX_START_CH1    (BIT(0))
-#define RMT_TX_START_CH1_M  (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S)
-#define RMT_TX_START_CH1_V  0x00000001U
-#define RMT_TX_START_CH1_S  0
-/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset read ram address for CHANNEL1 by accessing transmitter.
- */
-#define RMT_MEM_RD_RST_CH1    (BIT(1))
-#define RMT_MEM_RD_RST_CH1_M  (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S)
-#define RMT_MEM_RD_RST_CH1_V  0x00000001U
-#define RMT_MEM_RD_RST_CH1_S  1
-/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0;
- *  Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo.
- */
-#define RMT_APB_MEM_RST_CH1    (BIT(2))
-#define RMT_APB_MEM_RST_CH1_M  (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S)
-#define RMT_APB_MEM_RST_CH1_V  0x00000001U
-#define RMT_APB_MEM_RST_CH1_S  2
-/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0;
- *  Set this bit to restart transmission  from the first data to the last data in
- *  CHANNEL1.
- */
-#define RMT_TX_CONTI_MODE_CH1    (BIT(3))
-#define RMT_TX_CONTI_MODE_CH1_M  (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S)
-#define RMT_TX_CONTI_MODE_CH1_V  0x00000001U
-#define RMT_TX_CONTI_MODE_CH1_S  3
-/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0;
- *  This is the channel 1 enable bit for wraparound mode: it will resume sending at the
- *  start when the data to be sent is more than its memory size.
- */
-#define RMT_MEM_TX_WRAP_EN_CH1    (BIT(4))
-#define RMT_MEM_TX_WRAP_EN_CH1_M  (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S)
-#define RMT_MEM_TX_WRAP_EN_CH1_V  0x00000001U
-#define RMT_MEM_TX_WRAP_EN_CH1_S  4
-/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0;
- *  This bit configures the level of output signal in CHANNEL1 when the latter is in
- *  IDLE state.
- */
-#define RMT_IDLE_OUT_LV_CH1    (BIT(5))
-#define RMT_IDLE_OUT_LV_CH1_M  (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S)
-#define RMT_IDLE_OUT_LV_CH1_V  0x00000001U
-#define RMT_IDLE_OUT_LV_CH1_S  5
-/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0;
- *  This is the output enable-control bit for CHANNEL1 in IDLE state.
- */
-#define RMT_IDLE_OUT_EN_CH1    (BIT(6))
-#define RMT_IDLE_OUT_EN_CH1_M  (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S)
-#define RMT_IDLE_OUT_EN_CH1_V  0x00000001U
-#define RMT_IDLE_OUT_EN_CH1_S  6
-/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0;
- *  Set this bit to stop the transmitter of CHANNEL1 sending data out.
- */
-#define RMT_TX_STOP_CH1    (BIT(7))
-#define RMT_TX_STOP_CH1_M  (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S)
-#define RMT_TX_STOP_CH1_V  0x00000001U
-#define RMT_TX_STOP_CH1_S  7
-/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2;
- *  This register is used to configure the divider for clock of CHANNEL1.
- */
-#define RMT_DIV_CNT_CH1    0x000000FFU
-#define RMT_DIV_CNT_CH1_M  (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S)
-#define RMT_DIV_CNT_CH1_V  0x000000FFU
-#define RMT_DIV_CNT_CH1_S  8
-/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [18:16]; default: 1;
- *  This register is used to configure the maximum size of memory allocated to CHANNEL1.
- */
-#define RMT_MEM_SIZE_CH1    0x00000007U
-#define RMT_MEM_SIZE_CH1_M  (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S)
-#define RMT_MEM_SIZE_CH1_V  0x00000007U
-#define RMT_MEM_SIZE_CH1_S  16
-/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1;
- *  1: Add carrier modulation on the output signal only at the send data state for
- *  CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1.
- *  Only valid when RMT_CARRIER_EN_CH1 is 1.
- */
-#define RMT_CARRIER_EFF_EN_CH1    (BIT(20))
-#define RMT_CARRIER_EFF_EN_CH1_M  (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S)
-#define RMT_CARRIER_EFF_EN_CH1_V  0x00000001U
-#define RMT_CARRIER_EFF_EN_CH1_S  20
-/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1;
- *  This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier
- *  modulation in the output signal. 0: No carrier modulation in sig_out.
- */
-#define RMT_CARRIER_EN_CH1    (BIT(21))
-#define RMT_CARRIER_EN_CH1_M  (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S)
-#define RMT_CARRIER_EN_CH1_V  0x00000001U
-#define RMT_CARRIER_EN_CH1_S  21
-/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1;
- *  This bit is used to configure the position of carrier wave for CHANNEL1.
- *
- *  1'h0: add carrier wave on low level.
- *
- *  1'h1: add carrier wave on high level.
- */
-#define RMT_CARRIER_OUT_LV_CH1    (BIT(22))
-#define RMT_CARRIER_OUT_LV_CH1_M  (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S)
-#define RMT_CARRIER_OUT_LV_CH1_V  0x00000001U
-#define RMT_CARRIER_OUT_LV_CH1_S  22
-/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0;
- *  synchronization bit for CHANNEL1
- */
-#define RMT_CONF_UPDATE_CH1    (BIT(24))
-#define RMT_CONF_UPDATE_CH1_M  (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S)
-#define RMT_CONF_UPDATE_CH1_V  0x00000001U
-#define RMT_CONF_UPDATE_CH1_S  24
-
-/** RMT_CH2CONF0_REG register
- *  Channel 2 configure register 0
- */
-#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x18)
-/** RMT_DIV_CNT_CH2 : R/W; bitpos: [7:0]; default: 2;
- *  This register is used to configure the divider for clock of CHANNEL2.
- */
-#define RMT_DIV_CNT_CH2    0x000000FFU
-#define RMT_DIV_CNT_CH2_M  (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S)
-#define RMT_DIV_CNT_CH2_V  0x000000FFU
-#define RMT_DIV_CNT_CH2_S  0
-/** RMT_IDLE_THRES_CH2 : R/W; bitpos: [22:8]; default: 32767;
- *  When no edge is detected on the input signal and continuous clock cycles is longer
- *  than this register value, received process is finished.
- */
-#define RMT_IDLE_THRES_CH2    0x00007FFFU
-#define RMT_IDLE_THRES_CH2_M  (RMT_IDLE_THRES_CH2_V << RMT_IDLE_THRES_CH2_S)
-#define RMT_IDLE_THRES_CH2_V  0x00007FFFU
-#define RMT_IDLE_THRES_CH2_S  8
-/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [25:23]; default: 1;
- *  This register is used to configure the maximum size of memory allocated to CHANNEL2.
- */
-#define RMT_MEM_SIZE_CH2    0x00000007U
-#define RMT_MEM_SIZE_CH2_M  (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S)
-#define RMT_MEM_SIZE_CH2_V  0x00000007U
-#define RMT_MEM_SIZE_CH2_S  23
-/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [28]; default: 1;
- *  This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier
- *  modulation in the output signal. 0: No carrier modulation in sig_out.
- */
-#define RMT_CARRIER_EN_CH2    (BIT(28))
-#define RMT_CARRIER_EN_CH2_M  (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S)
-#define RMT_CARRIER_EN_CH2_V  0x00000001U
-#define RMT_CARRIER_EN_CH2_S  28
-/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [29]; default: 1;
- *  This bit is used to configure the position of carrier wave for CHANNEL2.
- *
- *  1'h0: add carrier wave on low level.
- *
- *  1'h1: add carrier wave on high level.
- */
-#define RMT_CARRIER_OUT_LV_CH2    (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH2_M  (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S)
-#define RMT_CARRIER_OUT_LV_CH2_V  0x00000001U
-#define RMT_CARRIER_OUT_LV_CH2_S  29
-
-/** RMT_CH2CONF1_REG register
- *  Channel 2 configure register 1
- */
-#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x1c)
-/** RMT_RX_EN_CH2 : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable receiver to receive data on CHANNEL2.
- */
-#define RMT_RX_EN_CH2    (BIT(0))
-#define RMT_RX_EN_CH2_M  (RMT_RX_EN_CH2_V << RMT_RX_EN_CH2_S)
-#define RMT_RX_EN_CH2_V  0x00000001U
-#define RMT_RX_EN_CH2_S  0
-/** RMT_MEM_WR_RST_CH2 : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset write ram address for CHANNEL2 by accessing receiver.
- */
-#define RMT_MEM_WR_RST_CH2    (BIT(1))
-#define RMT_MEM_WR_RST_CH2_M  (RMT_MEM_WR_RST_CH2_V << RMT_MEM_WR_RST_CH2_S)
-#define RMT_MEM_WR_RST_CH2_V  0x00000001U
-#define RMT_MEM_WR_RST_CH2_S  1
-/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0;
- *  Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo.
- */
-#define RMT_APB_MEM_RST_CH2    (BIT(2))
-#define RMT_APB_MEM_RST_CH2_M  (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S)
-#define RMT_APB_MEM_RST_CH2_V  0x00000001U
-#define RMT_APB_MEM_RST_CH2_S  2
-/** RMT_MEM_OWNER_CH2 : R/W/SC; bitpos: [3]; default: 1;
- *  This register marks the ownership of CHANNEL2's ram block.
- *
- *  1'h1: Receiver is using the ram.
- *
- *  1'h0: APB bus is using the ram.
- */
-#define RMT_MEM_OWNER_CH2    (BIT(3))
-#define RMT_MEM_OWNER_CH2_M  (RMT_MEM_OWNER_CH2_V << RMT_MEM_OWNER_CH2_S)
-#define RMT_MEM_OWNER_CH2_V  0x00000001U
-#define RMT_MEM_OWNER_CH2_S  3
-/** RMT_RX_FILTER_EN_CH2 : R/W; bitpos: [4]; default: 0;
- *  This is the receive filter's enable bit for CHANNEL2.
- */
-#define RMT_RX_FILTER_EN_CH2    (BIT(4))
-#define RMT_RX_FILTER_EN_CH2_M  (RMT_RX_FILTER_EN_CH2_V << RMT_RX_FILTER_EN_CH2_S)
-#define RMT_RX_FILTER_EN_CH2_V  0x00000001U
-#define RMT_RX_FILTER_EN_CH2_S  4
-/** RMT_RX_FILTER_THRES_CH2 : R/W; bitpos: [12:5]; default: 15;
- *  Ignores the input pulse when its width is smaller than this register value in APB
- *  clock periods (in receive mode).
- */
-#define RMT_RX_FILTER_THRES_CH2    0x000000FFU
-#define RMT_RX_FILTER_THRES_CH2_M  (RMT_RX_FILTER_THRES_CH2_V << RMT_RX_FILTER_THRES_CH2_S)
-#define RMT_RX_FILTER_THRES_CH2_V  0x000000FFU
-#define RMT_RX_FILTER_THRES_CH2_S  5
-/** RMT_MEM_RX_WRAP_EN_CH2 : R/W; bitpos: [13]; default: 0;
- *  This is the channel 2 enable bit for wraparound mode: it will resume receiving at
- *  the start when the data to be received is more than its memory size.
- */
-#define RMT_MEM_RX_WRAP_EN_CH2    (BIT(13))
-#define RMT_MEM_RX_WRAP_EN_CH2_M  (RMT_MEM_RX_WRAP_EN_CH2_V << RMT_MEM_RX_WRAP_EN_CH2_S)
-#define RMT_MEM_RX_WRAP_EN_CH2_V  0x00000001U
-#define RMT_MEM_RX_WRAP_EN_CH2_S  13
-/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [15]; default: 0;
- *  synchronization bit for CHANNEL2
- */
-#define RMT_CONF_UPDATE_CH2    (BIT(15))
-#define RMT_CONF_UPDATE_CH2_M  (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S)
-#define RMT_CONF_UPDATE_CH2_V  0x00000001U
-#define RMT_CONF_UPDATE_CH2_S  15
-
-/** RMT_CH3CONF0_REG register
- *  Channel 3 configure register 0
- */
-#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x20)
-/** RMT_DIV_CNT_CH3 : R/W; bitpos: [7:0]; default: 2;
- *  This register is used to configure the divider for clock of CHANNEL3.
- */
-#define RMT_DIV_CNT_CH3    0x000000FFU
-#define RMT_DIV_CNT_CH3_M  (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S)
-#define RMT_DIV_CNT_CH3_V  0x000000FFU
-#define RMT_DIV_CNT_CH3_S  0
-/** RMT_IDLE_THRES_CH3 : R/W; bitpos: [22:8]; default: 32767;
- *  When no edge is detected on the input signal and continuous clock cycles is longer
- *  than this register value, received process is finished.
- */
-#define RMT_IDLE_THRES_CH3    0x00007FFFU
-#define RMT_IDLE_THRES_CH3_M  (RMT_IDLE_THRES_CH3_V << RMT_IDLE_THRES_CH3_S)
-#define RMT_IDLE_THRES_CH3_V  0x00007FFFU
-#define RMT_IDLE_THRES_CH3_S  8
-/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [25:23]; default: 1;
- *  This register is used to configure the maximum size of memory allocated to CHANNEL3.
- */
-#define RMT_MEM_SIZE_CH3    0x00000007U
-#define RMT_MEM_SIZE_CH3_M  (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S)
-#define RMT_MEM_SIZE_CH3_V  0x00000007U
-#define RMT_MEM_SIZE_CH3_S  23
-/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [28]; default: 1;
- *  This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier
- *  modulation in the output signal. 0: No carrier modulation in sig_out.
- */
-#define RMT_CARRIER_EN_CH3    (BIT(28))
-#define RMT_CARRIER_EN_CH3_M  (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S)
-#define RMT_CARRIER_EN_CH3_V  0x00000001U
-#define RMT_CARRIER_EN_CH3_S  28
-/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [29]; default: 1;
- *  This bit is used to configure the position of carrier wave for CHANNEL3.
- *
- *  1'h0: add carrier wave on low level.
- *
- *  1'h1: add carrier wave on high level.
- */
-#define RMT_CARRIER_OUT_LV_CH3    (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH3_M  (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S)
-#define RMT_CARRIER_OUT_LV_CH3_V  0x00000001U
-#define RMT_CARRIER_OUT_LV_CH3_S  29
-
-/** RMT_CH3CONF1_REG register
- *  Channel 3 configure register 1
- */
-#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x24)
-/** RMT_RX_EN_CH3 : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable receiver to receive data on CHANNEL3.
- */
-#define RMT_RX_EN_CH3    (BIT(0))
-#define RMT_RX_EN_CH3_M  (RMT_RX_EN_CH3_V << RMT_RX_EN_CH3_S)
-#define RMT_RX_EN_CH3_V  0x00000001U
-#define RMT_RX_EN_CH3_S  0
-/** RMT_MEM_WR_RST_CH3 : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset write ram address for CHANNEL3 by accessing receiver.
- */
-#define RMT_MEM_WR_RST_CH3    (BIT(1))
-#define RMT_MEM_WR_RST_CH3_M  (RMT_MEM_WR_RST_CH3_V << RMT_MEM_WR_RST_CH3_S)
-#define RMT_MEM_WR_RST_CH3_V  0x00000001U
-#define RMT_MEM_WR_RST_CH3_S  1
-/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0;
- *  Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo.
- */
-#define RMT_APB_MEM_RST_CH3    (BIT(2))
-#define RMT_APB_MEM_RST_CH3_M  (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S)
-#define RMT_APB_MEM_RST_CH3_V  0x00000001U
-#define RMT_APB_MEM_RST_CH3_S  2
-/** RMT_MEM_OWNER_CH3 : R/W/SC; bitpos: [3]; default: 1;
- *  This register marks the ownership of CHANNEL3's ram block.
- *
- *  1'h1: Receiver is using the ram.
- *
- *  1'h0: APB bus is using the ram.
- */
-#define RMT_MEM_OWNER_CH3    (BIT(3))
-#define RMT_MEM_OWNER_CH3_M  (RMT_MEM_OWNER_CH3_V << RMT_MEM_OWNER_CH3_S)
-#define RMT_MEM_OWNER_CH3_V  0x00000001U
-#define RMT_MEM_OWNER_CH3_S  3
-/** RMT_RX_FILTER_EN_CH3 : R/W; bitpos: [4]; default: 0;
- *  This is the receive filter's enable bit for CHANNEL3.
- */
-#define RMT_RX_FILTER_EN_CH3    (BIT(4))
-#define RMT_RX_FILTER_EN_CH3_M  (RMT_RX_FILTER_EN_CH3_V << RMT_RX_FILTER_EN_CH3_S)
-#define RMT_RX_FILTER_EN_CH3_V  0x00000001U
-#define RMT_RX_FILTER_EN_CH3_S  4
-/** RMT_RX_FILTER_THRES_CH3 : R/W; bitpos: [12:5]; default: 15;
- *  Ignores the input pulse when its width is smaller than this register value in APB
- *  clock periods (in receive mode).
- */
-#define RMT_RX_FILTER_THRES_CH3    0x000000FFU
-#define RMT_RX_FILTER_THRES_CH3_M  (RMT_RX_FILTER_THRES_CH3_V << RMT_RX_FILTER_THRES_CH3_S)
-#define RMT_RX_FILTER_THRES_CH3_V  0x000000FFU
-#define RMT_RX_FILTER_THRES_CH3_S  5
-/** RMT_MEM_RX_WRAP_EN_CH3 : R/W; bitpos: [13]; default: 0;
- *  This is the channel 3 enable bit for wraparound mode: it will resume receiving at
- *  the start when the data to be received is more than its memory size.
- */
-#define RMT_MEM_RX_WRAP_EN_CH3    (BIT(13))
-#define RMT_MEM_RX_WRAP_EN_CH3_M  (RMT_MEM_RX_WRAP_EN_CH3_V << RMT_MEM_RX_WRAP_EN_CH3_S)
-#define RMT_MEM_RX_WRAP_EN_CH3_V  0x00000001U
-#define RMT_MEM_RX_WRAP_EN_CH3_S  13
-/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [15]; default: 0;
- *  synchronization bit for CHANNEL3
- */
-#define RMT_CONF_UPDATE_CH3    (BIT(15))
-#define RMT_CONF_UPDATE_CH3_M  (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S)
-#define RMT_CONF_UPDATE_CH3_V  0x00000001U
-#define RMT_CONF_UPDATE_CH3_S  15
-
-/** RMT_CH0STATUS_REG register
- *  Channel 0 status register
- */
-#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x28)
-/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0;
- *  This register records the memory address offset when transmitter of CHANNEL0 is
- *  using the RAM.
- */
-#define RMT_MEM_RADDR_EX_CH0    0x000001FFU
-#define RMT_MEM_RADDR_EX_CH0_M  (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S)
-#define RMT_MEM_RADDR_EX_CH0_V  0x000001FFU
-#define RMT_MEM_RADDR_EX_CH0_S  0
-/** RMT_STATE_CH0 : RO; bitpos: [11:9]; default: 0;
- *  This register records the FSM status of CHANNEL0.
- */
-#define RMT_STATE_CH0    0x00000007U
-#define RMT_STATE_CH0_M  (RMT_STATE_CH0_V << RMT_STATE_CH0_S)
-#define RMT_STATE_CH0_V  0x00000007U
-#define RMT_STATE_CH0_S  9
-/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:12]; default: 0;
- *  This register records the memory address offset when writes RAM over APB bus.
- */
-#define RMT_APB_MEM_WADDR_CH0    0x000001FFU
-#define RMT_APB_MEM_WADDR_CH0_M  (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S)
-#define RMT_APB_MEM_WADDR_CH0_V  0x000001FFU
-#define RMT_APB_MEM_WADDR_CH0_S  12
-/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [21]; default: 0;
- *  This status bit will be set if the offset address out of memory size when reading
- *  via APB bus.
- */
-#define RMT_APB_MEM_RD_ERR_CH0    (BIT(21))
-#define RMT_APB_MEM_RD_ERR_CH0_M  (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S)
-#define RMT_APB_MEM_RD_ERR_CH0_V  0x00000001U
-#define RMT_APB_MEM_RD_ERR_CH0_S  21
-/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [22]; default: 0;
- *  This status bit will be set when the data to be set is more than memory size and
- *  the wraparound mode is disabled.
- */
-#define RMT_MEM_EMPTY_CH0    (BIT(22))
-#define RMT_MEM_EMPTY_CH0_M  (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S)
-#define RMT_MEM_EMPTY_CH0_V  0x00000001U
-#define RMT_MEM_EMPTY_CH0_S  22
-/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [23]; default: 0;
- *  This status bit will be set if the offset address out of memory size when writes
- *  via APB bus.
- */
-#define RMT_APB_MEM_WR_ERR_CH0    (BIT(23))
-#define RMT_APB_MEM_WR_ERR_CH0_M  (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S)
-#define RMT_APB_MEM_WR_ERR_CH0_V  0x00000001U
-#define RMT_APB_MEM_WR_ERR_CH0_S  23
-/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [31:24]; default: 0;
- *  This register records the memory address offset when reading RAM over APB bus.
- */
-#define RMT_APB_MEM_RADDR_CH0    0x000000FFU
-#define RMT_APB_MEM_RADDR_CH0_M  (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S)
-#define RMT_APB_MEM_RADDR_CH0_V  0x000000FFU
-#define RMT_APB_MEM_RADDR_CH0_S  24
-
-/** RMT_CH1STATUS_REG register
- *  Channel 1 status register
- */
-#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x2c)
-/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [8:0]; default: 0;
- *  This register records the memory address offset when transmitter of CHANNEL1 is
- *  using the RAM.
- */
-#define RMT_MEM_RADDR_EX_CH1    0x000001FFU
-#define RMT_MEM_RADDR_EX_CH1_M  (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S)
-#define RMT_MEM_RADDR_EX_CH1_V  0x000001FFU
-#define RMT_MEM_RADDR_EX_CH1_S  0
-/** RMT_STATE_CH1 : RO; bitpos: [11:9]; default: 0;
- *  This register records the FSM status of CHANNEL1.
- */
-#define RMT_STATE_CH1    0x00000007U
-#define RMT_STATE_CH1_M  (RMT_STATE_CH1_V << RMT_STATE_CH1_S)
-#define RMT_STATE_CH1_V  0x00000007U
-#define RMT_STATE_CH1_S  9
-/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:12]; default: 0;
- *  This register records the memory address offset when writes RAM over APB bus.
- */
-#define RMT_APB_MEM_WADDR_CH1    0x000001FFU
-#define RMT_APB_MEM_WADDR_CH1_M  (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S)
-#define RMT_APB_MEM_WADDR_CH1_V  0x000001FFU
-#define RMT_APB_MEM_WADDR_CH1_S  12
-/** RMT_APB_MEM_RD_ERR_CH1 : RO; bitpos: [21]; default: 0;
- *  This status bit will be set if the offset address out of memory size when reading
- *  via APB bus.
- */
-#define RMT_APB_MEM_RD_ERR_CH1    (BIT(21))
-#define RMT_APB_MEM_RD_ERR_CH1_M  (RMT_APB_MEM_RD_ERR_CH1_V << RMT_APB_MEM_RD_ERR_CH1_S)
-#define RMT_APB_MEM_RD_ERR_CH1_V  0x00000001U
-#define RMT_APB_MEM_RD_ERR_CH1_S  21
-/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [22]; default: 0;
- *  This status bit will be set when the data to be set is more than memory size and
- *  the wraparound mode is disabled.
- */
-#define RMT_MEM_EMPTY_CH1    (BIT(22))
-#define RMT_MEM_EMPTY_CH1_M  (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S)
-#define RMT_MEM_EMPTY_CH1_V  0x00000001U
-#define RMT_MEM_EMPTY_CH1_S  22
-/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [23]; default: 0;
- *  This status bit will be set if the offset address out of memory size when writes
- *  via APB bus.
- */
-#define RMT_APB_MEM_WR_ERR_CH1    (BIT(23))
-#define RMT_APB_MEM_WR_ERR_CH1_M  (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S)
-#define RMT_APB_MEM_WR_ERR_CH1_V  0x00000001U
-#define RMT_APB_MEM_WR_ERR_CH1_S  23
-/** RMT_APB_MEM_RADDR_CH1 : RO; bitpos: [31:24]; default: 0;
- *  This register records the memory address offset when reading RAM over APB bus.
- */
-#define RMT_APB_MEM_RADDR_CH1    0x000000FFU
-#define RMT_APB_MEM_RADDR_CH1_M  (RMT_APB_MEM_RADDR_CH1_V << RMT_APB_MEM_RADDR_CH1_S)
-#define RMT_APB_MEM_RADDR_CH1_V  0x000000FFU
-#define RMT_APB_MEM_RADDR_CH1_S  24
-
-/** RMT_CH2STATUS_REG register
- *  Channel 2 status register
- */
-#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x30)
-/** RMT_MEM_WADDR_EX_CH2 : RO; bitpos: [8:0]; default: 0;
- *  This register records the memory address offset when receiver of CHANNEL2 is using
- *  the RAM.
- */
-#define RMT_MEM_WADDR_EX_CH2    0x000001FFU
-#define RMT_MEM_WADDR_EX_CH2_M  (RMT_MEM_WADDR_EX_CH2_V << RMT_MEM_WADDR_EX_CH2_S)
-#define RMT_MEM_WADDR_EX_CH2_V  0x000001FFU
-#define RMT_MEM_WADDR_EX_CH2_S  0
-/** RMT_APB_MEM_RADDR_CH2 : RO; bitpos: [20:12]; default: 0;
- *  This register records the memory address offset when reads RAM over APB bus.
- */
-#define RMT_APB_MEM_RADDR_CH2    0x000001FFU
-#define RMT_APB_MEM_RADDR_CH2_M  (RMT_APB_MEM_RADDR_CH2_V << RMT_APB_MEM_RADDR_CH2_S)
-#define RMT_APB_MEM_RADDR_CH2_V  0x000001FFU
-#define RMT_APB_MEM_RADDR_CH2_S  12
-/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0;
- *  This register records the FSM status of CHANNEL2.
- */
-#define RMT_STATE_CH2    0x00000007U
-#define RMT_STATE_CH2_M  (RMT_STATE_CH2_V << RMT_STATE_CH2_S)
-#define RMT_STATE_CH2_V  0x00000007U
-#define RMT_STATE_CH2_S  22
-/** RMT_MEM_OWNER_ERR_CH2 : RO; bitpos: [25]; default: 0;
- *  This status bit will be set when the ownership of memory block is wrong.
- */
-#define RMT_MEM_OWNER_ERR_CH2    (BIT(25))
-#define RMT_MEM_OWNER_ERR_CH2_M  (RMT_MEM_OWNER_ERR_CH2_V << RMT_MEM_OWNER_ERR_CH2_S)
-#define RMT_MEM_OWNER_ERR_CH2_V  0x00000001U
-#define RMT_MEM_OWNER_ERR_CH2_S  25
-/** RMT_MEM_FULL_CH2 : RO; bitpos: [26]; default: 0;
- *  This status bit will be set if the receiver receives more data than the memory size.
- */
-#define RMT_MEM_FULL_CH2    (BIT(26))
-#define RMT_MEM_FULL_CH2_M  (RMT_MEM_FULL_CH2_V << RMT_MEM_FULL_CH2_S)
-#define RMT_MEM_FULL_CH2_V  0x00000001U
-#define RMT_MEM_FULL_CH2_S  26
-/** RMT_APB_MEM_RD_ERR_CH2 : RO; bitpos: [27]; default: 0;
- *  This status bit will be set if the offset address out of memory size when reads via
- *  APB bus.
- */
-#define RMT_APB_MEM_RD_ERR_CH2    (BIT(27))
-#define RMT_APB_MEM_RD_ERR_CH2_M  (RMT_APB_MEM_RD_ERR_CH2_V << RMT_APB_MEM_RD_ERR_CH2_S)
-#define RMT_APB_MEM_RD_ERR_CH2_V  0x00000001U
-#define RMT_APB_MEM_RD_ERR_CH2_S  27
-
-/** RMT_CH3STATUS_REG register
- *  Channel 3 status register
- */
-#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x34)
-/** RMT_MEM_WADDR_EX_CH3 : RO; bitpos: [8:0]; default: 0;
- *  This register records the memory address offset when receiver of CHANNEL3 is using
- *  the RAM.
- */
-#define RMT_MEM_WADDR_EX_CH3    0x000001FFU
-#define RMT_MEM_WADDR_EX_CH3_M  (RMT_MEM_WADDR_EX_CH3_V << RMT_MEM_WADDR_EX_CH3_S)
-#define RMT_MEM_WADDR_EX_CH3_V  0x000001FFU
-#define RMT_MEM_WADDR_EX_CH3_S  0
-/** RMT_APB_MEM_RADDR_CH3 : RO; bitpos: [20:12]; default: 0;
- *  This register records the memory address offset when reads RAM over APB bus.
- */
-#define RMT_APB_MEM_RADDR_CH3    0x000001FFU
-#define RMT_APB_MEM_RADDR_CH3_M  (RMT_APB_MEM_RADDR_CH3_V << RMT_APB_MEM_RADDR_CH3_S)
-#define RMT_APB_MEM_RADDR_CH3_V  0x000001FFU
-#define RMT_APB_MEM_RADDR_CH3_S  12
-/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0;
- *  This register records the FSM status of CHANNEL3.
- */
-#define RMT_STATE_CH3    0x00000007U
-#define RMT_STATE_CH3_M  (RMT_STATE_CH3_V << RMT_STATE_CH3_S)
-#define RMT_STATE_CH3_V  0x00000007U
-#define RMT_STATE_CH3_S  22
-/** RMT_MEM_OWNER_ERR_CH3 : RO; bitpos: [25]; default: 0;
- *  This status bit will be set when the ownership of memory block is wrong.
- */
-#define RMT_MEM_OWNER_ERR_CH3    (BIT(25))
-#define RMT_MEM_OWNER_ERR_CH3_M  (RMT_MEM_OWNER_ERR_CH3_V << RMT_MEM_OWNER_ERR_CH3_S)
-#define RMT_MEM_OWNER_ERR_CH3_V  0x00000001U
-#define RMT_MEM_OWNER_ERR_CH3_S  25
-/** RMT_MEM_FULL_CH3 : RO; bitpos: [26]; default: 0;
- *  This status bit will be set if the receiver receives more data than the memory size.
- */
-#define RMT_MEM_FULL_CH3    (BIT(26))
-#define RMT_MEM_FULL_CH3_M  (RMT_MEM_FULL_CH3_V << RMT_MEM_FULL_CH3_S)
-#define RMT_MEM_FULL_CH3_V  0x00000001U
-#define RMT_MEM_FULL_CH3_S  26
-/** RMT_APB_MEM_RD_ERR_CH3 : RO; bitpos: [27]; default: 0;
- *  This status bit will be set if the offset address out of memory size when reads via
- *  APB bus.
- */
-#define RMT_APB_MEM_RD_ERR_CH3    (BIT(27))
-#define RMT_APB_MEM_RD_ERR_CH3_M  (RMT_APB_MEM_RD_ERR_CH3_V << RMT_APB_MEM_RD_ERR_CH3_S)
-#define RMT_APB_MEM_RD_ERR_CH3_V  0x00000001U
-#define RMT_APB_MEM_RD_ERR_CH3_S  27
-
-/** RMT_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x38)
-/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The interrupt raw bit for CHANNEL0. Triggered when transmission done.
- */
-#define RMT_CH0_TX_END_INT_RAW    (BIT(0))
-#define RMT_CH0_TX_END_INT_RAW_M  (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S)
-#define RMT_CH0_TX_END_INT_RAW_V  0x00000001U
-#define RMT_CH0_TX_END_INT_RAW_S  0
-/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The interrupt raw bit for CHANNEL1. Triggered when transmission done.
- */
-#define RMT_CH1_TX_END_INT_RAW    (BIT(1))
-#define RMT_CH1_TX_END_INT_RAW_M  (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S)
-#define RMT_CH1_TX_END_INT_RAW_V  0x00000001U
-#define RMT_CH1_TX_END_INT_RAW_S  1
-/** RMT_CH2_RX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The interrupt raw bit for CHANNEL2. Triggered when reception done.
- */
-#define RMT_CH2_RX_END_INT_RAW    (BIT(2))
-#define RMT_CH2_RX_END_INT_RAW_M  (RMT_CH2_RX_END_INT_RAW_V << RMT_CH2_RX_END_INT_RAW_S)
-#define RMT_CH2_RX_END_INT_RAW_V  0x00000001U
-#define RMT_CH2_RX_END_INT_RAW_S  2
-/** RMT_CH3_RX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The interrupt raw bit for CHANNEL3. Triggered when reception done.
- */
-#define RMT_CH3_RX_END_INT_RAW    (BIT(3))
-#define RMT_CH3_RX_END_INT_RAW_M  (RMT_CH3_RX_END_INT_RAW_V << RMT_CH3_RX_END_INT_RAW_S)
-#define RMT_CH3_RX_END_INT_RAW_V  0x00000001U
-#define RMT_CH3_RX_END_INT_RAW_S  3
-/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
- */
-#define RMT_CH0_ERR_INT_RAW    (BIT(4))
-#define RMT_CH0_ERR_INT_RAW_M  (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S)
-#define RMT_CH0_ERR_INT_RAW_V  0x00000001U
-#define RMT_CH0_ERR_INT_RAW_S  4
-/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
- */
-#define RMT_CH1_ERR_INT_RAW    (BIT(5))
-#define RMT_CH1_ERR_INT_RAW_M  (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S)
-#define RMT_CH1_ERR_INT_RAW_V  0x00000001U
-#define RMT_CH1_ERR_INT_RAW_S  5
-/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
- */
-#define RMT_CH2_ERR_INT_RAW    (BIT(6))
-#define RMT_CH2_ERR_INT_RAW_M  (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S)
-#define RMT_CH2_ERR_INT_RAW_V  0x00000001U
-#define RMT_CH2_ERR_INT_RAW_S  6
-/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
- */
-#define RMT_CH3_ERR_INT_RAW    (BIT(7))
-#define RMT_CH3_ERR_INT_RAW_M  (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S)
-#define RMT_CH3_ERR_INT_RAW_V  0x00000001U
-#define RMT_CH3_ERR_INT_RAW_S  7
-/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
- *  configured value.
- */
-#define RMT_CH0_TX_THR_EVENT_INT_RAW    (BIT(8))
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_M  (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S)
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_V  0x00000001U
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_S  8
-/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
- *  configured value.
- */
-#define RMT_CH1_TX_THR_EVENT_INT_RAW    (BIT(9))
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_M  (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S)
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_V  0x00000001U
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_S  9
-/** RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than
- *  configured value.
- */
-#define RMT_CH2_RX_THR_EVENT_INT_RAW    (BIT(10))
-#define RMT_CH2_RX_THR_EVENT_INT_RAW_M  (RMT_CH2_RX_THR_EVENT_INT_RAW_V << RMT_CH2_RX_THR_EVENT_INT_RAW_S)
-#define RMT_CH2_RX_THR_EVENT_INT_RAW_V  0x00000001U
-#define RMT_CH2_RX_THR_EVENT_INT_RAW_S  10
-/** RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than
- *  configured value.
- */
-#define RMT_CH3_RX_THR_EVENT_INT_RAW    (BIT(11))
-#define RMT_CH3_RX_THR_EVENT_INT_RAW_M  (RMT_CH3_RX_THR_EVENT_INT_RAW_V << RMT_CH3_RX_THR_EVENT_INT_RAW_S)
-#define RMT_CH3_RX_THR_EVENT_INT_RAW_V  0x00000001U
-#define RMT_CH3_RX_THR_EVENT_INT_RAW_S  11
-/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
- *  configured threshold value.
- */
-#define RMT_CH0_TX_LOOP_INT_RAW    (BIT(12))
-#define RMT_CH0_TX_LOOP_INT_RAW_M  (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S)
-#define RMT_CH0_TX_LOOP_INT_RAW_V  0x00000001U
-#define RMT_CH0_TX_LOOP_INT_RAW_S  12
-/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
- *  configured threshold value.
- */
-#define RMT_CH1_TX_LOOP_INT_RAW    (BIT(13))
-#define RMT_CH1_TX_LOOP_INT_RAW_M  (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S)
-#define RMT_CH1_TX_LOOP_INT_RAW_V  0x00000001U
-#define RMT_CH1_TX_LOOP_INT_RAW_S  13
-
-/** RMT_INT_ST_REG register
- *  Masked interrupt status
- */
-#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x3c)
-/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit for CH0_TX_END_INT.
- */
-#define RMT_CH0_TX_END_INT_ST    (BIT(0))
-#define RMT_CH0_TX_END_INT_ST_M  (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S)
-#define RMT_CH0_TX_END_INT_ST_V  0x00000001U
-#define RMT_CH0_TX_END_INT_ST_S  0
-/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit for CH1_TX_END_INT.
- */
-#define RMT_CH1_TX_END_INT_ST    (BIT(1))
-#define RMT_CH1_TX_END_INT_ST_M  (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S)
-#define RMT_CH1_TX_END_INT_ST_V  0x00000001U
-#define RMT_CH1_TX_END_INT_ST_S  1
-/** RMT_CH2_RX_END_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit for CH2_RX_END_INT.
- */
-#define RMT_CH2_RX_END_INT_ST    (BIT(2))
-#define RMT_CH2_RX_END_INT_ST_M  (RMT_CH2_RX_END_INT_ST_V << RMT_CH2_RX_END_INT_ST_S)
-#define RMT_CH2_RX_END_INT_ST_V  0x00000001U
-#define RMT_CH2_RX_END_INT_ST_S  2
-/** RMT_CH3_RX_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit for CH3_RX_END_INT.
- */
-#define RMT_CH3_RX_END_INT_ST    (BIT(3))
-#define RMT_CH3_RX_END_INT_ST_M  (RMT_CH3_RX_END_INT_ST_V << RMT_CH3_RX_END_INT_ST_S)
-#define RMT_CH3_RX_END_INT_ST_V  0x00000001U
-#define RMT_CH3_RX_END_INT_ST_S  3
-/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked interrupt status bit for CH$n_ERR_INT.
- */
-#define RMT_CH0_ERR_INT_ST    (BIT(4))
-#define RMT_CH0_ERR_INT_ST_M  (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S)
-#define RMT_CH0_ERR_INT_ST_V  0x00000001U
-#define RMT_CH0_ERR_INT_ST_S  4
-/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked interrupt status bit for CH$n_ERR_INT.
- */
-#define RMT_CH1_ERR_INT_ST    (BIT(5))
-#define RMT_CH1_ERR_INT_ST_M  (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S)
-#define RMT_CH1_ERR_INT_ST_V  0x00000001U
-#define RMT_CH1_ERR_INT_ST_S  5
-/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked interrupt status bit for CH$n_ERR_INT.
- */
-#define RMT_CH2_ERR_INT_ST    (BIT(6))
-#define RMT_CH2_ERR_INT_ST_M  (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S)
-#define RMT_CH2_ERR_INT_ST_V  0x00000001U
-#define RMT_CH2_ERR_INT_ST_S  6
-/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked interrupt status bit for CH$n_ERR_INT.
- */
-#define RMT_CH3_ERR_INT_ST    (BIT(7))
-#define RMT_CH3_ERR_INT_ST_M  (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S)
-#define RMT_CH3_ERR_INT_ST_V  0x00000001U
-#define RMT_CH3_ERR_INT_ST_S  7
-/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
- */
-#define RMT_CH0_TX_THR_EVENT_INT_ST    (BIT(8))
-#define RMT_CH0_TX_THR_EVENT_INT_ST_M  (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S)
-#define RMT_CH0_TX_THR_EVENT_INT_ST_V  0x00000001U
-#define RMT_CH0_TX_THR_EVENT_INT_ST_S  8
-/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
- */
-#define RMT_CH1_TX_THR_EVENT_INT_ST    (BIT(9))
-#define RMT_CH1_TX_THR_EVENT_INT_ST_M  (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S)
-#define RMT_CH1_TX_THR_EVENT_INT_ST_V  0x00000001U
-#define RMT_CH1_TX_THR_EVENT_INT_ST_S  9
-/** RMT_CH2_RX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked interrupt status bit for CH2_RX_THR_EVENT_INT.
- */
-#define RMT_CH2_RX_THR_EVENT_INT_ST    (BIT(10))
-#define RMT_CH2_RX_THR_EVENT_INT_ST_M  (RMT_CH2_RX_THR_EVENT_INT_ST_V << RMT_CH2_RX_THR_EVENT_INT_ST_S)
-#define RMT_CH2_RX_THR_EVENT_INT_ST_V  0x00000001U
-#define RMT_CH2_RX_THR_EVENT_INT_ST_S  10
-/** RMT_CH3_RX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked interrupt status bit for CH3_RX_THR_EVENT_INT.
- */
-#define RMT_CH3_RX_THR_EVENT_INT_ST    (BIT(11))
-#define RMT_CH3_RX_THR_EVENT_INT_ST_M  (RMT_CH3_RX_THR_EVENT_INT_ST_V << RMT_CH3_RX_THR_EVENT_INT_ST_S)
-#define RMT_CH3_RX_THR_EVENT_INT_ST_V  0x00000001U
-#define RMT_CH3_RX_THR_EVENT_INT_ST_S  11
-/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked interrupt status bit for CH0_TX_LOOP_INT.
- */
-#define RMT_CH0_TX_LOOP_INT_ST    (BIT(12))
-#define RMT_CH0_TX_LOOP_INT_ST_M  (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S)
-#define RMT_CH0_TX_LOOP_INT_ST_V  0x00000001U
-#define RMT_CH0_TX_LOOP_INT_ST_S  12
-/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked interrupt status bit for CH1_TX_LOOP_INT.
- */
-#define RMT_CH1_TX_LOOP_INT_ST    (BIT(13))
-#define RMT_CH1_TX_LOOP_INT_ST_M  (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S)
-#define RMT_CH1_TX_LOOP_INT_ST_V  0x00000001U
-#define RMT_CH1_TX_LOOP_INT_ST_S  13
-
-/** RMT_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x40)
-/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for CH0_TX_END_INT.
- */
-#define RMT_CH0_TX_END_INT_ENA    (BIT(0))
-#define RMT_CH0_TX_END_INT_ENA_M  (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S)
-#define RMT_CH0_TX_END_INT_ENA_V  0x00000001U
-#define RMT_CH0_TX_END_INT_ENA_S  0
-/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for CH1_TX_END_INT.
- */
-#define RMT_CH1_TX_END_INT_ENA    (BIT(1))
-#define RMT_CH1_TX_END_INT_ENA_M  (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S)
-#define RMT_CH1_TX_END_INT_ENA_V  0x00000001U
-#define RMT_CH1_TX_END_INT_ENA_S  1
-/** RMT_CH2_RX_END_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for CH2_RX_END_INT.
- */
-#define RMT_CH2_RX_END_INT_ENA    (BIT(2))
-#define RMT_CH2_RX_END_INT_ENA_M  (RMT_CH2_RX_END_INT_ENA_V << RMT_CH2_RX_END_INT_ENA_S)
-#define RMT_CH2_RX_END_INT_ENA_V  0x00000001U
-#define RMT_CH2_RX_END_INT_ENA_S  2
-/** RMT_CH3_RX_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for CH3_RX_END_INT.
- */
-#define RMT_CH3_RX_END_INT_ENA    (BIT(3))
-#define RMT_CH3_RX_END_INT_ENA_M  (RMT_CH3_RX_END_INT_ENA_V << RMT_CH3_RX_END_INT_ENA_S)
-#define RMT_CH3_RX_END_INT_ENA_V  0x00000001U
-#define RMT_CH3_RX_END_INT_ENA_S  3
-/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for CH$n_ERR_INT.
- */
-#define RMT_CH0_ERR_INT_ENA    (BIT(4))
-#define RMT_CH0_ERR_INT_ENA_M  (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S)
-#define RMT_CH0_ERR_INT_ENA_V  0x00000001U
-#define RMT_CH0_ERR_INT_ENA_S  4
-/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for CH$n_ERR_INT.
- */
-#define RMT_CH1_ERR_INT_ENA    (BIT(5))
-#define RMT_CH1_ERR_INT_ENA_M  (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S)
-#define RMT_CH1_ERR_INT_ENA_V  0x00000001U
-#define RMT_CH1_ERR_INT_ENA_S  5
-/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for CH$n_ERR_INT.
- */
-#define RMT_CH2_ERR_INT_ENA    (BIT(6))
-#define RMT_CH2_ERR_INT_ENA_M  (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S)
-#define RMT_CH2_ERR_INT_ENA_V  0x00000001U
-#define RMT_CH2_ERR_INT_ENA_S  6
-/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for CH$n_ERR_INT.
- */
-#define RMT_CH3_ERR_INT_ENA    (BIT(7))
-#define RMT_CH3_ERR_INT_ENA_M  (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S)
-#define RMT_CH3_ERR_INT_ENA_V  0x00000001U
-#define RMT_CH3_ERR_INT_ENA_S  7
-/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for CH0_TX_THR_EVENT_INT.
- */
-#define RMT_CH0_TX_THR_EVENT_INT_ENA    (BIT(8))
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_M  (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S)
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_V  0x00000001U
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_S  8
-/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for CH1_TX_THR_EVENT_INT.
- */
-#define RMT_CH1_TX_THR_EVENT_INT_ENA    (BIT(9))
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_M  (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S)
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_V  0x00000001U
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_S  9
-/** RMT_CH2_RX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for CH2_RX_THR_EVENT_INT.
- */
-#define RMT_CH2_RX_THR_EVENT_INT_ENA    (BIT(10))
-#define RMT_CH2_RX_THR_EVENT_INT_ENA_M  (RMT_CH2_RX_THR_EVENT_INT_ENA_V << RMT_CH2_RX_THR_EVENT_INT_ENA_S)
-#define RMT_CH2_RX_THR_EVENT_INT_ENA_V  0x00000001U
-#define RMT_CH2_RX_THR_EVENT_INT_ENA_S  10
-/** RMT_CH3_RX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for CH3_RX_THR_EVENT_INT.
- */
-#define RMT_CH3_RX_THR_EVENT_INT_ENA    (BIT(11))
-#define RMT_CH3_RX_THR_EVENT_INT_ENA_M  (RMT_CH3_RX_THR_EVENT_INT_ENA_V << RMT_CH3_RX_THR_EVENT_INT_ENA_S)
-#define RMT_CH3_RX_THR_EVENT_INT_ENA_V  0x00000001U
-#define RMT_CH3_RX_THR_EVENT_INT_ENA_S  11
-/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for CH0_TX_LOOP_INT.
- */
-#define RMT_CH0_TX_LOOP_INT_ENA    (BIT(12))
-#define RMT_CH0_TX_LOOP_INT_ENA_M  (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S)
-#define RMT_CH0_TX_LOOP_INT_ENA_V  0x00000001U
-#define RMT_CH0_TX_LOOP_INT_ENA_S  12
-/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for CH1_TX_LOOP_INT.
- */
-#define RMT_CH1_TX_LOOP_INT_ENA    (BIT(13))
-#define RMT_CH1_TX_LOOP_INT_ENA_M  (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S)
-#define RMT_CH1_TX_LOOP_INT_ENA_V  0x00000001U
-#define RMT_CH1_TX_LOOP_INT_ENA_S  13
-
-/** RMT_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x44)
-/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear theCH0_TX_END_INT interrupt.
- */
-#define RMT_CH0_TX_END_INT_CLR    (BIT(0))
-#define RMT_CH0_TX_END_INT_CLR_M  (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S)
-#define RMT_CH0_TX_END_INT_CLR_V  0x00000001U
-#define RMT_CH0_TX_END_INT_CLR_S  0
-/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear theCH1_TX_END_INT interrupt.
- */
-#define RMT_CH1_TX_END_INT_CLR    (BIT(1))
-#define RMT_CH1_TX_END_INT_CLR_M  (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S)
-#define RMT_CH1_TX_END_INT_CLR_V  0x00000001U
-#define RMT_CH1_TX_END_INT_CLR_S  1
-/** RMT_CH2_RX_END_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear theCH2_RX_END_INT interrupt.
- */
-#define RMT_CH2_RX_END_INT_CLR    (BIT(2))
-#define RMT_CH2_RX_END_INT_CLR_M  (RMT_CH2_RX_END_INT_CLR_V << RMT_CH2_RX_END_INT_CLR_S)
-#define RMT_CH2_RX_END_INT_CLR_V  0x00000001U
-#define RMT_CH2_RX_END_INT_CLR_S  2
-/** RMT_CH3_RX_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear theCH3_RX_END_INT interrupt.
- */
-#define RMT_CH3_RX_END_INT_CLR    (BIT(3))
-#define RMT_CH3_RX_END_INT_CLR_M  (RMT_CH3_RX_END_INT_CLR_V << RMT_CH3_RX_END_INT_CLR_S)
-#define RMT_CH3_RX_END_INT_CLR_V  0x00000001U
-#define RMT_CH3_RX_END_INT_CLR_S  3
-/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear theCH$n_ERR_INT interrupt.
- */
-#define RMT_CH0_ERR_INT_CLR    (BIT(4))
-#define RMT_CH0_ERR_INT_CLR_M  (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S)
-#define RMT_CH0_ERR_INT_CLR_V  0x00000001U
-#define RMT_CH0_ERR_INT_CLR_S  4
-/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear theCH$n_ERR_INT interrupt.
- */
-#define RMT_CH1_ERR_INT_CLR    (BIT(5))
-#define RMT_CH1_ERR_INT_CLR_M  (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S)
-#define RMT_CH1_ERR_INT_CLR_V  0x00000001U
-#define RMT_CH1_ERR_INT_CLR_S  5
-/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear theCH$n_ERR_INT interrupt.
- */
-#define RMT_CH2_ERR_INT_CLR    (BIT(6))
-#define RMT_CH2_ERR_INT_CLR_M  (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S)
-#define RMT_CH2_ERR_INT_CLR_V  0x00000001U
-#define RMT_CH2_ERR_INT_CLR_S  6
-/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear theCH$n_ERR_INT interrupt.
- */
-#define RMT_CH3_ERR_INT_CLR    (BIT(7))
-#define RMT_CH3_ERR_INT_CLR_M  (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S)
-#define RMT_CH3_ERR_INT_CLR_V  0x00000001U
-#define RMT_CH3_ERR_INT_CLR_S  7
-/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
- */
-#define RMT_CH0_TX_THR_EVENT_INT_CLR    (BIT(8))
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_M  (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S)
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_V  0x00000001U
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_S  8
-/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
- */
-#define RMT_CH1_TX_THR_EVENT_INT_CLR    (BIT(9))
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_M  (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S)
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_V  0x00000001U
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_S  9
-/** RMT_CH2_RX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
- */
-#define RMT_CH2_RX_THR_EVENT_INT_CLR    (BIT(10))
-#define RMT_CH2_RX_THR_EVENT_INT_CLR_M  (RMT_CH2_RX_THR_EVENT_INT_CLR_V << RMT_CH2_RX_THR_EVENT_INT_CLR_S)
-#define RMT_CH2_RX_THR_EVENT_INT_CLR_V  0x00000001U
-#define RMT_CH2_RX_THR_EVENT_INT_CLR_S  10
-/** RMT_CH3_RX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.
- */
-#define RMT_CH3_RX_THR_EVENT_INT_CLR    (BIT(11))
-#define RMT_CH3_RX_THR_EVENT_INT_CLR_M  (RMT_CH3_RX_THR_EVENT_INT_CLR_V << RMT_CH3_RX_THR_EVENT_INT_CLR_S)
-#define RMT_CH3_RX_THR_EVENT_INT_CLR_V  0x00000001U
-#define RMT_CH3_RX_THR_EVENT_INT_CLR_S  11
-/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear theCH0_TX_LOOP_INT interrupt.
- */
-#define RMT_CH0_TX_LOOP_INT_CLR    (BIT(12))
-#define RMT_CH0_TX_LOOP_INT_CLR_M  (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S)
-#define RMT_CH0_TX_LOOP_INT_CLR_V  0x00000001U
-#define RMT_CH0_TX_LOOP_INT_CLR_S  12
-/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear theCH1_TX_LOOP_INT interrupt.
- */
-#define RMT_CH1_TX_LOOP_INT_CLR    (BIT(13))
-#define RMT_CH1_TX_LOOP_INT_CLR_M  (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S)
-#define RMT_CH1_TX_LOOP_INT_CLR_V  0x00000001U
-#define RMT_CH1_TX_LOOP_INT_CLR_S  13
-
-/** RMT_CH0CARRIER_DUTY_REG register
- *  Channel 0 duty cycle configuration register
- */
-#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x48)
-/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64;
- *  This register is used to configure carrier wave 's low level clock period for
- *  CHANNEL0.
- */
-#define RMT_CARRIER_LOW_CH0    0x0000FFFFU
-#define RMT_CARRIER_LOW_CH0_M  (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S)
-#define RMT_CARRIER_LOW_CH0_V  0x0000FFFFU
-#define RMT_CARRIER_LOW_CH0_S  0
-/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64;
- *  This register is used to configure carrier wave 's high level clock period for
- *  CHANNEL0.
- */
-#define RMT_CARRIER_HIGH_CH0    0x0000FFFFU
-#define RMT_CARRIER_HIGH_CH0_M  (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S)
-#define RMT_CARRIER_HIGH_CH0_V  0x0000FFFFU
-#define RMT_CARRIER_HIGH_CH0_S  16
-
-/** RMT_CH1CARRIER_DUTY_REG register
- *  Channel 1 duty cycle configuration register
- */
-#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x4c)
-/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64;
- *  This register is used to configure carrier wave 's low level clock period for
- *  CHANNEL1.
- */
-#define RMT_CARRIER_LOW_CH1    0x0000FFFFU
-#define RMT_CARRIER_LOW_CH1_M  (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S)
-#define RMT_CARRIER_LOW_CH1_V  0x0000FFFFU
-#define RMT_CARRIER_LOW_CH1_S  0
-/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64;
- *  This register is used to configure carrier wave 's high level clock period for
- *  CHANNEL1.
- */
-#define RMT_CARRIER_HIGH_CH1    0x0000FFFFU
-#define RMT_CARRIER_HIGH_CH1_M  (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S)
-#define RMT_CARRIER_HIGH_CH1_V  0x0000FFFFU
-#define RMT_CARRIER_HIGH_CH1_S  16
-
-/** RMT_CH2_RX_CARRIER_RM_REG register
- *  Channel 2 carrier remove register
- */
-#define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x50)
-/** RMT_CARRIER_LOW_THRES_CH2 : R/W; bitpos: [15:0]; default: 0;
- *  The low level period in a carrier modulation mode is
- *  (REG_RMT_REG_CARRIER_LOW_THRES_CH2 + 1) for channel 2.
- */
-#define RMT_CARRIER_LOW_THRES_CH2    0x0000FFFFU
-#define RMT_CARRIER_LOW_THRES_CH2_M  (RMT_CARRIER_LOW_THRES_CH2_V << RMT_CARRIER_LOW_THRES_CH2_S)
-#define RMT_CARRIER_LOW_THRES_CH2_V  0x0000FFFFU
-#define RMT_CARRIER_LOW_THRES_CH2_S  0
-/** RMT_CARRIER_HIGH_THRES_CH2 : R/W; bitpos: [31:16]; default: 0;
- *  The high level period in a carrier modulation mode is
- *  (REG_RMT_REG_CARRIER_HIGH_THRES_CH2 + 1) for channel 2.
- */
-#define RMT_CARRIER_HIGH_THRES_CH2    0x0000FFFFU
-#define RMT_CARRIER_HIGH_THRES_CH2_M  (RMT_CARRIER_HIGH_THRES_CH2_V << RMT_CARRIER_HIGH_THRES_CH2_S)
-#define RMT_CARRIER_HIGH_THRES_CH2_V  0x0000FFFFU
-#define RMT_CARRIER_HIGH_THRES_CH2_S  16
-
-/** RMT_CH3_RX_CARRIER_RM_REG register
- *  Channel 3 carrier remove register
- */
-#define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x54)
-/** RMT_CARRIER_LOW_THRES_CH3 : R/W; bitpos: [15:0]; default: 0;
- *  The low level period in a carrier modulation mode is
- *  (REG_RMT_REG_CARRIER_LOW_THRES_CH3 + 1) for channel 3.
- */
-#define RMT_CARRIER_LOW_THRES_CH3    0x0000FFFFU
-#define RMT_CARRIER_LOW_THRES_CH3_M  (RMT_CARRIER_LOW_THRES_CH3_V << RMT_CARRIER_LOW_THRES_CH3_S)
-#define RMT_CARRIER_LOW_THRES_CH3_V  0x0000FFFFU
-#define RMT_CARRIER_LOW_THRES_CH3_S  0
-/** RMT_CARRIER_HIGH_THRES_CH3 : R/W; bitpos: [31:16]; default: 0;
- *  The high level period in a carrier modulation mode is
- *  (REG_RMT_REG_CARRIER_HIGH_THRES_CH3 + 1) for channel 3.
- */
-#define RMT_CARRIER_HIGH_THRES_CH3    0x0000FFFFU
-#define RMT_CARRIER_HIGH_THRES_CH3_M  (RMT_CARRIER_HIGH_THRES_CH3_V << RMT_CARRIER_HIGH_THRES_CH3_S)
-#define RMT_CARRIER_HIGH_THRES_CH3_V  0x0000FFFFU
-#define RMT_CARRIER_HIGH_THRES_CH3_S  16
-
-/** RMT_CH0_TX_LIM_REG register
- *  Channel 0 Tx event configuration register
- */
-#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x58)
-/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128;
- *  This register is used to configure the maximum entries that CHANNEL0 can send out.
- */
-#define RMT_TX_LIM_CH0    0x000001FFU
-#define RMT_TX_LIM_CH0_M  (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S)
-#define RMT_TX_LIM_CH0_V  0x000001FFU
-#define RMT_TX_LIM_CH0_S  0
-/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0;
- *  This register is used to configure the maximum loop count when tx_conti_mode is
- *  valid.
- */
-#define RMT_TX_LOOP_NUM_CH0    0x000003FFU
-#define RMT_TX_LOOP_NUM_CH0_M  (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S)
-#define RMT_TX_LOOP_NUM_CH0_V  0x000003FFU
-#define RMT_TX_LOOP_NUM_CH0_S  9
-/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0;
- *  This register is the enabled bit for loop count.
- */
-#define RMT_TX_LOOP_CNT_EN_CH0    (BIT(19))
-#define RMT_TX_LOOP_CNT_EN_CH0_M  (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S)
-#define RMT_TX_LOOP_CNT_EN_CH0_V  0x00000001U
-#define RMT_TX_LOOP_CNT_EN_CH0_S  19
-/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0;
- *  This register is used to reset the loop count when tx_conti_mode is valid.
- */
-#define RMT_LOOP_COUNT_RESET_CH0    (BIT(20))
-#define RMT_LOOP_COUNT_RESET_CH0_M  (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S)
-#define RMT_LOOP_COUNT_RESET_CH0_V  0x00000001U
-#define RMT_LOOP_COUNT_RESET_CH0_S  20
-/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0;
- *  This bit is used to enable the loop send stop function after the loop counter
- *  counts to  loop number for CHANNEL0.
- */
-#define RMT_LOOP_STOP_EN_CH0    (BIT(21))
-#define RMT_LOOP_STOP_EN_CH0_M  (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S)
-#define RMT_LOOP_STOP_EN_CH0_V  0x00000001U
-#define RMT_LOOP_STOP_EN_CH0_S  21
-
-/** RMT_CH1_TX_LIM_REG register
- *  Channel 1 Tx event configuration register
- */
-#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x5c)
-/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128;
- *  This register is used to configure the maximum entries that CHANNEL1 can send out.
- */
-#define RMT_TX_LIM_CH1    0x000001FFU
-#define RMT_TX_LIM_CH1_M  (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S)
-#define RMT_TX_LIM_CH1_V  0x000001FFU
-#define RMT_TX_LIM_CH1_S  0
-/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0;
- *  This register is used to configure the maximum loop count when tx_conti_mode is
- *  valid.
- */
-#define RMT_TX_LOOP_NUM_CH1    0x000003FFU
-#define RMT_TX_LOOP_NUM_CH1_M  (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S)
-#define RMT_TX_LOOP_NUM_CH1_V  0x000003FFU
-#define RMT_TX_LOOP_NUM_CH1_S  9
-/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0;
- *  This register is the enabled bit for loop count.
- */
-#define RMT_TX_LOOP_CNT_EN_CH1    (BIT(19))
-#define RMT_TX_LOOP_CNT_EN_CH1_M  (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S)
-#define RMT_TX_LOOP_CNT_EN_CH1_V  0x00000001U
-#define RMT_TX_LOOP_CNT_EN_CH1_S  19
-/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0;
- *  This register is used to reset the loop count when tx_conti_mode is valid.
- */
-#define RMT_LOOP_COUNT_RESET_CH1    (BIT(20))
-#define RMT_LOOP_COUNT_RESET_CH1_M  (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S)
-#define RMT_LOOP_COUNT_RESET_CH1_V  0x00000001U
-#define RMT_LOOP_COUNT_RESET_CH1_S  20
-/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0;
- *  This bit is used to enable the loop send stop function after the loop counter
- *  counts to  loop number for CHANNEL1.
- */
-#define RMT_LOOP_STOP_EN_CH1    (BIT(21))
-#define RMT_LOOP_STOP_EN_CH1_M  (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S)
-#define RMT_LOOP_STOP_EN_CH1_V  0x00000001U
-#define RMT_LOOP_STOP_EN_CH1_S  21
-
-/** RMT_CH2_RX_LIM_REG register
- *  Channel 2 Rx event configuration register
- */
-#define RMT_CH2_RX_LIM_REG (DR_REG_RMT_BASE + 0x60)
-/** RMT_RX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128;
- *  This register is used to configure the maximum entries that CHANNEL2 can receive.
- */
-#define RMT_RX_LIM_CH2    0x000001FFU
-#define RMT_RX_LIM_CH2_M  (RMT_RX_LIM_CH2_V << RMT_RX_LIM_CH2_S)
-#define RMT_RX_LIM_CH2_V  0x000001FFU
-#define RMT_RX_LIM_CH2_S  0
-
-/** RMT_CH3_RX_LIM_REG register
- *  Channel 3 Rx event configuration register
- */
-#define RMT_CH3_RX_LIM_REG (DR_REG_RMT_BASE + 0x64)
-/** RMT_RX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128;
- *  This register is used to configure the maximum entries that CHANNEL3 can receive.
- */
-#define RMT_RX_LIM_CH3    0x000001FFU
-#define RMT_RX_LIM_CH3_M  (RMT_RX_LIM_CH3_V << RMT_RX_LIM_CH3_S)
-#define RMT_RX_LIM_CH3_V  0x000001FFU
-#define RMT_RX_LIM_CH3_S  0
-
-/** RMT_SYS_CONF_REG register
- *  RMT apb configuration register
- */
-#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x68)
-/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0;
- *  1'h1: access memory directly.   1'h0: access memory by FIFO.
- */
-#define RMT_APB_FIFO_MASK    (BIT(0))
-#define RMT_APB_FIFO_MASK_M  (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S)
-#define RMT_APB_FIFO_MASK_V  0x00000001U
-#define RMT_APB_FIFO_MASK_S  0
-/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable the clock for RMT memory.
- */
-#define RMT_MEM_CLK_FORCE_ON    (BIT(1))
-#define RMT_MEM_CLK_FORCE_ON_M  (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S)
-#define RMT_MEM_CLK_FORCE_ON_V  0x00000001U
-#define RMT_MEM_CLK_FORCE_ON_S  1
-/** RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to power down RMT memory.
- */
-#define RMT_MEM_FORCE_PD    (BIT(2))
-#define RMT_MEM_FORCE_PD_M  (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S)
-#define RMT_MEM_FORCE_PD_V  0x00000001U
-#define RMT_MEM_FORCE_PD_S  2
-/** RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0;
- *  1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
- *  when RMT is in light sleep mode.
- */
-#define RMT_MEM_FORCE_PU    (BIT(3))
-#define RMT_MEM_FORCE_PU_M  (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S)
-#define RMT_MEM_FORCE_PU_V  0x00000001U
-#define RMT_MEM_FORCE_PU_S  3
-/** RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1;
- *  the integral part of the fractional divisor
- */
-#define RMT_SCLK_DIV_NUM    0x000000FFU
-#define RMT_SCLK_DIV_NUM_M  (RMT_SCLK_DIV_NUM_V << RMT_SCLK_DIV_NUM_S)
-#define RMT_SCLK_DIV_NUM_V  0x000000FFU
-#define RMT_SCLK_DIV_NUM_S  4
-/** RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0;
- *  the numerator of the fractional part of the fractional divisor
- */
-#define RMT_SCLK_DIV_A    0x0000003FU
-#define RMT_SCLK_DIV_A_M  (RMT_SCLK_DIV_A_V << RMT_SCLK_DIV_A_S)
-#define RMT_SCLK_DIV_A_V  0x0000003FU
-#define RMT_SCLK_DIV_A_S  12
-/** RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0;
- *  the denominator of the fractional part of the fractional divisor
- */
-#define RMT_SCLK_DIV_B    0x0000003FU
-#define RMT_SCLK_DIV_B_M  (RMT_SCLK_DIV_B_V << RMT_SCLK_DIV_B_S)
-#define RMT_SCLK_DIV_B_V  0x0000003FU
-#define RMT_SCLK_DIV_B_S  18
-/** RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1;
- *  choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL
- */
-#define RMT_SCLK_SEL    0x00000003U
-#define RMT_SCLK_SEL_M  (RMT_SCLK_SEL_V << RMT_SCLK_SEL_S)
-#define RMT_SCLK_SEL_V  0x00000003U
-#define RMT_SCLK_SEL_S  24
-/** RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1;
- *  rmt_sclk switch
- */
-#define RMT_SCLK_ACTIVE    (BIT(26))
-#define RMT_SCLK_ACTIVE_M  (RMT_SCLK_ACTIVE_V << RMT_SCLK_ACTIVE_S)
-#define RMT_SCLK_ACTIVE_V  0x00000001U
-#define RMT_SCLK_ACTIVE_S  26
-/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
- *  Power down the drive clock of registers
- */
-#define RMT_CLK_EN    (BIT(31))
-#define RMT_CLK_EN_M  (RMT_CLK_EN_V << RMT_CLK_EN_S)
-#define RMT_CLK_EN_V  0x00000001U
-#define RMT_CLK_EN_S  31
-
-/** RMT_TX_SIM_REG register
- *  RMT TX synchronous register
- */
-#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x6c)
-/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable CHANNEL0 to start sending data synchronously with other
- *  enabled channels.
- */
-#define RMT_TX_SIM_CH0    (BIT(0))
-#define RMT_TX_SIM_CH0_M  (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S)
-#define RMT_TX_SIM_CH0_V  0x00000001U
-#define RMT_TX_SIM_CH0_S  0
-/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable CHANNEL1 to start sending data synchronously with other
- *  enabled channels.
- */
-#define RMT_TX_SIM_CH1    (BIT(1))
-#define RMT_TX_SIM_CH1_M  (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S)
-#define RMT_TX_SIM_CH1_V  0x00000001U
-#define RMT_TX_SIM_CH1_S  1
-/** RMT_TX_SIM_EN : R/W; bitpos: [2]; default: 0;
- *  This register is used to enable multiple of channels to start sending data
- *  synchronously.
- */
-#define RMT_TX_SIM_EN    (BIT(2))
-#define RMT_TX_SIM_EN_M  (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S)
-#define RMT_TX_SIM_EN_V  0x00000001U
-#define RMT_TX_SIM_EN_S  2
-
-/** RMT_REF_CNT_RST_REG register
- *  RMT clock divider reset register
- */
-#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x70)
-/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0;
- *  This register is used to reset the clock divider of CHANNEL0.
- */
-#define RMT_REF_CNT_RST_CH0    (BIT(0))
-#define RMT_REF_CNT_RST_CH0_M  (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S)
-#define RMT_REF_CNT_RST_CH0_V  0x00000001U
-#define RMT_REF_CNT_RST_CH0_S  0
-/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0;
- *  This register is used to reset the clock divider of CHANNEL1.
- */
-#define RMT_REF_CNT_RST_CH1    (BIT(1))
-#define RMT_REF_CNT_RST_CH1_M  (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S)
-#define RMT_REF_CNT_RST_CH1_V  0x00000001U
-#define RMT_REF_CNT_RST_CH1_S  1
-/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0;
- *  This register is used to reset the clock divider of CHANNEL2.
- */
-#define RMT_REF_CNT_RST_CH2    (BIT(2))
-#define RMT_REF_CNT_RST_CH2_M  (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S)
-#define RMT_REF_CNT_RST_CH2_V  0x00000001U
-#define RMT_REF_CNT_RST_CH2_S  2
-/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0;
- *  This register is used to reset the clock divider of CHANNEL3.
- */
-#define RMT_REF_CNT_RST_CH3    (BIT(3))
-#define RMT_REF_CNT_RST_CH3_M  (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S)
-#define RMT_REF_CNT_RST_CH3_V  0x00000001U
-#define RMT_REF_CNT_RST_CH3_S  3
-
-/** RMT_DATE_REG register
- *  RMT version register
- */
-#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc)
-/** RMT_DATE : R/W; bitpos: [27:0]; default: 34636307;
- *  This is the version register.
- */
-#define RMT_DATE    0x0FFFFFFFU
-#define RMT_DATE_M  (RMT_DATE_V << RMT_DATE_S)
-#define RMT_DATE_V  0x0FFFFFFFU
-#define RMT_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/rmt_struct.h b/components/soc/esp32c5/beta3/include/soc/rmt_struct.h
deleted file mode 100644
index 02d2138a80..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/rmt_struct.h
+++ /dev/null
@@ -1,802 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO R/W registers */
-/** Type of chndata register
- *  The read and write  data register for CHANNELn by apb fifo access.
- */
-typedef union {
-    struct {
-        /** chndata : HRO; bitpos: [31:0]; default: 0;
-         *  Read and write data for channel n via APB FIFO.
-         */
-        uint32_t chndata:32;
-    };
-    uint32_t val;
-} rmt_chndata_reg_t;
-
-/** Type of chmdata register
- *  The read and write  data register for CHANNELn by apb fifo access.
- */
-typedef union {
-    struct {
-        /** chmdata : HRO; bitpos: [31:0]; default: 0;
-         *  Read and write data for channel n via APB FIFO.
-         */
-        uint32_t chmdata:32;
-    };
-    uint32_t val;
-} rmt_chmdata_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of chnconf0 register
- *  Channel n configure register 0
- */
-typedef union {
-    struct {
-        /** tx_start_chn : WT; bitpos: [0]; default: 0;
-         *  Set this bit to start sending data on CHANNELn.
-         */
-        uint32_t tx_start_chn:1;
-        /** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset read ram address for CHANNELn by accessing transmitter.
-         */
-        uint32_t mem_rd_rst_chn:1;
-        /** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
-         *  Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo.
-         */
-        uint32_t apb_mem_rst_chn:1;
-        /** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to restart transmission  from the first data to the last data in
-         *  CHANNELn.
-         */
-        uint32_t tx_conti_mode_chn:1;
-        /** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
-         *  This is the channel n enable bit for wraparound mode: it will resume sending at the
-         *  start when the data to be sent is more than its memory size.
-         */
-        uint32_t mem_tx_wrap_en_chn:1;
-        /** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
-         *  This bit configures the level of output signal in CHANNELn when the latter is in
-         *  IDLE state.
-         */
-        uint32_t idle_out_lv_chn:1;
-        /** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
-         *  This is the output enable-control bit for CHANNELn in IDLE state.
-         */
-        uint32_t idle_out_en_chn:1;
-        /** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
-         *  Set this bit to stop the transmitter of CHANNELn sending data out.
-         */
-        uint32_t tx_stop_chn:1;
-        /** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
-         *  This register is used to configure the divider for clock of CHANNELn.
-         */
-        uint32_t div_cnt_chn:8;
-        /** mem_size_chn : R/W; bitpos: [18:16]; default: 1;
-         *  This register is used to configure the maximum size of memory allocated to CHANNELn.
-         */
-        uint32_t mem_size_chn:3;
-        uint32_t reserved_19:1;
-        /** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
-         *  1: Add carrier modulation on the output signal only at the send data state for
-         *  CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn.
-         *  Only valid when RMT_CARRIER_EN_CHn is 1.
-         */
-        uint32_t carrier_eff_en_chn:1;
-        /** carrier_en_chn : R/W; bitpos: [21]; default: 1;
-         *  This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier
-         *  modulation in the output signal. 0: No carrier modulation in sig_out.
-         */
-        uint32_t carrier_en_chn:1;
-        /** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
-         *  This bit is used to configure the position of carrier wave for CHANNELn.
-         *
-         *  1'h0: add carrier wave on low level.
-         *
-         *  1'h1: add carrier wave on high level.
-         */
-        uint32_t carrier_out_lv_chn:1;
-        uint32_t reserved_23:1;
-        /** conf_update_chn : WT; bitpos: [24]; default: 0;
-         *  synchronization bit for CHANNELn
-         */
-        uint32_t conf_update_chn:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} rmt_chnconf0_reg_t;
-
-/** Type of chmconf0 register
- *  Channel m configure register 0
- */
-typedef union {
-    struct {
-        /** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
-         *  This register is used to configure the divider for clock of CHANNELm.
-         */
-        uint32_t div_cnt_chm:8;
-        /** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
-         *  When no edge is detected on the input signal and continuous clock cycles is longer
-         *  than this register value, received process is finished.
-         */
-        uint32_t idle_thres_chm:15;
-        /** mem_size_chm : R/W; bitpos: [25:23]; default: 1;
-         *  This register is used to configure the maximum size of memory allocated to CHANNELm.
-         */
-        uint32_t mem_size_chm:3;
-        uint32_t reserved_26:2;
-        /** carrier_en_chm : R/W; bitpos: [28]; default: 1;
-         *  This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
-         *  modulation in the output signal. 0: No carrier modulation in sig_out.
-         */
-        uint32_t carrier_en_chm:1;
-        /** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
-         *  This bit is used to configure the position of carrier wave for CHANNELm.
-         *
-         *  1'h0: add carrier wave on low level.
-         *
-         *  1'h1: add carrier wave on high level.
-         */
-        uint32_t carrier_out_lv_chm:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} rmt_chmconf0_reg_t;
-
-/** Type of chmconf1 register
- *  Channel m configure register 1
- */
-typedef union {
-    struct {
-        /** rx_en_chm : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable receiver to receive data on CHANNELm.
-         */
-        uint32_t rx_en_chm:1;
-        /** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset write ram address for CHANNELm by accessing receiver.
-         */
-        uint32_t mem_wr_rst_chm:1;
-        /** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
-         *  Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
-         */
-        uint32_t apb_mem_rst_chm:1;
-        /** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
-         *  This register marks the ownership of CHANNELm's ram block.
-         *
-         *  1'h1: Receiver is using the ram.
-         *
-         *  1'h0: APB bus is using the ram.
-         */
-        uint32_t mem_owner_chm:1;
-        /** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
-         *  This is the receive filter's enable bit for CHANNELm.
-         */
-        uint32_t rx_filter_en_chm:1;
-        /** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
-         *  Ignores the input pulse when its width is smaller than this register value in APB
-         *  clock periods (in receive mode).
-         */
-        uint32_t rx_filter_thres_chm:8;
-        /** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
-         *  This is the channel m enable bit for wraparound mode: it will resume receiving at
-         *  the start when the data to be received is more than its memory size.
-         */
-        uint32_t mem_rx_wrap_en_chm:1;
-        uint32_t reserved_14:1;
-        /** conf_update_chm : WT; bitpos: [15]; default: 0;
-         *  synchronization bit for CHANNELm
-         */
-        uint32_t conf_update_chm:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} rmt_chmconf1_reg_t;
-
-/** Type of sys_conf register
- *  RMT apb configuration register
- */
-typedef union {
-    struct {
-        /** apb_fifo_mask : R/W; bitpos: [0]; default: 0;
-         *  1'h1: access memory directly.   1'h0: access memory by FIFO.
-         */
-        uint32_t apb_fifo_mask:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable the clock for RMT memory.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to power down RMT memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [3]; default: 0;
-         *  1: Disable RMT memory light sleep power down function. 0: Power down RMT memory
-         *  when RMT is in light sleep mode.
-         */
-        uint32_t mem_force_pu:1;
-        /** sclk_div_num : R/W; bitpos: [11:4]; default: 1;
-         *  the integral part of the fractional divisor
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_div_a : R/W; bitpos: [17:12]; default: 0;
-         *  the numerator of the fractional part of the fractional divisor
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_b : R/W; bitpos: [23:18]; default: 0;
-         *  the denominator of the fractional part of the fractional divisor
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_sel : R/W; bitpos: [25:24]; default: 1;
-         *  choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL
-         */
-        uint32_t sclk_sel:2;
-        /** sclk_active : R/W; bitpos: [26]; default: 1;
-         *  rmt_sclk switch
-         */
-        uint32_t sclk_active:1;
-        uint32_t reserved_27:4;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0:
-         *  Power down the drive clock of registers
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} rmt_sys_conf_reg_t;
-
-/** Type of ref_cnt_rst register
- *  RMT clock divider reset register
- */
-typedef union {
-    struct {
-        /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0;
-         *  This register is used to reset the clock divider of CHANNEL0.
-         */
-        uint32_t ref_cnt_rst_ch0:1;
-        /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0;
-         *  This register is used to reset the clock divider of CHANNEL1.
-         */
-        uint32_t ref_cnt_rst_ch1:1;
-        /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0;
-         *  This register is used to reset the clock divider of CHANNEL2.
-         */
-        uint32_t ref_cnt_rst_ch2:1;
-        /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0;
-         *  This register is used to reset the clock divider of CHANNEL3.
-         */
-        uint32_t ref_cnt_rst_ch3:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} rmt_ref_cnt_rst_reg_t;
-
-
-/** Group: Status registers */
-/** Type of chnstatus register
- *  Channel n status register
- */
-typedef union {
-    struct {
-        /** mem_raddr_ex_chn : RO; bitpos: [8:0]; default: 0;
-         *  This register records the memory address offset when transmitter of CHANNELn is
-         *  using the RAM.
-         */
-        uint32_t mem_raddr_ex_chn:9;
-        /** state_chn : RO; bitpos: [11:9]; default: 0;
-         *  This register records the FSM status of CHANNELn.
-         */
-        uint32_t state_chn:3;
-        /** apb_mem_waddr_chn : RO; bitpos: [20:12]; default: 0;
-         *  This register records the memory address offset when writes RAM over APB bus.
-         */
-        uint32_t apb_mem_waddr_chn:9;
-        /** apb_mem_rd_err_chn : RO; bitpos: [21]; default: 0;
-         *  This status bit will be set if the offset address out of memory size when reading
-         *  via APB bus.
-         */
-        uint32_t apb_mem_rd_err_chn:1;
-        /** mem_empty_chn : RO; bitpos: [22]; default: 0;
-         *  This status bit will be set when the data to be set is more than memory size and
-         *  the wraparound mode is disabled.
-         */
-        uint32_t mem_empty_chn:1;
-        /** apb_mem_wr_err_chn : RO; bitpos: [23]; default: 0;
-         *  This status bit will be set if the offset address out of memory size when writes
-         *  via APB bus.
-         */
-        uint32_t apb_mem_wr_err_chn:1;
-        /** apb_mem_raddr_chn : RO; bitpos: [31:24]; default: 0;
-         *  This register records the memory address offset when reading RAM over APB bus.
-         */
-        uint32_t apb_mem_raddr_chn:8;
-    };
-    uint32_t val;
-} rmt_chnstatus_reg_t;
-
-/** Type of chmstatus register
- *  Channel m status register
- */
-typedef union {
-    struct {
-        /** mem_waddr_ex_chm : RO; bitpos: [8:0]; default: 0;
-         *  This register records the memory address offset when receiver of CHANNELm is using
-         *  the RAM.
-         */
-        uint32_t mem_waddr_ex_chm:9;
-        uint32_t reserved_9:3;
-        /** apb_mem_raddr_chm : RO; bitpos: [20:12]; default: 0;
-         *  This register records the memory address offset when reads RAM over APB bus.
-         */
-        uint32_t apb_mem_raddr_chm:9;
-        uint32_t reserved_21:1;
-        /** state_chm : RO; bitpos: [24:22]; default: 0;
-         *  This register records the FSM status of CHANNELm.
-         */
-        uint32_t state_chm:3;
-        /** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
-         *  This status bit will be set when the ownership of memory block is wrong.
-         */
-        uint32_t mem_owner_err_chm:1;
-        /** mem_full_chm : RO; bitpos: [26]; default: 0;
-         *  This status bit will be set if the receiver receives more data than the memory size.
-         */
-        uint32_t mem_full_chm:1;
-        /** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
-         *  This status bit will be set if the offset address out of memory size when reads via
-         *  APB bus.
-         */
-        uint32_t apb_mem_rd_err_chm:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} rmt_chmstatus_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The interrupt raw bit for CHANNEL0. Triggered when transmission done.
-         */
-        uint32_t ch0_tx_end_int_raw:1;
-        /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The interrupt raw bit for CHANNEL1. Triggered when transmission done.
-         */
-        uint32_t ch1_tx_end_int_raw:1;
-        /** ch2_rx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The interrupt raw bit for CHANNEL2. Triggered when reception done.
-         */
-        uint32_t ch2_rx_end_int_raw:1;
-        /** ch3_rx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The interrupt raw bit for CHANNEL3. Triggered when reception done.
-         */
-        uint32_t ch3_rx_end_int_raw:1;
-        /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
-         */
-        uint32_t ch0_err_int_raw:1;
-        /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
-         */
-        uint32_t ch1_err_int_raw:1;
-        /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
-         */
-        uint32_t ch2_err_int_raw:1;
-        /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The interrupt raw bit for CHANNEL$m. Triggered when error occurs.
-         */
-        uint32_t ch3_err_int_raw:1;
-        /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than
-         *  configured value.
-         */
-        uint32_t ch0_tx_thr_event_int_raw:1;
-        /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than
-         *  configured value.
-         */
-        uint32_t ch1_tx_thr_event_int_raw:1;
-        /** ch2_rx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than
-         *  configured value.
-         */
-        uint32_t ch2_rx_thr_event_int_raw:1;
-        /** ch3_rx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than
-         *  configured value.
-         */
-        uint32_t ch3_rx_thr_event_int_raw:1;
-        /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the
-         *  configured threshold value.
-         */
-        uint32_t ch0_tx_loop_int_raw:1;
-        /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the
-         *  configured threshold value.
-         */
-        uint32_t ch1_tx_loop_int_raw:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} rmt_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit for CH0_TX_END_INT.
-         */
-        uint32_t ch0_tx_end_int_st:1;
-        /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit for CH1_TX_END_INT.
-         */
-        uint32_t ch1_tx_end_int_st:1;
-        /** ch2_rx_end_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit for CH2_RX_END_INT.
-         */
-        uint32_t ch2_rx_end_int_st:1;
-        /** ch3_rx_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit for CH3_RX_END_INT.
-         */
-        uint32_t ch3_rx_end_int_st:1;
-        /** ch0_err_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked interrupt status bit for CH$n_ERR_INT.
-         */
-        uint32_t ch0_err_int_st:1;
-        /** ch1_err_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status bit for CH$n_ERR_INT.
-         */
-        uint32_t ch1_err_int_st:1;
-        /** ch2_err_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status bit for CH$n_ERR_INT.
-         */
-        uint32_t ch2_err_int_st:1;
-        /** ch3_err_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status bit for CH$n_ERR_INT.
-         */
-        uint32_t ch3_err_int_st:1;
-        /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
-         */
-        uint32_t ch0_tx_thr_event_int_st:1;
-        /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
-         */
-        uint32_t ch1_tx_thr_event_int_st:1;
-        /** ch2_rx_thr_event_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status bit for CH2_RX_THR_EVENT_INT.
-         */
-        uint32_t ch2_rx_thr_event_int_st:1;
-        /** ch3_rx_thr_event_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status bit for CH3_RX_THR_EVENT_INT.
-         */
-        uint32_t ch3_rx_thr_event_int_st:1;
-        /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status bit for CH0_TX_LOOP_INT.
-         */
-        uint32_t ch0_tx_loop_int_st:1;
-        /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked interrupt status bit for CH1_TX_LOOP_INT.
-         */
-        uint32_t ch1_tx_loop_int_st:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} rmt_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for CH0_TX_END_INT.
-         */
-        uint32_t ch0_tx_end_int_ena:1;
-        /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for CH1_TX_END_INT.
-         */
-        uint32_t ch1_tx_end_int_ena:1;
-        /** ch2_rx_end_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for CH2_RX_END_INT.
-         */
-        uint32_t ch2_rx_end_int_ena:1;
-        /** ch3_rx_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for CH3_RX_END_INT.
-         */
-        uint32_t ch3_rx_end_int_ena:1;
-        /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for CH$n_ERR_INT.
-         */
-        uint32_t ch0_err_int_ena:1;
-        /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for CH$n_ERR_INT.
-         */
-        uint32_t ch1_err_int_ena:1;
-        /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for CH$n_ERR_INT.
-         */
-        uint32_t ch2_err_int_ena:1;
-        /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for CH$n_ERR_INT.
-         */
-        uint32_t ch3_err_int_ena:1;
-        /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for CH0_TX_THR_EVENT_INT.
-         */
-        uint32_t ch0_tx_thr_event_int_ena:1;
-        /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for CH1_TX_THR_EVENT_INT.
-         */
-        uint32_t ch1_tx_thr_event_int_ena:1;
-        /** ch2_rx_thr_event_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The interrupt enable bit for CH2_RX_THR_EVENT_INT.
-         */
-        uint32_t ch2_rx_thr_event_int_ena:1;
-        /** ch3_rx_thr_event_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The interrupt enable bit for CH3_RX_THR_EVENT_INT.
-         */
-        uint32_t ch3_rx_thr_event_int_ena:1;
-        /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The interrupt enable bit for CH0_TX_LOOP_INT.
-         */
-        uint32_t ch0_tx_loop_int_ena:1;
-        /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The interrupt enable bit for CH1_TX_LOOP_INT.
-         */
-        uint32_t ch1_tx_loop_int_ena:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} rmt_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear theCH0_TX_END_INT interrupt.
-         */
-        uint32_t ch0_tx_end_int_clr:1;
-        /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear theCH1_TX_END_INT interrupt.
-         */
-        uint32_t ch1_tx_end_int_clr:1;
-        /** ch2_rx_end_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear theCH2_RX_END_INT interrupt.
-         */
-        uint32_t ch2_rx_end_int_clr:1;
-        /** ch3_rx_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear theCH3_RX_END_INT interrupt.
-         */
-        uint32_t ch3_rx_end_int_clr:1;
-        /** ch0_err_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear theCH$n_ERR_INT interrupt.
-         */
-        uint32_t ch0_err_int_clr:1;
-        /** ch1_err_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear theCH$n_ERR_INT interrupt.
-         */
-        uint32_t ch1_err_int_clr:1;
-        /** ch2_err_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear theCH$n_ERR_INT interrupt.
-         */
-        uint32_t ch2_err_int_clr:1;
-        /** ch3_err_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear theCH$n_ERR_INT interrupt.
-         */
-        uint32_t ch3_err_int_clr:1;
-        /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
-         */
-        uint32_t ch0_tx_thr_event_int_clr:1;
-        /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
-         */
-        uint32_t ch1_tx_thr_event_int_clr:1;
-        /** ch2_rx_thr_event_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
-         */
-        uint32_t ch2_rx_thr_event_int_clr:1;
-        /** ch3_rx_thr_event_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.
-         */
-        uint32_t ch3_rx_thr_event_int_clr:1;
-        /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear theCH0_TX_LOOP_INT interrupt.
-         */
-        uint32_t ch0_tx_loop_int_clr:1;
-        /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear theCH1_TX_LOOP_INT interrupt.
-         */
-        uint32_t ch1_tx_loop_int_clr:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} rmt_int_clr_reg_t;
-
-
-/** Group: Carrier wave duty cycle registers */
-/** Type of chncarrier_duty register
- *  Channel n duty cycle configuration register
- */
-typedef union {
-    struct {
-        /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
-         *  This register is used to configure carrier wave 's low level clock period for
-         *  CHANNELn.
-         */
-        uint32_t carrier_low_chn:16;
-        /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
-         *  This register is used to configure carrier wave 's high level clock period for
-         *  CHANNELn.
-         */
-        uint32_t carrier_high_chn:16;
-    };
-    uint32_t val;
-} rmt_chncarrier_duty_reg_t;
-
-/** Type of chm_rx_carrier_rm register
- *  Channel m carrier remove register
- */
-typedef union {
-    struct {
-        /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0;
-         *  The low level period in a carrier modulation mode is
-         *  (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m.
-         */
-        uint32_t carrier_low_thres_chm:16;
-        /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0;
-         *  The high level period in a carrier modulation mode is
-         *  (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m.
-         */
-        uint32_t carrier_high_thres_chm:16;
-    };
-    uint32_t val;
-} rmt_chm_rx_carrier_rm_reg_t;
-
-
-/** Group: Tx event configuration registers */
-/** Type of chn_tx_lim register
- *  Channel n Tx event configuration register
- */
-typedef union {
-    struct {
-        /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
-         *  This register is used to configure the maximum entries that CHANNELn can send out.
-         */
-        uint32_t tx_lim_chn:9;
-        /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
-         *  This register is used to configure the maximum loop count when tx_conti_mode is
-         *  valid.
-         */
-        uint32_t tx_loop_num_chn:10;
-        /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
-         *  This register is the enabled bit for loop count.
-         */
-        uint32_t tx_loop_cnt_en_chn:1;
-        /** loop_count_reset_chn : WT; bitpos: [20]; default: 0;
-         *  This register is used to reset the loop count when tx_conti_mode is valid.
-         */
-        uint32_t loop_count_reset_chn:1;
-        /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0;
-         *  This bit is used to enable the loop send stop function after the loop counter
-         *  counts to  loop number for CHANNELn.
-         */
-        uint32_t loop_stop_en_chn:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} rmt_chn_tx_lim_reg_t;
-
-/** Type of tx_sim register
- *  RMT TX synchronous register
- */
-typedef union {
-    struct {
-        /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable CHANNEL0 to start sending data synchronously with other
-         *  enabled channels.
-         */
-        uint32_t tx_sim_ch0:1;
-        /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable CHANNEL1 to start sending data synchronously with other
-         *  enabled channels.
-         */
-        uint32_t tx_sim_ch1:1;
-        /** tx_sim_en : R/W; bitpos: [2]; default: 0;
-         *  This register is used to enable multiple of channels to start sending data
-         *  synchronously.
-         */
-        uint32_t tx_sim_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} rmt_tx_sim_reg_t;
-
-
-/** Group: Rx event configuration registers */
-/** Type of chm_rx_lim register
- *  Channel m Rx event configuration register
- */
-typedef union {
-    struct {
-        /** rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
-         *  This register is used to configure the maximum entries that CHANNELm can receive.
-         */
-        uint32_t rx_lim_chm:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} rmt_chm_rx_lim_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  RMT version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 34636307;
-         *  This is the version register.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} rmt_date_reg_t;
-
-
-typedef struct rmt_dev_t {
-    volatile rmt_chndata_reg_t chndata[2];
-    volatile rmt_chmdata_reg_t chmdata[2];
-    volatile rmt_chnconf0_reg_t chnconf0[2];
-    volatile struct {
-        rmt_chmconf0_reg_t conf0;
-        rmt_chmconf1_reg_t conf1;
-    } chmconf[2];;
-    volatile rmt_chnstatus_reg_t chnstatus[2];
-    volatile rmt_chmstatus_reg_t chmstatus[2];
-    volatile rmt_int_raw_reg_t int_raw;
-    volatile rmt_int_st_reg_t int_st;
-    volatile rmt_int_ena_reg_t int_ena;
-    volatile rmt_int_clr_reg_t int_clr;
-    volatile rmt_chncarrier_duty_reg_t chncarrier_duty[2];
-    volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[2];
-    volatile rmt_chn_tx_lim_reg_t chn_tx_lim[2];
-    volatile rmt_chm_rx_lim_reg_t chm_rx_lim[2];
-    volatile rmt_sys_conf_reg_t sys_conf;
-    volatile rmt_tx_sim_reg_t tx_sim;
-    volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
-    uint32_t reserved_074[22];
-    volatile rmt_date_reg_t date;
-} rmt_dev_t;
-
-extern rmt_dev_t RMT;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/rsa_reg.h b/components/soc/esp32c5/beta3/include/soc/rsa_reg.h
deleted file mode 100644
index 542612dbb4..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/rsa_reg.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** RSA_M_MEM register
- *  Represents M
- */
-#define RSA_M_MEM (DR_REG_RSA_BASE + 0x0)
-#define RSA_M_MEM_SIZE_BYTES 16
-
-/** RSA_Z_MEM register
- *  Represents Z
- */
-#define RSA_Z_MEM (DR_REG_RSA_BASE + 0x200)
-#define RSA_Z_MEM_SIZE_BYTES 16
-
-/** RSA_Y_MEM register
- *  Represents Y
- */
-#define RSA_Y_MEM (DR_REG_RSA_BASE + 0x400)
-#define RSA_Y_MEM_SIZE_BYTES 16
-
-/** RSA_X_MEM register
- *  Represents X
- */
-#define RSA_X_MEM (DR_REG_RSA_BASE + 0x600)
-#define RSA_X_MEM_SIZE_BYTES 16
-
-/** RSA_M_PRIME_REG register
- *  Represents M’
- */
-#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
-/** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
- *  Represents M’
- */
-#define RSA_M_PRIME    0xFFFFFFFFU
-#define RSA_M_PRIME_M  (RSA_M_PRIME_V << RSA_M_PRIME_S)
-#define RSA_M_PRIME_V  0xFFFFFFFFU
-#define RSA_M_PRIME_S  0
-
-/** RSA_MODE_REG register
- *  Configures RSA length
- */
-#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
-/** RSA_MODE : R/W; bitpos: [6:0]; default: 0;
- *  Configures the RSA length.
- */
-#define RSA_MODE    0x0000007FU
-#define RSA_MODE_M  (RSA_MODE_V << RSA_MODE_S)
-#define RSA_MODE_V  0x0000007FU
-#define RSA_MODE_S  0
-
-/** RSA_QUERY_CLEAN_REG register
- *  RSA clean register
- */
-#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
-/** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0;
- *  Represents whether or not the RSA memory completes initialization.
- *
- *  0: Not complete
- *
- *  1: Completed
- *
- */
-#define RSA_QUERY_CLEAN    (BIT(0))
-#define RSA_QUERY_CLEAN_M  (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S)
-#define RSA_QUERY_CLEAN_V  0x00000001U
-#define RSA_QUERY_CLEAN_S  0
-
-/** RSA_SET_START_MODEXP_REG register
- *  Starts modular exponentiation
- */
-#define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c)
-/** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0;
- *  Configure whether or not to start the modular exponentiation.
- *
- *  0: No effect
- *
- *  1: Start
- *
- */
-#define RSA_SET_START_MODEXP    (BIT(0))
-#define RSA_SET_START_MODEXP_M  (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S)
-#define RSA_SET_START_MODEXP_V  0x00000001U
-#define RSA_SET_START_MODEXP_S  0
-
-/** RSA_SET_START_MODMULT_REG register
- *  Starts modular multiplication
- */
-#define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810)
-/** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0;
- *  Configure whether or not to start the modular multiplication.
- *
- *  0: No effect
- *
- *  1: Start
- *
- */
-#define RSA_SET_START_MODMULT    (BIT(0))
-#define RSA_SET_START_MODMULT_M  (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S)
-#define RSA_SET_START_MODMULT_V  0x00000001U
-#define RSA_SET_START_MODMULT_S  0
-
-/** RSA_SET_START_MULT_REG register
- *  Starts multiplication
- */
-#define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814)
-/** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0;
- *  Configure whether or not to start the multiplication.
- *
- *  0: No effect
- *
- *  1: Start
- *
- */
-#define RSA_SET_START_MULT    (BIT(0))
-#define RSA_SET_START_MULT_M  (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S)
-#define RSA_SET_START_MULT_V  0x00000001U
-#define RSA_SET_START_MULT_S  0
-
-/** RSA_QUERY_IDLE_REG register
- *  Represents the RSA status
- */
-#define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818)
-/** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0;
- *  Represents the RSA status.
- *
- *  0: Busy
- *
- *  1: Idle
- *
- */
-#define RSA_QUERY_IDLE    (BIT(0))
-#define RSA_QUERY_IDLE_M  (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S)
-#define RSA_QUERY_IDLE_V  0x00000001U
-#define RSA_QUERY_IDLE_S  0
-
-/** RSA_INT_CLR_REG register
- *  Clears RSA interrupt
- */
-#define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c)
-/** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear the RSA interrupt.
- */
-#define RSA_CLEAR_INTERRUPT    (BIT(0))
-#define RSA_CLEAR_INTERRUPT_M  (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
-#define RSA_CLEAR_INTERRUPT_V  0x00000001U
-#define RSA_CLEAR_INTERRUPT_S  0
-
-/** RSA_CONSTANT_TIME_REG register
- *  Configures the constant_time option
- */
-#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
-/** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
- *  Configures the constant_time option.
- *
- *  0: Acceleration
- *
- *  1: No acceleration (default)
- *
- */
-#define RSA_CONSTANT_TIME    (BIT(0))
-#define RSA_CONSTANT_TIME_M  (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
-#define RSA_CONSTANT_TIME_V  0x00000001U
-#define RSA_CONSTANT_TIME_S  0
-
-/** RSA_SEARCH_ENABLE_REG register
- *  Configures the search option
- */
-#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
-/** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Configure the search option.
- *
- *  0: No acceleration (default)
- *
- *  1: Acceleration
- *
- *  This option should be used together with RSA_SEARCH_POS.
- */
-#define RSA_SEARCH_ENABLE    (BIT(0))
-#define RSA_SEARCH_ENABLE_M  (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
-#define RSA_SEARCH_ENABLE_V  0x00000001U
-#define RSA_SEARCH_ENABLE_S  0
-
-/** RSA_SEARCH_POS_REG register
- *  Configures the search position
- */
-#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
-/** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
- *  Configures the starting address to start search. This field should be used together
- *  with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
- */
-#define RSA_SEARCH_POS    0x00000FFFU
-#define RSA_SEARCH_POS_M  (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
-#define RSA_SEARCH_POS_V  0x00000FFFU
-#define RSA_SEARCH_POS_S  0
-
-/** RSA_INT_ENA_REG register
- *  Enables the RSA interrupt
- */
-#define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
-/** RSA_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable the RSA interrupt.
- */
-#define RSA_INT_ENA    (BIT(0))
-#define RSA_INT_ENA_M  (RSA_INT_ENA_V << RSA_INT_ENA_S)
-#define RSA_INT_ENA_V  0x00000001U
-#define RSA_INT_ENA_S  0
-
-/** RSA_DATE_REG register
- *  Version control register
- */
-#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
-/** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624;
- *  Version control register.
- */
-#define RSA_DATE    0x3FFFFFFFU
-#define RSA_DATE_M  (RSA_DATE_V << RSA_DATE_S)
-#define RSA_DATE_V  0x3FFFFFFFU
-#define RSA_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/rsa_struct.h b/components/soc/esp32c5/beta3/include/soc/rsa_struct.h
deleted file mode 100644
index 7546b4e713..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/rsa_struct.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory */
-
-/** Group: Control / Configuration Registers */
-/** Type of m_prime register
- *  Represents M’
- */
-typedef union {
-    struct {
-        /** m_prime : R/W; bitpos: [31:0]; default: 0;
-         *  Represents M’
-         */
-        uint32_t m_prime:32;
-    };
-    uint32_t val;
-} rsa_m_prime_reg_t;
-
-/** Type of mode register
- *  Configures RSA length
- */
-typedef union {
-    struct {
-        /** mode : R/W; bitpos: [6:0]; default: 0;
-         *  Configures the RSA length.
-         */
-        uint32_t mode:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} rsa_mode_reg_t;
-
-/** Type of set_start_modexp register
- *  Starts modular exponentiation
- */
-typedef union {
-    struct {
-        /** set_start_modexp : WT; bitpos: [0]; default: 0;
-         *  Configure whether or not to start the modular exponentiation.
-         *
-         *  0: No effect
-         *
-         *  1: Start
-         *
-         */
-        uint32_t set_start_modexp:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_set_start_modexp_reg_t;
-
-/** Type of set_start_modmult register
- *  Starts modular multiplication
- */
-typedef union {
-    struct {
-        /** set_start_modmult : WT; bitpos: [0]; default: 0;
-         *  Configure whether or not to start the modular multiplication.
-         *
-         *  0: No effect
-         *
-         *  1: Start
-         *
-         */
-        uint32_t set_start_modmult:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_set_start_modmult_reg_t;
-
-/** Type of set_start_mult register
- *  Starts multiplication
- */
-typedef union {
-    struct {
-        /** set_start_mult : WT; bitpos: [0]; default: 0;
-         *  Configure whether or not to start the multiplication.
-         *
-         *  0: No effect
-         *
-         *  1: Start
-         *
-         */
-        uint32_t set_start_mult:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_set_start_mult_reg_t;
-
-/** Type of query_idle register
- *  Represents the RSA status
- */
-typedef union {
-    struct {
-        /** query_idle : RO; bitpos: [0]; default: 0;
-         *  Represents the RSA status.
-         *
-         *  0: Busy
-         *
-         *  1: Idle
-         *
-         */
-        uint32_t query_idle:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_query_idle_reg_t;
-
-/** Type of constant_time register
- *  Configures the constant_time option
- */
-typedef union {
-    struct {
-        /** constant_time : R/W; bitpos: [0]; default: 1;
-         *  Configures the constant_time option.
-         *
-         *  0: Acceleration
-         *
-         *  1: No acceleration (default)
-         *
-         */
-        uint32_t constant_time:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_constant_time_reg_t;
-
-/** Type of search_enable register
- *  Configures the search option
- */
-typedef union {
-    struct {
-        /** search_enable : R/W; bitpos: [0]; default: 0;
-         *  Configure the search option.
-         *
-         *  0: No acceleration (default)
-         *
-         *  1: Acceleration
-         *
-         *  This option should be used together with RSA_SEARCH_POS.
-         */
-        uint32_t search_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_search_enable_reg_t;
-
-/** Type of search_pos register
- *  Configures the search position
- */
-typedef union {
-    struct {
-        /** search_pos : R/W; bitpos: [11:0]; default: 0;
-         *  Configures the starting address to start search. This field should be used together
-         *  with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.
-         */
-        uint32_t search_pos:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} rsa_search_pos_reg_t;
-
-
-/** Group: Status Register */
-/** Type of query_clean register
- *  RSA clean register
- */
-typedef union {
-    struct {
-        /** query_clean : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not the RSA memory completes initialization.
-         *
-         *  0: Not complete
-         *
-         *  1: Completed
-         *
-         */
-        uint32_t query_clean:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_query_clean_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_clr register
- *  Clears RSA interrupt
- */
-typedef union {
-    struct {
-        /** clear_interrupt : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear the RSA interrupt.
-         */
-        uint32_t clear_interrupt:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_int_clr_reg_t;
-
-/** Type of int_ena register
- *  Enables the RSA interrupt
- */
-typedef union {
-    struct {
-        /** int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable the RSA interrupt.
-         */
-        uint32_t int_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} rsa_int_ena_reg_t;
-
-
-/** Group: Version Control Register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [29:0]; default: 538969624;
-         *  Version control register.
-         */
-        uint32_t date:30;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} rsa_date_reg_t;
-
-
-typedef struct rsa_dev_t {
-    volatile uint32_t m[4];
-    uint32_t reserved_010[124];
-    volatile uint32_t z[4];
-    uint32_t reserved_210[124];
-    volatile uint32_t y[4];
-    uint32_t reserved_410[124];
-    volatile uint32_t x[4];
-    uint32_t reserved_610[124];
-    volatile rsa_m_prime_reg_t m_prime;
-    volatile rsa_mode_reg_t mode;
-    volatile rsa_query_clean_reg_t query_clean;
-    volatile rsa_set_start_modexp_reg_t set_start_modexp;
-    volatile rsa_set_start_modmult_reg_t set_start_modmult;
-    volatile rsa_set_start_mult_reg_t set_start_mult;
-    volatile rsa_query_idle_reg_t query_idle;
-    volatile rsa_int_clr_reg_t int_clr;
-    volatile rsa_constant_time_reg_t constant_time;
-    volatile rsa_search_enable_reg_t search_enable;
-    volatile rsa_search_pos_reg_t search_pos;
-    volatile rsa_int_ena_reg_t int_ena;
-    volatile rsa_date_reg_t date;
-} rsa_dev_t;
-
-extern rsa_dev_t RSA;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(rsa_dev_t) == 0x834, "Invalid size of rsa_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/rtc_io_channel.h b/components/soc/esp32c5/beta3/include/soc/rtc_io_channel.h
deleted file mode 100644
index f954459939..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/rtc_io_channel.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-// TODO: [ESP32C5] IDF-8719 (inherit from C6)
-//RTC GPIO channels
-#define RTCIO_GPIO0_CHANNEL         0   //RTCIO_CHANNEL_0
-#define RTCIO_CHANNEL_0_GPIO_NUM    0
-
-#define RTCIO_GPIO1_CHANNEL         1   //RTCIO_CHANNEL_1
-#define RTCIO_CHANNEL_1_GPIO_NUM    1
-
-#define RTCIO_GPIO2_CHANNEL         2   //RTCIO_CHANNEL_2
-#define RTCIO_CHANNEL_2_GPIO_NUM    2
-
-#define RTCIO_GPIO3_CHANNEL         3   //RTCIO_CHANNEL_3
-#define RTCIO_CHANNEL_3_GPIO_NUM    3
-
-#define RTCIO_GPIO4_CHANNEL         4   //RTCIO_CHANNEL_4
-#define RTCIO_CHANNEL_4_GPIO_NUM    4
-
-#define RTCIO_GPIO5_CHANNEL         5   //RTCIO_CHANNEL_5
-#define RTCIO_CHANNEL_5_GPIO_NUM    5
-
-#define RTCIO_GPIO6_CHANNEL         6   //RTCIO_CHANNEL_6
-#define RTCIO_CHANNEL_6_GPIO_NUM    6
-
-#define RTCIO_GPIO7_CHANNEL         7   //RTCIO_CHANNEL_7
-#define RTCIO_CHANNEL_7_GPIO_NUM    7
diff --git a/components/soc/esp32c5/beta3/include/soc/sha_reg.h b/components/soc/esp32c5/beta3/include/soc/sha_reg.h
deleted file mode 100644
index 11181a16e1..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/sha_reg.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SHA_MODE_REG register
- *  Initial configuration register.
- */
-#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
-/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Sha mode.
- */
-#define SHA_MODE    0x00000007U
-#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
-#define SHA_MODE_V  0x00000007U
-#define SHA_MODE_S  0
-
-/** SHA_DMA_BLOCK_NUM_REG register
- *  DMA configuration register 0.
- */
-#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
-/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
- *  Dma-sha block number.
- */
-#define SHA_DMA_BLOCK_NUM    0x0000003FU
-#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
-#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
-#define SHA_DMA_BLOCK_NUM_S  0
-
-/** SHA_START_REG register
- *  Typical SHA configuration register 0.
- */
-#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
-/** SHA_START : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_START    0x7FFFFFFFU
-#define SHA_START_M  (SHA_START_V << SHA_START_S)
-#define SHA_START_V  0x7FFFFFFFU
-#define SHA_START_S  1
-
-/** SHA_CONTINUE_REG register
- *  Typical SHA configuration register 1.
- */
-#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
-/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_CONTINUE    0x7FFFFFFFU
-#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
-#define SHA_CONTINUE_V  0x7FFFFFFFU
-#define SHA_CONTINUE_S  1
-
-/** SHA_BUSY_REG register
- *  Busy register.
- */
-#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
-/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
- *  Sha busy state. 1'b0: idle. 1'b1: busy.
- */
-#define SHA_BUSY_STATE    (BIT(0))
-#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
-#define SHA_BUSY_STATE_V  0x00000001U
-#define SHA_BUSY_STATE_S  0
-
-/** SHA_DMA_START_REG register
- *  DMA configuration register 1.
- */
-#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
-/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
- *  Start dma-sha.
- */
-#define SHA_DMA_START    (BIT(0))
-#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
-#define SHA_DMA_START_V  0x00000001U
-#define SHA_DMA_START_S  0
-
-/** SHA_DMA_CONTINUE_REG register
- *  DMA configuration register 2.
- */
-#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
-/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
- *  Continue dma-sha.
- */
-#define SHA_DMA_CONTINUE    (BIT(0))
-#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
-#define SHA_DMA_CONTINUE_V  0x00000001U
-#define SHA_DMA_CONTINUE_S  0
-
-/** SHA_CLEAR_IRQ_REG register
- *  Interrupt clear register.
- */
-#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
-/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
- *  Clear sha interrupt.
- */
-#define SHA_CLEAR_INTERRUPT    (BIT(0))
-#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
-#define SHA_CLEAR_INTERRUPT_V  0x00000001U
-#define SHA_CLEAR_INTERRUPT_S  0
-
-/** SHA_IRQ_ENA_REG register
- *  Interrupt enable register.
- */
-#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
-/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
- *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
- */
-#define SHA_INTERRUPT_ENA    (BIT(0))
-#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
-#define SHA_INTERRUPT_ENA_V  0x00000001U
-#define SHA_INTERRUPT_ENA_S  0
-
-/** SHA_DATE_REG register
- *  Date register.
- */
-#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
-/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
- *  Sha date information/ sha version information.
- */
-#define SHA_DATE    0x3FFFFFFFU
-#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
-#define SHA_DATE_V  0x3FFFFFFFU
-#define SHA_DATE_S  0
-
-/** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
- */
-#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
-#define SHA_H_MEM_SIZE_BYTES 64
-
-/** SHA_M_MEM register
- *  Sha M memory which contains message.
- */
-#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
-#define SHA_M_MEM_SIZE_BYTES 64
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/sha_struct.h b/components/soc/esp32c5/beta3/include/soc/sha_struct.h
deleted file mode 100644
index 41ae395f7e..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/sha_struct.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of mode register
- *  Initial configuration register.
- */
-typedef union {
-    struct {
-        /** mode : R/W; bitpos: [2:0]; default: 0;
-         *  Sha mode.
-         */
-        uint32_t mode:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} sha_mode_reg_t;
-
-/** Type of dma_block_num register
- *  DMA configuration register 0.
- */
-typedef union {
-    struct {
-        /** dma_block_num : R/W; bitpos: [5:0]; default: 0;
-         *  Dma-sha block number.
-         */
-        uint32_t dma_block_num:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} sha_dma_block_num_reg_t;
-
-/** Type of start register
- *  Typical SHA configuration register 0.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** start : RO; bitpos: [31:1]; default: 0;
-         *  Reserved.
-         */
-        uint32_t start:31;
-    };
-    uint32_t val;
-} sha_start_reg_t;
-
-/** Type of continue register
- *  Typical SHA configuration register 1.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** conti : RO; bitpos: [31:1]; default: 0;
-         *  Reserved.
-         */
-        uint32_t conti:31;
-    };
-    uint32_t val;
-} sha_continue_reg_t;
-
-/** Type of dma_start register
- *  DMA configuration register 1.
- */
-typedef union {
-    struct {
-        /** dma_start : WO; bitpos: [0]; default: 0;
-         *  Start dma-sha.
-         */
-        uint32_t dma_start:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} sha_dma_start_reg_t;
-
-/** Type of dma_continue register
- *  DMA configuration register 2.
- */
-typedef union {
-    struct {
-        /** dma_continue : WO; bitpos: [0]; default: 0;
-         *  Continue dma-sha.
-         */
-        uint32_t dma_continue:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} sha_dma_continue_reg_t;
-
-
-/** Group: Status Register */
-/** Type of busy register
- *  Busy register.
- */
-typedef union {
-    struct {
-        /** busy_state : RO; bitpos: [0]; default: 0;
-         *  Sha busy state. 1'b0: idle. 1'b1: busy.
-         */
-        uint32_t busy_state:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} sha_busy_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of clear_irq register
- *  Interrupt clear register.
- */
-typedef union {
-    struct {
-        /** clear_interrupt : WO; bitpos: [0]; default: 0;
-         *  Clear sha interrupt.
-         */
-        uint32_t clear_interrupt:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} sha_clear_irq_reg_t;
-
-/** Type of irq_ena register
- *  Interrupt enable register.
- */
-typedef union {
-    struct {
-        /** interrupt_ena : R/W; bitpos: [0]; default: 0;
-         *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
-         */
-        uint32_t interrupt_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} sha_irq_ena_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [29:0]; default: 538972713;
-         *  Sha date information/ sha version information.
-         */
-        uint32_t date:30;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} sha_date_reg_t;
-
-
-/** Group: memory type */
-
-typedef struct sha_dev_t {
-    volatile sha_mode_reg_t mode;
-    uint32_t reserved_004[2];
-    volatile sha_dma_block_num_reg_t dma_block_num;
-    volatile sha_start_reg_t start;
-    volatile sha_continue_reg_t conti;
-    volatile sha_busy_reg_t busy;
-    volatile sha_dma_start_reg_t dma_start;
-    volatile sha_dma_continue_reg_t dma_continue;
-    volatile sha_clear_irq_reg_t clear_irq;
-    volatile sha_irq_ena_reg_t irq_ena;
-    volatile sha_date_reg_t date;
-    uint32_t reserved_030[4];
-    volatile uint32_t h[16];
-    volatile uint32_t m[16];
-} sha_dev_t;
-
-extern sha_dev_t SHA;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(sha_dev_t) == 0xc0, "Invalid size of sha_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/soc.h b/components/soc/esp32c5/beta3/include/soc/soc.h
deleted file mode 100644
index eaf6062299..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/soc.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#ifndef __ASSEMBLER__
-#include <stdint.h>
-#include "esp_assert.h"
-#endif
-
-#include "esp_bit_defs.h"
-#include "reg_base.h"
-
-#define PRO_CPU_NUM (0)
-
-/**
- * @brief Reg base address for multi-instance peripherals
- * @note  common multi-instance peripherals includes
- *        I2C, I2S, UART, UHCI, SPI, SPIMEM, MCPWM, TWAI, TIMER_GROUP
- *        please check `reg_base.h` and the corresponding `xxx_reg.h` whether the base addresses are match
- */
-#define REG_I2C_BASE(i)                         ((i) == 0 ? DR_REG_I2C0_BASE : DR_REG_I2C1_BASE) // two I2C on C5
-#define REG_TIMG_BASE(i)                        (DR_REG_TIMERG0_BASE + (i) * 0x1000)     // TIMERG0 and TIMERG1
-#define REG_TWAI_BASE(i)                        ((i) == 0 ? DR_REG_TWAI0_BASE : DR_REG_TWAI1_BASE)       // TWAI0 and TWAI1
-#define REG_UART_BASE(i)                        (DR_REG_UART0_BASE + (i) * 0x1000)        // UART0 and UART1
-#define REG_SPI_MEM_BASE(i)                     (DR_REG_SPIMEM0_BASE + (i) * 0x1000)
-//Registers Operation {{
-#define ETS_UNCACHED_ADDR(addr) (addr)
-#define ETS_CACHED_ADDR(addr) (addr)
-
-#ifndef __ASSEMBLER__
-
-//write value to register
-#define REG_WRITE(_r, _v)  do {                                                                                        \
-            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
-        } while(0)
-
-//read value from register
-#define REG_READ(_r) ({                                                                                                \
-            (*(volatile uint32_t *)(_r));                                                                              \
-        })
-
-//get bit or get bits from register
-#define REG_GET_BIT(_r, _b)  ({                                                                                        \
-            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
-        })
-
-//set bit or set bits to register
-#define REG_SET_BIT(_r, _b)  do {                                                                                      \
-            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b);                                            \
-        } while(0)
-
-//clear bit or clear bits of register
-#define REG_CLR_BIT(_r, _b)  do {                                                                                      \
-            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b));                                         \
-        } while(0)
-
-//set bits of register controlled by mask
-#define REG_SET_BITS(_r, _b, _m) do {                                                                                  \
-            *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m));                           \
-        } while(0)
-
-//get field from register, uses field _S & _V to determine mask
-#define REG_GET_FIELD(_r, _f) ({                                                                                       \
-            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
-        })
-
-//set field of a register from variable, uses field _S & _V to determine mask
-#define REG_SET_FIELD(_r, _f, _v) do {                                                                                 \
-            REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))));                  \
-        } while(0)
-
-//get field value from a variable, used when _f is not left shifted by _f##_S
-#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
-
-//get field value from a variable, used when _f is left shifted by _f##_S
-#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
-
-//set field value to a variable, used when _f is not left shifted by _f##_S
-#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
-
-//set field value to a variable, used when _f is left shifted by _f##_S
-#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
-
-//generate a value from a field value, used when _f is not left shifted by _f##_S
-#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
-
-//generate a value from a field value, used when _f is left shifted by _f##_S
-#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
-
-//read value from register
-#define READ_PERI_REG(addr) ({                                                                                         \
-            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
-        })
-
-//write value to register
-#define WRITE_PERI_REG(addr, val) do {                                                                                 \
-            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
-        } while(0)
-
-//clear bits of register controlled by mask
-#define CLEAR_PERI_REG_MASK(reg, mask)  do {                                                                           \
-            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
-        } while(0)
-
-//set bits of register controlled by mask
-#define SET_PERI_REG_MASK(reg, mask) do {                                                                              \
-            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
-        } while(0)
-
-//get bits of register controlled by mask
-#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
-            (READ_PERI_REG(reg) & (mask));                                                                             \
-        })
-
-//get bits of register controlled by highest bit and lowest bit
-#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
-            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
-        })
-
-//set bits of register controlled by mask and shift
-#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do {                                                                \
-            WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) );      \
-        } while(0)
-
-//get field of register
-#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
-            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
-        })
-
-#endif /* !__ASSEMBLER__ */
-//}}
-
-//Periheral Clock {{
-#define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
-#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
-#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
-#define  APB_CLK_FREQ                                ( 40*1000000 )
-#define  MODEM_REQUIRED_MIN_APB_CLK_FREQ             ( 80*1000000 )
-#define  REF_CLK_FREQ                                ( 1000000 )
-#define  XTAL_CLK_FREQ                               (40*1000000)
-#define  GPIO_MATRIX_DELAY_NS                        0
-//}}
-
-/* Overall memory map */
-/* Note: We should not use MACROs similar in cache_memory.h
- * those are defined during run-time. But the MACROs here
- * should be defined statically!
- */
-
-#define SOC_IROM_LOW    0x41000000
-#define SOC_IROM_HIGH   (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8))
-#define SOC_DROM_LOW    SOC_IROM_LOW
-#define SOC_DROM_HIGH   SOC_IROM_HIGH
-#define SOC_IROM_MASK_LOW  0x40000000
-#define SOC_IROM_MASK_HIGH 0x40050000
-#define SOC_DROM_MASK_LOW  0x40000000
-#define SOC_DROM_MASK_HIGH 0x40050000
-#define SOC_IRAM_LOW    0x40800000
-#define SOC_IRAM_HIGH   0x40880000
-#define SOC_DRAM_LOW    0x40800000
-#define SOC_DRAM_HIGH   0x40880000
-#define SOC_RTC_IRAM_LOW  0x50000000 // ESP32-C5 only has 16k LP memory
-#define SOC_RTC_IRAM_HIGH 0x50004000
-#define SOC_RTC_DRAM_LOW  0x50000000
-#define SOC_RTC_DRAM_HIGH 0x50004000
-#define SOC_RTC_DATA_LOW  0x50000000
-#define SOC_RTC_DATA_HIGH 0x50004000
-
-//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
-#define SOC_DIRAM_IRAM_LOW    0x40800000
-#define SOC_DIRAM_IRAM_HIGH   0x40880000
-#define SOC_DIRAM_DRAM_LOW    0x40800000
-#define SOC_DIRAM_DRAM_HIGH   0x40880000
-
-#define MAP_DRAM_TO_IRAM(addr) (addr)
-#define MAP_IRAM_TO_DRAM(addr) (addr)
-
-// Region of memory accessible via DMA. See esp_ptr_dma_capable().
-#define SOC_DMA_LOW  0x40800000
-#define SOC_DMA_HIGH 0x40880000
-
-// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
-#define SOC_BYTE_ACCESSIBLE_LOW     0x40800000
-#define SOC_BYTE_ACCESSIBLE_HIGH    0x40880000
-
-//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
-//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
-#define SOC_MEM_INTERNAL_LOW        0x40800000
-#define SOC_MEM_INTERNAL_HIGH       0x40880000
-#define SOC_MEM_INTERNAL_LOW1       0x40800000
-#define SOC_MEM_INTERNAL_HIGH1      0x40880000
-
-#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
-
-// Region of address space that holds peripherals
-#define SOC_PERIPHERAL_LOW 0x60000000
-#define SOC_PERIPHERAL_HIGH 0x60100000
-
-// CPU sub-system region, contains interrupt config registers
-#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
-#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
-
-// Start (highest address) of ROM boot stack, only relevant during early boot
-#define SOC_ROM_STACK_START         0x4087e610
-#define SOC_ROM_STACK_SIZE          0x2000
-
-//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
-//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
-
-//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
-#define ETS_T1_WDT_INUM                         24
-#define ETS_CACHEERR_INUM                       25
-#define ETS_MEMPROT_ERR_INUM                    26
-#define ETS_ASSIST_DEBUG_INUM                   27  // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated
-
-//CPU0 Max valid interrupt number
-#define ETS_MAX_INUM                            31
-
-//CPU0 Interrupt number used in ROM, should be cancelled in SDK
-#define ETS_SLC_INUM                            1
-#define ETS_UART0_INUM                          5
-#define ETS_UART1_INUM                          5
-#define ETS_SPI2_INUM                           1
-//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
-#define ETS_GPIO_INUM       4
-
-//Other interrupt number should be managed by the user
-
-//Invalid interrupt for number interrupt matrix
-#define ETS_INVALID_INUM                        0
-
-//Interrupt medium level, used for INT WDT for example
-#define SOC_INTERRUPT_LEVEL_MEDIUM              4
-
-// Interrupt number for the Interrupt watchdog
-#define ETS_INT_WDT_INUM                         (ETS_T1_WDT_INUM)
diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h
deleted file mode 100644
index 9d9b1bbaeb..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * These defines are parsed and imported as kconfig variables via the script
- * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
- *
- * If this file is changed the script will automatically run the script
- * and generate the kconfig variables as part of the pre-commit hooks.
- *
- * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md`
- */
-
-#pragma once
-
-/*-------------------------- COMMON CAPS ---------------------------------------*/
-// #define SOC_ADC_SUPPORTED               1  // TODO: [ESP32C5] IDF-8701
-// #define SOC_DEDICATED_GPIO_SUPPORTED    1  // TODO: [ESP32C5] IDF-8725
-#define SOC_UART_SUPPORTED              1
-#define SOC_GDMA_SUPPORTED              1
-#define SOC_AHB_GDMA_SUPPORTED          1
-#define SOC_GPTIMER_SUPPORTED           1
-#define SOC_PCNT_SUPPORTED              1
-// #define SOC_MCPWM_SUPPORTED             1  // TODO: [ESP32C5] IDF-8709
-// #define SOC_TWAI_SUPPORTED              1  // TODO: [ESP32C5] IDF-8691
-// #define SOC_ETM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8693
-// #define SOC_PARLIO_SUPPORTED            1  // TODO: [ESP32C5] IDF-8685, IDF-8686
-#define SOC_ASYNC_MEMCPY_SUPPORTED      1
-// #define SOC_USB_SERIAL_JTAG_SUPPORTED   1  // TODO: [ESP32C5] IDF-8721
-// #define SOC_TEMP_SENSOR_SUPPORTED       1  // TODO: [ESP32C5] IDF-8727
-#define SOC_PHY_SUPPORTED               1
-#define SOC_WIFI_SUPPORTED              1
-#define SOC_SUPPORTS_SECURE_DL_MODE     1
-// #define SOC_LP_CORE_SUPPORTED           1  // TODO: [ESP32C5] IDF-8637
-#define SOC_EFUSE_KEY_PURPOSE_FIELD     1
-#define SOC_EFUSE_SUPPORTED             1
-#define SOC_RTC_FAST_MEM_SUPPORTED      1
-#define SOC_RTC_MEM_SUPPORTED           1
-#define SOC_IEEE802154_SUPPORTED        1
-// #define SOC_I2S_SUPPORTED               1  // TODO: [ESP32C5] IDF-8713, IDF-8714
-#define SOC_RMT_SUPPORTED               1
-// #define SOC_SDM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8687
-#define SOC_GPSPI_SUPPORTED             1
-// #define SOC_LEDC_SUPPORTED              1  // TODO: [ESP32C5] IDF-8684
-#define SOC_I2C_SUPPORTED               1
-#define SOC_SYSTIMER_SUPPORTED          1     // TODO: [ESP32C5] IDF-8707
-#define SOC_AES_SUPPORTED               1
-#define SOC_MPI_SUPPORTED               1
-#define SOC_SHA_SUPPORTED               1
-#define SOC_RSA_SUPPORTED               1
-#define SOC_HMAC_SUPPORTED              1
-#define SOC_DIG_SIGN_SUPPORTED          1
-#define SOC_ECC_SUPPORTED               1
-#define SOC_ECC_EXTENDED_MODES_SUPPORTED   1
-#define SOC_FLASH_ENC_SUPPORTED         1
-#define SOC_SECURE_BOOT_SUPPORTED       1
-// #define SOC_BOD_SUPPORTED               1  // TODO: [ESP32C5] IDF-8647
-// #define SOC_APM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8614, IDF-8615
-#define SOC_PMU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8667
-#define SOC_PAU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8638
-#define SOC_LP_TIMER_SUPPORTED          1  // TODO: [ESP32C5] IDF-8636
-#define SOC_LP_AON_SUPPORTED            1  // TODO: [ESP32C5] IDF-8638
-#define SOC_LP_PERIPHERALS_SUPPORTED    1
-// #define SOC_LP_I2C_SUPPORTED            1  // TODO: [ESP32C5] IDF-8634
-#define SOC_ULP_SUPPORTED               1
-#define SOC_LP_CORE_SUPPORTED           1
-// #define SOC_ULP_LP_UART_SUPPORTED       1  // TODO: [ESP32C5] IDF-8633
-// #define SOC_CLK_TREE_SUPPORTED          1  // TODO: [ESP32C5] IDF-8642
-// #define SOC_ASSIST_DEBUG_SUPPORTED      1  // TODO: [ESP32C5] IDF-8663
-// #define SOC_WDT_SUPPORTED               1  // TODO: [ESP32C5] IDF-8650
-#define SOC_SPI_FLASH_SUPPORTED         1     // TODO: [ESP32C5] IDF-8715
-// #define SOC_BITSCRAMBLER_SUPPORTED      1  // TODO: [ESP32C5] IDF-8711
-#define SOC_ECDSA_SUPPORTED             1
-// #define SOC_KEY_MANAGER_SUPPORTED       1  // TODO: [ESP32C5] IDF-8621
-// #define SOC_HUK_SUPPORTED               1  // TODO: [ESP32C5] IDF-8617
-#define SOC_LIGHT_SLEEP_SUPPORTED       1
-// #define SOC_DEEP_SLEEP_SUPPORTED        1  // TODO: [ESP32C5] IDF-8638
-#define SOC_MODEM_CLOCK_SUPPORTED       1     // TODO: [ESP32C5] IDF-8845 need check, it is opened because pll has been used on beta3
-#define SOC_BT_SUPPORTED                1
-#define SOC_PHY_SUPPORTED               1
-#define SOC_PM_SUPPORTED                1
-
-/*-------------------------- XTAL CAPS ---------------------------------------*/
-#define SOC_XTAL_SUPPORT_40M            1
-#define SOC_XTAL_SUPPORT_48M            1
-
-/*-------------------------- AES CAPS -----------------------------------------*/
-#define SOC_AES_SUPPORT_DMA     (1)
-
-/* Has a centralized DMA, which is shared with all peripherals */
-#define SOC_AES_GDMA            (1)
-
-#define SOC_AES_SUPPORT_AES_128 (1)
-#define SOC_AES_SUPPORT_AES_256 (1)
-
-/*-------------------------- ADC CAPS -------------------------------*/
-/*!< SAR ADC Module*/
-// #define SOC_ADC_DIG_CTRL_SUPPORTED              1
-// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
-// #define SOC_ADC_MONITOR_SUPPORTED               1
-// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
-// #define SOC_ADC_DMA_SUPPORTED                   1
-#define SOC_ADC_PERIPH_NUM                      (1U)
-// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (7)
-#define SOC_ADC_MAX_CHANNEL_NUM                 (7)
-// #define SOC_ADC_ATTEN_NUM                       (4)
-
-/*!< Digital */
-// #define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
-// #define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
-// #define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
-// #define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
-// #define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
-// #define SOC_ADC_DIGI_MONITOR_NUM                (2)
-// #define SOC_ADC_DIGI_RESULT_BYTES               (4)
-// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
-/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
-// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
-// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
-
-/*!< RTC */
-// #define SOC_ADC_RTC_MIN_BITWIDTH                (12)
-// #define SOC_ADC_RTC_MAX_BITWIDTH                (12)
-
-/*!< Calibration */
-// #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
-// #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
-// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
-
-/*!< Interrupt */
-// #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
-
-/*!< ADC power control is shared by PWDET */
-// #define SOC_ADC_SHARED_POWER                    1
-
-// ESP32C5-TODO: Copy from esp32C5, need check
-/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
-// #define SOC_APB_BACKUP_DMA              (0)
-
-/*-------------------------- BROWNOUT CAPS -----------------------------------*/
-// #define SOC_BROWNOUT_RESET_SUPPORTED 1
-
-/*-------------------------- CACHE CAPS --------------------------------------*/
-#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
-#define SOC_CACHE_FREEZE_SUPPORTED              1
-
-/*-------------------------- CPU CAPS ----------------------------------------*/
-#define SOC_CPU_CORES_NUM               (1U)
-#define SOC_CPU_INTR_NUM                32
-#define SOC_CPU_HAS_FLEXIBLE_INTC       1
-#define SOC_INT_CLIC_SUPPORTED          1
-#define SOC_INT_HW_NESTED_SUPPORTED     1       // Support for hardware interrupts nesting
-#define SOC_BRANCH_PREDICTOR_SUPPORTED  1
-
-#define SOC_CPU_BREAKPOINTS_NUM         4
-#define SOC_CPU_WATCHPOINTS_NUM         4
-#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE         0x100 // bytes
-
-#define SOC_CPU_HAS_PMA                 1
-#define SOC_CPU_IDRAM_SPLIT_USING_PMP   1
-
-/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
-/** The maximum length of a Digital Signature in bits. */
-#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
-
-/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
-#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
-
-/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
-    See TRM DS chapter for more details */
-#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
-
-/*-------------------------- GDMA CAPS -------------------------------------*/
-#define SOC_AHB_GDMA_VERSION                1U
-#define SOC_GDMA_NUM_GROUPS_MAX             1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX        3
-// #define SOC_GDMA_SUPPORT_ETM                1  // Support ETM submodule TODO: IDF-9224
-// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1  // TODO: IDF-9225
-
-/*-------------------------- ETM CAPS --------------------------------------*/
-// #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
-// #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
-
-/*-------------------------- GPIO CAPS ---------------------------------------*/
-// ESP32-C5 has 1 GPIO peripheral
-#define SOC_GPIO_PORT                      1U
-#define SOC_GPIO_PIN_COUNT                 27   // TODO: update C5bate3 to C5 MP
-// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
-// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
-#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER      1
-
-// GPIO peripheral has the ETM extension
-// #define SOC_GPIO_SUPPORT_ETM          1
-
-// Target has the full LP IO subsystem
-// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
-#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
-// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
-// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  // TODO: [ESP32C5] IDF-8719
-
-#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
-#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
-
-#define SOC_GPIO_IN_RANGE_MAX           26
-#define SOC_GPIO_OUT_RANGE_MAX          26
-
-#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
-
-// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_26)
-#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000007FFFF00ULL
-
-// Support to force hold all IOs
-#define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-// Support to hold a single digital I/O when the digital domain is powered off
-#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
-
-// The Clock Out signal is route to the pin by GPIO matrix
-// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
-#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
-
-/*-------------------------- RTCIO CAPS --------------------------------------*/
-#define SOC_RTCIO_PIN_COUNT                 0UL
-// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1  /* This macro indicates that the target has separate RTC IOMUX hardware feature,
-                                            //  * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
-                                            //  * when the pins are switched to RTC function.
-                                            //  */
-// #define SOC_RTCIO_HOLD_SUPPORTED            1
-// #define SOC_RTCIO_WAKE_SUPPORTED            1
-
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
-// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
-/*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C5 has 1 I2C
-#define SOC_I2C_NUM                 (1U)
-#define SOC_HP_I2C_NUM              (1U)
-
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
-
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
-
-#define SOC_I2C_SUPPORT_XTAL        (1)
-// #define SOC_I2C_SUPPORT_RTC         (1)   // TODO: [ESP32C5] IDF-8667
-#define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-
-// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693
-
-/*-------------------------- LP_I2C CAPS -------------------------------------*/
-// ESP32-C5 has 1 LP_I2C
-// #define SOC_LP_I2C_NUM              (1U)
-
-// #define SOC_LP_I2C_FIFO_LEN         (16) /*!< LP_I2C hardware FIFO depth */
-
-/*-------------------------- I2S CAPS ----------------------------------------*/
-// #define SOC_I2S_NUM                 (1U)
-// #define SOC_I2S_HW_VERSION_2        (1)
-// #define SOC_I2S_SUPPORTS_XTAL       (1)
-// #define SOC_I2S_SUPPORTS_PLL_F160M  (1)
-// #define SOC_I2S_SUPPORTS_PCM        (1)
-// #define SOC_I2S_SUPPORTS_PDM        (1)
-// #define SOC_I2S_SUPPORTS_PDM_TX     (1)
-// #define SOC_I2S_PDM_MAX_TX_LINES    (2)
-// #define SOC_I2S_SUPPORTS_TDM        (1)
-
-/*-------------------------- LEDC CAPS ---------------------------------------*/
-// TODO: [ESP32C5] 8684
-#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
-#define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
-#define SOC_LEDC_CHANNEL_NUM                (6)
-// #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
-// #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
-// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
-// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
-// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
-
-/*-------------------------- MMU CAPS ----------------------------------------*/
-// TODO: [ESP32C5] IDF-8658
-// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (1)
-#define SOC_MMU_PERIPH_NUM                    (1U)
-#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM     (1U)
-#define SOC_MMU_DI_VADDR_SHARED               (1) /*!< D/I vaddr are shared */
-
-/*-------------------------- MPU CAPS ----------------------------------------*/
-// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
-// #define SOC_MPU_MIN_REGION_SIZE                   0x20000000U
-// #define SOC_MPU_REGIONS_MAX_NUM                   8
-// #define SOC_MPU_REGION_RO_SUPPORTED               0
-// #define SOC_MPU_REGION_WO_SUPPORTED               0
-
-/*-------------------------- PCNT CAPS ---------------------------------------*/
-#define SOC_PCNT_GROUPS                       1U
-#define SOC_PCNT_UNITS_PER_GROUP              4
-#define SOC_PCNT_CHANNELS_PER_UNIT            2
-#define SOC_PCNT_THRES_POINT_PER_UNIT         2
-#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
-#define SOC_PCNT_SUPPORT_CLEAR_SIGNAL         1
-
-/*--------------------------- RMT CAPS ---------------------------------------*/
-#define SOC_RMT_GROUPS                        1U /*!< One RMT group */
-#define SOC_RMT_TX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Transmit */
-#define SOC_RMT_RX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Receive */
-#define SOC_RMT_CHANNELS_PER_GROUP            4  /*!< Total 4 channels */
-#define SOC_RMT_MEM_WORDS_PER_CHANNEL         48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
-#define SOC_RMT_SUPPORT_RX_PINGPONG           1  /*!< Support Ping-Pong mode on RX path */
-#define SOC_RMT_SUPPORT_RX_DEMODULATION       1  /*!< Support signal demodulation on RX path (i.e. remove carrier) */
-#define SOC_RMT_SUPPORT_TX_ASYNC_STOP         1  /*!< Support stop transmission asynchronously */
-#define SOC_RMT_SUPPORT_TX_LOOP_COUNT         1  /*!< Support transmit specified number of cycles in loop mode */
-#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP     1  /*!< Hardware support of auto-stop in loop mode */
-#define SOC_RMT_SUPPORT_TX_SYNCHRO            1  /*!< Support coordinate a group of TX channels to start simultaneously */
-#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY  1  /*!< TX carrier can be modulated to data phase only */
-#define SOC_RMT_SUPPORT_XTAL                  1  /*!< Support set XTAL clock as the RMT clock source */
-// #define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST as the RMT clock source */
-
-/*-------------------------- MCPWM CAPS --------------------------------------*/
-// #define SOC_MCPWM_GROUPS                     (1U)   ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
-// #define SOC_MCPWM_TIMERS_PER_GROUP           (3)    ///< The number of timers that each group has
-// #define SOC_MCPWM_OPERATORS_PER_GROUP        (3)    ///< The number of operators that each group has
-// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR   (2)    ///< The number of comparators that each operator has
-// #define SOC_MCPWM_GENERATORS_PER_OPERATOR    (2)    ///< The number of generators that each operator has
-// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR      (2)    ///< The number of triggers that each operator has
-// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP      (3)    ///< The number of fault signal detectors that each group has
-// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP   (1)    ///< The number of capture timers that each group has
-// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3)    ///< The number of capture channels that each capture timer has
-// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP    (3)    ///< The number of GPIO synchros that each group has
-// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE       (1)    ///< Software sync event can be routed to its output
-// #define SOC_MCPWM_SUPPORT_ETM                (1)    ///< Support ETM (Event Task Matrix)
-// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP     (1)    ///< Capture timer shares clock with other PWM timers
-
-/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
-// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
-
-/*-------------------------- PARLIO CAPS --------------------------------------*/
-// #define SOC_PARLIO_GROUPS                    1U  /*!< Number of parallel IO peripherals */
-// #define SOC_PARLIO_TX_UNITS_PER_GROUP        1U  /*!< number of TX units in each group */
-// #define SOC_PARLIO_RX_UNITS_PER_GROUP        1U  /*!< number of RX units in each group */
-// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
-// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
-// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT     1   /*!< TX and RX unit share the same interrupt source number */
-
-/*--------------------------- MPI CAPS ---------------------------------------*/
-#define SOC_MPI_MEM_BLOCKS_NUM (4)
-#define SOC_MPI_OPERATIONS_NUM (3)
-
-/*--------------------------- RSA CAPS ---------------------------------------*/
-#define SOC_RSA_MAX_BIT_LEN    (3072)
-
-/*--------------------------- SHA CAPS ---------------------------------------*/
-
-/* Max amount of bytes in a single DMA operation is 4095,
-   for SHA this means that the biggest safe amount of bytes is
-   31 blocks of 128 bytes = 3968
-*/
-#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
-#define SOC_SHA_SUPPORT_DMA             (1)
-
-/* The SHA engine is able to resume hashing from a user */
-#define SOC_SHA_SUPPORT_RESUME          (1)
-
-/* Has a centralized DMA, which is shared with all peripherals */
-#define SOC_SHA_GDMA             (1)
-
-/* Supported HW algorithms */
-#define SOC_SHA_SUPPORT_SHA1            (1)
-#define SOC_SHA_SUPPORT_SHA224          (1)
-#define SOC_SHA_SUPPORT_SHA256          (1)
-
-/*--------------------------- ECDSA CAPS ---------------------------------------*/
-#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY     (1)
-
-/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-// #define SOC_SDM_GROUPS               1U
-// #define SOC_SDM_CHANNELS_PER_GROUP   4
-// #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
-// #define SOC_SDM_CLK_SUPPORT_XTAL     1
-
-/*-------------------------- SPI CAPS ----------------------------------------*/
-#define SOC_SPI_PERIPH_NUM          2
-#define SOC_SPI_PERIPH_CS_NUM(i)    6
-#define SOC_SPI_MAX_CS_NUM          6
-
-#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
-
-#define SOC_SPI_SUPPORT_DDRCLK              1
-#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
-#define SOC_SPI_SUPPORT_CD_SIG              1
-#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
-#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
-#define SOC_SPI_SUPPORT_CLK_XTAL            1
-// #define SOC_SPI_SUPPORT_CLK_PLL_F160M        1
-// #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
-
-// Peripheral supports DIO, DOUT, QIO, or QOUT
-// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
-#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)  ({(void)host_id; 1;})
-
-#define SOC_MEMSPI_IS_INDEPENDENT       1
-#define SOC_SPI_MAX_PRE_DIVIDER         256
-
-/*-------------------------- SPI MEM CAPS ---------------------------------------*/
-// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
-// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
-// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
-// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
-// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
-// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
-// #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
-
-// TODO: [ESP32C5] IDF-8649
-#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
-
-/*-------------------------- SYSTIMER CAPS ----------------------------------*/
-// TODO: [ESP32C5] IDF-8707
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
-// #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event
-
-/*-------------------------- LP_TIMER CAPS ----------------------------------*/
-#define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
-#define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
-
-/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
-// #define SOC_TIMER_SUPPORT_ETM             (1)
-// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
-
-/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
-// #define SOC_MWDT_SUPPORT_XTAL              (1)
-
-/*-------------------------- TWAI CAPS ---------------------------------------*/
-// #define SOC_TWAI_CONTROLLER_NUM         2
-// #define SOC_TWAI_CLK_SUPPORT_XTAL       1
-// #define SOC_TWAI_BRP_MIN                2
-// #define SOC_TWAI_BRP_MAX                32768
-// #define SOC_TWAI_SUPPORTS_RX_STATUS     1
-
-/*-------------------------- eFuse CAPS----------------------------*/
-// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
-// #define SOC_EFUSE_DIS_PAD_JTAG 1
-// #define SOC_EFUSE_DIS_USB_JTAG 1
-// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
-// #define SOC_EFUSE_SOFT_DIS_JTAG 1
-// #define SOC_EFUSE_DIS_ICACHE 1
-#define SOC_EFUSE_ECDSA_KEY 1
-
-/*-------------------------- Secure Boot CAPS----------------------------*/
-#define SOC_SECURE_BOOT_V2_RSA              1
-#define SOC_SECURE_BOOT_V2_ECC              1
-#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
-#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS   1
-#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY  1
-
-/*-------------------------- Flash Encryption CAPS----------------------------*/
-#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (64)
-#define SOC_FLASH_ENCRYPTION_XTS_AES        1
-#define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
-
-/*------------------------ Anti DPA (Security) CAPS --------------------------*/
-// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED     1
-
-/*-------------------------- UART CAPS ---------------------------------------*/
-// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
-#define SOC_UART_NUM                    (3)
-#define SOC_UART_HP_NUM                 (2)
-#define SOC_UART_LP_NUM                 (1U)
-#define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
-#define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
-#define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
-#define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
-// #define SOC_UART_SUPPORT_RTC_CLK        (1)         // TODO: [ESP32C5] IDF-8642
-#define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
-#define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
-#define SOC_UART_HAS_LP_UART            (1)         /*!< Support LP UART */
-
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
-#define SOC_UART_SUPPORT_SLEEP_RETENTION   (1)         /*!< Support back up registers before sleep */
-
-/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
-#define SOC_COEX_HW_PTI                 (1)
-
-/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
-// #define SOC_EXTERNAL_COEX_ADVANCE              (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
-// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE       (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
-
-/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
-// #define SOC_PHY_DIG_REGS_MEM_SIZE       (21*4)
-
-/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
-#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
-
-/*-------------------------- Power Management CAPS ----------------------------*/
-// #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
-// #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
-#define SOC_PM_SUPPORT_CPU_PD           (1)
-#define SOC_PM_SUPPORT_MODEM_PD         (1)
-#define SOC_PM_SUPPORT_XTAL32K_PD       (1)
-#define SOC_PM_SUPPORT_RC32K_PD         (1)
-#define SOC_PM_SUPPORT_RC_FAST_PD       (1)
-#define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
-#define SOC_PM_SUPPORT_TOP_PD           (1)
-#define SOC_PM_SUPPORT_HP_AON_PD        (1)
-// #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
-#define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
-
-#define SOC_PM_SUPPORT_PMU_MODEM_STATE  (0)
-/* macro redefine for pass esp_wifi headers md5sum check */
-#define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
-
-#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
-
-#define SOC_PM_CPU_RETENTION_BY_SW          (1)
-#define SOC_PM_MODEM_RETENTION_BY_REGDMA    (1)
-// #define SOC_PM_RETENTION_HAS_CLOCK_BUG      (1)
-
-#define SOC_PM_PAU_LINK_NUM             (4)
-
-/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
-#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
-#define SOC_MODEM_CLOCK_IS_INDEPENDENT            (1)
-
-#define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
-#define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
-#define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
-
-#define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
-
-/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
-// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
-// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)
-// #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
-
-/*------------------------------------ WI-FI CAPS ------------------------------------*/
-#define SOC_WIFI_HW_TSF                     (1)    /*!< Support hardware TSF */
-#define SOC_WIFI_FTM_SUPPORT                (0)    /*!< Support FTM */
-#define SOC_WIFI_GCMP_SUPPORT               (1)    /*!< Support GCMP(GCMP128 and GCMP256) */
-#define SOC_WIFI_WAPI_SUPPORT               (1)    /*!< Support WAPI */
-#define SOC_WIFI_CSI_SUPPORT                (1)    /*!< Support CSI */
-#define SOC_WIFI_MESH_SUPPORT               (1)    /*!< Support WIFI MESH */
-#define SOC_WIFI_HE_SUPPORT                 (1)    /*!< Support Wi-Fi 6 in 2.4G */
-#define SOC_WIFI_HE_SUPPORT_5G              (1)    /*!< Support Wi-Fi 6 in 5G */
-
-/*---------------------------------- Bluetooth CAPS ----------------------------------*/
-#define SOC_BLE_SUPPORTED                   (1)    /*!< Support Bluetooth Low Energy hardware */
-#define SOC_BLE_MESH_SUPPORTED              (1)    /*!< Support BLE MESH */
-#define SOC_ESP_NIMBLE_CONTROLLER           (1)    /*!< Support BLE EMBEDDED controller V1 */
-#define SOC_BLE_50_SUPPORTED                (1)    /*!< Support Bluetooth 5.0 */
-#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED    (1)    /*!< Support BLE device privacy mode */
-#define SOC_BLE_POWER_CONTROL_SUPPORTED     (1)    /*!< Support Bluetooth Power Control */
-#define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED  (1)    /*!< Support For BLE Periodic Adv Enhancements */
-#define SOC_BLUFI_SUPPORTED                 (1)    /*!< Support BLUFI */
-#define SOC_BLE_MULTI_CONN_OPTIMIZATION     (1)    /*!< Support multiple connections optimization */
-
-/*------------------------------------- PHY CAPS -------------------------------------*/
-// #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
diff --git a/components/soc/esp32c5/beta3/include/soc/soc_etm_reg.h b/components/soc/esp32c5/beta3/include/soc/soc_etm_reg.h
deleted file mode 100644
index d5ca5417e7..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/soc_etm_reg.h
+++ /dev/null
@@ -1,6867 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SOC_ETM_CH_ENA_AD0_REG register
- *  Channel enable status register
- */
-#define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0)
-/** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0;
- *  Represents ch0 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED0    (BIT(0))
-#define SOC_ETM_CH_ENABLED0_M  (SOC_ETM_CH_ENABLED0_V << SOC_ETM_CH_ENABLED0_S)
-#define SOC_ETM_CH_ENABLED0_V  0x00000001U
-#define SOC_ETM_CH_ENABLED0_S  0
-/** SOC_ETM_CH_ENABLED1 : R/WTC/WTS; bitpos: [1]; default: 0;
- *  Represents ch1 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED1    (BIT(1))
-#define SOC_ETM_CH_ENABLED1_M  (SOC_ETM_CH_ENABLED1_V << SOC_ETM_CH_ENABLED1_S)
-#define SOC_ETM_CH_ENABLED1_V  0x00000001U
-#define SOC_ETM_CH_ENABLED1_S  1
-/** SOC_ETM_CH_ENABLED2 : R/WTC/WTS; bitpos: [2]; default: 0;
- *  Represents ch2 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED2    (BIT(2))
-#define SOC_ETM_CH_ENABLED2_M  (SOC_ETM_CH_ENABLED2_V << SOC_ETM_CH_ENABLED2_S)
-#define SOC_ETM_CH_ENABLED2_V  0x00000001U
-#define SOC_ETM_CH_ENABLED2_S  2
-/** SOC_ETM_CH_ENABLED3 : R/WTC/WTS; bitpos: [3]; default: 0;
- *  Represents ch3 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED3    (BIT(3))
-#define SOC_ETM_CH_ENABLED3_M  (SOC_ETM_CH_ENABLED3_V << SOC_ETM_CH_ENABLED3_S)
-#define SOC_ETM_CH_ENABLED3_V  0x00000001U
-#define SOC_ETM_CH_ENABLED3_S  3
-/** SOC_ETM_CH_ENABLED4 : R/WTC/WTS; bitpos: [4]; default: 0;
- *  Represents ch4 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED4    (BIT(4))
-#define SOC_ETM_CH_ENABLED4_M  (SOC_ETM_CH_ENABLED4_V << SOC_ETM_CH_ENABLED4_S)
-#define SOC_ETM_CH_ENABLED4_V  0x00000001U
-#define SOC_ETM_CH_ENABLED4_S  4
-/** SOC_ETM_CH_ENABLED5 : R/WTC/WTS; bitpos: [5]; default: 0;
- *  Represents ch5 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED5    (BIT(5))
-#define SOC_ETM_CH_ENABLED5_M  (SOC_ETM_CH_ENABLED5_V << SOC_ETM_CH_ENABLED5_S)
-#define SOC_ETM_CH_ENABLED5_V  0x00000001U
-#define SOC_ETM_CH_ENABLED5_S  5
-/** SOC_ETM_CH_ENABLED6 : R/WTC/WTS; bitpos: [6]; default: 0;
- *  Represents ch6 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED6    (BIT(6))
-#define SOC_ETM_CH_ENABLED6_M  (SOC_ETM_CH_ENABLED6_V << SOC_ETM_CH_ENABLED6_S)
-#define SOC_ETM_CH_ENABLED6_V  0x00000001U
-#define SOC_ETM_CH_ENABLED6_S  6
-/** SOC_ETM_CH_ENABLED7 : R/WTC/WTS; bitpos: [7]; default: 0;
- *  Represents ch7 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED7    (BIT(7))
-#define SOC_ETM_CH_ENABLED7_M  (SOC_ETM_CH_ENABLED7_V << SOC_ETM_CH_ENABLED7_S)
-#define SOC_ETM_CH_ENABLED7_V  0x00000001U
-#define SOC_ETM_CH_ENABLED7_S  7
-/** SOC_ETM_CH_ENABLED8 : R/WTC/WTS; bitpos: [8]; default: 0;
- *  Represents ch8 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED8    (BIT(8))
-#define SOC_ETM_CH_ENABLED8_M  (SOC_ETM_CH_ENABLED8_V << SOC_ETM_CH_ENABLED8_S)
-#define SOC_ETM_CH_ENABLED8_V  0x00000001U
-#define SOC_ETM_CH_ENABLED8_S  8
-/** SOC_ETM_CH_ENABLED9 : R/WTC/WTS; bitpos: [9]; default: 0;
- *  Represents ch9 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED9    (BIT(9))
-#define SOC_ETM_CH_ENABLED9_M  (SOC_ETM_CH_ENABLED9_V << SOC_ETM_CH_ENABLED9_S)
-#define SOC_ETM_CH_ENABLED9_V  0x00000001U
-#define SOC_ETM_CH_ENABLED9_S  9
-/** SOC_ETM_CH_ENABLED10 : R/WTC/WTS; bitpos: [10]; default: 0;
- *  Represents ch10 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED10    (BIT(10))
-#define SOC_ETM_CH_ENABLED10_M  (SOC_ETM_CH_ENABLED10_V << SOC_ETM_CH_ENABLED10_S)
-#define SOC_ETM_CH_ENABLED10_V  0x00000001U
-#define SOC_ETM_CH_ENABLED10_S  10
-/** SOC_ETM_CH_ENABLED11 : R/WTC/WTS; bitpos: [11]; default: 0;
- *  Represents ch11 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED11    (BIT(11))
-#define SOC_ETM_CH_ENABLED11_M  (SOC_ETM_CH_ENABLED11_V << SOC_ETM_CH_ENABLED11_S)
-#define SOC_ETM_CH_ENABLED11_V  0x00000001U
-#define SOC_ETM_CH_ENABLED11_S  11
-/** SOC_ETM_CH_ENABLED12 : R/WTC/WTS; bitpos: [12]; default: 0;
- *  Represents ch12 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED12    (BIT(12))
-#define SOC_ETM_CH_ENABLED12_M  (SOC_ETM_CH_ENABLED12_V << SOC_ETM_CH_ENABLED12_S)
-#define SOC_ETM_CH_ENABLED12_V  0x00000001U
-#define SOC_ETM_CH_ENABLED12_S  12
-/** SOC_ETM_CH_ENABLED13 : R/WTC/WTS; bitpos: [13]; default: 0;
- *  Represents ch13 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED13    (BIT(13))
-#define SOC_ETM_CH_ENABLED13_M  (SOC_ETM_CH_ENABLED13_V << SOC_ETM_CH_ENABLED13_S)
-#define SOC_ETM_CH_ENABLED13_V  0x00000001U
-#define SOC_ETM_CH_ENABLED13_S  13
-/** SOC_ETM_CH_ENABLED14 : R/WTC/WTS; bitpos: [14]; default: 0;
- *  Represents ch14 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED14    (BIT(14))
-#define SOC_ETM_CH_ENABLED14_M  (SOC_ETM_CH_ENABLED14_V << SOC_ETM_CH_ENABLED14_S)
-#define SOC_ETM_CH_ENABLED14_V  0x00000001U
-#define SOC_ETM_CH_ENABLED14_S  14
-/** SOC_ETM_CH_ENABLED15 : R/WTC/WTS; bitpos: [15]; default: 0;
- *  Represents ch15 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED15    (BIT(15))
-#define SOC_ETM_CH_ENABLED15_M  (SOC_ETM_CH_ENABLED15_V << SOC_ETM_CH_ENABLED15_S)
-#define SOC_ETM_CH_ENABLED15_V  0x00000001U
-#define SOC_ETM_CH_ENABLED15_S  15
-/** SOC_ETM_CH_ENABLED16 : R/WTC/WTS; bitpos: [16]; default: 0;
- *  Represents ch16 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED16    (BIT(16))
-#define SOC_ETM_CH_ENABLED16_M  (SOC_ETM_CH_ENABLED16_V << SOC_ETM_CH_ENABLED16_S)
-#define SOC_ETM_CH_ENABLED16_V  0x00000001U
-#define SOC_ETM_CH_ENABLED16_S  16
-/** SOC_ETM_CH_ENABLED17 : R/WTC/WTS; bitpos: [17]; default: 0;
- *  Represents ch17 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED17    (BIT(17))
-#define SOC_ETM_CH_ENABLED17_M  (SOC_ETM_CH_ENABLED17_V << SOC_ETM_CH_ENABLED17_S)
-#define SOC_ETM_CH_ENABLED17_V  0x00000001U
-#define SOC_ETM_CH_ENABLED17_S  17
-/** SOC_ETM_CH_ENABLED18 : R/WTC/WTS; bitpos: [18]; default: 0;
- *  Represents ch18 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED18    (BIT(18))
-#define SOC_ETM_CH_ENABLED18_M  (SOC_ETM_CH_ENABLED18_V << SOC_ETM_CH_ENABLED18_S)
-#define SOC_ETM_CH_ENABLED18_V  0x00000001U
-#define SOC_ETM_CH_ENABLED18_S  18
-/** SOC_ETM_CH_ENABLED19 : R/WTC/WTS; bitpos: [19]; default: 0;
- *  Represents ch19 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED19    (BIT(19))
-#define SOC_ETM_CH_ENABLED19_M  (SOC_ETM_CH_ENABLED19_V << SOC_ETM_CH_ENABLED19_S)
-#define SOC_ETM_CH_ENABLED19_V  0x00000001U
-#define SOC_ETM_CH_ENABLED19_S  19
-/** SOC_ETM_CH_ENABLED20 : R/WTC/WTS; bitpos: [20]; default: 0;
- *  Represents ch20 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED20    (BIT(20))
-#define SOC_ETM_CH_ENABLED20_M  (SOC_ETM_CH_ENABLED20_V << SOC_ETM_CH_ENABLED20_S)
-#define SOC_ETM_CH_ENABLED20_V  0x00000001U
-#define SOC_ETM_CH_ENABLED20_S  20
-/** SOC_ETM_CH_ENABLED21 : R/WTC/WTS; bitpos: [21]; default: 0;
- *  Represents ch21 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED21    (BIT(21))
-#define SOC_ETM_CH_ENABLED21_M  (SOC_ETM_CH_ENABLED21_V << SOC_ETM_CH_ENABLED21_S)
-#define SOC_ETM_CH_ENABLED21_V  0x00000001U
-#define SOC_ETM_CH_ENABLED21_S  21
-/** SOC_ETM_CH_ENABLED22 : R/WTC/WTS; bitpos: [22]; default: 0;
- *  Represents ch22 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED22    (BIT(22))
-#define SOC_ETM_CH_ENABLED22_M  (SOC_ETM_CH_ENABLED22_V << SOC_ETM_CH_ENABLED22_S)
-#define SOC_ETM_CH_ENABLED22_V  0x00000001U
-#define SOC_ETM_CH_ENABLED22_S  22
-/** SOC_ETM_CH_ENABLED23 : R/WTC/WTS; bitpos: [23]; default: 0;
- *  Represents ch23 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED23    (BIT(23))
-#define SOC_ETM_CH_ENABLED23_M  (SOC_ETM_CH_ENABLED23_V << SOC_ETM_CH_ENABLED23_S)
-#define SOC_ETM_CH_ENABLED23_V  0x00000001U
-#define SOC_ETM_CH_ENABLED23_S  23
-/** SOC_ETM_CH_ENABLED24 : R/WTC/WTS; bitpos: [24]; default: 0;
- *  Represents ch24 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED24    (BIT(24))
-#define SOC_ETM_CH_ENABLED24_M  (SOC_ETM_CH_ENABLED24_V << SOC_ETM_CH_ENABLED24_S)
-#define SOC_ETM_CH_ENABLED24_V  0x00000001U
-#define SOC_ETM_CH_ENABLED24_S  24
-/** SOC_ETM_CH_ENABLED25 : R/WTC/WTS; bitpos: [25]; default: 0;
- *  Represents ch25 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED25    (BIT(25))
-#define SOC_ETM_CH_ENABLED25_M  (SOC_ETM_CH_ENABLED25_V << SOC_ETM_CH_ENABLED25_S)
-#define SOC_ETM_CH_ENABLED25_V  0x00000001U
-#define SOC_ETM_CH_ENABLED25_S  25
-/** SOC_ETM_CH_ENABLED26 : R/WTC/WTS; bitpos: [26]; default: 0;
- *  Represents ch26 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED26    (BIT(26))
-#define SOC_ETM_CH_ENABLED26_M  (SOC_ETM_CH_ENABLED26_V << SOC_ETM_CH_ENABLED26_S)
-#define SOC_ETM_CH_ENABLED26_V  0x00000001U
-#define SOC_ETM_CH_ENABLED26_S  26
-/** SOC_ETM_CH_ENABLED27 : R/WTC/WTS; bitpos: [27]; default: 0;
- *  Represents ch27 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED27    (BIT(27))
-#define SOC_ETM_CH_ENABLED27_M  (SOC_ETM_CH_ENABLED27_V << SOC_ETM_CH_ENABLED27_S)
-#define SOC_ETM_CH_ENABLED27_V  0x00000001U
-#define SOC_ETM_CH_ENABLED27_S  27
-/** SOC_ETM_CH_ENABLED28 : R/WTC/WTS; bitpos: [28]; default: 0;
- *  Represents ch28 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED28    (BIT(28))
-#define SOC_ETM_CH_ENABLED28_M  (SOC_ETM_CH_ENABLED28_V << SOC_ETM_CH_ENABLED28_S)
-#define SOC_ETM_CH_ENABLED28_V  0x00000001U
-#define SOC_ETM_CH_ENABLED28_S  28
-/** SOC_ETM_CH_ENABLED29 : R/WTC/WTS; bitpos: [29]; default: 0;
- *  Represents ch29 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED29    (BIT(29))
-#define SOC_ETM_CH_ENABLED29_M  (SOC_ETM_CH_ENABLED29_V << SOC_ETM_CH_ENABLED29_S)
-#define SOC_ETM_CH_ENABLED29_V  0x00000001U
-#define SOC_ETM_CH_ENABLED29_S  29
-/** SOC_ETM_CH_ENABLED30 : R/WTC/WTS; bitpos: [30]; default: 0;
- *  Represents ch30 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED30    (BIT(30))
-#define SOC_ETM_CH_ENABLED30_M  (SOC_ETM_CH_ENABLED30_V << SOC_ETM_CH_ENABLED30_S)
-#define SOC_ETM_CH_ENABLED30_V  0x00000001U
-#define SOC_ETM_CH_ENABLED30_S  30
-/** SOC_ETM_CH_ENABLED31 : R/WTC/WTS; bitpos: [31]; default: 0;
- *  Represents ch31 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED31    (BIT(31))
-#define SOC_ETM_CH_ENABLED31_M  (SOC_ETM_CH_ENABLED31_V << SOC_ETM_CH_ENABLED31_S)
-#define SOC_ETM_CH_ENABLED31_V  0x00000001U
-#define SOC_ETM_CH_ENABLED31_S  31
-
-/** SOC_ETM_CH_ENA_AD0_SET_REG register
- *  Channel enable set register
- */
-#define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4)
-/** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE0    (BIT(0))
-#define SOC_ETM_CH_ENABLE0_M  (SOC_ETM_CH_ENABLE0_V << SOC_ETM_CH_ENABLE0_S)
-#define SOC_ETM_CH_ENABLE0_V  0x00000001U
-#define SOC_ETM_CH_ENABLE0_S  0
-/** SOC_ETM_CH_ENABLE1 : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE1    (BIT(1))
-#define SOC_ETM_CH_ENABLE1_M  (SOC_ETM_CH_ENABLE1_V << SOC_ETM_CH_ENABLE1_S)
-#define SOC_ETM_CH_ENABLE1_V  0x00000001U
-#define SOC_ETM_CH_ENABLE1_S  1
-/** SOC_ETM_CH_ENABLE2 : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE2    (BIT(2))
-#define SOC_ETM_CH_ENABLE2_M  (SOC_ETM_CH_ENABLE2_V << SOC_ETM_CH_ENABLE2_S)
-#define SOC_ETM_CH_ENABLE2_V  0x00000001U
-#define SOC_ETM_CH_ENABLE2_S  2
-/** SOC_ETM_CH_ENABLE3 : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE3    (BIT(3))
-#define SOC_ETM_CH_ENABLE3_M  (SOC_ETM_CH_ENABLE3_V << SOC_ETM_CH_ENABLE3_S)
-#define SOC_ETM_CH_ENABLE3_V  0x00000001U
-#define SOC_ETM_CH_ENABLE3_S  3
-/** SOC_ETM_CH_ENABLE4 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE4    (BIT(4))
-#define SOC_ETM_CH_ENABLE4_M  (SOC_ETM_CH_ENABLE4_V << SOC_ETM_CH_ENABLE4_S)
-#define SOC_ETM_CH_ENABLE4_V  0x00000001U
-#define SOC_ETM_CH_ENABLE4_S  4
-/** SOC_ETM_CH_ENABLE5 : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE5    (BIT(5))
-#define SOC_ETM_CH_ENABLE5_M  (SOC_ETM_CH_ENABLE5_V << SOC_ETM_CH_ENABLE5_S)
-#define SOC_ETM_CH_ENABLE5_V  0x00000001U
-#define SOC_ETM_CH_ENABLE5_S  5
-/** SOC_ETM_CH_ENABLE6 : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE6    (BIT(6))
-#define SOC_ETM_CH_ENABLE6_M  (SOC_ETM_CH_ENABLE6_V << SOC_ETM_CH_ENABLE6_S)
-#define SOC_ETM_CH_ENABLE6_V  0x00000001U
-#define SOC_ETM_CH_ENABLE6_S  6
-/** SOC_ETM_CH_ENABLE7 : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE7    (BIT(7))
-#define SOC_ETM_CH_ENABLE7_M  (SOC_ETM_CH_ENABLE7_V << SOC_ETM_CH_ENABLE7_S)
-#define SOC_ETM_CH_ENABLE7_V  0x00000001U
-#define SOC_ETM_CH_ENABLE7_S  7
-/** SOC_ETM_CH_ENABLE8 : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE8    (BIT(8))
-#define SOC_ETM_CH_ENABLE8_M  (SOC_ETM_CH_ENABLE8_V << SOC_ETM_CH_ENABLE8_S)
-#define SOC_ETM_CH_ENABLE8_V  0x00000001U
-#define SOC_ETM_CH_ENABLE8_S  8
-/** SOC_ETM_CH_ENABLE9 : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE9    (BIT(9))
-#define SOC_ETM_CH_ENABLE9_M  (SOC_ETM_CH_ENABLE9_V << SOC_ETM_CH_ENABLE9_S)
-#define SOC_ETM_CH_ENABLE9_V  0x00000001U
-#define SOC_ETM_CH_ENABLE9_S  9
-/** SOC_ETM_CH_ENABLE10 : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE10    (BIT(10))
-#define SOC_ETM_CH_ENABLE10_M  (SOC_ETM_CH_ENABLE10_V << SOC_ETM_CH_ENABLE10_S)
-#define SOC_ETM_CH_ENABLE10_V  0x00000001U
-#define SOC_ETM_CH_ENABLE10_S  10
-/** SOC_ETM_CH_ENABLE11 : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE11    (BIT(11))
-#define SOC_ETM_CH_ENABLE11_M  (SOC_ETM_CH_ENABLE11_V << SOC_ETM_CH_ENABLE11_S)
-#define SOC_ETM_CH_ENABLE11_V  0x00000001U
-#define SOC_ETM_CH_ENABLE11_S  11
-/** SOC_ETM_CH_ENABLE12 : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE12    (BIT(12))
-#define SOC_ETM_CH_ENABLE12_M  (SOC_ETM_CH_ENABLE12_V << SOC_ETM_CH_ENABLE12_S)
-#define SOC_ETM_CH_ENABLE12_V  0x00000001U
-#define SOC_ETM_CH_ENABLE12_S  12
-/** SOC_ETM_CH_ENABLE13 : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE13    (BIT(13))
-#define SOC_ETM_CH_ENABLE13_M  (SOC_ETM_CH_ENABLE13_V << SOC_ETM_CH_ENABLE13_S)
-#define SOC_ETM_CH_ENABLE13_V  0x00000001U
-#define SOC_ETM_CH_ENABLE13_S  13
-/** SOC_ETM_CH_ENABLE14 : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE14    (BIT(14))
-#define SOC_ETM_CH_ENABLE14_M  (SOC_ETM_CH_ENABLE14_V << SOC_ETM_CH_ENABLE14_S)
-#define SOC_ETM_CH_ENABLE14_V  0x00000001U
-#define SOC_ETM_CH_ENABLE14_S  14
-/** SOC_ETM_CH_ENABLE15 : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE15    (BIT(15))
-#define SOC_ETM_CH_ENABLE15_M  (SOC_ETM_CH_ENABLE15_V << SOC_ETM_CH_ENABLE15_S)
-#define SOC_ETM_CH_ENABLE15_V  0x00000001U
-#define SOC_ETM_CH_ENABLE15_S  15
-/** SOC_ETM_CH_ENABLE16 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE16    (BIT(16))
-#define SOC_ETM_CH_ENABLE16_M  (SOC_ETM_CH_ENABLE16_V << SOC_ETM_CH_ENABLE16_S)
-#define SOC_ETM_CH_ENABLE16_V  0x00000001U
-#define SOC_ETM_CH_ENABLE16_S  16
-/** SOC_ETM_CH_ENABLE17 : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE17    (BIT(17))
-#define SOC_ETM_CH_ENABLE17_M  (SOC_ETM_CH_ENABLE17_V << SOC_ETM_CH_ENABLE17_S)
-#define SOC_ETM_CH_ENABLE17_V  0x00000001U
-#define SOC_ETM_CH_ENABLE17_S  17
-/** SOC_ETM_CH_ENABLE18 : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE18    (BIT(18))
-#define SOC_ETM_CH_ENABLE18_M  (SOC_ETM_CH_ENABLE18_V << SOC_ETM_CH_ENABLE18_S)
-#define SOC_ETM_CH_ENABLE18_V  0x00000001U
-#define SOC_ETM_CH_ENABLE18_S  18
-/** SOC_ETM_CH_ENABLE19 : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE19    (BIT(19))
-#define SOC_ETM_CH_ENABLE19_M  (SOC_ETM_CH_ENABLE19_V << SOC_ETM_CH_ENABLE19_S)
-#define SOC_ETM_CH_ENABLE19_V  0x00000001U
-#define SOC_ETM_CH_ENABLE19_S  19
-/** SOC_ETM_CH_ENABLE20 : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE20    (BIT(20))
-#define SOC_ETM_CH_ENABLE20_M  (SOC_ETM_CH_ENABLE20_V << SOC_ETM_CH_ENABLE20_S)
-#define SOC_ETM_CH_ENABLE20_V  0x00000001U
-#define SOC_ETM_CH_ENABLE20_S  20
-/** SOC_ETM_CH_ENABLE21 : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE21    (BIT(21))
-#define SOC_ETM_CH_ENABLE21_M  (SOC_ETM_CH_ENABLE21_V << SOC_ETM_CH_ENABLE21_S)
-#define SOC_ETM_CH_ENABLE21_V  0x00000001U
-#define SOC_ETM_CH_ENABLE21_S  21
-/** SOC_ETM_CH_ENABLE22 : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE22    (BIT(22))
-#define SOC_ETM_CH_ENABLE22_M  (SOC_ETM_CH_ENABLE22_V << SOC_ETM_CH_ENABLE22_S)
-#define SOC_ETM_CH_ENABLE22_V  0x00000001U
-#define SOC_ETM_CH_ENABLE22_S  22
-/** SOC_ETM_CH_ENABLE23 : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE23    (BIT(23))
-#define SOC_ETM_CH_ENABLE23_M  (SOC_ETM_CH_ENABLE23_V << SOC_ETM_CH_ENABLE23_S)
-#define SOC_ETM_CH_ENABLE23_V  0x00000001U
-#define SOC_ETM_CH_ENABLE23_S  23
-/** SOC_ETM_CH_ENABLE24 : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE24    (BIT(24))
-#define SOC_ETM_CH_ENABLE24_M  (SOC_ETM_CH_ENABLE24_V << SOC_ETM_CH_ENABLE24_S)
-#define SOC_ETM_CH_ENABLE24_V  0x00000001U
-#define SOC_ETM_CH_ENABLE24_S  24
-/** SOC_ETM_CH_ENABLE25 : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE25    (BIT(25))
-#define SOC_ETM_CH_ENABLE25_M  (SOC_ETM_CH_ENABLE25_V << SOC_ETM_CH_ENABLE25_S)
-#define SOC_ETM_CH_ENABLE25_V  0x00000001U
-#define SOC_ETM_CH_ENABLE25_S  25
-/** SOC_ETM_CH_ENABLE26 : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE26    (BIT(26))
-#define SOC_ETM_CH_ENABLE26_M  (SOC_ETM_CH_ENABLE26_V << SOC_ETM_CH_ENABLE26_S)
-#define SOC_ETM_CH_ENABLE26_V  0x00000001U
-#define SOC_ETM_CH_ENABLE26_S  26
-/** SOC_ETM_CH_ENABLE27 : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE27    (BIT(27))
-#define SOC_ETM_CH_ENABLE27_M  (SOC_ETM_CH_ENABLE27_V << SOC_ETM_CH_ENABLE27_S)
-#define SOC_ETM_CH_ENABLE27_V  0x00000001U
-#define SOC_ETM_CH_ENABLE27_S  27
-/** SOC_ETM_CH_ENABLE28 : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE28    (BIT(28))
-#define SOC_ETM_CH_ENABLE28_M  (SOC_ETM_CH_ENABLE28_V << SOC_ETM_CH_ENABLE28_S)
-#define SOC_ETM_CH_ENABLE28_V  0x00000001U
-#define SOC_ETM_CH_ENABLE28_S  28
-/** SOC_ETM_CH_ENABLE29 : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE29    (BIT(29))
-#define SOC_ETM_CH_ENABLE29_M  (SOC_ETM_CH_ENABLE29_V << SOC_ETM_CH_ENABLE29_S)
-#define SOC_ETM_CH_ENABLE29_V  0x00000001U
-#define SOC_ETM_CH_ENABLE29_S  29
-/** SOC_ETM_CH_ENABLE30 : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE30    (BIT(30))
-#define SOC_ETM_CH_ENABLE30_M  (SOC_ETM_CH_ENABLE30_V << SOC_ETM_CH_ENABLE30_S)
-#define SOC_ETM_CH_ENABLE30_V  0x00000001U
-#define SOC_ETM_CH_ENABLE30_S  30
-/** SOC_ETM_CH_ENABLE31 : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE31    (BIT(31))
-#define SOC_ETM_CH_ENABLE31_M  (SOC_ETM_CH_ENABLE31_V << SOC_ETM_CH_ENABLE31_S)
-#define SOC_ETM_CH_ENABLE31_V  0x00000001U
-#define SOC_ETM_CH_ENABLE31_S  31
-
-/** SOC_ETM_CH_ENA_AD0_CLR_REG register
- *  Channel enable clear register
- */
-#define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8)
-/** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE0    (BIT(0))
-#define SOC_ETM_CH_DISABLE0_M  (SOC_ETM_CH_DISABLE0_V << SOC_ETM_CH_DISABLE0_S)
-#define SOC_ETM_CH_DISABLE0_V  0x00000001U
-#define SOC_ETM_CH_DISABLE0_S  0
-/** SOC_ETM_CH_DISABLE1 : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE1    (BIT(1))
-#define SOC_ETM_CH_DISABLE1_M  (SOC_ETM_CH_DISABLE1_V << SOC_ETM_CH_DISABLE1_S)
-#define SOC_ETM_CH_DISABLE1_V  0x00000001U
-#define SOC_ETM_CH_DISABLE1_S  1
-/** SOC_ETM_CH_DISABLE2 : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE2    (BIT(2))
-#define SOC_ETM_CH_DISABLE2_M  (SOC_ETM_CH_DISABLE2_V << SOC_ETM_CH_DISABLE2_S)
-#define SOC_ETM_CH_DISABLE2_V  0x00000001U
-#define SOC_ETM_CH_DISABLE2_S  2
-/** SOC_ETM_CH_DISABLE3 : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE3    (BIT(3))
-#define SOC_ETM_CH_DISABLE3_M  (SOC_ETM_CH_DISABLE3_V << SOC_ETM_CH_DISABLE3_S)
-#define SOC_ETM_CH_DISABLE3_V  0x00000001U
-#define SOC_ETM_CH_DISABLE3_S  3
-/** SOC_ETM_CH_DISABLE4 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE4    (BIT(4))
-#define SOC_ETM_CH_DISABLE4_M  (SOC_ETM_CH_DISABLE4_V << SOC_ETM_CH_DISABLE4_S)
-#define SOC_ETM_CH_DISABLE4_V  0x00000001U
-#define SOC_ETM_CH_DISABLE4_S  4
-/** SOC_ETM_CH_DISABLE5 : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE5    (BIT(5))
-#define SOC_ETM_CH_DISABLE5_M  (SOC_ETM_CH_DISABLE5_V << SOC_ETM_CH_DISABLE5_S)
-#define SOC_ETM_CH_DISABLE5_V  0x00000001U
-#define SOC_ETM_CH_DISABLE5_S  5
-/** SOC_ETM_CH_DISABLE6 : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE6    (BIT(6))
-#define SOC_ETM_CH_DISABLE6_M  (SOC_ETM_CH_DISABLE6_V << SOC_ETM_CH_DISABLE6_S)
-#define SOC_ETM_CH_DISABLE6_V  0x00000001U
-#define SOC_ETM_CH_DISABLE6_S  6
-/** SOC_ETM_CH_DISABLE7 : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE7    (BIT(7))
-#define SOC_ETM_CH_DISABLE7_M  (SOC_ETM_CH_DISABLE7_V << SOC_ETM_CH_DISABLE7_S)
-#define SOC_ETM_CH_DISABLE7_V  0x00000001U
-#define SOC_ETM_CH_DISABLE7_S  7
-/** SOC_ETM_CH_DISABLE8 : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE8    (BIT(8))
-#define SOC_ETM_CH_DISABLE8_M  (SOC_ETM_CH_DISABLE8_V << SOC_ETM_CH_DISABLE8_S)
-#define SOC_ETM_CH_DISABLE8_V  0x00000001U
-#define SOC_ETM_CH_DISABLE8_S  8
-/** SOC_ETM_CH_DISABLE9 : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE9    (BIT(9))
-#define SOC_ETM_CH_DISABLE9_M  (SOC_ETM_CH_DISABLE9_V << SOC_ETM_CH_DISABLE9_S)
-#define SOC_ETM_CH_DISABLE9_V  0x00000001U
-#define SOC_ETM_CH_DISABLE9_S  9
-/** SOC_ETM_CH_DISABLE10 : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE10    (BIT(10))
-#define SOC_ETM_CH_DISABLE10_M  (SOC_ETM_CH_DISABLE10_V << SOC_ETM_CH_DISABLE10_S)
-#define SOC_ETM_CH_DISABLE10_V  0x00000001U
-#define SOC_ETM_CH_DISABLE10_S  10
-/** SOC_ETM_CH_DISABLE11 : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE11    (BIT(11))
-#define SOC_ETM_CH_DISABLE11_M  (SOC_ETM_CH_DISABLE11_V << SOC_ETM_CH_DISABLE11_S)
-#define SOC_ETM_CH_DISABLE11_V  0x00000001U
-#define SOC_ETM_CH_DISABLE11_S  11
-/** SOC_ETM_CH_DISABLE12 : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE12    (BIT(12))
-#define SOC_ETM_CH_DISABLE12_M  (SOC_ETM_CH_DISABLE12_V << SOC_ETM_CH_DISABLE12_S)
-#define SOC_ETM_CH_DISABLE12_V  0x00000001U
-#define SOC_ETM_CH_DISABLE12_S  12
-/** SOC_ETM_CH_DISABLE13 : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE13    (BIT(13))
-#define SOC_ETM_CH_DISABLE13_M  (SOC_ETM_CH_DISABLE13_V << SOC_ETM_CH_DISABLE13_S)
-#define SOC_ETM_CH_DISABLE13_V  0x00000001U
-#define SOC_ETM_CH_DISABLE13_S  13
-/** SOC_ETM_CH_DISABLE14 : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE14    (BIT(14))
-#define SOC_ETM_CH_DISABLE14_M  (SOC_ETM_CH_DISABLE14_V << SOC_ETM_CH_DISABLE14_S)
-#define SOC_ETM_CH_DISABLE14_V  0x00000001U
-#define SOC_ETM_CH_DISABLE14_S  14
-/** SOC_ETM_CH_DISABLE15 : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE15    (BIT(15))
-#define SOC_ETM_CH_DISABLE15_M  (SOC_ETM_CH_DISABLE15_V << SOC_ETM_CH_DISABLE15_S)
-#define SOC_ETM_CH_DISABLE15_V  0x00000001U
-#define SOC_ETM_CH_DISABLE15_S  15
-/** SOC_ETM_CH_DISABLE16 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE16    (BIT(16))
-#define SOC_ETM_CH_DISABLE16_M  (SOC_ETM_CH_DISABLE16_V << SOC_ETM_CH_DISABLE16_S)
-#define SOC_ETM_CH_DISABLE16_V  0x00000001U
-#define SOC_ETM_CH_DISABLE16_S  16
-/** SOC_ETM_CH_DISABLE17 : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE17    (BIT(17))
-#define SOC_ETM_CH_DISABLE17_M  (SOC_ETM_CH_DISABLE17_V << SOC_ETM_CH_DISABLE17_S)
-#define SOC_ETM_CH_DISABLE17_V  0x00000001U
-#define SOC_ETM_CH_DISABLE17_S  17
-/** SOC_ETM_CH_DISABLE18 : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE18    (BIT(18))
-#define SOC_ETM_CH_DISABLE18_M  (SOC_ETM_CH_DISABLE18_V << SOC_ETM_CH_DISABLE18_S)
-#define SOC_ETM_CH_DISABLE18_V  0x00000001U
-#define SOC_ETM_CH_DISABLE18_S  18
-/** SOC_ETM_CH_DISABLE19 : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE19    (BIT(19))
-#define SOC_ETM_CH_DISABLE19_M  (SOC_ETM_CH_DISABLE19_V << SOC_ETM_CH_DISABLE19_S)
-#define SOC_ETM_CH_DISABLE19_V  0x00000001U
-#define SOC_ETM_CH_DISABLE19_S  19
-/** SOC_ETM_CH_DISABLE20 : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE20    (BIT(20))
-#define SOC_ETM_CH_DISABLE20_M  (SOC_ETM_CH_DISABLE20_V << SOC_ETM_CH_DISABLE20_S)
-#define SOC_ETM_CH_DISABLE20_V  0x00000001U
-#define SOC_ETM_CH_DISABLE20_S  20
-/** SOC_ETM_CH_DISABLE21 : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE21    (BIT(21))
-#define SOC_ETM_CH_DISABLE21_M  (SOC_ETM_CH_DISABLE21_V << SOC_ETM_CH_DISABLE21_S)
-#define SOC_ETM_CH_DISABLE21_V  0x00000001U
-#define SOC_ETM_CH_DISABLE21_S  21
-/** SOC_ETM_CH_DISABLE22 : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE22    (BIT(22))
-#define SOC_ETM_CH_DISABLE22_M  (SOC_ETM_CH_DISABLE22_V << SOC_ETM_CH_DISABLE22_S)
-#define SOC_ETM_CH_DISABLE22_V  0x00000001U
-#define SOC_ETM_CH_DISABLE22_S  22
-/** SOC_ETM_CH_DISABLE23 : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE23    (BIT(23))
-#define SOC_ETM_CH_DISABLE23_M  (SOC_ETM_CH_DISABLE23_V << SOC_ETM_CH_DISABLE23_S)
-#define SOC_ETM_CH_DISABLE23_V  0x00000001U
-#define SOC_ETM_CH_DISABLE23_S  23
-/** SOC_ETM_CH_DISABLE24 : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE24    (BIT(24))
-#define SOC_ETM_CH_DISABLE24_M  (SOC_ETM_CH_DISABLE24_V << SOC_ETM_CH_DISABLE24_S)
-#define SOC_ETM_CH_DISABLE24_V  0x00000001U
-#define SOC_ETM_CH_DISABLE24_S  24
-/** SOC_ETM_CH_DISABLE25 : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE25    (BIT(25))
-#define SOC_ETM_CH_DISABLE25_M  (SOC_ETM_CH_DISABLE25_V << SOC_ETM_CH_DISABLE25_S)
-#define SOC_ETM_CH_DISABLE25_V  0x00000001U
-#define SOC_ETM_CH_DISABLE25_S  25
-/** SOC_ETM_CH_DISABLE26 : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE26    (BIT(26))
-#define SOC_ETM_CH_DISABLE26_M  (SOC_ETM_CH_DISABLE26_V << SOC_ETM_CH_DISABLE26_S)
-#define SOC_ETM_CH_DISABLE26_V  0x00000001U
-#define SOC_ETM_CH_DISABLE26_S  26
-/** SOC_ETM_CH_DISABLE27 : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE27    (BIT(27))
-#define SOC_ETM_CH_DISABLE27_M  (SOC_ETM_CH_DISABLE27_V << SOC_ETM_CH_DISABLE27_S)
-#define SOC_ETM_CH_DISABLE27_V  0x00000001U
-#define SOC_ETM_CH_DISABLE27_S  27
-/** SOC_ETM_CH_DISABLE28 : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE28    (BIT(28))
-#define SOC_ETM_CH_DISABLE28_M  (SOC_ETM_CH_DISABLE28_V << SOC_ETM_CH_DISABLE28_S)
-#define SOC_ETM_CH_DISABLE28_V  0x00000001U
-#define SOC_ETM_CH_DISABLE28_S  28
-/** SOC_ETM_CH_DISABLE29 : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE29    (BIT(29))
-#define SOC_ETM_CH_DISABLE29_M  (SOC_ETM_CH_DISABLE29_V << SOC_ETM_CH_DISABLE29_S)
-#define SOC_ETM_CH_DISABLE29_V  0x00000001U
-#define SOC_ETM_CH_DISABLE29_S  29
-/** SOC_ETM_CH_DISABLE30 : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE30    (BIT(30))
-#define SOC_ETM_CH_DISABLE30_M  (SOC_ETM_CH_DISABLE30_V << SOC_ETM_CH_DISABLE30_S)
-#define SOC_ETM_CH_DISABLE30_V  0x00000001U
-#define SOC_ETM_CH_DISABLE30_S  30
-/** SOC_ETM_CH_DISABLE31 : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE31    (BIT(31))
-#define SOC_ETM_CH_DISABLE31_M  (SOC_ETM_CH_DISABLE31_V << SOC_ETM_CH_DISABLE31_S)
-#define SOC_ETM_CH_DISABLE31_V  0x00000001U
-#define SOC_ETM_CH_DISABLE31_S  31
-
-/** SOC_ETM_CH_ENA_AD1_REG register
- *  Channel enable status register
- */
-#define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc)
-/** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0;
- *  Represents ch32 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED32    (BIT(0))
-#define SOC_ETM_CH_ENABLED32_M  (SOC_ETM_CH_ENABLED32_V << SOC_ETM_CH_ENABLED32_S)
-#define SOC_ETM_CH_ENABLED32_V  0x00000001U
-#define SOC_ETM_CH_ENABLED32_S  0
-/** SOC_ETM_CH_ENABLED33 : R/WTC/WTS; bitpos: [1]; default: 0;
- *  Represents ch33 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED33    (BIT(1))
-#define SOC_ETM_CH_ENABLED33_M  (SOC_ETM_CH_ENABLED33_V << SOC_ETM_CH_ENABLED33_S)
-#define SOC_ETM_CH_ENABLED33_V  0x00000001U
-#define SOC_ETM_CH_ENABLED33_S  1
-/** SOC_ETM_CH_ENABLED34 : R/WTC/WTS; bitpos: [2]; default: 0;
- *  Represents ch34 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED34    (BIT(2))
-#define SOC_ETM_CH_ENABLED34_M  (SOC_ETM_CH_ENABLED34_V << SOC_ETM_CH_ENABLED34_S)
-#define SOC_ETM_CH_ENABLED34_V  0x00000001U
-#define SOC_ETM_CH_ENABLED34_S  2
-/** SOC_ETM_CH_ENABLED35 : R/WTC/WTS; bitpos: [3]; default: 0;
- *  Represents ch35 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED35    (BIT(3))
-#define SOC_ETM_CH_ENABLED35_M  (SOC_ETM_CH_ENABLED35_V << SOC_ETM_CH_ENABLED35_S)
-#define SOC_ETM_CH_ENABLED35_V  0x00000001U
-#define SOC_ETM_CH_ENABLED35_S  3
-/** SOC_ETM_CH_ENABLED36 : R/WTC/WTS; bitpos: [4]; default: 0;
- *  Represents ch36 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED36    (BIT(4))
-#define SOC_ETM_CH_ENABLED36_M  (SOC_ETM_CH_ENABLED36_V << SOC_ETM_CH_ENABLED36_S)
-#define SOC_ETM_CH_ENABLED36_V  0x00000001U
-#define SOC_ETM_CH_ENABLED36_S  4
-/** SOC_ETM_CH_ENABLED37 : R/WTC/WTS; bitpos: [5]; default: 0;
- *  Represents ch37 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED37    (BIT(5))
-#define SOC_ETM_CH_ENABLED37_M  (SOC_ETM_CH_ENABLED37_V << SOC_ETM_CH_ENABLED37_S)
-#define SOC_ETM_CH_ENABLED37_V  0x00000001U
-#define SOC_ETM_CH_ENABLED37_S  5
-/** SOC_ETM_CH_ENABLED38 : R/WTC/WTS; bitpos: [6]; default: 0;
- *  Represents ch38 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED38    (BIT(6))
-#define SOC_ETM_CH_ENABLED38_M  (SOC_ETM_CH_ENABLED38_V << SOC_ETM_CH_ENABLED38_S)
-#define SOC_ETM_CH_ENABLED38_V  0x00000001U
-#define SOC_ETM_CH_ENABLED38_S  6
-/** SOC_ETM_CH_ENABLED39 : R/WTC/WTS; bitpos: [7]; default: 0;
- *  Represents ch39 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED39    (BIT(7))
-#define SOC_ETM_CH_ENABLED39_M  (SOC_ETM_CH_ENABLED39_V << SOC_ETM_CH_ENABLED39_S)
-#define SOC_ETM_CH_ENABLED39_V  0x00000001U
-#define SOC_ETM_CH_ENABLED39_S  7
-/** SOC_ETM_CH_ENABLED40 : R/WTC/WTS; bitpos: [8]; default: 0;
- *  Represents ch40 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED40    (BIT(8))
-#define SOC_ETM_CH_ENABLED40_M  (SOC_ETM_CH_ENABLED40_V << SOC_ETM_CH_ENABLED40_S)
-#define SOC_ETM_CH_ENABLED40_V  0x00000001U
-#define SOC_ETM_CH_ENABLED40_S  8
-/** SOC_ETM_CH_ENABLED41 : R/WTC/WTS; bitpos: [9]; default: 0;
- *  Represents ch41 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED41    (BIT(9))
-#define SOC_ETM_CH_ENABLED41_M  (SOC_ETM_CH_ENABLED41_V << SOC_ETM_CH_ENABLED41_S)
-#define SOC_ETM_CH_ENABLED41_V  0x00000001U
-#define SOC_ETM_CH_ENABLED41_S  9
-/** SOC_ETM_CH_ENABLED42 : R/WTC/WTS; bitpos: [10]; default: 0;
- *  Represents ch42 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED42    (BIT(10))
-#define SOC_ETM_CH_ENABLED42_M  (SOC_ETM_CH_ENABLED42_V << SOC_ETM_CH_ENABLED42_S)
-#define SOC_ETM_CH_ENABLED42_V  0x00000001U
-#define SOC_ETM_CH_ENABLED42_S  10
-/** SOC_ETM_CH_ENABLED43 : R/WTC/WTS; bitpos: [11]; default: 0;
- *  Represents ch43 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED43    (BIT(11))
-#define SOC_ETM_CH_ENABLED43_M  (SOC_ETM_CH_ENABLED43_V << SOC_ETM_CH_ENABLED43_S)
-#define SOC_ETM_CH_ENABLED43_V  0x00000001U
-#define SOC_ETM_CH_ENABLED43_S  11
-/** SOC_ETM_CH_ENABLED44 : R/WTC/WTS; bitpos: [12]; default: 0;
- *  Represents ch44 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED44    (BIT(12))
-#define SOC_ETM_CH_ENABLED44_M  (SOC_ETM_CH_ENABLED44_V << SOC_ETM_CH_ENABLED44_S)
-#define SOC_ETM_CH_ENABLED44_V  0x00000001U
-#define SOC_ETM_CH_ENABLED44_S  12
-/** SOC_ETM_CH_ENABLED45 : R/WTC/WTS; bitpos: [13]; default: 0;
- *  Represents ch45 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED45    (BIT(13))
-#define SOC_ETM_CH_ENABLED45_M  (SOC_ETM_CH_ENABLED45_V << SOC_ETM_CH_ENABLED45_S)
-#define SOC_ETM_CH_ENABLED45_V  0x00000001U
-#define SOC_ETM_CH_ENABLED45_S  13
-/** SOC_ETM_CH_ENABLED46 : R/WTC/WTS; bitpos: [14]; default: 0;
- *  Represents ch46 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED46    (BIT(14))
-#define SOC_ETM_CH_ENABLED46_M  (SOC_ETM_CH_ENABLED46_V << SOC_ETM_CH_ENABLED46_S)
-#define SOC_ETM_CH_ENABLED46_V  0x00000001U
-#define SOC_ETM_CH_ENABLED46_S  14
-/** SOC_ETM_CH_ENABLED47 : R/WTC/WTS; bitpos: [15]; default: 0;
- *  Represents ch47 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED47    (BIT(15))
-#define SOC_ETM_CH_ENABLED47_M  (SOC_ETM_CH_ENABLED47_V << SOC_ETM_CH_ENABLED47_S)
-#define SOC_ETM_CH_ENABLED47_V  0x00000001U
-#define SOC_ETM_CH_ENABLED47_S  15
-/** SOC_ETM_CH_ENABLED48 : R/WTC/WTS; bitpos: [16]; default: 0;
- *  Represents ch48 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED48    (BIT(16))
-#define SOC_ETM_CH_ENABLED48_M  (SOC_ETM_CH_ENABLED48_V << SOC_ETM_CH_ENABLED48_S)
-#define SOC_ETM_CH_ENABLED48_V  0x00000001U
-#define SOC_ETM_CH_ENABLED48_S  16
-/** SOC_ETM_CH_ENABLED49 : R/WTC/WTS; bitpos: [17]; default: 0;
- *  Represents ch49 enable status.\\0: Disable\\1: Enable
- */
-#define SOC_ETM_CH_ENABLED49    (BIT(17))
-#define SOC_ETM_CH_ENABLED49_M  (SOC_ETM_CH_ENABLED49_V << SOC_ETM_CH_ENABLED49_S)
-#define SOC_ETM_CH_ENABLED49_V  0x00000001U
-#define SOC_ETM_CH_ENABLED49_S  17
-
-/** SOC_ETM_CH_ENA_AD1_SET_REG register
- *  Channel enable set register
- */
-#define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10)
-/** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE32    (BIT(0))
-#define SOC_ETM_CH_ENABLE32_M  (SOC_ETM_CH_ENABLE32_V << SOC_ETM_CH_ENABLE32_S)
-#define SOC_ETM_CH_ENABLE32_V  0x00000001U
-#define SOC_ETM_CH_ENABLE32_S  0
-/** SOC_ETM_CH_ENABLE33 : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE33    (BIT(1))
-#define SOC_ETM_CH_ENABLE33_M  (SOC_ETM_CH_ENABLE33_V << SOC_ETM_CH_ENABLE33_S)
-#define SOC_ETM_CH_ENABLE33_V  0x00000001U
-#define SOC_ETM_CH_ENABLE33_S  1
-/** SOC_ETM_CH_ENABLE34 : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE34    (BIT(2))
-#define SOC_ETM_CH_ENABLE34_M  (SOC_ETM_CH_ENABLE34_V << SOC_ETM_CH_ENABLE34_S)
-#define SOC_ETM_CH_ENABLE34_V  0x00000001U
-#define SOC_ETM_CH_ENABLE34_S  2
-/** SOC_ETM_CH_ENABLE35 : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE35    (BIT(3))
-#define SOC_ETM_CH_ENABLE35_M  (SOC_ETM_CH_ENABLE35_V << SOC_ETM_CH_ENABLE35_S)
-#define SOC_ETM_CH_ENABLE35_V  0x00000001U
-#define SOC_ETM_CH_ENABLE35_S  3
-/** SOC_ETM_CH_ENABLE36 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE36    (BIT(4))
-#define SOC_ETM_CH_ENABLE36_M  (SOC_ETM_CH_ENABLE36_V << SOC_ETM_CH_ENABLE36_S)
-#define SOC_ETM_CH_ENABLE36_V  0x00000001U
-#define SOC_ETM_CH_ENABLE36_S  4
-/** SOC_ETM_CH_ENABLE37 : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE37    (BIT(5))
-#define SOC_ETM_CH_ENABLE37_M  (SOC_ETM_CH_ENABLE37_V << SOC_ETM_CH_ENABLE37_S)
-#define SOC_ETM_CH_ENABLE37_V  0x00000001U
-#define SOC_ETM_CH_ENABLE37_S  5
-/** SOC_ETM_CH_ENABLE38 : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE38    (BIT(6))
-#define SOC_ETM_CH_ENABLE38_M  (SOC_ETM_CH_ENABLE38_V << SOC_ETM_CH_ENABLE38_S)
-#define SOC_ETM_CH_ENABLE38_V  0x00000001U
-#define SOC_ETM_CH_ENABLE38_S  6
-/** SOC_ETM_CH_ENABLE39 : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE39    (BIT(7))
-#define SOC_ETM_CH_ENABLE39_M  (SOC_ETM_CH_ENABLE39_V << SOC_ETM_CH_ENABLE39_S)
-#define SOC_ETM_CH_ENABLE39_V  0x00000001U
-#define SOC_ETM_CH_ENABLE39_S  7
-/** SOC_ETM_CH_ENABLE40 : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE40    (BIT(8))
-#define SOC_ETM_CH_ENABLE40_M  (SOC_ETM_CH_ENABLE40_V << SOC_ETM_CH_ENABLE40_S)
-#define SOC_ETM_CH_ENABLE40_V  0x00000001U
-#define SOC_ETM_CH_ENABLE40_S  8
-/** SOC_ETM_CH_ENABLE41 : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE41    (BIT(9))
-#define SOC_ETM_CH_ENABLE41_M  (SOC_ETM_CH_ENABLE41_V << SOC_ETM_CH_ENABLE41_S)
-#define SOC_ETM_CH_ENABLE41_V  0x00000001U
-#define SOC_ETM_CH_ENABLE41_S  9
-/** SOC_ETM_CH_ENABLE42 : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE42    (BIT(10))
-#define SOC_ETM_CH_ENABLE42_M  (SOC_ETM_CH_ENABLE42_V << SOC_ETM_CH_ENABLE42_S)
-#define SOC_ETM_CH_ENABLE42_V  0x00000001U
-#define SOC_ETM_CH_ENABLE42_S  10
-/** SOC_ETM_CH_ENABLE43 : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE43    (BIT(11))
-#define SOC_ETM_CH_ENABLE43_M  (SOC_ETM_CH_ENABLE43_V << SOC_ETM_CH_ENABLE43_S)
-#define SOC_ETM_CH_ENABLE43_V  0x00000001U
-#define SOC_ETM_CH_ENABLE43_S  11
-/** SOC_ETM_CH_ENABLE44 : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE44    (BIT(12))
-#define SOC_ETM_CH_ENABLE44_M  (SOC_ETM_CH_ENABLE44_V << SOC_ETM_CH_ENABLE44_S)
-#define SOC_ETM_CH_ENABLE44_V  0x00000001U
-#define SOC_ETM_CH_ENABLE44_S  12
-/** SOC_ETM_CH_ENABLE45 : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE45    (BIT(13))
-#define SOC_ETM_CH_ENABLE45_M  (SOC_ETM_CH_ENABLE45_V << SOC_ETM_CH_ENABLE45_S)
-#define SOC_ETM_CH_ENABLE45_V  0x00000001U
-#define SOC_ETM_CH_ENABLE45_S  13
-/** SOC_ETM_CH_ENABLE46 : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE46    (BIT(14))
-#define SOC_ETM_CH_ENABLE46_M  (SOC_ETM_CH_ENABLE46_V << SOC_ETM_CH_ENABLE46_S)
-#define SOC_ETM_CH_ENABLE46_V  0x00000001U
-#define SOC_ETM_CH_ENABLE46_S  14
-/** SOC_ETM_CH_ENABLE47 : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE47    (BIT(15))
-#define SOC_ETM_CH_ENABLE47_M  (SOC_ETM_CH_ENABLE47_V << SOC_ETM_CH_ENABLE47_S)
-#define SOC_ETM_CH_ENABLE47_V  0x00000001U
-#define SOC_ETM_CH_ENABLE47_S  15
-/** SOC_ETM_CH_ENABLE48 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE48    (BIT(16))
-#define SOC_ETM_CH_ENABLE48_M  (SOC_ETM_CH_ENABLE48_V << SOC_ETM_CH_ENABLE48_S)
-#define SOC_ETM_CH_ENABLE48_V  0x00000001U
-#define SOC_ETM_CH_ENABLE48_S  16
-/** SOC_ETM_CH_ENABLE49 : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable
- */
-#define SOC_ETM_CH_ENABLE49    (BIT(17))
-#define SOC_ETM_CH_ENABLE49_M  (SOC_ETM_CH_ENABLE49_V << SOC_ETM_CH_ENABLE49_S)
-#define SOC_ETM_CH_ENABLE49_V  0x00000001U
-#define SOC_ETM_CH_ENABLE49_S  17
-
-/** SOC_ETM_CH_ENA_AD1_CLR_REG register
- *  Channel enable clear register
- */
-#define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14)
-/** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE32    (BIT(0))
-#define SOC_ETM_CH_DISABLE32_M  (SOC_ETM_CH_DISABLE32_V << SOC_ETM_CH_DISABLE32_S)
-#define SOC_ETM_CH_DISABLE32_V  0x00000001U
-#define SOC_ETM_CH_DISABLE32_S  0
-/** SOC_ETM_CH_DISABLE33 : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE33    (BIT(1))
-#define SOC_ETM_CH_DISABLE33_M  (SOC_ETM_CH_DISABLE33_V << SOC_ETM_CH_DISABLE33_S)
-#define SOC_ETM_CH_DISABLE33_V  0x00000001U
-#define SOC_ETM_CH_DISABLE33_S  1
-/** SOC_ETM_CH_DISABLE34 : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE34    (BIT(2))
-#define SOC_ETM_CH_DISABLE34_M  (SOC_ETM_CH_DISABLE34_V << SOC_ETM_CH_DISABLE34_S)
-#define SOC_ETM_CH_DISABLE34_V  0x00000001U
-#define SOC_ETM_CH_DISABLE34_S  2
-/** SOC_ETM_CH_DISABLE35 : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE35    (BIT(3))
-#define SOC_ETM_CH_DISABLE35_M  (SOC_ETM_CH_DISABLE35_V << SOC_ETM_CH_DISABLE35_S)
-#define SOC_ETM_CH_DISABLE35_V  0x00000001U
-#define SOC_ETM_CH_DISABLE35_S  3
-/** SOC_ETM_CH_DISABLE36 : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE36    (BIT(4))
-#define SOC_ETM_CH_DISABLE36_M  (SOC_ETM_CH_DISABLE36_V << SOC_ETM_CH_DISABLE36_S)
-#define SOC_ETM_CH_DISABLE36_V  0x00000001U
-#define SOC_ETM_CH_DISABLE36_S  4
-/** SOC_ETM_CH_DISABLE37 : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE37    (BIT(5))
-#define SOC_ETM_CH_DISABLE37_M  (SOC_ETM_CH_DISABLE37_V << SOC_ETM_CH_DISABLE37_S)
-#define SOC_ETM_CH_DISABLE37_V  0x00000001U
-#define SOC_ETM_CH_DISABLE37_S  5
-/** SOC_ETM_CH_DISABLE38 : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE38    (BIT(6))
-#define SOC_ETM_CH_DISABLE38_M  (SOC_ETM_CH_DISABLE38_V << SOC_ETM_CH_DISABLE38_S)
-#define SOC_ETM_CH_DISABLE38_V  0x00000001U
-#define SOC_ETM_CH_DISABLE38_S  6
-/** SOC_ETM_CH_DISABLE39 : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE39    (BIT(7))
-#define SOC_ETM_CH_DISABLE39_M  (SOC_ETM_CH_DISABLE39_V << SOC_ETM_CH_DISABLE39_S)
-#define SOC_ETM_CH_DISABLE39_V  0x00000001U
-#define SOC_ETM_CH_DISABLE39_S  7
-/** SOC_ETM_CH_DISABLE40 : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE40    (BIT(8))
-#define SOC_ETM_CH_DISABLE40_M  (SOC_ETM_CH_DISABLE40_V << SOC_ETM_CH_DISABLE40_S)
-#define SOC_ETM_CH_DISABLE40_V  0x00000001U
-#define SOC_ETM_CH_DISABLE40_S  8
-/** SOC_ETM_CH_DISABLE41 : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE41    (BIT(9))
-#define SOC_ETM_CH_DISABLE41_M  (SOC_ETM_CH_DISABLE41_V << SOC_ETM_CH_DISABLE41_S)
-#define SOC_ETM_CH_DISABLE41_V  0x00000001U
-#define SOC_ETM_CH_DISABLE41_S  9
-/** SOC_ETM_CH_DISABLE42 : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE42    (BIT(10))
-#define SOC_ETM_CH_DISABLE42_M  (SOC_ETM_CH_DISABLE42_V << SOC_ETM_CH_DISABLE42_S)
-#define SOC_ETM_CH_DISABLE42_V  0x00000001U
-#define SOC_ETM_CH_DISABLE42_S  10
-/** SOC_ETM_CH_DISABLE43 : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE43    (BIT(11))
-#define SOC_ETM_CH_DISABLE43_M  (SOC_ETM_CH_DISABLE43_V << SOC_ETM_CH_DISABLE43_S)
-#define SOC_ETM_CH_DISABLE43_V  0x00000001U
-#define SOC_ETM_CH_DISABLE43_S  11
-/** SOC_ETM_CH_DISABLE44 : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE44    (BIT(12))
-#define SOC_ETM_CH_DISABLE44_M  (SOC_ETM_CH_DISABLE44_V << SOC_ETM_CH_DISABLE44_S)
-#define SOC_ETM_CH_DISABLE44_V  0x00000001U
-#define SOC_ETM_CH_DISABLE44_S  12
-/** SOC_ETM_CH_DISABLE45 : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE45    (BIT(13))
-#define SOC_ETM_CH_DISABLE45_M  (SOC_ETM_CH_DISABLE45_V << SOC_ETM_CH_DISABLE45_S)
-#define SOC_ETM_CH_DISABLE45_V  0x00000001U
-#define SOC_ETM_CH_DISABLE45_S  13
-/** SOC_ETM_CH_DISABLE46 : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE46    (BIT(14))
-#define SOC_ETM_CH_DISABLE46_M  (SOC_ETM_CH_DISABLE46_V << SOC_ETM_CH_DISABLE46_S)
-#define SOC_ETM_CH_DISABLE46_V  0x00000001U
-#define SOC_ETM_CH_DISABLE46_S  14
-/** SOC_ETM_CH_DISABLE47 : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE47    (BIT(15))
-#define SOC_ETM_CH_DISABLE47_M  (SOC_ETM_CH_DISABLE47_V << SOC_ETM_CH_DISABLE47_S)
-#define SOC_ETM_CH_DISABLE47_V  0x00000001U
-#define SOC_ETM_CH_DISABLE47_S  15
-/** SOC_ETM_CH_DISABLE48 : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE48    (BIT(16))
-#define SOC_ETM_CH_DISABLE48_M  (SOC_ETM_CH_DISABLE48_V << SOC_ETM_CH_DISABLE48_S)
-#define SOC_ETM_CH_DISABLE48_V  0x00000001U
-#define SOC_ETM_CH_DISABLE48_S  16
-/** SOC_ETM_CH_DISABLE49 : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_CH_DISABLE49    (BIT(17))
-#define SOC_ETM_CH_DISABLE49_M  (SOC_ETM_CH_DISABLE49_V << SOC_ETM_CH_DISABLE49_S)
-#define SOC_ETM_CH_DISABLE49_V  0x00000001U
-#define SOC_ETM_CH_DISABLE49_S  17
-
-/** SOC_ETM_CH0_EVT_ID_REG register
- *  Channel0 event id register
- */
-#define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18)
-/** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch0_evt_id
- */
-#define SOC_ETM_CH0_EVT_ID    0x000000FFU
-#define SOC_ETM_CH0_EVT_ID_M  (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S)
-#define SOC_ETM_CH0_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH0_EVT_ID_S  0
-
-/** SOC_ETM_CH0_TASK_ID_REG register
- *  Channel0 task id register
- */
-#define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c)
-/** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch0_task_id
- */
-#define SOC_ETM_CH0_TASK_ID    0x000000FFU
-#define SOC_ETM_CH0_TASK_ID_M  (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S)
-#define SOC_ETM_CH0_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH0_TASK_ID_S  0
-
-/** SOC_ETM_CH1_EVT_ID_REG register
- *  Channel1 event id register
- */
-#define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20)
-/** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch1_evt_id
- */
-#define SOC_ETM_CH1_EVT_ID    0x000000FFU
-#define SOC_ETM_CH1_EVT_ID_M  (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S)
-#define SOC_ETM_CH1_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH1_EVT_ID_S  0
-
-/** SOC_ETM_CH1_TASK_ID_REG register
- *  Channel1 task id register
- */
-#define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24)
-/** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch1_task_id
- */
-#define SOC_ETM_CH1_TASK_ID    0x000000FFU
-#define SOC_ETM_CH1_TASK_ID_M  (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S)
-#define SOC_ETM_CH1_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH1_TASK_ID_S  0
-
-/** SOC_ETM_CH2_EVT_ID_REG register
- *  Channel2 event id register
- */
-#define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28)
-/** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch2_evt_id
- */
-#define SOC_ETM_CH2_EVT_ID    0x000000FFU
-#define SOC_ETM_CH2_EVT_ID_M  (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S)
-#define SOC_ETM_CH2_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH2_EVT_ID_S  0
-
-/** SOC_ETM_CH2_TASK_ID_REG register
- *  Channel2 task id register
- */
-#define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c)
-/** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch2_task_id
- */
-#define SOC_ETM_CH2_TASK_ID    0x000000FFU
-#define SOC_ETM_CH2_TASK_ID_M  (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S)
-#define SOC_ETM_CH2_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH2_TASK_ID_S  0
-
-/** SOC_ETM_CH3_EVT_ID_REG register
- *  Channel3 event id register
- */
-#define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30)
-/** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch3_evt_id
- */
-#define SOC_ETM_CH3_EVT_ID    0x000000FFU
-#define SOC_ETM_CH3_EVT_ID_M  (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S)
-#define SOC_ETM_CH3_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH3_EVT_ID_S  0
-
-/** SOC_ETM_CH3_TASK_ID_REG register
- *  Channel3 task id register
- */
-#define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34)
-/** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch3_task_id
- */
-#define SOC_ETM_CH3_TASK_ID    0x000000FFU
-#define SOC_ETM_CH3_TASK_ID_M  (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S)
-#define SOC_ETM_CH3_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH3_TASK_ID_S  0
-
-/** SOC_ETM_CH4_EVT_ID_REG register
- *  Channel4 event id register
- */
-#define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38)
-/** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch4_evt_id
- */
-#define SOC_ETM_CH4_EVT_ID    0x000000FFU
-#define SOC_ETM_CH4_EVT_ID_M  (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S)
-#define SOC_ETM_CH4_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH4_EVT_ID_S  0
-
-/** SOC_ETM_CH4_TASK_ID_REG register
- *  Channel4 task id register
- */
-#define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c)
-/** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch4_task_id
- */
-#define SOC_ETM_CH4_TASK_ID    0x000000FFU
-#define SOC_ETM_CH4_TASK_ID_M  (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S)
-#define SOC_ETM_CH4_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH4_TASK_ID_S  0
-
-/** SOC_ETM_CH5_EVT_ID_REG register
- *  Channel5 event id register
- */
-#define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40)
-/** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch5_evt_id
- */
-#define SOC_ETM_CH5_EVT_ID    0x000000FFU
-#define SOC_ETM_CH5_EVT_ID_M  (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S)
-#define SOC_ETM_CH5_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH5_EVT_ID_S  0
-
-/** SOC_ETM_CH5_TASK_ID_REG register
- *  Channel5 task id register
- */
-#define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44)
-/** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch5_task_id
- */
-#define SOC_ETM_CH5_TASK_ID    0x000000FFU
-#define SOC_ETM_CH5_TASK_ID_M  (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S)
-#define SOC_ETM_CH5_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH5_TASK_ID_S  0
-
-/** SOC_ETM_CH6_EVT_ID_REG register
- *  Channel6 event id register
- */
-#define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48)
-/** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch6_evt_id
- */
-#define SOC_ETM_CH6_EVT_ID    0x000000FFU
-#define SOC_ETM_CH6_EVT_ID_M  (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S)
-#define SOC_ETM_CH6_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH6_EVT_ID_S  0
-
-/** SOC_ETM_CH6_TASK_ID_REG register
- *  Channel6 task id register
- */
-#define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c)
-/** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch6_task_id
- */
-#define SOC_ETM_CH6_TASK_ID    0x000000FFU
-#define SOC_ETM_CH6_TASK_ID_M  (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S)
-#define SOC_ETM_CH6_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH6_TASK_ID_S  0
-
-/** SOC_ETM_CH7_EVT_ID_REG register
- *  Channel7 event id register
- */
-#define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50)
-/** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch7_evt_id
- */
-#define SOC_ETM_CH7_EVT_ID    0x000000FFU
-#define SOC_ETM_CH7_EVT_ID_M  (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S)
-#define SOC_ETM_CH7_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH7_EVT_ID_S  0
-
-/** SOC_ETM_CH7_TASK_ID_REG register
- *  Channel7 task id register
- */
-#define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54)
-/** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch7_task_id
- */
-#define SOC_ETM_CH7_TASK_ID    0x000000FFU
-#define SOC_ETM_CH7_TASK_ID_M  (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S)
-#define SOC_ETM_CH7_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH7_TASK_ID_S  0
-
-/** SOC_ETM_CH8_EVT_ID_REG register
- *  Channel8 event id register
- */
-#define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58)
-/** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch8_evt_id
- */
-#define SOC_ETM_CH8_EVT_ID    0x000000FFU
-#define SOC_ETM_CH8_EVT_ID_M  (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S)
-#define SOC_ETM_CH8_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH8_EVT_ID_S  0
-
-/** SOC_ETM_CH8_TASK_ID_REG register
- *  Channel8 task id register
- */
-#define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c)
-/** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch8_task_id
- */
-#define SOC_ETM_CH8_TASK_ID    0x000000FFU
-#define SOC_ETM_CH8_TASK_ID_M  (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S)
-#define SOC_ETM_CH8_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH8_TASK_ID_S  0
-
-/** SOC_ETM_CH9_EVT_ID_REG register
- *  Channel9 event id register
- */
-#define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60)
-/** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch9_evt_id
- */
-#define SOC_ETM_CH9_EVT_ID    0x000000FFU
-#define SOC_ETM_CH9_EVT_ID_M  (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S)
-#define SOC_ETM_CH9_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH9_EVT_ID_S  0
-
-/** SOC_ETM_CH9_TASK_ID_REG register
- *  Channel9 task id register
- */
-#define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64)
-/** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch9_task_id
- */
-#define SOC_ETM_CH9_TASK_ID    0x000000FFU
-#define SOC_ETM_CH9_TASK_ID_M  (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S)
-#define SOC_ETM_CH9_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH9_TASK_ID_S  0
-
-/** SOC_ETM_CH10_EVT_ID_REG register
- *  Channel10 event id register
- */
-#define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68)
-/** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch10_evt_id
- */
-#define SOC_ETM_CH10_EVT_ID    0x000000FFU
-#define SOC_ETM_CH10_EVT_ID_M  (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S)
-#define SOC_ETM_CH10_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH10_EVT_ID_S  0
-
-/** SOC_ETM_CH10_TASK_ID_REG register
- *  Channel10 task id register
- */
-#define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c)
-/** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch10_task_id
- */
-#define SOC_ETM_CH10_TASK_ID    0x000000FFU
-#define SOC_ETM_CH10_TASK_ID_M  (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S)
-#define SOC_ETM_CH10_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH10_TASK_ID_S  0
-
-/** SOC_ETM_CH11_EVT_ID_REG register
- *  Channel11 event id register
- */
-#define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70)
-/** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch11_evt_id
- */
-#define SOC_ETM_CH11_EVT_ID    0x000000FFU
-#define SOC_ETM_CH11_EVT_ID_M  (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S)
-#define SOC_ETM_CH11_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH11_EVT_ID_S  0
-
-/** SOC_ETM_CH11_TASK_ID_REG register
- *  Channel11 task id register
- */
-#define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74)
-/** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch11_task_id
- */
-#define SOC_ETM_CH11_TASK_ID    0x000000FFU
-#define SOC_ETM_CH11_TASK_ID_M  (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S)
-#define SOC_ETM_CH11_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH11_TASK_ID_S  0
-
-/** SOC_ETM_CH12_EVT_ID_REG register
- *  Channel12 event id register
- */
-#define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78)
-/** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch12_evt_id
- */
-#define SOC_ETM_CH12_EVT_ID    0x000000FFU
-#define SOC_ETM_CH12_EVT_ID_M  (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S)
-#define SOC_ETM_CH12_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH12_EVT_ID_S  0
-
-/** SOC_ETM_CH12_TASK_ID_REG register
- *  Channel12 task id register
- */
-#define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c)
-/** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch12_task_id
- */
-#define SOC_ETM_CH12_TASK_ID    0x000000FFU
-#define SOC_ETM_CH12_TASK_ID_M  (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S)
-#define SOC_ETM_CH12_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH12_TASK_ID_S  0
-
-/** SOC_ETM_CH13_EVT_ID_REG register
- *  Channel13 event id register
- */
-#define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80)
-/** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch13_evt_id
- */
-#define SOC_ETM_CH13_EVT_ID    0x000000FFU
-#define SOC_ETM_CH13_EVT_ID_M  (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S)
-#define SOC_ETM_CH13_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH13_EVT_ID_S  0
-
-/** SOC_ETM_CH13_TASK_ID_REG register
- *  Channel13 task id register
- */
-#define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84)
-/** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch13_task_id
- */
-#define SOC_ETM_CH13_TASK_ID    0x000000FFU
-#define SOC_ETM_CH13_TASK_ID_M  (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S)
-#define SOC_ETM_CH13_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH13_TASK_ID_S  0
-
-/** SOC_ETM_CH14_EVT_ID_REG register
- *  Channel14 event id register
- */
-#define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88)
-/** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch14_evt_id
- */
-#define SOC_ETM_CH14_EVT_ID    0x000000FFU
-#define SOC_ETM_CH14_EVT_ID_M  (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S)
-#define SOC_ETM_CH14_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH14_EVT_ID_S  0
-
-/** SOC_ETM_CH14_TASK_ID_REG register
- *  Channel14 task id register
- */
-#define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c)
-/** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch14_task_id
- */
-#define SOC_ETM_CH14_TASK_ID    0x000000FFU
-#define SOC_ETM_CH14_TASK_ID_M  (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S)
-#define SOC_ETM_CH14_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH14_TASK_ID_S  0
-
-/** SOC_ETM_CH15_EVT_ID_REG register
- *  Channel15 event id register
- */
-#define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90)
-/** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch15_evt_id
- */
-#define SOC_ETM_CH15_EVT_ID    0x000000FFU
-#define SOC_ETM_CH15_EVT_ID_M  (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S)
-#define SOC_ETM_CH15_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH15_EVT_ID_S  0
-
-/** SOC_ETM_CH15_TASK_ID_REG register
- *  Channel15 task id register
- */
-#define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94)
-/** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch15_task_id
- */
-#define SOC_ETM_CH15_TASK_ID    0x000000FFU
-#define SOC_ETM_CH15_TASK_ID_M  (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S)
-#define SOC_ETM_CH15_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH15_TASK_ID_S  0
-
-/** SOC_ETM_CH16_EVT_ID_REG register
- *  Channel16 event id register
- */
-#define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98)
-/** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch16_evt_id
- */
-#define SOC_ETM_CH16_EVT_ID    0x000000FFU
-#define SOC_ETM_CH16_EVT_ID_M  (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S)
-#define SOC_ETM_CH16_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH16_EVT_ID_S  0
-
-/** SOC_ETM_CH16_TASK_ID_REG register
- *  Channel16 task id register
- */
-#define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c)
-/** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch16_task_id
- */
-#define SOC_ETM_CH16_TASK_ID    0x000000FFU
-#define SOC_ETM_CH16_TASK_ID_M  (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S)
-#define SOC_ETM_CH16_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH16_TASK_ID_S  0
-
-/** SOC_ETM_CH17_EVT_ID_REG register
- *  Channel17 event id register
- */
-#define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0)
-/** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch17_evt_id
- */
-#define SOC_ETM_CH17_EVT_ID    0x000000FFU
-#define SOC_ETM_CH17_EVT_ID_M  (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S)
-#define SOC_ETM_CH17_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH17_EVT_ID_S  0
-
-/** SOC_ETM_CH17_TASK_ID_REG register
- *  Channel17 task id register
- */
-#define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4)
-/** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch17_task_id
- */
-#define SOC_ETM_CH17_TASK_ID    0x000000FFU
-#define SOC_ETM_CH17_TASK_ID_M  (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S)
-#define SOC_ETM_CH17_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH17_TASK_ID_S  0
-
-/** SOC_ETM_CH18_EVT_ID_REG register
- *  Channel18 event id register
- */
-#define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8)
-/** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch18_evt_id
- */
-#define SOC_ETM_CH18_EVT_ID    0x000000FFU
-#define SOC_ETM_CH18_EVT_ID_M  (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S)
-#define SOC_ETM_CH18_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH18_EVT_ID_S  0
-
-/** SOC_ETM_CH18_TASK_ID_REG register
- *  Channel18 task id register
- */
-#define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac)
-/** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch18_task_id
- */
-#define SOC_ETM_CH18_TASK_ID    0x000000FFU
-#define SOC_ETM_CH18_TASK_ID_M  (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S)
-#define SOC_ETM_CH18_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH18_TASK_ID_S  0
-
-/** SOC_ETM_CH19_EVT_ID_REG register
- *  Channel19 event id register
- */
-#define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0)
-/** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch19_evt_id
- */
-#define SOC_ETM_CH19_EVT_ID    0x000000FFU
-#define SOC_ETM_CH19_EVT_ID_M  (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S)
-#define SOC_ETM_CH19_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH19_EVT_ID_S  0
-
-/** SOC_ETM_CH19_TASK_ID_REG register
- *  Channel19 task id register
- */
-#define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4)
-/** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch19_task_id
- */
-#define SOC_ETM_CH19_TASK_ID    0x000000FFU
-#define SOC_ETM_CH19_TASK_ID_M  (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S)
-#define SOC_ETM_CH19_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH19_TASK_ID_S  0
-
-/** SOC_ETM_CH20_EVT_ID_REG register
- *  Channel20 event id register
- */
-#define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8)
-/** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch20_evt_id
- */
-#define SOC_ETM_CH20_EVT_ID    0x000000FFU
-#define SOC_ETM_CH20_EVT_ID_M  (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S)
-#define SOC_ETM_CH20_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH20_EVT_ID_S  0
-
-/** SOC_ETM_CH20_TASK_ID_REG register
- *  Channel20 task id register
- */
-#define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc)
-/** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch20_task_id
- */
-#define SOC_ETM_CH20_TASK_ID    0x000000FFU
-#define SOC_ETM_CH20_TASK_ID_M  (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S)
-#define SOC_ETM_CH20_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH20_TASK_ID_S  0
-
-/** SOC_ETM_CH21_EVT_ID_REG register
- *  Channel21 event id register
- */
-#define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0)
-/** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch21_evt_id
- */
-#define SOC_ETM_CH21_EVT_ID    0x000000FFU
-#define SOC_ETM_CH21_EVT_ID_M  (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S)
-#define SOC_ETM_CH21_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH21_EVT_ID_S  0
-
-/** SOC_ETM_CH21_TASK_ID_REG register
- *  Channel21 task id register
- */
-#define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4)
-/** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch21_task_id
- */
-#define SOC_ETM_CH21_TASK_ID    0x000000FFU
-#define SOC_ETM_CH21_TASK_ID_M  (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S)
-#define SOC_ETM_CH21_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH21_TASK_ID_S  0
-
-/** SOC_ETM_CH22_EVT_ID_REG register
- *  Channel22 event id register
- */
-#define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8)
-/** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch22_evt_id
- */
-#define SOC_ETM_CH22_EVT_ID    0x000000FFU
-#define SOC_ETM_CH22_EVT_ID_M  (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S)
-#define SOC_ETM_CH22_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH22_EVT_ID_S  0
-
-/** SOC_ETM_CH22_TASK_ID_REG register
- *  Channel22 task id register
- */
-#define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc)
-/** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch22_task_id
- */
-#define SOC_ETM_CH22_TASK_ID    0x000000FFU
-#define SOC_ETM_CH22_TASK_ID_M  (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S)
-#define SOC_ETM_CH22_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH22_TASK_ID_S  0
-
-/** SOC_ETM_CH23_EVT_ID_REG register
- *  Channel23 event id register
- */
-#define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0)
-/** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch23_evt_id
- */
-#define SOC_ETM_CH23_EVT_ID    0x000000FFU
-#define SOC_ETM_CH23_EVT_ID_M  (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S)
-#define SOC_ETM_CH23_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH23_EVT_ID_S  0
-
-/** SOC_ETM_CH23_TASK_ID_REG register
- *  Channel23 task id register
- */
-#define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4)
-/** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch23_task_id
- */
-#define SOC_ETM_CH23_TASK_ID    0x000000FFU
-#define SOC_ETM_CH23_TASK_ID_M  (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S)
-#define SOC_ETM_CH23_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH23_TASK_ID_S  0
-
-/** SOC_ETM_CH24_EVT_ID_REG register
- *  Channel24 event id register
- */
-#define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8)
-/** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch24_evt_id
- */
-#define SOC_ETM_CH24_EVT_ID    0x000000FFU
-#define SOC_ETM_CH24_EVT_ID_M  (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S)
-#define SOC_ETM_CH24_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH24_EVT_ID_S  0
-
-/** SOC_ETM_CH24_TASK_ID_REG register
- *  Channel24 task id register
- */
-#define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc)
-/** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch24_task_id
- */
-#define SOC_ETM_CH24_TASK_ID    0x000000FFU
-#define SOC_ETM_CH24_TASK_ID_M  (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S)
-#define SOC_ETM_CH24_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH24_TASK_ID_S  0
-
-/** SOC_ETM_CH25_EVT_ID_REG register
- *  Channel25 event id register
- */
-#define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0)
-/** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch25_evt_id
- */
-#define SOC_ETM_CH25_EVT_ID    0x000000FFU
-#define SOC_ETM_CH25_EVT_ID_M  (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S)
-#define SOC_ETM_CH25_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH25_EVT_ID_S  0
-
-/** SOC_ETM_CH25_TASK_ID_REG register
- *  Channel25 task id register
- */
-#define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4)
-/** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch25_task_id
- */
-#define SOC_ETM_CH25_TASK_ID    0x000000FFU
-#define SOC_ETM_CH25_TASK_ID_M  (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S)
-#define SOC_ETM_CH25_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH25_TASK_ID_S  0
-
-/** SOC_ETM_CH26_EVT_ID_REG register
- *  Channel26 event id register
- */
-#define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8)
-/** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch26_evt_id
- */
-#define SOC_ETM_CH26_EVT_ID    0x000000FFU
-#define SOC_ETM_CH26_EVT_ID_M  (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S)
-#define SOC_ETM_CH26_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH26_EVT_ID_S  0
-
-/** SOC_ETM_CH26_TASK_ID_REG register
- *  Channel26 task id register
- */
-#define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec)
-/** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch26_task_id
- */
-#define SOC_ETM_CH26_TASK_ID    0x000000FFU
-#define SOC_ETM_CH26_TASK_ID_M  (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S)
-#define SOC_ETM_CH26_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH26_TASK_ID_S  0
-
-/** SOC_ETM_CH27_EVT_ID_REG register
- *  Channel27 event id register
- */
-#define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0)
-/** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch27_evt_id
- */
-#define SOC_ETM_CH27_EVT_ID    0x000000FFU
-#define SOC_ETM_CH27_EVT_ID_M  (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S)
-#define SOC_ETM_CH27_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH27_EVT_ID_S  0
-
-/** SOC_ETM_CH27_TASK_ID_REG register
- *  Channel27 task id register
- */
-#define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4)
-/** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch27_task_id
- */
-#define SOC_ETM_CH27_TASK_ID    0x000000FFU
-#define SOC_ETM_CH27_TASK_ID_M  (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S)
-#define SOC_ETM_CH27_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH27_TASK_ID_S  0
-
-/** SOC_ETM_CH28_EVT_ID_REG register
- *  Channel28 event id register
- */
-#define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8)
-/** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch28_evt_id
- */
-#define SOC_ETM_CH28_EVT_ID    0x000000FFU
-#define SOC_ETM_CH28_EVT_ID_M  (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S)
-#define SOC_ETM_CH28_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH28_EVT_ID_S  0
-
-/** SOC_ETM_CH28_TASK_ID_REG register
- *  Channel28 task id register
- */
-#define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc)
-/** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch28_task_id
- */
-#define SOC_ETM_CH28_TASK_ID    0x000000FFU
-#define SOC_ETM_CH28_TASK_ID_M  (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S)
-#define SOC_ETM_CH28_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH28_TASK_ID_S  0
-
-/** SOC_ETM_CH29_EVT_ID_REG register
- *  Channel29 event id register
- */
-#define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100)
-/** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch29_evt_id
- */
-#define SOC_ETM_CH29_EVT_ID    0x000000FFU
-#define SOC_ETM_CH29_EVT_ID_M  (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S)
-#define SOC_ETM_CH29_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH29_EVT_ID_S  0
-
-/** SOC_ETM_CH29_TASK_ID_REG register
- *  Channel29 task id register
- */
-#define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104)
-/** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch29_task_id
- */
-#define SOC_ETM_CH29_TASK_ID    0x000000FFU
-#define SOC_ETM_CH29_TASK_ID_M  (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S)
-#define SOC_ETM_CH29_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH29_TASK_ID_S  0
-
-/** SOC_ETM_CH30_EVT_ID_REG register
- *  Channel30 event id register
- */
-#define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108)
-/** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch30_evt_id
- */
-#define SOC_ETM_CH30_EVT_ID    0x000000FFU
-#define SOC_ETM_CH30_EVT_ID_M  (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S)
-#define SOC_ETM_CH30_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH30_EVT_ID_S  0
-
-/** SOC_ETM_CH30_TASK_ID_REG register
- *  Channel30 task id register
- */
-#define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c)
-/** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch30_task_id
- */
-#define SOC_ETM_CH30_TASK_ID    0x000000FFU
-#define SOC_ETM_CH30_TASK_ID_M  (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S)
-#define SOC_ETM_CH30_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH30_TASK_ID_S  0
-
-/** SOC_ETM_CH31_EVT_ID_REG register
- *  Channel31 event id register
- */
-#define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110)
-/** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch31_evt_id
- */
-#define SOC_ETM_CH31_EVT_ID    0x000000FFU
-#define SOC_ETM_CH31_EVT_ID_M  (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S)
-#define SOC_ETM_CH31_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH31_EVT_ID_S  0
-
-/** SOC_ETM_CH31_TASK_ID_REG register
- *  Channel31 task id register
- */
-#define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114)
-/** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch31_task_id
- */
-#define SOC_ETM_CH31_TASK_ID    0x000000FFU
-#define SOC_ETM_CH31_TASK_ID_M  (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S)
-#define SOC_ETM_CH31_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH31_TASK_ID_S  0
-
-/** SOC_ETM_CH32_EVT_ID_REG register
- *  Channel32 event id register
- */
-#define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118)
-/** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch32_evt_id
- */
-#define SOC_ETM_CH32_EVT_ID    0x000000FFU
-#define SOC_ETM_CH32_EVT_ID_M  (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S)
-#define SOC_ETM_CH32_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH32_EVT_ID_S  0
-
-/** SOC_ETM_CH32_TASK_ID_REG register
- *  Channel32 task id register
- */
-#define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c)
-/** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch32_task_id
- */
-#define SOC_ETM_CH32_TASK_ID    0x000000FFU
-#define SOC_ETM_CH32_TASK_ID_M  (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S)
-#define SOC_ETM_CH32_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH32_TASK_ID_S  0
-
-/** SOC_ETM_CH33_EVT_ID_REG register
- *  Channel33 event id register
- */
-#define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120)
-/** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch33_evt_id
- */
-#define SOC_ETM_CH33_EVT_ID    0x000000FFU
-#define SOC_ETM_CH33_EVT_ID_M  (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S)
-#define SOC_ETM_CH33_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH33_EVT_ID_S  0
-
-/** SOC_ETM_CH33_TASK_ID_REG register
- *  Channel33 task id register
- */
-#define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124)
-/** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch33_task_id
- */
-#define SOC_ETM_CH33_TASK_ID    0x000000FFU
-#define SOC_ETM_CH33_TASK_ID_M  (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S)
-#define SOC_ETM_CH33_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH33_TASK_ID_S  0
-
-/** SOC_ETM_CH34_EVT_ID_REG register
- *  Channel34 event id register
- */
-#define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128)
-/** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch34_evt_id
- */
-#define SOC_ETM_CH34_EVT_ID    0x000000FFU
-#define SOC_ETM_CH34_EVT_ID_M  (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S)
-#define SOC_ETM_CH34_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH34_EVT_ID_S  0
-
-/** SOC_ETM_CH34_TASK_ID_REG register
- *  Channel34 task id register
- */
-#define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c)
-/** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch34_task_id
- */
-#define SOC_ETM_CH34_TASK_ID    0x000000FFU
-#define SOC_ETM_CH34_TASK_ID_M  (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S)
-#define SOC_ETM_CH34_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH34_TASK_ID_S  0
-
-/** SOC_ETM_CH35_EVT_ID_REG register
- *  Channel35 event id register
- */
-#define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130)
-/** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch35_evt_id
- */
-#define SOC_ETM_CH35_EVT_ID    0x000000FFU
-#define SOC_ETM_CH35_EVT_ID_M  (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S)
-#define SOC_ETM_CH35_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH35_EVT_ID_S  0
-
-/** SOC_ETM_CH35_TASK_ID_REG register
- *  Channel35 task id register
- */
-#define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134)
-/** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch35_task_id
- */
-#define SOC_ETM_CH35_TASK_ID    0x000000FFU
-#define SOC_ETM_CH35_TASK_ID_M  (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S)
-#define SOC_ETM_CH35_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH35_TASK_ID_S  0
-
-/** SOC_ETM_CH36_EVT_ID_REG register
- *  Channel36 event id register
- */
-#define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138)
-/** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch36_evt_id
- */
-#define SOC_ETM_CH36_EVT_ID    0x000000FFU
-#define SOC_ETM_CH36_EVT_ID_M  (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S)
-#define SOC_ETM_CH36_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH36_EVT_ID_S  0
-
-/** SOC_ETM_CH36_TASK_ID_REG register
- *  Channel36 task id register
- */
-#define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c)
-/** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch36_task_id
- */
-#define SOC_ETM_CH36_TASK_ID    0x000000FFU
-#define SOC_ETM_CH36_TASK_ID_M  (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S)
-#define SOC_ETM_CH36_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH36_TASK_ID_S  0
-
-/** SOC_ETM_CH37_EVT_ID_REG register
- *  Channel37 event id register
- */
-#define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140)
-/** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch37_evt_id
- */
-#define SOC_ETM_CH37_EVT_ID    0x000000FFU
-#define SOC_ETM_CH37_EVT_ID_M  (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S)
-#define SOC_ETM_CH37_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH37_EVT_ID_S  0
-
-/** SOC_ETM_CH37_TASK_ID_REG register
- *  Channel37 task id register
- */
-#define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144)
-/** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch37_task_id
- */
-#define SOC_ETM_CH37_TASK_ID    0x000000FFU
-#define SOC_ETM_CH37_TASK_ID_M  (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S)
-#define SOC_ETM_CH37_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH37_TASK_ID_S  0
-
-/** SOC_ETM_CH38_EVT_ID_REG register
- *  Channel38 event id register
- */
-#define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148)
-/** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch38_evt_id
- */
-#define SOC_ETM_CH38_EVT_ID    0x000000FFU
-#define SOC_ETM_CH38_EVT_ID_M  (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S)
-#define SOC_ETM_CH38_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH38_EVT_ID_S  0
-
-/** SOC_ETM_CH38_TASK_ID_REG register
- *  Channel38 task id register
- */
-#define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c)
-/** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch38_task_id
- */
-#define SOC_ETM_CH38_TASK_ID    0x000000FFU
-#define SOC_ETM_CH38_TASK_ID_M  (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S)
-#define SOC_ETM_CH38_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH38_TASK_ID_S  0
-
-/** SOC_ETM_CH39_EVT_ID_REG register
- *  Channel39 event id register
- */
-#define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150)
-/** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch39_evt_id
- */
-#define SOC_ETM_CH39_EVT_ID    0x000000FFU
-#define SOC_ETM_CH39_EVT_ID_M  (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S)
-#define SOC_ETM_CH39_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH39_EVT_ID_S  0
-
-/** SOC_ETM_CH39_TASK_ID_REG register
- *  Channel39 task id register
- */
-#define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154)
-/** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch39_task_id
- */
-#define SOC_ETM_CH39_TASK_ID    0x000000FFU
-#define SOC_ETM_CH39_TASK_ID_M  (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S)
-#define SOC_ETM_CH39_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH39_TASK_ID_S  0
-
-/** SOC_ETM_CH40_EVT_ID_REG register
- *  Channel40 event id register
- */
-#define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158)
-/** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch40_evt_id
- */
-#define SOC_ETM_CH40_EVT_ID    0x000000FFU
-#define SOC_ETM_CH40_EVT_ID_M  (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S)
-#define SOC_ETM_CH40_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH40_EVT_ID_S  0
-
-/** SOC_ETM_CH40_TASK_ID_REG register
- *  Channel40 task id register
- */
-#define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c)
-/** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch40_task_id
- */
-#define SOC_ETM_CH40_TASK_ID    0x000000FFU
-#define SOC_ETM_CH40_TASK_ID_M  (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S)
-#define SOC_ETM_CH40_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH40_TASK_ID_S  0
-
-/** SOC_ETM_CH41_EVT_ID_REG register
- *  Channel41 event id register
- */
-#define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160)
-/** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch41_evt_id
- */
-#define SOC_ETM_CH41_EVT_ID    0x000000FFU
-#define SOC_ETM_CH41_EVT_ID_M  (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S)
-#define SOC_ETM_CH41_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH41_EVT_ID_S  0
-
-/** SOC_ETM_CH41_TASK_ID_REG register
- *  Channel41 task id register
- */
-#define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164)
-/** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch41_task_id
- */
-#define SOC_ETM_CH41_TASK_ID    0x000000FFU
-#define SOC_ETM_CH41_TASK_ID_M  (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S)
-#define SOC_ETM_CH41_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH41_TASK_ID_S  0
-
-/** SOC_ETM_CH42_EVT_ID_REG register
- *  Channel42 event id register
- */
-#define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168)
-/** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch42_evt_id
- */
-#define SOC_ETM_CH42_EVT_ID    0x000000FFU
-#define SOC_ETM_CH42_EVT_ID_M  (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S)
-#define SOC_ETM_CH42_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH42_EVT_ID_S  0
-
-/** SOC_ETM_CH42_TASK_ID_REG register
- *  Channel42 task id register
- */
-#define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c)
-/** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch42_task_id
- */
-#define SOC_ETM_CH42_TASK_ID    0x000000FFU
-#define SOC_ETM_CH42_TASK_ID_M  (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S)
-#define SOC_ETM_CH42_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH42_TASK_ID_S  0
-
-/** SOC_ETM_CH43_EVT_ID_REG register
- *  Channel43 event id register
- */
-#define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170)
-/** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch43_evt_id
- */
-#define SOC_ETM_CH43_EVT_ID    0x000000FFU
-#define SOC_ETM_CH43_EVT_ID_M  (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S)
-#define SOC_ETM_CH43_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH43_EVT_ID_S  0
-
-/** SOC_ETM_CH43_TASK_ID_REG register
- *  Channel43 task id register
- */
-#define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174)
-/** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch43_task_id
- */
-#define SOC_ETM_CH43_TASK_ID    0x000000FFU
-#define SOC_ETM_CH43_TASK_ID_M  (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S)
-#define SOC_ETM_CH43_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH43_TASK_ID_S  0
-
-/** SOC_ETM_CH44_EVT_ID_REG register
- *  Channel44 event id register
- */
-#define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178)
-/** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch44_evt_id
- */
-#define SOC_ETM_CH44_EVT_ID    0x000000FFU
-#define SOC_ETM_CH44_EVT_ID_M  (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S)
-#define SOC_ETM_CH44_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH44_EVT_ID_S  0
-
-/** SOC_ETM_CH44_TASK_ID_REG register
- *  Channel44 task id register
- */
-#define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c)
-/** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch44_task_id
- */
-#define SOC_ETM_CH44_TASK_ID    0x000000FFU
-#define SOC_ETM_CH44_TASK_ID_M  (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S)
-#define SOC_ETM_CH44_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH44_TASK_ID_S  0
-
-/** SOC_ETM_CH45_EVT_ID_REG register
- *  Channel45 event id register
- */
-#define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180)
-/** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch45_evt_id
- */
-#define SOC_ETM_CH45_EVT_ID    0x000000FFU
-#define SOC_ETM_CH45_EVT_ID_M  (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S)
-#define SOC_ETM_CH45_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH45_EVT_ID_S  0
-
-/** SOC_ETM_CH45_TASK_ID_REG register
- *  Channel45 task id register
- */
-#define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184)
-/** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch45_task_id
- */
-#define SOC_ETM_CH45_TASK_ID    0x000000FFU
-#define SOC_ETM_CH45_TASK_ID_M  (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S)
-#define SOC_ETM_CH45_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH45_TASK_ID_S  0
-
-/** SOC_ETM_CH46_EVT_ID_REG register
- *  Channel46 event id register
- */
-#define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188)
-/** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch46_evt_id
- */
-#define SOC_ETM_CH46_EVT_ID    0x000000FFU
-#define SOC_ETM_CH46_EVT_ID_M  (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S)
-#define SOC_ETM_CH46_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH46_EVT_ID_S  0
-
-/** SOC_ETM_CH46_TASK_ID_REG register
- *  Channel46 task id register
- */
-#define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c)
-/** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch46_task_id
- */
-#define SOC_ETM_CH46_TASK_ID    0x000000FFU
-#define SOC_ETM_CH46_TASK_ID_M  (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S)
-#define SOC_ETM_CH46_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH46_TASK_ID_S  0
-
-/** SOC_ETM_CH47_EVT_ID_REG register
- *  Channel47 event id register
- */
-#define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190)
-/** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch47_evt_id
- */
-#define SOC_ETM_CH47_EVT_ID    0x000000FFU
-#define SOC_ETM_CH47_EVT_ID_M  (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S)
-#define SOC_ETM_CH47_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH47_EVT_ID_S  0
-
-/** SOC_ETM_CH47_TASK_ID_REG register
- *  Channel47 task id register
- */
-#define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194)
-/** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch47_task_id
- */
-#define SOC_ETM_CH47_TASK_ID    0x000000FFU
-#define SOC_ETM_CH47_TASK_ID_M  (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S)
-#define SOC_ETM_CH47_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH47_TASK_ID_S  0
-
-/** SOC_ETM_CH48_EVT_ID_REG register
- *  Channel48 event id register
- */
-#define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198)
-/** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch48_evt_id
- */
-#define SOC_ETM_CH48_EVT_ID    0x000000FFU
-#define SOC_ETM_CH48_EVT_ID_M  (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S)
-#define SOC_ETM_CH48_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH48_EVT_ID_S  0
-
-/** SOC_ETM_CH48_TASK_ID_REG register
- *  Channel48 task id register
- */
-#define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c)
-/** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch48_task_id
- */
-#define SOC_ETM_CH48_TASK_ID    0x000000FFU
-#define SOC_ETM_CH48_TASK_ID_M  (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S)
-#define SOC_ETM_CH48_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH48_TASK_ID_S  0
-
-/** SOC_ETM_CH49_EVT_ID_REG register
- *  Channel49 event id register
- */
-#define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0)
-/** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch49_evt_id
- */
-#define SOC_ETM_CH49_EVT_ID    0x000000FFU
-#define SOC_ETM_CH49_EVT_ID_M  (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S)
-#define SOC_ETM_CH49_EVT_ID_V  0x000000FFU
-#define SOC_ETM_CH49_EVT_ID_S  0
-
-/** SOC_ETM_CH49_TASK_ID_REG register
- *  Channel49 task id register
- */
-#define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4)
-/** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0;
- *  Configures ch49_task_id
- */
-#define SOC_ETM_CH49_TASK_ID    0x000000FFU
-#define SOC_ETM_CH49_TASK_ID_M  (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S)
-#define SOC_ETM_CH49_TASK_ID_V  0x000000FFU
-#define SOC_ETM_CH49_TASK_ID_S  0
-
-/** SOC_ETM_EVT_ST0_REG register
- *  Events trigger status register
- */
-#define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8)
-/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST    (BIT(0))
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S  0
-/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST    (BIT(1))
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S  1
-/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST    (BIT(2))
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S  2
-/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST    (BIT(3))
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S  3
-/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST    (BIT(4))
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S  4
-/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST    (BIT(5))
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S  5
-/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST    (BIT(6))
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S  6
-/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST    (BIT(7))
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S  7
-/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST    (BIT(8))
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S  8
-/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST    (BIT(9))
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S  9
-/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST    (BIT(10))
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S  10
-/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST    (BIT(11))
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S  11
-/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST    (BIT(12))
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S  12
-/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST    (BIT(13))
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S  13
-/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST    (BIT(14))
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S  14
-/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST    (BIT(15))
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S  15
-/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST    (BIT(16))
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S  16
-/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST    (BIT(17))
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S  17
-/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST    (BIT(18))
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S  18
-/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST    (BIT(19))
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S  19
-/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST    (BIT(20))
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S  20
-/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST    (BIT(21))
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S  21
-/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST    (BIT(22))
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S  22
-/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST    (BIT(23))
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_M  (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S)
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S  23
-/** SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents GPIO_evt_zero_det_pos trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST    (BIT(24))
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_M  (SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_S)
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_S  24
-/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents GPIO_evt_zero_det_neg trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST    (BIT(25))
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_M  (SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_S)
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_S  25
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST    (BIT(26))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S  26
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST    (BIT(27))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S  27
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST    (BIT(28))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S  28
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST    (BIT(29))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S  29
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST    (BIT(30))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S  30
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST    (BIT(31))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S  31
-
-/** SOC_ETM_EVT_ST0_CLR_REG register
- *  Events trigger status clear register
- */
-#define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac)
-/** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR    (BIT(0))
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S  0
-/** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR    (BIT(1))
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S  1
-/** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR    (BIT(2))
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S  2
-/** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR    (BIT(3))
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S  3
-/** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR    (BIT(4))
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S  4
-/** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR    (BIT(5))
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S  5
-/** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR    (BIT(6))
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S  6
-/** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR    (BIT(7))
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S  7
-/** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR    (BIT(8))
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S  8
-/** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR    (BIT(9))
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S  9
-/** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR    (BIT(10))
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S  10
-/** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR    (BIT(11))
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S  11
-/** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR    (BIT(12))
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S  12
-/** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR    (BIT(13))
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S  13
-/** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR    (BIT(14))
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S  14
-/** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR    (BIT(15))
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S  15
-/** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR    (BIT(16))
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S  16
-/** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR    (BIT(17))
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S  17
-/** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR    (BIT(18))
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S  18
-/** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR    (BIT(19))
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S  19
-/** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR    (BIT(20))
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S  20
-/** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR    (BIT(21))
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S  21
-/** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR    (BIT(22))
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S  22
-/** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR    (BIT(23))
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_M  (SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V << SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S  23
-/** SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear GPIO_evt_zero_det_pos trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR    (BIT(24))
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_M  (SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_ZERO_DET_POS_ST_CLR_S  24
-/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear GPIO_evt_zero_det_neg trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR    (BIT(25))
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_M  (SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_S)
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG_ST_CLR_S  25
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR    (BIT(26))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S  26
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR    (BIT(27))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S  27
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR    (BIT(28))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S  28
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR    (BIT(29))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S  29
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR    (BIT(30))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S  30
-/** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR    (BIT(31))
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_M  (SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S  31
-
-/** SOC_ETM_EVT_ST1_REG register
- *  Events trigger status register
- */
-#define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0)
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST    (BIT(0))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S  0
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST    (BIT(1))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S  1
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST    (BIT(2))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S  2
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST    (BIT(3))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S  3
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST    (BIT(4))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S  4
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST    (BIT(5))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S  5
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST    (BIT(6))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S  6
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST    (BIT(7))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S  7
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST    (BIT(8))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S  8
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST    (BIT(9))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S  9
-/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST    (BIT(10))
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S)
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S  10
-/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST    (BIT(11))
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S)
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S  11
-/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST    (BIT(12))
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S)
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S  12
-/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST    (BIT(13))
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_M  (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S)
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S  13
-/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST    (BIT(14))
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S)
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S  14
-/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST    (BIT(15))
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S)
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S  15
-/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST    (BIT(16))
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S)
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S  16
-/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST    (BIT(17))
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S)
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S  17
-/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST    (BIT(18))
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S)
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V  0x00000001U
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S  18
-/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST    (BIT(19))
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S)
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V  0x00000001U
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S  19
-/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST    (BIT(20))
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S)
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V  0x00000001U
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S  20
-/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST    (BIT(21))
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_S  21
-/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST    (BIT(22))
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_S  22
-/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST    (BIT(23))
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_S  23
-/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST    (BIT(24))
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_S  24
-/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST    (BIT(25))
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_S  25
-/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST    (BIT(26))
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_S  26
-/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST    (BIT(27))
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_S  27
-/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST    (BIT(28))
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_S  28
-/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST    (BIT(29))
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_S  29
-/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST    (BIT(30))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_S  30
-/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST    (BIT(31))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_S  31
-
-/** SOC_ETM_EVT_ST1_CLR_REG register
- *  Events trigger status clear register
- */
-#define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4)
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR    (BIT(0))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S  0
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR    (BIT(1))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S  1
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR    (BIT(2))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S  2
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR    (BIT(3))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S  3
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR    (BIT(4))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S  4
-/** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR    (BIT(5))
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_M  (SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V << SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S  5
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR    (BIT(6))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S  6
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR    (BIT(7))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S  7
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR    (BIT(8))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S  8
-/** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR    (BIT(9))
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V << SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S  9
-/** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR    (BIT(10))
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S  10
-/** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR    (BIT(11))
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S  11
-/** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR    (BIT(12))
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S  12
-/** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR    (BIT(13))
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_M  (SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V << SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S)
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S  13
-/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR    (BIT(14))
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S  14
-/** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR    (BIT(15))
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_M  (SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S  15
-/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR    (BIT(16))
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S  16
-/** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR    (BIT(17))
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_M  (SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V << SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S  17
-/** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR    (BIT(18))
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S)
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V  0x00000001U
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S  18
-/** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR    (BIT(19))
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S)
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V  0x00000001U
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S  19
-/** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR    (BIT(20))
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_M  (SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V << SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S)
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V  0x00000001U
-#define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S  20
-/** SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR    (BIT(21))
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER0_STOP_ST_CLR_S  21
-/** SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR    (BIT(22))
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER1_STOP_ST_CLR_S  22
-/** SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR    (BIT(23))
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER2_STOP_ST_CLR_S  23
-/** SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR    (BIT(24))
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_S  24
-/** SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR    (BIT(25))
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_S  25
-/** SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR    (BIT(26))
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_S  26
-/** SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR    (BIT(27))
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER0_TEP_ST_CLR_S  27
-/** SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR    (BIT(28))
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER1_TEP_ST_CLR_S  28
-/** SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR    (BIT(29))
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TIMER2_TEP_ST_CLR_S  29
-/** SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR    (BIT(30))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEA_ST_CLR_S  30
-/** SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR    (BIT(31))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEA_ST_CLR_S  31
-
-/** SOC_ETM_EVT_ST2_REG register
- *  Events trigger status register
- */
-#define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8)
-/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST    (BIT(0))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_S  0
-/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST    (BIT(1))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_S  1
-/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST    (BIT(2))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_S  2
-/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST    (BIT(3))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_S  3
-/** SOC_ETM_MCPWM0_EVT_F0_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_F0_ST    (BIT(4))
-#define SOC_ETM_MCPWM0_EVT_F0_ST_M  (SOC_ETM_MCPWM0_EVT_F0_ST_V << SOC_ETM_MCPWM0_EVT_F0_ST_S)
-#define SOC_ETM_MCPWM0_EVT_F0_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F0_ST_S  4
-/** SOC_ETM_MCPWM0_EVT_F1_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_F1_ST    (BIT(5))
-#define SOC_ETM_MCPWM0_EVT_F1_ST_M  (SOC_ETM_MCPWM0_EVT_F1_ST_V << SOC_ETM_MCPWM0_EVT_F1_ST_S)
-#define SOC_ETM_MCPWM0_EVT_F1_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F1_ST_S  5
-/** SOC_ETM_MCPWM0_EVT_F2_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_F2_ST    (BIT(6))
-#define SOC_ETM_MCPWM0_EVT_F2_ST_M  (SOC_ETM_MCPWM0_EVT_F2_ST_V << SOC_ETM_MCPWM0_EVT_F2_ST_S)
-#define SOC_ETM_MCPWM0_EVT_F2_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F2_ST_S  6
-/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST    (BIT(7))
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_M  (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S)
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_S  7
-/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST    (BIT(8))
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_M  (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S)
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_S  8
-/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST    (BIT(9))
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_M  (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S)
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_S  9
-/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST    (BIT(10))
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_M  (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_S  10
-/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST    (BIT(11))
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_M  (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_S  11
-/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST    (BIT(12))
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_M  (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_S  12
-/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST    (BIT(13))
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_M  (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_S  13
-/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST    (BIT(14))
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_M  (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_S  14
-/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST    (BIT(15))
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_M  (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S)
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_S  15
-/** SOC_ETM_MCPWM0_EVT_CAP0_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST    (BIT(16))
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST_M  (SOC_ETM_MCPWM0_EVT_CAP0_ST_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_S)
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST_S  16
-/** SOC_ETM_MCPWM0_EVT_CAP1_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST    (BIT(17))
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST_M  (SOC_ETM_MCPWM0_EVT_CAP1_ST_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_S)
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST_S  17
-/** SOC_ETM_MCPWM0_EVT_CAP2_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST    (BIT(18))
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST_M  (SOC_ETM_MCPWM0_EVT_CAP2_ST_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_S)
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST_S  18
-/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST    (BIT(19))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_S  19
-/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST    (BIT(20))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_S  20
-/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST    (BIT(21))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_S  21
-/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST    (BIT(22))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_S  22
-/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST    (BIT(23))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_S  23
-/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST    (BIT(24))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_S  24
-/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST    (BIT(25))
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_M  (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S)
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S  25
-/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST    (BIT(26))
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S)
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S  26
-/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST    (BIT(27))
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S)
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S  27
-/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST    (BIT(28))
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S)
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S  28
-/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST    (BIT(29))
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S)
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S  29
-/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST    (BIT(30))
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_M  (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S)
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S  30
-/** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_STOPPED0_ST    (BIT(31))
-#define SOC_ETM_ADC_EVT_STOPPED0_ST_M  (SOC_ETM_ADC_EVT_STOPPED0_ST_V << SOC_ETM_ADC_EVT_STOPPED0_ST_S)
-#define SOC_ETM_ADC_EVT_STOPPED0_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_STOPPED0_ST_S  31
-
-/** SOC_ETM_EVT_ST2_CLR_REG register
- *  Events trigger status clear register
- */
-#define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc)
-/** SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR    (BIT(0))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEA_ST_CLR_S  0
-/** SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR    (BIT(1))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEB_ST_CLR_S  1
-/** SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR    (BIT(2))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEB_ST_CLR_S  2
-/** SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR    (BIT(3))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEB_ST_CLR_S  3
-/** SOC_ETM_MCPWM0_EVT_F0_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR    (BIT(4))
-#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F0_ST_CLR_S  4
-/** SOC_ETM_MCPWM0_EVT_F1_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR    (BIT(5))
-#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F1_ST_CLR_S  5
-/** SOC_ETM_MCPWM0_EVT_F2_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR    (BIT(6))
-#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F2_ST_CLR_S  6
-/** SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR    (BIT(7))
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F0_CLR_ST_CLR_S  7
-/** SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR    (BIT(8))
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F1_CLR_ST_CLR_S  8
-/** SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR    (BIT(9))
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V << SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_F2_CLR_ST_CLR_S  9
-/** SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR    (BIT(10))
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ0_CBC_ST_CLR_S  10
-/** SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR    (BIT(11))
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ1_CBC_ST_CLR_S  11
-/** SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR    (BIT(12))
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ2_CBC_ST_CLR_S  12
-/** SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR    (BIT(13))
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ0_OST_ST_CLR_S  13
-/** SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR    (BIT(14))
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ1_OST_ST_CLR_S  14
-/** SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR    (BIT(15))
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_TZ2_OST_ST_CLR_S  15
-/** SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR    (BIT(16))
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_CAP0_ST_CLR_S  16
-/** SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR    (BIT(17))
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_CAP1_ST_CLR_S  17
-/** SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR    (BIT(18))
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_CAP2_ST_CLR_S  18
-/** SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR    (BIT(19))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE1_ST_CLR_S  19
-/** SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR    (BIT(20))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE1_ST_CLR_S  20
-/** SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR    (BIT(21))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE1_ST_CLR_S  21
-/** SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR    (BIT(22))
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP0_TEE2_ST_CLR_S  22
-/** SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR    (BIT(23))
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP1_TEE2_ST_CLR_S  23
-/** SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR    (BIT(24))
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_M  (SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V << SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S)
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_EVT_OP2_TEE2_ST_CLR_S  24
-/** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR    (BIT(25))
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_M  (SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V << SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S  25
-/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR    (BIT(26))
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S  26
-/** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR    (BIT(27))
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S  27
-/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR    (BIT(28))
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S  28
-/** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR    (BIT(29))
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_M  (SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V << SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S  29
-/** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR    (BIT(30))
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_M  (SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V << SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S  30
-/** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR    (BIT(31))
-#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_M  (SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V << SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S  31
-
-/** SOC_ETM_EVT_ST3_REG register
- *  Events trigger status register
- */
-#define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0)
-/** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_EVT_STARTED0_ST    (BIT(0))
-#define SOC_ETM_ADC_EVT_STARTED0_ST_M  (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S)
-#define SOC_ETM_ADC_EVT_STARTED0_ST_V  0x00000001U
-#define SOC_ETM_ADC_EVT_STARTED0_ST_S  0
-/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_DONE0_ST    (BIT(1))
-#define SOC_ETM_REGDMA_EVT_DONE0_ST_M  (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S)
-#define SOC_ETM_REGDMA_EVT_DONE0_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE0_ST_S  1
-/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_DONE1_ST    (BIT(2))
-#define SOC_ETM_REGDMA_EVT_DONE1_ST_M  (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S)
-#define SOC_ETM_REGDMA_EVT_DONE1_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE1_ST_S  2
-/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_DONE2_ST    (BIT(3))
-#define SOC_ETM_REGDMA_EVT_DONE2_ST_M  (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S)
-#define SOC_ETM_REGDMA_EVT_DONE2_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE2_ST_S  3
-/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_DONE3_ST    (BIT(4))
-#define SOC_ETM_REGDMA_EVT_DONE3_ST_M  (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S)
-#define SOC_ETM_REGDMA_EVT_DONE3_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE3_ST_S  4
-/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_ERR0_ST    (BIT(5))
-#define SOC_ETM_REGDMA_EVT_ERR0_ST_M  (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S)
-#define SOC_ETM_REGDMA_EVT_ERR0_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR0_ST_S  5
-/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_ERR1_ST    (BIT(6))
-#define SOC_ETM_REGDMA_EVT_ERR1_ST_M  (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S)
-#define SOC_ETM_REGDMA_EVT_ERR1_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR1_ST_S  6
-/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_ERR2_ST    (BIT(7))
-#define SOC_ETM_REGDMA_EVT_ERR2_ST_M  (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S)
-#define SOC_ETM_REGDMA_EVT_ERR2_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR2_ST_S  7
-/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_EVT_ERR3_ST    (BIT(8))
-#define SOC_ETM_REGDMA_EVT_ERR3_ST_M  (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S)
-#define SOC_ETM_REGDMA_EVT_ERR3_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR3_ST_S  8
-/** SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents GDMA_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST    (BIT(9))
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_M  (SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_S  9
-/** SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents GDMA_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST    (BIT(10))
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_M  (SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_S  10
-/** SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents GDMA_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST    (BIT(11))
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_M  (SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_S  11
-/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents GDMA_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST    (BIT(12))
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_M  (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_S  12
-/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents GDMA_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST    (BIT(13))
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_M  (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_S  13
-/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents GDMA_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST    (BIT(14))
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_M  (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_S  14
-/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST    (BIT(15))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_M  (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_S  15
-/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST    (BIT(16))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_M  (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_S  16
-/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST    (BIT(17))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_M  (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_S  17
-/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents GDMA_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST    (BIT(18))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_M  (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_S  18
-/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents GDMA_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST    (BIT(19))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_M  (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_S  19
-/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents GDMA_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST    (BIT(20))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_M  (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_S  20
-/** SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents GDMA_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST    (BIT(21))
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_M  (SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_S  21
-/** SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents GDMA_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST    (BIT(22))
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_M  (SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_S  22
-/** SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents GDMA_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST    (BIT(23))
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_M  (SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_S  23
-/** SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents GDMA_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST    (BIT(24))
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_M  (SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_S  24
-/** SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents GDMA_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST    (BIT(25))
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_M  (SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_S  25
-/** SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents GDMA_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST    (BIT(26))
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_M  (SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_S  26
-/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents GDMA_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST    (BIT(27))
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_M  (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_S  27
-/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents GDMA_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST    (BIT(28))
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_M  (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_S  28
-/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents GDMA_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST    (BIT(29))
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_M  (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_S  29
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST    (BIT(30))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_S  30
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST    (BIT(31))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_S  31
-
-/** SOC_ETM_EVT_ST3_CLR_REG register
- *  Events trigger status clear register
- */
-#define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4)
-/** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR    (BIT(0))
-#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M  (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S)
-#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S  0
-/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR    (BIT(1))
-#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S  1
-/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR    (BIT(2))
-#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S  2
-/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR    (BIT(3))
-#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S  3
-/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR    (BIT(4))
-#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M  (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S  4
-/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR    (BIT(5))
-#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S  5
-/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR    (BIT(6))
-#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S  6
-/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR    (BIT(7))
-#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S  7
-/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR    (BIT(8))
-#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M  (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S)
-#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S  8
-/** SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_done_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR    (BIT(9))
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH0_ST_CLR_S  9
-/** SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_done_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR    (BIT(10))
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH1_ST_CLR_S  10
-/** SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_done_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR    (BIT(11))
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_DONE_CH2_ST_CLR_S  11
-/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_suc_eof_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR    (BIT(12))
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH0_ST_CLR_S  12
-/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR    (BIT(13))
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH1_ST_CLR_S  13
-/** SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_suc_eof_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR    (BIT(14))
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_SUC_EOF_CH2_ST_CLR_S  14
-/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_fifo_empty_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR    (BIT(15))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S  15
-/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_fifo_empty_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR    (BIT(16))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S  16
-/** SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_fifo_empty_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR    (BIT(17))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S  17
-/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_fifo_full_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR    (BIT(18))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH0_ST_CLR_S  18
-/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_fifo_full_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR    (BIT(19))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH1_ST_CLR_S  19
-/** SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear GDMA_evt_in_fifo_full_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR    (BIT(20))
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_IN_FIFO_FULL_CH2_ST_CLR_S  20
-/** SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR    (BIT(21))
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH0_ST_CLR_S  21
-/** SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR    (BIT(22))
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH1_ST_CLR_S  22
-/** SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR    (BIT(23))
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_DONE_CH2_ST_CLR_S  23
-/** SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR    (BIT(24))
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH0_ST_CLR_S  24
-/** SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR    (BIT(25))
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH1_ST_CLR_S  25
-/** SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR    (BIT(26))
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_EOF_CH2_ST_CLR_S  26
-/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR    (BIT(27))
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S  27
-/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR    (BIT(28))
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S  28
-/** SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR    (BIT(29))
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S  29
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR    (BIT(30))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S  30
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR    (BIT(31))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S  31
-
-/** SOC_ETM_EVT_ST4_REG register
- *  Events trigger status register
- */
-#define SOC_ETM_EVT_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1c8)
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST    (BIT(0))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_S  0
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents GDMA_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST    (BIT(1))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_S  1
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents GDMA_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST    (BIT(2))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_S  2
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents GDMA_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST    (BIT(3))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_S  3
-/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST    (BIT(4))
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_M  (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S)
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V  0x00000001U
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S  4
-/** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST    (BIT(5))
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST_M  (SOC_ETM_I2S0_EVT_RX_DONE_ST_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_S)
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST_S  5
-/** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST    (BIT(6))
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST_M  (SOC_ETM_I2S0_EVT_TX_DONE_ST_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_S)
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST_S  6
-/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST    (BIT(7))
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_M  (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S)
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S  7
-/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST    (BIT(8))
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M  (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S)
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S  8
-/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST    (BIT(9))
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M  (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S)
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V  0x00000001U
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S  9
-/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ULP_EVT_HALT_ST    (BIT(10))
-#define SOC_ETM_ULP_EVT_HALT_ST_M  (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S)
-#define SOC_ETM_ULP_EVT_HALT_ST_V  0x00000001U
-#define SOC_ETM_ULP_EVT_HALT_ST_S  10
-/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ULP_EVT_START_INTR_ST    (BIT(11))
-#define SOC_ETM_ULP_EVT_START_INTR_ST_M  (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S)
-#define SOC_ETM_ULP_EVT_START_INTR_ST_V  0x00000001U
-#define SOC_ETM_ULP_EVT_START_INTR_ST_S  11
-/** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_RTC_EVT_TICK_ST    (BIT(12))
-#define SOC_ETM_RTC_EVT_TICK_ST_M  (SOC_ETM_RTC_EVT_TICK_ST_V << SOC_ETM_RTC_EVT_TICK_ST_S)
-#define SOC_ETM_RTC_EVT_TICK_ST_V  0x00000001U
-#define SOC_ETM_RTC_EVT_TICK_ST_S  12
-/** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_RTC_EVT_OVF_ST    (BIT(13))
-#define SOC_ETM_RTC_EVT_OVF_ST_M  (SOC_ETM_RTC_EVT_OVF_ST_V << SOC_ETM_RTC_EVT_OVF_ST_S)
-#define SOC_ETM_RTC_EVT_OVF_ST_V  0x00000001U
-#define SOC_ETM_RTC_EVT_OVF_ST_S  13
-/** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_RTC_EVT_CMP_ST    (BIT(14))
-#define SOC_ETM_RTC_EVT_CMP_ST_M  (SOC_ETM_RTC_EVT_CMP_ST_V << SOC_ETM_RTC_EVT_CMP_ST_S)
-#define SOC_ETM_RTC_EVT_CMP_ST_V  0x00000001U
-#define SOC_ETM_RTC_EVT_CMP_ST_S  14
-/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST    (BIT(15))
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_M  (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S)
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_V  0x00000001U
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S  15
-
-/** SOC_ETM_EVT_ST4_CLR_REG register
- *  Events trigger status clear register
- */
-#define SOC_ETM_EVT_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc)
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR    (BIT(0))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S  0
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR    (BIT(1))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S  1
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR    (BIT(2))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S  2
-/** SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR    (BIT(3))
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M  (SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S  3
-/** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR    (BIT(4))
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_M  (SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V << SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S)
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V  0x00000001U
-#define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S  4
-/** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR    (BIT(5))
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_M  (SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S)
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S  5
-/** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR    (BIT(6))
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_M  (SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S)
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S  6
-/** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR    (BIT(7))
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_M  (SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S)
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S  7
-/** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR    (BIT(8))
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M  (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S)
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S  8
-/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR    (BIT(9))
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M  (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S)
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V  0x00000001U
-#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S  9
-/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ULP_EVT_HALT_ST_CLR    (BIT(10))
-#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M  (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S)
-#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V  0x00000001U
-#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S  10
-/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR    (BIT(11))
-#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M  (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S)
-#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V  0x00000001U
-#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S  11
-/** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_RTC_EVT_TICK_ST_CLR    (BIT(12))
-#define SOC_ETM_RTC_EVT_TICK_ST_CLR_M  (SOC_ETM_RTC_EVT_TICK_ST_CLR_V << SOC_ETM_RTC_EVT_TICK_ST_CLR_S)
-#define SOC_ETM_RTC_EVT_TICK_ST_CLR_V  0x00000001U
-#define SOC_ETM_RTC_EVT_TICK_ST_CLR_S  12
-/** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_RTC_EVT_OVF_ST_CLR    (BIT(13))
-#define SOC_ETM_RTC_EVT_OVF_ST_CLR_M  (SOC_ETM_RTC_EVT_OVF_ST_CLR_V << SOC_ETM_RTC_EVT_OVF_ST_CLR_S)
-#define SOC_ETM_RTC_EVT_OVF_ST_CLR_V  0x00000001U
-#define SOC_ETM_RTC_EVT_OVF_ST_CLR_S  13
-/** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_RTC_EVT_CMP_ST_CLR    (BIT(14))
-#define SOC_ETM_RTC_EVT_CMP_ST_CLR_M  (SOC_ETM_RTC_EVT_CMP_ST_CLR_V << SOC_ETM_RTC_EVT_CMP_ST_CLR_S)
-#define SOC_ETM_RTC_EVT_CMP_ST_CLR_V  0x00000001U
-#define SOC_ETM_RTC_EVT_CMP_ST_CLR_S  14
-/** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR    (BIT(15))
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_M  (SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V << SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S)
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_V  0x00000001U
-#define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S  15
-
-/** SOC_ETM_TASK_ST0_REG register
- *  Tasks trigger status register
- */
-#define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1d0)
-/** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST    (BIT(0))
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST_M  (SOC_ETM_GPIO_TASK_CH0_SET_ST_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST_S  0
-/** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST    (BIT(1))
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST_M  (SOC_ETM_GPIO_TASK_CH1_SET_ST_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST_S  1
-/** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST    (BIT(2))
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST_M  (SOC_ETM_GPIO_TASK_CH2_SET_ST_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST_S  2
-/** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST    (BIT(3))
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST_M  (SOC_ETM_GPIO_TASK_CH3_SET_ST_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST_S  3
-/** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST    (BIT(4))
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST_M  (SOC_ETM_GPIO_TASK_CH4_SET_ST_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST_S  4
-/** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST    (BIT(5))
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST_M  (SOC_ETM_GPIO_TASK_CH5_SET_ST_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST_S  5
-/** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST    (BIT(6))
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST_M  (SOC_ETM_GPIO_TASK_CH6_SET_ST_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST_S  6
-/** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST    (BIT(7))
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST_M  (SOC_ETM_GPIO_TASK_CH7_SET_ST_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_S)
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST_S  7
-/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST    (BIT(8))
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S  8
-/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST    (BIT(9))
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S  9
-/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST    (BIT(10))
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S  10
-/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST    (BIT(11))
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S  11
-/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST    (BIT(12))
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S  12
-/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST    (BIT(13))
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S  13
-/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST    (BIT(14))
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S  14
-/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST    (BIT(15))
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_M  (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S)
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S  15
-/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST    (BIT(16))
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S  16
-/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST    (BIT(17))
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S  17
-/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST    (BIT(18))
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S  18
-/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST    (BIT(19))
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S  19
-/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST    (BIT(20))
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S  20
-/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST    (BIT(21))
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S  21
-/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST    (BIT(22))
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S  22
-/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST    (BIT(23))
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_M  (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S)
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S  23
-/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST    (BIT(24))
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S  24
-/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST    (BIT(25))
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S  25
-/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST    (BIT(26))
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S  26
-/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST    (BIT(27))
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S  27
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST    (BIT(28))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S  28
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST    (BIT(29))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S  29
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST    (BIT(30))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S  30
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST    (BIT(31))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S  31
-
-/** SOC_ETM_TASK_ST0_CLR_REG register
- *  Tasks trigger status clear register
- */
-#define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4)
-/** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR    (BIT(0))
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S  0
-/** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR    (BIT(1))
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S  1
-/** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR    (BIT(2))
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S  2
-/** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR    (BIT(3))
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S  3
-/** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR    (BIT(4))
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S  4
-/** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR    (BIT(5))
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S  5
-/** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR    (BIT(6))
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S  6
-/** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR    (BIT(7))
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S  7
-/** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR    (BIT(8))
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S  8
-/** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR    (BIT(9))
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S  9
-/** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR    (BIT(10))
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S  10
-/** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR    (BIT(11))
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S  11
-/** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR    (BIT(12))
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S  12
-/** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR    (BIT(13))
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S  13
-/** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR    (BIT(14))
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S  14
-/** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR    (BIT(15))
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S  15
-/** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR    (BIT(16))
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S  16
-/** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR    (BIT(17))
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S  17
-/** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR    (BIT(18))
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S  18
-/** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR    (BIT(19))
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S  19
-/** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR    (BIT(20))
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S  20
-/** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR    (BIT(21))
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S  21
-/** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR    (BIT(22))
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S  22
-/** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR    (BIT(23))
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_M  (SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V << SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S)
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S  23
-/** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR    (BIT(24))
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S  24
-/** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR    (BIT(25))
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S  25
-/** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR    (BIT(26))
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S  26
-/** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR    (BIT(27))
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S  27
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger
- *  status.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR    (BIT(28))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S  28
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger
- *  status.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR    (BIT(29))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S  29
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger
- *  status.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR    (BIT(30))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S  30
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger
- *  status.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR    (BIT(31))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S  31
-
-/** SOC_ETM_TASK_ST1_REG register
- *  Tasks trigger status register
- */
-#define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1d8)
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST    (BIT(0))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S  0
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST    (BIT(1))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S  1
-/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST    (BIT(2))
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S  2
-/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST    (BIT(3))
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S  3
-/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST    (BIT(4))
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S  4
-/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST    (BIT(5))
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S  5
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST    (BIT(6))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S  6
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST    (BIT(7))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S  7
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST    (BIT(8))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S  8
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST    (BIT(9))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S  9
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST    (BIT(10))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S  10
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST    (BIT(11))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S  11
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST    (BIT(12))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S  12
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST    (BIT(13))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S  13
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST    (BIT(14))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S  14
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST    (BIT(15))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S  15
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST    (BIT(16))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S  16
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST    (BIT(17))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S  17
-/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST    (BIT(18))
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S  18
-/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST    (BIT(19))
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S  19
-/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST    (BIT(20))
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S  20
-/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST    (BIT(21))
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S  21
-/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST    (BIT(22))
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S  22
-/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST    (BIT(23))
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S  23
-/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST    (BIT(24))
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S  24
-/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST    (BIT(25))
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S  25
-/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST    (BIT(26))
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S  26
-/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST    (BIT(27))
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S  27
-/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST    (BIT(28))
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S  28
-/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST    (BIT(29))
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_M  (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S  29
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST    (BIT(30))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S  30
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST    (BIT(31))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S  31
-
-/** SOC_ETM_TASK_ST1_CLR_REG register
- *  Tasks trigger status clear register
- */
-#define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc)
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger
- *  status.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR    (BIT(0))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S  0
-/** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger
- *  status.\\0: Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR    (BIT(1))
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S  1
-/** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR    (BIT(2))
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S  2
-/** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR    (BIT(3))
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S  3
-/** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR    (BIT(4))
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S  4
-/** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR    (BIT(5))
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S  5
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR    (BIT(6))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S  6
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR    (BIT(7))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S  7
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR    (BIT(8))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S  8
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR    (BIT(9))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S  9
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR    (BIT(10))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S  10
-/** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR    (BIT(11))
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S  11
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR    (BIT(12))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S  12
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR    (BIT(13))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S  13
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR    (BIT(14))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S  14
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR    (BIT(15))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S  15
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR    (BIT(16))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S  16
-/** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR    (BIT(17))
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S  17
-/** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR    (BIT(18))
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S  18
-/** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR    (BIT(19))
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S  19
-/** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR    (BIT(20))
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S  20
-/** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR    (BIT(21))
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S  21
-/** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR    (BIT(22))
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S  22
-/** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR    (BIT(23))
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S  23
-/** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR    (BIT(24))
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S  24
-/** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR    (BIT(25))
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S  25
-/** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR    (BIT(26))
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S  26
-/** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR    (BIT(27))
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S  27
-/** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR    (BIT(28))
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S  28
-/** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR    (BIT(29))
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_M  (SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V << SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S  29
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR    (BIT(30))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S  30
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR    (BIT(31))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S  31
-
-/** SOC_ETM_TASK_ST2_REG register
- *  Tasks trigger status register
- */
-#define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1e0)
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST    (BIT(0))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S  0
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST    (BIT(1))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S  1
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST    (BIT(2))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S  2
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST    (BIT(3))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S  3
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST    (BIT(4))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S  4
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST    (BIT(5))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S  5
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST    (BIT(6))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S  6
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST    (BIT(7))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S  7
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST    (BIT(8))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S  8
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST    (BIT(9))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S  9
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST    (BIT(10))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S  10
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST    (BIT(11))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S  11
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST    (BIT(12))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S  12
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST    (BIT(13))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S  13
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST    (BIT(14))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S  14
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST    (BIT(15))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S  15
-/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST    (BIT(16))
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S  16
-/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST    (BIT(17))
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S)
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S  17
-/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST    (BIT(18))
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S  18
-/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST    (BIT(19))
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S  19
-/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST    (BIT(20))
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S  20
-/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST    (BIT(21))
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S  21
-/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST    (BIT(22))
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S)
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S  22
-/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST    (BIT(23))
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S  23
-/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST    (BIT(24))
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S  24
-/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST    (BIT(25))
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S)
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S  25
-/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST    (BIT(26))
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S  26
-/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST    (BIT(27))
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S)
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S  27
-/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST    (BIT(28))
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S  28
-/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST    (BIT(29))
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S  29
-/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST    (BIT(30))
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S  30
-/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST    (BIT(31))
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S  31
-
-/** SOC_ETM_TASK_ST2_CLR_REG register
- *  Tasks trigger status clear register
- */
-#define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4)
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR    (BIT(0))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S  0
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR    (BIT(1))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S  1
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR    (BIT(2))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S  2
-/** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR    (BIT(3))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S  3
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR    (BIT(4))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S  4
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR    (BIT(5))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S  5
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR    (BIT(6))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S  6
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR    (BIT(7))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S  7
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR    (BIT(8))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S  8
-/** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR    (BIT(9))
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S  9
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR    (BIT(10))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S  10
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR    (BIT(11))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S  11
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR    (BIT(12))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S  12
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR    (BIT(13))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S  13
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR    (BIT(14))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S  14
-/** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR    (BIT(15))
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_M  (SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V << SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S)
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V  0x00000001U
-#define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S  15
-/** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR    (BIT(16))
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S  16
-/** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR    (BIT(17))
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S  17
-/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR    (BIT(18))
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S  18
-/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR    (BIT(19))
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S  19
-/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR    (BIT(20))
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S  20
-/** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR    (BIT(21))
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S  21
-/** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR    (BIT(22))
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S  22
-/** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR    (BIT(23))
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S  23
-/** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR    (BIT(24))
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S  24
-/** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR    (BIT(25))
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_M  (SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S  25
-/** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR    (BIT(26))
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S  26
-/** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR    (BIT(27))
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S  27
-/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR    (BIT(28))
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S  28
-/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR    (BIT(29))
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S  29
-/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR    (BIT(30))
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S  30
-/** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR    (BIT(31))
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S  31
-
-/** SOC_ETM_TASK_ST3_REG register
- *  Tasks trigger status register
- */
-#define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1e8)
-/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST    (BIT(0))
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S)
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S  0
-/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST    (BIT(1))
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S  1
-/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST    (BIT(2))
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S  2
-/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST    (BIT(3))
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S)
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S  3
-/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST    (BIT(4))
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_S  4
-/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST    (BIT(5))
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_S  5
-/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST    (BIT(6))
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_S  6
-/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST    (BIT(7))
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_S  7
-/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST    (BIT(8))
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_S  8
-/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST    (BIT(9))
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_M  (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_S  9
-/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST    (BIT(10))
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_M  (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_S  10
-/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST    (BIT(11))
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_S  11
-/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST    (BIT(12))
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_S  12
-/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST    (BIT(13))
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_S  13
-/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST    (BIT(14))
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_S  14
-/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST    (BIT(15))
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_S  15
-/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1:
- *  Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST    (BIT(16))
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_M  (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_S  16
-/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST    (BIT(17))
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_M  (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_S  17
-/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST    (BIT(18))
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_M  (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_S  18
-/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST    (BIT(19))
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_M  (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S)
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_S  19
-/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST    (BIT(20))
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_M  (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_S  20
-/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST : R/WTC/SS; bitpos: [21]; default: 0;
- *  Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST    (BIT(21))
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_M  (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_S  21
-/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST : R/WTC/SS; bitpos: [22]; default: 0;
- *  Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST    (BIT(22))
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_M  (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_S  22
-/** SOC_ETM_MCPWM0_TASK_CAP0_ST : R/WTC/SS; bitpos: [23]; default: 0;
- *  Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST    (BIT(23))
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST_M  (SOC_ETM_MCPWM0_TASK_CAP0_ST_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST_S  23
-/** SOC_ETM_MCPWM0_TASK_CAP1_ST : R/WTC/SS; bitpos: [24]; default: 0;
- *  Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST    (BIT(24))
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST_M  (SOC_ETM_MCPWM0_TASK_CAP1_ST_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST_S  24
-/** SOC_ETM_MCPWM0_TASK_CAP2_ST : R/WTC/SS; bitpos: [25]; default: 0;
- *  Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST    (BIT(25))
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST_M  (SOC_ETM_MCPWM0_TASK_CAP2_ST_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_S)
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST_S  25
-/** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [26]; default: 0;
- *  Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST    (BIT(26))
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST_M  (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S)
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST_V  0x00000001U
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST_S  26
-/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [27]; default: 0;
- *  Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST    (BIT(27))
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M  (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S)
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V  0x00000001U
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S  27
-/** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [28]; default: 0;
- *  Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_TASK_START0_ST    (BIT(28))
-#define SOC_ETM_ADC_TASK_START0_ST_M  (SOC_ETM_ADC_TASK_START0_ST_V << SOC_ETM_ADC_TASK_START0_ST_S)
-#define SOC_ETM_ADC_TASK_START0_ST_V  0x00000001U
-#define SOC_ETM_ADC_TASK_START0_ST_S  28
-/** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [29]; default: 0;
- *  Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ADC_TASK_STOP0_ST    (BIT(29))
-#define SOC_ETM_ADC_TASK_STOP0_ST_M  (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S)
-#define SOC_ETM_ADC_TASK_STOP0_ST_V  0x00000001U
-#define SOC_ETM_ADC_TASK_STOP0_ST_S  29
-/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [30]; default: 0;
- *  Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_TASK_START0_ST    (BIT(30))
-#define SOC_ETM_REGDMA_TASK_START0_ST_M  (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S)
-#define SOC_ETM_REGDMA_TASK_START0_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START0_ST_S  30
-/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [31]; default: 0;
- *  Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_TASK_START1_ST    (BIT(31))
-#define SOC_ETM_REGDMA_TASK_START1_ST_M  (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S)
-#define SOC_ETM_REGDMA_TASK_START1_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START1_ST_S  31
-
-/** SOC_ETM_TASK_ST3_CLR_REG register
- *  Tasks trigger status clear register
- */
-#define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec)
-/** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR    (BIT(0))
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S  0
-/** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR    (BIT(1))
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S  1
-/** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR    (BIT(2))
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S  2
-/** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR    (BIT(3))
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_M  (SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V << SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S)
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V  0x00000001U
-#define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S  3
-/** SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR    (BIT(4))
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_S  4
-/** SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR    (BIT(5))
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_S  5
-/** SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR    (BIT(6))
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_S  6
-/** SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR    (BIT(7))
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_S  7
-/** SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR    (BIT(8))
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_S  8
-/** SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR    (BIT(9))
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_S  9
-/** SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR    (BIT(10))
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_GEN_STOP_ST_CLR_S  10
-/** SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR    (BIT(11))
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER0_SYN_ST_CLR_S  11
-/** SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR    (BIT(12))
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER1_SYN_ST_CLR_S  12
-/** SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR    (BIT(13))
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER2_SYN_ST_CLR_S  13
-/** SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR    (BIT(14))
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_S  14
-/** SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR    (BIT(15))
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_S  15
-/** SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR    (BIT(16))
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_S  16
-/** SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR    (BIT(17))
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TZ0_OST_ST_CLR_S  17
-/** SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR    (BIT(18))
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TZ1_OST_ST_CLR_S  18
-/** SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR    (BIT(19))
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_TZ2_OST_ST_CLR_S  19
-/** SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR    (BIT(20))
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CLR0_OST_ST_CLR_S  20
-/** SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR : WT; bitpos: [21]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR    (BIT(21))
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CLR1_OST_ST_CLR_S  21
-/** SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR : WT; bitpos: [22]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR    (BIT(22))
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CLR2_OST_ST_CLR_S  22
-/** SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR    (BIT(23))
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CAP0_ST_CLR_S  23
-/** SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR : WT; bitpos: [24]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR    (BIT(24))
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CAP1_ST_CLR_S  24
-/** SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR : WT; bitpos: [25]; default: 0;
- *  Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR    (BIT(25))
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_M  (SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V << SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S)
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_V  0x00000001U
-#define SOC_ETM_MCPWM0_TASK_CAP2_ST_CLR_S  25
-/** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [26]; default: 0;
- *  Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR    (BIT(26))
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M  (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S)
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S  26
-/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [27]; default: 0;
- *  Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR    (BIT(27))
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M  (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S)
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S  27
-/** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [28]; default: 0;
- *  Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ADC_TASK_START0_ST_CLR    (BIT(28))
-#define SOC_ETM_ADC_TASK_START0_ST_CLR_M  (SOC_ETM_ADC_TASK_START0_ST_CLR_V << SOC_ETM_ADC_TASK_START0_ST_CLR_S)
-#define SOC_ETM_ADC_TASK_START0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_TASK_START0_ST_CLR_S  28
-/** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ADC_TASK_STOP0_ST_CLR    (BIT(29))
-#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M  (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S)
-#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V  0x00000001U
-#define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S  29
-/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_TASK_START0_ST_CLR    (BIT(30))
-#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S)
-#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S  30
-/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_TASK_START1_ST_CLR    (BIT(31))
-#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S)
-#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S  31
-
-/** SOC_ETM_TASK_ST4_REG register
- *  Tasks trigger status register
- */
-#define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1f0)
-/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [0]; default: 0;
- *  Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_TASK_START2_ST    (BIT(0))
-#define SOC_ETM_REGDMA_TASK_START2_ST_M  (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S)
-#define SOC_ETM_REGDMA_TASK_START2_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START2_ST_S  0
-/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [1]; default: 0;
- *  Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_REGDMA_TASK_START3_ST    (BIT(1))
-#define SOC_ETM_REGDMA_TASK_START3_ST_M  (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S)
-#define SOC_ETM_REGDMA_TASK_START3_ST_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START3_ST_S  1
-/** SOC_ETM_GDMA_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0;
- *  Represents GDMA_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST    (BIT(2))
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_M  (SOC_ETM_GDMA_TASK_IN_START_CH0_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH0_ST_S)
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_S  2
-/** SOC_ETM_GDMA_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0;
- *  Represents GDMA_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST    (BIT(3))
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_M  (SOC_ETM_GDMA_TASK_IN_START_CH1_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH1_ST_S)
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_S  3
-/** SOC_ETM_GDMA_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0;
- *  Represents GDMA_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST    (BIT(4))
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_M  (SOC_ETM_GDMA_TASK_IN_START_CH2_ST_V << SOC_ETM_GDMA_TASK_IN_START_CH2_ST_S)
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_S  4
-/** SOC_ETM_GDMA_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0;
- *  Represents GDMA_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST    (BIT(5))
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_M  (SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_S)
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_S  5
-/** SOC_ETM_GDMA_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0;
- *  Represents GDMA_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST    (BIT(6))
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_M  (SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_S)
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_S  6
-/** SOC_ETM_GDMA_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [7]; default: 0;
- *  Represents GDMA_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST    (BIT(7))
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_M  (SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_V << SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_S)
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_S  7
-/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [8]; default: 0;
- *  Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST    (BIT(8))
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_M  (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S)
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V  0x00000001U
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S  8
-/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [9]; default: 0;
- *  Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST    (BIT(9))
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_M  (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S)
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V  0x00000001U
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S  9
-/** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [10]; default: 0;
- *  Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_TASK_START_RX_ST    (BIT(10))
-#define SOC_ETM_I2S0_TASK_START_RX_ST_M  (SOC_ETM_I2S0_TASK_START_RX_ST_V << SOC_ETM_I2S0_TASK_START_RX_ST_S)
-#define SOC_ETM_I2S0_TASK_START_RX_ST_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_START_RX_ST_S  10
-/** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [11]; default: 0;
- *  Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_TASK_START_TX_ST    (BIT(11))
-#define SOC_ETM_I2S0_TASK_START_TX_ST_M  (SOC_ETM_I2S0_TASK_START_TX_ST_V << SOC_ETM_I2S0_TASK_START_TX_ST_S)
-#define SOC_ETM_I2S0_TASK_START_TX_ST_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_START_TX_ST_S  11
-/** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [12]; default: 0;
- *  Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST    (BIT(12))
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST_M  (SOC_ETM_I2S0_TASK_STOP_RX_ST_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_S)
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST_S  12
-/** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [13]; default: 0;
- *  Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST    (BIT(13))
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST_M  (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S)
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST_S  13
-/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [14]; default: 0;
- *  Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST    (BIT(14))
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M  (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S)
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V  0x00000001U
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S  14
-/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [15]; default: 0;
- *  Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_ULP_TASK_INT_CPU_ST    (BIT(15))
-#define SOC_ETM_ULP_TASK_INT_CPU_ST_M  (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S)
-#define SOC_ETM_ULP_TASK_INT_CPU_ST_V  0x00000001U
-#define SOC_ETM_ULP_TASK_INT_CPU_ST_S  15
-/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [16]; default: 0;
- *  Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_RTC_TASK_START_ST    (BIT(16))
-#define SOC_ETM_RTC_TASK_START_ST_M  (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S)
-#define SOC_ETM_RTC_TASK_START_ST_V  0x00000001U
-#define SOC_ETM_RTC_TASK_START_ST_S  16
-/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [17]; default: 0;
- *  Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_RTC_TASK_STOP_ST    (BIT(17))
-#define SOC_ETM_RTC_TASK_STOP_ST_M  (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S)
-#define SOC_ETM_RTC_TASK_STOP_ST_V  0x00000001U
-#define SOC_ETM_RTC_TASK_STOP_ST_S  17
-/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [18]; default: 0;
- *  Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_RTC_TASK_CLR_ST    (BIT(18))
-#define SOC_ETM_RTC_TASK_CLR_ST_M  (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S)
-#define SOC_ETM_RTC_TASK_CLR_ST_V  0x00000001U
-#define SOC_ETM_RTC_TASK_CLR_ST_S  18
-/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [19]; default: 0;
- *  Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST    (BIT(19))
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M  (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S)
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V  0x00000001U
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S  19
-/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [20]; default: 0;
- *  Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered
- */
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST    (BIT(20))
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_M  (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S)
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_V  0x00000001U
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S  20
-
-/** SOC_ETM_TASK_ST4_CLR_REG register
- *  Tasks trigger status clear register
- */
-#define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1f4)
-/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [0]; default: 0;
- *  Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_TASK_START2_ST_CLR    (BIT(0))
-#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S)
-#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S  0
-/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [1]; default: 0;
- *  Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_REGDMA_TASK_START3_ST_CLR    (BIT(1))
-#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M  (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S)
-#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V  0x00000001U
-#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S  1
-/** SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [2]; default: 0;
- *  Configures whether or not to clear GDMA_task_in_start_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR    (BIT(2))
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_M  (SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_IN_START_CH0_ST_CLR_S  2
-/** SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [3]; default: 0;
- *  Configures whether or not to clear GDMA_task_in_start_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR    (BIT(3))
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_M  (SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_IN_START_CH1_ST_CLR_S  3
-/** SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [4]; default: 0;
- *  Configures whether or not to clear GDMA_task_in_start_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR    (BIT(4))
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_M  (SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_IN_START_CH2_ST_CLR_S  4
-/** SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [5]; default: 0;
- *  Configures whether or not to clear GDMA_task_out_start_ch0 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR    (BIT(5))
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_M  (SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_S)
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_OUT_START_CH0_ST_CLR_S  5
-/** SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [6]; default: 0;
- *  Configures whether or not to clear GDMA_task_out_start_ch1 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR    (BIT(6))
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_M  (SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_S)
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_OUT_START_CH1_ST_CLR_S  6
-/** SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [7]; default: 0;
- *  Configures whether or not to clear GDMA_task_out_start_ch2 trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR    (BIT(7))
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_M  (SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_S)
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_V  0x00000001U
-#define SOC_ETM_GDMA_TASK_OUT_START_CH2_ST_CLR_S  7
-/** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [8]; default: 0;
- *  Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR    (BIT(8))
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_M  (SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S)
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S  8
-/** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [9]; default: 0;
- *  Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0:
- *  Invalid, No effect\\1: Clear
- */
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR    (BIT(9))
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_M  (SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V << SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S)
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V  0x00000001U
-#define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S  9
-/** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [10]; default: 0;
- *  Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR    (BIT(10))
-#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_M  (SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S)
-#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S  10
-/** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [11]; default: 0;
- *  Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR    (BIT(11))
-#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_M  (SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S)
-#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S  11
-/** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [12]; default: 0;
- *  Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR    (BIT(12))
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_M  (SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S)
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S  12
-/** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [13]; default: 0;
- *  Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR    (BIT(13))
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M  (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S)
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V  0x00000001U
-#define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S  13
-/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [14]; default: 0;
- *  Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR    (BIT(14))
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M  (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S)
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V  0x00000001U
-#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S  14
-/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [15]; default: 0;
- *  Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR    (BIT(15))
-#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M  (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S)
-#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V  0x00000001U
-#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S  15
-/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [16]; default: 0;
- *  Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_RTC_TASK_START_ST_CLR    (BIT(16))
-#define SOC_ETM_RTC_TASK_START_ST_CLR_M  (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S)
-#define SOC_ETM_RTC_TASK_START_ST_CLR_V  0x00000001U
-#define SOC_ETM_RTC_TASK_START_ST_CLR_S  16
-/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [17]; default: 0;
- *  Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_RTC_TASK_STOP_ST_CLR    (BIT(17))
-#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M  (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S)
-#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V  0x00000001U
-#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S  17
-/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [18]; default: 0;
- *  Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No
- *  effect\\1: Clear
- */
-#define SOC_ETM_RTC_TASK_CLR_ST_CLR    (BIT(18))
-#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M  (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S)
-#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V  0x00000001U
-#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S  18
-/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [19]; default: 0;
- *  Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR    (BIT(19))
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M  (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S)
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V  0x00000001U
-#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S  19
-/** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [20]; default: 0;
- *  Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid,
- *  No effect\\1: Clear
- */
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR    (BIT(20))
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_M  (SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V << SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S)
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_V  0x00000001U
-#define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR_S  20
-
-/** SOC_ETM_CLK_EN_REG register
- *  ETM clock enable register
- */
-#define SOC_ETM_CLK_EN_REG (DR_REG_SOC_ETM_BASE + 0x1f8)
-/** SOC_ETM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
- *  when application writes registers\\1: Force open the clock gate for register
- */
-#define SOC_ETM_CLK_EN    (BIT(0))
-#define SOC_ETM_CLK_EN_M  (SOC_ETM_CLK_EN_V << SOC_ETM_CLK_EN_S)
-#define SOC_ETM_CLK_EN_V  0x00000001U
-#define SOC_ETM_CLK_EN_S  0
-
-/** SOC_ETM_DATE_REG register
- *  ETM date register
- */
-#define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1fc)
-/** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36716929;
- *  Configures the version.
- */
-#define SOC_ETM_DATE    0x0FFFFFFFU
-#define SOC_ETM_DATE_M  (SOC_ETM_DATE_V << SOC_ETM_DATE_S)
-#define SOC_ETM_DATE_V  0x0FFFFFFFU
-#define SOC_ETM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/soc_etm_source.h b/components/soc/esp32c5/beta3/include/soc/soc_etm_source.h
deleted file mode 100644
index e8b7e4a951..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/soc_etm_source.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#define GPIO_EVT_CH0_RISE_EDGE 1
-#define GPIO_EVT_CH1_RISE_EDGE 2
-#define GPIO_EVT_CH2_RISE_EDGE 3
-#define GPIO_EVT_CH3_RISE_EDGE 4
-#define GPIO_EVT_CH4_RISE_EDGE 5
-#define GPIO_EVT_CH5_RISE_EDGE 6
-#define GPIO_EVT_CH6_RISE_EDGE 7
-#define GPIO_EVT_CH7_RISE_EDGE 8
-#define GPIO_EVT_CH0_FALL_EDGE 9
-#define GPIO_EVT_CH1_FALL_EDGE 10
-#define GPIO_EVT_CH2_FALL_EDGE 11
-#define GPIO_EVT_CH3_FALL_EDGE 12
-#define GPIO_EVT_CH4_FALL_EDGE 13
-#define GPIO_EVT_CH5_FALL_EDGE 14
-#define GPIO_EVT_CH6_FALL_EDGE 15
-#define GPIO_EVT_CH7_FALL_EDGE 16
-#define GPIO_EVT_CH0_ANY_EDGE 17
-#define GPIO_EVT_CH1_ANY_EDGE 18
-#define GPIO_EVT_CH2_ANY_EDGE 19
-#define GPIO_EVT_CH3_ANY_EDGE 20
-#define GPIO_EVT_CH4_ANY_EDGE 21
-#define GPIO_EVT_CH5_ANY_EDGE 22
-#define GPIO_EVT_CH6_ANY_EDGE 23
-#define GPIO_EVT_CH7_ANY_EDGE 24
-#define GPIO_EVT_ZERO_DET_POS 25
-#define GPIO_EVT_ZERO_DET_NEG 26
-#define LEDC_EVT_DUTY_CHNG_END_CH0 27
-#define LEDC_EVT_DUTY_CHNG_END_CH1 28
-#define LEDC_EVT_DUTY_CHNG_END_CH2 29
-#define LEDC_EVT_DUTY_CHNG_END_CH3 30
-#define LEDC_EVT_DUTY_CHNG_END_CH4 31
-#define LEDC_EVT_DUTY_CHNG_END_CH5 32
-#define LEDC_EVT_OVF_CNT_PLS_CH0 33
-#define LEDC_EVT_OVF_CNT_PLS_CH1 34
-#define LEDC_EVT_OVF_CNT_PLS_CH2 35
-#define LEDC_EVT_OVF_CNT_PLS_CH3 36
-#define LEDC_EVT_OVF_CNT_PLS_CH4 37
-#define LEDC_EVT_OVF_CNT_PLS_CH5 38
-#define LEDC_EVT_TIME_OVF_TIMER0 39
-#define LEDC_EVT_TIME_OVF_TIMER1 40
-#define LEDC_EVT_TIME_OVF_TIMER2 41
-#define LEDC_EVT_TIME_OVF_TIMER3 42
-#define LEDC_EVT_TIMER0_CMP 43
-#define LEDC_EVT_TIMER1_CMP 44
-#define LEDC_EVT_TIMER2_CMP 45
-#define LEDC_EVT_TIMER3_CMP 46
-#define TG0_EVT_CNT_CMP_TIMER0 47
-#define TG0_EVT_CNT_CMP_TIMER1 48
-#define TG1_EVT_CNT_CMP_TIMER0 49
-#define TG1_EVT_CNT_CMP_TIMER1 50
-#define SYSTIMER_EVT_CNT_CMP0 51
-#define SYSTIMER_EVT_CNT_CMP1 52
-#define SYSTIMER_EVT_CNT_CMP2 53
-#define MCPWM0_EVT_TIMER0_STOP 54
-#define MCPWM0_EVT_TIMER1_STOP 55
-#define MCPWM0_EVT_TIMER2_STOP 56
-#define MCPWM0_EVT_TIMER0_TEZ 57
-#define MCPWM0_EVT_TIMER1_TEZ 58
-#define MCPWM0_EVT_TIMER2_TEZ 59
-#define MCPWM0_EVT_TIMER0_TEP 60
-#define MCPWM0_EVT_TIMER1_TEP 61
-#define MCPWM0_EVT_TIMER2_TEP 62
-#define MCPWM0_EVT_OP0_TEA 63
-#define MCPWM0_EVT_OP1_TEA 64
-#define MCPWM0_EVT_OP2_TEA 65
-#define MCPWM0_EVT_OP0_TEB 66
-#define MCPWM0_EVT_OP1_TEB 67
-#define MCPWM0_EVT_OP2_TEB 68
-#define MCPWM0_EVT_F0 69
-#define MCPWM0_EVT_F1 70
-#define MCPWM0_EVT_F2 71
-#define MCPWM0_EVT_F0_CLR 72
-#define MCPWM0_EVT_F1_CLR 73
-#define MCPWM0_EVT_F2_CLR 74
-#define MCPWM0_EVT_TZ0_CBC 75
-#define MCPWM0_EVT_TZ1_CBC 76
-#define MCPWM0_EVT_TZ2_CBC 77
-#define MCPWM0_EVT_TZ0_OST 78
-#define MCPWM0_EVT_TZ1_OST 79
-#define MCPWM0_EVT_TZ2_OST 80
-#define MCPWM0_EVT_CAP0 81
-#define MCPWM0_EVT_CAP1 82
-#define MCPWM0_EVT_CAP2 83
-#define MCPWM0_EVT_OP0_TEE1 84
-#define MCPWM0_EVT_OP1_TEE1 85
-#define MCPWM0_EVT_OP2_TEE1 86
-#define MCPWM0_EVT_OP0_TEE2 87
-#define MCPWM0_EVT_OP1_TEE2 88
-#define MCPWM0_EVT_OP2_TEE2 89
-#define ADC_EVT_CONV_CMPLT0 90
-#define ADC_EVT_EQ_ABOVE_THRESH0 91
-#define ADC_EVT_EQ_ABOVE_THRESH1 92
-#define ADC_EVT_EQ_BELOW_THRESH0 93
-#define ADC_EVT_EQ_BELOW_THRESH1 94
-#define ADC_EVT_RESULT_DONE0 95
-#define ADC_EVT_STOPPED0 96
-#define ADC_EVT_STARTED0 97
-#define REGDMA_EVT_DONE0 98
-#define REGDMA_EVT_DONE1 99
-#define REGDMA_EVT_DONE2 100
-#define REGDMA_EVT_DONE3 101
-#define REGDMA_EVT_ERR0 102
-#define REGDMA_EVT_ERR1 103
-#define REGDMA_EVT_ERR2 104
-#define REGDMA_EVT_ERR3 105
-#define GDMA_EVT_IN_DONE_CH0 106
-#define GDMA_EVT_IN_DONE_CH1 107
-#define GDMA_EVT_IN_DONE_CH2 108
-#define GDMA_EVT_IN_SUC_EOF_CH0 109
-#define GDMA_EVT_IN_SUC_EOF_CH1 110
-#define GDMA_EVT_IN_SUC_EOF_CH2 111
-#define GDMA_EVT_IN_FIFO_EMPTY_CH0 112
-#define GDMA_EVT_IN_FIFO_EMPTY_CH1 113
-#define GDMA_EVT_IN_FIFO_EMPTY_CH2 114
-#define GDMA_EVT_IN_FIFO_FULL_CH0 115
-#define GDMA_EVT_IN_FIFO_FULL_CH1 116
-#define GDMA_EVT_IN_FIFO_FULL_CH2 117
-#define GDMA_EVT_OUT_DONE_CH0 118
-#define GDMA_EVT_OUT_DONE_CH1 119
-#define GDMA_EVT_OUT_DONE_CH2 120
-#define GDMA_EVT_OUT_EOF_CH0 121
-#define GDMA_EVT_OUT_EOF_CH1 122
-#define GDMA_EVT_OUT_EOF_CH2 123
-#define GDMA_EVT_OUT_TOTAL_EOF_CH0 124
-#define GDMA_EVT_OUT_TOTAL_EOF_CH1 125
-#define GDMA_EVT_OUT_TOTAL_EOF_CH2 126
-#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 127
-#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 128
-#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 129
-#define GDMA_EVT_OUT_FIFO_FULL_CH0 130
-#define GDMA_EVT_OUT_FIFO_FULL_CH1 131
-#define GDMA_EVT_OUT_FIFO_FULL_CH2 132
-#define TMPSNSR_EVT_OVER_LIMIT 133
-#define I2S0_EVT_RX_DONE 134
-#define I2S0_EVT_TX_DONE 135
-#define I2S0_EVT_X_WORDS_RECEIVED 136
-#define I2S0_EVT_X_WORDS_SENT 137
-#define ULP_EVT_ERR_INTR 138
-#define ULP_EVT_HALT 139
-#define ULP_EVT_START_INTR 140
-#define RTC_EVT_TICK 141
-#define RTC_EVT_OVF 142
-#define RTC_EVT_CMP 143
-#define PMU_EVT_SLEEP_WEEKUP 144
-#define GPIO_TASK_CH0_SET 1
-#define GPIO_TASK_CH1_SET 2
-#define GPIO_TASK_CH2_SET 3
-#define GPIO_TASK_CH3_SET 4
-#define GPIO_TASK_CH4_SET 5
-#define GPIO_TASK_CH5_SET 6
-#define GPIO_TASK_CH6_SET 7
-#define GPIO_TASK_CH7_SET 8
-#define GPIO_TASK_CH0_CLEAR 9
-#define GPIO_TASK_CH1_CLEAR 10
-#define GPIO_TASK_CH2_CLEAR 11
-#define GPIO_TASK_CH3_CLEAR 12
-#define GPIO_TASK_CH4_CLEAR 13
-#define GPIO_TASK_CH5_CLEAR 14
-#define GPIO_TASK_CH6_CLEAR 15
-#define GPIO_TASK_CH7_CLEAR 16
-#define GPIO_TASK_CH0_TOGGLE 17
-#define GPIO_TASK_CH1_TOGGLE 18
-#define GPIO_TASK_CH2_TOGGLE 19
-#define GPIO_TASK_CH3_TOGGLE 20
-#define GPIO_TASK_CH4_TOGGLE 21
-#define GPIO_TASK_CH5_TOGGLE 22
-#define GPIO_TASK_CH6_TOGGLE 23
-#define GPIO_TASK_CH7_TOGGLE 24
-#define LEDC_TASK_TIMER0_RES_UPDATE 25
-#define LEDC_TASK_TIMER1_RES_UPDATE 26
-#define LEDC_TASK_TIMER2_RES_UPDATE 27
-#define LEDC_TASK_TIMER3_RES_UPDATE 28
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34
-#define LEDC_TASK_TIMER0_CAP 35
-#define LEDC_TASK_TIMER1_CAP 36
-#define LEDC_TASK_TIMER2_CAP 37
-#define LEDC_TASK_TIMER3_CAP 38
-#define LEDC_TASK_SIG_OUT_DIS_CH0 39
-#define LEDC_TASK_SIG_OUT_DIS_CH1 40
-#define LEDC_TASK_SIG_OUT_DIS_CH2 41
-#define LEDC_TASK_SIG_OUT_DIS_CH3 42
-#define LEDC_TASK_SIG_OUT_DIS_CH4 43
-#define LEDC_TASK_SIG_OUT_DIS_CH5 44
-#define LEDC_TASK_OVF_CNT_RST_CH0 45
-#define LEDC_TASK_OVF_CNT_RST_CH1 46
-#define LEDC_TASK_OVF_CNT_RST_CH2 47
-#define LEDC_TASK_OVF_CNT_RST_CH3 48
-#define LEDC_TASK_OVF_CNT_RST_CH4 49
-#define LEDC_TASK_OVF_CNT_RST_CH5 50
-#define LEDC_TASK_TIMER0_RST 51
-#define LEDC_TASK_TIMER1_RST 52
-#define LEDC_TASK_TIMER2_RST 53
-#define LEDC_TASK_TIMER3_RST 54
-#define LEDC_TASK_TIMER0_RESUME 55
-#define LEDC_TASK_TIMER1_RESUME 56
-#define LEDC_TASK_TIMER2_RESUME 57
-#define LEDC_TASK_TIMER3_RESUME 58
-#define LEDC_TASK_TIMER0_PAUSE 59
-#define LEDC_TASK_TIMER1_PAUSE 60
-#define LEDC_TASK_TIMER2_PAUSE 61
-#define LEDC_TASK_TIMER3_PAUSE 62
-#define LEDC_TASK_GAMMA_RESTART_CH0 63
-#define LEDC_TASK_GAMMA_RESTART_CH1 64
-#define LEDC_TASK_GAMMA_RESTART_CH2 65
-#define LEDC_TASK_GAMMA_RESTART_CH3 66
-#define LEDC_TASK_GAMMA_RESTART_CH4 67
-#define LEDC_TASK_GAMMA_RESTART_CH5 68
-#define LEDC_TASK_GAMMA_PAUSE_CH0 69
-#define LEDC_TASK_GAMMA_PAUSE_CH1 70
-#define LEDC_TASK_GAMMA_PAUSE_CH2 71
-#define LEDC_TASK_GAMMA_PAUSE_CH3 72
-#define LEDC_TASK_GAMMA_PAUSE_CH4 73
-#define LEDC_TASK_GAMMA_PAUSE_CH5 74
-#define LEDC_TASK_GAMMA_RESUME_CH0 75
-#define LEDC_TASK_GAMMA_RESUME_CH1 76
-#define LEDC_TASK_GAMMA_RESUME_CH2 77
-#define LEDC_TASK_GAMMA_RESUME_CH3 78
-#define LEDC_TASK_GAMMA_RESUME_CH4 79
-#define LEDC_TASK_GAMMA_RESUME_CH5 80
-#define TG0_TASK_CNT_START_TIMER0 81
-#define TG0_TASK_ALARM_START_TIMER0 82
-#define TG0_TASK_CNT_STOP_TIMER0 83
-#define TG0_TASK_CNT_RELOAD_TIMER0 84
-#define TG0_TASK_CNT_CAP_TIMER0 85
-#define TG0_TASK_CNT_START_TIMER1 86
-#define TG0_TASK_ALARM_START_TIMER1 87
-#define TG0_TASK_CNT_STOP_TIMER1 88
-#define TG0_TASK_CNT_RELOAD_TIMER1 89
-#define TG0_TASK_CNT_CAP_TIMER1 90
-#define TG1_TASK_CNT_START_TIMER0 91
-#define TG1_TASK_ALARM_START_TIMER0 92
-#define TG1_TASK_CNT_STOP_TIMER0 93
-#define TG1_TASK_CNT_RELOAD_TIMER0 94
-#define TG1_TASK_CNT_CAP_TIMER0 95
-#define TG1_TASK_CNT_START_TIMER1 96
-#define TG1_TASK_ALARM_START_TIMER1 97
-#define TG1_TASK_CNT_STOP_TIMER1 98
-#define TG1_TASK_CNT_RELOAD_TIMER1 99
-#define TG1_TASK_CNT_CAP_TIMER1 100
-#define MCPWM0_TASK_CMPR0_A_UP 101
-#define MCPWM0_TASK_CMPR1_A_UP 102
-#define MCPWM0_TASK_CMPR2_A_UP 103
-#define MCPWM0_TASK_CMPR0_B_UP 104
-#define MCPWM0_TASK_CMPR1_B_UP 105
-#define MCPWM0_TASK_CMPR2_B_UP 106
-#define MCPWM0_TASK_GEN_STOP 107
-#define MCPWM0_TASK_TIMER0_SYN 108
-#define MCPWM0_TASK_TIMER1_SYN 109
-#define MCPWM0_TASK_TIMER2_SYN 110
-#define MCPWM0_TASK_TIMER0_PERIOD_UP 111
-#define MCPWM0_TASK_TIMER1_PERIOD_UP 112
-#define MCPWM0_TASK_TIMER2_PERIOD_UP 113
-#define MCPWM0_TASK_TZ0_OST 114
-#define MCPWM0_TASK_TZ1_OST 115
-#define MCPWM0_TASK_TZ2_OST 116
-#define MCPWM0_TASK_CLR0_OST 117
-#define MCPWM0_TASK_CLR1_OST 118
-#define MCPWM0_TASK_CLR2_OST 119
-#define MCPWM0_TASK_CAP0 120
-#define MCPWM0_TASK_CAP1 121
-#define MCPWM0_TASK_CAP2 122
-#define ADC_TASK_SAMPLE0 123
-#define ADC_TASK_SAMPLE1 124
-#define ADC_TASK_START0 125
-#define ADC_TASK_STOP0 126
-#define REGDMA_TASK_START0 127
-#define REGDMA_TASK_START1 128
-#define REGDMA_TASK_START2 129
-#define REGDMA_TASK_START3 130
-#define GDMA_TASK_IN_START_CH0 131
-#define GDMA_TASK_IN_START_CH1 132
-#define GDMA_TASK_IN_START_CH2 133
-#define GDMA_TASK_OUT_START_CH0 134
-#define GDMA_TASK_OUT_START_CH1 135
-#define GDMA_TASK_OUT_START_CH2 136
-#define TMPSNSR_TASK_START_SAMPLE 137
-#define TMPSNSR_TASK_STOP_SAMPLE 138
-#define I2S0_TASK_START_RX 139
-#define I2S0_TASK_START_TX 140
-#define I2S0_TASK_STOP_RX 141
-#define I2S0_TASK_STOP_TX 142
-#define ULP_TASK_WAKEUP_CPU 143
-#define ULP_TASK_INT_CPU 144
-#define RTC_TASK_START 145
-#define RTC_TASK_STOP 146
-#define RTC_TASK_CLR 147
-#define RTC_TASK_TRIGGERFLW 148
-#define PMU_TASK_SLEEP_REQ 149
diff --git a/components/soc/esp32c5/beta3/include/soc/soc_etm_struct.h b/components/soc/esp32c5/beta3/include/soc/soc_etm_struct.h
deleted file mode 100644
index df93face4f..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/soc_etm_struct.h
+++ /dev/null
@@ -1,3649 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Status register */
-/** Type of ch_ena_ad0 register
- *  Channel enable status register
- */
-typedef union {
-    struct {
-        /** ch_enabled0 : R/WTC/WTS; bitpos: [0]; default: 0;
-         *  Represents ch0 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled0:1;
-        /** ch_enabled1 : R/WTC/WTS; bitpos: [1]; default: 0;
-         *  Represents ch1 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled1:1;
-        /** ch_enabled2 : R/WTC/WTS; bitpos: [2]; default: 0;
-         *  Represents ch2 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled2:1;
-        /** ch_enabled3 : R/WTC/WTS; bitpos: [3]; default: 0;
-         *  Represents ch3 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled3:1;
-        /** ch_enabled4 : R/WTC/WTS; bitpos: [4]; default: 0;
-         *  Represents ch4 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled4:1;
-        /** ch_enabled5 : R/WTC/WTS; bitpos: [5]; default: 0;
-         *  Represents ch5 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled5:1;
-        /** ch_enabled6 : R/WTC/WTS; bitpos: [6]; default: 0;
-         *  Represents ch6 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled6:1;
-        /** ch_enabled7 : R/WTC/WTS; bitpos: [7]; default: 0;
-         *  Represents ch7 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled7:1;
-        /** ch_enabled8 : R/WTC/WTS; bitpos: [8]; default: 0;
-         *  Represents ch8 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled8:1;
-        /** ch_enabled9 : R/WTC/WTS; bitpos: [9]; default: 0;
-         *  Represents ch9 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled9:1;
-        /** ch_enabled10 : R/WTC/WTS; bitpos: [10]; default: 0;
-         *  Represents ch10 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled10:1;
-        /** ch_enabled11 : R/WTC/WTS; bitpos: [11]; default: 0;
-         *  Represents ch11 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled11:1;
-        /** ch_enabled12 : R/WTC/WTS; bitpos: [12]; default: 0;
-         *  Represents ch12 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled12:1;
-        /** ch_enabled13 : R/WTC/WTS; bitpos: [13]; default: 0;
-         *  Represents ch13 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled13:1;
-        /** ch_enabled14 : R/WTC/WTS; bitpos: [14]; default: 0;
-         *  Represents ch14 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled14:1;
-        /** ch_enabled15 : R/WTC/WTS; bitpos: [15]; default: 0;
-         *  Represents ch15 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled15:1;
-        /** ch_enabled16 : R/WTC/WTS; bitpos: [16]; default: 0;
-         *  Represents ch16 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled16:1;
-        /** ch_enabled17 : R/WTC/WTS; bitpos: [17]; default: 0;
-         *  Represents ch17 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled17:1;
-        /** ch_enabled18 : R/WTC/WTS; bitpos: [18]; default: 0;
-         *  Represents ch18 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled18:1;
-        /** ch_enabled19 : R/WTC/WTS; bitpos: [19]; default: 0;
-         *  Represents ch19 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled19:1;
-        /** ch_enabled20 : R/WTC/WTS; bitpos: [20]; default: 0;
-         *  Represents ch20 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled20:1;
-        /** ch_enabled21 : R/WTC/WTS; bitpos: [21]; default: 0;
-         *  Represents ch21 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled21:1;
-        /** ch_enabled22 : R/WTC/WTS; bitpos: [22]; default: 0;
-         *  Represents ch22 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled22:1;
-        /** ch_enabled23 : R/WTC/WTS; bitpos: [23]; default: 0;
-         *  Represents ch23 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled23:1;
-        /** ch_enabled24 : R/WTC/WTS; bitpos: [24]; default: 0;
-         *  Represents ch24 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled24:1;
-        /** ch_enabled25 : R/WTC/WTS; bitpos: [25]; default: 0;
-         *  Represents ch25 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled25:1;
-        /** ch_enabled26 : R/WTC/WTS; bitpos: [26]; default: 0;
-         *  Represents ch26 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled26:1;
-        /** ch_enabled27 : R/WTC/WTS; bitpos: [27]; default: 0;
-         *  Represents ch27 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled27:1;
-        /** ch_enabled28 : R/WTC/WTS; bitpos: [28]; default: 0;
-         *  Represents ch28 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled28:1;
-        /** ch_enabled29 : R/WTC/WTS; bitpos: [29]; default: 0;
-         *  Represents ch29 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled29:1;
-        /** ch_enabled30 : R/WTC/WTS; bitpos: [30]; default: 0;
-         *  Represents ch30 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled30:1;
-        /** ch_enabled31 : R/WTC/WTS; bitpos: [31]; default: 0;
-         *  Represents ch31 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled31:1;
-    };
-    uint32_t val;
-} soc_etm_ch_ena_ad0_reg_t;
-
-/** Type of ch_ena_ad1 register
- *  Channel enable status register
- */
-typedef union {
-    struct {
-        /** ch_enabled32 : R/WTC/WTS; bitpos: [0]; default: 0;
-         *  Represents ch32 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled32:1;
-        /** ch_enabled33 : R/WTC/WTS; bitpos: [1]; default: 0;
-         *  Represents ch33 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled33:1;
-        /** ch_enabled34 : R/WTC/WTS; bitpos: [2]; default: 0;
-         *  Represents ch34 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled34:1;
-        /** ch_enabled35 : R/WTC/WTS; bitpos: [3]; default: 0;
-         *  Represents ch35 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled35:1;
-        /** ch_enabled36 : R/WTC/WTS; bitpos: [4]; default: 0;
-         *  Represents ch36 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled36:1;
-        /** ch_enabled37 : R/WTC/WTS; bitpos: [5]; default: 0;
-         *  Represents ch37 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled37:1;
-        /** ch_enabled38 : R/WTC/WTS; bitpos: [6]; default: 0;
-         *  Represents ch38 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled38:1;
-        /** ch_enabled39 : R/WTC/WTS; bitpos: [7]; default: 0;
-         *  Represents ch39 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled39:1;
-        /** ch_enabled40 : R/WTC/WTS; bitpos: [8]; default: 0;
-         *  Represents ch40 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled40:1;
-        /** ch_enabled41 : R/WTC/WTS; bitpos: [9]; default: 0;
-         *  Represents ch41 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled41:1;
-        /** ch_enabled42 : R/WTC/WTS; bitpos: [10]; default: 0;
-         *  Represents ch42 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled42:1;
-        /** ch_enabled43 : R/WTC/WTS; bitpos: [11]; default: 0;
-         *  Represents ch43 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled43:1;
-        /** ch_enabled44 : R/WTC/WTS; bitpos: [12]; default: 0;
-         *  Represents ch44 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled44:1;
-        /** ch_enabled45 : R/WTC/WTS; bitpos: [13]; default: 0;
-         *  Represents ch45 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled45:1;
-        /** ch_enabled46 : R/WTC/WTS; bitpos: [14]; default: 0;
-         *  Represents ch46 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled46:1;
-        /** ch_enabled47 : R/WTC/WTS; bitpos: [15]; default: 0;
-         *  Represents ch47 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled47:1;
-        /** ch_enabled48 : R/WTC/WTS; bitpos: [16]; default: 0;
-         *  Represents ch48 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled48:1;
-        /** ch_enabled49 : R/WTC/WTS; bitpos: [17]; default: 0;
-         *  Represents ch49 enable status.\\0: Disable\\1: Enable
-         */
-        uint32_t ch_enabled49:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} soc_etm_ch_ena_ad1_reg_t;
-
-/** Type of evt_st0 register
- *  Events trigger status register
- */
-typedef union {
-    struct {
-        /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch0_rise_edge_st:1;
-        /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch1_rise_edge_st:1;
-        /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch2_rise_edge_st:1;
-        /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch3_rise_edge_st:1;
-        /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch4_rise_edge_st:1;
-        /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch5_rise_edge_st:1;
-        /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch6_rise_edge_st:1;
-        /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch7_rise_edge_st:1;
-        /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch0_fall_edge_st:1;
-        /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch1_fall_edge_st:1;
-        /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch2_fall_edge_st:1;
-        /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch3_fall_edge_st:1;
-        /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch4_fall_edge_st:1;
-        /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch5_fall_edge_st:1;
-        /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch6_fall_edge_st:1;
-        /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch7_fall_edge_st:1;
-        /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch0_any_edge_st:1;
-        /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch1_any_edge_st:1;
-        /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch2_any_edge_st:1;
-        /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch3_any_edge_st:1;
-        /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch4_any_edge_st:1;
-        /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch5_any_edge_st:1;
-        /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch6_any_edge_st:1;
-        /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_ch7_any_edge_st:1;
-        /** gpio_evt_zero_det_pos_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents GPIO_evt_zero_det_pos trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_zero_det_pos_st:1;
-        /** gpio_evt_zero_det_neg_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents GPIO_evt_zero_det_neg trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_evt_zero_det_neg_st:1;
-        /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_evt_duty_chng_end_ch0_st:1;
-        /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_evt_duty_chng_end_ch1_st:1;
-        /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_evt_duty_chng_end_ch2_st:1;
-        /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_evt_duty_chng_end_ch3_st:1;
-        /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_evt_duty_chng_end_ch4_st:1;
-        /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_evt_duty_chng_end_ch5_st:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st0_reg_t;
-
-/** Type of evt_st1 register
- *  Events trigger status register
- */
-typedef union {
-    struct {
-        /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch0_st:1;
-        /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch1_st:1;
-        /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch2_st:1;
-        /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch3_st:1;
-        /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch4_st:1;
-        /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch5_st:1;
-        /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_time_ovf_timer0_st:1;
-        /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_time_ovf_timer1_st:1;
-        /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_time_ovf_timer2_st:1;
-        /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_time_ovf_timer3_st:1;
-        /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_timer0_cmp_st:1;
-        /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_timer1_cmp_st:1;
-        /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_timer2_cmp_st:1;
-        /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_evt_timer3_cmp_st:1;
-        /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_evt_cnt_cmp_timer0_st:1;
-        /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_evt_cnt_cmp_timer1_st:1;
-        /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_evt_cnt_cmp_timer0_st:1;
-        /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_evt_cnt_cmp_timer1_st:1;
-        /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t systimer_evt_cnt_cmp0_st:1;
-        /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t systimer_evt_cnt_cmp1_st:1;
-        /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t systimer_evt_cnt_cmp2_st:1;
-        /** mcpwm0_evt_timer0_stop_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer0_stop_st:1;
-        /** mcpwm0_evt_timer1_stop_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer1_stop_st:1;
-        /** mcpwm0_evt_timer2_stop_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer2_stop_st:1;
-        /** mcpwm0_evt_timer0_tez_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer0_tez_st:1;
-        /** mcpwm0_evt_timer1_tez_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer1_tez_st:1;
-        /** mcpwm0_evt_timer2_tez_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer2_tez_st:1;
-        /** mcpwm0_evt_timer0_tep_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer0_tep_st:1;
-        /** mcpwm0_evt_timer1_tep_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer1_tep_st:1;
-        /** mcpwm0_evt_timer2_tep_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_timer2_tep_st:1;
-        /** mcpwm0_evt_op0_tea_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op0_tea_st:1;
-        /** mcpwm0_evt_op1_tea_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op1_tea_st:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st1_reg_t;
-
-/** Type of evt_st2 register
- *  Events trigger status register
- */
-typedef union {
-    struct {
-        /** mcpwm0_evt_op2_tea_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op2_tea_st:1;
-        /** mcpwm0_evt_op0_teb_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op0_teb_st:1;
-        /** mcpwm0_evt_op1_teb_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op1_teb_st:1;
-        /** mcpwm0_evt_op2_teb_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op2_teb_st:1;
-        /** mcpwm0_evt_f0_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_f0_st:1;
-        /** mcpwm0_evt_f1_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_f1_st:1;
-        /** mcpwm0_evt_f2_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_f2_st:1;
-        /** mcpwm0_evt_f0_clr_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_f0_clr_st:1;
-        /** mcpwm0_evt_f1_clr_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_f1_clr_st:1;
-        /** mcpwm0_evt_f2_clr_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_f2_clr_st:1;
-        /** mcpwm0_evt_tz0_cbc_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_tz0_cbc_st:1;
-        /** mcpwm0_evt_tz1_cbc_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_tz1_cbc_st:1;
-        /** mcpwm0_evt_tz2_cbc_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_tz2_cbc_st:1;
-        /** mcpwm0_evt_tz0_ost_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_tz0_ost_st:1;
-        /** mcpwm0_evt_tz1_ost_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_tz1_ost_st:1;
-        /** mcpwm0_evt_tz2_ost_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_tz2_ost_st:1;
-        /** mcpwm0_evt_cap0_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_cap0_st:1;
-        /** mcpwm0_evt_cap1_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_cap1_st:1;
-        /** mcpwm0_evt_cap2_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_cap2_st:1;
-        /** mcpwm0_evt_op0_tee1_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op0_tee1_st:1;
-        /** mcpwm0_evt_op1_tee1_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op1_tee1_st:1;
-        /** mcpwm0_evt_op2_tee1_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op2_tee1_st:1;
-        /** mcpwm0_evt_op0_tee2_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op0_tee2_st:1;
-        /** mcpwm0_evt_op1_tee2_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op1_tee2_st:1;
-        /** mcpwm0_evt_op2_tee2_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_evt_op2_tee2_st:1;
-        /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_conv_cmplt0_st:1;
-        /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_eq_above_thresh0_st:1;
-        /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_eq_above_thresh1_st:1;
-        /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_eq_below_thresh0_st:1;
-        /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_eq_below_thresh1_st:1;
-        /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_result_done0_st:1;
-        /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_stopped0_st:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st2_reg_t;
-
-/** Type of evt_st3 register
- *  Events trigger status register
- */
-typedef union {
-    struct {
-        /** adc_evt_started0_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_evt_started0_st:1;
-        /** regdma_evt_done0_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_done0_st:1;
-        /** regdma_evt_done1_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_done1_st:1;
-        /** regdma_evt_done2_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_done2_st:1;
-        /** regdma_evt_done3_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_done3_st:1;
-        /** regdma_evt_err0_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_err0_st:1;
-        /** regdma_evt_err1_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_err1_st:1;
-        /** regdma_evt_err2_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_err2_st:1;
-        /** regdma_evt_err3_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_evt_err3_st:1;
-        /** gdma_evt_in_done_ch0_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents GDMA_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_done_ch0_st:1;
-        /** gdma_evt_in_done_ch1_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents GDMA_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_done_ch1_st:1;
-        /** gdma_evt_in_done_ch2_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents GDMA_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_done_ch2_st:1;
-        /** gdma_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents GDMA_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_suc_eof_ch0_st:1;
-        /** gdma_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents GDMA_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_suc_eof_ch1_st:1;
-        /** gdma_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents GDMA_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_suc_eof_ch2_st:1;
-        /** gdma_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents GDMA_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_in_fifo_empty_ch0_st:1;
-        /** gdma_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents GDMA_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_in_fifo_empty_ch1_st:1;
-        /** gdma_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents GDMA_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_in_fifo_empty_ch2_st:1;
-        /** gdma_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents GDMA_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_fifo_full_ch0_st:1;
-        /** gdma_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents GDMA_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_fifo_full_ch1_st:1;
-        /** gdma_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents GDMA_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_in_fifo_full_ch2_st:1;
-        /** gdma_evt_out_done_ch0_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents GDMA_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_out_done_ch0_st:1;
-        /** gdma_evt_out_done_ch1_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents GDMA_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_out_done_ch1_st:1;
-        /** gdma_evt_out_done_ch2_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents GDMA_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_out_done_ch2_st:1;
-        /** gdma_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents GDMA_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_out_eof_ch0_st:1;
-        /** gdma_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents GDMA_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_out_eof_ch1_st:1;
-        /** gdma_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents GDMA_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_evt_out_eof_ch2_st:1;
-        /** gdma_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents GDMA_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_total_eof_ch0_st:1;
-        /** gdma_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents GDMA_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_total_eof_ch1_st:1;
-        /** gdma_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents GDMA_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_total_eof_ch2_st:1;
-        /** gdma_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents GDMA_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_fifo_empty_ch0_st:1;
-        /** gdma_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents GDMA_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_fifo_empty_ch1_st:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st3_reg_t;
-
-/** Type of evt_st4 register
- *  Events trigger status register
- */
-typedef union {
-    struct {
-        /** gdma_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents GDMA_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_fifo_empty_ch2_st:1;
-        /** gdma_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents GDMA_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_fifo_full_ch0_st:1;
-        /** gdma_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents GDMA_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_fifo_full_ch1_st:1;
-        /** gdma_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents GDMA_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t gdma_evt_out_fifo_full_ch2_st:1;
-        /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tmpsnsr_evt_over_limit_st:1;
-        /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_evt_rx_done_st:1;
-        /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_evt_tx_done_st:1;
-        /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_evt_x_words_received_st:1;
-        /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_evt_x_words_sent_st:1;
-        /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ulp_evt_err_intr_st:1;
-        /** ulp_evt_halt_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ulp_evt_halt_st:1;
-        /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ulp_evt_start_intr_st:1;
-        /** rtc_evt_tick_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t rtc_evt_tick_st:1;
-        /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t rtc_evt_ovf_st:1;
-        /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t rtc_evt_cmp_st:1;
-        /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t pmu_evt_sleep_weekup_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} soc_etm_evt_st4_reg_t;
-
-/** Type of task_st0 register
- *  Tasks trigger status register
- */
-typedef union {
-    struct {
-        /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch0_set_st:1;
-        /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch1_set_st:1;
-        /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch2_set_st:1;
-        /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch3_set_st:1;
-        /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch4_set_st:1;
-        /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch5_set_st:1;
-        /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch6_set_st:1;
-        /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch7_set_st:1;
-        /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch0_clear_st:1;
-        /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch1_clear_st:1;
-        /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch2_clear_st:1;
-        /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch3_clear_st:1;
-        /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch4_clear_st:1;
-        /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch5_clear_st:1;
-        /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch6_clear_st:1;
-        /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch7_clear_st:1;
-        /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch0_toggle_st:1;
-        /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch1_toggle_st:1;
-        /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch2_toggle_st:1;
-        /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch3_toggle_st:1;
-        /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch4_toggle_st:1;
-        /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch5_toggle_st:1;
-        /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch6_toggle_st:1;
-        /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gpio_task_ch7_toggle_st:1;
-        /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_timer0_res_update_st:1;
-        /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_timer1_res_update_st:1;
-        /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_timer2_res_update_st:1;
-        /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_timer3_res_update_st:1;
-        /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_duty_scale_update_ch0_st:1;
-        /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_duty_scale_update_ch1_st:1;
-        /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_duty_scale_update_ch2_st:1;
-        /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_duty_scale_update_ch3_st:1;
-    };
-    uint32_t val;
-} soc_etm_task_st0_reg_t;
-
-/** Type of task_st1 register
- *  Tasks trigger status register
- */
-typedef union {
-    struct {
-        /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_duty_scale_update_ch4_st:1;
-        /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_duty_scale_update_ch5_st:1;
-        /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer0_cap_st:1;
-        /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer1_cap_st:1;
-        /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer2_cap_st:1;
-        /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer3_cap_st:1;
-        /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_sig_out_dis_ch0_st:1;
-        /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_sig_out_dis_ch1_st:1;
-        /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_sig_out_dis_ch2_st:1;
-        /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_sig_out_dis_ch3_st:1;
-        /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_sig_out_dis_ch4_st:1;
-        /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_sig_out_dis_ch5_st:1;
-        /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch0_st:1;
-        /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch1_st:1;
-        /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch2_st:1;
-        /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch3_st:1;
-        /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch4_st:1;
-        /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch5_st:1;
-        /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer0_rst_st:1;
-        /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer1_rst_st:1;
-        /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer2_rst_st:1;
-        /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer3_rst_st:1;
-        /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer0_resume_st:1;
-        /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer1_resume_st:1;
-        /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer2_resume_st:1;
-        /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer3_resume_st:1;
-        /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer0_pause_st:1;
-        /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer1_pause_st:1;
-        /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer2_pause_st:1;
-        /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_timer3_pause_st:1;
-        /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_restart_ch0_st:1;
-        /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_restart_ch1_st:1;
-    };
-    uint32_t val;
-} soc_etm_task_st1_reg_t;
-
-/** Type of task_st2 register
- *  Tasks trigger status register
- */
-typedef union {
-    struct {
-        /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_restart_ch2_st:1;
-        /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_restart_ch3_st:1;
-        /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_restart_ch4_st:1;
-        /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_restart_ch5_st:1;
-        /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_gamma_pause_ch0_st:1;
-        /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_gamma_pause_ch1_st:1;
-        /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_gamma_pause_ch2_st:1;
-        /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_gamma_pause_ch3_st:1;
-        /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_gamma_pause_ch4_st:1;
-        /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ledc_task_gamma_pause_ch5_st:1;
-        /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_resume_ch0_st:1;
-        /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_resume_ch1_st:1;
-        /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_resume_ch2_st:1;
-        /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_resume_ch3_st:1;
-        /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_resume_ch4_st:1;
-        /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t ledc_task_gamma_resume_ch5_st:1;
-        /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_task_cnt_start_timer0_st:1;
-        /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg0_task_alarm_start_timer0_st:1;
-        /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_task_cnt_stop_timer0_st:1;
-        /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg0_task_cnt_reload_timer0_st:1;
-        /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_task_cnt_cap_timer0_st:1;
-        /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_task_cnt_start_timer1_st:1;
-        /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg0_task_alarm_start_timer1_st:1;
-        /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_task_cnt_stop_timer1_st:1;
-        /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg0_task_cnt_reload_timer1_st:1;
-        /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg0_task_cnt_cap_timer1_st:1;
-        /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_task_cnt_start_timer0_st:1;
-        /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg1_task_alarm_start_timer0_st:1;
-        /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_task_cnt_stop_timer0_st:1;
-        /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg1_task_cnt_reload_timer0_st:1;
-        /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_task_cnt_cap_timer0_st:1;
-        /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_task_cnt_start_timer1_st:1;
-    };
-    uint32_t val;
-} soc_etm_task_st2_reg_t;
-
-/** Type of task_st3 register
- *  Tasks trigger status register
- */
-typedef union {
-    struct {
-        /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg1_task_alarm_start_timer1_st:1;
-        /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_task_cnt_stop_timer1_st:1;
-        /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t tg1_task_cnt_reload_timer1_st:1;
-        /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tg1_task_cnt_cap_timer1_st:1;
-        /** mcpwm0_task_cmpr0_a_up_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cmpr0_a_up_st:1;
-        /** mcpwm0_task_cmpr1_a_up_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cmpr1_a_up_st:1;
-        /** mcpwm0_task_cmpr2_a_up_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cmpr2_a_up_st:1;
-        /** mcpwm0_task_cmpr0_b_up_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cmpr0_b_up_st:1;
-        /** mcpwm0_task_cmpr1_b_up_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cmpr1_b_up_st:1;
-        /** mcpwm0_task_cmpr2_b_up_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cmpr2_b_up_st:1;
-        /** mcpwm0_task_gen_stop_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_gen_stop_st:1;
-        /** mcpwm0_task_timer0_syn_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_timer0_syn_st:1;
-        /** mcpwm0_task_timer1_syn_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_timer1_syn_st:1;
-        /** mcpwm0_task_timer2_syn_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_timer2_syn_st:1;
-        /** mcpwm0_task_timer0_period_up_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t mcpwm0_task_timer0_period_up_st:1;
-        /** mcpwm0_task_timer1_period_up_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t mcpwm0_task_timer1_period_up_st:1;
-        /** mcpwm0_task_timer2_period_up_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1:
-         *  Triggered
-         */
-        uint32_t mcpwm0_task_timer2_period_up_st:1;
-        /** mcpwm0_task_tz0_ost_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_tz0_ost_st:1;
-        /** mcpwm0_task_tz1_ost_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_tz1_ost_st:1;
-        /** mcpwm0_task_tz2_ost_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_tz2_ost_st:1;
-        /** mcpwm0_task_clr0_ost_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_clr0_ost_st:1;
-        /** mcpwm0_task_clr1_ost_st : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_clr1_ost_st:1;
-        /** mcpwm0_task_clr2_ost_st : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_clr2_ost_st:1;
-        /** mcpwm0_task_cap0_st : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cap0_st:1;
-        /** mcpwm0_task_cap1_st : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cap1_st:1;
-        /** mcpwm0_task_cap2_st : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t mcpwm0_task_cap2_st:1;
-        /** adc_task_sample0_st : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_task_sample0_st:1;
-        /** adc_task_sample1_st : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_task_sample1_st:1;
-        /** adc_task_start0_st : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_task_start0_st:1;
-        /** adc_task_stop0_st : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t adc_task_stop0_st:1;
-        /** regdma_task_start0_st : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_task_start0_st:1;
-        /** regdma_task_start1_st : R/WTC/SS; bitpos: [31]; default: 0;
-         *  Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_task_start1_st:1;
-    };
-    uint32_t val;
-} soc_etm_task_st3_reg_t;
-
-/** Type of task_st4 register
- *  Tasks trigger status register
- */
-typedef union {
-    struct {
-        /** regdma_task_start2_st : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_task_start2_st:1;
-        /** regdma_task_start3_st : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t regdma_task_start3_st:1;
-        /** gdma_task_in_start_ch0_st : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Represents GDMA_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_task_in_start_ch0_st:1;
-        /** gdma_task_in_start_ch1_st : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Represents GDMA_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_task_in_start_ch1_st:1;
-        /** gdma_task_in_start_ch2_st : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Represents GDMA_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_task_in_start_ch2_st:1;
-        /** gdma_task_out_start_ch0_st : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Represents GDMA_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_task_out_start_ch0_st:1;
-        /** gdma_task_out_start_ch1_st : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Represents GDMA_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_task_out_start_ch1_st:1;
-        /** gdma_task_out_start_ch2_st : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Represents GDMA_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t gdma_task_out_start_ch2_st:1;
-        /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tmpsnsr_task_start_sample_st:1;
-        /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t tmpsnsr_task_stop_sample_st:1;
-        /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_task_start_rx_st:1;
-        /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_task_start_tx_st:1;
-        /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_task_stop_rx_st:1;
-        /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t i2s0_task_stop_tx_st:1;
-        /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ulp_task_wakeup_cpu_st:1;
-        /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t ulp_task_int_cpu_st:1;
-        /** rtc_task_start_st : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t rtc_task_start_st:1;
-        /** rtc_task_stop_st : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t rtc_task_stop_st:1;
-        /** rtc_task_clr_st : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t rtc_task_clr_st:1;
-        /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t rtc_task_triggerflw_st:1;
-        /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered
-         */
-        uint32_t pmu_task_sleep_req_st:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} soc_etm_task_st4_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of ch_ena_ad0_set register
- *  Channel enable set register
- */
-typedef union {
-    struct {
-        /** ch_enable0 : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable0:1;
-        /** ch_enable1 : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable1:1;
-        /** ch_enable2 : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable2:1;
-        /** ch_enable3 : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable3:1;
-        /** ch_enable4 : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable4:1;
-        /** ch_enable5 : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable5:1;
-        /** ch_enable6 : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable6:1;
-        /** ch_enable7 : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable7:1;
-        /** ch_enable8 : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable8:1;
-        /** ch_enable9 : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable9:1;
-        /** ch_enable10 : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable10:1;
-        /** ch_enable11 : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable11:1;
-        /** ch_enable12 : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable12:1;
-        /** ch_enable13 : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable13:1;
-        /** ch_enable14 : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable14:1;
-        /** ch_enable15 : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable15:1;
-        /** ch_enable16 : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable16:1;
-        /** ch_enable17 : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable17:1;
-        /** ch_enable18 : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable18:1;
-        /** ch_enable19 : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable19:1;
-        /** ch_enable20 : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable20:1;
-        /** ch_enable21 : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable21:1;
-        /** ch_enable22 : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable22:1;
-        /** ch_enable23 : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable23:1;
-        /** ch_enable24 : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable24:1;
-        /** ch_enable25 : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable25:1;
-        /** ch_enable26 : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable26:1;
-        /** ch_enable27 : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable27:1;
-        /** ch_enable28 : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable28:1;
-        /** ch_enable29 : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable29:1;
-        /** ch_enable30 : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable30:1;
-        /** ch_enable31 : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable31:1;
-    };
-    uint32_t val;
-} soc_etm_ch_ena_ad0_set_reg_t;
-
-/** Type of ch_ena_ad0_clr register
- *  Channel enable clear register
- */
-typedef union {
-    struct {
-        /** ch_disable0 : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable0:1;
-        /** ch_disable1 : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable1:1;
-        /** ch_disable2 : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable2:1;
-        /** ch_disable3 : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable3:1;
-        /** ch_disable4 : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable4:1;
-        /** ch_disable5 : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable5:1;
-        /** ch_disable6 : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable6:1;
-        /** ch_disable7 : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable7:1;
-        /** ch_disable8 : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable8:1;
-        /** ch_disable9 : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable9:1;
-        /** ch_disable10 : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable10:1;
-        /** ch_disable11 : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable11:1;
-        /** ch_disable12 : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable12:1;
-        /** ch_disable13 : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable13:1;
-        /** ch_disable14 : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable14:1;
-        /** ch_disable15 : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable15:1;
-        /** ch_disable16 : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable16:1;
-        /** ch_disable17 : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable17:1;
-        /** ch_disable18 : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable18:1;
-        /** ch_disable19 : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable19:1;
-        /** ch_disable20 : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable20:1;
-        /** ch_disable21 : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable21:1;
-        /** ch_disable22 : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable22:1;
-        /** ch_disable23 : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable23:1;
-        /** ch_disable24 : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable24:1;
-        /** ch_disable25 : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable25:1;
-        /** ch_disable26 : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable26:1;
-        /** ch_disable27 : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable27:1;
-        /** ch_disable28 : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable28:1;
-        /** ch_disable29 : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable29:1;
-        /** ch_disable30 : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable30:1;
-        /** ch_disable31 : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable31:1;
-    };
-    uint32_t val;
-} soc_etm_ch_ena_ad0_clr_reg_t;
-
-/** Type of ch_ena_ad1_set register
- *  Channel enable set register
- */
-typedef union {
-    struct {
-        /** ch_enable32 : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable32:1;
-        /** ch_enable33 : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable33:1;
-        /** ch_enable34 : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable34:1;
-        /** ch_enable35 : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable35:1;
-        /** ch_enable36 : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable36:1;
-        /** ch_enable37 : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable37:1;
-        /** ch_enable38 : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable38:1;
-        /** ch_enable39 : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable39:1;
-        /** ch_enable40 : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable40:1;
-        /** ch_enable41 : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable41:1;
-        /** ch_enable42 : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable42:1;
-        /** ch_enable43 : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable43:1;
-        /** ch_enable44 : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable44:1;
-        /** ch_enable45 : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable45:1;
-        /** ch_enable46 : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable46:1;
-        /** ch_enable47 : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable47:1;
-        /** ch_enable48 : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable48:1;
-        /** ch_enable49 : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable
-         */
-        uint32_t ch_enable49:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} soc_etm_ch_ena_ad1_set_reg_t;
-
-/** Type of ch_ena_ad1_clr register
- *  Channel enable clear register
- */
-typedef union {
-    struct {
-        /** ch_disable32 : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable32:1;
-        /** ch_disable33 : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable33:1;
-        /** ch_disable34 : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable34:1;
-        /** ch_disable35 : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable35:1;
-        /** ch_disable36 : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable36:1;
-        /** ch_disable37 : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable37:1;
-        /** ch_disable38 : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable38:1;
-        /** ch_disable39 : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable39:1;
-        /** ch_disable40 : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable40:1;
-        /** ch_disable41 : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable41:1;
-        /** ch_disable42 : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable42:1;
-        /** ch_disable43 : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable43:1;
-        /** ch_disable44 : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable44:1;
-        /** ch_disable45 : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable45:1;
-        /** ch_disable46 : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable46:1;
-        /** ch_disable47 : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable47:1;
-        /** ch_disable48 : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable48:1;
-        /** ch_disable49 : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ch_disable49:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} soc_etm_ch_ena_ad1_clr_reg_t;
-
-/** Type of chn_evt_id register
- *  channeln event id register
- */
-typedef union {
-    struct {
-        /** evt_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures ch0_evt_id
-         */
-        uint32_t evt_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_chn_evt_id_reg_t;
-
-/** Type of chn_task_id register
- *  channeln task id register
- */
-typedef union {
-    struct {
-        /** task_id : R/W; bitpos: [7:0]; default: 0;
-         *  Configures task_id
-         */
-        uint32_t task_id:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} soc_etm_chn_task_id_reg_t;
-
-
-/** Type of evt_st0_clr register
- *  Events trigger status clear register
- */
-typedef union {
-    struct {
-        /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch0_rise_edge_st_clr:1;
-        /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch1_rise_edge_st_clr:1;
-        /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch2_rise_edge_st_clr:1;
-        /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch3_rise_edge_st_clr:1;
-        /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch4_rise_edge_st_clr:1;
-        /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch5_rise_edge_st_clr:1;
-        /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch6_rise_edge_st_clr:1;
-        /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch7_rise_edge_st_clr:1;
-        /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch0_fall_edge_st_clr:1;
-        /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch1_fall_edge_st_clr:1;
-        /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch2_fall_edge_st_clr:1;
-        /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch3_fall_edge_st_clr:1;
-        /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch4_fall_edge_st_clr:1;
-        /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch5_fall_edge_st_clr:1;
-        /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch6_fall_edge_st_clr:1;
-        /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch7_fall_edge_st_clr:1;
-        /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch0_any_edge_st_clr:1;
-        /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch1_any_edge_st_clr:1;
-        /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch2_any_edge_st_clr:1;
-        /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch3_any_edge_st_clr:1;
-        /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch4_any_edge_st_clr:1;
-        /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch5_any_edge_st_clr:1;
-        /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch6_any_edge_st_clr:1;
-        /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_ch7_any_edge_st_clr:1;
-        /** gpio_evt_zero_det_pos_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_zero_det_pos trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_zero_det_pos_st_clr:1;
-        /** gpio_evt_zero_det_neg_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear GPIO_evt_zero_det_neg trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_evt_zero_det_neg_st_clr:1;
-        /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_duty_chng_end_ch0_st_clr:1;
-        /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_duty_chng_end_ch1_st_clr:1;
-        /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_duty_chng_end_ch2_st_clr:1;
-        /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_duty_chng_end_ch3_st_clr:1;
-        /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_duty_chng_end_ch4_st_clr:1;
-        /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_duty_chng_end_ch5_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st0_clr_reg_t;
-
-/** Type of evt_st1_clr register
- *  Events trigger status clear register
- */
-typedef union {
-    struct {
-        /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr:1;
-        /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr:1;
-        /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr:1;
-        /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr:1;
-        /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr:1;
-        /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr:1;
-        /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_time_ovf_timer0_st_clr:1;
-        /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_time_ovf_timer1_st_clr:1;
-        /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_time_ovf_timer2_st_clr:1;
-        /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_evt_time_ovf_timer3_st_clr:1;
-        /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t ledc_evt_timer0_cmp_st_clr:1;
-        /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t ledc_evt_timer1_cmp_st_clr:1;
-        /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t ledc_evt_timer2_cmp_st_clr:1;
-        /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t ledc_evt_timer3_cmp_st_clr:1;
-        /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_evt_cnt_cmp_timer0_st_clr:1;
-        /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_evt_cnt_cmp_timer1_st_clr:1;
-        /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_evt_cnt_cmp_timer0_st_clr:1;
-        /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_evt_cnt_cmp_timer1_st_clr:1;
-        /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t systimer_evt_cnt_cmp0_st_clr:1;
-        /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t systimer_evt_cnt_cmp1_st_clr:1;
-        /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t systimer_evt_cnt_cmp2_st_clr:1;
-        /** mcpwm0_evt_timer0_stop_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer0_stop_st_clr:1;
-        /** mcpwm0_evt_timer1_stop_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer1_stop_st_clr:1;
-        /** mcpwm0_evt_timer2_stop_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer2_stop_st_clr:1;
-        /** mcpwm0_evt_timer0_tez_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer0_tez_st_clr:1;
-        /** mcpwm0_evt_timer1_tez_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer1_tez_st_clr:1;
-        /** mcpwm0_evt_timer2_tez_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer2_tez_st_clr:1;
-        /** mcpwm0_evt_timer0_tep_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer0_tep_st_clr:1;
-        /** mcpwm0_evt_timer1_tep_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer1_tep_st_clr:1;
-        /** mcpwm0_evt_timer2_tep_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_timer2_tep_st_clr:1;
-        /** mcpwm0_evt_op0_tea_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op0_tea_st_clr:1;
-        /** mcpwm0_evt_op1_tea_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op1_tea_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st1_clr_reg_t;
-
-/** Type of evt_st2_clr register
- *  Events trigger status clear register
- */
-typedef union {
-    struct {
-        /** mcpwm0_evt_op2_tea_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op2_tea_st_clr:1;
-        /** mcpwm0_evt_op0_teb_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op0_teb_st_clr:1;
-        /** mcpwm0_evt_op1_teb_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op1_teb_st_clr:1;
-        /** mcpwm0_evt_op2_teb_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op2_teb_st_clr:1;
-        /** mcpwm0_evt_f0_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_f0_st_clr:1;
-        /** mcpwm0_evt_f1_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_f1_st_clr:1;
-        /** mcpwm0_evt_f2_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_f2_st_clr:1;
-        /** mcpwm0_evt_f0_clr_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_f0_clr_st_clr:1;
-        /** mcpwm0_evt_f1_clr_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_f1_clr_st_clr:1;
-        /** mcpwm0_evt_f2_clr_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_f2_clr_st_clr:1;
-        /** mcpwm0_evt_tz0_cbc_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_tz0_cbc_st_clr:1;
-        /** mcpwm0_evt_tz1_cbc_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_tz1_cbc_st_clr:1;
-        /** mcpwm0_evt_tz2_cbc_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_tz2_cbc_st_clr:1;
-        /** mcpwm0_evt_tz0_ost_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_tz0_ost_st_clr:1;
-        /** mcpwm0_evt_tz1_ost_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_tz1_ost_st_clr:1;
-        /** mcpwm0_evt_tz2_ost_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_tz2_ost_st_clr:1;
-        /** mcpwm0_evt_cap0_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_cap0_st_clr:1;
-        /** mcpwm0_evt_cap1_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_cap1_st_clr:1;
-        /** mcpwm0_evt_cap2_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_cap2_st_clr:1;
-        /** mcpwm0_evt_op0_tee1_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op0_tee1_st_clr:1;
-        /** mcpwm0_evt_op1_tee1_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op1_tee1_st_clr:1;
-        /** mcpwm0_evt_op2_tee1_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op2_tee1_st_clr:1;
-        /** mcpwm0_evt_op0_tee2_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op0_tee2_st_clr:1;
-        /** mcpwm0_evt_op1_tee2_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op1_tee2_st_clr:1;
-        /** mcpwm0_evt_op2_tee2_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_evt_op2_tee2_st_clr:1;
-        /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t adc_evt_conv_cmplt0_st_clr:1;
-        /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t adc_evt_eq_above_thresh0_st_clr:1;
-        /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t adc_evt_eq_above_thresh1_st_clr:1;
-        /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t adc_evt_eq_below_thresh0_st_clr:1;
-        /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t adc_evt_eq_below_thresh1_st_clr:1;
-        /** adc_evt_result_done0_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t adc_evt_result_done0_st_clr:1;
-        /** adc_evt_stopped0_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t adc_evt_stopped0_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st2_clr_reg_t;
-
-/** Type of evt_st3_clr register
- *  Events trigger status clear register
- */
-typedef union {
-    struct {
-        /** adc_evt_started0_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t adc_evt_started0_st_clr:1;
-        /** regdma_evt_done0_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_done0_st_clr:1;
-        /** regdma_evt_done1_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_done1_st_clr:1;
-        /** regdma_evt_done2_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_done2_st_clr:1;
-        /** regdma_evt_done3_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_done3_st_clr:1;
-        /** regdma_evt_err0_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_err0_st_clr:1;
-        /** regdma_evt_err1_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_err1_st_clr:1;
-        /** regdma_evt_err2_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_err2_st_clr:1;
-        /** regdma_evt_err3_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t regdma_evt_err3_st_clr:1;
-        /** gdma_evt_in_done_ch0_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_done_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_done_ch0_st_clr:1;
-        /** gdma_evt_in_done_ch1_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_done_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_done_ch1_st_clr:1;
-        /** gdma_evt_in_done_ch2_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_done_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_done_ch2_st_clr:1;
-        /** gdma_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_suc_eof_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_suc_eof_ch0_st_clr:1;
-        /** gdma_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_suc_eof_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_suc_eof_ch1_st_clr:1;
-        /** gdma_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_suc_eof_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_suc_eof_ch2_st_clr:1;
-        /** gdma_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_fifo_empty_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_fifo_empty_ch0_st_clr:1;
-        /** gdma_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_fifo_empty_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_fifo_empty_ch1_st_clr:1;
-        /** gdma_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_fifo_empty_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_fifo_empty_ch2_st_clr:1;
-        /** gdma_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_fifo_full_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_fifo_full_ch0_st_clr:1;
-        /** gdma_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_fifo_full_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_fifo_full_ch1_st_clr:1;
-        /** gdma_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_in_fifo_full_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_in_fifo_full_ch2_st_clr:1;
-        /** gdma_evt_out_done_ch0_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_done_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_done_ch0_st_clr:1;
-        /** gdma_evt_out_done_ch1_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_done_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_done_ch1_st_clr:1;
-        /** gdma_evt_out_done_ch2_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_done_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_done_ch2_st_clr:1;
-        /** gdma_evt_out_eof_ch0_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_eof_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_eof_ch0_st_clr:1;
-        /** gdma_evt_out_eof_ch1_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_eof_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_eof_ch1_st_clr:1;
-        /** gdma_evt_out_eof_ch2_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_eof_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_eof_ch2_st_clr:1;
-        /** gdma_evt_out_total_eof_ch0_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_total_eof_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_total_eof_ch0_st_clr:1;
-        /** gdma_evt_out_total_eof_ch1_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_total_eof_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_total_eof_ch1_st_clr:1;
-        /** gdma_evt_out_total_eof_ch2_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_total_eof_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_total_eof_ch2_st_clr:1;
-        /** gdma_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_fifo_empty_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_fifo_empty_ch0_st_clr:1;
-        /** gdma_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_fifo_empty_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_fifo_empty_ch1_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_evt_st3_clr_reg_t;
-
-/** Type of evt_st4_clr register
- *  Events trigger status clear register
- */
-typedef union {
-    struct {
-        /** gdma_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_fifo_empty_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_fifo_empty_ch2_st_clr:1;
-        /** gdma_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_fifo_full_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_fifo_full_ch0_st_clr:1;
-        /** gdma_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_fifo_full_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_fifo_full_ch1_st_clr:1;
-        /** gdma_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear GDMA_evt_out_fifo_full_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_evt_out_fifo_full_ch2_st_clr:1;
-        /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tmpsnsr_evt_over_limit_st_clr:1;
-        /** i2s0_evt_rx_done_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t i2s0_evt_rx_done_st_clr:1;
-        /** i2s0_evt_tx_done_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t i2s0_evt_tx_done_st_clr:1;
-        /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t i2s0_evt_x_words_received_st_clr:1;
-        /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t i2s0_evt_x_words_sent_st_clr:1;
-        /** ulp_evt_err_intr_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t ulp_evt_err_intr_st_clr:1;
-        /** ulp_evt_halt_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t ulp_evt_halt_st_clr:1;
-        /** ulp_evt_start_intr_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t ulp_evt_start_intr_st_clr:1;
-        /** rtc_evt_tick_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t rtc_evt_tick_st_clr:1;
-        /** rtc_evt_ovf_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t rtc_evt_ovf_st_clr:1;
-        /** rtc_evt_cmp_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t rtc_evt_cmp_st_clr:1;
-        /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t pmu_evt_sleep_weekup_st_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} soc_etm_evt_st4_clr_reg_t;
-
-/** Type of task_st0_clr register
- *  Tasks trigger status clear register
- */
-typedef union {
-    struct {
-        /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch0_set_st_clr:1;
-        /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch1_set_st_clr:1;
-        /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch2_set_st_clr:1;
-        /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch3_set_st_clr:1;
-        /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch4_set_st_clr:1;
-        /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch5_set_st_clr:1;
-        /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch6_set_st_clr:1;
-        /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch7_set_st_clr:1;
-        /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch0_clear_st_clr:1;
-        /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch1_clear_st_clr:1;
-        /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch2_clear_st_clr:1;
-        /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch3_clear_st_clr:1;
-        /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch4_clear_st_clr:1;
-        /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch5_clear_st_clr:1;
-        /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch6_clear_st_clr:1;
-        /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch7_clear_st_clr:1;
-        /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch0_toggle_st_clr:1;
-        /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch1_toggle_st_clr:1;
-        /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch2_toggle_st_clr:1;
-        /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch3_toggle_st_clr:1;
-        /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch4_toggle_st_clr:1;
-        /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch5_toggle_st_clr:1;
-        /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch6_toggle_st_clr:1;
-        /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gpio_task_ch7_toggle_st_clr:1;
-        /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer0_res_update_st_clr:1;
-        /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer1_res_update_st_clr:1;
-        /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer2_res_update_st_clr:1;
-        /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer3_res_update_st_clr:1;
-        /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger
-         *  status.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_duty_scale_update_ch0_st_clr:1;
-        /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger
-         *  status.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_duty_scale_update_ch1_st_clr:1;
-        /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger
-         *  status.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_duty_scale_update_ch2_st_clr:1;
-        /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger
-         *  status.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_duty_scale_update_ch3_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_task_st0_clr_reg_t;
-
-/** Type of task_st1_clr register
- *  Tasks trigger status clear register
- */
-typedef union {
-    struct {
-        /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger
-         *  status.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_duty_scale_update_ch4_st_clr:1;
-        /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger
-         *  status.\\0: Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_duty_scale_update_ch5_st_clr:1;
-        /** ledc_task_timer0_cap_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer0_cap_st_clr:1;
-        /** ledc_task_timer1_cap_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer1_cap_st_clr:1;
-        /** ledc_task_timer2_cap_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer2_cap_st_clr:1;
-        /** ledc_task_timer3_cap_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer3_cap_st_clr:1;
-        /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_sig_out_dis_ch0_st_clr:1;
-        /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_sig_out_dis_ch1_st_clr:1;
-        /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_sig_out_dis_ch2_st_clr:1;
-        /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_sig_out_dis_ch3_st_clr:1;
-        /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_sig_out_dis_ch4_st_clr:1;
-        /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_sig_out_dis_ch5_st_clr:1;
-        /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr:1;
-        /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr:1;
-        /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr:1;
-        /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr:1;
-        /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr:1;
-        /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr:1;
-        /** ledc_task_timer0_rst_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer0_rst_st_clr:1;
-        /** ledc_task_timer1_rst_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer1_rst_st_clr:1;
-        /** ledc_task_timer2_rst_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer2_rst_st_clr:1;
-        /** ledc_task_timer3_rst_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer3_rst_st_clr:1;
-        /** ledc_task_timer0_resume_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer0_resume_st_clr:1;
-        /** ledc_task_timer1_resume_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer1_resume_st_clr:1;
-        /** ledc_task_timer2_resume_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer2_resume_st_clr:1;
-        /** ledc_task_timer3_resume_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer3_resume_st_clr:1;
-        /** ledc_task_timer0_pause_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer0_pause_st_clr:1;
-        /** ledc_task_timer1_pause_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer1_pause_st_clr:1;
-        /** ledc_task_timer2_pause_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer2_pause_st_clr:1;
-        /** ledc_task_timer3_pause_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_timer3_pause_st_clr:1;
-        /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_restart_ch0_st_clr:1;
-        /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_restart_ch1_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_task_st1_clr_reg_t;
-
-/** Type of task_st2_clr register
- *  Tasks trigger status clear register
- */
-typedef union {
-    struct {
-        /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_restart_ch2_st_clr:1;
-        /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_restart_ch3_st_clr:1;
-        /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_restart_ch4_st_clr:1;
-        /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_restart_ch5_st_clr:1;
-        /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_pause_ch0_st_clr:1;
-        /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_pause_ch1_st_clr:1;
-        /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_pause_ch2_st_clr:1;
-        /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_pause_ch3_st_clr:1;
-        /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_pause_ch4_st_clr:1;
-        /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_pause_ch5_st_clr:1;
-        /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_resume_ch0_st_clr:1;
-        /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_resume_ch1_st_clr:1;
-        /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_resume_ch2_st_clr:1;
-        /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_resume_ch3_st_clr:1;
-        /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_resume_ch4_st_clr:1;
-        /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t ledc_task_gamma_resume_ch5_st_clr:1;
-        /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_start_timer0_st_clr:1;
-        /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_alarm_start_timer0_st_clr:1;
-        /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_stop_timer0_st_clr:1;
-        /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_reload_timer0_st_clr:1;
-        /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_cap_timer0_st_clr:1;
-        /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_start_timer1_st_clr:1;
-        /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_alarm_start_timer1_st_clr:1;
-        /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_stop_timer1_st_clr:1;
-        /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_reload_timer1_st_clr:1;
-        /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg0_task_cnt_cap_timer1_st_clr:1;
-        /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_start_timer0_st_clr:1;
-        /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_alarm_start_timer0_st_clr:1;
-        /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_stop_timer0_st_clr:1;
-        /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_reload_timer0_st_clr:1;
-        /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_cap_timer0_st_clr:1;
-        /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_start_timer1_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_task_st2_clr_reg_t;
-
-/** Type of task_st3_clr register
- *  Tasks trigger status clear register
- */
-typedef union {
-    struct {
-        /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_alarm_start_timer1_st_clr:1;
-        /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_stop_timer1_st_clr:1;
-        /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_reload_timer1_st_clr:1;
-        /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tg1_task_cnt_cap_timer1_st_clr:1;
-        /** mcpwm0_task_cmpr0_a_up_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cmpr0_a_up_st_clr:1;
-        /** mcpwm0_task_cmpr1_a_up_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cmpr1_a_up_st_clr:1;
-        /** mcpwm0_task_cmpr2_a_up_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cmpr2_a_up_st_clr:1;
-        /** mcpwm0_task_cmpr0_b_up_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cmpr0_b_up_st_clr:1;
-        /** mcpwm0_task_cmpr1_b_up_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cmpr1_b_up_st_clr:1;
-        /** mcpwm0_task_cmpr2_b_up_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cmpr2_b_up_st_clr:1;
-        /** mcpwm0_task_gen_stop_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_gen_stop_st_clr:1;
-        /** mcpwm0_task_timer0_syn_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_timer0_syn_st_clr:1;
-        /** mcpwm0_task_timer1_syn_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_timer1_syn_st_clr:1;
-        /** mcpwm0_task_timer2_syn_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_timer2_syn_st_clr:1;
-        /** mcpwm0_task_timer0_period_up_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_timer0_period_up_st_clr:1;
-        /** mcpwm0_task_timer1_period_up_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_timer1_period_up_st_clr:1;
-        /** mcpwm0_task_timer2_period_up_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_timer2_period_up_st_clr:1;
-        /** mcpwm0_task_tz0_ost_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_tz0_ost_st_clr:1;
-        /** mcpwm0_task_tz1_ost_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_tz1_ost_st_clr:1;
-        /** mcpwm0_task_tz2_ost_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_tz2_ost_st_clr:1;
-        /** mcpwm0_task_clr0_ost_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_clr0_ost_st_clr:1;
-        /** mcpwm0_task_clr1_ost_st_clr : WT; bitpos: [21]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_clr1_ost_st_clr:1;
-        /** mcpwm0_task_clr2_ost_st_clr : WT; bitpos: [22]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_clr2_ost_st_clr:1;
-        /** mcpwm0_task_cap0_st_clr : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cap0_st_clr:1;
-        /** mcpwm0_task_cap1_st_clr : WT; bitpos: [24]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cap1_st_clr:1;
-        /** mcpwm0_task_cap2_st_clr : WT; bitpos: [25]; default: 0;
-         *  Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t mcpwm0_task_cap2_st_clr:1;
-        /** adc_task_sample0_st_clr : WT; bitpos: [26]; default: 0;
-         *  Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t adc_task_sample0_st_clr:1;
-        /** adc_task_sample1_st_clr : WT; bitpos: [27]; default: 0;
-         *  Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t adc_task_sample1_st_clr:1;
-        /** adc_task_start0_st_clr : WT; bitpos: [28]; default: 0;
-         *  Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t adc_task_start0_st_clr:1;
-        /** adc_task_stop0_st_clr : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t adc_task_stop0_st_clr:1;
-        /** regdma_task_start0_st_clr : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t regdma_task_start0_st_clr:1;
-        /** regdma_task_start1_st_clr : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t regdma_task_start1_st_clr:1;
-    };
-    uint32_t val;
-} soc_etm_task_st3_clr_reg_t;
-
-/** Type of task_st4_clr register
- *  Tasks trigger status clear register
- */
-typedef union {
-    struct {
-        /** regdma_task_start2_st_clr : WT; bitpos: [0]; default: 0;
-         *  Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t regdma_task_start2_st_clr:1;
-        /** regdma_task_start3_st_clr : WT; bitpos: [1]; default: 0;
-         *  Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t regdma_task_start3_st_clr:1;
-        /** gdma_task_in_start_ch0_st_clr : WT; bitpos: [2]; default: 0;
-         *  Configures whether or not to clear GDMA_task_in_start_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_task_in_start_ch0_st_clr:1;
-        /** gdma_task_in_start_ch1_st_clr : WT; bitpos: [3]; default: 0;
-         *  Configures whether or not to clear GDMA_task_in_start_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_task_in_start_ch1_st_clr:1;
-        /** gdma_task_in_start_ch2_st_clr : WT; bitpos: [4]; default: 0;
-         *  Configures whether or not to clear GDMA_task_in_start_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_task_in_start_ch2_st_clr:1;
-        /** gdma_task_out_start_ch0_st_clr : WT; bitpos: [5]; default: 0;
-         *  Configures whether or not to clear GDMA_task_out_start_ch0 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_task_out_start_ch0_st_clr:1;
-        /** gdma_task_out_start_ch1_st_clr : WT; bitpos: [6]; default: 0;
-         *  Configures whether or not to clear GDMA_task_out_start_ch1 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_task_out_start_ch1_st_clr:1;
-        /** gdma_task_out_start_ch2_st_clr : WT; bitpos: [7]; default: 0;
-         *  Configures whether or not to clear GDMA_task_out_start_ch2 trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t gdma_task_out_start_ch2_st_clr:1;
-        /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [8]; default: 0;
-         *  Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tmpsnsr_task_start_sample_st_clr:1;
-        /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [9]; default: 0;
-         *  Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0:
-         *  Invalid, No effect\\1: Clear
-         */
-        uint32_t tmpsnsr_task_stop_sample_st_clr:1;
-        /** i2s0_task_start_rx_st_clr : WT; bitpos: [10]; default: 0;
-         *  Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t i2s0_task_start_rx_st_clr:1;
-        /** i2s0_task_start_tx_st_clr : WT; bitpos: [11]; default: 0;
-         *  Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t i2s0_task_start_tx_st_clr:1;
-        /** i2s0_task_stop_rx_st_clr : WT; bitpos: [12]; default: 0;
-         *  Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t i2s0_task_stop_rx_st_clr:1;
-        /** i2s0_task_stop_tx_st_clr : WT; bitpos: [13]; default: 0;
-         *  Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t i2s0_task_stop_tx_st_clr:1;
-        /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [14]; default: 0;
-         *  Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t ulp_task_wakeup_cpu_st_clr:1;
-        /** ulp_task_int_cpu_st_clr : WT; bitpos: [15]; default: 0;
-         *  Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t ulp_task_int_cpu_st_clr:1;
-        /** rtc_task_start_st_clr : WT; bitpos: [16]; default: 0;
-         *  Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t rtc_task_start_st_clr:1;
-        /** rtc_task_stop_st_clr : WT; bitpos: [17]; default: 0;
-         *  Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t rtc_task_stop_st_clr:1;
-        /** rtc_task_clr_st_clr : WT; bitpos: [18]; default: 0;
-         *  Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No
-         *  effect\\1: Clear
-         */
-        uint32_t rtc_task_clr_st_clr:1;
-        /** rtc_task_triggerflw_st_clr : WT; bitpos: [19]; default: 0;
-         *  Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t rtc_task_triggerflw_st_clr:1;
-        /** pmu_task_sleep_req_st_clr : WT; bitpos: [20]; default: 0;
-         *  Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid,
-         *  No effect\\1: Clear
-         */
-        uint32_t pmu_task_sleep_req_st_clr:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} soc_etm_task_st4_clr_reg_t;
-
-/** Type of clk_en register
- *  ETM clock enable register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
-         *  when application writes registers\\1: Force open the clock gate for register
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} soc_etm_clk_en_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  ETM date register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36716929;
-         *  Configures the version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} soc_etm_date_reg_t;
-
-
-typedef struct soc_etm_dev_t {
-    volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
-    volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
-    volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
-    volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
-    volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
-    volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
-    volatile struct {
-        soc_etm_chn_evt_id_reg_t evt_id;
-        soc_etm_chn_task_id_reg_t task_id;
-    } channel[50];
-    volatile soc_etm_evt_st0_reg_t evt_st0;
-    volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
-    volatile soc_etm_evt_st1_reg_t evt_st1;
-    volatile soc_etm_evt_st1_clr_reg_t evt_st1_clr;
-    volatile soc_etm_evt_st2_reg_t evt_st2;
-    volatile soc_etm_evt_st2_clr_reg_t evt_st2_clr;
-    volatile soc_etm_evt_st3_reg_t evt_st3;
-    volatile soc_etm_evt_st3_clr_reg_t evt_st3_clr;
-    volatile soc_etm_evt_st4_reg_t evt_st4;
-    volatile soc_etm_evt_st4_clr_reg_t evt_st4_clr;
-    volatile soc_etm_task_st0_reg_t task_st0;
-    volatile soc_etm_task_st0_clr_reg_t task_st0_clr;
-    volatile soc_etm_task_st1_reg_t task_st1;
-    volatile soc_etm_task_st1_clr_reg_t task_st1_clr;
-    volatile soc_etm_task_st2_reg_t task_st2;
-    volatile soc_etm_task_st2_clr_reg_t task_st2_clr;
-    volatile soc_etm_task_st3_reg_t task_st3;
-    volatile soc_etm_task_st3_clr_reg_t task_st3_clr;
-    volatile soc_etm_task_st4_reg_t task_st4;
-    volatile soc_etm_task_st4_clr_reg_t task_st4_clr;
-    volatile soc_etm_clk_en_reg_t clk_en;
-    volatile soc_etm_date_reg_t date;
-} soc_etm_dev_t;
-
-extern soc_etm_dev_t SOC_ETM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(soc_etm_dev_t) == 0x200, "Invalid size of soc_etm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/soc_pins.h b/components/soc/esp32c5/beta3/include/soc/soc_pins.h
deleted file mode 100644
index 064950aaaa..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/soc_pins.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * Pin definition header file. The long term plan is to have a single soc_pins.h for all
- * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
- * peripheral and include them here to avoid developing conflicts in those header files.
- */
-
-#pragma once
-
-#include "soc/gpio_pins.h"
-#include "soc/spi_pins.h"
diff --git a/components/soc/esp32c5/beta3/include/soc/spi1_mem_reg.h b/components/soc/esp32c5/beta3/include/soc/spi1_mem_reg.h
deleted file mode 100644
index 75ad9765f7..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/spi1_mem_reg.h
+++ /dev/null
@@ -1,1232 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI1_MEM_CMD_REG register
- *  SPI1 memory command register
- */
-#define SPI1_MEM_CMD_REG (DR_REG_SPIMEM1_BASE + 0x0)
-/** SPI1_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
- *  The current status of SPI1 master FSM.
- */
-#define SPI1_MEM_MST_ST    0x0000000FU
-#define SPI1_MEM_MST_ST_M  (SPI1_MEM_MST_ST_V << SPI1_MEM_MST_ST_S)
-#define SPI1_MEM_MST_ST_V  0x0000000FU
-#define SPI1_MEM_MST_ST_S  0
-/** SPI1_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
- *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
- *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
- *  6:write data state, 7: done state, 8: read data end state.
- */
-#define SPI1_MEM_SLV_ST    0x0000000FU
-#define SPI1_MEM_SLV_ST_M  (SPI1_MEM_SLV_ST_V << SPI1_MEM_SLV_ST_S)
-#define SPI1_MEM_SLV_ST_V  0x0000000FU
-#define SPI1_MEM_SLV_ST_S  4
-/** SPI1_MEM_USR : R/W/SC; bitpos: [18]; default: 0;
- *  User define command enable.  An operation will be triggered when the bit is set.
- *  The bit will be cleared once the operation done.1: enable 0: disable.
- */
-#define SPI1_MEM_USR    (BIT(18))
-#define SPI1_MEM_USR_M  (SPI1_MEM_USR_V << SPI1_MEM_USR_S)
-#define SPI1_MEM_USR_V  0x00000001U
-#define SPI1_MEM_USR_S  18
-
-/** SPI1_MEM_ADDR_REG register
- *  SPI1 address register
- */
-#define SPI1_MEM_ADDR_REG (DR_REG_SPIMEM1_BASE + 0x4)
-/** SPI1_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
- *  address, the bit24-bit31 are the byte length of a transfer.
- */
-#define SPI1_MEM_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI1_MEM_USR_ADDR_VALUE_M  (SPI1_MEM_USR_ADDR_VALUE_V << SPI1_MEM_USR_ADDR_VALUE_S)
-#define SPI1_MEM_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI1_MEM_USR_ADDR_VALUE_S  0
-
-/** SPI1_MEM_CTRL_REG register
- *  SPI1 control register.
- */
-#define SPI1_MEM_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x8)
-/** SPI1_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
- *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
- *  level of SPI bus is output by the MSPI controller.
- */
-#define SPI1_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI1_MEM_FDUMMY_RIN_M  (SPI1_MEM_FDUMMY_RIN_V << SPI1_MEM_FDUMMY_RIN_S)
-#define SPI1_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI1_MEM_FDUMMY_RIN_S  2
-/** SPI1_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
- *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
- *  level of SPI bus is output by the MSPI controller.
- */
-#define SPI1_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI1_MEM_FDUMMY_WOUT_M  (SPI1_MEM_FDUMMY_WOUT_V << SPI1_MEM_FDUMMY_WOUT_S)
-#define SPI1_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI1_MEM_FDUMMY_WOUT_S  3
-/** SPI1_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
- *  Apply 8 signals during write-data phase 1:enable 0: disable
- */
-#define SPI1_MEM_FDOUT_OCT    (BIT(4))
-#define SPI1_MEM_FDOUT_OCT_M  (SPI1_MEM_FDOUT_OCT_V << SPI1_MEM_FDOUT_OCT_S)
-#define SPI1_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI1_MEM_FDOUT_OCT_S  4
-/** SPI1_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0;
- *  Apply 8 signals during read-data phase 1:enable 0: disable
- */
-#define SPI1_MEM_FDIN_OCT    (BIT(5))
-#define SPI1_MEM_FDIN_OCT_M  (SPI1_MEM_FDIN_OCT_V << SPI1_MEM_FDIN_OCT_S)
-#define SPI1_MEM_FDIN_OCT_V  0x00000001U
-#define SPI1_MEM_FDIN_OCT_S  5
-/** SPI1_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0;
- *  Apply 8 signals during address phase 1:enable 0: disable
- */
-#define SPI1_MEM_FADDR_OCT    (BIT(6))
-#define SPI1_MEM_FADDR_OCT_M  (SPI1_MEM_FADDR_OCT_V << SPI1_MEM_FADDR_OCT_S)
-#define SPI1_MEM_FADDR_OCT_V  0x00000001U
-#define SPI1_MEM_FADDR_OCT_S  6
-/** SPI1_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
- *  Apply 4 signals during command phase 1:enable 0: disable
- */
-#define SPI1_MEM_FCMD_QUAD    (BIT(8))
-#define SPI1_MEM_FCMD_QUAD_M  (SPI1_MEM_FCMD_QUAD_V << SPI1_MEM_FCMD_QUAD_S)
-#define SPI1_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI1_MEM_FCMD_QUAD_S  8
-/** SPI1_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0;
- *  Apply 8 signals during command phase 1:enable 0: disable
- */
-#define SPI1_MEM_FCMD_OCT    (BIT(9))
-#define SPI1_MEM_FCMD_OCT_M  (SPI1_MEM_FCMD_OCT_V << SPI1_MEM_FCMD_OCT_S)
-#define SPI1_MEM_FCMD_OCT_V  0x00000001U
-#define SPI1_MEM_FCMD_OCT_S  9
-/** SPI1_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
- *  and spi_mem_fread_dout. 1: enable 0: disable.
- */
-#define SPI1_MEM_FASTRD_MODE    (BIT(13))
-#define SPI1_MEM_FASTRD_MODE_M  (SPI1_MEM_FASTRD_MODE_V << SPI1_MEM_FASTRD_MODE_S)
-#define SPI1_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI1_MEM_FASTRD_MODE_S  13
-/** SPI1_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
- */
-#define SPI1_MEM_FREAD_DUAL    (BIT(14))
-#define SPI1_MEM_FREAD_DUAL_M  (SPI1_MEM_FREAD_DUAL_V << SPI1_MEM_FREAD_DUAL_S)
-#define SPI1_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI1_MEM_FREAD_DUAL_S  14
-/** SPI1_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
- *  The bit is used to set MISO line polarity, 1: high 0, low
- */
-#define SPI1_MEM_Q_POL    (BIT(18))
-#define SPI1_MEM_Q_POL_M  (SPI1_MEM_Q_POL_V << SPI1_MEM_Q_POL_S)
-#define SPI1_MEM_Q_POL_V  0x00000001U
-#define SPI1_MEM_Q_POL_S  18
-/** SPI1_MEM_D_POL : R/W; bitpos: [19]; default: 1;
- *  The bit is used to set MOSI line polarity, 1: high 0, low
- */
-#define SPI1_MEM_D_POL    (BIT(19))
-#define SPI1_MEM_D_POL_M  (SPI1_MEM_D_POL_V << SPI1_MEM_D_POL_S)
-#define SPI1_MEM_D_POL_V  0x00000001U
-#define SPI1_MEM_D_POL_S  19
-/** SPI1_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
- *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
- */
-#define SPI1_MEM_FREAD_QUAD    (BIT(20))
-#define SPI1_MEM_FREAD_QUAD_M  (SPI1_MEM_FREAD_QUAD_V << SPI1_MEM_FREAD_QUAD_S)
-#define SPI1_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI1_MEM_FREAD_QUAD_S  20
-/** SPI1_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
- *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
- */
-#define SPI1_MEM_WP_REG    (BIT(21))
-#define SPI1_MEM_WP_REG_M  (SPI1_MEM_WP_REG_V << SPI1_MEM_WP_REG_S)
-#define SPI1_MEM_WP_REG_V  0x00000001U
-#define SPI1_MEM_WP_REG_S  21
-/** SPI1_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
- *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
- *  0: disable.
- */
-#define SPI1_MEM_FREAD_DIO    (BIT(23))
-#define SPI1_MEM_FREAD_DIO_M  (SPI1_MEM_FREAD_DIO_V << SPI1_MEM_FREAD_DIO_S)
-#define SPI1_MEM_FREAD_DIO_V  0x00000001U
-#define SPI1_MEM_FREAD_DIO_S  23
-/** SPI1_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
- *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
- *  0: disable.
- */
-#define SPI1_MEM_FREAD_QIO    (BIT(24))
-#define SPI1_MEM_FREAD_QIO_M  (SPI1_MEM_FREAD_QIO_V << SPI1_MEM_FREAD_QIO_S)
-#define SPI1_MEM_FREAD_QIO_V  0x00000001U
-#define SPI1_MEM_FREAD_QIO_S  24
-
-/** SPI1_MEM_CTRL1_REG register
- *  SPI1 control1 register.
- */
-#define SPI1_MEM_CTRL1_REG (DR_REG_SPIMEM1_BASE + 0xc)
-/** SPI1_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
- *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
- */
-#define SPI1_MEM_CLK_MODE    0x00000003U
-#define SPI1_MEM_CLK_MODE_M  (SPI1_MEM_CLK_MODE_V << SPI1_MEM_CLK_MODE_S)
-#define SPI1_MEM_CLK_MODE_V  0x00000003U
-#define SPI1_MEM_CLK_MODE_S  0
-
-/** SPI1_MEM_CTRL2_REG register
- *  SPI1 control2 register.
- */
-#define SPI1_MEM_CTRL2_REG (DR_REG_SPIMEM1_BASE + 0x10)
-/** SPI1_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
- *  The FSM will be reset.
- */
-#define SPI1_MEM_SYNC_RESET    (BIT(31))
-#define SPI1_MEM_SYNC_RESET_M  (SPI1_MEM_SYNC_RESET_V << SPI1_MEM_SYNC_RESET_S)
-#define SPI1_MEM_SYNC_RESET_V  0x00000001U
-#define SPI1_MEM_SYNC_RESET_S  31
-
-/** SPI1_MEM_CLOCK_REG register
- *  SPI1 clock division control register.
- */
-#define SPI1_MEM_CLOCK_REG (DR_REG_SPIMEM1_BASE + 0x14)
-/** SPI1_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
- *  In the master mode it must be equal to spi_mem_clkcnt_N.
- */
-#define SPI1_MEM_CLKCNT_L    0x000000FFU
-#define SPI1_MEM_CLKCNT_L_M  (SPI1_MEM_CLKCNT_L_V << SPI1_MEM_CLKCNT_L_S)
-#define SPI1_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI1_MEM_CLKCNT_L_S  0
-/** SPI1_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
- *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
- */
-#define SPI1_MEM_CLKCNT_H    0x000000FFU
-#define SPI1_MEM_CLKCNT_H_M  (SPI1_MEM_CLKCNT_H_V << SPI1_MEM_CLKCNT_H_S)
-#define SPI1_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI1_MEM_CLKCNT_H_S  8
-/** SPI1_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
- *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- *  system/(spi_mem_clkcnt_N+1)
- */
-#define SPI1_MEM_CLKCNT_N    0x000000FFU
-#define SPI1_MEM_CLKCNT_N_M  (SPI1_MEM_CLKCNT_N_V << SPI1_MEM_CLKCNT_N_S)
-#define SPI1_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI1_MEM_CLKCNT_N_S  16
-/** SPI1_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
- *  reserved
- */
-#define SPI1_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI1_MEM_CLK_EQU_SYSCLK_M  (SPI1_MEM_CLK_EQU_SYSCLK_V << SPI1_MEM_CLK_EQU_SYSCLK_S)
-#define SPI1_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI1_MEM_CLK_EQU_SYSCLK_S  31
-
-/** SPI1_MEM_USER_REG register
- *  SPI1 user register.
- */
-#define SPI1_MEM_USER_REG (DR_REG_SPIMEM1_BASE + 0x18)
-/** SPI1_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
- */
-#define SPI1_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI1_MEM_CK_OUT_EDGE_M  (SPI1_MEM_CK_OUT_EDGE_V << SPI1_MEM_CK_OUT_EDGE_S)
-#define SPI1_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI1_MEM_CK_OUT_EDGE_S  9
-/** SPI1_MEM_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
- *  In the write operations read-data phase apply 2 signals
- */
-#define SPI1_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI1_MEM_FWRITE_DUAL_M  (SPI1_MEM_FWRITE_DUAL_V << SPI1_MEM_FWRITE_DUAL_S)
-#define SPI1_MEM_FWRITE_DUAL_V  0x00000001U
-#define SPI1_MEM_FWRITE_DUAL_S  12
-/** SPI1_MEM_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
- *  In the write operations read-data phase apply 4 signals
- */
-#define SPI1_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI1_MEM_FWRITE_QUAD_M  (SPI1_MEM_FWRITE_QUAD_V << SPI1_MEM_FWRITE_QUAD_S)
-#define SPI1_MEM_FWRITE_QUAD_V  0x00000001U
-#define SPI1_MEM_FWRITE_QUAD_S  13
-/** SPI1_MEM_FWRITE_DIO : R/W; bitpos: [14]; default: 0;
- *  In the write operations address phase and read-data phase apply 2 signals.
- */
-#define SPI1_MEM_FWRITE_DIO    (BIT(14))
-#define SPI1_MEM_FWRITE_DIO_M  (SPI1_MEM_FWRITE_DIO_V << SPI1_MEM_FWRITE_DIO_S)
-#define SPI1_MEM_FWRITE_DIO_V  0x00000001U
-#define SPI1_MEM_FWRITE_DIO_S  14
-/** SPI1_MEM_FWRITE_QIO : R/W; bitpos: [15]; default: 0;
- *  In the write operations address phase and read-data phase apply 4 signals.
- */
-#define SPI1_MEM_FWRITE_QIO    (BIT(15))
-#define SPI1_MEM_FWRITE_QIO_M  (SPI1_MEM_FWRITE_QIO_V << SPI1_MEM_FWRITE_QIO_S)
-#define SPI1_MEM_FWRITE_QIO_V  0x00000001U
-#define SPI1_MEM_FWRITE_QIO_S  15
-/** SPI1_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- *  SPI clock is disable in dummy phase when the bit is enable.
- */
-#define SPI1_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI1_MEM_USR_DUMMY_IDLE_M  (SPI1_MEM_USR_DUMMY_IDLE_V << SPI1_MEM_USR_DUMMY_IDLE_S)
-#define SPI1_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI1_MEM_USR_DUMMY_IDLE_S  26
-/** SPI1_MEM_USR_MOSI : R/W; bitpos: [27]; default: 0;
- *  This bit enable the write-data phase of an operation.
- */
-#define SPI1_MEM_USR_MOSI    (BIT(27))
-#define SPI1_MEM_USR_MOSI_M  (SPI1_MEM_USR_MOSI_V << SPI1_MEM_USR_MOSI_S)
-#define SPI1_MEM_USR_MOSI_V  0x00000001U
-#define SPI1_MEM_USR_MOSI_S  27
-/** SPI1_MEM_USR_MISO : R/W; bitpos: [28]; default: 0;
- *  This bit enable the read-data phase of an operation.
- */
-#define SPI1_MEM_USR_MISO    (BIT(28))
-#define SPI1_MEM_USR_MISO_M  (SPI1_MEM_USR_MISO_V << SPI1_MEM_USR_MISO_S)
-#define SPI1_MEM_USR_MISO_V  0x00000001U
-#define SPI1_MEM_USR_MISO_S  28
-/** SPI1_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- *  This bit enable the dummy phase of an operation.
- */
-#define SPI1_MEM_USR_DUMMY    (BIT(29))
-#define SPI1_MEM_USR_DUMMY_M  (SPI1_MEM_USR_DUMMY_V << SPI1_MEM_USR_DUMMY_S)
-#define SPI1_MEM_USR_DUMMY_V  0x00000001U
-#define SPI1_MEM_USR_DUMMY_S  29
-/** SPI1_MEM_USR_ADDR : R/W; bitpos: [30]; default: 0;
- *  This bit enable the address phase of an operation.
- */
-#define SPI1_MEM_USR_ADDR    (BIT(30))
-#define SPI1_MEM_USR_ADDR_M  (SPI1_MEM_USR_ADDR_V << SPI1_MEM_USR_ADDR_S)
-#define SPI1_MEM_USR_ADDR_V  0x00000001U
-#define SPI1_MEM_USR_ADDR_S  30
-/** SPI1_MEM_USR_COMMAND : R/W; bitpos: [31]; default: 1;
- *  This bit enable the command phase of an operation.
- */
-#define SPI1_MEM_USR_COMMAND    (BIT(31))
-#define SPI1_MEM_USR_COMMAND_M  (SPI1_MEM_USR_COMMAND_V << SPI1_MEM_USR_COMMAND_S)
-#define SPI1_MEM_USR_COMMAND_V  0x00000001U
-#define SPI1_MEM_USR_COMMAND_S  31
-
-/** SPI1_MEM_USER1_REG register
- *  SPI1 user1 register.
- */
-#define SPI1_MEM_USER1_REG (DR_REG_SPIMEM1_BASE + 0x1c)
-/** SPI1_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
- *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
- *  (cycle_num-1).
- */
-#define SPI1_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI1_MEM_USR_DUMMY_CYCLELEN_M  (SPI1_MEM_USR_DUMMY_CYCLELEN_V << SPI1_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI1_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI1_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI1_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
- *  The length in bits of address phase. The register value shall be (bit_num-1).
- */
-#define SPI1_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI1_MEM_USR_ADDR_BITLEN_M  (SPI1_MEM_USR_ADDR_BITLEN_V << SPI1_MEM_USR_ADDR_BITLEN_S)
-#define SPI1_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI1_MEM_USR_ADDR_BITLEN_S  26
-
-/** SPI1_MEM_USER2_REG register
- *  SPI1 user2 register.
- */
-#define SPI1_MEM_USER2_REG (DR_REG_SPIMEM1_BASE + 0x20)
-/** SPI1_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- *  The value of  command.
- */
-#define SPI1_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI1_MEM_USR_COMMAND_VALUE_M  (SPI1_MEM_USR_COMMAND_VALUE_V << SPI1_MEM_USR_COMMAND_VALUE_S)
-#define SPI1_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI1_MEM_USR_COMMAND_VALUE_S  0
-/** SPI1_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- *  The length in bits of command phase. The register value shall be (bit_num-1)
- */
-#define SPI1_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI1_MEM_USR_COMMAND_BITLEN_M  (SPI1_MEM_USR_COMMAND_BITLEN_V << SPI1_MEM_USR_COMMAND_BITLEN_S)
-#define SPI1_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI1_MEM_USR_COMMAND_BITLEN_S  28
-
-/** SPI1_MEM_MOSI_DLEN_REG register
- *  SPI1 send data bit length control register.
- */
-#define SPI1_MEM_MOSI_DLEN_REG (DR_REG_SPIMEM1_BASE + 0x24)
-/** SPI1_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
- *  The length in bits of write-data. The register value shall be (bit_num-1).
- */
-#define SPI1_MEM_USR_MOSI_DBITLEN    0x000003FFU
-#define SPI1_MEM_USR_MOSI_DBITLEN_M  (SPI1_MEM_USR_MOSI_DBITLEN_V << SPI1_MEM_USR_MOSI_DBITLEN_S)
-#define SPI1_MEM_USR_MOSI_DBITLEN_V  0x000003FFU
-#define SPI1_MEM_USR_MOSI_DBITLEN_S  0
-
-/** SPI1_MEM_MISO_DLEN_REG register
- *  SPI1 receive data bit length control register.
- */
-#define SPI1_MEM_MISO_DLEN_REG (DR_REG_SPIMEM1_BASE + 0x28)
-/** SPI1_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
- *  The length in bits of  read-data. The register value shall be (bit_num-1).
- */
-#define SPI1_MEM_USR_MISO_DBITLEN    0x000003FFU
-#define SPI1_MEM_USR_MISO_DBITLEN_M  (SPI1_MEM_USR_MISO_DBITLEN_V << SPI1_MEM_USR_MISO_DBITLEN_S)
-#define SPI1_MEM_USR_MISO_DBITLEN_V  0x000003FFU
-#define SPI1_MEM_USR_MISO_DBITLEN_S  0
-
-/** SPI1_MEM_RD_STATUS_REG register
- *  SPI1 status register.
- */
-#define SPI1_MEM_RD_STATUS_REG (DR_REG_SPIMEM1_BASE + 0x2c)
-/** SPI1_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
- *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
- */
-#define SPI1_MEM_STATUS    0x0000FFFFU
-#define SPI1_MEM_STATUS_M  (SPI1_MEM_STATUS_V << SPI1_MEM_STATUS_S)
-#define SPI1_MEM_STATUS_V  0x0000FFFFU
-#define SPI1_MEM_STATUS_S  0
-
-/** SPI1_MEM_MISC_REG register
- *  SPI1 misc register
- */
-#define SPI1_MEM_MISC_REG (DR_REG_SPIMEM1_BASE + 0x34)
-/** SPI1_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
- *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
- *  device, such as flash, external RAM and so on.
- */
-#define SPI1_MEM_CS0_DIS    (BIT(0))
-#define SPI1_MEM_CS0_DIS_M  (SPI1_MEM_CS0_DIS_V << SPI1_MEM_CS0_DIS_S)
-#define SPI1_MEM_CS0_DIS_V  0x00000001U
-#define SPI1_MEM_CS0_DIS_S  0
-/** SPI1_MEM_CS1_DIS : R/W; bitpos: [1]; default: 1;
- *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
- *  device, such as flash, external RAM and so on.
- */
-#define SPI1_MEM_CS1_DIS    (BIT(1))
-#define SPI1_MEM_CS1_DIS_M  (SPI1_MEM_CS1_DIS_V << SPI1_MEM_CS1_DIS_S)
-#define SPI1_MEM_CS1_DIS_V  0x00000001U
-#define SPI1_MEM_CS1_DIS_S  1
-/** SPI1_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
- *  1: spi clk line is high when idle     0: spi clk line is low when idle
- */
-#define SPI1_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI1_MEM_CK_IDLE_EDGE_M  (SPI1_MEM_CK_IDLE_EDGE_V << SPI1_MEM_CK_IDLE_EDGE_S)
-#define SPI1_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI1_MEM_CK_IDLE_EDGE_S  9
-/** SPI1_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
- *  spi cs line keep low when the bit is set.
- */
-#define SPI1_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI1_MEM_CS_KEEP_ACTIVE_M  (SPI1_MEM_CS_KEEP_ACTIVE_V << SPI1_MEM_CS_KEEP_ACTIVE_S)
-#define SPI1_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI1_MEM_CS_KEEP_ACTIVE_S  10
-
-/** SPI1_MEM_W0_REG register
- *  SPI1 memory data buffer0
- */
-#define SPI1_MEM_W0_REG (DR_REG_SPIMEM1_BASE + 0x58)
-/** SPI1_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF0    0xFFFFFFFFU
-#define SPI1_MEM_BUF0_M  (SPI1_MEM_BUF0_V << SPI1_MEM_BUF0_S)
-#define SPI1_MEM_BUF0_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF0_S  0
-
-/** SPI1_MEM_W1_REG register
- *  SPI1 memory data buffer1
- */
-#define SPI1_MEM_W1_REG (DR_REG_SPIMEM1_BASE + 0x5c)
-/** SPI1_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF1    0xFFFFFFFFU
-#define SPI1_MEM_BUF1_M  (SPI1_MEM_BUF1_V << SPI1_MEM_BUF1_S)
-#define SPI1_MEM_BUF1_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF1_S  0
-
-/** SPI1_MEM_W2_REG register
- *  SPI1 memory data buffer2
- */
-#define SPI1_MEM_W2_REG (DR_REG_SPIMEM1_BASE + 0x60)
-/** SPI1_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF2    0xFFFFFFFFU
-#define SPI1_MEM_BUF2_M  (SPI1_MEM_BUF2_V << SPI1_MEM_BUF2_S)
-#define SPI1_MEM_BUF2_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF2_S  0
-
-/** SPI1_MEM_W3_REG register
- *  SPI1 memory data buffer3
- */
-#define SPI1_MEM_W3_REG (DR_REG_SPIMEM1_BASE + 0x64)
-/** SPI1_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF3    0xFFFFFFFFU
-#define SPI1_MEM_BUF3_M  (SPI1_MEM_BUF3_V << SPI1_MEM_BUF3_S)
-#define SPI1_MEM_BUF3_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF3_S  0
-
-/** SPI1_MEM_W4_REG register
- *  SPI1 memory data buffer4
- */
-#define SPI1_MEM_W4_REG (DR_REG_SPIMEM1_BASE + 0x68)
-/** SPI1_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF4    0xFFFFFFFFU
-#define SPI1_MEM_BUF4_M  (SPI1_MEM_BUF4_V << SPI1_MEM_BUF4_S)
-#define SPI1_MEM_BUF4_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF4_S  0
-
-/** SPI1_MEM_W5_REG register
- *  SPI1 memory data buffer5
- */
-#define SPI1_MEM_W5_REG (DR_REG_SPIMEM1_BASE + 0x6c)
-/** SPI1_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF5    0xFFFFFFFFU
-#define SPI1_MEM_BUF5_M  (SPI1_MEM_BUF5_V << SPI1_MEM_BUF5_S)
-#define SPI1_MEM_BUF5_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF5_S  0
-
-/** SPI1_MEM_W6_REG register
- *  SPI1 memory data buffer6
- */
-#define SPI1_MEM_W6_REG (DR_REG_SPIMEM1_BASE + 0x70)
-/** SPI1_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF6    0xFFFFFFFFU
-#define SPI1_MEM_BUF6_M  (SPI1_MEM_BUF6_V << SPI1_MEM_BUF6_S)
-#define SPI1_MEM_BUF6_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF6_S  0
-
-/** SPI1_MEM_W7_REG register
- *  SPI1 memory data buffer7
- */
-#define SPI1_MEM_W7_REG (DR_REG_SPIMEM1_BASE + 0x74)
-/** SPI1_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF7    0xFFFFFFFFU
-#define SPI1_MEM_BUF7_M  (SPI1_MEM_BUF7_V << SPI1_MEM_BUF7_S)
-#define SPI1_MEM_BUF7_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF7_S  0
-
-/** SPI1_MEM_W8_REG register
- *  SPI1 memory data buffer8
- */
-#define SPI1_MEM_W8_REG (DR_REG_SPIMEM1_BASE + 0x78)
-/** SPI1_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF8    0xFFFFFFFFU
-#define SPI1_MEM_BUF8_M  (SPI1_MEM_BUF8_V << SPI1_MEM_BUF8_S)
-#define SPI1_MEM_BUF8_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF8_S  0
-
-/** SPI1_MEM_W9_REG register
- *  SPI1 memory data buffer9
- */
-#define SPI1_MEM_W9_REG (DR_REG_SPIMEM1_BASE + 0x7c)
-/** SPI1_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF9    0xFFFFFFFFU
-#define SPI1_MEM_BUF9_M  (SPI1_MEM_BUF9_V << SPI1_MEM_BUF9_S)
-#define SPI1_MEM_BUF9_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF9_S  0
-
-/** SPI1_MEM_W10_REG register
- *  SPI1 memory data buffer10
- */
-#define SPI1_MEM_W10_REG (DR_REG_SPIMEM1_BASE + 0x80)
-/** SPI1_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF10    0xFFFFFFFFU
-#define SPI1_MEM_BUF10_M  (SPI1_MEM_BUF10_V << SPI1_MEM_BUF10_S)
-#define SPI1_MEM_BUF10_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF10_S  0
-
-/** SPI1_MEM_W11_REG register
- *  SPI1 memory data buffer11
- */
-#define SPI1_MEM_W11_REG (DR_REG_SPIMEM1_BASE + 0x84)
-/** SPI1_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF11    0xFFFFFFFFU
-#define SPI1_MEM_BUF11_M  (SPI1_MEM_BUF11_V << SPI1_MEM_BUF11_S)
-#define SPI1_MEM_BUF11_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF11_S  0
-
-/** SPI1_MEM_W12_REG register
- *  SPI1 memory data buffer12
- */
-#define SPI1_MEM_W12_REG (DR_REG_SPIMEM1_BASE + 0x88)
-/** SPI1_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF12    0xFFFFFFFFU
-#define SPI1_MEM_BUF12_M  (SPI1_MEM_BUF12_V << SPI1_MEM_BUF12_S)
-#define SPI1_MEM_BUF12_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF12_S  0
-
-/** SPI1_MEM_W13_REG register
- *  SPI1 memory data buffer13
- */
-#define SPI1_MEM_W13_REG (DR_REG_SPIMEM1_BASE + 0x8c)
-/** SPI1_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF13    0xFFFFFFFFU
-#define SPI1_MEM_BUF13_M  (SPI1_MEM_BUF13_V << SPI1_MEM_BUF13_S)
-#define SPI1_MEM_BUF13_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF13_S  0
-
-/** SPI1_MEM_W14_REG register
- *  SPI1 memory data buffer14
- */
-#define SPI1_MEM_W14_REG (DR_REG_SPIMEM1_BASE + 0x90)
-/** SPI1_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF14    0xFFFFFFFFU
-#define SPI1_MEM_BUF14_M  (SPI1_MEM_BUF14_V << SPI1_MEM_BUF14_S)
-#define SPI1_MEM_BUF14_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF14_S  0
-
-/** SPI1_MEM_W15_REG register
- *  SPI1 memory data buffer15
- */
-#define SPI1_MEM_W15_REG (DR_REG_SPIMEM1_BASE + 0x94)
-/** SPI1_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI1_MEM_BUF15    0xFFFFFFFFU
-#define SPI1_MEM_BUF15_M  (SPI1_MEM_BUF15_V << SPI1_MEM_BUF15_S)
-#define SPI1_MEM_BUF15_V  0xFFFFFFFFU
-#define SPI1_MEM_BUF15_S  0
-
-/** SPI1_MEM_FLASH_WAITI_CTRL_REG register
- *  SPI1 wait idle control register
- */
-#define SPI1_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x98)
-/** SPI1_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
- *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
- *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
- *  Suspend/Resume are not supported.
- */
-#define SPI1_MEM_WAITI_EN    (BIT(0))
-#define SPI1_MEM_WAITI_EN_M  (SPI1_MEM_WAITI_EN_V << SPI1_MEM_WAITI_EN_S)
-#define SPI1_MEM_WAITI_EN_V  0x00000001U
-#define SPI1_MEM_WAITI_EN_S  0
-/** SPI1_MEM_WAITI_DUMMY : R/W; bitpos: [1]; default: 0;
- *  The dummy phase enable when wait flash idle (RDSR)
- */
-#define SPI1_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI1_MEM_WAITI_DUMMY_M  (SPI1_MEM_WAITI_DUMMY_V << SPI1_MEM_WAITI_DUMMY_S)
-#define SPI1_MEM_WAITI_DUMMY_V  0x00000001U
-#define SPI1_MEM_WAITI_DUMMY_S  1
-/** SPI1_MEM_WAITI_ADDR_EN : R/W; bitpos: [2]; default: 0;
- *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
- *  address in RDSR or read SUS command transfer.
- */
-#define SPI1_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI1_MEM_WAITI_ADDR_EN_M  (SPI1_MEM_WAITI_ADDR_EN_V << SPI1_MEM_WAITI_ADDR_EN_S)
-#define SPI1_MEM_WAITI_ADDR_EN_V  0x00000001U
-#define SPI1_MEM_WAITI_ADDR_EN_S  2
-/** SPI1_MEM_WAITI_ADDR_CYCLELEN : R/W; bitpos: [4:3]; default: 0;
- *  When SPI1_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
- *  (SPI1_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active
- *  when SPI1_MEM_WAITI_ADDR_EN is cleared.
- */
-#define SPI1_MEM_WAITI_ADDR_CYCLELEN    0x00000003U
-#define SPI1_MEM_WAITI_ADDR_CYCLELEN_M  (SPI1_MEM_WAITI_ADDR_CYCLELEN_V << SPI1_MEM_WAITI_ADDR_CYCLELEN_S)
-#define SPI1_MEM_WAITI_ADDR_CYCLELEN_V  0x00000003U
-#define SPI1_MEM_WAITI_ADDR_CYCLELEN_S  3
-/** SPI1_MEM_WAITI_CMD_2B : R/W; bitpos: [9]; default: 0;
- *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
- */
-#define SPI1_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI1_MEM_WAITI_CMD_2B_M  (SPI1_MEM_WAITI_CMD_2B_V << SPI1_MEM_WAITI_CMD_2B_S)
-#define SPI1_MEM_WAITI_CMD_2B_V  0x00000001U
-#define SPI1_MEM_WAITI_CMD_2B_S  9
-/** SPI1_MEM_WAITI_DUMMY_CYCLELEN : R/W; bitpos: [15:10]; default: 0;
- *  The dummy cycle length when wait flash idle(RDSR).
- */
-#define SPI1_MEM_WAITI_DUMMY_CYCLELEN    0x0000003FU
-#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_M  (SPI1_MEM_WAITI_DUMMY_CYCLELEN_V << SPI1_MEM_WAITI_DUMMY_CYCLELEN_S)
-#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI1_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/** SPI1_MEM_WAITI_CMD : R/W; bitpos: [31:16]; default: 5;
- *  The command value to wait flash idle(RDSR).
- */
-#define SPI1_MEM_WAITI_CMD    0x0000FFFFU
-#define SPI1_MEM_WAITI_CMD_M  (SPI1_MEM_WAITI_CMD_V << SPI1_MEM_WAITI_CMD_S)
-#define SPI1_MEM_WAITI_CMD_V  0x0000FFFFU
-#define SPI1_MEM_WAITI_CMD_S  16
-
-/** SPI1_MEM_FLASH_SUS_CTRL_REG register
- *  SPI1 flash suspend control register
- */
-#define SPI1_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x9c)
-/** SPI1_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
- *  program erase resume bit, program erase suspend operation will be triggered when
- *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
- *  disable.
- */
-#define SPI1_MEM_FLASH_PER    (BIT(0))
-#define SPI1_MEM_FLASH_PER_M  (SPI1_MEM_FLASH_PER_V << SPI1_MEM_FLASH_PER_S)
-#define SPI1_MEM_FLASH_PER_V  0x00000001U
-#define SPI1_MEM_FLASH_PER_S  0
-/** SPI1_MEM_FLASH_PES : R/W/SC; bitpos: [1]; default: 0;
- *  program erase suspend bit, program erase suspend operation will be triggered when
- *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
- *  disable.
- */
-#define SPI1_MEM_FLASH_PES    (BIT(1))
-#define SPI1_MEM_FLASH_PES_M  (SPI1_MEM_FLASH_PES_V << SPI1_MEM_FLASH_PES_S)
-#define SPI1_MEM_FLASH_PES_V  0x00000001U
-#define SPI1_MEM_FLASH_PES_S  1
-/** SPI1_MEM_FLASH_PER_WAIT_EN : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
- *  program erase resume command is sent. 0: SPI1 does not wait after program erase
- *  resume command is sent.
- */
-#define SPI1_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI1_MEM_FLASH_PER_WAIT_EN_M  (SPI1_MEM_FLASH_PER_WAIT_EN_V << SPI1_MEM_FLASH_PER_WAIT_EN_S)
-#define SPI1_MEM_FLASH_PER_WAIT_EN_V  0x00000001U
-#define SPI1_MEM_FLASH_PER_WAIT_EN_S  2
-/** SPI1_MEM_FLASH_PES_WAIT_EN : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
- *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
- *  suspend command is sent.
- */
-#define SPI1_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI1_MEM_FLASH_PES_WAIT_EN_M  (SPI1_MEM_FLASH_PES_WAIT_EN_V << SPI1_MEM_FLASH_PES_WAIT_EN_S)
-#define SPI1_MEM_FLASH_PES_WAIT_EN_V  0x00000001U
-#define SPI1_MEM_FLASH_PES_WAIT_EN_S  3
-/** SPI1_MEM_PES_PER_EN : R/W; bitpos: [4]; default: 0;
- *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
- *  application should send PER after PES is done.
- */
-#define SPI1_MEM_PES_PER_EN    (BIT(4))
-#define SPI1_MEM_PES_PER_EN_M  (SPI1_MEM_PES_PER_EN_V << SPI1_MEM_PES_PER_EN_S)
-#define SPI1_MEM_PES_PER_EN_V  0x00000001U
-#define SPI1_MEM_PES_PER_EN_S  4
-/** SPI1_MEM_FLASH_PES_EN : R/W; bitpos: [5]; default: 0;
- *  Set this bit to enable Auto-suspending function.
- */
-#define SPI1_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI1_MEM_FLASH_PES_EN_M  (SPI1_MEM_FLASH_PES_EN_V << SPI1_MEM_FLASH_PES_EN_S)
-#define SPI1_MEM_FLASH_PES_EN_V  0x00000001U
-#define SPI1_MEM_FLASH_PES_EN_S  5
-/** SPI1_MEM_PESR_END_MSK : R/W; bitpos: [21:6]; default: 128;
- *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
- *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
- *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
- *  status_in[15:0]^ SPI1_MEM_PESR_END_MSK[15:0].
- */
-#define SPI1_MEM_PESR_END_MSK    0x0000FFFFU
-#define SPI1_MEM_PESR_END_MSK_M  (SPI1_MEM_PESR_END_MSK_V << SPI1_MEM_PESR_END_MSK_S)
-#define SPI1_MEM_PESR_END_MSK_V  0x0000FFFFU
-#define SPI1_MEM_PESR_END_MSK_S  6
-/** SPI1_MEM_F_RD_SUS_2B : R/W; bitpos: [22]; default: 0;
- *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
- *  check flash SUS/SUS1/SUS2 status bit
- */
-#define SPI1_MEM_F_RD_SUS_2B    (BIT(22))
-#define SPI1_MEM_F_RD_SUS_2B_M  (SPI1_MEM_F_RD_SUS_2B_V << SPI1_MEM_F_RD_SUS_2B_S)
-#define SPI1_MEM_F_RD_SUS_2B_V  0x00000001U
-#define SPI1_MEM_F_RD_SUS_2B_S  22
-/** SPI1_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0;
- *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
- *  flash. 0: Only need to check WIP is 0.
- */
-#define SPI1_MEM_PER_END_EN    (BIT(23))
-#define SPI1_MEM_PER_END_EN_M  (SPI1_MEM_PER_END_EN_V << SPI1_MEM_PER_END_EN_S)
-#define SPI1_MEM_PER_END_EN_V  0x00000001U
-#define SPI1_MEM_PER_END_EN_S  23
-/** SPI1_MEM_PES_END_EN : R/W; bitpos: [24]; default: 0;
- *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
- *  of flash. 0: Only need to check WIP is 0.
- */
-#define SPI1_MEM_PES_END_EN    (BIT(24))
-#define SPI1_MEM_PES_END_EN_M  (SPI1_MEM_PES_END_EN_V << SPI1_MEM_PES_END_EN_S)
-#define SPI1_MEM_PES_END_EN_V  0x00000001U
-#define SPI1_MEM_PES_END_EN_S  24
-/** SPI1_MEM_SUS_TIMEOUT_CNT : R/W; bitpos: [31:25]; default: 4;
- *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_SUS_TIMEOUT_CNT[6:0] times,
- *  it will be treated as check pass.
- */
-#define SPI1_MEM_SUS_TIMEOUT_CNT    0x0000007FU
-#define SPI1_MEM_SUS_TIMEOUT_CNT_M  (SPI1_MEM_SUS_TIMEOUT_CNT_V << SPI1_MEM_SUS_TIMEOUT_CNT_S)
-#define SPI1_MEM_SUS_TIMEOUT_CNT_V  0x0000007FU
-#define SPI1_MEM_SUS_TIMEOUT_CNT_S  25
-
-/** SPI1_MEM_FLASH_SUS_CMD_REG register
- *  SPI1 flash suspend command register
- */
-#define SPI1_MEM_FLASH_SUS_CMD_REG (DR_REG_SPIMEM1_BASE + 0xa0)
-/** SPI1_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
- *  Program/Erase suspend command.
- */
-#define SPI1_MEM_FLASH_PES_COMMAND    0x0000FFFFU
-#define SPI1_MEM_FLASH_PES_COMMAND_M  (SPI1_MEM_FLASH_PES_COMMAND_V << SPI1_MEM_FLASH_PES_COMMAND_S)
-#define SPI1_MEM_FLASH_PES_COMMAND_V  0x0000FFFFU
-#define SPI1_MEM_FLASH_PES_COMMAND_S  0
-/** SPI1_MEM_WAIT_PESR_COMMAND : R/W; bitpos: [31:16]; default: 5;
- *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
- *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
- */
-#define SPI1_MEM_WAIT_PESR_COMMAND    0x0000FFFFU
-#define SPI1_MEM_WAIT_PESR_COMMAND_M  (SPI1_MEM_WAIT_PESR_COMMAND_V << SPI1_MEM_WAIT_PESR_COMMAND_S)
-#define SPI1_MEM_WAIT_PESR_COMMAND_V  0x0000FFFFU
-#define SPI1_MEM_WAIT_PESR_COMMAND_S  16
-
-/** SPI1_MEM_SUS_STATUS_REG register
- *  SPI1 flash suspend status register
- */
-#define SPI1_MEM_SUS_STATUS_REG (DR_REG_SPIMEM1_BASE + 0xa4)
-/** SPI1_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
- *  The status of flash suspend, only used in SPI1.
- */
-#define SPI1_MEM_FLASH_SUS    (BIT(0))
-#define SPI1_MEM_FLASH_SUS_M  (SPI1_MEM_FLASH_SUS_V << SPI1_MEM_FLASH_SUS_S)
-#define SPI1_MEM_FLASH_SUS_V  0x00000001U
-#define SPI1_MEM_FLASH_SUS_S  0
-/** SPI1_MEM_WAIT_PESR_CMD_2B : R/W; bitpos: [1]; default: 0;
- *  1: SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- *  SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
- */
-#define SPI1_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI1_MEM_WAIT_PESR_CMD_2B_M  (SPI1_MEM_WAIT_PESR_CMD_2B_V << SPI1_MEM_WAIT_PESR_CMD_2B_S)
-#define SPI1_MEM_WAIT_PESR_CMD_2B_V  0x00000001U
-#define SPI1_MEM_WAIT_PESR_CMD_2B_S  1
-/** SPI1_MEM_FLASH_HPM_DLY_128 : R/W; bitpos: [2]; default: 0;
- *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
- *  command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- *  after HPM command is sent.
- */
-#define SPI1_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI1_MEM_FLASH_HPM_DLY_128_M  (SPI1_MEM_FLASH_HPM_DLY_128_V << SPI1_MEM_FLASH_HPM_DLY_128_S)
-#define SPI1_MEM_FLASH_HPM_DLY_128_V  0x00000001U
-#define SPI1_MEM_FLASH_HPM_DLY_128_S  2
-/** SPI1_MEM_FLASH_RES_DLY_128 : R/W; bitpos: [3]; default: 0;
- *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
- *  command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- *  after RES command is sent.
- */
-#define SPI1_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI1_MEM_FLASH_RES_DLY_128_M  (SPI1_MEM_FLASH_RES_DLY_128_V << SPI1_MEM_FLASH_RES_DLY_128_S)
-#define SPI1_MEM_FLASH_RES_DLY_128_V  0x00000001U
-#define SPI1_MEM_FLASH_RES_DLY_128_S  3
-/** SPI1_MEM_FLASH_DP_DLY_128 : R/W; bitpos: [4]; default: 0;
- *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
- *  command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- *  after DP command is sent.
- */
-#define SPI1_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI1_MEM_FLASH_DP_DLY_128_M  (SPI1_MEM_FLASH_DP_DLY_128_V << SPI1_MEM_FLASH_DP_DLY_128_S)
-#define SPI1_MEM_FLASH_DP_DLY_128_V  0x00000001U
-#define SPI1_MEM_FLASH_DP_DLY_128_S  4
-/** SPI1_MEM_FLASH_PER_DLY_128 : R/W; bitpos: [5]; default: 0;
- *  Valid when SPI1_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
- *  0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
- *  command is sent.
- */
-#define SPI1_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI1_MEM_FLASH_PER_DLY_128_M  (SPI1_MEM_FLASH_PER_DLY_128_V << SPI1_MEM_FLASH_PER_DLY_128_S)
-#define SPI1_MEM_FLASH_PER_DLY_128_V  0x00000001U
-#define SPI1_MEM_FLASH_PER_DLY_128_S  5
-/** SPI1_MEM_FLASH_PES_DLY_128 : R/W; bitpos: [6]; default: 0;
- *  Valid when SPI1_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
- *  (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
- *  0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
- *  command is sent.
- */
-#define SPI1_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI1_MEM_FLASH_PES_DLY_128_M  (SPI1_MEM_FLASH_PES_DLY_128_V << SPI1_MEM_FLASH_PES_DLY_128_S)
-#define SPI1_MEM_FLASH_PES_DLY_128_V  0x00000001U
-#define SPI1_MEM_FLASH_PES_DLY_128_S  6
-/** SPI1_MEM_SPI0_LOCK_EN : R/W; bitpos: [7]; default: 0;
- *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
- */
-#define SPI1_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI1_MEM_SPI0_LOCK_EN_M  (SPI1_MEM_SPI0_LOCK_EN_V << SPI1_MEM_SPI0_LOCK_EN_S)
-#define SPI1_MEM_SPI0_LOCK_EN_V  0x00000001U
-#define SPI1_MEM_SPI0_LOCK_EN_S  7
-/** SPI1_MEM_FLASH_PESR_CMD_2B : R/W; bitpos: [15]; default: 0;
- *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
- *  of Program/Erase Suspend/Resume command is 8.
- */
-#define SPI1_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI1_MEM_FLASH_PESR_CMD_2B_M  (SPI1_MEM_FLASH_PESR_CMD_2B_V << SPI1_MEM_FLASH_PESR_CMD_2B_S)
-#define SPI1_MEM_FLASH_PESR_CMD_2B_V  0x00000001U
-#define SPI1_MEM_FLASH_PESR_CMD_2B_S  15
-/** SPI1_MEM_FLASH_PER_COMMAND : R/W; bitpos: [31:16]; default: 31354;
- *  Program/Erase resume command.
- */
-#define SPI1_MEM_FLASH_PER_COMMAND    0x0000FFFFU
-#define SPI1_MEM_FLASH_PER_COMMAND_M  (SPI1_MEM_FLASH_PER_COMMAND_V << SPI1_MEM_FLASH_PER_COMMAND_S)
-#define SPI1_MEM_FLASH_PER_COMMAND_V  0x0000FFFFU
-#define SPI1_MEM_FLASH_PER_COMMAND_S  16
-
-/** SPI1_MEM_INT_ENA_REG register
- *  SPI1 interrupt enable register
- */
-#define SPI1_MEM_INT_ENA_REG (DR_REG_SPIMEM1_BASE + 0xc0)
-/** SPI1_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI1_MEM_PER_END_INT interrupt.
- */
-#define SPI1_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI1_MEM_PER_END_INT_ENA_M  (SPI1_MEM_PER_END_INT_ENA_V << SPI1_MEM_PER_END_INT_ENA_S)
-#define SPI1_MEM_PER_END_INT_ENA_V  0x00000001U
-#define SPI1_MEM_PER_END_INT_ENA_S  0
-/** SPI1_MEM_PES_END_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI1_MEM_PES_END_INT interrupt.
- */
-#define SPI1_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI1_MEM_PES_END_INT_ENA_M  (SPI1_MEM_PES_END_INT_ENA_V << SPI1_MEM_PES_END_INT_ENA_S)
-#define SPI1_MEM_PES_END_INT_ENA_V  0x00000001U
-#define SPI1_MEM_PES_END_INT_ENA_S  1
-/** SPI1_MEM_WPE_END_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI1_MEM_WPE_END_INT interrupt.
- */
-#define SPI1_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI1_MEM_WPE_END_INT_ENA_M  (SPI1_MEM_WPE_END_INT_ENA_V << SPI1_MEM_WPE_END_INT_ENA_S)
-#define SPI1_MEM_WPE_END_INT_ENA_V  0x00000001U
-#define SPI1_MEM_WPE_END_INT_ENA_S  2
-/** SPI1_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI1_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI1_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI1_MEM_SLV_ST_END_INT_ENA_M  (SPI1_MEM_SLV_ST_END_INT_ENA_V << SPI1_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI1_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI1_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI1_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI1_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI1_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI1_MEM_MST_ST_END_INT_ENA_M  (SPI1_MEM_MST_ST_END_INT_ENA_V << SPI1_MEM_MST_ST_END_INT_ENA_S)
-#define SPI1_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI1_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI1_MEM_BROWN_OUT_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI1_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI1_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI1_MEM_BROWN_OUT_INT_ENA_M  (SPI1_MEM_BROWN_OUT_INT_ENA_V << SPI1_MEM_BROWN_OUT_INT_ENA_S)
-#define SPI1_MEM_BROWN_OUT_INT_ENA_V  0x00000001U
-#define SPI1_MEM_BROWN_OUT_INT_ENA_S  10
-
-/** SPI1_MEM_INT_CLR_REG register
- *  SPI1 interrupt clear register
- */
-#define SPI1_MEM_INT_CLR_REG (DR_REG_SPIMEM1_BASE + 0xc4)
-/** SPI1_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI1_MEM_PER_END_INT interrupt.
- */
-#define SPI1_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI1_MEM_PER_END_INT_CLR_M  (SPI1_MEM_PER_END_INT_CLR_V << SPI1_MEM_PER_END_INT_CLR_S)
-#define SPI1_MEM_PER_END_INT_CLR_V  0x00000001U
-#define SPI1_MEM_PER_END_INT_CLR_S  0
-/** SPI1_MEM_PES_END_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI1_MEM_PES_END_INT interrupt.
- */
-#define SPI1_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI1_MEM_PES_END_INT_CLR_M  (SPI1_MEM_PES_END_INT_CLR_V << SPI1_MEM_PES_END_INT_CLR_S)
-#define SPI1_MEM_PES_END_INT_CLR_V  0x00000001U
-#define SPI1_MEM_PES_END_INT_CLR_S  1
-/** SPI1_MEM_WPE_END_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI1_MEM_WPE_END_INT interrupt.
- */
-#define SPI1_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI1_MEM_WPE_END_INT_CLR_M  (SPI1_MEM_WPE_END_INT_CLR_V << SPI1_MEM_WPE_END_INT_CLR_S)
-#define SPI1_MEM_WPE_END_INT_CLR_V  0x00000001U
-#define SPI1_MEM_WPE_END_INT_CLR_S  2
-/** SPI1_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI1_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI1_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI1_MEM_SLV_ST_END_INT_CLR_M  (SPI1_MEM_SLV_ST_END_INT_CLR_V << SPI1_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI1_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI1_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI1_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI1_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI1_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI1_MEM_MST_ST_END_INT_CLR_M  (SPI1_MEM_MST_ST_END_INT_CLR_V << SPI1_MEM_MST_ST_END_INT_CLR_S)
-#define SPI1_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI1_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI1_MEM_BROWN_OUT_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The status bit for SPI1_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI1_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI1_MEM_BROWN_OUT_INT_CLR_M  (SPI1_MEM_BROWN_OUT_INT_CLR_V << SPI1_MEM_BROWN_OUT_INT_CLR_S)
-#define SPI1_MEM_BROWN_OUT_INT_CLR_V  0x00000001U
-#define SPI1_MEM_BROWN_OUT_INT_CLR_S  10
-
-/** SPI1_MEM_INT_RAW_REG register
- *  SPI1 interrupt raw register
- */
-#define SPI1_MEM_INT_RAW_REG (DR_REG_SPIMEM1_BASE + 0xc8)
-/** SPI1_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit for SPI1_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
- *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
- */
-#define SPI1_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI1_MEM_PER_END_INT_RAW_M  (SPI1_MEM_PER_END_INT_RAW_V << SPI1_MEM_PER_END_INT_RAW_S)
-#define SPI1_MEM_PER_END_INT_RAW_V  0x00000001U
-#define SPI1_MEM_PER_END_INT_RAW_S  0
-/** SPI1_MEM_PES_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit for SPI1_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
- *  command (0x75) is sent and flash is suspended successfully. 0: Others.
- */
-#define SPI1_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI1_MEM_PES_END_INT_RAW_M  (SPI1_MEM_PES_END_INT_RAW_V << SPI1_MEM_PES_END_INT_RAW_S)
-#define SPI1_MEM_PES_END_INT_RAW_V  0x00000001U
-#define SPI1_MEM_PES_END_INT_RAW_S  1
-/** SPI1_MEM_WPE_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI1_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
- *  is sent and flash is already idle. 0: Others.
- */
-#define SPI1_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI1_MEM_WPE_END_INT_RAW_M  (SPI1_MEM_WPE_END_INT_RAW_V << SPI1_MEM_WPE_END_INT_RAW_S)
-#define SPI1_MEM_WPE_END_INT_RAW_V  0x00000001U
-#define SPI1_MEM_WPE_END_INT_RAW_S  2
-/** SPI1_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI1_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
- *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
- *  Others
- */
-#define SPI1_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI1_MEM_SLV_ST_END_INT_RAW_M  (SPI1_MEM_SLV_ST_END_INT_RAW_V << SPI1_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI1_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI1_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI1_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI1_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
- *  changed from non idle state to idle state. 0: Others.
- */
-#define SPI1_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI1_MEM_MST_ST_END_INT_RAW_M  (SPI1_MEM_MST_ST_END_INT_RAW_V << SPI1_MEM_MST_ST_END_INT_RAW_S)
-#define SPI1_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI1_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI1_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI1_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
- *  chip is loosing power and RTC module sends out brown out close flash request to
- *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
- *  and MSPI returns to idle state. 0: Others.
- */
-#define SPI1_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI1_MEM_BROWN_OUT_INT_RAW_M  (SPI1_MEM_BROWN_OUT_INT_RAW_V << SPI1_MEM_BROWN_OUT_INT_RAW_S)
-#define SPI1_MEM_BROWN_OUT_INT_RAW_V  0x00000001U
-#define SPI1_MEM_BROWN_OUT_INT_RAW_S  10
-
-/** SPI1_MEM_INT_ST_REG register
- *  SPI1 interrupt status register
- */
-#define SPI1_MEM_INT_ST_REG (DR_REG_SPIMEM1_BASE + 0xcc)
-/** SPI1_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI1_MEM_PER_END_INT interrupt.
- */
-#define SPI1_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI1_MEM_PER_END_INT_ST_M  (SPI1_MEM_PER_END_INT_ST_V << SPI1_MEM_PER_END_INT_ST_S)
-#define SPI1_MEM_PER_END_INT_ST_V  0x00000001U
-#define SPI1_MEM_PER_END_INT_ST_S  0
-/** SPI1_MEM_PES_END_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI1_MEM_PES_END_INT interrupt.
- */
-#define SPI1_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI1_MEM_PES_END_INT_ST_M  (SPI1_MEM_PES_END_INT_ST_V << SPI1_MEM_PES_END_INT_ST_S)
-#define SPI1_MEM_PES_END_INT_ST_V  0x00000001U
-#define SPI1_MEM_PES_END_INT_ST_S  1
-/** SPI1_MEM_WPE_END_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI1_MEM_WPE_END_INT interrupt.
- */
-#define SPI1_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI1_MEM_WPE_END_INT_ST_M  (SPI1_MEM_WPE_END_INT_ST_V << SPI1_MEM_WPE_END_INT_ST_S)
-#define SPI1_MEM_WPE_END_INT_ST_V  0x00000001U
-#define SPI1_MEM_WPE_END_INT_ST_S  2
-/** SPI1_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI1_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI1_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI1_MEM_SLV_ST_END_INT_ST_M  (SPI1_MEM_SLV_ST_END_INT_ST_V << SPI1_MEM_SLV_ST_END_INT_ST_S)
-#define SPI1_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI1_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI1_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI1_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI1_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI1_MEM_MST_ST_END_INT_ST_M  (SPI1_MEM_MST_ST_END_INT_ST_V << SPI1_MEM_MST_ST_END_INT_ST_S)
-#define SPI1_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI1_MEM_MST_ST_END_INT_ST_S  4
-/** SPI1_MEM_BROWN_OUT_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI1_MEM_BROWN_OUT_INT interrupt.
- */
-#define SPI1_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI1_MEM_BROWN_OUT_INT_ST_M  (SPI1_MEM_BROWN_OUT_INT_ST_V << SPI1_MEM_BROWN_OUT_INT_ST_S)
-#define SPI1_MEM_BROWN_OUT_INT_ST_V  0x00000001U
-#define SPI1_MEM_BROWN_OUT_INT_ST_S  10
-
-/** SPI1_MEM_DDR_REG register
- *  SPI1 DDR control register
- */
-#define SPI1_MEM_DDR_REG (DR_REG_SPIMEM1_BASE + 0xd4)
-/** SPI1_MEM_F_DDR_EN : HRO; bitpos: [0]; default: 0;
- *  1: in ddr mode,  0 in sdr mode
- */
-#define SPI1_MEM_F_DDR_EN    (BIT(0))
-#define SPI1_MEM_F_DDR_EN_M  (SPI1_MEM_F_DDR_EN_V << SPI1_MEM_F_DDR_EN_S)
-#define SPI1_MEM_F_DDR_EN_V  0x00000001U
-#define SPI1_MEM_F_DDR_EN_S  0
-/** SPI1_MEM_F_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
- *  Set the bit to enable variable dummy cycle in spi ddr mode.
- */
-#define SPI1_MEM_F_VAR_DUMMY    (BIT(1))
-#define SPI1_MEM_F_VAR_DUMMY_M  (SPI1_MEM_F_VAR_DUMMY_V << SPI1_MEM_F_VAR_DUMMY_S)
-#define SPI1_MEM_F_VAR_DUMMY_V  0x00000001U
-#define SPI1_MEM_F_VAR_DUMMY_S  1
-/** SPI1_MEM_F_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
- *  Set the bit to reorder rx data of the word in spi ddr mode.
- */
-#define SPI1_MEM_F_DDR_RDAT_SWP    (BIT(2))
-#define SPI1_MEM_F_DDR_RDAT_SWP_M  (SPI1_MEM_F_DDR_RDAT_SWP_V << SPI1_MEM_F_DDR_RDAT_SWP_S)
-#define SPI1_MEM_F_DDR_RDAT_SWP_V  0x00000001U
-#define SPI1_MEM_F_DDR_RDAT_SWP_S  2
-/** SPI1_MEM_F_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
- *  Set the bit to reorder tx data of the word in spi ddr mode.
- */
-#define SPI1_MEM_F_DDR_WDAT_SWP    (BIT(3))
-#define SPI1_MEM_F_DDR_WDAT_SWP_M  (SPI1_MEM_F_DDR_WDAT_SWP_V << SPI1_MEM_F_DDR_WDAT_SWP_S)
-#define SPI1_MEM_F_DDR_WDAT_SWP_V  0x00000001U
-#define SPI1_MEM_F_DDR_WDAT_SWP_S  3
-/** SPI1_MEM_F_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
- *  the bit is used to disable dual edge in command phase when ddr mode.
- */
-#define SPI1_MEM_F_DDR_CMD_DIS    (BIT(4))
-#define SPI1_MEM_F_DDR_CMD_DIS_M  (SPI1_MEM_F_DDR_CMD_DIS_V << SPI1_MEM_F_DDR_CMD_DIS_S)
-#define SPI1_MEM_F_DDR_CMD_DIS_V  0x00000001U
-#define SPI1_MEM_F_DDR_CMD_DIS_S  4
-/** SPI1_MEM_F_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
- *  It is the minimum output data length in the panda device.
- */
-#define SPI1_MEM_F_OUTMINBYTELEN    0x0000007FU
-#define SPI1_MEM_F_OUTMINBYTELEN_M  (SPI1_MEM_F_OUTMINBYTELEN_V << SPI1_MEM_F_OUTMINBYTELEN_S)
-#define SPI1_MEM_F_OUTMINBYTELEN_V  0x0000007FU
-#define SPI1_MEM_F_OUTMINBYTELEN_S  5
-/** SPI1_MEM_F_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
- *  The delay number of data strobe which from memory based on SPI clock.
- */
-#define SPI1_MEM_F_USR_DDR_DQS_THD    0x0000007FU
-#define SPI1_MEM_F_USR_DDR_DQS_THD_M  (SPI1_MEM_F_USR_DDR_DQS_THD_V << SPI1_MEM_F_USR_DDR_DQS_THD_S)
-#define SPI1_MEM_F_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI1_MEM_F_USR_DDR_DQS_THD_S  14
-/** SPI1_MEM_F_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
- *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI1_MEM_DIN state. It is used when there is no SPI_DQS signal or
- *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
- *  negative edge of SPI_DQS.
- */
-#define SPI1_MEM_F_DDR_DQS_LOOP    (BIT(21))
-#define SPI1_MEM_F_DDR_DQS_LOOP_M  (SPI1_MEM_F_DDR_DQS_LOOP_V << SPI1_MEM_F_DDR_DQS_LOOP_S)
-#define SPI1_MEM_F_DDR_DQS_LOOP_V  0x00000001U
-#define SPI1_MEM_F_DDR_DQS_LOOP_S  21
-/** SPI1_MEM_F_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
- *  Set this bit to enable the differential SPI_CLK#.
- */
-#define SPI1_MEM_F_CLK_DIFF_EN    (BIT(24))
-#define SPI1_MEM_F_CLK_DIFF_EN_M  (SPI1_MEM_F_CLK_DIFF_EN_V << SPI1_MEM_F_CLK_DIFF_EN_S)
-#define SPI1_MEM_F_CLK_DIFF_EN_V  0x00000001U
-#define SPI1_MEM_F_CLK_DIFF_EN_S  24
-/** SPI1_MEM_F_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
- *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
- */
-#define SPI1_MEM_F_DQS_CA_IN    (BIT(26))
-#define SPI1_MEM_F_DQS_CA_IN_M  (SPI1_MEM_F_DQS_CA_IN_V << SPI1_MEM_F_DQS_CA_IN_S)
-#define SPI1_MEM_F_DQS_CA_IN_V  0x00000001U
-#define SPI1_MEM_F_DQS_CA_IN_S  26
-/** SPI1_MEM_F_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
- *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
- *  accesses flash or SPI1 accesses flash or sram.
- */
-#define SPI1_MEM_F_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_M  (SPI1_MEM_F_HYPERBUS_DUMMY_2X_V << SPI1_MEM_F_HYPERBUS_DUMMY_2X_S)
-#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI1_MEM_F_HYPERBUS_DUMMY_2X_S  27
-/** SPI1_MEM_F_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
- *  Set this bit to invert SPI_DIFF when accesses to flash. .
- */
-#define SPI1_MEM_F_CLK_DIFF_INV    (BIT(28))
-#define SPI1_MEM_F_CLK_DIFF_INV_M  (SPI1_MEM_F_CLK_DIFF_INV_V << SPI1_MEM_F_CLK_DIFF_INV_S)
-#define SPI1_MEM_F_CLK_DIFF_INV_V  0x00000001U
-#define SPI1_MEM_F_CLK_DIFF_INV_S  28
-/** SPI1_MEM_F_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
- *  Set this bit to enable octa_ram address out when accesses to flash, which means
- *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
- */
-#define SPI1_MEM_F_OCTA_RAM_ADDR    (BIT(29))
-#define SPI1_MEM_F_OCTA_RAM_ADDR_M  (SPI1_MEM_F_OCTA_RAM_ADDR_V << SPI1_MEM_F_OCTA_RAM_ADDR_S)
-#define SPI1_MEM_F_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI1_MEM_F_OCTA_RAM_ADDR_S  29
-/** SPI1_MEM_F_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
- *  Set this bit to enable HyperRAM address out when accesses to flash, which means
- *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
- */
-#define SPI1_MEM_F_HYPERBUS_CA    (BIT(30))
-#define SPI1_MEM_F_HYPERBUS_CA_M  (SPI1_MEM_F_HYPERBUS_CA_V << SPI1_MEM_F_HYPERBUS_CA_S)
-#define SPI1_MEM_F_HYPERBUS_CA_V  0x00000001U
-#define SPI1_MEM_F_HYPERBUS_CA_S  30
-
-/** SPI1_MEM_TIMING_CALI_REG register
- *  SPI1 timing control register
- */
-#define SPI1_MEM_TIMING_CALI_REG (DR_REG_SPIMEM1_BASE + 0x180)
-/** SPI1_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable timing auto-calibration for all reading operations.
- */
-#define SPI1_MEM_TIMING_CALI    (BIT(1))
-#define SPI1_MEM_TIMING_CALI_M  (SPI1_MEM_TIMING_CALI_V << SPI1_MEM_TIMING_CALI_S)
-#define SPI1_MEM_TIMING_CALI_V  0x00000001U
-#define SPI1_MEM_TIMING_CALI_S  1
-/** SPI1_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
- *  add extra dummy spi clock cycle length for spi clock calibration.
- */
-#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI1_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI1_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI1_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-
-/** SPI1_MEM_CLOCK_GATE_REG register
- *  SPI1 clk_gate register
- */
-#define SPI1_MEM_CLOCK_GATE_REG (DR_REG_SPIMEM1_BASE + 0x200)
-/** SPI1_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Register clock gate enable signal. 1: Enable. 0: Disable.
- */
-#define SPI1_MEM_CLK_EN    (BIT(0))
-#define SPI1_MEM_CLK_EN_M  (SPI1_MEM_CLK_EN_V << SPI1_MEM_CLK_EN_S)
-#define SPI1_MEM_CLK_EN_V  0x00000001U
-#define SPI1_MEM_CLK_EN_S  0
-
-/** SPI1_MEM_DATE_REG register
- *  Version control register
- */
-#define SPI1_MEM_DATE_REG (DR_REG_SPIMEM1_BASE + 0x3fc)
-/** SPI1_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128;
- *  Version control register
- */
-#define SPI1_MEM_DATE    0x0FFFFFFFU
-#define SPI1_MEM_DATE_M  (SPI1_MEM_DATE_V << SPI1_MEM_DATE_S)
-#define SPI1_MEM_DATE_V  0x0FFFFFFFU
-#define SPI1_MEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/spi1_mem_struct.h b/components/soc/esp32c5/beta3/include/soc/spi1_mem_struct.h
deleted file mode 100644
index b54bbc7de4..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/spi1_mem_struct.h
+++ /dev/null
@@ -1,1081 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: User-defined control registers */
-/** Type of cmd register
- *  SPI1 memory command register
- */
-typedef union {
-    struct {
-        /** mst_st : RO; bitpos: [3:0]; default: 0;
-         *  The current status of SPI1 master FSM.
-         */
-        uint32_t mst_st:4;
-        /** slv_st : RO; bitpos: [7:4]; default: 0;
-         *  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state,
-         *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
-         *  6:write data state, 7: done state, 8: read data end state.
-         */
-        uint32_t slv_st:4;
-        uint32_t reserved_8:10;
-        /** usr : R/W/SC; bitpos: [18]; default: 0;
-         *  User define command enable.  An operation will be triggered when the bit is set.
-         *  The bit will be cleared once the operation done.1: enable 0: disable.
-         */
-        uint32_t usr:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} spi1_mem_cmd_reg_t;
-
-/** Type of addr register
- *  SPI1 address register
- */
-typedef union {
-    struct {
-        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
-         *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
-         *  address, the bit24-bit31 are the byte length of a transfer.
-         */
-        uint32_t usr_addr_value:32;
-    };
-    uint32_t val;
-} spi1_mem_addr_reg_t;
-
-/** Type of user register
- *  SPI1 user register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
-         */
-        uint32_t ck_out_edge:1;
-        uint32_t reserved_10:2;
-        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
-         *  In the write operations read-data phase apply 2 signals
-         */
-        uint32_t fwrite_dual:1;
-        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
-         *  In the write operations read-data phase apply 4 signals
-         */
-        uint32_t fwrite_quad:1;
-        /** fwrite_dio : R/W; bitpos: [14]; default: 0;
-         *  In the write operations address phase and read-data phase apply 2 signals.
-         */
-        uint32_t fwrite_dio:1;
-        /** fwrite_qio : R/W; bitpos: [15]; default: 0;
-         *  In the write operations address phase and read-data phase apply 4 signals.
-         */
-        uint32_t fwrite_qio:1;
-        uint32_t reserved_16:10;
-        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
-         *  SPI clock is disable in dummy phase when the bit is enable.
-         */
-        uint32_t usr_dummy_idle:1;
-        /** usr_mosi : R/W; bitpos: [27]; default: 0;
-         *  This bit enable the write-data phase of an operation.
-         */
-        uint32_t usr_mosi:1;
-        /** usr_miso : R/W; bitpos: [28]; default: 0;
-         *  This bit enable the read-data phase of an operation.
-         */
-        uint32_t usr_miso:1;
-        /** usr_dummy : R/W; bitpos: [29]; default: 0;
-         *  This bit enable the dummy phase of an operation.
-         */
-        uint32_t usr_dummy:1;
-        /** usr_addr : R/W; bitpos: [30]; default: 0;
-         *  This bit enable the address phase of an operation.
-         */
-        uint32_t usr_addr:1;
-        /** usr_command : R/W; bitpos: [31]; default: 1;
-         *  This bit enable the command phase of an operation.
-         */
-        uint32_t usr_command:1;
-    };
-    uint32_t val;
-} spi1_mem_user_reg_t;
-
-/** Type of user1 register
- *  SPI1 user1 register.
- */
-typedef union {
-    struct {
-        /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7;
-         *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
-         *  (cycle_num-1).
-         */
-        uint32_t usr_dummy_cyclelen:6;
-        uint32_t reserved_6:20;
-        /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23;
-         *  The length in bits of address phase. The register value shall be (bit_num-1).
-         */
-        uint32_t usr_addr_bitlen:6;
-    };
-    uint32_t val;
-} spi1_mem_user1_reg_t;
-
-/** Type of user2 register
- *  SPI1 user2 register.
- */
-typedef union {
-    struct {
-        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
-         *  The value of  command.
-         */
-        uint32_t usr_command_value:16;
-        uint32_t reserved_16:12;
-        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
-         *  The length in bits of command phase. The register value shall be (bit_num-1)
-         */
-        uint32_t usr_command_bitlen:4;
-    };
-    uint32_t val;
-} spi1_mem_user2_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of ctrl register
- *  SPI1 control register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** fdummy_rin : R/W; bitpos: [2]; default: 1;
-         *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
-         *  level of SPI bus is output by the MSPI controller.
-         */
-        uint32_t fdummy_rin:1;
-        /** fdummy_wout : R/W; bitpos: [3]; default: 1;
-         *  In the dummy phase of a MSPI write data transfer when accesses to flash, the signal
-         *  level of SPI bus is output by the MSPI controller.
-         */
-        uint32_t fdummy_wout:1;
-        /** fdout_oct : HRO; bitpos: [4]; default: 0;
-         *  Apply 8 signals during write-data phase 1:enable 0: disable
-         */
-        uint32_t fdout_oct:1;
-        /** fdin_oct : HRO; bitpos: [5]; default: 0;
-         *  Apply 8 signals during read-data phase 1:enable 0: disable
-         */
-        uint32_t fdin_oct:1;
-        /** faddr_oct : HRO; bitpos: [6]; default: 0;
-         *  Apply 8 signals during address phase 1:enable 0: disable
-         */
-        uint32_t faddr_oct:1;
-        uint32_t reserved_7:1;
-        /** fcmd_quad : R/W; bitpos: [8]; default: 0;
-         *  Apply 4 signals during command phase 1:enable 0: disable
-         */
-        uint32_t fcmd_quad:1;
-        /** fcmd_oct : HRO; bitpos: [9]; default: 0;
-         *  Apply 8 signals during command phase 1:enable 0: disable
-         */
-        uint32_t fcmd_oct:1;
-        uint32_t reserved_10:3;
-        /** fastrd_mode : R/W; bitpos: [13]; default: 1;
-         *  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout
-         *  and spi_mem_fread_dout. 1: enable 0: disable.
-         */
-        uint32_t fastrd_mode:1;
-        /** fread_dual : R/W; bitpos: [14]; default: 0;
-         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-         */
-        uint32_t fread_dual:1;
-        uint32_t reserved_15:3;
-        /** q_pol : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to set MISO line polarity, 1: high 0, low
-         */
-        uint32_t q_pol:1;
-        /** d_pol : R/W; bitpos: [19]; default: 1;
-         *  The bit is used to set MOSI line polarity, 1: high 0, low
-         */
-        uint32_t d_pol:1;
-        /** fread_quad : R/W; bitpos: [20]; default: 0;
-         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-         */
-        uint32_t fread_quad:1;
-        /** wp_reg : R/W; bitpos: [21]; default: 1;
-         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
-         */
-        uint32_t wp_reg:1;
-        uint32_t reserved_22:1;
-        /** fread_dio : R/W; bitpos: [23]; default: 0;
-         *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
-         *  0: disable.
-         */
-        uint32_t fread_dio:1;
-        /** fread_qio : R/W; bitpos: [24]; default: 0;
-         *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
-         *  0: disable.
-         */
-        uint32_t fread_qio:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} spi1_mem_ctrl_reg_t;
-
-/** Type of ctrl1 register
- *  SPI1 control1 register.
- */
-typedef union {
-    struct {
-        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
-         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
-         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on.
-         */
-        uint32_t clk_mode:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} spi1_mem_ctrl1_reg_t;
-
-/** Type of ctrl2 register
- *  SPI1 control2 register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** sync_reset : WT; bitpos: [31]; default: 0;
-         *  The FSM will be reset.
-         */
-        uint32_t sync_reset:1;
-    };
-    uint32_t val;
-} spi1_mem_ctrl2_reg_t;
-
-/** Type of clock register
- *  SPI1 clock division control register.
- */
-typedef union {
-    struct {
-        /** clkcnt_l : R/W; bitpos: [7:0]; default: 3;
-         *  In the master mode it must be equal to spi_mem_clkcnt_N.
-         */
-        uint32_t clkcnt_l:8;
-        /** clkcnt_h : R/W; bitpos: [15:8]; default: 1;
-         *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-         */
-        uint32_t clkcnt_h:8;
-        /** clkcnt_n : R/W; bitpos: [23:16]; default: 3;
-         *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-         *  system/(spi_mem_clkcnt_N+1)
-         */
-        uint32_t clkcnt_n:8;
-        uint32_t reserved_24:7;
-        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0;
-         *  reserved
-         */
-        uint32_t clk_equ_sysclk:1;
-    };
-    uint32_t val;
-} spi1_mem_clock_reg_t;
-
-/** Type of mosi_dlen register
- *  SPI1 send data bit length control register.
- */
-typedef union {
-    struct {
-        /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0;
-         *  The length in bits of write-data. The register value shall be (bit_num-1).
-         */
-        uint32_t usr_mosi_dbitlen:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} spi1_mem_mosi_dlen_reg_t;
-
-/** Type of miso_dlen register
- *  SPI1 receive data bit length control register.
- */
-typedef union {
-    struct {
-        /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0;
-         *  The length in bits of  read-data. The register value shall be (bit_num-1).
-         */
-        uint32_t usr_miso_dbitlen:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} spi1_mem_miso_dlen_reg_t;
-
-/** Type of rd_status register
- *  SPI1 status register.
- */
-typedef union {
-    struct {
-        /** status : R/W/SS; bitpos: [15:0]; default: 0;
-         *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
-         */
-        uint32_t status:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} spi1_mem_rd_status_reg_t;
-
-/** Type of misc register
- *  SPI1 misc register
- */
-typedef union {
-    struct {
-        /** cs0_dis : R/W; bitpos: [0]; default: 0;
-         *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
-         *  device, such as flash, external RAM and so on.
-         */
-        uint32_t cs0_dis:1;
-        /** cs1_dis : R/W; bitpos: [1]; default: 1;
-         *  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
-         *  device, such as flash, external RAM and so on.
-         */
-        uint32_t cs1_dis:1;
-        uint32_t reserved_2:7;
-        /** ck_idle_edge : R/W; bitpos: [9]; default: 0;
-         *  1: spi clk line is high when idle     0: spi clk line is low when idle
-         */
-        uint32_t ck_idle_edge:1;
-        /** cs_keep_active : R/W; bitpos: [10]; default: 0;
-         *  spi cs line keep low when the bit is set.
-         */
-        uint32_t cs_keep_active:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} spi1_mem_misc_reg_t;
-
-/** Type of flash_waiti_ctrl register
- *  SPI1 wait idle control register
- */
-typedef union {
-    struct {
-        /** waiti_en : R/W; bitpos: [0]; default: 1;
-         *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
-         *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
-         *  Suspend/Resume are not supported.
-         */
-        uint32_t waiti_en:1;
-        /** waiti_dummy : R/W; bitpos: [1]; default: 0;
-         *  The dummy phase enable when wait flash idle (RDSR)
-         */
-        uint32_t waiti_dummy:1;
-        /** waiti_addr_en : R/W; bitpos: [2]; default: 0;
-         *  1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out
-         *  address in RDSR or read SUS command transfer.
-         */
-        uint32_t waiti_addr_en:1;
-        /** waiti_addr_cyclelen : R/W; bitpos: [4:3]; default: 0;
-         *  When SPI1_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is
-         *  (SPI1_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active
-         *  when SPI1_MEM_WAITI_ADDR_EN is cleared.
-         */
-        uint32_t waiti_addr_cyclelen:2;
-        uint32_t reserved_5:4;
-        /** waiti_cmd_2b : R/W; bitpos: [9]; default: 0;
-         *  1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
-         */
-        uint32_t waiti_cmd_2b:1;
-        /** waiti_dummy_cyclelen : R/W; bitpos: [15:10]; default: 0;
-         *  The dummy cycle length when wait flash idle(RDSR).
-         */
-        uint32_t waiti_dummy_cyclelen:6;
-        /** waiti_cmd : R/W; bitpos: [31:16]; default: 5;
-         *  The command value to wait flash idle(RDSR).
-         */
-        uint32_t waiti_cmd:16;
-    };
-    uint32_t val;
-} spi1_mem_flash_waiti_ctrl_reg_t;
-
-/** Type of flash_sus_ctrl register
- *  SPI1 flash suspend control register
- */
-typedef union {
-    struct {
-        /** flash_per : R/W/SC; bitpos: [0]; default: 0;
-         *  program erase resume bit, program erase suspend operation will be triggered when
-         *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
-         *  disable.
-         */
-        uint32_t flash_per:1;
-        /** flash_pes : R/W/SC; bitpos: [1]; default: 0;
-         *  program erase suspend bit, program erase suspend operation will be triggered when
-         *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
-         *  disable.
-         */
-        uint32_t flash_pes:1;
-        /** flash_per_wait_en : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-         *  program erase resume command is sent. 0: SPI1 does not wait after program erase
-         *  resume command is sent.
-         */
-        uint32_t flash_per_wait_en:1;
-        /** flash_pes_wait_en : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-         *  program erase suspend command is sent. 0: SPI1 does not wait after program erase
-         *  suspend command is sent.
-         */
-        uint32_t flash_pes_wait_en:1;
-        /** pes_per_en : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
-         *  application should send PER after PES is done.
-         */
-        uint32_t pes_per_en:1;
-        /** flash_pes_en : R/W; bitpos: [5]; default: 0;
-         *  Set this bit to enable Auto-suspending function.
-         */
-        uint32_t flash_pes_en:1;
-        /** pesr_end_msk : R/W; bitpos: [21:6]; default: 128;
-         *  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
-         *  status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
-         *  out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 =
-         *  status_in[15:0]^ SPI1_MEM_PESR_END_MSK[15:0].
-         */
-        uint32_t pesr_end_msk:16;
-        /** f_rd_sus_2b : R/W; bitpos: [22]; default: 0;
-         *  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when
-         *  check flash SUS/SUS1/SUS2 status bit
-         */
-        uint32_t f_rd_sus_2b:1;
-        /** per_end_en : R/W; bitpos: [23]; default: 0;
-         *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of
-         *  flash. 0: Only need to check WIP is 0.
-         */
-        uint32_t per_end_en:1;
-        /** pes_end_en : R/W; bitpos: [24]; default: 0;
-         *  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status
-         *  of flash. 0: Only need to check WIP is 0.
-         */
-        uint32_t pes_end_en:1;
-        /** sus_timeout_cnt : R/W; bitpos: [31:25]; default: 4;
-         *  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI1_MEM_SUS_TIMEOUT_CNT[6:0] times,
-         *  it will be treated as check pass.
-         */
-        uint32_t sus_timeout_cnt:7;
-    };
-    uint32_t val;
-} spi1_mem_flash_sus_ctrl_reg_t;
-
-/** Type of flash_sus_cmd register
- *  SPI1 flash suspend command register
- */
-typedef union {
-    struct {
-        /** flash_pes_command : R/W; bitpos: [15:0]; default: 30069;
-         *  Program/Erase suspend command.
-         */
-        uint32_t flash_pes_command:16;
-        /** wait_pesr_command : R/W; bitpos: [31:16]; default: 5;
-         *  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
-         *  SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
-         */
-        uint32_t wait_pesr_command:16;
-    };
-    uint32_t val;
-} spi1_mem_flash_sus_cmd_reg_t;
-
-/** Type of sus_status register
- *  SPI1 flash suspend status register
- */
-typedef union {
-    struct {
-        /** flash_sus : R/W/SS/SC; bitpos: [0]; default: 0;
-         *  The status of flash suspend, only used in SPI1.
-         */
-        uint32_t flash_sus:1;
-        /** wait_pesr_cmd_2b : R/W; bitpos: [1]; default: 0;
-         *  1: SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
-         *  SPI1 sends out SPI1_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
-         */
-        uint32_t wait_pesr_cmd_2b:1;
-        /** flash_hpm_dly_128 : R/W; bitpos: [2]; default: 0;
-         *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
-         *  command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-         *  after HPM command is sent.
-         */
-        uint32_t flash_hpm_dly_128:1;
-        /** flash_res_dly_128 : R/W; bitpos: [3]; default: 0;
-         *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
-         *  command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-         *  after RES command is sent.
-         */
-        uint32_t flash_res_dly_128:1;
-        /** flash_dp_dly_128 : R/W; bitpos: [4]; default: 0;
-         *  1: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
-         *  command is sent. 0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-         *  after DP command is sent.
-         */
-        uint32_t flash_dp_dly_128:1;
-        /** flash_per_dly_128 : R/W; bitpos: [5]; default: 0;
-         *  Valid when SPI1_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
-         *  0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
-         *  command is sent.
-         */
-        uint32_t flash_per_dly_128:1;
-        /** flash_pes_dly_128 : R/W; bitpos: [6]; default: 0;
-         *  Valid when SPI1_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
-         *  (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
-         *  0: SPI1 waits (SPI1_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
-         *  command is sent.
-         */
-        uint32_t flash_pes_dly_128:1;
-        /** spi0_lock_en : R/W; bitpos: [7]; default: 0;
-         *  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
-         */
-        uint32_t spi0_lock_en:1;
-        uint32_t reserved_8:7;
-        /** flash_pesr_cmd_2b : R/W; bitpos: [15]; default: 0;
-         *  1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length
-         *  of Program/Erase Suspend/Resume command is 8.
-         */
-        uint32_t flash_pesr_cmd_2b:1;
-        /** flash_per_command : R/W; bitpos: [31:16]; default: 31354;
-         *  Program/Erase resume command.
-         */
-        uint32_t flash_per_command:16;
-    };
-    uint32_t val;
-} spi1_mem_sus_status_reg_t;
-
-/** Type of ddr register
- *  SPI1 DDR control register
- */
-typedef union {
-    struct {
-        /** f_ddr_en : HRO; bitpos: [0]; default: 0;
-         *  1: in ddr mode,  0 in sdr mode
-         */
-        uint32_t f_ddr_en:1;
-        /** f_var_dummy : HRO; bitpos: [1]; default: 0;
-         *  Set the bit to enable variable dummy cycle in spi ddr mode.
-         */
-        uint32_t f_var_dummy:1;
-        /** f_ddr_rdat_swp : HRO; bitpos: [2]; default: 0;
-         *  Set the bit to reorder rx data of the word in spi ddr mode.
-         */
-        uint32_t f_ddr_rdat_swp:1;
-        /** f_ddr_wdat_swp : HRO; bitpos: [3]; default: 0;
-         *  Set the bit to reorder tx data of the word in spi ddr mode.
-         */
-        uint32_t f_ddr_wdat_swp:1;
-        /** f_ddr_cmd_dis : HRO; bitpos: [4]; default: 0;
-         *  the bit is used to disable dual edge in command phase when ddr mode.
-         */
-        uint32_t f_ddr_cmd_dis:1;
-        /** f_outminbytelen : HRO; bitpos: [11:5]; default: 1;
-         *  It is the minimum output data length in the panda device.
-         */
-        uint32_t f_outminbytelen:7;
-        uint32_t reserved_12:2;
-        /** f_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0;
-         *  The delay number of data strobe which from memory based on SPI clock.
-         */
-        uint32_t f_usr_ddr_dqs_thd:7;
-        /** f_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
-         *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
-         *  spi0_slv_st is in SPI1_MEM_DIN state. It is used when there is no SPI_DQS signal or
-         *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
-         *  negative edge of SPI_DQS.
-         */
-        uint32_t f_ddr_dqs_loop:1;
-        uint32_t reserved_22:2;
-        /** f_clk_diff_en : HRO; bitpos: [24]; default: 0;
-         *  Set this bit to enable the differential SPI_CLK#.
-         */
-        uint32_t f_clk_diff_en:1;
-        uint32_t reserved_25:1;
-        /** f_dqs_ca_in : HRO; bitpos: [26]; default: 0;
-         *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
-         */
-        uint32_t f_dqs_ca_in:1;
-        /** f_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0;
-         *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
-         *  accesses flash or SPI1 accesses flash or sram.
-         */
-        uint32_t f_hyperbus_dummy_2x:1;
-        /** f_clk_diff_inv : HRO; bitpos: [28]; default: 0;
-         *  Set this bit to invert SPI_DIFF when accesses to flash. .
-         */
-        uint32_t f_clk_diff_inv:1;
-        /** f_octa_ram_addr : HRO; bitpos: [29]; default: 0;
-         *  Set this bit to enable octa_ram address out when accesses to flash, which means
-         *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
-         */
-        uint32_t f_octa_ram_addr:1;
-        /** f_hyperbus_ca : HRO; bitpos: [30]; default: 0;
-         *  Set this bit to enable HyperRAM address out when accesses to flash, which means
-         *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
-         */
-        uint32_t f_hyperbus_ca:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} spi1_mem_ddr_reg_t;
-
-/** Type of clock_gate register
- *  SPI1 clk_gate register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Register clock gate enable signal. 1: Enable. 0: Disable.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} spi1_mem_clock_gate_reg_t;
-
-
-/** Group: Memory data buffer register */
-/** Type of wn register
- *  SPI1 memory data buffer n
- */
-typedef union {
-    struct {
-        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf:32;
-    };
-    uint32_t val;
-} spi1_mem_wn_reg_t;
-
-/** Type of w1 register
- *  SPI1 memory data buffer1
- */
-typedef union {
-    struct {
-        /** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf1:32;
-    };
-    uint32_t val;
-} spi1_mem_w1_reg_t;
-
-/** Type of w2 register
- *  SPI1 memory data buffer2
- */
-typedef union {
-    struct {
-        /** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf2:32;
-    };
-    uint32_t val;
-} spi1_mem_w2_reg_t;
-
-/** Type of w3 register
- *  SPI1 memory data buffer3
- */
-typedef union {
-    struct {
-        /** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf3:32;
-    };
-    uint32_t val;
-} spi1_mem_w3_reg_t;
-
-/** Type of w4 register
- *  SPI1 memory data buffer4
- */
-typedef union {
-    struct {
-        /** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf4:32;
-    };
-    uint32_t val;
-} spi1_mem_w4_reg_t;
-
-/** Type of w5 register
- *  SPI1 memory data buffer5
- */
-typedef union {
-    struct {
-        /** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf5:32;
-    };
-    uint32_t val;
-} spi1_mem_w5_reg_t;
-
-/** Type of w6 register
- *  SPI1 memory data buffer6
- */
-typedef union {
-    struct {
-        /** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf6:32;
-    };
-    uint32_t val;
-} spi1_mem_w6_reg_t;
-
-/** Type of w7 register
- *  SPI1 memory data buffer7
- */
-typedef union {
-    struct {
-        /** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf7:32;
-    };
-    uint32_t val;
-} spi1_mem_w7_reg_t;
-
-/** Type of w8 register
- *  SPI1 memory data buffer8
- */
-typedef union {
-    struct {
-        /** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf8:32;
-    };
-    uint32_t val;
-} spi1_mem_w8_reg_t;
-
-/** Type of w9 register
- *  SPI1 memory data buffer9
- */
-typedef union {
-    struct {
-        /** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf9:32;
-    };
-    uint32_t val;
-} spi1_mem_w9_reg_t;
-
-/** Type of w10 register
- *  SPI1 memory data buffer10
- */
-typedef union {
-    struct {
-        /** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf10:32;
-    };
-    uint32_t val;
-} spi1_mem_w10_reg_t;
-
-/** Type of w11 register
- *  SPI1 memory data buffer11
- */
-typedef union {
-    struct {
-        /** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf11:32;
-    };
-    uint32_t val;
-} spi1_mem_w11_reg_t;
-
-/** Type of w12 register
- *  SPI1 memory data buffer12
- */
-typedef union {
-    struct {
-        /** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf12:32;
-    };
-    uint32_t val;
-} spi1_mem_w12_reg_t;
-
-/** Type of w13 register
- *  SPI1 memory data buffer13
- */
-typedef union {
-    struct {
-        /** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf13:32;
-    };
-    uint32_t val;
-} spi1_mem_w13_reg_t;
-
-/** Type of w14 register
- *  SPI1 memory data buffer14
- */
-typedef union {
-    struct {
-        /** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf14:32;
-    };
-    uint32_t val;
-} spi1_mem_w14_reg_t;
-
-/** Type of w15 register
- *  SPI1 memory data buffer15
- */
-typedef union {
-    struct {
-        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf15:32;
-    };
-    uint32_t val;
-} spi1_mem_w15_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_ena register
- *  SPI1 interrupt enable register
- */
-typedef union {
-    struct {
-        /** per_end_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI1_MEM_PER_END_INT interrupt.
-         */
-        uint32_t per_end_int_ena:1;
-        /** pes_end_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI1_MEM_PES_END_INT interrupt.
-         */
-        uint32_t pes_end_int_ena:1;
-        /** wpe_end_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI1_MEM_WPE_END_INT interrupt.
-         */
-        uint32_t wpe_end_int_ena:1;
-        /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI1_MEM_SLV_ST_END_INT interrupt.
-         */
-        uint32_t slv_st_end_int_ena:1;
-        /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI1_MEM_MST_ST_END_INT interrupt.
-         */
-        uint32_t mst_st_end_int_ena:1;
-        uint32_t reserved_5:5;
-        /** brown_out_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI1_MEM_BROWN_OUT_INT interrupt.
-         */
-        uint32_t brown_out_int_ena:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} spi1_mem_int_ena_reg_t;
-
-/** Type of int_clr register
- *  SPI1 interrupt clear register
- */
-typedef union {
-    struct {
-        /** per_end_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI1_MEM_PER_END_INT interrupt.
-         */
-        uint32_t per_end_int_clr:1;
-        /** pes_end_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI1_MEM_PES_END_INT interrupt.
-         */
-        uint32_t pes_end_int_clr:1;
-        /** wpe_end_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI1_MEM_WPE_END_INT interrupt.
-         */
-        uint32_t wpe_end_int_clr:1;
-        /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI1_MEM_SLV_ST_END_INT interrupt.
-         */
-        uint32_t slv_st_end_int_clr:1;
-        /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI1_MEM_MST_ST_END_INT interrupt.
-         */
-        uint32_t mst_st_end_int_clr:1;
-        uint32_t reserved_5:5;
-        /** brown_out_int_clr : WT; bitpos: [10]; default: 0;
-         *  The status bit for SPI1_MEM_BROWN_OUT_INT interrupt.
-         */
-        uint32_t brown_out_int_clr:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} spi1_mem_int_clr_reg_t;
-
-/** Type of int_raw register
- *  SPI1 interrupt raw register
- */
-typedef union {
-    struct {
-        /** per_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit for SPI1_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
-         *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
-         */
-        uint32_t per_end_int_raw:1;
-        /** pes_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit for SPI1_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
-         *  command (0x75) is sent and flash is suspended successfully. 0: Others.
-         */
-        uint32_t pes_end_int_raw:1;
-        /** wpe_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI1_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE
-         *  is sent and flash is already idle. 0: Others.
-         */
-        uint32_t wpe_end_int_raw:1;
-        /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI1_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is
-         *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
-         *  Others
-         */
-        uint32_t slv_st_end_int_raw:1;
-        /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI1_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is
-         *  changed from non idle state to idle state. 0: Others.
-         */
-        uint32_t mst_st_end_int_raw:1;
-        uint32_t reserved_5:5;
-        /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI1_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-         *  chip is loosing power and RTC module sends out brown out close flash request to
-         *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
-         *  and MSPI returns to idle state. 0: Others.
-         */
-        uint32_t brown_out_int_raw:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} spi1_mem_int_raw_reg_t;
-
-/** Type of int_st register
- *  SPI1 interrupt status register
- */
-typedef union {
-    struct {
-        /** per_end_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI1_MEM_PER_END_INT interrupt.
-         */
-        uint32_t per_end_int_st:1;
-        /** pes_end_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI1_MEM_PES_END_INT interrupt.
-         */
-        uint32_t pes_end_int_st:1;
-        /** wpe_end_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI1_MEM_WPE_END_INT interrupt.
-         */
-        uint32_t wpe_end_int_st:1;
-        /** slv_st_end_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI1_MEM_SLV_ST_END_INT interrupt.
-         */
-        uint32_t slv_st_end_int_st:1;
-        /** mst_st_end_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI1_MEM_MST_ST_END_INT interrupt.
-         */
-        uint32_t mst_st_end_int_st:1;
-        uint32_t reserved_5:5;
-        /** brown_out_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI1_MEM_BROWN_OUT_INT interrupt.
-         */
-        uint32_t brown_out_int_st:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} spi1_mem_int_st_reg_t;
-
-
-/** Group: Timing registers */
-/** Type of timing_cali register
- *  SPI1 timing control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** timing_cali : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to enable timing auto-calibration for all reading operations.
-         */
-        uint32_t timing_cali:1;
-        /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0;
-         *  add extra dummy spi clock cycle length for spi clock calibration.
-         */
-        uint32_t extra_dummy_cyclelen:3;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} spi1_mem_timing_cali_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35660128;
-         *  Version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} spi1_mem_date_reg_t;
-
-
-typedef struct spi1_mem_dev_t {
-    volatile spi1_mem_cmd_reg_t cmd;
-    volatile spi1_mem_addr_reg_t addr;
-    volatile spi1_mem_ctrl_reg_t ctrl;
-    volatile spi1_mem_ctrl1_reg_t ctrl1;
-    volatile spi1_mem_ctrl2_reg_t ctrl2;
-    volatile spi1_mem_clock_reg_t clock;
-    volatile spi1_mem_user_reg_t user;
-    volatile spi1_mem_user1_reg_t user1;
-    volatile spi1_mem_user2_reg_t user2;
-    volatile spi1_mem_mosi_dlen_reg_t mosi_dlen;
-    volatile spi1_mem_miso_dlen_reg_t miso_dlen;
-    volatile spi1_mem_rd_status_reg_t rd_status;
-    uint32_t reserved_030;
-    volatile spi1_mem_misc_reg_t misc;
-    uint32_t reserved_038[8];
-    volatile spi1_mem_wn_reg_t data_buf[16];
-    volatile spi1_mem_flash_waiti_ctrl_reg_t flash_waiti_ctrl;
-    volatile spi1_mem_flash_sus_ctrl_reg_t flash_sus_ctrl;
-    volatile spi1_mem_flash_sus_cmd_reg_t flash_sus_cmd;
-    volatile spi1_mem_sus_status_reg_t sus_status;
-    uint32_t reserved_0a8[6];
-    volatile spi1_mem_int_ena_reg_t int_ena;
-    volatile spi1_mem_int_clr_reg_t int_clr;
-    volatile spi1_mem_int_raw_reg_t int_raw;
-    volatile spi1_mem_int_st_reg_t int_st;
-    uint32_t reserved_0d0;
-    volatile spi1_mem_ddr_reg_t ddr;
-    uint32_t reserved_0d8[42];
-    volatile spi1_mem_timing_cali_reg_t timing_cali;
-    uint32_t reserved_184[31];
-    volatile spi1_mem_clock_gate_reg_t clock_gate;
-    uint32_t reserved_204[126];
-    volatile spi1_mem_date_reg_t date;
-} spi1_mem_dev_t;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi1_mem_dev_t) == 0x400, "Invalid size of spi1_mem_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/spi_mem_reg.h b/components/soc/esp32c5/beta3/include/soc/spi_mem_reg.h
deleted file mode 100644
index 5cc59b057c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/spi_mem_reg.h
+++ /dev/null
@@ -1,2737 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI_MEM_CMD_REG register
- *  SPI0 FSM status register
- */
-#define SPI_MEM_CMD_REG(i)  (REG_SPI_MEM_BASE(i) + 0x0)
-/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
- *  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
- *  2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
- *  data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
- */
-#define SPI_MEM_MST_ST    0x0000000FU
-#define SPI_MEM_MST_ST_M  (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S)
-#define SPI_MEM_MST_ST_V  0x0000000FU
-#define SPI_MEM_MST_ST_S  0
-/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0;
- *  The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
- *  2: send command state, 3: send address state, 4: wait state, 5: read data state,
- *  6:write data state, 7: done state, 8: read data end state.
- */
-#define SPI_MEM_SLV_ST    0x0000000FU
-#define SPI_MEM_SLV_ST_M  (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S)
-#define SPI_MEM_SLV_ST_V  0x0000000FU
-#define SPI_MEM_SLV_ST_S  4
-/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0;
- *  SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
- *  will be triggered when the bit is set. The bit will be cleared once the operation
- *  done.1: enable 0: disable.
- */
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (SPI_MEM_USR_V << SPI_MEM_USR_S)
-#define SPI_MEM_USR_V  0x00000001U
-#define SPI_MEM_USR_S  18
-
-/** SPI_MEM_CTRL_REG register
- *  SPI0 control register.
- */
-#define SPI_MEM_CTRL_REG(i)  (REG_SPI_MEM_BASE(i) + 0x8)
-/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0;
- *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
- *  of SPI_DQS is output by the MSPI controller.
- */
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S)
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0;
- *  In the dummy phase of an MSPI write data transfer when accesses to flash, the level
- *  of SPI_IO[7:0] is output by the MSPI controller.
- */
-#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S)
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
- *  In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is
- *  output by the MSPI controller in the first half part of dummy phase. It is used to
- *  mask invalid SPI_DQS in the half part of dummy phase.
- */
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S)
-#define SPI_MEM_FDUMMY_RIN_V  0x00000001U
-#define SPI_MEM_FDUMMY_RIN_S  2
-/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1;
- *  In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is
- *  output by the MSPI controller in the second half part of dummy phase. It is used to
- *  pre-drive flash.
- */
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S)
-#define SPI_MEM_FDUMMY_WOUT_V  0x00000001U
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0;
- *  Apply 8 signals during write-data phase 1:enable 0: disable
- */
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S)
-#define SPI_MEM_FDOUT_OCT_V  0x00000001U
-#define SPI_MEM_FDOUT_OCT_S  4
-/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0;
- *  Apply 8 signals during read-data phase 1:enable 0: disable
- */
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S)
-#define SPI_MEM_FDIN_OCT_V  0x00000001U
-#define SPI_MEM_FDIN_OCT_S  5
-/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0;
- *  Apply 8 signals during address phase 1:enable 0: disable
- */
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S)
-#define SPI_MEM_FADDR_OCT_V  0x00000001U
-#define SPI_MEM_FADDR_OCT_S  6
-/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0;
- *  Apply 4 signals during command phase 1:enable 0: disable
- */
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S)
-#define SPI_MEM_FCMD_QUAD_V  0x00000001U
-#define SPI_MEM_FCMD_QUAD_S  8
-/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0;
- *  Apply 8 signals during command phase 1:enable 0: disable
- */
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S)
-#define SPI_MEM_FCMD_OCT_V  0x00000001U
-#define SPI_MEM_FCMD_OCT_S  9
-/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1;
- *  This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT
- *  and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.
- */
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S)
-#define SPI_MEM_FASTRD_MODE_V  0x00000001U
-#define SPI_MEM_FASTRD_MODE_S  13
-/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
- */
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S)
-#define SPI_MEM_FREAD_DUAL_V  0x00000001U
-#define SPI_MEM_FREAD_DUAL_S  14
-/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1;
- *  The bit is used to set MISO line polarity, 1: high 0, low
- */
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S)
-#define SPI_MEM_Q_POL_V  0x00000001U
-#define SPI_MEM_Q_POL_S  18
-/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1;
- *  The bit is used to set MOSI line polarity, 1: high 0, low
- */
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S)
-#define SPI_MEM_D_POL_V  0x00000001U
-#define SPI_MEM_D_POL_S  19
-/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0;
- *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
- */
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S)
-#define SPI_MEM_FREAD_QUAD_V  0x00000001U
-#define SPI_MEM_FREAD_QUAD_S  20
-/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1;
- *  Write protect signal output when SPI is idle.  1: output high, 0: output low.
- */
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S)
-#define SPI_MEM_WP_REG_V  0x00000001U
-#define SPI_MEM_WP_REG_S  21
-/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0;
- *  In the read operations address phase and read-data phase apply 2 signals. 1: enable
- *  0: disable.
- */
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S)
-#define SPI_MEM_FREAD_DIO_V  0x00000001U
-#define SPI_MEM_FREAD_DIO_S  23
-/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0;
- *  In the read operations address phase and read-data phase apply 4 signals. 1: enable
- *  0: disable.
- */
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S)
-#define SPI_MEM_FREAD_QIO_V  0x00000001U
-#define SPI_MEM_FREAD_QIO_S  24
-/** SPI_MEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0;
- *  When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
- *  1. 0: Others.
- */
-#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S)
-#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1;
- *  When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are
- *  always 1. 0: Others.
- */
-#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S)
-#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
-
-/** SPI_MEM_CTRL1_REG register
- *  SPI0 control1 register.
- */
-#define SPI_MEM_CTRL1_REG(i)  (REG_SPI_MEM_BASE(i) + 0xc)
-/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
- *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
- */
-#define SPI_MEM_CLK_MODE    0x00000003U
-#define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
-#define SPI_MEM_CLK_MODE_V  0x00000003U
-#define SPI_MEM_CLK_MODE_S  0
-/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1;
- *  1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply
- *  the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.
- */
-#define SPI_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define SPI_AR_SIZE0_1_SUPPORT_EN_M  (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S)
-#define SPI_AR_SIZE0_1_SUPPORT_EN_V  0x00000001U
-#define SPI_AR_SIZE0_1_SUPPORT_EN_S  21
-/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1;
- *  1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.
- */
-#define SPI_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define SPI_AW_SIZE0_1_SUPPORT_EN_M  (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S)
-#define SPI_AW_SIZE0_1_SUPPORT_EN_V  0x00000001U
-#define SPI_AW_SIZE0_1_SUPPORT_EN_S  22
-/** SPI_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1;
- *  1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0:
- *  Reply AXI read data to AXI bus when all the read data is available.
- */
-#define SPI_AXI_RDATA_BACK_FAST    (BIT(23))
-#define SPI_AXI_RDATA_BACK_FAST_M  (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S)
-#define SPI_AXI_RDATA_BACK_FAST_V  0x00000001U
-#define SPI_AXI_RDATA_BACK_FAST_S  23
-/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0;
- *  1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
- *  when there is a ECC error in AXI read data. The ECC error information is recorded
- *  in SPI_MEM_ECC_ERR_ADDR_REG.
- */
-#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_M  (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S)
-#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x00000001U
-#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
-/** SPI_MEM_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0;
- *  Set this bit to enable AXI Read Splice-transfer.
- */
-#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_M  (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S)
-#define SPI_MEM_AR_SPLICE_EN_V  0x00000001U
-#define SPI_MEM_AR_SPLICE_EN_S  25
-/** SPI_MEM_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0;
- *  Set this bit to enable AXI Write Splice-transfer.
- */
-#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_M  (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S)
-#define SPI_MEM_AW_SPLICE_EN_V  0x00000001U
-#define SPI_MEM_AW_SPLICE_EN_S  26
-/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1;
- *  When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be
- *  accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1
- *  will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be
- *  accessed at the same time.
- */
-#define SPI_MEM_RAM0_EN    (BIT(27))
-#define SPI_MEM_RAM0_EN_M  (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S)
-#define SPI_MEM_RAM0_EN_V  0x00000001U
-#define SPI_MEM_RAM0_EN_S  27
-/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0;
- *  Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the
- *  same time.
- */
-#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_M  (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S)
-#define SPI_MEM_DUAL_RAM_EN_V  0x00000001U
-#define SPI_MEM_DUAL_RAM_EN_S  28
-/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1;
- *  Set this bit to write data faster, do not wait write data has been stored in
- *  tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
- *  in  tx_bus_fifo_l2.
- */
-#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_M  (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S)
-#define SPI_MEM_FAST_WRITE_EN_V  0x00000001U
-#define SPI_MEM_FAST_WRITE_EN_S  29
-/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0;
- *  The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
- *  receive signals from AXI.  Set this bit to reset these FIFO.
- */
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S)
-#define SPI_MEM_RXFIFO_RST_V  0x00000001U
-#define SPI_MEM_RXFIFO_RST_S  30
-/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0;
- *  The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
- *  send signals to AXI. Set this bit to reset these FIFO.
- */
-#define SPI_MEM_TXFIFO_RST    (BIT(31))
-#define SPI_MEM_TXFIFO_RST_M  (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S)
-#define SPI_MEM_TXFIFO_RST_V  0x00000001U
-#define SPI_MEM_TXFIFO_RST_S  31
-
-/** SPI_MEM_CTRL2_REG register
- *  SPI0 control2 register.
- */
-#define SPI_MEM_CTRL2_REG(i)  (REG_SPI_MEM_BASE(i) + 0x10)
-/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
- *  (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
- *  SPI_MEM_CS_SETUP bit.
- */
-#define SPI_MEM_CS_SETUP_TIME    0x0000001FU
-#define SPI_MEM_CS_SETUP_TIME_M  (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S)
-#define SPI_MEM_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_MEM_CS_SETUP_TIME_S  0
-/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1;
- *  SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with
- *  SPI_MEM_CS_HOLD bit.
- */
-#define SPI_MEM_CS_HOLD_TIME    0x0000001FU
-#define SPI_MEM_CS_HOLD_TIME_M  (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S)
-#define SPI_MEM_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/** SPI_MEM_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3;
- *  SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
- *  mode when accessed flash.
- */
-#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007U
-#define SPI_MEM_ECC_CS_HOLD_TIME_M  (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S)
-#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x00000007U
-#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
-/** SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1;
- *  1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when
- *  accesses flash.
- */
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S)
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/** SPI_MEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0;
- *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
- *  accesses flash.
- */
-#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S)
-#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x00000001U
-#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 1;
- *  Set this bit to enable SPI0 split one AXI read flash transfer into two SPI
- *  transfers when one transfer will cross flash or EXT_RAM page corner, valid no
- *  matter whether there is an ECC region or not.
- */
-#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_M  (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S)
-#define SPI_MEM_SPLIT_TRANS_EN_V  0x00000001U
-#define SPI_MEM_SPLIT_TRANS_EN_S  24
-/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0;
- *  These bits are used to set the minimum CS high time tSHSL between SPI burst
- *  transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
- *  core clock cycles.
- */
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003FU
-#define SPI_MEM_CS_HOLD_DELAY_M  (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S)
-#define SPI_MEM_CS_HOLD_DELAY_V  0x0000003FU
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
- *  The spi0_mst_st and spi0_slv_st will be reset.
- */
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S)
-#define SPI_MEM_SYNC_RESET_V  0x00000001U
-#define SPI_MEM_SYNC_RESET_S  31
-
-/** SPI_MEM_CLOCK_REG register
- *  SPI clock division control register.
- */
-#define SPI_MEM_CLOCK_REG(i)  (REG_SPI_MEM_BASE(i) + 0x14)
-/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
- *  In the master mode it must be equal to spi_mem_clkcnt_N.
- */
-#define SPI_MEM_CLKCNT_L    0x000000FFU
-#define SPI_MEM_CLKCNT_L_M  (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S)
-#define SPI_MEM_CLKCNT_L_V  0x000000FFU
-#define SPI_MEM_CLKCNT_L_S  0
-/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1;
- *  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
- */
-#define SPI_MEM_CLKCNT_H    0x000000FFU
-#define SPI_MEM_CLKCNT_H_M  (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S)
-#define SPI_MEM_CLKCNT_H_V  0x000000FFU
-#define SPI_MEM_CLKCNT_H_S  8
-/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3;
- *  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- *  system/(spi_mem_clkcnt_N+1)
- */
-#define SPI_MEM_CLKCNT_N    0x000000FFU
-#define SPI_MEM_CLKCNT_N_M  (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S)
-#define SPI_MEM_CLKCNT_N_V  0x000000FFU
-#define SPI_MEM_CLKCNT_N_S  16
-/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
- *  1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
- *  clock.
- */
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S)
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
-
-/** SPI_MEM_USER_REG register
- *  SPI0 user register.
- */
-#define SPI_MEM_USER_REG(i)  (REG_SPI_MEM_BASE(i) + 0x18)
-/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0;
- *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
- */
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S)
-#define SPI_MEM_CS_HOLD_V  0x00000001U
-#define SPI_MEM_CS_HOLD_S  6
-/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0;
- *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
- */
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S)
-#define SPI_MEM_CS_SETUP_V  0x00000001U
-#define SPI_MEM_CS_SETUP_S  7
-/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
- */
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S)
-#define SPI_MEM_CK_OUT_EDGE_V  0x00000001U
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- *  spi clock is disable in dummy phase when the bit is enable.
- */
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S)
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- *  This bit enable the dummy phase of an operation.
- */
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S)
-#define SPI_MEM_USR_DUMMY_V  0x00000001U
-#define SPI_MEM_USR_DUMMY_S  29
-
-/** SPI_MEM_USER1_REG register
- *  SPI0 user1 register.
- */
-#define SPI_MEM_USER1_REG(i)  (REG_SPI_MEM_BASE(i) + 0x1c)
-/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
- *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
- *  (cycle_num-1).
- */
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S)
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x0000003FU
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1;
- *  SPI0 USR_CMD read or write data byte length -1
- */
-#define SPI_MEM_USR_DBYTELEN    0x00000007U
-#define SPI_MEM_USR_DBYTELEN_M  (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S)
-#define SPI_MEM_USR_DBYTELEN_V  0x00000007U
-#define SPI_MEM_USR_DBYTELEN_S  6
-/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23;
- *  The length in bits of address phase. The register value shall be (bit_num-1).
- */
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_M  (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S)
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
-
-/** SPI_MEM_USER2_REG register
- *  SPI0 user2 register.
- */
-#define SPI_MEM_USER2_REG(i)  (REG_SPI_MEM_BASE(i) + 0x20)
-/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- *  The value of  command.
- */
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_M  (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S)
-#define SPI_MEM_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- *  The length in bits of command phase. The register value shall be (bit_num-1)
- */
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_M  (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S)
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
-
-/** SPI_MEM_MISC_REG register
- *  SPI0 misc register
- */
-#define SPI_MEM_MISC_REG(i)  (REG_SPI_MEM_BASE(i) + 0x34)
-/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0;
- *  For SPI0,  flash is connected to SUBPINs.
- */
-#define SPI_MEM_FSUB_PIN    (BIT(7))
-#define SPI_MEM_FSUB_PIN_M  (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S)
-#define SPI_MEM_FSUB_PIN_V  0x00000001U
-#define SPI_MEM_FSUB_PIN_S  7
-/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0;
- *  For SPI0,  sram is connected to SUBPINs.
- */
-#define SPI_MEM_SSUB_PIN    (BIT(8))
-#define SPI_MEM_SSUB_PIN_M  (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S)
-#define SPI_MEM_SSUB_PIN_V  0x00000001U
-#define SPI_MEM_SSUB_PIN_S  8
-/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0;
- *  1: SPI_CLK line is high when idle     0: spi clk line is low when idle
- */
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S)
-#define SPI_MEM_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0;
- *  SPI_CS line keep low when the bit is set.
- */
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S)
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
-
-/** SPI_MEM_CACHE_FCTRL_REG register
- *  SPI0 bit mode control register.
- */
-#define SPI_MEM_CACHE_FCTRL_REG(i)  (REG_SPI_MEM_BASE(i) + 0x3c)
-/** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1;
- *  Set this bit to check AXI read/write the same address region.
- */
-#define SPI_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_M  (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S)
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_V  0x00000001U
-#define SPI_SAME_AW_AR_ADDR_CHK_EN_S  30
-/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1;
- *  Set this bit to close AXI read/write transfer to MSPI, which means that only
- *  SLV_ERR will be replied to BRESP/RRESP.
- */
-#define SPI_CLOSE_AXI_INF_EN    (BIT(31))
-#define SPI_CLOSE_AXI_INF_EN_M  (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S)
-#define SPI_CLOSE_AXI_INF_EN_V  0x00000001U
-#define SPI_CLOSE_AXI_INF_EN_S  31
-
-/** SPI_MEM_SRAM_CMD_REG register
- *  SPI0 external RAM mode control register
- */
-#define SPI_MEM_SRAM_CMD_REG(i)  (REG_SPI_MEM_BASE(i) + 0x44)
-/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0;
- *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- *  the level of SPI_DQS is output by the MSPI controller.
- */
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S)
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x00000001U
-#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/** SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0;
- *  In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- *  the level of SPI_IO[7:0] is output by the MSPI controller.
- */
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M  (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S)
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V  0x00000001U
-#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/** SPI_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1;
- *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are
- *  always 1. 0: Others.
- */
-#define SPI_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_M  (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S)
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_SMEM_DQS_IE_ALWAYS_ON_S  30
-/** SPI_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1;
- *  When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0]
- *  are always 1. 0: Others.
- */
-#define SPI_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_M  (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S)
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_V  0x00000001U
-#define SPI_SMEM_DATA_IE_ALWAYS_ON_S  31
-
-/** SPI_MEM_FSM_REG register
- *  SPI0 FSM status register
- */
-#define SPI_MEM_FSM_REG(i)  (REG_SPI_MEM_BASE(i) + 0x54)
-/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
- *  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
- */
-#define SPI_MEM_LOCK_DELAY_TIME    0x0000001FU
-#define SPI_MEM_LOCK_DELAY_TIME_M  (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S)
-#define SPI_MEM_LOCK_DELAY_TIME_V  0x0000001FU
-#define SPI_MEM_LOCK_DELAY_TIME_S  7
-
-/** SPI_MEM_INT_ENA_REG register
- *  SPI0 interrupt enable register
- */
-#define SPI_MEM_INT_ENA_REG(i)  (REG_SPI_MEM_BASE(i) + 0xc0)
-/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S)
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S)
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/** SPI_MEM_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0;
- *  The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
- */
-#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_M  (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S)
-#define SPI_MEM_ECC_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_ENA_S  5
-/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
- */
-#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_M  (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S)
-#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M  (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S  9
-
-/** SPI_MEM_INT_CLR_REG register
- *  SPI0 interrupt clear register
- */
-#define SPI_MEM_INT_CLR_REG(i)  (REG_SPI_MEM_BASE(i) + 0xc4)
-/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S)
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S)
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/** SPI_MEM_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0;
- *  The clear bit for SPI_MEM_ECC_ERR_INT interrupt.
- */
-#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_M  (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S)
-#define SPI_MEM_ECC_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_CLR_S  5
-/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.
- */
-#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_M  (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S)
-#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
- *  The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
- *  The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
-
-/** SPI_MEM_INT_RAW_REG register
- *  SPI0 interrupt raw register
- */
-#define SPI_MEM_INT_RAW_REG(i)  (REG_SPI_MEM_BASE(i) + 0xc8)
-/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
- *  changed from non idle state to idle state. It means that SPI_CS raises high. 0:
- *  Others
- */
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S)
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is
- *  changed from non idle state to idle state. 0: Others.
- */
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S)
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/** SPI_MEM_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0;
- *  The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set
- *  and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times
- *  of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When
- *  SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is
- *  triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger
- *  than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and
- *  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
- *  of SPI0/1 ECC read external RAM and flash are equal or bigger than
- *  SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN
- *  are cleared, this bit will not be triggered.
- */
-#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_M  (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S)
-#define SPI_MEM_ECC_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_RAW_S  5
-/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is
- *  rejected. 0: Others.
- */
-#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_M  (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S)
-#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
- *  address is invalid by compared to MMU configuration. 0: Others.
- */
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0;
- *  The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write
- *  flash request is received. 0: Others.
- */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0;
- *  The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
- *  address is invalid by compared to MMU configuration. 0: Others.
- */
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
-
-/** SPI_MEM_INT_ST_REG register
- *  SPI0 interrupt status register
- */
-#define SPI_MEM_INT_ST_REG(i)  (REG_SPI_MEM_BASE(i) + 0xcc)
-/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
- */
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S)
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
- */
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S)
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x00000001U
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/** SPI_MEM_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0;
- *  The status bit for SPI_MEM_ECC_ERR_INT interrupt.
- */
-#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_M  (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S)
-#define SPI_MEM_ECC_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_ECC_ERR_INT_ST_S  5
-/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0;
- *  The status bit for SPI_MEM_PMS_REJECT_INT interrupt.
- */
-#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_M  (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S)
-#define SPI_MEM_PMS_REJECT_INT_ST_V  0x00000001U
-#define SPI_MEM_PMS_REJECT_INT_ST_S  6
-/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S)
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S)
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/** SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
- *  The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.
- */
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S)
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
-
-/** SPI_MEM_DDR_REG register
- *  SPI0 flash DDR mode control register
- */
-#define SPI_MEM_DDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0xd4)
-/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
- *  1: in DDR mode,  0 in SDR mode
- */
-#define SPI_FMEM_DDR_EN    (BIT(0))
-#define SPI_FMEM_DDR_EN_M  (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S)
-#define SPI_FMEM_DDR_EN_V  0x00000001U
-#define SPI_FMEM_DDR_EN_S  0
-/** SPI_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
- *  Set the bit to enable variable dummy cycle in spi DDR mode.
- */
-#define SPI_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_FMEM_VAR_DUMMY_M  (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S)
-#define SPI_FMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_FMEM_VAR_DUMMY_S  1
-/** SPI_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
- *  Set the bit to reorder rx data of the word in spi DDR mode.
- */
-#define SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_FMEM_DDR_RDAT_SWP_M  (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S)
-#define SPI_FMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_FMEM_DDR_RDAT_SWP_S  2
-/** SPI_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
- *  Set the bit to reorder tx data of the word in spi DDR mode.
- */
-#define SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_FMEM_DDR_WDAT_SWP_M  (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S)
-#define SPI_FMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_FMEM_DDR_WDAT_SWP_S  3
-/** SPI_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
- *  the bit is used to disable dual edge in command phase when DDR mode.
- */
-#define SPI_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_FMEM_DDR_CMD_DIS_M  (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S)
-#define SPI_FMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_FMEM_DDR_CMD_DIS_S  4
-/** SPI_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
- *  It is the minimum output data length in the panda device.
- */
-#define SPI_FMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_FMEM_OUTMINBYTELEN_M  (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S)
-#define SPI_FMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_FMEM_OUTMINBYTELEN_S  5
-/** SPI_FMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
- *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- *  accesses to flash.
- */
-#define SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_FMEM_TX_DDR_MSK_EN_M  (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S)
-#define SPI_FMEM_TX_DDR_MSK_EN_V  0x00000001U
-#define SPI_FMEM_TX_DDR_MSK_EN_S  12
-/** SPI_FMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
- *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
- *  accesses to flash.
- */
-#define SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_FMEM_RX_DDR_MSK_EN_M  (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S)
-#define SPI_FMEM_RX_DDR_MSK_EN_V  0x00000001U
-#define SPI_FMEM_RX_DDR_MSK_EN_S  13
-/** SPI_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
- *  The delay number of data strobe which from memory based on SPI clock.
- */
-#define SPI_FMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_FMEM_USR_DDR_DQS_THD_M  (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S)
-#define SPI_FMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_FMEM_USR_DDR_DQS_THD_S  14
-/** SPI_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
- *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
- *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
- *  negative edge of SPI_DQS.
- */
-#define SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_FMEM_DDR_DQS_LOOP_M  (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S)
-#define SPI_FMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_FMEM_DDR_DQS_LOOP_S  21
-/** SPI_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
- *  Set this bit to enable the differential SPI_CLK#.
- */
-#define SPI_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_FMEM_CLK_DIFF_EN_M  (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S)
-#define SPI_FMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_FMEM_CLK_DIFF_EN_S  24
-/** SPI_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
- *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
- */
-#define SPI_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_FMEM_DQS_CA_IN_M  (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S)
-#define SPI_FMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_FMEM_DQS_CA_IN_S  26
-/** SPI_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
- *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
- *  accesses flash or SPI1 accesses flash or sram.
- */
-#define SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_M  (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
- *  Set this bit to invert SPI_DIFF when accesses to flash. .
- */
-#define SPI_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_FMEM_CLK_DIFF_INV_M  (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S)
-#define SPI_FMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_FMEM_CLK_DIFF_INV_S  28
-/** SPI_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
- *  Set this bit to enable octa_ram address out when accesses to flash, which means
- *  ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
- */
-#define SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_FMEM_OCTA_RAM_ADDR_M  (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S)
-#define SPI_FMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_FMEM_OCTA_RAM_ADDR_S  29
-/** SPI_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
- *  Set this bit to enable HyperRAM address out when accesses to flash, which means
- *  ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
- */
-#define SPI_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_FMEM_HYPERBUS_CA_M  (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S)
-#define SPI_FMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_FMEM_HYPERBUS_CA_S  30
-
-/** SPI_SMEM_DDR_REG register
- *  SPI0 external RAM DDR mode control register
- */
-#define SPI_SMEM_DDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0xd8)
-/** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
- *  1: in DDR mode,  0 in SDR mode
- */
-#define SPI_SMEM_DDR_EN    (BIT(0))
-#define SPI_SMEM_DDR_EN_M  (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S)
-#define SPI_SMEM_DDR_EN_V  0x00000001U
-#define SPI_SMEM_DDR_EN_S  0
-/** SPI_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0;
- *  Set the bit to enable variable dummy cycle in spi DDR mode.
- */
-#define SPI_SMEM_VAR_DUMMY    (BIT(1))
-#define SPI_SMEM_VAR_DUMMY_M  (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S)
-#define SPI_SMEM_VAR_DUMMY_V  0x00000001U
-#define SPI_SMEM_VAR_DUMMY_S  1
-/** SPI_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0;
- *  Set the bit to reorder rx data of the word in spi DDR mode.
- */
-#define SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_SMEM_DDR_RDAT_SWP_M  (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S)
-#define SPI_SMEM_DDR_RDAT_SWP_V  0x00000001U
-#define SPI_SMEM_DDR_RDAT_SWP_S  2
-/** SPI_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0;
- *  Set the bit to reorder tx data of the word in spi DDR mode.
- */
-#define SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_SMEM_DDR_WDAT_SWP_M  (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S)
-#define SPI_SMEM_DDR_WDAT_SWP_V  0x00000001U
-#define SPI_SMEM_DDR_WDAT_SWP_S  3
-/** SPI_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0;
- *  the bit is used to disable dual edge in command phase when DDR mode.
- */
-#define SPI_SMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_SMEM_DDR_CMD_DIS_M  (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S)
-#define SPI_SMEM_DDR_CMD_DIS_V  0x00000001U
-#define SPI_SMEM_DDR_CMD_DIS_S  4
-/** SPI_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1;
- *  It is the minimum output data length in the DDR psram.
- */
-#define SPI_SMEM_OUTMINBYTELEN    0x0000007FU
-#define SPI_SMEM_OUTMINBYTELEN_M  (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S)
-#define SPI_SMEM_OUTMINBYTELEN_V  0x0000007FU
-#define SPI_SMEM_OUTMINBYTELEN_S  5
-/** SPI_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1;
- *  Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- *  accesses to external RAM.
- */
-#define SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_SMEM_TX_DDR_MSK_EN_M  (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S)
-#define SPI_SMEM_TX_DDR_MSK_EN_V  0x00000001U
-#define SPI_SMEM_TX_DDR_MSK_EN_S  12
-/** SPI_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1;
- *  Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
- *  accesses to external RAM.
- */
-#define SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_SMEM_RX_DDR_MSK_EN_M  (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S)
-#define SPI_SMEM_RX_DDR_MSK_EN_V  0x00000001U
-#define SPI_SMEM_RX_DDR_MSK_EN_S  13
-/** SPI_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0;
- *  The delay number of data strobe which from memory based on SPI clock.
- */
-#define SPI_SMEM_USR_DDR_DQS_THD    0x0000007FU
-#define SPI_SMEM_USR_DDR_DQS_THD_M  (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S)
-#define SPI_SMEM_USR_DDR_DQS_THD_V  0x0000007FU
-#define SPI_SMEM_USR_DDR_DQS_THD_S  14
-/** SPI_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0;
- *  1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
- *  spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
- *  SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
- *  negative edge of SPI_DQS.
- */
-#define SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_SMEM_DDR_DQS_LOOP_M  (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S)
-#define SPI_SMEM_DDR_DQS_LOOP_V  0x00000001U
-#define SPI_SMEM_DDR_DQS_LOOP_S  21
-/** SPI_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0;
- *  Set this bit to enable the differential SPI_CLK#.
- */
-#define SPI_SMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_SMEM_CLK_DIFF_EN_M  (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S)
-#define SPI_SMEM_CLK_DIFF_EN_V  0x00000001U
-#define SPI_SMEM_CLK_DIFF_EN_S  24
-/** SPI_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0;
- *  Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
- */
-#define SPI_SMEM_DQS_CA_IN    (BIT(26))
-#define SPI_SMEM_DQS_CA_IN_M  (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S)
-#define SPI_SMEM_DQS_CA_IN_V  0x00000001U
-#define SPI_SMEM_DQS_CA_IN_S  26
-/** SPI_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0;
- *  Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
- *  accesses flash or SPI1 accesses flash or sram.
- */
-#define SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_M  (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S)
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x00000001U
-#define SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
-/** SPI_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0;
- *  Set this bit to invert SPI_DIFF when accesses to external RAM. .
- */
-#define SPI_SMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_SMEM_CLK_DIFF_INV_M  (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S)
-#define SPI_SMEM_CLK_DIFF_INV_V  0x00000001U
-#define SPI_SMEM_CLK_DIFF_INV_S  28
-/** SPI_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0;
- *  Set this bit to enable octa_ram address out when accesses to external RAM, which
- *  means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
- *  1'b0}.
- */
-#define SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_SMEM_OCTA_RAM_ADDR_M  (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S)
-#define SPI_SMEM_OCTA_RAM_ADDR_V  0x00000001U
-#define SPI_SMEM_OCTA_RAM_ADDR_S  29
-/** SPI_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0;
- *  Set this bit to enable HyperRAM address out when accesses to external RAM, which
- *  means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
- */
-#define SPI_SMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_SMEM_HYPERBUS_CA_M  (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S)
-#define SPI_SMEM_HYPERBUS_CA_V  0x00000001U
-#define SPI_SMEM_HYPERBUS_CA_S  30
-
-/** SPI_FMEM_PMS0_ATTR_REG register
- *  MSPI flash PMS section 0 attribute register
- */
-#define SPI_FMEM_PMS0_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x100)
-/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 flash PMS section 0 read accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS0_RD_ATTR_M  (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S)
-#define SPI_FMEM_PMS0_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS0_RD_ATTR_S  0
-/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 flash PMS section 0 write accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS0_WR_ATTR_M  (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S)
-#define SPI_FMEM_PMS0_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS0_WR_ATTR_S  1
-/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and
- *  SPI_FMEM_PMS0_SIZE_REG.
- */
-#define SPI_FMEM_PMS0_ECC    (BIT(2))
-#define SPI_FMEM_PMS0_ECC_M  (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S)
-#define SPI_FMEM_PMS0_ECC_V  0x00000001U
-#define SPI_FMEM_PMS0_ECC_S  2
-
-/** SPI_FMEM_PMS1_ATTR_REG register
- *  MSPI flash PMS section 1 attribute register
- */
-#define SPI_FMEM_PMS1_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x104)
-/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 flash PMS section 1 read accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS1_RD_ATTR_M  (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S)
-#define SPI_FMEM_PMS1_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS1_RD_ATTR_S  0
-/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 flash PMS section 1 write accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS1_WR_ATTR_M  (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S)
-#define SPI_FMEM_PMS1_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS1_WR_ATTR_S  1
-/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and
- *  SPI_FMEM_PMS1_SIZE_REG.
- */
-#define SPI_FMEM_PMS1_ECC    (BIT(2))
-#define SPI_FMEM_PMS1_ECC_M  (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S)
-#define SPI_FMEM_PMS1_ECC_V  0x00000001U
-#define SPI_FMEM_PMS1_ECC_S  2
-
-/** SPI_FMEM_PMS2_ATTR_REG register
- *  MSPI flash PMS section 2 attribute register
- */
-#define SPI_FMEM_PMS2_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x108)
-/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 flash PMS section 2 read accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS2_RD_ATTR_M  (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S)
-#define SPI_FMEM_PMS2_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS2_RD_ATTR_S  0
-/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 flash PMS section 2 write accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS2_WR_ATTR_M  (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S)
-#define SPI_FMEM_PMS2_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS2_WR_ATTR_S  1
-/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and
- *  SPI_FMEM_PMS2_SIZE_REG.
- */
-#define SPI_FMEM_PMS2_ECC    (BIT(2))
-#define SPI_FMEM_PMS2_ECC_M  (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S)
-#define SPI_FMEM_PMS2_ECC_V  0x00000001U
-#define SPI_FMEM_PMS2_ECC_S  2
-
-/** SPI_FMEM_PMS3_ATTR_REG register
- *  MSPI flash PMS section 3 attribute register
- */
-#define SPI_FMEM_PMS3_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x10c)
-/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 flash PMS section 3 read accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_FMEM_PMS3_RD_ATTR_M  (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S)
-#define SPI_FMEM_PMS3_RD_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS3_RD_ATTR_S  0
-/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 flash PMS section 3 write accessible. 0: Not allowed.
- */
-#define SPI_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_FMEM_PMS3_WR_ATTR_M  (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S)
-#define SPI_FMEM_PMS3_WR_ATTR_V  0x00000001U
-#define SPI_FMEM_PMS3_WR_ATTR_S  1
-/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS
- *  section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and
- *  SPI_FMEM_PMS3_SIZE_REG.
- */
-#define SPI_FMEM_PMS3_ECC    (BIT(2))
-#define SPI_FMEM_PMS3_ECC_M  (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S)
-#define SPI_FMEM_PMS3_ECC_V  0x00000001U
-#define SPI_FMEM_PMS3_ECC_S  2
-
-/** SPI_FMEM_PMS0_ADDR_REG register
- *  SPI1 flash PMS section 0 start address register
- */
-#define SPI_FMEM_PMS0_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x110)
-/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 flash PMS section 0 start address value
- */
-#define SPI_FMEM_PMS0_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS0_ADDR_S_M  (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S)
-#define SPI_FMEM_PMS0_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS0_ADDR_S_S  0
-
-/** SPI_FMEM_PMS1_ADDR_REG register
- *  SPI1 flash PMS section 1 start address register
- */
-#define SPI_FMEM_PMS1_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x114)
-/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 flash PMS section 1 start address value
- */
-#define SPI_FMEM_PMS1_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS1_ADDR_S_M  (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S)
-#define SPI_FMEM_PMS1_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS1_ADDR_S_S  0
-
-/** SPI_FMEM_PMS2_ADDR_REG register
- *  SPI1 flash PMS section 2 start address register
- */
-#define SPI_FMEM_PMS2_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x118)
-/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 flash PMS section 2 start address value
- */
-#define SPI_FMEM_PMS2_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS2_ADDR_S_M  (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S)
-#define SPI_FMEM_PMS2_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS2_ADDR_S_S  0
-
-/** SPI_FMEM_PMS3_ADDR_REG register
- *  SPI1 flash PMS section 3 start address register
- */
-#define SPI_FMEM_PMS3_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x11c)
-/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 flash PMS section 3 start address value
- */
-#define SPI_FMEM_PMS3_ADDR_S    0x07FFFFFFU
-#define SPI_FMEM_PMS3_ADDR_S_M  (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S)
-#define SPI_FMEM_PMS3_ADDR_S_V  0x07FFFFFFU
-#define SPI_FMEM_PMS3_ADDR_S_S  0
-
-/** SPI_FMEM_PMS0_SIZE_REG register
- *  SPI1 flash PMS section 0 start address register
- */
-#define SPI_FMEM_PMS0_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x120)
-/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S,
- *  SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE)
- */
-#define SPI_FMEM_PMS0_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS0_SIZE_M  (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S)
-#define SPI_FMEM_PMS0_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS0_SIZE_S  0
-
-/** SPI_FMEM_PMS1_SIZE_REG register
- *  SPI1 flash PMS section 1 start address register
- */
-#define SPI_FMEM_PMS1_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x124)
-/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S,
- *  SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE)
- */
-#define SPI_FMEM_PMS1_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS1_SIZE_M  (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S)
-#define SPI_FMEM_PMS1_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS1_SIZE_S  0
-
-/** SPI_FMEM_PMS2_SIZE_REG register
- *  SPI1 flash PMS section 2 start address register
- */
-#define SPI_FMEM_PMS2_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x128)
-/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S,
- *  SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE)
- */
-#define SPI_FMEM_PMS2_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS2_SIZE_M  (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S)
-#define SPI_FMEM_PMS2_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS2_SIZE_S  0
-
-/** SPI_FMEM_PMS3_SIZE_REG register
- *  SPI1 flash PMS section 3 start address register
- */
-#define SPI_FMEM_PMS3_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x12c)
-/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S,
- *  SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE)
- */
-#define SPI_FMEM_PMS3_SIZE    0x00007FFFU
-#define SPI_FMEM_PMS3_SIZE_M  (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S)
-#define SPI_FMEM_PMS3_SIZE_V  0x00007FFFU
-#define SPI_FMEM_PMS3_SIZE_S  0
-
-/** SPI_SMEM_PMS0_ATTR_REG register
- *  SPI1 flash PMS section 0 start address register
- */
-#define SPI_SMEM_PMS0_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x130)
-/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS0_RD_ATTR_M  (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S)
-#define SPI_SMEM_PMS0_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS0_RD_ATTR_S  0
-/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS0_WR_ATTR_M  (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S)
-#define SPI_SMEM_PMS0_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS0_WR_ATTR_S  1
-/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and
- *  SPI_SMEM_PMS0_SIZE_REG.
- */
-#define SPI_SMEM_PMS0_ECC    (BIT(2))
-#define SPI_SMEM_PMS0_ECC_M  (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S)
-#define SPI_SMEM_PMS0_ECC_V  0x00000001U
-#define SPI_SMEM_PMS0_ECC_S  2
-
-/** SPI_SMEM_PMS1_ATTR_REG register
- *  SPI1 flash PMS section 1 start address register
- */
-#define SPI_SMEM_PMS1_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x134)
-/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS1_RD_ATTR_M  (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S)
-#define SPI_SMEM_PMS1_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS1_RD_ATTR_S  0
-/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS1_WR_ATTR_M  (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S)
-#define SPI_SMEM_PMS1_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS1_WR_ATTR_S  1
-/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and
- *  SPI_SMEM_PMS1_SIZE_REG.
- */
-#define SPI_SMEM_PMS1_ECC    (BIT(2))
-#define SPI_SMEM_PMS1_ECC_M  (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S)
-#define SPI_SMEM_PMS1_ECC_V  0x00000001U
-#define SPI_SMEM_PMS1_ECC_S  2
-
-/** SPI_SMEM_PMS2_ATTR_REG register
- *  SPI1 flash PMS section 2 start address register
- */
-#define SPI_SMEM_PMS2_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x138)
-/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS2_RD_ATTR_M  (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S)
-#define SPI_SMEM_PMS2_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS2_RD_ATTR_S  0
-/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS2_WR_ATTR_M  (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S)
-#define SPI_SMEM_PMS2_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS2_WR_ATTR_S  1
-/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and
- *  SPI_SMEM_PMS2_SIZE_REG.
- */
-#define SPI_SMEM_PMS2_ECC    (BIT(2))
-#define SPI_SMEM_PMS2_ECC_M  (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S)
-#define SPI_SMEM_PMS2_ECC_V  0x00000001U
-#define SPI_SMEM_PMS2_ECC_S  2
-
-/** SPI_SMEM_PMS3_ATTR_REG register
- *  SPI1 flash PMS section 3 start address register
- */
-#define SPI_SMEM_PMS3_ATTR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x13c)
-/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
- *  1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_SMEM_PMS3_RD_ATTR_M  (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S)
-#define SPI_SMEM_PMS3_RD_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS3_RD_ATTR_S  0
-/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1;
- *  1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed.
- */
-#define SPI_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_SMEM_PMS3_WR_ATTR_M  (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S)
-#define SPI_SMEM_PMS3_WR_ATTR_V  0x00000001U
-#define SPI_SMEM_PMS3_WR_ATTR_S  1
-/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0;
- *  SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The
- *  external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and
- *  SPI_SMEM_PMS3_SIZE_REG.
- */
-#define SPI_SMEM_PMS3_ECC    (BIT(2))
-#define SPI_SMEM_PMS3_ECC_M  (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S)
-#define SPI_SMEM_PMS3_ECC_V  0x00000001U
-#define SPI_SMEM_PMS3_ECC_S  2
-
-/** SPI_SMEM_PMS0_ADDR_REG register
- *  SPI1 external RAM PMS section 0 start address register
- */
-#define SPI_SMEM_PMS0_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x140)
-/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 external RAM PMS section 0 start address value
- */
-#define SPI_SMEM_PMS0_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS0_ADDR_S_M  (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S)
-#define SPI_SMEM_PMS0_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS0_ADDR_S_S  0
-
-/** SPI_SMEM_PMS1_ADDR_REG register
- *  SPI1 external RAM PMS section 1 start address register
- */
-#define SPI_SMEM_PMS1_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x144)
-/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 external RAM PMS section 1 start address value
- */
-#define SPI_SMEM_PMS1_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS1_ADDR_S_M  (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S)
-#define SPI_SMEM_PMS1_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS1_ADDR_S_S  0
-
-/** SPI_SMEM_PMS2_ADDR_REG register
- *  SPI1 external RAM PMS section 2 start address register
- */
-#define SPI_SMEM_PMS2_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x148)
-/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 external RAM PMS section 2 start address value
- */
-#define SPI_SMEM_PMS2_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS2_ADDR_S_M  (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S)
-#define SPI_SMEM_PMS2_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS2_ADDR_S_S  0
-
-/** SPI_SMEM_PMS3_ADDR_REG register
- *  SPI1 external RAM PMS section 3 start address register
- */
-#define SPI_SMEM_PMS3_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x14c)
-/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
- *  SPI1 external RAM PMS section 3 start address value
- */
-#define SPI_SMEM_PMS3_ADDR_S    0x07FFFFFFU
-#define SPI_SMEM_PMS3_ADDR_S_M  (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S)
-#define SPI_SMEM_PMS3_ADDR_S_V  0x07FFFFFFU
-#define SPI_SMEM_PMS3_ADDR_S_S  0
-
-/** SPI_SMEM_PMS0_SIZE_REG register
- *  SPI1 external RAM PMS section 0 start address register
- */
-#define SPI_SMEM_PMS0_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x150)
-/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S,
- *  SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE)
- */
-#define SPI_SMEM_PMS0_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS0_SIZE_M  (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S)
-#define SPI_SMEM_PMS0_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS0_SIZE_S  0
-
-/** SPI_SMEM_PMS1_SIZE_REG register
- *  SPI1 external RAM PMS section 1 start address register
- */
-#define SPI_SMEM_PMS1_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x154)
-/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S,
- *  SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE)
- */
-#define SPI_SMEM_PMS1_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS1_SIZE_M  (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S)
-#define SPI_SMEM_PMS1_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS1_SIZE_S  0
-
-/** SPI_SMEM_PMS2_SIZE_REG register
- *  SPI1 external RAM PMS section 2 start address register
- */
-#define SPI_SMEM_PMS2_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x158)
-/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S,
- *  SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE)
- */
-#define SPI_SMEM_PMS2_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS2_SIZE_M  (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S)
-#define SPI_SMEM_PMS2_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS2_SIZE_S  0
-
-/** SPI_SMEM_PMS3_SIZE_REG register
- *  SPI1 external RAM PMS section 3 start address register
- */
-#define SPI_SMEM_PMS3_SIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x15c)
-/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
- *  SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S,
- *  SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE)
- */
-#define SPI_SMEM_PMS3_SIZE    0x00007FFFU
-#define SPI_SMEM_PMS3_SIZE_M  (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S)
-#define SPI_SMEM_PMS3_SIZE_V  0x00007FFFU
-#define SPI_SMEM_PMS3_SIZE_S  0
-
-/** SPI_MEM_PMS_REJECT_REG register
- *  SPI1 access reject register
- */
-#define SPI_MEM_PMS_REJECT_REG(i)  (REG_SPI_MEM_BASE(i) + 0x164)
-/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
- *  This bits show the first SPI1 access error address. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
- */
-#define SPI_MEM_REJECT_ADDR    0x07FFFFFFU
-#define SPI_MEM_REJECT_ADDR_M  (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S)
-#define SPI_MEM_REJECT_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_REJECT_ADDR_S  0
-/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0;
- *  Set this bit to enable SPI0/1 transfer permission control function.
- */
-#define SPI_MEM_PM_EN    (BIT(27))
-#define SPI_MEM_PM_EN_M  (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S)
-#define SPI_MEM_PM_EN_V  0x00000001U
-#define SPI_MEM_PM_EN_S  27
-/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0;
- *  1: SPI1 write access error. 0: No write access error. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
- */
-#define SPI_MEM_PMS_LD    (BIT(28))
-#define SPI_MEM_PMS_LD_M  (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S)
-#define SPI_MEM_PMS_LD_V  0x00000001U
-#define SPI_MEM_PMS_LD_S  28
-/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0;
- *  1: SPI1 read access error. 0: No read access error. It is cleared by when
- *  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
- */
-#define SPI_MEM_PMS_ST    (BIT(29))
-#define SPI_MEM_PMS_ST_M  (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S)
-#define SPI_MEM_PMS_ST_V  0x00000001U
-#define SPI_MEM_PMS_ST_S  29
-/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0;
- *  1: SPI1 access is rejected because of address miss. 0: No address miss error. It is
- *  cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
- */
-#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_M  (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S)
-#define SPI_MEM_PMS_MULTI_HIT_V  0x00000001U
-#define SPI_MEM_PMS_MULTI_HIT_S  30
-/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0;
- *  1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- *  error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.
- */
-#define SPI_MEM_PMS_IVD    (BIT(31))
-#define SPI_MEM_PMS_IVD_M  (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S)
-#define SPI_MEM_PMS_IVD_V  0x00000001U
-#define SPI_MEM_PMS_IVD_S  31
-
-/** SPI_MEM_ECC_CTRL_REG register
- *  MSPI ECC control register
- */
-#define SPI_MEM_ECC_CTRL_REG(i)  (REG_SPI_MEM_BASE(i) + 0x168)
-/** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0;
- *  This bits show the error times of MSPI ECC read. It is cleared by when
- *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
- */
-#define SPI_MEM_ECC_ERR_CNT    0x0000003FU
-#define SPI_MEM_ECC_ERR_CNT_M  (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S)
-#define SPI_MEM_ECC_ERR_CNT_V  0x0000003FU
-#define SPI_MEM_ECC_ERR_CNT_S  5
-/** SPI_FMEM_ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10;
- *  Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.
- */
-#define SPI_FMEM_ECC_ERR_INT_NUM    0x0000003FU
-#define SPI_FMEM_ECC_ERR_INT_NUM_M  (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S)
-#define SPI_FMEM_ECC_ERR_INT_NUM_V  0x0000003FU
-#define SPI_FMEM_ECC_ERR_INT_NUM_S  11
-/** SPI_FMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
- *  Set this bit to calculate the error times of MSPI ECC read when accesses to flash.
- */
-#define SPI_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_FMEM_ECC_ERR_INT_EN_M  (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S)
-#define SPI_FMEM_ECC_ERR_INT_EN_V  0x00000001U
-#define SPI_FMEM_ECC_ERR_INT_EN_S  17
-/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0;
- *  Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
- *  1024 bytes. 3: 2048 bytes.
- */
-#define SPI_FMEM_PAGE_SIZE    0x00000003U
-#define SPI_FMEM_PAGE_SIZE_M  (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S)
-#define SPI_FMEM_PAGE_SIZE_V  0x00000003U
-#define SPI_FMEM_PAGE_SIZE_S  18
-/** SPI_FMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
- *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
- *  ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit
- *  should be 0. Otherwise, this bit should be 1.
- */
-#define SPI_FMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_FMEM_ECC_ADDR_EN_M  (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S)
-#define SPI_FMEM_ECC_ADDR_EN_V  0x00000001U
-#define SPI_FMEM_ECC_ADDR_EN_S  20
-/** SPI_MEM_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0;
- *  Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.
- */
-#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_M  (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S)
-#define SPI_MEM_USR_ECC_ADDR_EN_V  0x00000001U
-#define SPI_MEM_USR_ECC_ADDR_EN_S  21
-/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1;
- *  1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is
- *  updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and
- *  SPI_MEM_ECC_ERR_ADDR record the first ECC error information.
- */
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S)
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x00000001U
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/** SPI_MEM_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0;
- *  Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to
- *  byte 0 bit 0 to byte 15 bit 7)
- */
-#define SPI_MEM_ECC_ERR_BITS    0x0000007FU
-#define SPI_MEM_ECC_ERR_BITS_M  (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S)
-#define SPI_MEM_ECC_ERR_BITS_V  0x0000007FU
-#define SPI_MEM_ECC_ERR_BITS_S  25
-
-/** SPI_MEM_ECC_ERR_ADDR_REG register
- *  MSPI ECC error address register
- */
-#define SPI_MEM_ECC_ERR_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x16c)
-/** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0;
- *  This bits show the first MSPI ECC error address. It is cleared by when
- *  SPI_MEM_ECC_ERR_INT_CLR bit is set.
- */
-#define SPI_MEM_ECC_ERR_ADDR    0x07FFFFFFU
-#define SPI_MEM_ECC_ERR_ADDR_M  (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S)
-#define SPI_MEM_ECC_ERR_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_ECC_ERR_ADDR_S  0
-
-/** SPI_MEM_AXI_ERR_ADDR_REG register
- *  SPI0 AXI request error address.
- */
-#define SPI_MEM_AXI_ERR_ADDR_REG(i)  (REG_SPI_MEM_BASE(i) + 0x170)
-/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
- *  This bits show the first AXI write/read invalid error or AXI write flash error
- *  address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
- *  SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.
- */
-#define SPI_MEM_AXI_ERR_ADDR    0x07FFFFFFU
-#define SPI_MEM_AXI_ERR_ADDR_M  (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S)
-#define SPI_MEM_AXI_ERR_ADDR_V  0x07FFFFFFU
-#define SPI_MEM_AXI_ERR_ADDR_S  0
-
-/** SPI_SMEM_ECC_CTRL_REG register
- *  MSPI ECC control register
- */
-#define SPI_SMEM_ECC_CTRL_REG(i)  (REG_SPI_MEM_BASE(i) + 0x174)
-/** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
- *  Set this bit to calculate the error times of MSPI ECC read when accesses to
- *  external RAM.
- */
-#define SPI_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_SMEM_ECC_ERR_INT_EN_M  (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S)
-#define SPI_SMEM_ECC_ERR_INT_EN_V  0x00000001U
-#define SPI_SMEM_ECC_ERR_INT_EN_S  17
-/** SPI_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2;
- *  Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes.
- *  2: 1024 bytes. 3: 2048 bytes.
- */
-#define SPI_SMEM_PAGE_SIZE    0x00000003U
-#define SPI_SMEM_PAGE_SIZE_M  (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S)
-#define SPI_SMEM_PAGE_SIZE_V  0x00000003U
-#define SPI_SMEM_PAGE_SIZE_S  18
-/** SPI_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0;
- *  Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the
- *  ECC region or non-ECC region of external RAM. If there is no ECC region in external
- *  RAM, this bit should be 0. Otherwise, this bit should be 1.
- */
-#define SPI_SMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_SMEM_ECC_ADDR_EN_M  (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S)
-#define SPI_SMEM_ECC_ADDR_EN_V  0x00000001U
-#define SPI_SMEM_ECC_ADDR_EN_S  20
-
-/** SPI_SMEM_AXI_ADDR_CTRL_REG register
- *  SPI0 AXI address control register
- */
-#define SPI_SMEM_AXI_ADDR_CTRL_REG(i)  (REG_SPI_MEM_BASE(i) + 0x178)
-/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
- *  The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
- *  and SPI0 transfers are done. 0: Others.
- */
-#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_M  (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S)
-#define SPI_MEM_ALL_FIFO_EMPTY_V  0x00000001U
-#define SPI_MEM_ALL_FIFO_EMPTY_S  26
-/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1;
- *  1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.
- */
-#define SPI_RDATA_AFIFO_REMPTY    (BIT(27))
-#define SPI_RDATA_AFIFO_REMPTY_M  (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S)
-#define SPI_RDATA_AFIFO_REMPTY_V  0x00000001U
-#define SPI_RDATA_AFIFO_REMPTY_S  27
-/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1;
- *  1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.
- */
-#define SPI_RADDR_AFIFO_REMPTY    (BIT(28))
-#define SPI_RADDR_AFIFO_REMPTY_M  (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S)
-#define SPI_RADDR_AFIFO_REMPTY_V  0x00000001U
-#define SPI_RADDR_AFIFO_REMPTY_S  28
-/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1;
- *  1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.
- */
-#define SPI_WDATA_AFIFO_REMPTY    (BIT(29))
-#define SPI_WDATA_AFIFO_REMPTY_M  (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S)
-#define SPI_WDATA_AFIFO_REMPTY_V  0x00000001U
-#define SPI_WDATA_AFIFO_REMPTY_S  29
-/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1;
- *  1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.
- */
-#define SPI_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define SPI_WBLEN_AFIFO_REMPTY_M  (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S)
-#define SPI_WBLEN_AFIFO_REMPTY_V  0x00000001U
-#define SPI_WBLEN_AFIFO_REMPTY_S  30
-/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1;
- *  This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and
- *  RDATA_AFIFO are empty and spi0_mst_st is IDLE.
- */
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M  (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S)
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x00000001U
-#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
-
-/** SPI_MEM_AXI_ERR_RESP_EN_REG register
- *  SPI0 AXI error response enable register
- */
-#define SPI_MEM_AXI_ERR_RESP_EN_REG(i)  (REG_SPI_MEM_BASE(i) + 0x17c)
-/** SPI_MEM_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0;
- *  Set this bit  to enable AXI response function for mmu valid err in axi write trans.
- */
-#define SPI_MEM_AW_RESP_EN_MMU_VLD    (BIT(0))
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_M  (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S)
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_VLD_S  0
-/** SPI_MEM_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0;
- *  Set this bit  to enable AXI response function for mmu gid err in axi write trans.
- */
-#define SPI_MEM_AW_RESP_EN_MMU_GID    (BIT(1))
-#define SPI_MEM_AW_RESP_EN_MMU_GID_M  (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S)
-#define SPI_MEM_AW_RESP_EN_MMU_GID_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_GID_S  1
-/** SPI_MEM_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0;
- *  Set this bit  to enable AXI response function for axi size err in axi write trans.
- */
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE    (BIT(2))
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M  (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S)
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S  2
-/** SPI_MEM_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0;
- *  Set this bit  to enable AXI response function for axi flash err in axi write trans.
- */
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH    (BIT(3))
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M  (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S)
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S  3
-/** SPI_MEM_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0;
- *  Set this bit  to enable AXI response function for mmu ecc err in axi write trans.
- */
-#define SPI_MEM_AW_RESP_EN_MMU_ECC    (BIT(4))
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_M  (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S)
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_ECC_S  4
-/** SPI_MEM_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0;
- *  Set this bit  to enable AXI response function for mmu sens in err axi write trans.
- */
-#define SPI_MEM_AW_RESP_EN_MMU_SENS    (BIT(5))
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_M  (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S)
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_MMU_SENS_S  5
-/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0;
- *  Set this bit  to enable AXI response function for axi wstrb err in axi write trans.
- */
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB    (BIT(6))
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M  (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S)
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V  0x00000001U
-#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S  6
-/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0;
- *  Set this bit  to enable AXI response function for mmu valid err in axi read trans.
- */
-#define SPI_MEM_AR_RESP_EN_MMU_VLD    (BIT(7))
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_M  (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S)
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_VLD_S  7
-/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0;
- *  Set this bit  to enable AXI response function for mmu gid err in axi read trans.
- */
-#define SPI_MEM_AR_RESP_EN_MMU_GID    (BIT(8))
-#define SPI_MEM_AR_RESP_EN_MMU_GID_M  (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S)
-#define SPI_MEM_AR_RESP_EN_MMU_GID_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_GID_S  8
-/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0;
- *  Set this bit  to enable AXI response function for mmu ecc err in axi read trans.
- */
-#define SPI_MEM_AR_RESP_EN_MMU_ECC    (BIT(9))
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_M  (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S)
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_ECC_S  9
-/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0;
- *  Set this bit  to enable AXI response function for mmu sensitive err in axi read
- *  trans.
- */
-#define SPI_MEM_AR_RESP_EN_MMU_SENS    (BIT(10))
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_M  (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S)
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_MMU_SENS_S  10
-/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0;
- *  Set this bit  to enable AXI response function for axi size err in axi read trans.
- */
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE    (BIT(11))
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M  (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S)
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V  0x00000001U
-#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S  11
-
-/** SPI_MEM_TIMING_CALI_REG register
- *  SPI0 flash timing calibration register
- */
-#define SPI_MEM_TIMING_CALI_REG(i)  (REG_SPI_MEM_BASE(i) + 0x180)
-/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable timing adjust clock for all reading operations.
- */
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S)
-#define SPI_MEM_TIMING_CLK_ENA_V  0x00000001U
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable timing auto-calibration for all reading operations.
- */
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S)
-#define SPI_MEM_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_S  1
-/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0;
- *  add extra dummy spi clock cycle length for spi clock calibration.
- */
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/** SPI_MEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
- *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
- *  flash.
- */
-#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_M  (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S)
-#define SPI_MEM_DLL_TIMING_CALI_V  0x00000001U
-#define SPI_MEM_DLL_TIMING_CALI_S  5
-/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0;
- *  Set this bit to update delay mode, delay num and extra dummy in MSPI.
- */
-#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_M  (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S)
-#define SPI_MEM_TIMING_CALI_UPDATE_V  0x00000001U
-#define SPI_MEM_TIMING_CALI_UPDATE_S  6
-
-/** SPI_MEM_DIN_MODE_REG register
- *  MSPI flash input timing delay mode control register
- */
-#define SPI_MEM_DIN_MODE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x184)
-/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_MEM_DIN0_MODE    0x00000007U
-#define SPI_MEM_DIN0_MODE_M  (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S)
-#define SPI_MEM_DIN0_MODE_V  0x00000007U
-#define SPI_MEM_DIN0_MODE_S  0
-/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_MEM_DIN1_MODE    0x00000007U
-#define SPI_MEM_DIN1_MODE_M  (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S)
-#define SPI_MEM_DIN1_MODE_V  0x00000007U
-#define SPI_MEM_DIN1_MODE_S  3
-/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_MEM_DIN2_MODE    0x00000007U
-#define SPI_MEM_DIN2_MODE_M  (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S)
-#define SPI_MEM_DIN2_MODE_V  0x00000007U
-#define SPI_MEM_DIN2_MODE_S  6
-/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_MEM_DIN3_MODE    0x00000007U
-#define SPI_MEM_DIN3_MODE_M  (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S)
-#define SPI_MEM_DIN3_MODE_V  0x00000007U
-#define SPI_MEM_DIN3_MODE_S  9
-/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk
- */
-#define SPI_MEM_DIN4_MODE    0x00000007U
-#define SPI_MEM_DIN4_MODE_M  (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S)
-#define SPI_MEM_DIN4_MODE_V  0x00000007U
-#define SPI_MEM_DIN4_MODE_S  12
-/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk
- */
-#define SPI_MEM_DIN5_MODE    0x00000007U
-#define SPI_MEM_DIN5_MODE_M  (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S)
-#define SPI_MEM_DIN5_MODE_V  0x00000007U
-#define SPI_MEM_DIN5_MODE_S  15
-/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk
- */
-#define SPI_MEM_DIN6_MODE    0x00000007U
-#define SPI_MEM_DIN6_MODE_M  (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S)
-#define SPI_MEM_DIN6_MODE_V  0x00000007U
-#define SPI_MEM_DIN6_MODE_S  18
-/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk
- */
-#define SPI_MEM_DIN7_MODE    0x00000007U
-#define SPI_MEM_DIN7_MODE_M  (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S)
-#define SPI_MEM_DIN7_MODE_V  0x00000007U
-#define SPI_MEM_DIN7_MODE_S  21
-/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk
- */
-#define SPI_MEM_DINS_MODE    0x00000007U
-#define SPI_MEM_DINS_MODE_M  (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S)
-#define SPI_MEM_DINS_MODE_V  0x00000007U
-#define SPI_MEM_DINS_MODE_S  24
-
-/** SPI_MEM_DIN_NUM_REG register
- *  MSPI flash input timing delay number control register
- */
-#define SPI_MEM_DIN_NUM_REG(i)  (REG_SPI_MEM_BASE(i) + 0x188)
-/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN0_NUM    0x00000003U
-#define SPI_MEM_DIN0_NUM_M  (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S)
-#define SPI_MEM_DIN0_NUM_V  0x00000003U
-#define SPI_MEM_DIN0_NUM_S  0
-/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN1_NUM    0x00000003U
-#define SPI_MEM_DIN1_NUM_M  (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S)
-#define SPI_MEM_DIN1_NUM_V  0x00000003U
-#define SPI_MEM_DIN1_NUM_S  2
-/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN2_NUM    0x00000003U
-#define SPI_MEM_DIN2_NUM_M  (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S)
-#define SPI_MEM_DIN2_NUM_V  0x00000003U
-#define SPI_MEM_DIN2_NUM_S  4
-/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN3_NUM    0x00000003U
-#define SPI_MEM_DIN3_NUM_M  (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S)
-#define SPI_MEM_DIN3_NUM_V  0x00000003U
-#define SPI_MEM_DIN3_NUM_S  6
-/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN4_NUM    0x00000003U
-#define SPI_MEM_DIN4_NUM_M  (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S)
-#define SPI_MEM_DIN4_NUM_V  0x00000003U
-#define SPI_MEM_DIN4_NUM_S  8
-/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN5_NUM    0x00000003U
-#define SPI_MEM_DIN5_NUM_M  (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S)
-#define SPI_MEM_DIN5_NUM_V  0x00000003U
-#define SPI_MEM_DIN5_NUM_S  10
-/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN6_NUM    0x00000003U
-#define SPI_MEM_DIN6_NUM_M  (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S)
-#define SPI_MEM_DIN6_NUM_V  0x00000003U
-#define SPI_MEM_DIN6_NUM_S  12
-/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DIN7_NUM    0x00000003U
-#define SPI_MEM_DIN7_NUM_M  (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S)
-#define SPI_MEM_DIN7_NUM_V  0x00000003U
-#define SPI_MEM_DIN7_NUM_S  14
-/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_MEM_DINS_NUM    0x00000003U
-#define SPI_MEM_DINS_NUM_M  (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S)
-#define SPI_MEM_DINS_NUM_V  0x00000003U
-#define SPI_MEM_DINS_NUM_S  16
-
-/** SPI_MEM_DOUT_MODE_REG register
- *  MSPI flash output timing adjustment control register
- */
-#define SPI_MEM_DOUT_MODE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x18c)
-/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S)
-#define SPI_MEM_DOUT0_MODE_V  0x00000001U
-#define SPI_MEM_DOUT0_MODE_S  0
-/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S)
-#define SPI_MEM_DOUT1_MODE_V  0x00000001U
-#define SPI_MEM_DOUT1_MODE_S  1
-/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S)
-#define SPI_MEM_DOUT2_MODE_V  0x00000001U
-#define SPI_MEM_DOUT2_MODE_S  2
-/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S)
-#define SPI_MEM_DOUT3_MODE_V  0x00000001U
-#define SPI_MEM_DOUT3_MODE_S  3
-/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the spi_clk
- */
-#define SPI_MEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_DOUT4_MODE_M  (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S)
-#define SPI_MEM_DOUT4_MODE_V  0x00000001U
-#define SPI_MEM_DOUT4_MODE_S  4
-/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the spi_clk
- */
-#define SPI_MEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_DOUT5_MODE_M  (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S)
-#define SPI_MEM_DOUT5_MODE_V  0x00000001U
-#define SPI_MEM_DOUT5_MODE_S  5
-/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the spi_clk
- */
-#define SPI_MEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_DOUT6_MODE_M  (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S)
-#define SPI_MEM_DOUT6_MODE_V  0x00000001U
-#define SPI_MEM_DOUT6_MODE_S  6
-/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the spi_clk
- */
-#define SPI_MEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_DOUT7_MODE_M  (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S)
-#define SPI_MEM_DOUT7_MODE_V  0x00000001U
-#define SPI_MEM_DOUT7_MODE_S  7
-/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the spi_clk
- */
-#define SPI_MEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_DOUTS_MODE_M  (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S)
-#define SPI_MEM_DOUTS_MODE_V  0x00000001U
-#define SPI_MEM_DOUTS_MODE_S  8
-
-/** SPI_SMEM_TIMING_CALI_REG register
- *  MSPI external RAM timing calibration register
- */
-#define SPI_SMEM_TIMING_CALI_REG(i)  (REG_SPI_MEM_BASE(i) + 0x190)
-/** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1;
- *  For sram, the bit is used to enable timing adjust clock for all reading operations.
- */
-#define SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_SMEM_TIMING_CLK_ENA_M  (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S)
-#define SPI_SMEM_TIMING_CLK_ENA_V  0x00000001U
-#define SPI_SMEM_TIMING_CLK_ENA_S  0
-/** SPI_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0;
- *  For sram, the bit is used to enable timing auto-calibration for all reading
- *  operations.
- */
-#define SPI_SMEM_TIMING_CALI    (BIT(1))
-#define SPI_SMEM_TIMING_CALI_M  (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S)
-#define SPI_SMEM_TIMING_CALI_V  0x00000001U
-#define SPI_SMEM_TIMING_CALI_S  1
-/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0;
- *  For sram, add extra dummy spi clock cycle length for spi clock calibration.
- */
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007U
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
-#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/** SPI_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0;
- *  Set this bit to enable DLL for timing calibration in DDR mode when accessed to
- *  EXT_RAM.
- */
-#define SPI_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_SMEM_DLL_TIMING_CALI_M  (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S)
-#define SPI_SMEM_DLL_TIMING_CALI_V  0x00000001U
-#define SPI_SMEM_DLL_TIMING_CALI_S  5
-
-/** SPI_SMEM_DIN_MODE_REG register
- *  MSPI external RAM input timing delay mode control register
- */
-#define SPI_SMEM_DIN_MODE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x194)
-/** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN0_MODE    0x00000007U
-#define SPI_SMEM_DIN0_MODE_M  (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S)
-#define SPI_SMEM_DIN0_MODE_V  0x00000007U
-#define SPI_SMEM_DIN0_MODE_S  0
-/** SPI_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN1_MODE    0x00000007U
-#define SPI_SMEM_DIN1_MODE_M  (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S)
-#define SPI_SMEM_DIN1_MODE_V  0x00000007U
-#define SPI_SMEM_DIN1_MODE_S  3
-/** SPI_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN2_MODE    0x00000007U
-#define SPI_SMEM_DIN2_MODE_M  (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S)
-#define SPI_SMEM_DIN2_MODE_V  0x00000007U
-#define SPI_SMEM_DIN2_MODE_S  6
-/** SPI_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN3_MODE    0x00000007U
-#define SPI_SMEM_DIN3_MODE_M  (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S)
-#define SPI_SMEM_DIN3_MODE_V  0x00000007U
-#define SPI_SMEM_DIN3_MODE_S  9
-/** SPI_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN4_MODE    0x00000007U
-#define SPI_SMEM_DIN4_MODE_M  (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S)
-#define SPI_SMEM_DIN4_MODE_V  0x00000007U
-#define SPI_SMEM_DIN4_MODE_S  12
-/** SPI_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN5_MODE    0x00000007U
-#define SPI_SMEM_DIN5_MODE_M  (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S)
-#define SPI_SMEM_DIN5_MODE_V  0x00000007U
-#define SPI_SMEM_DIN5_MODE_S  15
-/** SPI_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN6_MODE    0x00000007U
-#define SPI_SMEM_DIN6_MODE_M  (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S)
-#define SPI_SMEM_DIN6_MODE_V  0x00000007U
-#define SPI_SMEM_DIN6_MODE_S  18
-/** SPI_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DIN7_MODE    0x00000007U
-#define SPI_SMEM_DIN7_MODE_M  (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S)
-#define SPI_SMEM_DIN7_MODE_V  0x00000007U
-#define SPI_SMEM_DIN7_MODE_S  21
-/** SPI_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: input without delayed, 1:
- *  input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input
- *  with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the
- *  spi_clk high edge,  6: input with the spi_clk low edge
- */
-#define SPI_SMEM_DINS_MODE    0x00000007U
-#define SPI_SMEM_DINS_MODE_M  (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S)
-#define SPI_SMEM_DINS_MODE_V  0x00000007U
-#define SPI_SMEM_DINS_MODE_S  24
-
-/** SPI_SMEM_DIN_NUM_REG register
- *  MSPI external RAM input timing delay number control register
- */
-#define SPI_SMEM_DIN_NUM_REG(i)  (REG_SPI_MEM_BASE(i) + 0x198)
-/** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN0_NUM    0x00000003U
-#define SPI_SMEM_DIN0_NUM_M  (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S)
-#define SPI_SMEM_DIN0_NUM_V  0x00000003U
-#define SPI_SMEM_DIN0_NUM_S  0
-/** SPI_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN1_NUM    0x00000003U
-#define SPI_SMEM_DIN1_NUM_M  (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S)
-#define SPI_SMEM_DIN1_NUM_V  0x00000003U
-#define SPI_SMEM_DIN1_NUM_S  2
-/** SPI_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN2_NUM    0x00000003U
-#define SPI_SMEM_DIN2_NUM_M  (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S)
-#define SPI_SMEM_DIN2_NUM_V  0x00000003U
-#define SPI_SMEM_DIN2_NUM_S  4
-/** SPI_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN3_NUM    0x00000003U
-#define SPI_SMEM_DIN3_NUM_M  (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S)
-#define SPI_SMEM_DIN3_NUM_V  0x00000003U
-#define SPI_SMEM_DIN3_NUM_S  6
-/** SPI_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN4_NUM    0x00000003U
-#define SPI_SMEM_DIN4_NUM_M  (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S)
-#define SPI_SMEM_DIN4_NUM_V  0x00000003U
-#define SPI_SMEM_DIN4_NUM_S  8
-/** SPI_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN5_NUM    0x00000003U
-#define SPI_SMEM_DIN5_NUM_M  (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S)
-#define SPI_SMEM_DIN5_NUM_V  0x00000003U
-#define SPI_SMEM_DIN5_NUM_S  10
-/** SPI_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN6_NUM    0x00000003U
-#define SPI_SMEM_DIN6_NUM_M  (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S)
-#define SPI_SMEM_DIN6_NUM_V  0x00000003U
-#define SPI_SMEM_DIN6_NUM_S  12
-/** SPI_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DIN7_NUM    0x00000003U
-#define SPI_SMEM_DIN7_NUM_M  (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S)
-#define SPI_SMEM_DIN7_NUM_V  0x00000003U
-#define SPI_SMEM_DIN7_NUM_S  14
-/** SPI_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0;
- *  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...
- */
-#define SPI_SMEM_DINS_NUM    0x00000003U
-#define SPI_SMEM_DINS_NUM_M  (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S)
-#define SPI_SMEM_DINS_NUM_V  0x00000003U
-#define SPI_SMEM_DINS_NUM_S  16
-
-/** SPI_SMEM_DOUT_MODE_REG register
- *  MSPI external RAM output timing adjustment control register
- */
-#define SPI_SMEM_DOUT_MODE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x19c)
-/** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT0_MODE    (BIT(0))
-#define SPI_SMEM_DOUT0_MODE_M  (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S)
-#define SPI_SMEM_DOUT0_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT0_MODE_S  0
-/** SPI_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT1_MODE    (BIT(1))
-#define SPI_SMEM_DOUT1_MODE_M  (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S)
-#define SPI_SMEM_DOUT1_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT1_MODE_S  1
-/** SPI_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT2_MODE    (BIT(2))
-#define SPI_SMEM_DOUT2_MODE_M  (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S)
-#define SPI_SMEM_DOUT2_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT2_MODE_S  2
-/** SPI_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT3_MODE    (BIT(3))
-#define SPI_SMEM_DOUT3_MODE_M  (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S)
-#define SPI_SMEM_DOUT3_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT3_MODE_S  3
-/** SPI_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT4_MODE    (BIT(4))
-#define SPI_SMEM_DOUT4_MODE_M  (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S)
-#define SPI_SMEM_DOUT4_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT4_MODE_S  4
-/** SPI_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT5_MODE    (BIT(5))
-#define SPI_SMEM_DOUT5_MODE_M  (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S)
-#define SPI_SMEM_DOUT5_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT5_MODE_S  5
-/** SPI_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT6_MODE    (BIT(6))
-#define SPI_SMEM_DOUT6_MODE_M  (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S)
-#define SPI_SMEM_DOUT6_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT6_MODE_S  6
-/** SPI_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUT7_MODE    (BIT(7))
-#define SPI_SMEM_DOUT7_MODE_M  (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S)
-#define SPI_SMEM_DOUT7_MODE_V  0x00000001U
-#define SPI_SMEM_DOUT7_MODE_S  7
-/** SPI_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0;
- *  the output signals are delayed by system clock cycles, 0: output without delayed,
- *  1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- *  output with the posedge of clk_160,4 output with the negedge of clk_160,5: output
- *  with the spi_clk high edge ,6: output with the spi_clk low edge
- */
-#define SPI_SMEM_DOUTS_MODE    (BIT(8))
-#define SPI_SMEM_DOUTS_MODE_M  (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S)
-#define SPI_SMEM_DOUTS_MODE_V  0x00000001U
-#define SPI_SMEM_DOUTS_MODE_S  8
-
-/** SPI_SMEM_AC_REG register
- *  MSPI external RAM ECC and SPI CS timing control register
- */
-#define SPI_SMEM_AC_REG(i)  (REG_SPI_MEM_BASE(i) + 0x1a0)
-/** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0;
- *  For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
- *  disable.
- */
-#define SPI_SMEM_CS_SETUP    (BIT(0))
-#define SPI_SMEM_CS_SETUP_M  (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S)
-#define SPI_SMEM_CS_SETUP_V  0x00000001U
-#define SPI_SMEM_CS_SETUP_S  0
-/** SPI_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0;
- *  For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.
- */
-#define SPI_SMEM_CS_HOLD    (BIT(1))
-#define SPI_SMEM_CS_HOLD_M  (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S)
-#define SPI_SMEM_CS_HOLD_V  0x00000001U
-#define SPI_SMEM_CS_HOLD_S  1
-/** SPI_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1;
- *  For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with
- *  spi_mem_cs_setup bit.
- */
-#define SPI_SMEM_CS_SETUP_TIME    0x0000001FU
-#define SPI_SMEM_CS_SETUP_TIME_M  (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S)
-#define SPI_SMEM_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_SMEM_CS_SETUP_TIME_S  2
-/** SPI_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1;
- *  For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are
- *  combined with spi_mem_cs_hold bit.
- */
-#define SPI_SMEM_CS_HOLD_TIME    0x0000001FU
-#define SPI_SMEM_CS_HOLD_TIME_M  (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S)
-#define SPI_SMEM_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_SMEM_CS_HOLD_TIME_S  7
-/** SPI_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3;
- *  SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold
- *  cycles in ECC mode when accessed external RAM.
- */
-#define SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007U
-#define SPI_SMEM_ECC_CS_HOLD_TIME_M  (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S)
-#define SPI_SMEM_ECC_CS_HOLD_TIME_V  0x00000007U
-#define SPI_SMEM_ECC_CS_HOLD_TIME_S  12
-/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1;
- *  1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when
- *  accesses external RAM.
- */
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S)
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x00000001U
-#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/** SPI_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0;
- *  Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
- *  accesses external RAM.
- */
-#define SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_M  (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S)
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x00000001U
-#define SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
-/** SPI_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0;
- *  These bits are used to set the minimum CS high time tSHSL between SPI burst
- *  transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1)
- *  MSPI core clock cycles.
- */
-#define SPI_SMEM_CS_HOLD_DELAY    0x0000003FU
-#define SPI_SMEM_CS_HOLD_DELAY_M  (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S)
-#define SPI_SMEM_CS_HOLD_DELAY_V  0x0000003FU
-#define SPI_SMEM_CS_HOLD_DELAY_S  25
-/** SPI_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 1;
- *  Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
- *  transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter
- *  whether there is an ECC region or not.
- */
-#define SPI_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define SPI_SMEM_SPLIT_TRANS_EN_M  (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S)
-#define SPI_SMEM_SPLIT_TRANS_EN_V  0x00000001U
-#define SPI_SMEM_SPLIT_TRANS_EN_S  31
-
-/** SPI_MEM_CLOCK_GATE_REG register
- *  SPI0 clock gate register
- */
-#define SPI_MEM_CLOCK_GATE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x200)
-/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Register clock gate enable signal. 1: Enable. 0: Disable.
- */
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
-#define SPI_CLK_EN_V  0x00000001U
-#define SPI_CLK_EN_S  0
-
-/** SPI_MEM_XTS_PLAIN_BASE_REG register
- *  The base address of the memory that stores plaintext in Manual Encryption
- */
-#define SPI_MEM_XTS_PLAIN_BASE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x300)
-/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
- *  This field is only used to generate include file in c case. This field is useless.
- *  Please do not use this field.
- */
-#define SPI_XTS_PLAIN    0xFFFFFFFFU
-#define SPI_XTS_PLAIN_M  (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S)
-#define SPI_XTS_PLAIN_V  0xFFFFFFFFU
-#define SPI_XTS_PLAIN_S  0
-
-/** SPI_MEM_XTS_LINESIZE_REG register
- *  Manual Encryption Line-Size register
- */
-#define SPI_MEM_XTS_LINESIZE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x340)
-/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
- *  This bits stores the line-size parameter which will be used in manual encryption
- *  calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
- *  32-bytes, 2: 64-bytes, 3:reserved.
- */
-#define SPI_XTS_LINESIZE    0x00000003U
-#define SPI_XTS_LINESIZE_M  (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S)
-#define SPI_XTS_LINESIZE_V  0x00000003U
-#define SPI_XTS_LINESIZE_S  0
-
-/** SPI_MEM_XTS_DESTINATION_REG register
- *  Manual Encryption destination register
- */
-#define SPI_MEM_XTS_DESTINATION_REG(i)  (REG_SPI_MEM_BASE(i) + 0x344)
-/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
- *  This bit stores the destination parameter which will be used in manual encryption
- *  calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
- */
-#define SPI_XTS_DESTINATION    (BIT(0))
-#define SPI_XTS_DESTINATION_M  (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S)
-#define SPI_XTS_DESTINATION_V  0x00000001U
-#define SPI_XTS_DESTINATION_S  0
-
-/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register
- *  Manual Encryption physical address register
- */
-#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i)  (REG_SPI_MEM_BASE(i) + 0x348)
-/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
- *  This bits stores the physical-address parameter which will be used in manual
- *  encryption calculation. This value should aligned with byte number decided by
- *  line-size parameter.
- */
-#define SPI_XTS_PHYSICAL_ADDRESS    0x03FFFFFFU
-#define SPI_XTS_PHYSICAL_ADDRESS_M  (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S)
-#define SPI_XTS_PHYSICAL_ADDRESS_V  0x03FFFFFFU
-#define SPI_XTS_PHYSICAL_ADDRESS_S  0
-
-/** SPI_MEM_XTS_TRIGGER_REG register
- *  Manual Encryption physical address register
- */
-#define SPI_MEM_XTS_TRIGGER_REG(i)  (REG_SPI_MEM_BASE(i) + 0x34c)
-/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0;
- *  Set this bit to trigger the process of manual encryption calculation. This action
- *  should only be asserted when manual encryption status is 0. After this action,
- *  manual encryption status becomes 1. After calculation is done, manual encryption
- *  status becomes 2.
- */
-#define SPI_XTS_TRIGGER    (BIT(0))
-#define SPI_XTS_TRIGGER_M  (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S)
-#define SPI_XTS_TRIGGER_V  0x00000001U
-#define SPI_XTS_TRIGGER_S  0
-
-/** SPI_MEM_XTS_RELEASE_REG register
- *  Manual Encryption physical address register
- */
-#define SPI_MEM_XTS_RELEASE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x350)
-/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0;
- *  Set this bit to release encrypted result to mspi. This action should only be
- *  asserted when manual encryption status is 2. After this action, manual encryption
- *  status will become 3.
- */
-#define SPI_XTS_RELEASE    (BIT(0))
-#define SPI_XTS_RELEASE_M  (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S)
-#define SPI_XTS_RELEASE_V  0x00000001U
-#define SPI_XTS_RELEASE_S  0
-
-/** SPI_MEM_XTS_DESTROY_REG register
- *  Manual Encryption physical address register
- */
-#define SPI_MEM_XTS_DESTROY_REG(i)  (REG_SPI_MEM_BASE(i) + 0x354)
-/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0;
- *  Set this bit to destroy encrypted result. This action should be asserted only when
- *  manual encryption status is 3. After this action, manual encryption status will
- *  become 0.
- */
-#define SPI_XTS_DESTROY    (BIT(0))
-#define SPI_XTS_DESTROY_M  (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S)
-#define SPI_XTS_DESTROY_V  0x00000001U
-#define SPI_XTS_DESTROY_S  0
-
-/** SPI_MEM_XTS_STATE_REG register
- *  Manual Encryption physical address register
- */
-#define SPI_MEM_XTS_STATE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x358)
-/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0;
- *  This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
- *  calculation, 2: encryption calculation is done but the encrypted result is
- *  invisible to mspi, 3: the encrypted result is visible to mspi.
- */
-#define SPI_XTS_STATE    0x00000003U
-#define SPI_XTS_STATE_M  (SPI_XTS_STATE_V << SPI_XTS_STATE_S)
-#define SPI_XTS_STATE_V  0x00000003U
-#define SPI_XTS_STATE_S  0
-
-/** SPI_MEM_XTS_DATE_REG register
- *  Manual Encryption version register
- */
-#define SPI_MEM_XTS_DATE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x35c)
-/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176;
- *  This bits stores the last modified-time of manual encryption feature.
- */
-#define SPI_XTS_DATE    0x3FFFFFFFU
-#define SPI_XTS_DATE_M  (SPI_XTS_DATE_V << SPI_XTS_DATE_S)
-#define SPI_XTS_DATE_V  0x3FFFFFFFU
-#define SPI_XTS_DATE_S  0
-
-/** SPI_MEM_MMU_ITEM_CONTENT_REG register
- *  MSPI-MMU item content register
- */
-#define SPI_MEM_MMU_ITEM_CONTENT_REG(i)  (REG_SPI_MEM_BASE(i) + 0x37c)
-/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
- *  MSPI-MMU item content
- */
-#define SPI_MMU_ITEM_CONTENT    0xFFFFFFFFU
-#define SPI_MMU_ITEM_CONTENT_M  (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S)
-#define SPI_MMU_ITEM_CONTENT_V  0xFFFFFFFFU
-#define SPI_MMU_ITEM_CONTENT_S  0
-
-/** SPI_MEM_MMU_ITEM_INDEX_REG register
- *  MSPI-MMU item index register
- */
-#define SPI_MEM_MMU_ITEM_INDEX_REG(i)  (REG_SPI_MEM_BASE(i) + 0x380)
-/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
- *  MSPI-MMU item index
- */
-#define SPI_MMU_ITEM_INDEX    0xFFFFFFFFU
-#define SPI_MMU_ITEM_INDEX_M  (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S)
-#define SPI_MMU_ITEM_INDEX_V  0xFFFFFFFFU
-#define SPI_MMU_ITEM_INDEX_S  0
-
-/** SPI_MEM_MMU_POWER_CTRL_REG register
- *  MSPI MMU power control register
- */
-#define SPI_MEM_MMU_POWER_CTRL_REG(i)  (REG_SPI_MEM_BASE(i) + 0x384)
-/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable mmu-memory clock force on
- */
-#define SPI_MMU_MEM_FORCE_ON    (BIT(0))
-#define SPI_MMU_MEM_FORCE_ON_M  (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S)
-#define SPI_MMU_MEM_FORCE_ON_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_ON_S  0
-/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
- *  Set this bit to force mmu-memory powerdown
- */
-#define SPI_MMU_MEM_FORCE_PD    (BIT(1))
-#define SPI_MMU_MEM_FORCE_PD_M  (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S)
-#define SPI_MMU_MEM_FORCE_PD_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_PD_S  1
-/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
- *  Set this bit to force mmu-memory powerup, in this case, the power should also be
- *  controlled by rtc.
- */
-#define SPI_MMU_MEM_FORCE_PU    (BIT(2))
-#define SPI_MMU_MEM_FORCE_PU_M  (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S)
-#define SPI_MMU_MEM_FORCE_PU_V  0x00000001U
-#define SPI_MMU_MEM_FORCE_PU_S  2
-/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0;
- *  0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8
- */
-#define SPI_MMU_PAGE_SIZE    0x00000003U
-#define SPI_MMU_PAGE_SIZE_M  (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S)
-#define SPI_MMU_PAGE_SIZE_V  0x00000003U
-#define SPI_MMU_PAGE_SIZE_S  3
-/** SPI_MEM_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896;
- *  MMU PSRAM aux control register
- */
-#define SPI_MEM_AUX_CTRL    0x00003FFFU
-#define SPI_MEM_AUX_CTRL_M  (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S)
-#define SPI_MEM_AUX_CTRL_V  0x00003FFFU
-#define SPI_MEM_AUX_CTRL_S  16
-
-/** SPI_MEM_DPA_CTRL_REG register
- *  SPI memory cryption DPA register
- */
-#define SPI_MEM_DPA_CTRL_REG(i)  (REG_SPI_MEM_BASE(i) + 0x388)
-/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
- *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
- *  The bigger the number is, the more secure the cryption is. (Note that the
- *  performance of cryption will decrease together with this number increasing)
- */
-#define SPI_CRYPT_SECURITY_LEVEL    0x00000007U
-#define SPI_CRYPT_SECURITY_LEVEL_M  (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S)
-#define SPI_CRYPT_SECURITY_LEVEL_V  0x00000007U
-#define SPI_CRYPT_SECURITY_LEVEL_S  0
-/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1;
- *  Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the
- *  calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that
- *  using key 1.
- */
-#define SPI_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define SPI_CRYPT_CALC_D_DPA_EN_M  (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S)
-#define SPI_CRYPT_CALC_D_DPA_EN_V  0x00000001U
-#define SPI_CRYPT_CALC_D_DPA_EN_S  3
-/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0;
- *  1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and
- *  SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.
- */
-#define SPI_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define SPI_CRYPT_DPA_SELECT_REGISTER_M  (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S)
-#define SPI_CRYPT_DPA_SELECT_REGISTER_V  0x00000001U
-#define SPI_CRYPT_DPA_SELECT_REGISTER_S  4
-
-/** SPI_MEM_DATE_REG register
- *  SPI0 version control register
- */
-#define SPI_MEM_DATE_REG(i)  (REG_SPI_MEM_BASE(i) + 0x3fc)
-/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36712560;
- *  SPI0 register version.
- */
-#define SPI_MEM_DATE    0x0FFFFFFFU
-#define SPI_MEM_DATE_M  (SPI_MEM_DATE_V << SPI_MEM_DATE_S)
-#define SPI_MEM_DATE_V  0x0FFFFFFFU
-#define SPI_MEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/spi_mem_struct.h b/components/soc/esp32c5/beta3/include/soc/spi_mem_struct.h
deleted file mode 100644
index e1b866f321..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/spi_mem_struct.h
+++ /dev/null
@@ -1,1081 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct spi_mem_dev_s {
-    union {
-        struct {
-            uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
-            uint32_t slv_st                        :    4;  /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
-            uint32_t reserved8                     :    9;  /*reserved*/
-            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t usr                           :    1;  /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
-            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t fdummy_rin                    :    1;  /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/
-            uint32_t fdummy_wout                   :    1;  /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/
-            uint32_t fdout_oct                     :    1;  /*Apply 8 signals during write-data phase 1:enable 0: disable*/
-            uint32_t fdin_oct                      :    1;  /*Apply 8 signals during read-data phase 1:enable 0: disable*/
-            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during address phase 1:enable 0: disable*/
-            uint32_t reserved7                     :    1;  /*reserved*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
-            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable*/
-            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
-            uint32_t reserved12                    :    1;  /*reserved*/
-            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
-            uint32_t reserved16                    :    2;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
-            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
-            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t reserved25                    :    5;  /*reserved*/
-            uint32_t dqs_ie_always_on              :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t data_ie_always_on             :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
-            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
-            uint32_t reserved2                     :    9;  /*reserved*/
-            uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_aw_size0_1_support_en     :    1;  /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_axi_rdata_back_fast       :    1;  /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/
-            uint32_t rresp_ecc_err_en              :    1;  /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/
-            uint32_t ar_splice_en                  :    1;  /*Set this bit to enable AXI Read Splice-transfer.*/
-            uint32_t aw_splice_en                  :    1;  /*Set this bit to enable AXI Write Splice-transfer.*/
-            uint32_t ram0_en                       :    1;  /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t dual_ram_en                   :    1;  /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t fast_write_en                 :    1;  /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.*/
-            uint32_t rxfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.*/
-            uint32_t txfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/
-            uint32_t cs_hold_time                  :    5;  /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/
-            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/
-            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
-            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
-            uint32_t reserved15                    :    9;  /*reserved*/
-            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t sync_reset                    :    1;  /*The spi0_mst_st and spi0_slv_st will be reset.*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
-            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
-            uint32_t clk_equ_sysclk                :    1;  /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
-            uint32_t reserved8                     :    1;  /*reserved*/
-            uint32_t ck_out_edge                   :    1;  /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
-            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
-            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
-            uint32_t reserved16                    :    8;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
-            uint32_t usr_dbytelen                  :    3;  /*SPI0 USR_CMD read or write data byte length -1*/
-            uint32_t reserved9                     :    17;  /*reserved*/
-            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    union {
-        struct {
-            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } rd_status;
-    uint32_t reserved_30;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t reserved0                     :    5;  /*reserved*/
-            uint32_t fsub_pin                      :    1;  /*For SPI0,  flash is connected to SUBPINs.*/
-            uint32_t ssub_pin                      :    1;  /*For SPI0,  sram is connected to SUBPINs.*/
-            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle     0: spi clk line is low when idle */
-            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } misc;
-    uint32_t tx_crc;
-    union {
-        struct {
-            uint32_t axi_req_en                    :    1;  /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
-            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
-            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
-            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t reserved9                     :    21;  /*reserved*/
-            uint32_t reg_same_aw_ar_addr_chk_en    :    1;  /*Set this bit to check AXI read/write the same address region.*/
-            uint32_t reg_close_axi_inf_en          :    1;  /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    union {
-        struct {
-            uint32_t usr_saddr_4byte               :    1;  /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
-            uint32_t usr_sram_dio                  :    1;  /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_sram_qio                  :    1;  /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_wr_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
-            uint32_t usr_rd_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
-            uint32_t sram_usr_rcmd                 :    1;  /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
-            uint32_t sram_rdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved12                    :    2;  /*reserved*/
-            uint32_t sram_addr_bitlen              :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
-            uint32_t sram_usr_wcmd                 :    1;  /*For SPI0, In the external RAM mode cache write sram for user define command*/
-            uint32_t sram_oct                      :    1;  /*reserved*/
-            uint32_t sram_wdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_sctrl;
-    union {
-        struct {
-            uint32_t sclk_mode                     :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
-            uint32_t swb_mode                      :    8;  /*Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t sdin_dual                     :    1;  /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t sdout_dual                    :    1;  /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t saddr_dual                    :    1;  /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t reserved13                    :    1;  /*reserved*/
-            uint32_t sdin_quad                     :    1;  /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdout_quad                    :    1;  /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t saddr_quad                    :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t scmd_quad                     :    1;  /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdin_oct                      :    1;  /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdout_oct                     :    1;  /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t saddr_oct                     :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t scmd_oct                      :    1;  /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdummy_rin                    :    1;  /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t sdummy_wout                   :    1;  /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t reg_smem_wdummy_dqs_always_out:    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t reg_smem_wdummy_always_out    :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t reserved26                    :    4;  /*reserved*/
-            uint32_t reg_smem_dqs_ie_always_on     :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t reg_smem_data_ie_always_on    :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } sram_cmd;
-    union {
-        struct {
-            uint32_t sram_usr_rd_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t sram_usr_rd_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_drd_cmd;
-    union {
-        struct {
-            uint32_t sram_usr_wr_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t sram_usr_wr_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_dwr_cmd;
-    union {
-        struct {
-            uint32_t sclkcnt_l                     :    8;  /*For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.*/
-            uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
-        };
-        uint32_t val;
-    } sram_clk;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;  /*reserved*/
-            uint32_t lock_delay_time               :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } fsm;
-    uint32_t data_buf[16];
-    union {
-        struct {
-            uint32_t waiti_en                      :    1;  /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/
-            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
-            uint32_t waiti_addr_en                 :    1;  /*1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/
-            uint32_t waiti_addr_cyclelen           :    2;  /*When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/
-            uint32_t reserved5                     :    4;  /*reserved*/
-            uint32_t waiti_cmd_2b                  :    1;  /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/
-            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
-            uint32_t waiti_cmd                     :    16;  /*The command value to wait flash idle(RDSR).*/
-        };
-        uint32_t val;
-    } flash_waiti_ctrl;
-    union {
-        struct {
-            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
-            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
-            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
-            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
-            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
-            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
-            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
-        };
-        uint32_t val;
-    } flash_sus_ctrl;
-    union {
-        struct {
-            uint32_t flash_pes_command             :    16;  /*Program/Erase suspend command.*/
-            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
-        };
-        uint32_t val;
-    } flash_sus_cmd;
-    union {
-        struct {
-            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
-            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
-            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
-            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
-            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
-            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
-            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
-            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
-            uint32_t reserved8                     :    7;  /*reserved*/
-            uint32_t flash_pesr_cmd_2b             :    1;  /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/
-            uint32_t flash_per_command             :    16;  /*Program/Erase resume command.*/
-        };
-        uint32_t val;
-    } sus_status;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    union {
-        struct {
-            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject_en                 :    1;  /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err_en           :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
-            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
-            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
-            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
-            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/
-            uint32_t ecc_err                       :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
-            uint32_t pms_reject                    :    1;  /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/
-            uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
-            uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    uint32_t reserved_d0;
-    union {
-        struct {
-            uint32_t reg_fmem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t reg_fmem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t reg_fmem_outminbytelen        :    7;  /*It is the minimum output data length in the panda device.*/
-            uint32_t reg_fmem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
-            uint32_t reg_fmem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/
-            uint32_t reg_fmem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t reg_fmem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t reg_fmem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t reg_fmem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t reg_fmem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t reg_fmem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
-            uint32_t reg_fmem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t reg_fmem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } ddr;
-    union {
-        struct {
-            uint32_t reg_smem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t reg_smem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t reg_smem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t reg_smem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t reg_smem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t reg_smem_outminbytelen        :    7;  /*It is the minimum output data length in the DDR psram.*/
-            uint32_t reg_smem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/
-            uint32_t reg_smem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/
-            uint32_t reg_smem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t reg_smem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t reg_smem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t reg_smem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t reg_smem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t reg_smem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
-            uint32_t reg_smem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t reg_smem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ddr;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms0_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms0_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms1_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms1_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms2_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms2_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms3_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms3_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms0_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms0_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms1_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms1_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms2_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms2_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms3_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms3_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_size;
-    uint32_t reserved_160;
-    union {
-        struct {
-            uint32_t reject_addr                   :    26;  /*This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pm_en                         :    1;  /*Set this bit to enable SPI0/1 transfer permission control function.*/
-            uint32_t reserved27                    :    1;  /*reserved*/
-            uint32_t pms_ld                        :    1;  /*1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_st                        :    1;  /*1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_multi_hit                 :    1;  /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_ivd                       :    1;  /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } pms_reject;
-    union {
-        struct {
-            uint32_t reserved0                     :    11;  /*reserved*/
-            uint32_t ecc_err_int_num               :    6;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t reg_fmem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
-            uint32_t reg_fmem_page_size            :    2;  /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t reg_fmem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t usr_ecc_addr_en               :    1;  /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t ecc_continue_record_err_en    :    1;  /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/
-            uint32_t ecc_err_bits                  :    7;  /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/
-        };
-        uint32_t val;
-    } ecc_ctrl;
-    union {
-        struct {
-            uint32_t ecc_err_addr                  :    26;  /*This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-            uint32_t ecc_err_cnt                   :    6;  /*This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } ecc_err_addr;
-    union {
-        struct {
-            uint32_t axi_err_addr                  :    26;  /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
-            uint32_t all_fifo_empty                :    1;  /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
-            uint32_t reg_rdata_afifo_rempty        :    1;  /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_raddr_afifo_rempty        :    1;  /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_wdata_afifo_rempty        :    1;  /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_wblen_afifo_rempty        :    1;  /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_all_axi_trans_afifo_empty :    1;  /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/
-        };
-        uint32_t val;
-    } axi_err_addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    17;  /*reserved*/
-            uint32_t reg_smem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
-            uint32_t reg_smem_page_size            :    2;  /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t reg_smem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ecc_ctrl;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    union {
-        struct {
-            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/
-            uint32_t timing_cali_update            :    1;  /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/
-            uint32_t reserved7                     :    25;  /*reserved*/
-        };
-        uint32_t val;
-    } timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    union {
-        struct {
-            uint32_t reg_smem_timing_clk_ena       :    1;  /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t reg_smem_timing_cali          :    1;  /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t reg_smem_extra_dummy_cyclelen :    3;  /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t reg_smem_dll_timing_cali      :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_timing_cali;
-    union {
-        struct {
-            uint32_t reg_smem_din0_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din1_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din2_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din3_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din4_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din5_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din6_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din7_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_dins_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_mode;
-    union {
-        struct {
-            uint32_t reg_smem_din0_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din1_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din2_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din3_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din4_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din5_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din6_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din7_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_dins_num             :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_num;
-    union {
-        struct {
-            uint32_t reg_smem_dout0_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout1_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout2_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout3_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout4_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout5_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout6_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout7_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_douts_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_dout_mode;
-    union {
-        struct {
-            uint32_t reg_smem_cs_setup             :    1;  /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
-            uint32_t reg_smem_cs_hold              :    1;  /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
-            uint32_t reg_smem_cs_setup_time        :    5;  /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
-            uint32_t reg_smem_cs_hold_time         :    5;  /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
-            uint32_t reg_smem_ecc_cs_hold_time     :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/
-            uint32_t reg_smem_ecc_skip_page_corner :    1;  /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
-            uint32_t reg_smem_ecc_16to18_byte_en   :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
-            uint32_t reserved17                    :    8;  /*reserved*/
-            uint32_t reg_smem_cs_hold_delay        :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t reg_smem_split_trans_en       :    1;  /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-        };
-        uint32_t val;
-    } spi_smem_ac;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t xts_plain_base;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    union {
-        struct {
-            uint32_t reg_xts_linesize              :    2;  /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_linesize;
-    union {
-        struct {
-            uint32_t reg_xts_destination           :    1;  /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destination;
-    union {
-        struct {
-            uint32_t reg_xts_physical_address      :    26;  /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_physical_address;
-    union {
-        struct {
-            uint32_t reg_xts_trigger               :    1;  /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_trigger;
-    union {
-        struct {
-            uint32_t reg_xts_release               :    1;  /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_release;
-    union {
-        struct {
-            uint32_t reg_xts_destroy               :    1;  /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destroy;
-    union {
-        struct {
-            uint32_t reg_xts_state                 :    2;  /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_state;
-    union {
-        struct {
-            uint32_t reg_xts_date                  :    30;  /*This bits stores the last modified-time of manual encryption feature.*/
-            uint32_t reserved30                    :    2;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_date;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t mmu_item_content;
-    uint32_t mmu_item_index;
-    union {
-        struct {
-            uint32_t reg_mmu_mem_force_on          :    1;  /*Set this bit to enable mmu-memory clock force on*/
-            uint32_t reg_mmu_mem_force_pd          :    1;  /*Set this bit to force mmu-memory powerdown*/
-            uint32_t reg_mmu_mem_force_pu          :    1;  /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/
-            uint32_t reg_mmu_page_size             :    2;  /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
-            uint32_t reserved5                     :    11;  /*reserved*/
-            uint32_t aux_ctrl                      :    14;  /*MMU PSRAM aux control register*/
-            uint32_t rdn_ena                       :    1;  /*ECO register enable bit*/
-            uint32_t rdn_result                    :    1;  /*MSPI module clock domain and AXI clock domain ECO register result register*/
-        };
-        uint32_t val;
-    } mmu_power_ctrl;
-    union {
-        struct {
-            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
-            uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
-            uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } dpa_ctrl;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t spi_memisterrnd_eco_high;
-    uint32_t spi_memisterrnd_eco_low;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI0/1 register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_mem_dev_t;
-
-extern spi_mem_dev_t SPIMEM0;
-extern spi_mem_dev_t SPIMEM1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/spi_pins.h b/components/soc/esp32c5/beta3/include/soc/spi_pins.h
deleted file mode 100644
index 918fc1ef66..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/spi_pins.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-// MSPI pin defined in io_mux_reg.h
-
-// IOMUX pin for GPSPI2
-#define SPI2_FUNC_NUM           2
-#define SPI2_IOMUX_PIN_NUM_MISO 2
-#define SPI2_IOMUX_PIN_NUM_HD   4
-#define SPI2_IOMUX_PIN_NUM_WP   5
-#define SPI2_IOMUX_PIN_NUM_CLK  6
-#define SPI2_IOMUX_PIN_NUM_MOSI 7
-#define SPI2_IOMUX_PIN_NUM_CS   12
diff --git a/components/soc/esp32c5/beta3/include/soc/spi_reg.h b/components/soc/esp32c5/beta3/include/soc/spi_reg.h
deleted file mode 100644
index a778b96d35..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/spi_reg.h
+++ /dev/null
@@ -1,2116 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI_CMD_REG register
- *  Command control register
- */
-#define SPI_CMD_REG (DR_REG_GPSPI2_BASE + 0x0)
-/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
- */
-#define SPI_CONF_BITLEN    0x0003FFFFU
-#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
-#define SPI_CONF_BITLEN_V  0x0003FFFFU
-#define SPI_CONF_BITLEN_S  0
-/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
- *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
- *  clock domain, which is only used in SPI master mode.
- */
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
-#define SPI_UPDATE_V  0x00000001U
-#define SPI_UPDATE_S  23
-/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
- *  User define command enable.  An operation will be triggered when the bit is set.
- *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
- *  changed by CONF_buf.
- */
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
-#define SPI_USR_V  0x00000001U
-#define SPI_USR_S  24
-
-/** SPI_ADDR_REG register
- *  Address value register
- */
-#define SPI_ADDR_REG (DR_REG_GPSPI2_BASE + 0x4)
-/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  Address to slave. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_S  0
-
-/** SPI_CTRL_REG register
- *  SPI control register
- */
-#define SPI_CTRL_REG (DR_REG_GPSPI2_BASE + 0x8)
-/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
- *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
- *  the FSPI bus signals are output. Can be configured in CONF state.
- */
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
-#define SPI_DUMMY_OUT_V  0x00000001U
-#define SPI_DUMMY_OUT_S  3
-/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
- *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
-#define SPI_FADDR_DUAL_V  0x00000001U
-#define SPI_FADDR_DUAL_S  5
-/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
- *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
-#define SPI_FADDR_QUAD_V  0x00000001U
-#define SPI_FADDR_QUAD_S  6
-/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0;
- *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_OCT    (BIT(7))
-#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
-#define SPI_FADDR_OCT_V  0x00000001U
-#define SPI_FADDR_OCT_S  7
-/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
- *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
-#define SPI_FCMD_DUAL_V  0x00000001U
-#define SPI_FCMD_DUAL_S  8
-/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
- *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
-#define SPI_FCMD_QUAD_V  0x00000001U
-#define SPI_FCMD_QUAD_S  9
-/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0;
- *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_OCT    (BIT(10))
-#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
-#define SPI_FCMD_OCT_V  0x00000001U
-#define SPI_FCMD_OCT_S  10
-/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
-#define SPI_FREAD_DUAL_V  0x00000001U
-#define SPI_FREAD_DUAL_S  14
-/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
- *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
-#define SPI_FREAD_QUAD_V  0x00000001U
-#define SPI_FREAD_QUAD_S  15
-/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0;
- *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_OCT    (BIT(16))
-#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
-#define SPI_FREAD_OCT_V  0x00000001U
-#define SPI_FREAD_OCT_S  16
-/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
- *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
-#define SPI_Q_POL_V  0x00000001U
-#define SPI_Q_POL_S  18
-/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
- *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
-#define SPI_D_POL_V  0x00000001U
-#define SPI_D_POL_S  19
-/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
- *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
- *  configured in CONF state.
- */
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
-#define SPI_HOLD_POL_V  0x00000001U
-#define SPI_HOLD_POL_S  20
-/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
- *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
- *  be configured in CONF state.
- */
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
-#define SPI_WP_POL_V  0x00000001U
-#define SPI_WP_POL_S  21
-/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
- *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
- *  state.
- */
-#define SPI_RD_BIT_ORDER    0x00000003U
-#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
-#define SPI_RD_BIT_ORDER_V  0x00000003U
-#define SPI_RD_BIT_ORDER_S  23
-/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
- *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
- *  configured in CONF state.
- */
-#define SPI_WR_BIT_ORDER    0x00000003U
-#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
-#define SPI_WR_BIT_ORDER_V  0x00000003U
-#define SPI_WR_BIT_ORDER_S  25
-
-/** SPI_CLOCK_REG register
- *  SPI clock control register
- */
-#define SPI_CLOCK_REG (DR_REG_GPSPI2_BASE + 0xc)
-/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
- *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
- *  0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_L    0x0000003FU
-#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
-#define SPI_CLKCNT_L_V  0x0000003FU
-#define SPI_CLKCNT_L_S  0
-/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
- *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
- *  must be 0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_H    0x0000003FU
-#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
-#define SPI_CLKCNT_H_V  0x0000003FU
-#define SPI_CLKCNT_H_S  6
-/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
- *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
- *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
- */
-#define SPI_CLKCNT_N    0x0000003FU
-#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
-#define SPI_CLKCNT_N_V  0x0000003FU
-#define SPI_CLKCNT_N_S  12
-/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
- *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
- */
-#define SPI_CLKDIV_PRE    0x0000000FU
-#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
-#define SPI_CLKDIV_PRE_V  0x0000000FU
-#define SPI_CLKDIV_PRE_S  18
-/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
- *  clock. Can be configured in CONF state.
- */
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
-#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_CLK_EQU_SYSCLK_S  31
-
-/** SPI_USER_REG register
- *  SPI USER control register
- */
-#define SPI_USER_REG (DR_REG_GPSPI2_BASE + 0x10)
-/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
- *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
-#define SPI_DOUTDIN_V  0x00000001U
-#define SPI_DOUTDIN_S  0
-/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
- *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
-#define SPI_QPI_MODE_V  0x00000001U
-#define SPI_QPI_MODE_S  3
-/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0;
- *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_OPI_MODE    (BIT(4))
-#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
-#define SPI_OPI_MODE_V  0x00000001U
-#define SPI_OPI_MODE_S  4
-/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
- *  spi_ck_i. 1:tsck = !spi_ck_i.
- */
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
-#define SPI_TSCK_I_EDGE_V  0x00000001U
-#define SPI_TSCK_I_EDGE_S  5
-/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
- *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
-#define SPI_CS_HOLD_V  0x00000001U
-#define SPI_CS_HOLD_S  6
-/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
- *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
-#define SPI_CS_SETUP_V  0x00000001U
-#define SPI_CS_SETUP_S  7
-/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
- *  !spi_ck_i. 1:rsck = spi_ck_i.
- */
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
-#define SPI_RSCK_I_EDGE_V  0x00000001U
-#define SPI_RSCK_I_EDGE_S  8
-/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
- *  be configured in CONF state.
- */
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
-#define SPI_CK_OUT_EDGE_V  0x00000001U
-#define SPI_CK_OUT_EDGE_S  9
-/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
- *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
-#define SPI_FWRITE_DUAL_V  0x00000001U
-#define SPI_FWRITE_DUAL_S  12
-/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
- *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
-#define SPI_FWRITE_QUAD_V  0x00000001U
-#define SPI_FWRITE_QUAD_S  13
-/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0;
- *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_OCT    (BIT(14))
-#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
-#define SPI_FWRITE_OCT_V  0x00000001U
-#define SPI_FWRITE_OCT_S  14
-/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
- *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
- *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
- *  not seg-trans mode. Can be configured in CONF state.
- */
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
-#define SPI_USR_CONF_NXT_V  0x00000001U
-#define SPI_USR_CONF_NXT_S  15
-/** SPI_SIO : R/W; bitpos: [17]; default: 0;
- *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
- *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
- */
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
-#define SPI_SIO_V  0x00000001U
-#define SPI_SIO_S  17
-/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
- *  disable. Can be configured in CONF state.
- */
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
-#define SPI_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_USR_MISO_HIGHPART_S  24
-/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
- *  0: disable.  Can be configured in CONF state.
- */
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
-#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_USR_MOSI_HIGHPART_S  25
-/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
- *  CONF state.
- */
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
-#define SPI_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_USR_DUMMY_IDLE_S  26
-/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
- *  This bit enable the write-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
-#define SPI_USR_MOSI_V  0x00000001U
-#define SPI_USR_MOSI_S  27
-/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
- *  This bit enable the read-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
-#define SPI_USR_MISO_V  0x00000001U
-#define SPI_USR_MISO_S  28
-/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
-#define SPI_USR_DUMMY_V  0x00000001U
-#define SPI_USR_DUMMY_S  29
-/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
- *  This bit enable the address phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
-#define SPI_USR_ADDR_V  0x00000001U
-#define SPI_USR_ADDR_S  30
-/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
- *  This bit enable the command phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
-#define SPI_USR_COMMAND_V  0x00000001U
-#define SPI_USR_COMMAND_S  31
-
-/** SPI_USER1_REG register
- *  SPI USER control register 1
- */
-#define SPI_USER1_REG (DR_REG_GPSPI2_BASE + 0x14)
-/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
- *  The length in spi_clk cycles of dummy phase. The register value shall be
- *  (cycle_num-1). Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
-#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
- *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
- *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
- *  GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
-#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
- *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
- *  bit. Can be configured in CONF state.
- */
-#define SPI_CS_SETUP_TIME    0x0000001FU
-#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
-#define SPI_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_CS_SETUP_TIME_S  17
-/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
- *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
- *  Can be configured in CONF state.
- */
-#define SPI_CS_HOLD_TIME    0x0000001FU
-#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
-#define SPI_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_CS_HOLD_TIME_S  22
-/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
- *  The length in bits of address phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_ADDR_BITLEN    0x0000001FU
-#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
-#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
-#define SPI_USR_ADDR_BITLEN_S  27
-
-/** SPI_USER2_REG register
- *  SPI USER control register 2
- */
-#define SPI_USER2_REG (DR_REG_GPSPI2_BASE + 0x18)
-/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- *  The value of  command. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
-#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_S  0
-/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
- *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
- *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
- *  is valid in GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- *  The length in bits of command phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
-#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_S  28
-
-/** SPI_MS_DLEN_REG register
- *  SPI data bit length control register
- */
-#define SPI_MS_DLEN_REG (DR_REG_GPSPI2_BASE + 0x1c)
-/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  The value of these bits is the configured SPI transmission data bit length in
- *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
- *  the configured bit length in slave mode DMA RX controlled transfer. The register
- *  value shall be (bit_num-1). Can be configured in CONF state.
- */
-#define SPI_MS_DATA_BITLEN    0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
-#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_S  0
-
-/** SPI_MISC_REG register
- *  SPI misc register
- */
-#define SPI_MISC_REG (DR_REG_GPSPI2_BASE + 0x20)
-/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
-#define SPI_CS0_DIS_V  0x00000001U
-#define SPI_CS0_DIS_S  0
-/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
-#define SPI_CS1_DIS_V  0x00000001U
-#define SPI_CS1_DIS_S  1
-/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
-#define SPI_CS2_DIS_V  0x00000001U
-#define SPI_CS2_DIS_S  2
-/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
-#define SPI_CS3_DIS_V  0x00000001U
-#define SPI_CS3_DIS_S  3
-/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
-#define SPI_CS4_DIS_V  0x00000001U
-#define SPI_CS4_DIS_S  4
-/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
-#define SPI_CS5_DIS_V  0x00000001U
-#define SPI_CS5_DIS_S  5
-/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
- *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
- */
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
-#define SPI_CK_DIS_V  0x00000001U
-#define SPI_CK_DIS_S  6
-/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
- *  In the master mode the bits are the polarity of spi cs line, the value is
- *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
- */
-#define SPI_MASTER_CS_POL    0x0000003FU
-#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
-#define SPI_MASTER_CS_POL_V  0x0000003FU
-#define SPI_MASTER_CS_POL_S  7
-/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0;
- *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
- *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
- */
-#define SPI_CLK_DATA_DTR_EN    (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
-#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
-#define SPI_CLK_DATA_DTR_EN_S  16
-/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0;
- *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
- *  Can be configured in CONF state.
- */
-#define SPI_DATA_DTR_EN    (BIT(17))
-#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
-#define SPI_DATA_DTR_EN_V  0x00000001U
-#define SPI_DATA_DTR_EN_S  17
-/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0;
- *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_ADDR_DTR_EN    (BIT(18))
-#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
-#define SPI_ADDR_DTR_EN_V  0x00000001U
-#define SPI_ADDR_DTR_EN_S  18
-/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0;
- *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
- *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_CMD_DTR_EN    (BIT(19))
-#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
-#define SPI_CMD_DTR_EN_V  0x00000001U
-#define SPI_CMD_DTR_EN_S  19
-/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
- *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
- *  CONF state.
- */
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
-#define SPI_SLAVE_CS_POL_V  0x00000001U
-#define SPI_SLAVE_CS_POL_S  23
-/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0;
- *  The default value of spi_dqs. Can be configured in CONF state.
- */
-#define SPI_DQS_IDLE_EDGE    (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
-#define SPI_DQS_IDLE_EDGE_V  0x00000001U
-#define SPI_DQS_IDLE_EDGE_S  24
-/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
- *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
- *  configured in CONF state.
- */
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
-#define SPI_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_CK_IDLE_EDGE_S  29
-/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
- *  spi cs line keep low when the bit is set. Can be configured in CONF state.
- */
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
-#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_CS_KEEP_ACTIVE_S  30
-/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
- *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
- *  spi quad input swap disable. Can be configured in CONF state.
- */
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-
-/** SPI_DIN_MODE_REG register
- *  SPI input delay mode configuration
- */
-#define SPI_DIN_MODE_REG (DR_REG_GPSPI2_BASE + 0x24)
-/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN0_MODE    0x00000003U
-#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
-#define SPI_DIN0_MODE_V  0x00000003U
-#define SPI_DIN0_MODE_S  0
-/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN1_MODE    0x00000003U
-#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
-#define SPI_DIN1_MODE_V  0x00000003U
-#define SPI_DIN1_MODE_S  2
-/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN2_MODE    0x00000003U
-#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
-#define SPI_DIN2_MODE_V  0x00000003U
-#define SPI_DIN2_MODE_S  4
-/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN3_MODE    0x00000003U
-#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
-#define SPI_DIN3_MODE_V  0x00000003U
-#define SPI_DIN3_MODE_S  6
-/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN4_MODE    0x00000003U
-#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
-#define SPI_DIN4_MODE_V  0x00000003U
-#define SPI_DIN4_MODE_S  8
-/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN5_MODE    0x00000003U
-#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
-#define SPI_DIN5_MODE_V  0x00000003U
-#define SPI_DIN5_MODE_S  10
-/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN6_MODE    0x00000003U
-#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
-#define SPI_DIN6_MODE_V  0x00000003U
-#define SPI_DIN6_MODE_S  12
-/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN7_MODE    0x00000003U
-#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
-#define SPI_DIN7_MODE_V  0x00000003U
-#define SPI_DIN7_MODE_S  14
-/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
- *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
- *  state.
- */
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
-#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-
-/** SPI_DIN_NUM_REG register
- *  SPI input delay number configuration
- */
-#define SPI_DIN_NUM_REG (DR_REG_GPSPI2_BASE + 0x28)
-/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN0_NUM    0x00000003U
-#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
-#define SPI_DIN0_NUM_V  0x00000003U
-#define SPI_DIN0_NUM_S  0
-/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN1_NUM    0x00000003U
-#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
-#define SPI_DIN1_NUM_V  0x00000003U
-#define SPI_DIN1_NUM_S  2
-/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN2_NUM    0x00000003U
-#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
-#define SPI_DIN2_NUM_V  0x00000003U
-#define SPI_DIN2_NUM_S  4
-/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN3_NUM    0x00000003U
-#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
-#define SPI_DIN3_NUM_V  0x00000003U
-#define SPI_DIN3_NUM_S  6
-/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN4_NUM    0x00000003U
-#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
-#define SPI_DIN4_NUM_V  0x00000003U
-#define SPI_DIN4_NUM_S  8
-/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN5_NUM    0x00000003U
-#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
-#define SPI_DIN5_NUM_V  0x00000003U
-#define SPI_DIN5_NUM_S  10
-/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN6_NUM    0x00000003U
-#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
-#define SPI_DIN6_NUM_V  0x00000003U
-#define SPI_DIN6_NUM_S  12
-/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN7_NUM    0x00000003U
-#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
-#define SPI_DIN7_NUM_V  0x00000003U
-#define SPI_DIN7_NUM_S  14
-
-/** SPI_DOUT_MODE_REG register
- *  SPI output delay mode configuration
- */
-#define SPI_DOUT_MODE_REG (DR_REG_GPSPI2_BASE + 0x2c)
-/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
-#define SPI_DOUT0_MODE_V  0x00000001U
-#define SPI_DOUT0_MODE_S  0
-/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
-#define SPI_DOUT1_MODE_V  0x00000001U
-#define SPI_DOUT1_MODE_S  1
-/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
-#define SPI_DOUT2_MODE_V  0x00000001U
-#define SPI_DOUT2_MODE_S  2
-/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
-#define SPI_DOUT3_MODE_V  0x00000001U
-#define SPI_DOUT3_MODE_S  3
-/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT4_MODE    (BIT(4))
-#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
-#define SPI_DOUT4_MODE_V  0x00000001U
-#define SPI_DOUT4_MODE_S  4
-/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT5_MODE    (BIT(5))
-#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
-#define SPI_DOUT5_MODE_V  0x00000001U
-#define SPI_DOUT5_MODE_S  5
-/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT6_MODE    (BIT(6))
-#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
-#define SPI_DOUT6_MODE_V  0x00000001U
-#define SPI_DOUT6_MODE_S  6
-/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT7_MODE    (BIT(7))
-#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
-#define SPI_DOUT7_MODE_V  0x00000001U
-#define SPI_DOUT7_MODE_S  7
-/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0;
- *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
- *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_D_DQS_MODE    (BIT(8))
-#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
-#define SPI_D_DQS_MODE_V  0x00000001U
-#define SPI_D_DQS_MODE_S  8
-
-/** SPI_DMA_CONF_REG register
- *  SPI DMA control register
- */
-#define SPI_DMA_CONF_REG (DR_REG_GPSPI2_BASE + 0x30)
-/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
- *  DMA TX FIFO is ready for sending data.
- */
-#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
-#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_S  0
-/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
- *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
- *  0: DMA RX FIFO is ready for receiving data.
- */
-#define SPI_DMA_INFIFO_FULL    (BIT(1))
-#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
-#define SPI_DMA_INFIFO_FULL_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_S  1
-/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
- *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
- */
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
- *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
- *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
- *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
- *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
- *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
- *  spi_dma_seg_trans_done in seg-trans.
- */
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
-#define SPI_RX_EOF_EN_V  0x00000001U
-#define SPI_RX_EOF_EN_S  21
-/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
- *  Set this bit to enable SPI DMA controlled receive data mode.
- */
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
-#define SPI_DMA_RX_ENA_V  0x00000001U
-#define SPI_DMA_RX_ENA_S  27
-/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
- *  Set this bit to enable SPI DMA controlled send data mode.
- */
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
-#define SPI_DMA_TX_ENA_V  0x00000001U
-#define SPI_DMA_TX_ENA_S  28
-/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
- *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
- *  slave mode transfer.
- */
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
-#define SPI_RX_AFIFO_RST_V  0x00000001U
-#define SPI_RX_AFIFO_RST_S  29
-/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
- *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
- *  controlled mode transfer and master mode transfer.
- */
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
-#define SPI_BUF_AFIFO_RST_V  0x00000001U
-#define SPI_BUF_AFIFO_RST_S  30
-/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
- *  controlled mode transfer.
- */
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
-#define SPI_DMA_AFIFO_RST_V  0x00000001U
-#define SPI_DMA_AFIFO_RST_S  31
-
-/** SPI_DMA_INT_ENA_REG register
- *  SPI interrupt enable register
- */
-#define SPI_DMA_INT_ENA_REG (DR_REG_GPSPI2_BASE + 0x34)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
-#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
-#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
-#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
-#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The enable bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
-#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  The enable bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
-#define SPI_APP2_INT_ENA_V  0x00000001U
-#define SPI_APP2_INT_ENA_S  19
-/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  The enable bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
-#define SPI_APP1_INT_ENA_V  0x00000001U
-#define SPI_APP1_INT_ENA_S  20
-
-/** SPI_DMA_INT_CLR_REG register
- *  SPI interrupt clear register
- */
-#define SPI_DMA_INT_CLR_REG (DR_REG_GPSPI2_BASE + 0x38)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
-#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The clear bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
-#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The clear bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
-#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The clear bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
-#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
- *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
- *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  The clear bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
-#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
- *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
- *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
- *  The clear bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
-#define SPI_APP2_INT_CLR_V  0x00000001U
-#define SPI_APP2_INT_CLR_S  19
-/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  The clear bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
-#define SPI_APP1_INT_CLR_V  0x00000001U
-#define SPI_APP1_INT_CLR_S  20
-
-/** SPI_DMA_INT_RAW_REG register
- *  SPI interrupt raw register
- */
-#define SPI_DMA_INT_RAW_REG (DR_REG_GPSPI2_BASE + 0x3c)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
- *  receive data.  0: Others.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
- *  master mode and send out all 0 in slave mode.  0: Others.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
-#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
-#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
-#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
-#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
- *  ended. 0: others.
- */
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
-#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
- *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
- *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
- *  is not ended or not occurred.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
- *  is error in the DMA seg-conf-trans. 0: others.
- */
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
- *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
- *  bigger than 63. 0: Others.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
- *  current SPI slave HD mode transmission is not supported. 0: Others.
- */
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
- *  write-full error when SPI inputs data in master mode. 0: Others.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
- *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
-#define SPI_APP2_INT_RAW_V  0x00000001U
-#define SPI_APP2_INT_RAW_S  19
-/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
-#define SPI_APP1_INT_RAW_V  0x00000001U
-#define SPI_APP1_INT_RAW_S  20
-
-/** SPI_DMA_INT_ST_REG register
- *  SPI interrupt status register
- */
-#define SPI_DMA_INT_ST_REG (DR_REG_GPSPI2_BASE + 0x40)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
-#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
-#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
-#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ST_S  4
-/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
- *  The status bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
-#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ST_S  5
-/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
- *  The status bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
-#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ST_S  6
-/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
- *  The status bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
-#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ST_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
- *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
- *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
- *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  The status bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
-#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ST_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
- *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
- *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
- *  The status bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
-#define SPI_APP2_INT_ST_V  0x00000001U
-#define SPI_APP2_INT_ST_S  19
-/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
- *  The status bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
-#define SPI_APP1_INT_ST_V  0x00000001U
-#define SPI_APP1_INT_ST_S  20
-
-/** SPI_DMA_INT_SET_REG register
- *  SPI interrupt software set register
- */
-#define SPI_DMA_INT_SET_REG (DR_REG_GPSPI2_BASE + 0x44)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
- *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
- *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
-/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
- *  The software set bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
-#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_SET_S  2
-/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
- *  The software set bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
-#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_SET_S  3
-/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
- *  The software set bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_SET    (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
-#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD7_INT_SET_S  4
-/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
- *  The software set bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_SET    (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
-#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD8_INT_SET_S  5
-/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
- *  The software set bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_SET    (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
-#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD9_INT_SET_S  6
-/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
- *  The software set bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_SET    (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
-#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
-#define SPI_SLV_CMDA_INT_SET_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
- *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
-#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
- *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
-#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
- *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
-#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
- *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
-#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
-/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
- *  The software set bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_SET    (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
-#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_TRANS_DONE_INT_SET_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
- *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
-/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
- *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
-#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
- *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
-/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
- *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
-#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_SET_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
- *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
- *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
-/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
- *  The software set bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_SET    (BIT(19))
-#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
-#define SPI_APP2_INT_SET_V  0x00000001U
-#define SPI_APP2_INT_SET_S  19
-/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
- *  The software set bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_SET    (BIT(20))
-#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
-#define SPI_APP1_INT_SET_V  0x00000001U
-#define SPI_APP1_INT_SET_S  20
-
-/** SPI_W0_REG register
- *  SPI CPU-controlled buffer0
- */
-#define SPI_W0_REG (DR_REG_GPSPI2_BASE + 0x98)
-/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF0    0xFFFFFFFFU
-#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
-#define SPI_BUF0_V  0xFFFFFFFFU
-#define SPI_BUF0_S  0
-
-/** SPI_W1_REG register
- *  SPI CPU-controlled buffer1
- */
-#define SPI_W1_REG (DR_REG_GPSPI2_BASE + 0x9c)
-/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF1    0xFFFFFFFFU
-#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
-#define SPI_BUF1_V  0xFFFFFFFFU
-#define SPI_BUF1_S  0
-
-/** SPI_W2_REG register
- *  SPI CPU-controlled buffer2
- */
-#define SPI_W2_REG (DR_REG_GPSPI2_BASE + 0xa0)
-/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF2    0xFFFFFFFFU
-#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
-#define SPI_BUF2_V  0xFFFFFFFFU
-#define SPI_BUF2_S  0
-
-/** SPI_W3_REG register
- *  SPI CPU-controlled buffer3
- */
-#define SPI_W3_REG (DR_REG_GPSPI2_BASE + 0xa4)
-/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF3    0xFFFFFFFFU
-#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
-#define SPI_BUF3_V  0xFFFFFFFFU
-#define SPI_BUF3_S  0
-
-/** SPI_W4_REG register
- *  SPI CPU-controlled buffer4
- */
-#define SPI_W4_REG (DR_REG_GPSPI2_BASE + 0xa8)
-/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF4    0xFFFFFFFFU
-#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
-#define SPI_BUF4_V  0xFFFFFFFFU
-#define SPI_BUF4_S  0
-
-/** SPI_W5_REG register
- *  SPI CPU-controlled buffer5
- */
-#define SPI_W5_REG (DR_REG_GPSPI2_BASE + 0xac)
-/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF5    0xFFFFFFFFU
-#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
-#define SPI_BUF5_V  0xFFFFFFFFU
-#define SPI_BUF5_S  0
-
-/** SPI_W6_REG register
- *  SPI CPU-controlled buffer6
- */
-#define SPI_W6_REG (DR_REG_GPSPI2_BASE + 0xb0)
-/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF6    0xFFFFFFFFU
-#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
-#define SPI_BUF6_V  0xFFFFFFFFU
-#define SPI_BUF6_S  0
-
-/** SPI_W7_REG register
- *  SPI CPU-controlled buffer7
- */
-#define SPI_W7_REG (DR_REG_GPSPI2_BASE + 0xb4)
-/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF7    0xFFFFFFFFU
-#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
-#define SPI_BUF7_V  0xFFFFFFFFU
-#define SPI_BUF7_S  0
-
-/** SPI_W8_REG register
- *  SPI CPU-controlled buffer8
- */
-#define SPI_W8_REG (DR_REG_GPSPI2_BASE + 0xb8)
-/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF8    0xFFFFFFFFU
-#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
-#define SPI_BUF8_V  0xFFFFFFFFU
-#define SPI_BUF8_S  0
-
-/** SPI_W9_REG register
- *  SPI CPU-controlled buffer9
- */
-#define SPI_W9_REG (DR_REG_GPSPI2_BASE + 0xbc)
-/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF9    0xFFFFFFFFU
-#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
-#define SPI_BUF9_V  0xFFFFFFFFU
-#define SPI_BUF9_S  0
-
-/** SPI_W10_REG register
- *  SPI CPU-controlled buffer10
- */
-#define SPI_W10_REG (DR_REG_GPSPI2_BASE + 0xc0)
-/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF10    0xFFFFFFFFU
-#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
-#define SPI_BUF10_V  0xFFFFFFFFU
-#define SPI_BUF10_S  0
-
-/** SPI_W11_REG register
- *  SPI CPU-controlled buffer11
- */
-#define SPI_W11_REG (DR_REG_GPSPI2_BASE + 0xc4)
-/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF11    0xFFFFFFFFU
-#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
-#define SPI_BUF11_V  0xFFFFFFFFU
-#define SPI_BUF11_S  0
-
-/** SPI_W12_REG register
- *  SPI CPU-controlled buffer12
- */
-#define SPI_W12_REG (DR_REG_GPSPI2_BASE + 0xc8)
-/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF12    0xFFFFFFFFU
-#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
-#define SPI_BUF12_V  0xFFFFFFFFU
-#define SPI_BUF12_S  0
-
-/** SPI_W13_REG register
- *  SPI CPU-controlled buffer13
- */
-#define SPI_W13_REG (DR_REG_GPSPI2_BASE + 0xcc)
-/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF13    0xFFFFFFFFU
-#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
-#define SPI_BUF13_V  0xFFFFFFFFU
-#define SPI_BUF13_S  0
-
-/** SPI_W14_REG register
- *  SPI CPU-controlled buffer14
- */
-#define SPI_W14_REG (DR_REG_GPSPI2_BASE + 0xd0)
-/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF14    0xFFFFFFFFU
-#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
-#define SPI_BUF14_V  0xFFFFFFFFU
-#define SPI_BUF14_S  0
-
-/** SPI_W15_REG register
- *  SPI CPU-controlled buffer15
- */
-#define SPI_W15_REG (DR_REG_GPSPI2_BASE + 0xd4)
-/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF15    0xFFFFFFFFU
-#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
-#define SPI_BUF15_V  0xFFFFFFFFU
-#define SPI_BUF15_S  0
-
-/** SPI_SLAVE_REG register
- *  SPI slave control register
- */
-#define SPI_SLAVE_REG (DR_REG_GPSPI2_BASE + 0xe0)
-/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
- *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on. Can be configured in CONF state.
- */
-#define SPI_CLK_MODE    0x00000003U
-#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
-#define SPI_CLK_MODE_V  0x00000003U
-#define SPI_CLK_MODE_S  0
-/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
- *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
- *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
- */
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
-#define SPI_CLK_MODE_13_V  0x00000001U
-#define SPI_CLK_MODE_13_S  2
-/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
- *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
- *  0: output data at tsck posedge
- */
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
-#define SPI_RSCK_DATA_OUT_V  0x00000001U
-#define SPI_RSCK_DATA_OUT_S  3
-/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  DMA controlled mode(Rd_DMA). 0: others
- */
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in DMA controlled mode(Wr_DMA). 0: others
- */
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  CPU controlled mode(Rd_BUF). 0: others
- */
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in CPU controlled mode(Wr_BUF). 0: others
- */
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0;
- *  Represents the effective bit of the last received data byte in SPI slave FD and HD
- *  mode.
- */
-#define SPI_SLV_LAST_BYTE_STRB    0x000000FFU
-#define SPI_SLV_LAST_BYTE_STRB_M  (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S)
-#define SPI_SLV_LAST_BYTE_STRB_V  0x000000FFU
-#define SPI_SLV_LAST_BYTE_STRB_S  12
-/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
- *  The magic value of BM table in master DMA seg-trans.
- */
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
- *  Set SPI work mode. 1: slave mode 0: master mode.
- */
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
-#define SPI_SLAVE_MODE_V  0x00000001U
-#define SPI_SLAVE_MODE_S  26
-/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
- *  Software reset enable, reset the spi clock line cs line and data lines. Can be
- *  configured in CONF state.
- */
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
-#define SPI_SOFT_RESET_V  0x00000001U
-#define SPI_SOFT_RESET_S  27
-/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
- *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
- *  will start. 0: This is not seg-trans mode.
- */
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
-#define SPI_USR_CONF_V  0x00000001U
-#define SPI_USR_CONF_S  28
-/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
- *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
- *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
- *  transfer.
- */
-#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
-
-/** SPI_SLAVE1_REG register
- *  SPI slave control register 1
- */
-#define SPI_SLAVE1_REG (DR_REG_GPSPI2_BASE + 0xe4)
-/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
- *  The transferred data bit length in SPI slave FD and HD mode.
- */
-#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
-#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_S  0
-/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
- *  In the slave mode it is the value of command.
- */
-#define SPI_SLV_LAST_COMMAND    0x000000FFU
-#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
-#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
-#define SPI_SLV_LAST_COMMAND_S  18
-/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
- *  In the slave mode it is the value of address.
- */
-#define SPI_SLV_LAST_ADDR    0x0000003FU
-#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
-#define SPI_SLV_LAST_ADDR_V  0x0000003FU
-#define SPI_SLV_LAST_ADDR_S  26
-
-/** SPI_CLK_GATE_REG register
- *  SPI module clock and register clock control
- */
-#define SPI_CLK_GATE_REG (DR_REG_GPSPI2_BASE + 0xe8)
-/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable clk gate
- */
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
-#define SPI_CLK_EN_V  0x00000001U
-#define SPI_CLK_EN_S  0
-/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
- *  Set this bit to power on the SPI module clock.
- */
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
-#define SPI_MST_CLK_ACTIVE_V  0x00000001U
-#define SPI_MST_CLK_ACTIVE_S  1
-/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
- *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
- *  0: XTAL CLK.
- */
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
-#define SPI_MST_CLK_SEL_V  0x00000001U
-#define SPI_MST_CLK_SEL_S  2
-
-/** SPI_DATE_REG register
- *  Version control
- */
-#define SPI_DATE_REG (DR_REG_GPSPI2_BASE + 0xf0)
-/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931;
- *  SPI register version.
- */
-#define SPI_DATE    0x0FFFFFFFU
-#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
-#define SPI_DATE_V  0x0FFFFFFFU
-#define SPI_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/spi_struct.h b/components/soc/esp32c5/beta3/include/soc/spi_struct.h
deleted file mode 100644
index b9fdba155a..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/spi_struct.h
+++ /dev/null
@@ -1,1405 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: User-defined control registers */
-/** Type of cmd register
- *  Command control register
- */
-typedef union {
-    struct {
-        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
-         */
-        uint32_t conf_bitlen:18;
-        uint32_t reserved_18:5;
-        /** update : WT; bitpos: [23]; default: 0;
-         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
-         *  clock domain, which is only used in SPI master mode.
-         */
-        uint32_t update:1;
-        /** usr : R/W/SC; bitpos: [24]; default: 0;
-         *  User define command enable.  An operation will be triggered when the bit is set.
-         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
-         *  changed by CONF_buf.
-         */
-        uint32_t usr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} spi_cmd_reg_t;
-
-/** Type of addr register
- *  Address value register
- */
-typedef union {
-    struct {
-        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
-         *  Address to slave. Can be configured in CONF state.
-         */
-        uint32_t usr_addr_value:32;
-    };
-    uint32_t val;
-} spi_addr_reg_t;
-
-/** Type of user register
- *  SPI USER control register
- */
-typedef union {
-    struct {
-        /** doutdin : R/W; bitpos: [0]; default: 0;
-         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t doutdin:1;
-        uint32_t reserved_1:2;
-        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
-         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t qpi_mode:1;
-        /** opi_mode : HRO; bitpos: [4]; default: 0;
-         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t opi_mode:1;
-        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
-         *  spi_ck_i. 1:tsck = !spi_ck_i.
-         */
-        uint32_t tsck_i_edge:1;
-        /** cs_hold : R/W; bitpos: [6]; default: 1;
-         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_hold:1;
-        /** cs_setup : R/W; bitpos: [7]; default: 1;
-         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_setup:1;
-        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
-         *  !spi_ck_i. 1:rsck = spi_ck_i.
-         */
-        uint32_t rsck_i_edge:1;
-        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
-         *  be configured in CONF state.
-         */
-        uint32_t ck_out_edge:1;
-        uint32_t reserved_10:2;
-        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
-         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_dual:1;
-        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
-         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_quad:1;
-        /** fwrite_oct : HRO; bitpos: [14]; default: 0;
-         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_oct:1;
-        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
-         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
-         *  not seg-trans mode. Can be configured in CONF state.
-         */
-        uint32_t usr_conf_nxt:1;
-        uint32_t reserved_16:1;
-        /** sio : R/W; bitpos: [17]; default: 0;
-         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
-         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
-         */
-        uint32_t sio:1;
-        uint32_t reserved_18:6;
-        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
-         *  disable. Can be configured in CONF state.
-         */
-        uint32_t usr_miso_highpart:1;
-        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
-         *  0: disable.  Can be configured in CONF state.
-         */
-        uint32_t usr_mosi_highpart:1;
-        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
-         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
-         *  CONF state.
-         */
-        uint32_t usr_dummy_idle:1;
-        /** usr_mosi : R/W; bitpos: [27]; default: 0;
-         *  This bit enable the write-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_mosi:1;
-        /** usr_miso : R/W; bitpos: [28]; default: 0;
-         *  This bit enable the read-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_miso:1;
-        /** usr_dummy : R/W; bitpos: [29]; default: 0;
-         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_dummy:1;
-        /** usr_addr : R/W; bitpos: [30]; default: 0;
-         *  This bit enable the address phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_addr:1;
-        /** usr_command : R/W; bitpos: [31]; default: 1;
-         *  This bit enable the command phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_command:1;
-    };
-    uint32_t val;
-} spi_user_reg_t;
-
-/** Type of user1 register
- *  SPI USER control register 1
- */
-typedef union {
-    struct {
-        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
-         *  The length in spi_clk cycles of dummy phase. The register value shall be
-         *  (cycle_num-1). Can be configured in CONF state.
-         */
-        uint32_t usr_dummy_cyclelen:8;
-        uint32_t reserved_8:8;
-        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
-         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
-         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
-         *  GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_wfull_err_end_en:1;
-        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
-         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
-         *  bit. Can be configured in CONF state.
-         */
-        uint32_t cs_setup_time:5;
-        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
-         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_hold_time:5;
-        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
-         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_addr_bitlen:5;
-    };
-    uint32_t val;
-} spi_user1_reg_t;
-
-/** Type of user2 register
- *  SPI USER control register 2
- */
-typedef union {
-    struct {
-        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
-         *  The value of  command. Can be configured in CONF state.
-         */
-        uint32_t usr_command_value:16;
-        uint32_t reserved_16:11;
-        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
-         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
-         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
-         *  is valid in GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_rempty_err_end_en:1;
-        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
-         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_command_bitlen:4;
-    };
-    uint32_t val;
-} spi_user2_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of ctrl register
- *  SPI control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** dummy_out : R/W; bitpos: [3]; default: 0;
-         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
-         *  the FSPI bus signals are output. Can be configured in CONF state.
-         */
-        uint32_t dummy_out:1;
-        uint32_t reserved_4:1;
-        /** faddr_dual : R/W; bitpos: [5]; default: 0;
-         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_dual:1;
-        /** faddr_quad : R/W; bitpos: [6]; default: 0;
-         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_quad:1;
-        /** faddr_oct : HRO; bitpos: [7]; default: 0;
-         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_oct:1;
-        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
-         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_dual:1;
-        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
-         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_quad:1;
-        /** fcmd_oct : HRO; bitpos: [10]; default: 0;
-         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_oct:1;
-        uint32_t reserved_11:3;
-        /** fread_dual : R/W; bitpos: [14]; default: 0;
-         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_dual:1;
-        /** fread_quad : R/W; bitpos: [15]; default: 0;
-         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_quad:1;
-        /** fread_oct : HRO; bitpos: [16]; default: 0;
-         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_oct:1;
-        uint32_t reserved_17:1;
-        /** q_pol : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t q_pol:1;
-        /** d_pol : R/W; bitpos: [19]; default: 1;
-         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t d_pol:1;
-        /** hold_pol : R/W; bitpos: [20]; default: 1;
-         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
-         *  configured in CONF state.
-         */
-        uint32_t hold_pol:1;
-        /** wp_pol : R/W; bitpos: [21]; default: 1;
-         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t wp_pol:1;
-        uint32_t reserved_22:1;
-        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
-         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
-         *  state.
-         */
-        uint32_t rd_bit_order:2;
-        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
-         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
-         *  configured in CONF state.
-         */
-        uint32_t wr_bit_order:2;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} spi_ctrl_reg_t;
-
-/** Type of ms_dlen register
- *  SPI data bit length control register
- */
-typedef union {
-    struct {
-        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  The value of these bits is the configured SPI transmission data bit length in
-         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
-         *  the configured bit length in slave mode DMA RX controlled transfer. The register
-         *  value shall be (bit_num-1). Can be configured in CONF state.
-         */
-        uint32_t ms_data_bitlen:18;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} spi_ms_dlen_reg_t;
-
-/** Type of misc register
- *  SPI misc register
- */
-typedef union {
-    struct {
-        /** cs0_dis : R/W; bitpos: [0]; default: 0;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs0_dis:1;
-        /** cs1_dis : R/W; bitpos: [1]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs1_dis:1;
-        /** cs2_dis : R/W; bitpos: [2]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs2_dis:1;
-        /** cs3_dis : R/W; bitpos: [3]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs3_dis:1;
-        /** cs4_dis : R/W; bitpos: [4]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs4_dis:1;
-        /** cs5_dis : R/W; bitpos: [5]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs5_dis:1;
-        /** ck_dis : R/W; bitpos: [6]; default: 0;
-         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
-         */
-        uint32_t ck_dis:1;
-        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
-         *  In the master mode the bits are the polarity of spi cs line, the value is
-         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-         */
-        uint32_t master_cs_pol:6;
-        uint32_t reserved_13:3;
-        /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0;
-         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
-         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
-         */
-        uint32_t clk_data_dtr_en:1;
-        /** data_dtr_en : HRO; bitpos: [17]; default: 0;
-         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
-         *  Can be configured in CONF state.
-         */
-        uint32_t data_dtr_en:1;
-        /** addr_dtr_en : HRO; bitpos: [18]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t addr_dtr_en:1;
-        /** cmd_dtr_en : HRO; bitpos: [19]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
-         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cmd_dtr_en:1;
-        uint32_t reserved_20:3;
-        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
-         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-         *  CONF state.
-         */
-        uint32_t slave_cs_pol:1;
-        /** dqs_idle_edge : HRO; bitpos: [24]; default: 0;
-         *  The default value of spi_dqs. Can be configured in CONF state.
-         */
-        uint32_t dqs_idle_edge:1;
-        uint32_t reserved_25:4;
-        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
-         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
-         *  configured in CONF state.
-         */
-        uint32_t ck_idle_edge:1;
-        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
-         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
-         */
-        uint32_t cs_keep_active:1;
-        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
-         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
-         *  spi quad input swap disable. Can be configured in CONF state.
-         */
-        uint32_t quad_din_pin_swap:1;
-    };
-    uint32_t val;
-} spi_misc_reg_t;
-
-/** Type of dma_conf register
- *  SPI DMA control register
- */
-typedef union {
-    struct {
-        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
-         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
-         *  DMA TX FIFO is ready for sending data.
-         */
-        uint32_t dma_outfifo_empty:1;
-        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
-         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
-         *  0: DMA RX FIFO is ready for receiving data.
-         */
-        uint32_t dma_infifo_full:1;
-        uint32_t reserved_2:16;
-        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
-         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-         */
-        uint32_t dma_slv_seg_trans_en:1;
-        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
-         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
-         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_rx_seg_trans_clr_en:1;
-        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
-         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
-         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_tx_seg_trans_clr_en:1;
-        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
-         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
-         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
-         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
-         *  spi_dma_seg_trans_done in seg-trans.
-         */
-        uint32_t rx_eof_en:1;
-        uint32_t reserved_22:5;
-        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
-         *  Set this bit to enable SPI DMA controlled receive data mode.
-         */
-        uint32_t dma_rx_ena:1;
-        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to enable SPI DMA controlled send data mode.
-         */
-        uint32_t dma_tx_ena:1;
-        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
-         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-         *  slave mode transfer.
-         */
-        uint32_t rx_afifo_rst:1;
-        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
-         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
-         *  controlled mode transfer and master mode transfer.
-         */
-        uint32_t buf_afifo_rst:1;
-        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
-         *  controlled mode transfer.
-         */
-        uint32_t dma_afifo_rst:1;
-    };
-    uint32_t val;
-} spi_dma_conf_reg_t;
-
-/** Type of slave register
- *  SPI slave control register
- */
-typedef union {
-    struct {
-        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
-         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
-         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on. Can be configured in CONF state.
-         */
-        uint32_t clk_mode:2;
-        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
-         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
-         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-         */
-        uint32_t clk_mode_13:1;
-        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
-         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
-         *  0: output data at tsck posedge
-         */
-        uint32_t rsck_data_out:1;
-        uint32_t reserved_4:4;
-        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  DMA controlled mode(Rd_DMA). 0: others
-         */
-        uint32_t slv_rddma_bitlen_en:1;
-        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in DMA controlled mode(Wr_DMA). 0: others
-         */
-        uint32_t slv_wrdma_bitlen_en:1;
-        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  CPU controlled mode(Rd_BUF). 0: others
-         */
-        uint32_t slv_rdbuf_bitlen_en:1;
-        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in CPU controlled mode(Wr_BUF). 0: others
-         */
-        uint32_t slv_wrbuf_bitlen_en:1;
-        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
-         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
-         *  mode.
-         */
-        uint32_t slv_last_byte_strb:8;
-        uint32_t reserved_20:2;
-        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
-         *  The magic value of BM table in master DMA seg-trans.
-         */
-        uint32_t dma_seg_magic_value:4;
-        /** slave_mode : R/W; bitpos: [26]; default: 0;
-         *  Set SPI work mode. 1: slave mode 0: master mode.
-         */
-        uint32_t slave_mode:1;
-        /** soft_reset : WT; bitpos: [27]; default: 0;
-         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
-         *  configured in CONF state.
-         */
-        uint32_t soft_reset:1;
-        /** usr_conf : R/W; bitpos: [28]; default: 0;
-         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
-         *  will start. 0: This is not seg-trans mode.
-         */
-        uint32_t usr_conf:1;
-        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
-         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
-         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
-         *  transfer.
-         */
-        uint32_t mst_fd_wait_dma_tx_data:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} spi_slave_reg_t;
-
-/** Type of slave1 register
- *  SPI slave control register 1
- */
-typedef union {
-    struct {
-        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
-         *  The transferred data bit length in SPI slave FD and HD mode.
-         */
-        uint32_t slv_data_bitlen:18;
-        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
-         *  In the slave mode it is the value of command.
-         */
-        uint32_t slv_last_command:8;
-        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
-         *  In the slave mode it is the value of address.
-         */
-        uint32_t slv_last_addr:6;
-    };
-    uint32_t val;
-} spi_slave1_reg_t;
-
-
-/** Group: Clock control registers */
-/** Type of clock register
- *  SPI clock control register
- */
-typedef union {
-    struct {
-        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
-         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
-         *  0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_l:6;
-        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
-         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-         *  must be 0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_h:6;
-        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
-         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
-         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-         */
-        uint32_t clkcnt_n:6;
-        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
-         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
-         */
-        uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:9;
-        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
-         *  clock. Can be configured in CONF state.
-         */
-        uint32_t clk_equ_sysclk:1;
-    };
-    uint32_t val;
-} spi_clock_reg_t;
-
-/** Type of clk_gate register
- *  SPI module clock and register clock control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable clk gate
-         */
-        uint32_t clk_en:1;
-        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to power on the SPI module clock.
-         */
-        uint32_t mst_clk_active:1;
-        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
-         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
-         *  0: XTAL CLK.
-         */
-        uint32_t mst_clk_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} spi_clk_gate_reg_t;
-
-
-/** Group: Timing registers */
-/** Type of din_mode register
- *  SPI input delay mode configuration
- */
-typedef union {
-    struct {
-        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din0_mode:2;
-        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din1_mode:2;
-        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din2_mode:2;
-        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din3_mode:2;
-        /** din4_mode : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din4_mode:2;
-        /** din5_mode : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din5_mode:2;
-        /** din6_mode : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din6_mode:2;
-        /** din7_mode : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din7_mode:2;
-        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
-         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
-         *  state.
-         */
-        uint32_t timing_hclk_active:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} spi_din_mode_reg_t;
-
-/** Type of din_num register
- *  SPI input delay number configuration
- */
-typedef union {
-    struct {
-        /** din0_num : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din0_num:2;
-        /** din1_num : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din1_num:2;
-        /** din2_num : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din2_num:2;
-        /** din3_num : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din3_num:2;
-        /** din4_num : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din4_num:2;
-        /** din5_num : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din5_num:2;
-        /** din6_num : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din6_num:2;
-        /** din7_num : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din7_num:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} spi_din_num_reg_t;
-
-/** Type of dout_mode register
- *  SPI output delay mode configuration
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [0]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout0_mode:1;
-        /** dout1_mode : R/W; bitpos: [1]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout1_mode:1;
-        /** dout2_mode : R/W; bitpos: [2]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout2_mode:1;
-        /** dout3_mode : R/W; bitpos: [3]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout3_mode:1;
-        /** dout4_mode : HRO; bitpos: [4]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout4_mode:1;
-        /** dout5_mode : HRO; bitpos: [5]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout5_mode:1;
-        /** dout6_mode : HRO; bitpos: [6]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout6_mode:1;
-        /** dout7_mode : HRO; bitpos: [7]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout7_mode:1;
-        /** d_dqs_mode : HRO; bitpos: [8]; default: 0;
-         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t d_dqs_mode:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} spi_dout_mode_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of dma_int_ena register
- *  SPI interrupt enable register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_ena:1;
-        /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_ena:1;
-        /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_ena:1;
-        /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_ena:1;
-        /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_ena:1;
-        /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_ena:1;
-        /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_ena:1;
-        /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_ena:1;
-        /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_ena:1;
-        /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_ena:1;
-        /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_ena:1;
-        /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_ena:1;
-        /** trans_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_ena:1;
-        /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_ena:1;
-        /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_ena:1;
-        /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_ena:1;
-        /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_ena:1;
-        /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
-         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_ena:1;
-        /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
-         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_ena:1;
-        /** app2_int_ena : R/W; bitpos: [19]; default: 0;
-         *  The enable bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_ena:1;
-        /** app1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  The enable bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_ena:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_ena_reg_t;
-
-/** Type of dma_int_clr register
- *  SPI interrupt clear register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_clr:1;
-        /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_clr:1;
-        /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_clr:1;
-        /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_clr:1;
-        /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_clr:1;
-        /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0;
-         *  The clear bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_clr:1;
-        /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0;
-         *  The clear bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_clr:1;
-        /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0;
-         *  The clear bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_clr:1;
-        /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0;
-         *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_clr:1;
-        /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0;
-         *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_clr:1;
-        /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
-         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_clr:1;
-        /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
-         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_clr:1;
-        /** trans_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_clr:1;
-        /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_clr:1;
-        /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
-         *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_clr:1;
-        /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_clr:1;
-        /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_clr:1;
-        /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
-         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_clr:1;
-        /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
-         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_clr:1;
-        /** app2_int_clr : WT; bitpos: [19]; default: 0;
-         *  The clear bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_clr:1;
-        /** app1_int_clr : WT; bitpos: [20]; default: 0;
-         *  The clear bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_clr:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_clr_reg_t;
-
-/** Type of dma_int_raw register
- *  SPI interrupt raw register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
-         *  receive data.  0: Others.
-         */
-        uint32_t dma_infifo_full_err_int_raw:1;
-        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
-         *  master mode and send out all 0 in slave mode.  0: Others.
-         */
-        uint32_t dma_outfifo_empty_err_int_raw:1;
-        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_ex_qpi_int_raw:1;
-        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_en_qpi_int_raw:1;
-        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd7_int_raw:1;
-        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd8_int_raw:1;
-        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd9_int_raw:1;
-        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmda_int_raw:1;
-        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_dma_done_int_raw:1;
-        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_dma_done_int_raw:1;
-        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_buf_done_int_raw:1;
-        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_buf_done_int_raw:1;
-        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
-         *  ended. 0: others.
-         */
-        uint32_t trans_done_int_raw:1;
-        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
-         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
-         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
-         *  is not ended or not occurred.
-         */
-        uint32_t dma_seg_trans_done_int_raw:1;
-        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
-         *  is error in the DMA seg-conf-trans. 0: others.
-         */
-        uint32_t seg_magic_err_int_raw:1;
-        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
-         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
-         *  bigger than 63. 0: Others.
-         */
-        uint32_t slv_buf_addr_err_int_raw:1;
-        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
-         *  current SPI slave HD mode transmission is not supported. 0: Others.
-         */
-        uint32_t slv_cmd_err_int_raw:1;
-        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
-         *  write-full error when SPI inputs data in master mode. 0: Others.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_raw:1;
-        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_raw:1;
-        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app2_int_raw:1;
-        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app1_int_raw:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_raw_reg_t;
-
-/** Type of dma_int_st register
- *  SPI interrupt status register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_st:1;
-        /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_st:1;
-        /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_st:1;
-        /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_st:1;
-        /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_st:1;
-        /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0;
-         *  The status bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_st:1;
-        /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0;
-         *  The status bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_st:1;
-        /** slv_cmda_int_st : RO; bitpos: [7]; default: 0;
-         *  The status bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_st:1;
-        /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0;
-         *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_st:1;
-        /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0;
-         *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_st:1;
-        /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_st:1;
-        /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
-         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_st:1;
-        /** trans_done_int_st : RO; bitpos: [12]; default: 0;
-         *  The status bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_st:1;
-        /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0;
-         *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_st:1;
-        /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
-         *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_st:1;
-        /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
-         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_st:1;
-        /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
-         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_st:1;
-        /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
-         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_st:1;
-        /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
-         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_st:1;
-        /** app2_int_st : RO; bitpos: [19]; default: 0;
-         *  The status bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_st:1;
-        /** app1_int_st : RO; bitpos: [20]; default: 0;
-         *  The status bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_st:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_st_reg_t;
-
-/** Type of dma_int_set register
- *  SPI interrupt software set register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
-         *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_set:1;
-        /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
-         *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_set:1;
-        /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
-         *  The software set bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_set:1;
-        /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
-         *  The software set bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_set:1;
-        /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
-         *  The software set bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_set:1;
-        /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
-         *  The software set bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_set:1;
-        /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
-         *  The software set bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_set:1;
-        /** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
-         *  The software set bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_set:1;
-        /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
-         *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_set:1;
-        /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
-         *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_set:1;
-        /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
-         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_set:1;
-        /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
-         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_set:1;
-        /** trans_done_int_set : WT; bitpos: [12]; default: 0;
-         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_set:1;
-        /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
-         *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_set:1;
-        /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
-         *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_set:1;
-        /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
-         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_set:1;
-        /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
-         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_set:1;
-        /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
-         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_set:1;
-        /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
-         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_set:1;
-        /** app2_int_set : WT; bitpos: [19]; default: 0;
-         *  The software set bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_set:1;
-        /** app1_int_set : WT; bitpos: [20]; default: 0;
-         *  The software set bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_set:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_set_reg_t;
-
-
-/** Group: CPU-controlled data buffer */
-/** Type of wn register
- *  SPI CPU-controlled buffer n
- */
-typedef union {
-    struct {
-        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf:32;
-    };
-    uint32_t val;
-} spi_wn_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36716931;
-         *  SPI register version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} spi_date_reg_t;
-
-
-typedef struct spi_dev_t {
-    volatile spi_cmd_reg_t cmd;
-    volatile spi_addr_reg_t addr;
-    volatile spi_ctrl_reg_t ctrl;
-    volatile spi_clock_reg_t clock;
-    volatile spi_user_reg_t user;
-    volatile spi_user1_reg_t user1;
-    volatile spi_user2_reg_t user2;
-    volatile spi_ms_dlen_reg_t ms_dlen;
-    volatile spi_misc_reg_t misc;
-    volatile spi_din_mode_reg_t din_mode;
-    volatile spi_din_num_reg_t din_num;
-    volatile spi_dout_mode_reg_t dout_mode;
-    volatile spi_dma_conf_reg_t dma_conf;
-    volatile spi_dma_int_ena_reg_t dma_int_ena;
-    volatile spi_dma_int_clr_reg_t dma_int_clr;
-    volatile spi_dma_int_raw_reg_t dma_int_raw;
-    volatile spi_dma_int_st_reg_t  dma_int_sta;
-    volatile spi_dma_int_set_reg_t dma_int_set;
-    uint32_t reserved_048[20];
-    volatile spi_wn_reg_t data_buf[16];
-    uint32_t reserved_0d8[2];
-    volatile spi_slave_reg_t slave;
-    volatile spi_slave1_reg_t slave1;
-    volatile spi_clk_gate_reg_t clk_gate;
-    uint32_t reserved_0ec;
-    volatile spi_date_reg_t date;
-} spi_dev_t;
-
-extern spi_dev_t GPSPI2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/system_periph_retention.h b/components/soc/esp32c5/beta3/include/soc/system_periph_retention.h
deleted file mode 100644
index 23c82b2953..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/system_periph_retention.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc_caps.h"
-#include "soc/regdma.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#if SOC_PAU_SUPPORTED
-/**
- * @brief Provide access to interrupt matrix configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define INT_MTX_RETENTION_LINK_LEN   1
-extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
-
-/**
- * @brief Provide access to hp_system configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define HP_SYSTEM_RETENTION_LINK_LEN 1
-extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
-
-/**
- * @brief Provide access to TEE_APM configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define TEE_APM_RETENTION_LINK_LEN   2
-extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN];
-#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN   1
-extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
-
-/**
- * @brief Provide access to timer group configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define TIMG_RETENTION_LINK_LEN     8
-extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN];
-
-/**
- * @brief Provide access to IOMUX configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define IOMUX_RETENTION_LINK_LEN    4
-extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN];
-
-/**
- * @brief Provide access to spimem configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define SPIMEM_RETENTION_LINK_LEN   8
-extern const regdma_entries_config_t spimem_regs_retention[SPIMEM_RETENTION_LINK_LEN];
-
-/**
- * @brief Provide access to systimer configuration registers retention
- * context definition.
- *
- * This is an internal function of the sleep retention driver, and is not
- * useful for external use.
- */
-#define SYSTIMER_RETENTION_LINK_LEN   19
-extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN];
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/system_reg.h b/components/soc/esp32c5/beta3/include/soc/system_reg.h
deleted file mode 100644
index dd39cb4189..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/system_reg.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/hp_system_reg.h"
-
-// TODO: IDF-5720
-#include "intpri_reg.h"
-#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
-#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
diff --git a/components/soc/esp32c5/beta3/include/soc/systimer_reg.h b/components/soc/esp32c5/beta3/include/soc/systimer_reg.h
deleted file mode 100644
index 07b67111f5..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/systimer_reg.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SYSTIMER_CONF_REG register
- *  Configure system timer clock
- */
-#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
-/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
- *  enable systimer's etm task and event
- */
-#define SYSTIMER_ETM_EN    (BIT(1))
-#define SYSTIMER_ETM_EN_M  (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
-#define SYSTIMER_ETM_EN_V  0x00000001U
-#define SYSTIMER_ETM_EN_S  1
-/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
- *  target2 work enable
- */
-#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
-#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
-#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001U
-#define SYSTIMER_TARGET2_WORK_EN_S  22
-/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
- *  target1 work enable
- */
-#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
-#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
-#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001U
-#define SYSTIMER_TARGET1_WORK_EN_S  23
-/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
- *  target0 work enable
- */
-#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
-#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
-#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001U
-#define SYSTIMER_TARGET0_WORK_EN_S  24
-/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
- *  If timer unit1 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
-/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
- *  If timer unit1 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
-/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
- *  If timer unit0 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
-/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
- *  If timer unit0 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
-/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
- *  timer unit1 work enable
- */
-#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
-/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
- *  timer unit0 work enable
- */
-#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
-/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  register file clk gating
- */
-#define SYSTIMER_CLK_EN    (BIT(31))
-#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
-#define SYSTIMER_CLK_EN_V  0x00000001U
-#define SYSTIMER_CLK_EN_S  31
-
-/** SYSTIMER_UNIT0_OP_REG register
- *  system timer unit0 value update register
- */
-#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
-/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  timer value is sync and valid
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer_unit0
- */
-#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
-
-/** SYSTIMER_UNIT1_OP_REG register
- *  system timer unit1 value update register
- */
-#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
-/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  timer value is sync and valid
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer unit1
- */
-#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
-
-/** SYSTIMER_UNIT0_LOAD_HI_REG register
- *  system timer unit0 value high load register
- */
-#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
-/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit0 load high 20 bits
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT0_LOAD_LO_REG register
- *  system timer unit0 value low load register
- */
-#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
-/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit0 load low 32 bits
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
-
-/** SYSTIMER_UNIT1_LOAD_HI_REG register
- *  system timer unit1 value high load register
- */
-#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
-/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit1 load high 20 bits
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT1_LOAD_LO_REG register
- *  system timer unit1 value low load register
- */
-#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
-/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit1 load low 32 bits
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
-
-/** SYSTIMER_TARGET0_HI_REG register
- *  system timer comp0 value high register
- */
-#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
-/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget0 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
-#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET0_HI_S  0
-
-/** SYSTIMER_TARGET0_LO_REG register
- *  system timer comp0 value low register
- */
-#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
-/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget0 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
-#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET0_LO_S  0
-
-/** SYSTIMER_TARGET1_HI_REG register
- *  system timer comp1 value high register
- */
-#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
-/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget1 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
-#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET1_HI_S  0
-
-/** SYSTIMER_TARGET1_LO_REG register
- *  system timer comp1 value low register
- */
-#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
-/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget1 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
-#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET1_LO_S  0
-
-/** SYSTIMER_TARGET2_HI_REG register
- *  system timer comp2 value high register
- */
-#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
-/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget2 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
-#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET2_HI_S  0
-
-/** SYSTIMER_TARGET2_LO_REG register
- *  system timer comp2 value low register
- */
-#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
-/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget2 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
-#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET2_LO_S  0
-
-/** SYSTIMER_TARGET0_CONF_REG register
- *  system timer comp0 target mode register
- */
-#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
-/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target0 period
- */
-#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFFU
-#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
-#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFFU
-#define SYSTIMER_TARGET0_PERIOD_S  0
-/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target0 to period mode
- */
-#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
-#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001U
-#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001U
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET1_CONF_REG register
- *  system timer comp1 target mode register
- */
-#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
-/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target1 period
- */
-#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFFU
-#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
-#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFFU
-#define SYSTIMER_TARGET1_PERIOD_S  0
-/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target1 to period mode
- */
-#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
-#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001U
-#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001U
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET2_CONF_REG register
- *  system timer comp2 target mode register
- */
-#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
-/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target2 period
- */
-#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFFU
-#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
-#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFFU
-#define SYSTIMER_TARGET2_PERIOD_S  0
-/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target2 to period mode
- */
-#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
-#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001U
-#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001U
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_UNIT0_VALUE_HI_REG register
- *  system timer unit0 value high register
- */
-#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
-/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 20bits
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT0_VALUE_LO_REG register
- *  system timer unit0 value low register
- */
-#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
-/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bits
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
-
-/** SYSTIMER_UNIT1_VALUE_HI_REG register
- *  system timer unit1 value high register
- */
-#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
-/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 20bits
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT1_VALUE_LO_REG register
- *  system timer unit1 value low register
- */
-#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
-/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bits
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
-
-/** SYSTIMER_COMP0_LOAD_REG register
- *  system timer comp0 conf sync register
- */
-#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
-/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp0 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
-#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_COMP0_LOAD_S  0
-
-/** SYSTIMER_COMP1_LOAD_REG register
- *  system timer comp1 conf sync register
- */
-#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
-/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp1 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
-#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_COMP1_LOAD_S  0
-
-/** SYSTIMER_COMP2_LOAD_REG register
- *  system timer comp2 conf sync register
- */
-#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
-/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp2 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
-#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_COMP2_LOAD_S  0
-
-/** SYSTIMER_UNIT0_LOAD_REG register
- *  system timer unit0 conf sync register
- */
-#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
-/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit0 sync enable signal
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
-
-/** SYSTIMER_UNIT1_LOAD_REG register
- *  system timer unit1 conf sync register
- */
-#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
-/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit1 sync enable signal
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
-
-/** SYSTIMER_INT_ENA_REG register
- *  systimer interrupt enable register
- */
-#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
-/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  interupt0 enable
- */
-#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
-#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_ENA_S  0
-/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  interupt1 enable
- */
-#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
-#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_ENA_S  1
-/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  interupt2 enable
- */
-#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
-#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_ENA_S  2
-
-/** SYSTIMER_INT_RAW_REG register
- *  systimer interrupt raw register
- */
-#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
-/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  interupt0 raw
- */
-#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
-#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
-#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_RAW_S  0
-/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  interupt1 raw
- */
-#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
-#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
-#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_RAW_S  1
-/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  interupt2 raw
- */
-#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
-#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
-#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_RAW_S  2
-
-/** SYSTIMER_INT_CLR_REG register
- *  systimer interrupt clear register
- */
-#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
-/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  interupt0 clear
- */
-#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
-#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
-#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_CLR_S  0
-/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  interupt1 clear
- */
-#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
-#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
-#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_CLR_S  1
-/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  interupt2 clear
- */
-#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
-#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
-#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_CLR_S  2
-
-/** SYSTIMER_INT_ST_REG register
- *  systimer interrupt status register
- */
-#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
-/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
- *  interupt0 status
- */
-#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
-#define SYSTIMER_TARGET0_INT_ST_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_ST_S  0
-/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
- *  interupt1 status
- */
-#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
-#define SYSTIMER_TARGET1_INT_ST_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_ST_S  1
-/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
- *  interupt2 status
- */
-#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
-#define SYSTIMER_TARGET2_INT_ST_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_ST_S  2
-
-/** SYSTIMER_REAL_TARGET0_LO_REG register
- *  system timer comp0 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
-/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET0_LO_RO    0xFFFFFFFFU
-#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
-#define SYSTIMER_TARGET0_LO_RO_V  0xFFFFFFFFU
-#define SYSTIMER_TARGET0_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET0_HI_REG register
- *  system timer comp0 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
-/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET0_HI_RO    0x000FFFFFU
-#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
-#define SYSTIMER_TARGET0_HI_RO_V  0x000FFFFFU
-#define SYSTIMER_TARGET0_HI_RO_S  0
-
-/** SYSTIMER_REAL_TARGET1_LO_REG register
- *  system timer comp1 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
-/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET1_LO_RO    0xFFFFFFFFU
-#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
-#define SYSTIMER_TARGET1_LO_RO_V  0xFFFFFFFFU
-#define SYSTIMER_TARGET1_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET1_HI_REG register
- *  system timer comp1 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
-/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET1_HI_RO    0x000FFFFFU
-#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
-#define SYSTIMER_TARGET1_HI_RO_V  0x000FFFFFU
-#define SYSTIMER_TARGET1_HI_RO_S  0
-
-/** SYSTIMER_REAL_TARGET2_LO_REG register
- *  system timer comp2 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
-/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET2_LO_RO    0xFFFFFFFFU
-#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
-#define SYSTIMER_TARGET2_LO_RO_V  0xFFFFFFFFU
-#define SYSTIMER_TARGET2_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET2_HI_REG register
- *  system timer comp2 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
-/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET2_HI_RO    0x000FFFFFU
-#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
-#define SYSTIMER_TARGET2_HI_RO_V  0x000FFFFFU
-#define SYSTIMER_TARGET2_HI_RO_S  0
-
-/** SYSTIMER_DATE_REG register
- *  system timer version control register
- */
-#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
-/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
- *  systimer register version
- */
-#define SYSTIMER_DATE    0xFFFFFFFFU
-#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
-#define SYSTIMER_DATE_V  0xFFFFFFFFU
-#define SYSTIMER_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/systimer_struct.h b/components/soc/esp32c5/beta3/include/soc/systimer_struct.h
deleted file mode 100644
index 3fe5b681d5..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/systimer_struct.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
-/** Type of conf register
- *  Configure system timer clock
- */
-typedef union {
-    struct {
-        /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
-         *  systimer clock force on
-         */
-        uint32_t systimer_clk_fo:1;
-        /** etm_en : R/W; bitpos: [1]; default: 0;
-         *  enable systimer's etm task and event
-         */
-        uint32_t etm_en:1;
-        uint32_t reserved_2:20;
-        /** target2_work_en : R/W; bitpos: [22]; default: 0;
-         *  target2 work enable
-         */
-        uint32_t target2_work_en:1;
-        /** target1_work_en : R/W; bitpos: [23]; default: 0;
-         *  target1 work enable
-         */
-        uint32_t target1_work_en:1;
-        /** target0_work_en : R/W; bitpos: [24]; default: 0;
-         *  target0 work enable
-         */
-        uint32_t target0_work_en:1;
-        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
-         *  If timer unit1 is stalled when core1 stalled
-         */
-        uint32_t timer_unit1_core1_stall_en:1;
-        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
-         *  If timer unit1 is stalled when core0 stalled
-         */
-        uint32_t timer_unit1_core0_stall_en:1;
-        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
-         *  If timer unit0 is stalled when core1 stalled
-         */
-        uint32_t timer_unit0_core1_stall_en:1;
-        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
-         *  If timer unit0 is stalled when core0 stalled
-         */
-        uint32_t timer_unit0_core0_stall_en:1;
-        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
-         *  timer unit1 work enable
-         */
-        uint32_t timer_unit1_work_en:1;
-        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
-         *  timer unit0 work enable
-         */
-        uint32_t timer_unit0_work_en:1;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  register file clk gating
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} systimer_conf_reg_t;
-
-
-/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */
-/** Type of unit_op register
- *  system timer unit value update register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0: 29;
-        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
-         *  timer value is sync and valid
-         */
-        uint32_t timer_unit_value_valid: 1;
-        /** timer_unit_update : WT; bitpos: [30]; default: 0;
-         *  update timer_unit
-         */
-        uint32_t timer_unit_update: 1;
-        uint32_t reserved31: 1;
-    };
-    uint32_t val;
-} systimer_unit_op_reg_t;
-
-/** Type of unit_load register
- *  system timer unit value high and low load register
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer unit load high 20 bit
-             */
-            uint32_t timer_unit_load_hi: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
-             *  timer unit load low 32 bit
-             */
-            uint32_t timer_unit_load_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_unit_load_val_reg_t;
-
-/** Type of unit_value_hi register
- *  system timer unit value high and low register
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
-             *  timer read value high 20 bit
-             */
-            uint32_t timer_unit_value_hi: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
-             *  timer read value low 32 bit
-             */
-            uint32_t timer_unit_value_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_unit_value_reg_t;
-
-/** Type of unit_load register
- *  system timer unit conf sync register
- */
-typedef union {
-    struct {
-        /** timer_unit_load : WT; bitpos: [0]; default: 0;
-         *  timer unit load value
-         */
-        uint32_t timer_unit_load: 1;
-        uint32_t reserved1: 31;
-    };
-    uint32_t val;
-} systimer_unit_load_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */
-/** Type of target register
- *  system timer comp value high and low register
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer target high 20 bit
-             */
-            uint32_t timer_target_hi: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
-             *  timer target low 32 bit
-             */
-            uint32_t timer_target_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_target_val_reg_t;
-
-/** Type of target_conf register
- *  system timer comp target mode register
- */
-typedef union {
-    struct {
-        /** target_period : R/W; bitpos: [25:0]; default: 0;
-         *  target period
-         */
-        uint32_t target_period: 26;
-        uint32_t reserved_26: 4;
-        /** target_period_mode : R/W; bitpos: [30]; default: 0;
-         *  Set target to period mode
-         */
-        uint32_t target_period_mode: 1;
-        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
-         *  select which unit to compare
-         */
-        uint32_t target_timer_unit_sel: 1;
-    };
-    uint32_t val;
-} systimer_target_conf_reg_t;
-
-/** Type of comp_load register
- *  system timer comp conf sync register
- */
-typedef union {
-    struct {
-        /** timer_comp_load : WT; bitpos: [0]; default: 0;
-         *  timer comp sync enable signal
-         */
-        uint32_t timer_comp_load: 1;
-        uint32_t reserved1: 31;
-    };
-    uint32_t val;
-} systimer_comp_load_reg_t;
-
-
-/** Group: SYSTEM TIMER INTERRUPT REGISTER */
-/** Type of int_ena register
- *  systimer interrupt enable register
- */
-typedef union {
-    struct {
-        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  interupt0 enable
-         */
-        uint32_t target0_int_ena:1;
-        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  interupt1 enable
-         */
-        uint32_t target1_int_ena:1;
-        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  interupt2 enable
-         */
-        uint32_t target2_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_ena_reg_t;
-
-/** Type of int_raw register
- *  systimer interrupt raw register
- */
-typedef union {
-    struct {
-        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  interupt0 raw
-         */
-        uint32_t target0_int_raw:1;
-        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  interupt1 raw
-         */
-        uint32_t target1_int_raw:1;
-        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  interupt2 raw
-         */
-        uint32_t target2_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_raw_reg_t;
-
-/** Type of int_clr register
- *  systimer interrupt clear register
- */
-typedef union {
-    struct {
-        /** target0_int_clr : WT; bitpos: [0]; default: 0;
-         *  interupt0 clear
-         */
-        uint32_t target0_int_clr:1;
-        /** target1_int_clr : WT; bitpos: [1]; default: 0;
-         *  interupt1 clear
-         */
-        uint32_t target1_int_clr:1;
-        /** target2_int_clr : WT; bitpos: [2]; default: 0;
-         *  interupt2 clear
-         */
-        uint32_t target2_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_clr_reg_t;
-
-/** Type of int_st register
- *  systimer interrupt status register
- */
-typedef union {
-    struct {
-        /** target0_int_st : RO; bitpos: [0]; default: 0;
-         *  interupt0 status
-         */
-        uint32_t target0_int_st:1;
-        /** target1_int_st : RO; bitpos: [1]; default: 0;
-         *  interupt1 status
-         */
-        uint32_t target1_int_st:1;
-        /** target2_int_st : RO; bitpos: [2]; default: 0;
-         *  interupt2 status
-         */
-        uint32_t target2_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_st_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP STATUS REGISTER */
-/** Type of real_target_hi/lo register
- *  system timer comp actual target value low register
- */
-typedef struct {
-    union {
-        struct {
-            /** target_lo_ro : RO; bitpos: [31:0]; default: 0;
-             *  actual target value value low 32 bits
-             */
-            uint32_t target_lo_ro: 32;
-        };
-        uint32_t val;
-    } lo;
-    union {
-        struct {
-            /** target_hi_ro : RO; bitpos: [19:0]; default: 0;
-             *  actual target value value high 20 bits
-             */
-            uint32_t target_hi_ro: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-} systimer_real_target_reg_t;
-
-
-/** Group: VERSION REGISTER */
-/** Type of date register
- *  system timer version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35655795;
-         *  systimer register version
-         */
-        uint32_t date: 32;
-    };
-    uint32_t val;
-} systimer_date_reg_t;
-
-
-typedef struct systimer_dev_t {
-    volatile systimer_conf_reg_t conf;
-    volatile systimer_unit_op_reg_t unit_op[2];
-    volatile systimer_unit_load_val_reg_t unit_load_val[2];
-    volatile systimer_target_val_reg_t target_val[3];
-    volatile systimer_target_conf_reg_t target_conf[3];
-    volatile systimer_unit_value_reg_t unit_val[2];
-    volatile systimer_comp_load_reg_t comp_load[3];
-    volatile systimer_unit_load_reg_t unit_load[2];
-    volatile systimer_int_ena_reg_t int_ena;
-    volatile systimer_int_raw_reg_t int_raw;
-    volatile systimer_int_clr_reg_t int_clr;
-    volatile systimer_int_st_reg_t int_st;
-    volatile systimer_real_target_reg_t real_target[3];
-    uint32_t reserved_08c[28];
-    volatile systimer_date_reg_t date;
-} systimer_dev_t;
-
-extern systimer_dev_t SYSTIMER;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/tee_reg.h b/components/soc/esp32c5/beta3/include/soc/tee_reg.h
deleted file mode 100644
index af5f268000..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/tee_reg.h
+++ /dev/null
@@ -1,680 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TEE_M0_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0)
-/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M0_MODE    0x00000003U
-#define TEE_M0_MODE_M  (TEE_M0_MODE_V << TEE_M0_MODE_S)
-#define TEE_M0_MODE_V  0x00000003U
-#define TEE_M0_MODE_S  0
-/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m0 tee configuration
- */
-#define TEE_M0_LOCK    (BIT(2))
-#define TEE_M0_LOCK_M  (TEE_M0_LOCK_V << TEE_M0_LOCK_S)
-#define TEE_M0_LOCK_V  0x00000001U
-#define TEE_M0_LOCK_S  2
-
-/** TEE_M1_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4)
-/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M1_MODE    0x00000003U
-#define TEE_M1_MODE_M  (TEE_M1_MODE_V << TEE_M1_MODE_S)
-#define TEE_M1_MODE_V  0x00000003U
-#define TEE_M1_MODE_S  0
-/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m1 tee configuration
- */
-#define TEE_M1_LOCK    (BIT(2))
-#define TEE_M1_LOCK_M  (TEE_M1_LOCK_V << TEE_M1_LOCK_S)
-#define TEE_M1_LOCK_V  0x00000001U
-#define TEE_M1_LOCK_S  2
-
-/** TEE_M2_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8)
-/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0;
- *  M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M2_MODE    0x00000003U
-#define TEE_M2_MODE_M  (TEE_M2_MODE_V << TEE_M2_MODE_S)
-#define TEE_M2_MODE_V  0x00000003U
-#define TEE_M2_MODE_S  0
-/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m2 tee configuration
- */
-#define TEE_M2_LOCK    (BIT(2))
-#define TEE_M2_LOCK_M  (TEE_M2_LOCK_V << TEE_M2_LOCK_S)
-#define TEE_M2_LOCK_V  0x00000001U
-#define TEE_M2_LOCK_S  2
-
-/** TEE_M3_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc)
-/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M3_MODE    0x00000003U
-#define TEE_M3_MODE_M  (TEE_M3_MODE_V << TEE_M3_MODE_S)
-#define TEE_M3_MODE_V  0x00000003U
-#define TEE_M3_MODE_S  0
-/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m3 tee configuration
- */
-#define TEE_M3_LOCK    (BIT(2))
-#define TEE_M3_LOCK_M  (TEE_M3_LOCK_V << TEE_M3_LOCK_S)
-#define TEE_M3_LOCK_V  0x00000001U
-#define TEE_M3_LOCK_S  2
-
-/** TEE_M4_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10)
-/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M4_MODE    0x00000003U
-#define TEE_M4_MODE_M  (TEE_M4_MODE_V << TEE_M4_MODE_S)
-#define TEE_M4_MODE_V  0x00000003U
-#define TEE_M4_MODE_S  0
-/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m4 tee configuration
- */
-#define TEE_M4_LOCK    (BIT(2))
-#define TEE_M4_LOCK_M  (TEE_M4_LOCK_V << TEE_M4_LOCK_S)
-#define TEE_M4_LOCK_V  0x00000001U
-#define TEE_M4_LOCK_S  2
-
-/** TEE_M5_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14)
-/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M5_MODE    0x00000003U
-#define TEE_M5_MODE_M  (TEE_M5_MODE_V << TEE_M5_MODE_S)
-#define TEE_M5_MODE_V  0x00000003U
-#define TEE_M5_MODE_S  0
-/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m5 tee configuration
- */
-#define TEE_M5_LOCK    (BIT(2))
-#define TEE_M5_LOCK_M  (TEE_M5_LOCK_V << TEE_M5_LOCK_S)
-#define TEE_M5_LOCK_V  0x00000001U
-#define TEE_M5_LOCK_S  2
-
-/** TEE_M6_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18)
-/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M6_MODE    0x00000003U
-#define TEE_M6_MODE_M  (TEE_M6_MODE_V << TEE_M6_MODE_S)
-#define TEE_M6_MODE_V  0x00000003U
-#define TEE_M6_MODE_S  0
-/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m6 tee configuration
- */
-#define TEE_M6_LOCK    (BIT(2))
-#define TEE_M6_LOCK_M  (TEE_M6_LOCK_V << TEE_M6_LOCK_S)
-#define TEE_M6_LOCK_V  0x00000001U
-#define TEE_M6_LOCK_S  2
-
-/** TEE_M7_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c)
-/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M7_MODE    0x00000003U
-#define TEE_M7_MODE_M  (TEE_M7_MODE_V << TEE_M7_MODE_S)
-#define TEE_M7_MODE_V  0x00000003U
-#define TEE_M7_MODE_S  0
-/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m7 tee configuration
- */
-#define TEE_M7_LOCK    (BIT(2))
-#define TEE_M7_LOCK_M  (TEE_M7_LOCK_V << TEE_M7_LOCK_S)
-#define TEE_M7_LOCK_V  0x00000001U
-#define TEE_M7_LOCK_S  2
-
-/** TEE_M8_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20)
-/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M8_MODE    0x00000003U
-#define TEE_M8_MODE_M  (TEE_M8_MODE_V << TEE_M8_MODE_S)
-#define TEE_M8_MODE_V  0x00000003U
-#define TEE_M8_MODE_S  0
-/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m8 tee configuration
- */
-#define TEE_M8_LOCK    (BIT(2))
-#define TEE_M8_LOCK_M  (TEE_M8_LOCK_V << TEE_M8_LOCK_S)
-#define TEE_M8_LOCK_V  0x00000001U
-#define TEE_M8_LOCK_S  2
-
-/** TEE_M9_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24)
-/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M9_MODE    0x00000003U
-#define TEE_M9_MODE_M  (TEE_M9_MODE_V << TEE_M9_MODE_S)
-#define TEE_M9_MODE_V  0x00000003U
-#define TEE_M9_MODE_S  0
-/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m9 tee configuration
- */
-#define TEE_M9_LOCK    (BIT(2))
-#define TEE_M9_LOCK_M  (TEE_M9_LOCK_V << TEE_M9_LOCK_S)
-#define TEE_M9_LOCK_V  0x00000001U
-#define TEE_M9_LOCK_S  2
-
-/** TEE_M10_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28)
-/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M10_MODE    0x00000003U
-#define TEE_M10_MODE_M  (TEE_M10_MODE_V << TEE_M10_MODE_S)
-#define TEE_M10_MODE_V  0x00000003U
-#define TEE_M10_MODE_S  0
-/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m10 tee configuration
- */
-#define TEE_M10_LOCK    (BIT(2))
-#define TEE_M10_LOCK_M  (TEE_M10_LOCK_V << TEE_M10_LOCK_S)
-#define TEE_M10_LOCK_V  0x00000001U
-#define TEE_M10_LOCK_S  2
-
-/** TEE_M11_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c)
-/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M11_MODE    0x00000003U
-#define TEE_M11_MODE_M  (TEE_M11_MODE_V << TEE_M11_MODE_S)
-#define TEE_M11_MODE_V  0x00000003U
-#define TEE_M11_MODE_S  0
-/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m11 tee configuration
- */
-#define TEE_M11_LOCK    (BIT(2))
-#define TEE_M11_LOCK_M  (TEE_M11_LOCK_V << TEE_M11_LOCK_S)
-#define TEE_M11_LOCK_V  0x00000001U
-#define TEE_M11_LOCK_S  2
-
-/** TEE_M12_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30)
-/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M12_MODE    0x00000003U
-#define TEE_M12_MODE_M  (TEE_M12_MODE_V << TEE_M12_MODE_S)
-#define TEE_M12_MODE_V  0x00000003U
-#define TEE_M12_MODE_S  0
-/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m12 tee configuration
- */
-#define TEE_M12_LOCK    (BIT(2))
-#define TEE_M12_LOCK_M  (TEE_M12_LOCK_V << TEE_M12_LOCK_S)
-#define TEE_M12_LOCK_V  0x00000001U
-#define TEE_M12_LOCK_S  2
-
-/** TEE_M13_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34)
-/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M13_MODE    0x00000003U
-#define TEE_M13_MODE_M  (TEE_M13_MODE_V << TEE_M13_MODE_S)
-#define TEE_M13_MODE_V  0x00000003U
-#define TEE_M13_MODE_S  0
-/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m13 tee configuration
- */
-#define TEE_M13_LOCK    (BIT(2))
-#define TEE_M13_LOCK_M  (TEE_M13_LOCK_V << TEE_M13_LOCK_S)
-#define TEE_M13_LOCK_V  0x00000001U
-#define TEE_M13_LOCK_S  2
-
-/** TEE_M14_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38)
-/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M14_MODE    0x00000003U
-#define TEE_M14_MODE_M  (TEE_M14_MODE_V << TEE_M14_MODE_S)
-#define TEE_M14_MODE_V  0x00000003U
-#define TEE_M14_MODE_S  0
-/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m14 tee configuration
- */
-#define TEE_M14_LOCK    (BIT(2))
-#define TEE_M14_LOCK_M  (TEE_M14_LOCK_V << TEE_M14_LOCK_S)
-#define TEE_M14_LOCK_V  0x00000001U
-#define TEE_M14_LOCK_S  2
-
-/** TEE_M15_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c)
-/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M15_MODE    0x00000003U
-#define TEE_M15_MODE_M  (TEE_M15_MODE_V << TEE_M15_MODE_S)
-#define TEE_M15_MODE_V  0x00000003U
-#define TEE_M15_MODE_S  0
-/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m15 tee configuration
- */
-#define TEE_M15_LOCK    (BIT(2))
-#define TEE_M15_LOCK_M  (TEE_M15_LOCK_V << TEE_M15_LOCK_S)
-#define TEE_M15_LOCK_V  0x00000001U
-#define TEE_M15_LOCK_S  2
-
-/** TEE_M16_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40)
-/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M16_MODE    0x00000003U
-#define TEE_M16_MODE_M  (TEE_M16_MODE_V << TEE_M16_MODE_S)
-#define TEE_M16_MODE_V  0x00000003U
-#define TEE_M16_MODE_S  0
-/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m16 tee configuration
- */
-#define TEE_M16_LOCK    (BIT(2))
-#define TEE_M16_LOCK_M  (TEE_M16_LOCK_V << TEE_M16_LOCK_S)
-#define TEE_M16_LOCK_V  0x00000001U
-#define TEE_M16_LOCK_S  2
-
-/** TEE_M17_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44)
-/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M17_MODE    0x00000003U
-#define TEE_M17_MODE_M  (TEE_M17_MODE_V << TEE_M17_MODE_S)
-#define TEE_M17_MODE_V  0x00000003U
-#define TEE_M17_MODE_S  0
-/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m17 tee configuration
- */
-#define TEE_M17_LOCK    (BIT(2))
-#define TEE_M17_LOCK_M  (TEE_M17_LOCK_V << TEE_M17_LOCK_S)
-#define TEE_M17_LOCK_V  0x00000001U
-#define TEE_M17_LOCK_S  2
-
-/** TEE_M18_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48)
-/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M18_MODE    0x00000003U
-#define TEE_M18_MODE_M  (TEE_M18_MODE_V << TEE_M18_MODE_S)
-#define TEE_M18_MODE_V  0x00000003U
-#define TEE_M18_MODE_S  0
-/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m18 tee configuration
- */
-#define TEE_M18_LOCK    (BIT(2))
-#define TEE_M18_LOCK_M  (TEE_M18_LOCK_V << TEE_M18_LOCK_S)
-#define TEE_M18_LOCK_V  0x00000001U
-#define TEE_M18_LOCK_S  2
-
-/** TEE_M19_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c)
-/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M19_MODE    0x00000003U
-#define TEE_M19_MODE_M  (TEE_M19_MODE_V << TEE_M19_MODE_S)
-#define TEE_M19_MODE_V  0x00000003U
-#define TEE_M19_MODE_S  0
-/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m19 tee configuration
- */
-#define TEE_M19_LOCK    (BIT(2))
-#define TEE_M19_LOCK_M  (TEE_M19_LOCK_V << TEE_M19_LOCK_S)
-#define TEE_M19_LOCK_V  0x00000001U
-#define TEE_M19_LOCK_S  2
-
-/** TEE_M20_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50)
-/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M20_MODE    0x00000003U
-#define TEE_M20_MODE_M  (TEE_M20_MODE_V << TEE_M20_MODE_S)
-#define TEE_M20_MODE_V  0x00000003U
-#define TEE_M20_MODE_S  0
-/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m20 tee configuration
- */
-#define TEE_M20_LOCK    (BIT(2))
-#define TEE_M20_LOCK_M  (TEE_M20_LOCK_V << TEE_M20_LOCK_S)
-#define TEE_M20_LOCK_V  0x00000001U
-#define TEE_M20_LOCK_S  2
-
-/** TEE_M21_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54)
-/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M21_MODE    0x00000003U
-#define TEE_M21_MODE_M  (TEE_M21_MODE_V << TEE_M21_MODE_S)
-#define TEE_M21_MODE_V  0x00000003U
-#define TEE_M21_MODE_S  0
-/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m21 tee configuration
- */
-#define TEE_M21_LOCK    (BIT(2))
-#define TEE_M21_LOCK_M  (TEE_M21_LOCK_V << TEE_M21_LOCK_S)
-#define TEE_M21_LOCK_V  0x00000001U
-#define TEE_M21_LOCK_S  2
-
-/** TEE_M22_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58)
-/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M22_MODE    0x00000003U
-#define TEE_M22_MODE_M  (TEE_M22_MODE_V << TEE_M22_MODE_S)
-#define TEE_M22_MODE_V  0x00000003U
-#define TEE_M22_MODE_S  0
-/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m22 tee configuration
- */
-#define TEE_M22_LOCK    (BIT(2))
-#define TEE_M22_LOCK_M  (TEE_M22_LOCK_V << TEE_M22_LOCK_S)
-#define TEE_M22_LOCK_V  0x00000001U
-#define TEE_M22_LOCK_S  2
-
-/** TEE_M23_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c)
-/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M23_MODE    0x00000003U
-#define TEE_M23_MODE_M  (TEE_M23_MODE_V << TEE_M23_MODE_S)
-#define TEE_M23_MODE_V  0x00000003U
-#define TEE_M23_MODE_S  0
-/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m23 tee configuration
- */
-#define TEE_M23_LOCK    (BIT(2))
-#define TEE_M23_LOCK_M  (TEE_M23_LOCK_V << TEE_M23_LOCK_S)
-#define TEE_M23_LOCK_V  0x00000001U
-#define TEE_M23_LOCK_S  2
-
-/** TEE_M24_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60)
-/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M24_MODE    0x00000003U
-#define TEE_M24_MODE_M  (TEE_M24_MODE_V << TEE_M24_MODE_S)
-#define TEE_M24_MODE_V  0x00000003U
-#define TEE_M24_MODE_S  0
-/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m24 tee configuration
- */
-#define TEE_M24_LOCK    (BIT(2))
-#define TEE_M24_LOCK_M  (TEE_M24_LOCK_V << TEE_M24_LOCK_S)
-#define TEE_M24_LOCK_V  0x00000001U
-#define TEE_M24_LOCK_S  2
-
-/** TEE_M25_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64)
-/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M25_MODE    0x00000003U
-#define TEE_M25_MODE_M  (TEE_M25_MODE_V << TEE_M25_MODE_S)
-#define TEE_M25_MODE_V  0x00000003U
-#define TEE_M25_MODE_S  0
-/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m25 tee configuration
- */
-#define TEE_M25_LOCK    (BIT(2))
-#define TEE_M25_LOCK_M  (TEE_M25_LOCK_V << TEE_M25_LOCK_S)
-#define TEE_M25_LOCK_V  0x00000001U
-#define TEE_M25_LOCK_S  2
-
-/** TEE_M26_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68)
-/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M26_MODE    0x00000003U
-#define TEE_M26_MODE_M  (TEE_M26_MODE_V << TEE_M26_MODE_S)
-#define TEE_M26_MODE_V  0x00000003U
-#define TEE_M26_MODE_S  0
-/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m26 tee configuration
- */
-#define TEE_M26_LOCK    (BIT(2))
-#define TEE_M26_LOCK_M  (TEE_M26_LOCK_V << TEE_M26_LOCK_S)
-#define TEE_M26_LOCK_V  0x00000001U
-#define TEE_M26_LOCK_S  2
-
-/** TEE_M27_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c)
-/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M27_MODE    0x00000003U
-#define TEE_M27_MODE_M  (TEE_M27_MODE_V << TEE_M27_MODE_S)
-#define TEE_M27_MODE_V  0x00000003U
-#define TEE_M27_MODE_S  0
-/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m27 tee configuration
- */
-#define TEE_M27_LOCK    (BIT(2))
-#define TEE_M27_LOCK_M  (TEE_M27_LOCK_V << TEE_M27_LOCK_S)
-#define TEE_M27_LOCK_V  0x00000001U
-#define TEE_M27_LOCK_S  2
-
-/** TEE_M28_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70)
-/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M28_MODE    0x00000003U
-#define TEE_M28_MODE_M  (TEE_M28_MODE_V << TEE_M28_MODE_S)
-#define TEE_M28_MODE_V  0x00000003U
-#define TEE_M28_MODE_S  0
-/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m28 tee configuration
- */
-#define TEE_M28_LOCK    (BIT(2))
-#define TEE_M28_LOCK_M  (TEE_M28_LOCK_V << TEE_M28_LOCK_S)
-#define TEE_M28_LOCK_V  0x00000001U
-#define TEE_M28_LOCK_S  2
-
-/** TEE_M29_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74)
-/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M29_MODE    0x00000003U
-#define TEE_M29_MODE_M  (TEE_M29_MODE_V << TEE_M29_MODE_S)
-#define TEE_M29_MODE_V  0x00000003U
-#define TEE_M29_MODE_S  0
-/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m29 tee configuration
- */
-#define TEE_M29_LOCK    (BIT(2))
-#define TEE_M29_LOCK_M  (TEE_M29_LOCK_V << TEE_M29_LOCK_S)
-#define TEE_M29_LOCK_V  0x00000001U
-#define TEE_M29_LOCK_S  2
-
-/** TEE_M30_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78)
-/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M30_MODE    0x00000003U
-#define TEE_M30_MODE_M  (TEE_M30_MODE_V << TEE_M30_MODE_S)
-#define TEE_M30_MODE_V  0x00000003U
-#define TEE_M30_MODE_S  0
-/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m30 tee configuration
- */
-#define TEE_M30_LOCK    (BIT(2))
-#define TEE_M30_LOCK_M  (TEE_M30_LOCK_V << TEE_M30_LOCK_S)
-#define TEE_M30_LOCK_V  0x00000001U
-#define TEE_M30_LOCK_S  2
-
-/** TEE_M31_MODE_CTRL_REG register
- *  Tee mode control register
- */
-#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c)
-/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 3;
- *  M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
- *  tee_mode
- */
-#define TEE_M31_MODE    0x00000003U
-#define TEE_M31_MODE_M  (TEE_M31_MODE_V << TEE_M31_MODE_S)
-#define TEE_M31_MODE_V  0x00000003U
-#define TEE_M31_MODE_S  0
-/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0;
- *  Set 1 to lock m31 tee configuration
- */
-#define TEE_M31_LOCK    (BIT(2))
-#define TEE_M31_LOCK_M  (TEE_M31_LOCK_V << TEE_M31_LOCK_S)
-#define TEE_M31_LOCK_V  0x00000001U
-#define TEE_M31_LOCK_S  2
-
-/** TEE_CLOCK_GATE_REG register
- *  Clock gating register
- */
-#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80)
-/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  reg_clk_en
- */
-#define TEE_CLK_EN    (BIT(0))
-#define TEE_CLK_EN_M  (TEE_CLK_EN_V << TEE_CLK_EN_S)
-#define TEE_CLK_EN_V  0x00000001U
-#define TEE_CLK_EN_S  0
-
-/** TEE_DATE_REG register
- *  Version register
- */
-#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc)
-/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
- *  reg_tee_date
- */
-#define TEE_DATE    0x0FFFFFFFU
-#define TEE_DATE_M  (TEE_DATE_V << TEE_DATE_S)
-#define TEE_DATE_V  0x0FFFFFFFU
-#define TEE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/tee_struct.h b/components/soc/esp32c5/beta3/include/soc/tee_struct.h
deleted file mode 100644
index 4cdb85c39c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/tee_struct.h
+++ /dev/null
@@ -1,701 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Tee mode control register */
-/** Type of m0_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m0_mode:2;
-        /** m0_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m0 tee configuration
-         */
-        uint32_t m0_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m0_mode_ctrl_reg_t;
-
-/** Type of m1_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m1_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m1_mode:2;
-        /** m1_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m1 tee configuration
-         */
-        uint32_t m1_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m1_mode_ctrl_reg_t;
-
-/** Type of m2_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m2_mode : R/W; bitpos: [1:0]; default: 0;
-         *  M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m2_mode:2;
-        /** m2_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m2 tee configuration
-         */
-        uint32_t m2_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m2_mode_ctrl_reg_t;
-
-/** Type of m3_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m3_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m3_mode:2;
-        /** m3_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m3 tee configuration
-         */
-        uint32_t m3_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m3_mode_ctrl_reg_t;
-
-/** Type of m4_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m4_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m4_mode:2;
-        /** m4_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m4 tee configuration
-         */
-        uint32_t m4_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m4_mode_ctrl_reg_t;
-
-/** Type of m5_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m5_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m5_mode:2;
-        /** m5_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m5 tee configuration
-         */
-        uint32_t m5_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m5_mode_ctrl_reg_t;
-
-/** Type of m6_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m6_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m6_mode:2;
-        /** m6_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m6 tee configuration
-         */
-        uint32_t m6_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m6_mode_ctrl_reg_t;
-
-/** Type of m7_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m7_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m7_mode:2;
-        /** m7_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m7 tee configuration
-         */
-        uint32_t m7_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m7_mode_ctrl_reg_t;
-
-/** Type of m8_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m8_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m8_mode:2;
-        /** m8_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m8 tee configuration
-         */
-        uint32_t m8_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m8_mode_ctrl_reg_t;
-
-/** Type of m9_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m9_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m9_mode:2;
-        /** m9_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m9 tee configuration
-         */
-        uint32_t m9_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m9_mode_ctrl_reg_t;
-
-/** Type of m10_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m10_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m10_mode:2;
-        /** m10_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m10 tee configuration
-         */
-        uint32_t m10_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m10_mode_ctrl_reg_t;
-
-/** Type of m11_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m11_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m11_mode:2;
-        /** m11_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m11 tee configuration
-         */
-        uint32_t m11_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m11_mode_ctrl_reg_t;
-
-/** Type of m12_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m12_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m12_mode:2;
-        /** m12_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m12 tee configuration
-         */
-        uint32_t m12_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m12_mode_ctrl_reg_t;
-
-/** Type of m13_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m13_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m13_mode:2;
-        /** m13_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m13 tee configuration
-         */
-        uint32_t m13_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m13_mode_ctrl_reg_t;
-
-/** Type of m14_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m14_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m14_mode:2;
-        /** m14_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m14 tee configuration
-         */
-        uint32_t m14_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m14_mode_ctrl_reg_t;
-
-/** Type of m15_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m15_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m15_mode:2;
-        /** m15_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m15 tee configuration
-         */
-        uint32_t m15_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m15_mode_ctrl_reg_t;
-
-/** Type of m16_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m16_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m16_mode:2;
-        /** m16_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m16 tee configuration
-         */
-        uint32_t m16_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m16_mode_ctrl_reg_t;
-
-/** Type of m17_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m17_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m17_mode:2;
-        /** m17_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m17 tee configuration
-         */
-        uint32_t m17_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m17_mode_ctrl_reg_t;
-
-/** Type of m18_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m18_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m18_mode:2;
-        /** m18_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m18 tee configuration
-         */
-        uint32_t m18_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m18_mode_ctrl_reg_t;
-
-/** Type of m19_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m19_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m19_mode:2;
-        /** m19_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m19 tee configuration
-         */
-        uint32_t m19_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m19_mode_ctrl_reg_t;
-
-/** Type of m20_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m20_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m20_mode:2;
-        /** m20_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m20 tee configuration
-         */
-        uint32_t m20_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m20_mode_ctrl_reg_t;
-
-/** Type of m21_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m21_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m21_mode:2;
-        /** m21_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m21 tee configuration
-         */
-        uint32_t m21_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m21_mode_ctrl_reg_t;
-
-/** Type of m22_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m22_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m22_mode:2;
-        /** m22_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m22 tee configuration
-         */
-        uint32_t m22_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m22_mode_ctrl_reg_t;
-
-/** Type of m23_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m23_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m23_mode:2;
-        /** m23_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m23 tee configuration
-         */
-        uint32_t m23_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m23_mode_ctrl_reg_t;
-
-/** Type of m24_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m24_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m24_mode:2;
-        /** m24_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m24 tee configuration
-         */
-        uint32_t m24_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m24_mode_ctrl_reg_t;
-
-/** Type of m25_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m25_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m25_mode:2;
-        /** m25_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m25 tee configuration
-         */
-        uint32_t m25_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m25_mode_ctrl_reg_t;
-
-/** Type of m26_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m26_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m26_mode:2;
-        /** m26_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m26 tee configuration
-         */
-        uint32_t m26_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m26_mode_ctrl_reg_t;
-
-/** Type of m27_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m27_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m27_mode:2;
-        /** m27_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m27 tee configuration
-         */
-        uint32_t m27_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m27_mode_ctrl_reg_t;
-
-/** Type of m28_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m28_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m28_mode:2;
-        /** m28_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m28 tee configuration
-         */
-        uint32_t m28_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m28_mode_ctrl_reg_t;
-
-/** Type of m29_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m29_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m29_mode:2;
-        /** m29_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m29 tee configuration
-         */
-        uint32_t m29_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m29_mode_ctrl_reg_t;
-
-/** Type of m30_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m30_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m30_mode:2;
-        /** m30_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m30 tee configuration
-         */
-        uint32_t m30_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m30_mode_ctrl_reg_t;
-
-/** Type of m31_mode_ctrl register
- *  Tee mode control register
- */
-typedef union {
-    struct {
-        /** m31_mode : R/W; bitpos: [1:0]; default: 3;
-         *  M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0:
-         *  tee_mode
-         */
-        uint32_t m31_mode:2;
-        /** m31_lock : R/W; bitpos: [2]; default: 0;
-         *  Set 1 to lock m31 tee configuration
-         */
-        uint32_t m31_lock:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} tee_m31_mode_ctrl_reg_t;
-
-
-/** Group: clock gating register */
-/** Type of clock_gate register
- *  Clock gating register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  reg_clk_en
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} tee_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date_reg : R/W; bitpos: [27:0]; default: 35725664;
-         *  reg_tee_date
-         */
-        uint32_t date_reg:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} tee_date_reg_t;
-
-
-typedef struct tee_dev_t {
-    volatile tee_m0_mode_ctrl_reg_t m0_mode_ctrl;
-    volatile tee_m1_mode_ctrl_reg_t m1_mode_ctrl;
-    volatile tee_m2_mode_ctrl_reg_t m2_mode_ctrl;
-    volatile tee_m3_mode_ctrl_reg_t m3_mode_ctrl;
-    volatile tee_m4_mode_ctrl_reg_t m4_mode_ctrl;
-    volatile tee_m5_mode_ctrl_reg_t m5_mode_ctrl;
-    volatile tee_m6_mode_ctrl_reg_t m6_mode_ctrl;
-    volatile tee_m7_mode_ctrl_reg_t m7_mode_ctrl;
-    volatile tee_m8_mode_ctrl_reg_t m8_mode_ctrl;
-    volatile tee_m9_mode_ctrl_reg_t m9_mode_ctrl;
-    volatile tee_m10_mode_ctrl_reg_t m10_mode_ctrl;
-    volatile tee_m11_mode_ctrl_reg_t m11_mode_ctrl;
-    volatile tee_m12_mode_ctrl_reg_t m12_mode_ctrl;
-    volatile tee_m13_mode_ctrl_reg_t m13_mode_ctrl;
-    volatile tee_m14_mode_ctrl_reg_t m14_mode_ctrl;
-    volatile tee_m15_mode_ctrl_reg_t m15_mode_ctrl;
-    volatile tee_m16_mode_ctrl_reg_t m16_mode_ctrl;
-    volatile tee_m17_mode_ctrl_reg_t m17_mode_ctrl;
-    volatile tee_m18_mode_ctrl_reg_t m18_mode_ctrl;
-    volatile tee_m19_mode_ctrl_reg_t m19_mode_ctrl;
-    volatile tee_m20_mode_ctrl_reg_t m20_mode_ctrl;
-    volatile tee_m21_mode_ctrl_reg_t m21_mode_ctrl;
-    volatile tee_m22_mode_ctrl_reg_t m22_mode_ctrl;
-    volatile tee_m23_mode_ctrl_reg_t m23_mode_ctrl;
-    volatile tee_m24_mode_ctrl_reg_t m24_mode_ctrl;
-    volatile tee_m25_mode_ctrl_reg_t m25_mode_ctrl;
-    volatile tee_m26_mode_ctrl_reg_t m26_mode_ctrl;
-    volatile tee_m27_mode_ctrl_reg_t m27_mode_ctrl;
-    volatile tee_m28_mode_ctrl_reg_t m28_mode_ctrl;
-    volatile tee_m29_mode_ctrl_reg_t m29_mode_ctrl;
-    volatile tee_m30_mode_ctrl_reg_t m30_mode_ctrl;
-    volatile tee_m31_mode_ctrl_reg_t m31_mode_ctrl;
-    volatile tee_clock_gate_reg_t clock_gate;
-    uint32_t reserved_084[990];
-    volatile tee_date_reg_t date;
-} tee_dev_t;
-
-extern tee_dev_t TEE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/timer_group_reg.h b/components/soc/esp32c5/beta3/include/soc/timer_group_reg.h
deleted file mode 100644
index 97a10ff9f0..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/timer_group_reg.h
+++ /dev/null
@@ -1,538 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TIMG_T0CONFIG_REG register
- *  Timer 0 configuration register
- */
-#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
-/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
- *  When set, the alarm is enabled. This bit is automatically cleared once an
- *  alarm occurs.
- */
-#define TIMG_T0_ALARM_EN    (BIT(10))
-#define TIMG_T0_ALARM_EN_M  (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
-#define TIMG_T0_ALARM_EN_V  0x00000001U
-#define TIMG_T0_ALARM_EN_S  10
-/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
- *  When set, Timer 0 's clock divider counter will be reset.
- */
-#define TIMG_T0_DIVCNT_RST    (BIT(12))
-#define TIMG_T0_DIVCNT_RST_M  (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
-#define TIMG_T0_DIVCNT_RST_V  0x00000001U
-#define TIMG_T0_DIVCNT_RST_S  12
-/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
- *  Timer 0 clock (T0_clk) prescaler value.
- */
-#define TIMG_T0_DIVIDER    0x0000FFFFU
-#define TIMG_T0_DIVIDER_M  (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
-#define TIMG_T0_DIVIDER_V  0x0000FFFFU
-#define TIMG_T0_DIVIDER_S  13
-/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
- *  When set, timer 0 auto-reload at alarm is enabled.
- */
-#define TIMG_T0_AUTORELOAD    (BIT(29))
-#define TIMG_T0_AUTORELOAD_M  (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
-#define TIMG_T0_AUTORELOAD_V  0x00000001U
-#define TIMG_T0_AUTORELOAD_S  29
-/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
- *  When set, the timer 0 time-base counter will increment every clock tick. When
- *  cleared, the timer 0 time-base counter will decrement.
- */
-#define TIMG_T0_INCREASE    (BIT(30))
-#define TIMG_T0_INCREASE_M  (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
-#define TIMG_T0_INCREASE_V  0x00000001U
-#define TIMG_T0_INCREASE_S  30
-/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
- *  When set, the timer 0 time-base counter is enabled.
- */
-#define TIMG_T0_EN    (BIT(31))
-#define TIMG_T0_EN_M  (TIMG_T0_EN_V << TIMG_T0_EN_S)
-#define TIMG_T0_EN_V  0x00000001U
-#define TIMG_T0_EN_S  31
-
-/** TIMG_T0LO_REG register
- *  Timer 0 current value, low 32 bits
- */
-#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
-/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
- *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
- *  of timer 0 can be read here.
- */
-#define TIMG_T0_LO    0xFFFFFFFFU
-#define TIMG_T0_LO_M  (TIMG_T0_LO_V << TIMG_T0_LO_S)
-#define TIMG_T0_LO_V  0xFFFFFFFFU
-#define TIMG_T0_LO_S  0
-
-/** TIMG_T0HI_REG register
- *  Timer 0 current value, high 22 bits
- */
-#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
-/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
- *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
- *  of timer 0 can be read here.
- */
-#define TIMG_T0_HI    0x003FFFFFU
-#define TIMG_T0_HI_M  (TIMG_T0_HI_V << TIMG_T0_HI_S)
-#define TIMG_T0_HI_V  0x003FFFFFU
-#define TIMG_T0_HI_S  0
-
-/** TIMG_T0UPDATE_REG register
- *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
- */
-#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
-/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
- *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
- */
-#define TIMG_T0_UPDATE    (BIT(31))
-#define TIMG_T0_UPDATE_M  (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
-#define TIMG_T0_UPDATE_V  0x00000001U
-#define TIMG_T0_UPDATE_S  31
-
-/** TIMG_T0ALARMLO_REG register
- *  Timer 0 alarm value, low 32 bits
- */
-#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
-/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
- *  Timer 0 alarm trigger time-base counter value, low 32 bits.
- */
-#define TIMG_T0_ALARM_LO    0xFFFFFFFFU
-#define TIMG_T0_ALARM_LO_M  (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
-#define TIMG_T0_ALARM_LO_V  0xFFFFFFFFU
-#define TIMG_T0_ALARM_LO_S  0
-
-/** TIMG_T0ALARMHI_REG register
- *  Timer 0 alarm value, high bits
- */
-#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
-/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
- *  Timer 0 alarm trigger time-base counter value, high 22 bits.
- */
-#define TIMG_T0_ALARM_HI    0x003FFFFFU
-#define TIMG_T0_ALARM_HI_M  (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
-#define TIMG_T0_ALARM_HI_V  0x003FFFFFU
-#define TIMG_T0_ALARM_HI_S  0
-
-/** TIMG_T0LOADLO_REG register
- *  Timer 0 reload value, low 32 bits
- */
-#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
-/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  Low 32 bits of the value that a reload will load onto timer 0 time-base
- *  Counter.
- */
-#define TIMG_T0_LOAD_LO    0xFFFFFFFFU
-#define TIMG_T0_LOAD_LO_M  (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
-#define TIMG_T0_LOAD_LO_V  0xFFFFFFFFU
-#define TIMG_T0_LOAD_LO_S  0
-
-/** TIMG_T0LOADHI_REG register
- *  Timer 0 reload value, high 22 bits
- */
-#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
-/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
- *  High 22 bits of the value that a reload will load onto timer 0 time-base
- *  counter.
- */
-#define TIMG_T0_LOAD_HI    0x003FFFFFU
-#define TIMG_T0_LOAD_HI_M  (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
-#define TIMG_T0_LOAD_HI_V  0x003FFFFFU
-#define TIMG_T0_LOAD_HI_S  0
-
-/** TIMG_T0LOAD_REG register
- *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
- */
-#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
-/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
- *
- *  Write any value to trigger a timer 0 time-base counter reload.
- */
-#define TIMG_T0_LOAD    0xFFFFFFFFU
-#define TIMG_T0_LOAD_M  (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
-#define TIMG_T0_LOAD_V  0xFFFFFFFFU
-#define TIMG_T0_LOAD_S  0
-
-/** TIMG_WDTCONFIG0_REG register
- *  Watchdog timer configuration register
- */
-#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
-/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
- *  WDT reset CPU enable.
- */
-#define TIMG_WDT_APPCPU_RESET_EN    (BIT(12))
-#define TIMG_WDT_APPCPU_RESET_EN_M  (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
-#define TIMG_WDT_APPCPU_RESET_EN_V  0x00000001U
-#define TIMG_WDT_APPCPU_RESET_EN_S  12
-/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
- *  WDT reset CPU enable.
- */
-#define TIMG_WDT_PROCPU_RESET_EN    (BIT(13))
-#define TIMG_WDT_PROCPU_RESET_EN_M  (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
-#define TIMG_WDT_PROCPU_RESET_EN_V  0x00000001U
-#define TIMG_WDT_PROCPU_RESET_EN_S  13
-/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
- *  When set, Flash boot protection is enabled.
- */
-#define TIMG_WDT_FLASHBOOT_MOD_EN    (BIT(14))
-#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
-#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x00000001U
-#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
-/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
- *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
- *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
- */
-#define TIMG_WDT_SYS_RESET_LENGTH    0x00000007U
-#define TIMG_WDT_SYS_RESET_LENGTH_M  (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
-#define TIMG_WDT_SYS_RESET_LENGTH_V  0x00000007U
-#define TIMG_WDT_SYS_RESET_LENGTH_S  15
-/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
- *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
- *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
- */
-#define TIMG_WDT_CPU_RESET_LENGTH    0x00000007U
-#define TIMG_WDT_CPU_RESET_LENGTH_M  (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
-#define TIMG_WDT_CPU_RESET_LENGTH_V  0x00000007U
-#define TIMG_WDT_CPU_RESET_LENGTH_S  18
-/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
- *  update the WDT configuration registers
- */
-#define TIMG_WDT_CONF_UPDATE_EN    (BIT(22))
-#define TIMG_WDT_CONF_UPDATE_EN_M  (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
-#define TIMG_WDT_CONF_UPDATE_EN_V  0x00000001U
-#define TIMG_WDT_CONF_UPDATE_EN_S  22
-/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
- *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG3    0x00000003U
-#define TIMG_WDT_STG3_M  (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
-#define TIMG_WDT_STG3_V  0x00000003U
-#define TIMG_WDT_STG3_S  23
-/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
- *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG2    0x00000003U
-#define TIMG_WDT_STG2_M  (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
-#define TIMG_WDT_STG2_V  0x00000003U
-#define TIMG_WDT_STG2_S  25
-/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
- *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG1    0x00000003U
-#define TIMG_WDT_STG1_M  (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
-#define TIMG_WDT_STG1_V  0x00000003U
-#define TIMG_WDT_STG1_S  27
-/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
- *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
- */
-#define TIMG_WDT_STG0    0x00000003U
-#define TIMG_WDT_STG0_M  (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
-#define TIMG_WDT_STG0_V  0x00000003U
-#define TIMG_WDT_STG0_S  29
-/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
- *  When set, MWDT is enabled.
- */
-#define TIMG_WDT_EN    (BIT(31))
-#define TIMG_WDT_EN_M  (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
-#define TIMG_WDT_EN_V  0x00000001U
-#define TIMG_WDT_EN_S  31
-
-/** TIMG_WDTCONFIG1_REG register
- *  Watchdog timer prescaler register
- */
-#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
-/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
- *  When set, WDT 's clock divider counter will be reset.
- */
-#define TIMG_WDT_DIVCNT_RST    (BIT(0))
-#define TIMG_WDT_DIVCNT_RST_M  (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
-#define TIMG_WDT_DIVCNT_RST_V  0x00000001U
-#define TIMG_WDT_DIVCNT_RST_S  0
-/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
- *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
- *  TIMG_WDT_CLK_PRESCALE.
- */
-#define TIMG_WDT_CLK_PRESCALE    0x0000FFFFU
-#define TIMG_WDT_CLK_PRESCALE_M  (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
-#define TIMG_WDT_CLK_PRESCALE_V  0x0000FFFFU
-#define TIMG_WDT_CLK_PRESCALE_S  16
-
-/** TIMG_WDTCONFIG2_REG register
- *  Watchdog timer stage 0 timeout value
- */
-#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
-/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
- *  Stage 0 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG0_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG0_HOLD_M  (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
-#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG0_HOLD_S  0
-
-/** TIMG_WDTCONFIG3_REG register
- *  Watchdog timer stage 1 timeout value
- */
-#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
-/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
- *  Stage 1 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG1_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG1_HOLD_M  (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
-#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG1_HOLD_S  0
-
-/** TIMG_WDTCONFIG4_REG register
- *  Watchdog timer stage 2 timeout value
- */
-#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
-/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
- *  Stage 2 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG2_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG2_HOLD_M  (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
-#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG2_HOLD_S  0
-
-/** TIMG_WDTCONFIG5_REG register
- *  Watchdog timer stage 3 timeout value
- */
-#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
-/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
- *  Stage 3 timeout value, in MWDT clock cycles.
- */
-#define TIMG_WDT_STG3_HOLD    0xFFFFFFFFU
-#define TIMG_WDT_STG3_HOLD_M  (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
-#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFFU
-#define TIMG_WDT_STG3_HOLD_S  0
-
-/** TIMG_WDTFEED_REG register
- *  Write to feed the watchdog timer
- */
-#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
-/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
- *  Write any value to feed the MWDT. (WO)
- */
-#define TIMG_WDT_FEED    0xFFFFFFFFU
-#define TIMG_WDT_FEED_M  (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
-#define TIMG_WDT_FEED_V  0xFFFFFFFFU
-#define TIMG_WDT_FEED_S  0
-
-/** TIMG_WDTWPROTECT_REG register
- *  Watchdog write protect register
- */
-#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
-/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
- *  If the register contains a different value than its reset value, write
- *  protection is enabled.
- */
-#define TIMG_WDT_WKEY    0xFFFFFFFFU
-#define TIMG_WDT_WKEY_M  (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
-#define TIMG_WDT_WKEY_V  0xFFFFFFFFU
-#define TIMG_WDT_WKEY_S  0
-
-/** TIMG_RTCCALICFG_REG register
- *  RTC calibration configure register
- */
-#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
-/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
- *  0: one-shot frequency calculation,1: periodic frequency calculation,
- */
-#define TIMG_RTC_CALI_START_CYCLING    (BIT(12))
-#define TIMG_RTC_CALI_START_CYCLING_M  (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
-#define TIMG_RTC_CALI_START_CYCLING_V  0x00000001U
-#define TIMG_RTC_CALI_START_CYCLING_S  12
-/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
- *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
- */
-#define TIMG_RTC_CALI_CLK_SEL    0x00000003U
-#define TIMG_RTC_CALI_CLK_SEL_M  (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
-#define TIMG_RTC_CALI_CLK_SEL_V  0x00000003U
-#define TIMG_RTC_CALI_CLK_SEL_S  13
-/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
- *  indicate one-shot frequency calculation is done.
- */
-#define TIMG_RTC_CALI_RDY    (BIT(15))
-#define TIMG_RTC_CALI_RDY_M  (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
-#define TIMG_RTC_CALI_RDY_V  0x00000001U
-#define TIMG_RTC_CALI_RDY_S  15
-/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
- *  Configure the time to calculate RTC slow clock's frequency.
- */
-#define TIMG_RTC_CALI_MAX    0x00007FFFU
-#define TIMG_RTC_CALI_MAX_M  (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
-#define TIMG_RTC_CALI_MAX_V  0x00007FFFU
-#define TIMG_RTC_CALI_MAX_S  16
-/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start one-shot frequency calculation.
- */
-#define TIMG_RTC_CALI_START    (BIT(31))
-#define TIMG_RTC_CALI_START_M  (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
-#define TIMG_RTC_CALI_START_V  0x00000001U
-#define TIMG_RTC_CALI_START_S  31
-
-/** TIMG_RTCCALICFG1_REG register
- *  RTC calibration configure1 register
- */
-#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
-/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
- *  indicate periodic frequency calculation is done.
- */
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD    (BIT(0))
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x00000001U
-#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
-/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
- *  When one-shot or periodic frequency calculation is done, read this value to
- *  calculate RTC slow clock's frequency.
- */
-#define TIMG_RTC_CALI_VALUE    0x01FFFFFFU
-#define TIMG_RTC_CALI_VALUE_M  (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
-#define TIMG_RTC_CALI_VALUE_V  0x01FFFFFFU
-#define TIMG_RTC_CALI_VALUE_S  7
-
-/** TIMG_INT_ENA_TIMERS_REG register
- *  Interrupt enable bits
- */
-#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
-/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_ENA    (BIT(0))
-#define TIMG_T0_INT_ENA_M  (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
-#define TIMG_T0_INT_ENA_V  0x00000001U
-#define TIMG_T0_INT_ENA_S  0
-/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_ENA    (BIT(2))
-#define TIMG_WDT_INT_ENA_M  (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
-#define TIMG_WDT_INT_ENA_V  0x00000001U
-#define TIMG_WDT_INT_ENA_S  2
-
-/** TIMG_INT_RAW_TIMERS_REG register
- *  Raw interrupt status
- */
-#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
-/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_RAW    (BIT(0))
-#define TIMG_T0_INT_RAW_M  (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
-#define TIMG_T0_INT_RAW_V  0x00000001U
-#define TIMG_T0_INT_RAW_S  0
-/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_RAW    (BIT(2))
-#define TIMG_WDT_INT_RAW_M  (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
-#define TIMG_WDT_INT_RAW_V  0x00000001U
-#define TIMG_WDT_INT_RAW_S  2
-
-/** TIMG_INT_ST_TIMERS_REG register
- *  Masked interrupt status
- */
-#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
-/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_ST    (BIT(0))
-#define TIMG_T0_INT_ST_M  (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
-#define TIMG_T0_INT_ST_V  0x00000001U
-#define TIMG_T0_INT_ST_S  0
-/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_ST    (BIT(2))
-#define TIMG_WDT_INT_ST_M  (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
-#define TIMG_WDT_INT_ST_V  0x00000001U
-#define TIMG_WDT_INT_ST_S  2
-
-/** TIMG_INT_CLR_TIMERS_REG register
- *  Interrupt clear bits
- */
-#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
-/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the TIMG_T$x_INT interrupt.
- */
-#define TIMG_T0_INT_CLR    (BIT(0))
-#define TIMG_T0_INT_CLR_M  (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
-#define TIMG_T0_INT_CLR_V  0x00000001U
-#define TIMG_T0_INT_CLR_S  0
-/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the TIMG_WDT_INT interrupt.
- */
-#define TIMG_WDT_INT_CLR    (BIT(2))
-#define TIMG_WDT_INT_CLR_M  (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
-#define TIMG_WDT_INT_CLR_V  0x00000001U
-#define TIMG_WDT_INT_CLR_S  2
-
-/** TIMG_RTCCALICFG2_REG register
- *  Timer group calibration register
- */
-#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
-/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
- *  RTC calibration timeout indicator
- */
-#define TIMG_RTC_CALI_TIMEOUT    (BIT(0))
-#define TIMG_RTC_CALI_TIMEOUT_M  (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
-#define TIMG_RTC_CALI_TIMEOUT_V  0x00000001U
-#define TIMG_RTC_CALI_TIMEOUT_S  0
-/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
- *  Cycles that release calibration timeout reset
- */
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT    0x0000000FU
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0x0000000FU
-#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
-/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
- *  Threshold value for the RTC calibration timer. If the calibration timer's value
- *  exceeds this threshold, a timeout is triggered.
- */
-#define TIMG_RTC_CALI_TIMEOUT_THRES    0x01FFFFFFU
-#define TIMG_RTC_CALI_TIMEOUT_THRES_M  (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
-#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x01FFFFFFU
-#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
-
-/** TIMG_NTIMERS_DATE_REG register
- *  Timer version control register
- */
-#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
-/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
- *  Timer version control register
- */
-#define TIMG_NTIMGS_DATE    0x0FFFFFFFU
-#define TIMG_NTIMGS_DATE_M  (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
-#define TIMG_NTIMGS_DATE_V  0x0FFFFFFFU
-#define TIMG_NTIMGS_DATE_S  0
-
-/** TIMG_REGCLK_REG register
- *  Timer group clock gate register
- */
-#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
-/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
- *  enable timer's etm task and event
- */
-#define TIMG_ETM_EN    (BIT(28))
-#define TIMG_ETM_EN_M  (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
-#define TIMG_ETM_EN_V  0x00000001U
-#define TIMG_ETM_EN_S  28
-/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
- *  Registers can not be read or written to by software.
- */
-#define TIMG_CLK_EN    (BIT(31))
-#define TIMG_CLK_EN_M  (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
-#define TIMG_CLK_EN_V  0x00000001U
-#define TIMG_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/timer_group_struct.h b/components/soc/esp32c5/beta3/include/soc/timer_group_struct.h
deleted file mode 100644
index e467a68b56..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/timer_group_struct.h
+++ /dev/null
@@ -1,556 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: T0 Control and configuration registers */
-/** Type of txconfig register
- *  Timer x configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
-         *  When set, the alarm is enabled. This bit is automatically cleared once an
-         *  alarm occurs.
-         */
-        uint32_t tx_alarm_en:1;
-        uint32_t reserved_11:1;
-        /** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
-         *  When set, Timer x 's clock divider counter will be reset.
-         */
-        uint32_t tx_divcnt_rst:1;
-        /** tx_divider : R/W; bitpos: [28:13]; default: 1;
-         *  Timer x clock (Tx_clk) prescaler value.
-         */
-        uint32_t tx_divider:16;
-        /** tx_autoreload : R/W; bitpos: [29]; default: 1;
-         *  When set, timer x auto-reload at alarm is enabled.
-         */
-        uint32_t tx_autoreload:1;
-        /** tx_increase : R/W; bitpos: [30]; default: 1;
-         *  When set, the timer x time-base counter will increment every clock tick. When
-         *  cleared, the timer x time-base counter will decrement.
-         */
-        uint32_t tx_increase:1;
-        /** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
-         *  When set, the timer x time-base counter is enabled.
-         */
-        uint32_t tx_en:1;
-    };
-    uint32_t val;
-} timg_txconfig_reg_t;
-
-/** Type of txlo register
- *  Timer x current value, low 32 bits
- */
-typedef union {
-    struct {
-        /** tx_lo : RO; bitpos: [31:0]; default: 0;
-         *  After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
-         *  of timer x can be read here.
-         */
-        uint32_t tx_lo:32;
-    };
-    uint32_t val;
-} timg_txlo_reg_t;
-
-/** Type of txhi register
- *  Timer x current value, high 22 bits
- */
-typedef union {
-    struct {
-        /** tx_hi : RO; bitpos: [21:0]; default: 0;
-         *  After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
-         *  of timer x can be read here.
-         */
-        uint32_t tx_hi:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} timg_txhi_reg_t;
-
-/** Type of txupdate register
- *  Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_update : R/W/SC; bitpos: [31]; default: 0;
-         *  After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
-         */
-        uint32_t tx_update:1;
-    };
-    uint32_t val;
-} timg_txupdate_reg_t;
-
-/** Type of txalarmlo register
- *  Timer x alarm value, low 32 bits
- */
-typedef union {
-    struct {
-        /** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
-         *  Timer x alarm trigger time-base counter value, low 32 bits.
-         */
-        uint32_t tx_alarm_lo:32;
-    };
-    uint32_t val;
-} timg_txalarmlo_reg_t;
-
-/** Type of txalarmhi register
- *  Timer x alarm value, high bits
- */
-typedef union {
-    struct {
-        /** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
-         *  Timer x alarm trigger time-base counter value, high 22 bits.
-         */
-        uint32_t tx_alarm_hi:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} timg_txalarmhi_reg_t;
-
-/** Type of txloadlo register
- *  Timer x reload value, low 32 bits
- */
-typedef union {
-    struct {
-        /** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
-         *  Low 32 bits of the value that a reload will load onto timer x time-base
-         *  Counter.
-         */
-        uint32_t tx_load_lo:32;
-    };
-    uint32_t val;
-} timg_txloadlo_reg_t;
-
-/** Type of txloadhi register
- *  Timer x reload value, high 22 bits
- */
-typedef union {
-    struct {
-        /** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
-         *  High 22 bits of the value that a reload will load onto timer x time-base
-         *  counter.
-         */
-        uint32_t tx_load_hi:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} timg_txloadhi_reg_t;
-
-/** Type of txload register
- *  Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
- */
-typedef union {
-    struct {
-        /** tx_load : WT; bitpos: [31:0]; default: 0;
-         *
-         *  Write any value to trigger a timer x time-base counter reload.
-         */
-        uint32_t tx_load:32;
-    };
-    uint32_t val;
-} timg_txload_reg_t;
-
-
-/** Group: WDT Control and configuration registers */
-/** Type of wdtconfig0 register
- *  Watchdog timer configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
-         *  WDT reset CPU enable.
-         */
-        uint32_t wdt_appcpu_reset_en:1;
-        /** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
-         *  WDT reset CPU enable.
-         */
-        uint32_t wdt_procpu_reset_en:1;
-        /** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
-         *  When set, Flash boot protection is enabled.
-         */
-        uint32_t wdt_flashboot_mod_en:1;
-        /** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
-         *  System reset signal length selection. 0: 100 ns, 1: 200 ns,
-         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
-         */
-        uint32_t wdt_sys_reset_length:3;
-        /** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
-         *  CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
-         *  2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
-         */
-        uint32_t wdt_cpu_reset_length:3;
-        uint32_t reserved_21:1;
-        /** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
-         *  update the WDT configuration registers
-         */
-        uint32_t wdt_conf_update_en:1;
-        /** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
-         *  Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg3:2;
-        /** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
-         *  Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg2:2;
-        /** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
-         *  Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg1:2;
-        /** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
-         *  Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
-         */
-        uint32_t wdt_stg0:2;
-        /** wdt_en : R/W; bitpos: [31]; default: 0;
-         *  When set, MWDT is enabled.
-         */
-        uint32_t wdt_en:1;
-    };
-    uint32_t val;
-} timg_wdtconfig0_reg_t;
-
-/** Type of wdtconfig1 register
- *  Watchdog timer prescaler register
- */
-typedef union {
-    struct {
-        /** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
-         *  When set, WDT 's clock divider counter will be reset.
-         */
-        uint32_t wdt_divcnt_rst:1;
-        uint32_t reserved_1:15;
-        /** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
-         *  MWDT clock prescaler value. MWDT clock period = 12.5 ns *
-         *  TIMG_WDT_CLK_PRESCALE.
-         */
-        uint32_t wdt_clk_prescale:16;
-    };
-    uint32_t val;
-} timg_wdtconfig1_reg_t;
-
-/** Type of wdtconfig2 register
- *  Watchdog timer stage 0 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
-         *  Stage 0 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg0_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig2_reg_t;
-
-/** Type of wdtconfig3 register
- *  Watchdog timer stage 1 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
-         *  Stage 1 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg1_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig3_reg_t;
-
-/** Type of wdtconfig4 register
- *  Watchdog timer stage 2 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
-         *  Stage 2 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg2_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig4_reg_t;
-
-/** Type of wdtconfig5 register
- *  Watchdog timer stage 3 timeout value
- */
-typedef union {
-    struct {
-        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
-         *  Stage 3 timeout value, in MWDT clock cycles.
-         */
-        uint32_t wdt_stg3_hold:32;
-    };
-    uint32_t val;
-} timg_wdtconfig5_reg_t;
-
-/** Type of wdtfeed register
- *  Write to feed the watchdog timer
- */
-typedef union {
-    struct {
-        /** wdt_feed : WT; bitpos: [31:0]; default: 0;
-         *  Write any value to feed the MWDT. (WO)
-         */
-        uint32_t wdt_feed:32;
-    };
-    uint32_t val;
-} timg_wdtfeed_reg_t;
-
-/** Type of wdtwprotect register
- *  Watchdog write protect register
- */
-typedef union {
-    struct {
-        /** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
-         *  If the register contains a different value than its reset value, write
-         *  protection is enabled.
-         */
-        uint32_t wdt_wkey:32;
-    };
-    uint32_t val;
-} timg_wdtwprotect_reg_t;
-
-
-/** Group: RTC CALI Control and configuration registers */
-/** Type of rtccalicfg register
- *  RTC calibration configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
-         *  0: one-shot frequency calculation,1: periodic frequency calculation,
-         */
-        uint32_t rtc_cali_start_cycling:1;
-        /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
-         */
-        uint32_t rtc_cali_clk_sel:2;
-        /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
-         *  indicate one-shot frequency calculation is done.
-         */
-        uint32_t rtc_cali_rdy:1;
-        /** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
-         *  Configure the time to calculate RTC slow clock's frequency.
-         */
-        uint32_t rtc_cali_max:15;
-        /** rtc_cali_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start one-shot frequency calculation.
-         */
-        uint32_t rtc_cali_start:1;
-    };
-    uint32_t val;
-} timg_rtccalicfg_reg_t;
-
-/** Type of rtccalicfg1 register
- *  RTC calibration configure1 register
- */
-typedef union {
-    struct {
-        /** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
-         *  indicate periodic frequency calculation is done.
-         */
-        uint32_t rtc_cali_cycling_data_vld:1;
-        uint32_t reserved_1:6;
-        /** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
-         *  When one-shot or periodic frequency calculation is done, read this value to
-         *  calculate RTC slow clock's frequency.
-         */
-        uint32_t rtc_cali_value:25;
-    };
-    uint32_t val;
-} timg_rtccalicfg1_reg_t;
-
-/** Type of rtccalicfg2 register
- *  Timer group calibration register
- */
-typedef union {
-    struct {
-        /** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
-         *  RTC calibration timeout indicator
-         */
-        uint32_t rtc_cali_timeout:1;
-        uint32_t reserved_1:2;
-        /** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
-         *  Cycles that release calibration timeout reset
-         */
-        uint32_t rtc_cali_timeout_rst_cnt:4;
-        /** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
-         *  Threshold value for the RTC calibration timer. If the calibration timer's value
-         *  exceeds this threshold, a timeout is triggered.
-         */
-        uint32_t rtc_cali_timeout_thres:25;
-    };
-    uint32_t val;
-} timg_rtccalicfg2_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_ena_timers register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** t0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_ena:1;
-        uint32_t reserved_1:1;
-        /** wdt_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_ena_timers_reg_t;
-
-/** Type of int_raw_timers register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_raw:1;
-        uint32_t reserved_1:1;
-        /** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_raw_timers_reg_t;
-
-/** Type of int_st_timers register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** t0_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_st:1;
-        uint32_t reserved_1:1;
-        /** wdt_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit for the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_st_timers_reg_t;
-
-/** Type of int_clr_timers register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** t0_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the TIMG_T$x_INT interrupt.
-         */
-        uint32_t t0_int_clr:1;
-        uint32_t reserved_1:1;
-        /** wdt_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the TIMG_WDT_INT interrupt.
-         */
-        uint32_t wdt_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} timg_int_clr_timers_reg_t;
-
-
-/** Group: Version register */
-/** Type of ntimers_date register
- *  Timer version control register
- */
-typedef union {
-    struct {
-        /** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
-         *  Timer version control register
-         */
-        uint32_t ntimgs_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} timg_ntimers_date_reg_t;
-
-
-/** Group: Clock configuration registers */
-/** Type of regclk register
- *  Timer group clock gate register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** etm_en : R/W; bitpos: [28]; default: 1;
-         *  enable timer's etm task and event
-         */
-        uint32_t etm_en:1;
-        uint32_t reserved_29:2;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Register clock gate signal. 1: Registers can be read and written to by software. 0:
-         *  Registers can not be read or written to by software.
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} timg_regclk_reg_t;
-
-
-typedef struct {
-    volatile timg_txconfig_reg_t config;
-    volatile timg_txlo_reg_t lo;
-    volatile timg_txhi_reg_t hi;
-    volatile timg_txupdate_reg_t update;
-    volatile timg_txalarmlo_reg_t alarmlo;
-    volatile timg_txalarmhi_reg_t alarmhi;
-    volatile timg_txloadlo_reg_t loadlo;
-    volatile timg_txloadhi_reg_t loadhi;
-    volatile timg_txload_reg_t load;
-} timg_hwtimer_reg_t;
-
-typedef struct timg_dev_t {
-    volatile timg_hwtimer_reg_t hw_timer[1];
-    uint32_t reserved_024[9];
-    volatile timg_wdtconfig0_reg_t wdtconfig0;
-    volatile timg_wdtconfig1_reg_t wdtconfig1;
-    volatile timg_wdtconfig2_reg_t wdtconfig2;
-    volatile timg_wdtconfig3_reg_t wdtconfig3;
-    volatile timg_wdtconfig4_reg_t wdtconfig4;
-    volatile timg_wdtconfig5_reg_t wdtconfig5;
-    volatile timg_wdtfeed_reg_t wdtfeed;
-    volatile timg_wdtwprotect_reg_t wdtwprotect;
-    volatile timg_rtccalicfg_reg_t rtccalicfg;
-    volatile timg_rtccalicfg1_reg_t rtccalicfg1;
-    volatile timg_int_ena_timers_reg_t int_ena_timers;
-    volatile timg_int_raw_timers_reg_t int_raw_timers;
-    volatile timg_int_st_timers_reg_t int_st_timers;
-    volatile timg_int_clr_timers_reg_t int_clr_timers;
-    volatile timg_rtccalicfg2_reg_t rtccalicfg2;
-    uint32_t reserved_084[29];
-    volatile timg_ntimers_date_reg_t ntimers_date;
-    volatile timg_regclk_reg_t regclk;
-} timg_dev_t;
-
-extern timg_dev_t TIMERG0;
-extern timg_dev_t TIMERG1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/trace_reg.h b/components/soc/esp32c5/beta3/include/soc/trace_reg.h
deleted file mode 100644
index c0f45143e9..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/trace_reg.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TRACE_MEM_START_ADDR_REG register
- *  mem start addr
- */
-#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
-/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  The start address of trace memory
- */
-#define TRACE_MEM_START_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_START_ADDR_M  (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
-#define TRACE_MEM_START_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_START_ADDR_S  0
-
-/** TRACE_MEM_END_ADDR_REG register
- *  mem end addr
- */
-#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
-/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  The end address of trace memory
- */
-#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
-#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_S  0
-
-/** TRACE_MEM_CURRENT_ADDR_REG register
- *  mem current addr
- */
-#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
-/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  current_mem_addr,indicate that next writing addr
- */
-#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
-#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_S  0
-
-/** TRACE_MEM_ADDR_UPDATE_REG register
- *  mem addr update
- */
-#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
-/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
- *  when set, the  will
- *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
- *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
- */
-#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
-
-/** TRACE_FIFO_STATUS_REG register
- *  fifo status register
- */
-#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
-/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  Represent whether the fifo is empty. \\1: empty \\0: not empty
- */
-#define TRACE_FIFO_EMPTY    (BIT(0))
-#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
-#define TRACE_FIFO_EMPTY_V  0x00000001U
-#define TRACE_FIFO_EMPTY_S  0
-/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
- *  Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due
- *  to hart halted or havereset \\3: lost state
- */
-#define TRACE_WORK_STATUS    0x00000003U
-#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
-#define TRACE_WORK_STATUS_V  0x00000003U
-#define TRACE_WORK_STATUS_S  1
-
-/** TRACE_INTR_ENA_REG register
- *  interrupt enable register
- */
-#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
-/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
- *  Set 1 enable fifo_overflow interrupt
- */
-#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
-/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
- *  Set 1 enable mem_full interrupt
- */
-#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
-#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
-#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_ENA_S  1
-
-/** TRACE_INTR_RAW_REG register
- *  interrupt status register
- */
-#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
-/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
- *  fifo_overflow interrupt status
- */
-#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
-/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
- *  mem_full interrupt status
- */
-#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
-#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
-#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_RAW_S  1
-
-/** TRACE_INTR_CLR_REG register
- *  interrupt clear register
- */
-#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
-/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
- *  Set 1 clear fifo overflow interrupt
- */
-#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
-/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
- *  Set 1 clear mem full interrupt
- */
-#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
-#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
-#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_CLR_S  1
-
-/** TRACE_TRIGGER_REG register
- *  trigger register
- */
-#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
-/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
- *  Configure whether or not start trace.\\1: start trace \\0: invalid\\
- */
-#define TRACE_TRIGGER_ON    (BIT(0))
-#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
-#define TRACE_TRIGGER_ON_V  0x00000001U
-#define TRACE_TRIGGER_ON_S  0
-/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
- *  Configure whether or not stop trace.\\1: stop trace \\0: invalid\\
- */
-#define TRACE_TRIGGER_OFF    (BIT(1))
-#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
-#define TRACE_TRIGGER_OFF_V  0x00000001U
-#define TRACE_TRIGGER_OFF_S  1
-/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
- *  Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when
- *  mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\
- */
-#define TRACE_MEM_LOOP    (BIT(2))
-#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
-#define TRACE_MEM_LOOP_V  0x00000001U
-#define TRACE_MEM_LOOP_S  2
-/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
- *  Configure whether or not enable auto-restart.\\1: enable\\0: disable\\
- */
-#define TRACE_RESTART_ENA    (BIT(3))
-#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
-#define TRACE_RESTART_ENA_V  0x00000001U
-#define TRACE_RESTART_ENA_S  3
-
-/** TRACE_CONFIG_REG register
- *  trace configuration register
- */
-#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24)
-/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
- *  Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\
- */
-#define TRACE_DM_TRIGGER_ENA    (BIT(0))
-#define TRACE_DM_TRIGGER_ENA_M  (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
-#define TRACE_DM_TRIGGER_ENA_V  0x00000001U
-#define TRACE_DM_TRIGGER_ENA_S  0
-/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
- *  Configure whether or not enable trace cpu haverest, when enabeld, if cpu have
- *  reset, the encoder will output a packet to report the address of the last
- *  instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0:
- *  disabled\\
- */
-#define TRACE_RESET_ENA    (BIT(1))
-#define TRACE_RESET_ENA_M  (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
-#define TRACE_RESET_ENA_V  0x00000001U
-#define TRACE_RESET_ENA_S  1
-/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
- *  Configure whether or not enable trace cpu is halted, when enabeld, if the cpu
- *  halted, the encoder will output a packet to report the address of the last
- *  instruction, and upon halted deassertion, the encoder start again.When disabled,
- *  encoder will not report the last address before halted and first address after
- *  halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\
- */
-#define TRACE_HALT_ENA    (BIT(2))
-#define TRACE_HALT_ENA_M  (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
-#define TRACE_HALT_ENA_V  0x00000001U
-#define TRACE_HALT_ENA_S  2
-/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
- *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
- *  the cpu will be stalled until the packets is able to write to fifo.\\1:
- *  enabled.\\0: disabled\\
- */
-#define TRACE_STALL_ENA    (BIT(3))
-#define TRACE_STALL_ENA_M  (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
-#define TRACE_STALL_ENA_V  0x00000001U
-#define TRACE_STALL_ENA_S  3
-/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
- *  Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta
- *  address mode\\
- */
-#define TRACE_FULL_ADDRESS    (BIT(4))
-#define TRACE_FULL_ADDRESS_M  (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
-#define TRACE_FULL_ADDRESS_V  0x00000001U
-#define TRACE_FULL_ADDRESS_S  4
-/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
- *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
- *  exception address, only exception cause in exception packets.\\1: enabled\\0:
- *  disabled\\
- */
-#define TRACE_IMPLICIT_EXCEPT    (BIT(5))
-#define TRACE_IMPLICIT_EXCEPT_M  (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
-#define TRACE_IMPLICIT_EXCEPT_V  0x00000001U
-#define TRACE_IMPLICIT_EXCEPT_S  5
-
-/** TRACE_FILTER_CONTROL_REG register
- *  filter control register
- */
-#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28)
-/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
- *  Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match
- */
-#define TRACE_FILTER_EN    (BIT(0))
-#define TRACE_FILTER_EN_M  (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
-#define TRACE_FILTER_EN_V  0x00000001U
-#define TRACE_FILTER_EN_S  0
-/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
- *  when set, the comparator must be high in order for the filter to match
- */
-#define TRACE_MATCH_COMP    (BIT(1))
-#define TRACE_MATCH_COMP_M  (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
-#define TRACE_MATCH_COMP_V  0x00000001U
-#define TRACE_MATCH_COMP_S  1
-/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
- *  when set, match privilege levels specified by
- *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
- */
-#define TRACE_MATCH_PRIVILEGE    (BIT(2))
-#define TRACE_MATCH_PRIVILEGE_M  (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
-#define TRACE_MATCH_PRIVILEGE_V  0x00000001U
-#define TRACE_MATCH_PRIVILEGE_S  2
-/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
- *  when set, start matching from exception cause codes specified by
- *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
- *  matching upon return from the 1st matching exception.
- */
-#define TRACE_MATCH_ECAUSE    (BIT(3))
-#define TRACE_MATCH_ECAUSE_M  (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
-#define TRACE_MATCH_ECAUSE_V  0x00000001U
-#define TRACE_MATCH_ECAUSE_S  3
-/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
- *  when set, start matching from a trap with the interrupt level codes specified by
- *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
- *  stop matching upon return from the 1st matching trap.
- */
-#define TRACE_MATCH_INTERRUPT    (BIT(4))
-#define TRACE_MATCH_INTERRUPT_M  (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
-#define TRACE_MATCH_INTERRUPT_V  0x00000001U
-#define TRACE_MATCH_INTERRUPT_S  4
-
-/** TRACE_FILTER_MATCH_CONTROL_REG register
- *  filter match control register
- */
-#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c)
-/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
- *  Select match which privilege level when
- *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1:
- *  machine mode. \\0: user mode
- */
-#define TRACE_MATCH_CHOICE_PRIVILEGE    (BIT(0))
-#define TRACE_MATCH_CHOICE_PRIVILEGE_M  (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
-#define TRACE_MATCH_CHOICE_PRIVILEGE_V  0x00000001U
-#define TRACE_MATCH_CHOICE_PRIVILEGE_S  0
-/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
- *  Select which match which itype when
- *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match
- *  itype of 2. \\0: match itype or 1.
- */
-#define TRACE_MATCH_VALUE_INTERRUPT    (BIT(1))
-#define TRACE_MATCH_VALUE_INTERRUPT_M  (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
-#define TRACE_MATCH_VALUE_INTERRUPT_V  0x00000001U
-#define TRACE_MATCH_VALUE_INTERRUPT_S  1
-/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
- *  specified which ecause matched.
- */
-#define TRACE_MATCH_CHOICE_ECAUSE    0x0000003FU
-#define TRACE_MATCH_CHOICE_ECAUSE_M  (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
-#define TRACE_MATCH_CHOICE_ECAUSE_V  0x0000003FU
-#define TRACE_MATCH_CHOICE_ECAUSE_S  2
-
-/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
- *  filter comparator match control register
- */
-#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30)
-/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
- *  Determines which input to compare against the primary comparator, \\0: iaddr, \\1:
- *  tval.
- */
-#define TRACE_P_INPUT    (BIT(0))
-#define TRACE_P_INPUT_M  (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
-#define TRACE_P_INPUT_V  0x00000001U
-#define TRACE_P_INPUT_S  0
-/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
- *  Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than,
- *  \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other:
- *  always match
- */
-#define TRACE_P_FUNCTION    0x00000007U
-#define TRACE_P_FUNCTION_M  (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
-#define TRACE_P_FUNCTION_V  0x00000007U
-#define TRACE_P_FUNCTION_S  2
-/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
- *  Generate a trace packet explicitly reporting the address that cause the primary
- *  match
- */
-#define TRACE_P_NOTIFY    (BIT(5))
-#define TRACE_P_NOTIFY_M  (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
-#define TRACE_P_NOTIFY_V  0x00000001U
-#define TRACE_P_NOTIFY_S  5
-/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
- *  Determines which input to compare against the secondary comparator, \\0: iaddr,
- *  \\1: tval.
- */
-#define TRACE_S_INPUT    (BIT(8))
-#define TRACE_S_INPUT_M  (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
-#define TRACE_S_INPUT_V  0x00000001U
-#define TRACE_S_INPUT_S  8
-/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
- *  Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less
- *  than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal,
- *  \\other: always match
- */
-#define TRACE_S_FUNCTION    0x00000007U
-#define TRACE_S_FUNCTION_M  (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
-#define TRACE_S_FUNCTION_V  0x00000007U
-#define TRACE_S_FUNCTION_S  10
-/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
- *  Generate a trace packet explicitly reporting the address that cause the secondary
- *  match
- */
-#define TRACE_S_NOTIFY    (BIT(13))
-#define TRACE_S_NOTIFY_M  (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
-#define TRACE_S_NOTIFY_V  0x00000001U
-#define TRACE_S_NOTIFY_S  13
-/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
- *  0: only primary matches, \\1: primary and secondary comparator both
- *  matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3:
- *  set when primary matches and continue to match until after secondary comparator
- *  matches
- */
-#define TRACE_MATCH_MODE    0x00000003U
-#define TRACE_MATCH_MODE_M  (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
-#define TRACE_MATCH_MODE_V  0x00000003U
-#define TRACE_MATCH_MODE_S  16
-
-/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
- *  primary comparator match value
- */
-#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34)
-/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
- *  primary comparator match value
- */
-#define TRACE_P_MATCH    0xFFFFFFFFU
-#define TRACE_P_MATCH_M  (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
-#define TRACE_P_MATCH_V  0xFFFFFFFFU
-#define TRACE_P_MATCH_S  0
-
-/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
- *  secondary comparator match value
- */
-#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38)
-/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
- *  secondary comparator match value
- */
-#define TRACE_S_MATCH    0xFFFFFFFFU
-#define TRACE_S_MATCH_M  (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
-#define TRACE_S_MATCH_V  0xFFFFFFFFU
-#define TRACE_S_MATCH_S  0
-
-/** TRACE_RESYNC_PROLONGED_REG register
- *  resync configuration register
- */
-#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c)
-/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
- *  count number, when count to this value, send a sync package
- */
-#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
-#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_S  0
-/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
- *  resyc mode sel: \\0: off, \\2: cycle count  \\3: package num count
- */
-#define TRACE_RESYNC_MODE    0x00000003U
-#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
-#define TRACE_RESYNC_MODE_V  0x00000003U
-#define TRACE_RESYNC_MODE_S  24
-
-/** TRACE_AHB_CONFIG_REG register
- *  AHB config register
- */
-#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
-/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
- *  set hburst
- */
-#define TRACE_HBURST    0x00000007U
-#define TRACE_HBURST_M  (TRACE_HBURST_V << TRACE_HBURST_S)
-#define TRACE_HBURST_V  0x00000007U
-#define TRACE_HBURST_S  0
-/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
- *  set max continuous access for incr mode
- */
-#define TRACE_MAX_INCR    0x00000007U
-#define TRACE_MAX_INCR_M  (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
-#define TRACE_MAX_INCR_V  0x00000007U
-#define TRACE_MAX_INCR_S  3
-
-/** TRACE_CLOCK_GATE_REG register
- *  Clock gate control register
- */
-#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44)
-/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable clock gate when access all registers in this module.
- */
-#define TRACE_CLK_EN    (BIT(0))
-#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
-#define TRACE_CLK_EN_V  0x00000001U
-#define TRACE_CLK_EN_S  0
-
-/** TRACE_DATE_REG register
- *  Version control register
- */
-#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
-/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
- *  version control register. Note that this default value stored is the latest date
- *  when the hardware logic was updated.
- */
-#define TRACE_DATE    0x0FFFFFFFU
-#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
-#define TRACE_DATE_V  0x0FFFFFFFU
-#define TRACE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/trace_struct.h b/components/soc/esp32c5/beta3/include/soc/trace_struct.h
deleted file mode 100644
index 66d28f93ce..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/trace_struct.h
+++ /dev/null
@@ -1,462 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Trace memory configuration registers */
-/** Type of mem_start_addr register
- *  mem start addr
- */
-typedef union {
-    struct {
-        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  The start address of trace memory
-         */
-        uint32_t mem_start_addr:32;
-    };
-    uint32_t val;
-} trace_mem_start_addr_reg_t;
-
-/** Type of mem_end_addr register
- *  mem end addr
- */
-typedef union {
-    struct {
-        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  The end address of trace memory
-         */
-        uint32_t mem_end_addr:32;
-    };
-    uint32_t val;
-} trace_mem_end_addr_reg_t;
-
-/** Type of mem_current_addr register
- *  mem current addr
- */
-typedef union {
-    struct {
-        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
-         *  current_mem_addr,indicate that next writing addr
-         */
-        uint32_t mem_current_addr:32;
-    };
-    uint32_t val;
-} trace_mem_current_addr_reg_t;
-
-/** Type of mem_addr_update register
- *  mem addr update
- */
-typedef union {
-    struct {
-        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
-         *  when set, the  will
-         *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to
-         *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.
-         */
-        uint32_t mem_current_addr_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_mem_addr_update_reg_t;
-
-
-/** Group: Trace fifo status register */
-/** Type of fifo_status register
- *  fifo status register
- */
-typedef union {
-    struct {
-        /** fifo_empty : RO; bitpos: [0]; default: 1;
-         *  Represent whether the fifo is empty. \\1: empty \\0: not empty
-         */
-        uint32_t fifo_empty:1;
-        /** work_status : RO; bitpos: [2:1]; default: 0;
-         *  Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due
-         *  to hart halted or havereset \\3: lost state
-         */
-        uint32_t work_status:2;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} trace_fifo_status_reg_t;
-
-
-/** Group: Trace interrupt configuration registers */
-/** Type of intr_ena register
- *  interrupt enable register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
-         *  Set 1 enable fifo_overflow interrupt
-         */
-        uint32_t fifo_overflow_intr_ena:1;
-        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
-         *  Set 1 enable mem_full interrupt
-         */
-        uint32_t mem_full_intr_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_ena_reg_t;
-
-/** Type of intr_raw register
- *  interrupt status register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
-         *  fifo_overflow interrupt status
-         */
-        uint32_t fifo_overflow_intr_raw:1;
-        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
-         *  mem_full interrupt status
-         */
-        uint32_t mem_full_intr_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_raw_reg_t;
-
-/** Type of intr_clr register
- *  interrupt clear register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
-         *  Set 1 clear fifo overflow interrupt
-         */
-        uint32_t fifo_overflow_intr_clr:1;
-        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
-         *  Set 1 clear mem full interrupt
-         */
-        uint32_t mem_full_intr_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_clr_reg_t;
-
-
-/** Group: Trace configuration register */
-/** Type of trigger register
- *  trigger register
- */
-typedef union {
-    struct {
-        /** trigger_on : WT; bitpos: [0]; default: 0;
-         *  Configure whether or not start trace.\\1: start trace \\0: invalid\\
-         */
-        uint32_t trigger_on:1;
-        /** trigger_off : WT; bitpos: [1]; default: 0;
-         *  Configure whether or not stop trace.\\1: stop trace \\0: invalid\\
-         */
-        uint32_t trigger_off:1;
-        /** mem_loop : R/W; bitpos: [2]; default: 1;
-         *  Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when
-         *  mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\
-         */
-        uint32_t mem_loop:1;
-        /** restart_ena : R/W; bitpos: [3]; default: 1;
-         *  Configure whether or not enable auto-restart.\\1: enable\\0: disable\\
-         */
-        uint32_t restart_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} trace_trigger_reg_t;
-
-/** Type of config register
- *  trace configuration register
- */
-typedef union {
-    struct {
-        /** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
-         *  Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\
-         */
-        uint32_t dm_trigger_ena:1;
-        /** reset_ena : R/W; bitpos: [1]; default: 0;
-         *  Configure whether or not enable trace cpu haverest, when enabeld, if cpu have
-         *  reset, the encoder will output a packet to report the address of the last
-         *  instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0:
-         *  disabled\\
-         */
-        uint32_t reset_ena:1;
-        /** halt_ena : R/W; bitpos: [2]; default: 0;
-         *  Configure whether or not enable trace cpu is halted, when enabeld, if the cpu
-         *  halted, the encoder will output a packet to report the address of the last
-         *  instruction, and upon halted deassertion, the encoder start again.When disabled,
-         *  encoder will not report the last address before halted and first address after
-         *  halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\
-         */
-        uint32_t halt_ena:1;
-        /** stall_ena : R/W; bitpos: [3]; default: 0;
-         *  Configure whether or not enable stall cpu. When enabled, when the fifo almost full,
-         *  the cpu will be stalled until the packets is able to write to fifo.\\1:
-         *  enabled.\\0: disabled\\
-         */
-        uint32_t stall_ena:1;
-        /** full_address : R/W; bitpos: [4]; default: 0;
-         *  Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta
-         *  address mode\\
-         */
-        uint32_t full_address:1;
-        /** implicit_except : R/W; bitpos: [5]; default: 0;
-         *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
-         *  exception address, only exception cause in exception packets.\\1: enabled\\0:
-         *  disabled\\
-         */
-        uint32_t implicit_except:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} trace_config_reg_t;
-
-/** Type of filter_control register
- *  filter control register
- */
-typedef union {
-    struct {
-        /** filter_en : R/W; bitpos: [0]; default: 0;
-         *  Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match
-         */
-        uint32_t filter_en:1;
-        /** match_comp : R/W; bitpos: [1]; default: 0;
-         *  when set, the comparator must be high in order for the filter to match
-         */
-        uint32_t match_comp:1;
-        /** match_privilege : R/W; bitpos: [2]; default: 0;
-         *  when set, match privilege levels specified by
-         *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
-         */
-        uint32_t match_privilege:1;
-        /** match_ecause : R/W; bitpos: [3]; default: 0;
-         *  when set, start matching from exception cause codes specified by
-         *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
-         *  matching upon return from the 1st matching exception.
-         */
-        uint32_t match_ecause:1;
-        /** match_interrupt : R/W; bitpos: [4]; default: 0;
-         *  when set, start matching from a trap with the interrupt level codes specified by
-         *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
-         *  stop matching upon return from the 1st matching trap.
-         */
-        uint32_t match_interrupt:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} trace_filter_control_reg_t;
-
-/** Type of filter_match_control register
- *  filter match control register
- */
-typedef union {
-    struct {
-        /** match_choice_privilege : R/W; bitpos: [0]; default: 0;
-         *  Select match which privilege level when
-         *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1:
-         *  machine mode. \\0: user mode
-         */
-        uint32_t match_choice_privilege:1;
-        /** match_value_interrupt : R/W; bitpos: [1]; default: 0;
-         *  Select which match which itype when
-         *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match
-         *  itype of 2. \\0: match itype or 1.
-         */
-        uint32_t match_value_interrupt:1;
-        /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
-         *  specified which ecause matched.
-         */
-        uint32_t match_choice_ecause:6;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} trace_filter_match_control_reg_t;
-
-/** Type of filter_comparator_control register
- *  filter comparator match control register
- */
-typedef union {
-    struct {
-        /** p_input : R/W; bitpos: [0]; default: 0;
-         *  Determines which input to compare against the primary comparator, \\0: iaddr, \\1:
-         *  tval.
-         */
-        uint32_t p_input:1;
-        uint32_t reserved_1:1;
-        /** p_function : R/W; bitpos: [4:2]; default: 0;
-         *  Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than,
-         *  \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other:
-         *  always match
-         */
-        uint32_t p_function:3;
-        /** p_notify : R/W; bitpos: [5]; default: 0;
-         *  Generate a trace packet explicitly reporting the address that cause the primary
-         *  match
-         */
-        uint32_t p_notify:1;
-        uint32_t reserved_6:2;
-        /** s_input : R/W; bitpos: [8]; default: 0;
-         *  Determines which input to compare against the secondary comparator, \\0: iaddr,
-         *  \\1: tval.
-         */
-        uint32_t s_input:1;
-        uint32_t reserved_9:1;
-        /** s_function : R/W; bitpos: [12:10]; default: 0;
-         *  Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less
-         *  than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal,
-         *  \\other: always match
-         */
-        uint32_t s_function:3;
-        /** s_notify : R/W; bitpos: [13]; default: 0;
-         *  Generate a trace packet explicitly reporting the address that cause the secondary
-         *  match
-         */
-        uint32_t s_notify:1;
-        uint32_t reserved_14:2;
-        /** match_mode : R/W; bitpos: [17:16]; default: 0;
-         *  0: only primary matches, \\1: primary and secondary comparator both
-         *  matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3:
-         *  set when primary matches and continue to match until after secondary comparator
-         *  matches
-         */
-        uint32_t match_mode:2;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} trace_filter_comparator_control_reg_t;
-
-/** Type of filter_p_comparator_match register
- *  primary comparator match value
- */
-typedef union {
-    struct {
-        /** p_match : R/W; bitpos: [31:0]; default: 0;
-         *  primary comparator match value
-         */
-        uint32_t p_match:32;
-    };
-    uint32_t val;
-} trace_filter_p_comparator_match_reg_t;
-
-/** Type of filter_s_comparator_match register
- *  secondary comparator match value
- */
-typedef union {
-    struct {
-        /** s_match : R/W; bitpos: [31:0]; default: 0;
-         *  secondary comparator match value
-         */
-        uint32_t s_match:32;
-    };
-    uint32_t val;
-} trace_filter_s_comparator_match_reg_t;
-
-/** Type of resync_prolonged register
- *  resync configuration register
- */
-typedef union {
-    struct {
-        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
-         *  count number, when count to this value, send a sync package
-         */
-        uint32_t resync_prolonged:24;
-        /** resync_mode : R/W; bitpos: [25:24]; default: 0;
-         *  resyc mode sel: \\0: off, \\2: cycle count  \\3: package num count
-         */
-        uint32_t resync_mode:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} trace_resync_prolonged_reg_t;
-
-/** Type of ahb_config register
- *  AHB config register
- */
-typedef union {
-    struct {
-        /** hburst : R/W; bitpos: [2:0]; default: 0;
-         *  set hburst
-         */
-        uint32_t hburst:3;
-        /** max_incr : R/W; bitpos: [5:3]; default: 0;
-         *  set max continuous access for incr mode
-         */
-        uint32_t max_incr:3;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} trace_ahb_config_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35721984;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} trace_date_reg_t;
-
-
-typedef struct trace_dev_t {
-    volatile trace_mem_start_addr_reg_t mem_start_addr;
-    volatile trace_mem_end_addr_reg_t mem_end_addr;
-    volatile trace_mem_current_addr_reg_t mem_current_addr;
-    volatile trace_mem_addr_update_reg_t mem_addr_update;
-    volatile trace_fifo_status_reg_t fifo_status;
-    volatile trace_intr_ena_reg_t intr_ena;
-    volatile trace_intr_raw_reg_t intr_raw;
-    volatile trace_intr_clr_reg_t intr_clr;
-    volatile trace_trigger_reg_t trigger;
-    volatile trace_config_reg_t config;
-    volatile trace_filter_control_reg_t filter_control;
-    volatile trace_filter_match_control_reg_t filter_match_control;
-    volatile trace_filter_comparator_control_reg_t filter_comparator_control;
-    volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
-    volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
-    volatile trace_resync_prolonged_reg_t resync_prolonged;
-    volatile trace_ahb_config_reg_t ahb_config;
-    volatile trace_clock_gate_reg_t clock_gate;
-    uint32_t reserved_048[237];
-    volatile trace_date_reg_t date;
-} trace_dev_t;
-
-extern trace_dev_t TRACE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/twai_reg.h b/components/soc/esp32c5/beta3/include/soc/twai_reg.h
deleted file mode 100644
index 2301765caf..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/twai_reg.h
+++ /dev/null
@@ -1,791 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TWAI_MODE_REG register
- *  TWAI mode register.
- */
-#define TWAI_MODE_REG(i) (REG_TWAI_BASE(i) + 0x0)
-/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
- *  1: reset, detection of a set reset mode bit results in aborting the current
- *  transmission/reception of a message and entering the reset mode. 0: normal, on the
- *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
- *  operating mode.
- */
-#define TWAI_RESET_MODE    (BIT(0))
-#define TWAI_RESET_MODE_M  (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S)
-#define TWAI_RESET_MODE_V  0x00000001U
-#define TWAI_RESET_MODE_S  0
-/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
- *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
- *  TWAI-bus, even if a message is received successfully. The error counters are
- *  stopped at the current value. 0: normal.
- */
-#define TWAI_LISTEN_ONLY_MODE    (BIT(1))
-#define TWAI_LISTEN_ONLY_MODE_M  (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S)
-#define TWAI_LISTEN_ONLY_MODE_V  0x00000001U
-#define TWAI_LISTEN_ONLY_MODE_S  1
-/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
- *  1: self test, in this mode a full node test is possible without any other active
- *  node on the bus using the self reception request command. The TWAI controller will
- *  perform a successful transmission, even if there is no acknowledge received. 0:
- *  normal, an acknowledge is required for successful transmission.
- */
-#define TWAI_SELF_TEST_MODE    (BIT(2))
-#define TWAI_SELF_TEST_MODE_M  (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S)
-#define TWAI_SELF_TEST_MODE_V  0x00000001U
-#define TWAI_SELF_TEST_MODE_S  2
-/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0;
- *  1:single, the single acceptance filter option is enabled (one filter with the
- *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
- *  (two filters, each with the length of 16 bit are active).
- */
-#define TWAI_ACCEPTANCE_FILTER_MODE    (BIT(3))
-#define TWAI_ACCEPTANCE_FILTER_MODE_M  (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S)
-#define TWAI_ACCEPTANCE_FILTER_MODE_V  0x00000001U
-#define TWAI_ACCEPTANCE_FILTER_MODE_S  3
-
-/** TWAI_CMD_REG register
- *  TWAI command register.
- */
-#define TWAI_CMD_REG(i) (REG_TWAI_BASE(i) + 0x4)
-/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
- *  1: present, a message shall be transmitted. 0: absent
- */
-#define TWAI_TX_REQUEST    (BIT(0))
-#define TWAI_TX_REQUEST_M  (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S)
-#define TWAI_TX_REQUEST_V  0x00000001U
-#define TWAI_TX_REQUEST_S  0
-/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0;
- *  1: present, if not already in progress, a pending transmission request is
- *  cancelled. 0: absent
- */
-#define TWAI_ABORT_TX    (BIT(1))
-#define TWAI_ABORT_TX_M  (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S)
-#define TWAI_ABORT_TX_V  0x00000001U
-#define TWAI_ABORT_TX_S  1
-/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0;
- *  1: released, the receive buffer, representing the message memory space in the
- *  RXFIFO is released. 0: no action
- */
-#define TWAI_RELEASE_BUFFER    (BIT(2))
-#define TWAI_RELEASE_BUFFER_M  (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S)
-#define TWAI_RELEASE_BUFFER_V  0x00000001U
-#define TWAI_RELEASE_BUFFER_S  2
-/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0;
- *  1: clear, the data overrun status bit is cleared. 0: no action.
- */
-#define TWAI_CLEAR_DATA_OVERRUN    (BIT(3))
-#define TWAI_CLEAR_DATA_OVERRUN_M  (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S)
-#define TWAI_CLEAR_DATA_OVERRUN_V  0x00000001U
-#define TWAI_CLEAR_DATA_OVERRUN_S  3
-/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0;
- *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
- */
-#define TWAI_SELF_RX_REQUEST    (BIT(4))
-#define TWAI_SELF_RX_REQUEST_M  (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S)
-#define TWAI_SELF_RX_REQUEST_V  0x00000001U
-#define TWAI_SELF_RX_REQUEST_S  4
-
-/** TWAI_STATUS_REG register
- *  TWAI status register.
- */
-#define TWAI_STATUS_REG(i) (REG_TWAI_BASE(i) + 0x8)
-/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
- *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
- *  message is available
- */
-#define TWAI_STATUS_RECEIVE_BUFFER    (BIT(0))
-#define TWAI_STATUS_RECEIVE_BUFFER_M  (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S)
-#define TWAI_STATUS_RECEIVE_BUFFER_V  0x00000001U
-#define TWAI_STATUS_RECEIVE_BUFFER_S  0
-/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0;
- *  1: overrun, a message was lost because there was not enough space for that message
- *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
- *  overrun command was given
- */
-#define TWAI_STATUS_OVERRUN    (BIT(1))
-#define TWAI_STATUS_OVERRUN_M  (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S)
-#define TWAI_STATUS_OVERRUN_V  0x00000001U
-#define TWAI_STATUS_OVERRUN_S  1
-/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0;
- *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
- *  CPU cannot access the transmit buffer, a message is either waiting for transmission
- *  or is in the process of being transmitted
- */
-#define TWAI_STATUS_TRANSMIT_BUFFER    (BIT(2))
-#define TWAI_STATUS_TRANSMIT_BUFFER_M  (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S)
-#define TWAI_STATUS_TRANSMIT_BUFFER_V  0x00000001U
-#define TWAI_STATUS_TRANSMIT_BUFFER_S  2
-/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0;
- *  1: complete, last requested transmission has been successfully completed. 0:
- *  incomplete, previously requested transmission is not yet completed
- */
-#define TWAI_STATUS_TRANSMISSION_COMPLETE    (BIT(3))
-#define TWAI_STATUS_TRANSMISSION_COMPLETE_M  (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S)
-#define TWAI_STATUS_TRANSMISSION_COMPLETE_V  0x00000001U
-#define TWAI_STATUS_TRANSMISSION_COMPLETE_S  3
-/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0;
- *  1: receive, the TWAI controller is receiving a message. 0: idle
- */
-#define TWAI_STATUS_RECEIVE    (BIT(4))
-#define TWAI_STATUS_RECEIVE_M  (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S)
-#define TWAI_STATUS_RECEIVE_V  0x00000001U
-#define TWAI_STATUS_RECEIVE_S  4
-/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0;
- *  1: transmit, the TWAI controller is transmitting a message. 0: idle
- */
-#define TWAI_STATUS_TRANSMIT    (BIT(5))
-#define TWAI_STATUS_TRANSMIT_M  (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S)
-#define TWAI_STATUS_TRANSMIT_V  0x00000001U
-#define TWAI_STATUS_TRANSMIT_S  5
-/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0;
- *  1: error, at least one of the error counters has reached or exceeded the CPU
- *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
- *  counters are below the warning limit
- */
-#define TWAI_STATUS_ERR    (BIT(6))
-#define TWAI_STATUS_ERR_M  (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S)
-#define TWAI_STATUS_ERR_V  0x00000001U
-#define TWAI_STATUS_ERR_S  6
-/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0;
- *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
- *  TWAI controller is involved in bus activities
- */
-#define TWAI_STATUS_NODE_BUS_OFF    (BIT(7))
-#define TWAI_STATUS_NODE_BUS_OFF_M  (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S)
-#define TWAI_STATUS_NODE_BUS_OFF_V  0x00000001U
-#define TWAI_STATUS_NODE_BUS_OFF_S  7
-/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0;
- *  1: current message is destroyed because of FIFO overflow.
- */
-#define TWAI_STATUS_MISS    (BIT(8))
-#define TWAI_STATUS_MISS_M  (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S)
-#define TWAI_STATUS_MISS_V  0x00000001U
-#define TWAI_STATUS_MISS_S  8
-
-/** TWAI_INTERRUPT_REG register
- *  Interrupt signals' register.
- */
-#define TWAI_INTERRUPT_REG(i) (REG_TWAI_BASE(i) + 0xc)
-/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
- *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
- *  within the interrupt enable register. 0: reset
- */
-#define TWAI_RECEIVE_INT_ST    (BIT(0))
-#define TWAI_RECEIVE_INT_ST_M  (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S)
-#define TWAI_RECEIVE_INT_ST_V  0x00000001U
-#define TWAI_RECEIVE_INT_ST_S  0
-/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0;
- *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
- *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
- */
-#define TWAI_TRANSMIT_INT_ST    (BIT(1))
-#define TWAI_TRANSMIT_INT_ST_M  (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S)
-#define TWAI_TRANSMIT_INT_ST_V  0x00000001U
-#define TWAI_TRANSMIT_INT_ST_S  1
-/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
- *  1: this bit is set on every change (set and clear) of either the error status or
- *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
- *  reset
- */
-#define TWAI_ERR_WARNING_INT_ST    (BIT(2))
-#define TWAI_ERR_WARNING_INT_ST_M  (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S)
-#define TWAI_ERR_WARNING_INT_ST_V  0x00000001U
-#define TWAI_ERR_WARNING_INT_ST_S  2
-/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
- *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
- *  DOIE bit is set within the interrupt enable register. 0: reset
- */
-#define TWAI_DATA_OVERRUN_INT_ST    (BIT(3))
-#define TWAI_DATA_OVERRUN_INT_ST_M  (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S)
-#define TWAI_DATA_OVERRUN_INT_ST_V  0x00000001U
-#define TWAI_DATA_OVERRUN_INT_ST_S  3
-/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0;
- *  1: this bit is set then the timestamp counter reaches the maximum value and
- *  overflow.
- */
-#define TWAI_TS_COUNTER_OVFL_INT_ST    (BIT(4))
-#define TWAI_TS_COUNTER_OVFL_INT_ST_M  (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S)
-#define TWAI_TS_COUNTER_OVFL_INT_ST_V  0x00000001U
-#define TWAI_TS_COUNTER_OVFL_INT_ST_S  4
-/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0;
- *  1: this bit is set whenever the TWAI controller has reached the error passive
- *  status (at least one error counter exceeds the protocol-defined level of 127) or if
- *  the TWAI controller is in the error passive status and enters the error active
- *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
- */
-#define TWAI_ERR_PASSIVE_INT_ST    (BIT(5))
-#define TWAI_ERR_PASSIVE_INT_ST_M  (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S)
-#define TWAI_ERR_PASSIVE_INT_ST_V  0x00000001U
-#define TWAI_ERR_PASSIVE_INT_ST_S  5
-/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0;
- *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
- *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
- */
-#define TWAI_ARBITRATION_LOST_INT_ST    (BIT(6))
-#define TWAI_ARBITRATION_LOST_INT_ST_M  (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S)
-#define TWAI_ARBITRATION_LOST_INT_ST_V  0x00000001U
-#define TWAI_ARBITRATION_LOST_INT_ST_S  6
-/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
- *  the BEIE bit is set within the interrupt enable register. 0: reset
- */
-#define TWAI_BUS_ERR_INT_ST    (BIT(7))
-#define TWAI_BUS_ERR_INT_ST_M  (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S)
-#define TWAI_BUS_ERR_INT_ST_V  0x00000001U
-#define TWAI_BUS_ERR_INT_ST_S  7
-/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0;
- *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
- *  this interrupt enable bit is set within the interrupt enable register. 0: reset
- */
-#define TWAI_IDLE_INT_ST    (BIT(8))
-#define TWAI_IDLE_INT_ST_M  (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S)
-#define TWAI_IDLE_INT_ST_V  0x00000001U
-#define TWAI_IDLE_INT_ST_S  8
-
-/** TWAI_INTERRUPT_ENABLE_REG register
- *  Interrupt enable register.
- */
-#define TWAI_INTERRUPT_ENABLE_REG(i) (REG_TWAI_BASE(i) + 0x10)
-/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
- *  the respective interrupt. 0: disable
- */
-#define TWAI_EXT_RECEIVE_INT_ENA    (BIT(0))
-#define TWAI_EXT_RECEIVE_INT_ENA_M  (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S)
-#define TWAI_EXT_RECEIVE_INT_ENA_V  0x00000001U
-#define TWAI_EXT_RECEIVE_INT_ENA_S  0
-/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  1: enabled, when a message has been successfully transmitted or the transmit buffer
- *  is accessible again (e.g. after an abort transmission command), the TWAI controller
- *  requests the respective interrupt. 0: disable
- */
-#define TWAI_EXT_TRANSMIT_INT_ENA    (BIT(1))
-#define TWAI_EXT_TRANSMIT_INT_ENA_M  (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S)
-#define TWAI_EXT_TRANSMIT_INT_ENA_V  0x00000001U
-#define TWAI_EXT_TRANSMIT_INT_ENA_S  1
-/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  1: enabled, if the error or bus status change (see status register. Table 14), the
- *  TWAI controllerrequests the respective interrupt. 0: disable
- */
-#define TWAI_EXT_ERR_WARNING_INT_ENA    (BIT(2))
-#define TWAI_EXT_ERR_WARNING_INT_ENA_M  (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S)
-#define TWAI_EXT_ERR_WARNING_INT_ENA_V  0x00000001U
-#define TWAI_EXT_ERR_WARNING_INT_ENA_S  2
-/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
- *  the TWAI controllerrequests the respective interrupt. 0: disable
- */
-#define TWAI_EXT_DATA_OVERRUN_INT_ENA    (BIT(3))
-#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M  (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S)
-#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V  0x00000001U
-#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S  3
-/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  enable the timestamp counter overflow interrupt request.
- */
-#define TWAI_TS_COUNTER_OVFL_INT_ENA    (BIT(4))
-#define TWAI_TS_COUNTER_OVFL_INT_ENA_M  (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S)
-#define TWAI_TS_COUNTER_OVFL_INT_ENA_V  0x00000001U
-#define TWAI_TS_COUNTER_OVFL_INT_ENA_S  4
-/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  1: enabled, if the error status of the TWAI controller changes from error active to
- *  error passive or vice versa, the respective interrupt is requested. 0: disable
- */
-#define TWAI_ERR_PASSIVE_INT_ENA    (BIT(5))
-#define TWAI_ERR_PASSIVE_INT_ENA_M  (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S)
-#define TWAI_ERR_PASSIVE_INT_ENA_V  0x00000001U
-#define TWAI_ERR_PASSIVE_INT_ENA_S  5
-/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
- *  is requested. 0: disable
- */
-#define TWAI_ARBITRATION_LOST_INT_ENA    (BIT(6))
-#define TWAI_ARBITRATION_LOST_INT_ENA_M  (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S)
-#define TWAI_ARBITRATION_LOST_INT_ENA_V  0x00000001U
-#define TWAI_ARBITRATION_LOST_INT_ENA_S  6
-/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  1: enabled, if an bus error has been detected, the TWAI controller requests the
- *  respective interrupt. 0: disable
- */
-#define TWAI_BUS_ERR_INT_ENA    (BIT(7))
-#define TWAI_BUS_ERR_INT_ENA_M  (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S)
-#define TWAI_BUS_ERR_INT_ENA_V  0x00000001U
-#define TWAI_BUS_ERR_INT_ENA_S  7
-/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0;
- *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
- *  respective interrupt. 0: disable
- */
-#define TWAI_IDLE_INT_ENA    (BIT(8))
-#define TWAI_IDLE_INT_ENA_M  (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S)
-#define TWAI_IDLE_INT_ENA_V  0x00000001U
-#define TWAI_IDLE_INT_ENA_S  8
-
-/** TWAI_BUS_TIMING_0_REG register
- *  Bit timing configuration register 0.
- */
-#define TWAI_BUS_TIMING_0_REG(i) (REG_TWAI_BASE(i) + 0x18)
-/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
- *  The period of the TWAI system clock is programmable and determines the individual
- *  bit timing. Software has R/W permission in reset mode and RO permission in
- *  operation mode.
- */
-#define TWAI_BAUD_PRESC    0x00003FFFU
-#define TWAI_BAUD_PRESC_M  (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S)
-#define TWAI_BAUD_PRESC_V  0x00003FFFU
-#define TWAI_BAUD_PRESC_S  0
-/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0;
- *  The synchronization jump width defines the maximum number of clock cycles a bit
- *  period may be shortened or lengthened. Software has R/W permission in reset mode
- *  and RO in operation mode.
- */
-#define TWAI_SYNC_JUMP_WIDTH    0x00000003U
-#define TWAI_SYNC_JUMP_WIDTH_M  (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S)
-#define TWAI_SYNC_JUMP_WIDTH_V  0x00000003U
-#define TWAI_SYNC_JUMP_WIDTH_S  14
-
-/** TWAI_BUS_TIMING_1_REG register
- *  Bit timing configuration register 1.
- */
-#define TWAI_BUS_TIMING_1_REG(i) (REG_TWAI_BASE(i) + 0x1c)
-/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
- *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
- *  reset mode and RO in operation mode.
- */
-#define TWAI_TIME_SEGMENT1    0x0000000FU
-#define TWAI_TIME_SEGMENT1_M  (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S)
-#define TWAI_TIME_SEGMENT1_V  0x0000000FU
-#define TWAI_TIME_SEGMENT1_S  0
-/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0;
- *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
- *  reset mode and RO in operation mode.
- */
-#define TWAI_TIME_SEGMENT2    0x00000007U
-#define TWAI_TIME_SEGMENT2_M  (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S)
-#define TWAI_TIME_SEGMENT2_V  0x00000007U
-#define TWAI_TIME_SEGMENT2_S  4
-/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0;
- *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
- *  Software has R/W permission in reset mode and RO in operation mode.
- */
-#define TWAI_TIME_SAMPLING    (BIT(7))
-#define TWAI_TIME_SAMPLING_M  (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S)
-#define TWAI_TIME_SAMPLING_V  0x00000001U
-#define TWAI_TIME_SAMPLING_S  7
-
-/** TWAI_ARB_LOST_CAP_REG register
- *  TWAI arbiter lost capture register.
- */
-#define TWAI_ARB_LOST_CAP_REG(i) (REG_TWAI_BASE(i) + 0x2c)
-/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
- *  This register contains information about the bit position of losing arbitration.
- */
-#define TWAI_ARBITRATION_LOST_CAPTURE    0x0000001FU
-#define TWAI_ARBITRATION_LOST_CAPTURE_M  (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S)
-#define TWAI_ARBITRATION_LOST_CAPTURE_V  0x0000001FU
-#define TWAI_ARBITRATION_LOST_CAPTURE_S  0
-
-/** TWAI_ERR_CODE_CAP_REG register
- *  TWAI error info capture register.
- */
-#define TWAI_ERR_CODE_CAP_REG(i) (REG_TWAI_BASE(i) + 0x30)
-/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
- *  This register contains information about the location of errors on the bus.
- */
-#define TWAI_ERR_CAPTURE_CODE_SEGMENT    0x0000001FU
-#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M  (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S)
-#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V  0x0000001FU
-#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S  0
-/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0;
- *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
- */
-#define TWAI_ERR_CAPTURE_CODE_DIRECTION    (BIT(5))
-#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M  (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S)
-#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V  0x00000001U
-#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S  5
-/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0;
- *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
- */
-#define TWAI_ERR_CAPTURE_CODE_TYPE    0x00000003U
-#define TWAI_ERR_CAPTURE_CODE_TYPE_M  (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S)
-#define TWAI_ERR_CAPTURE_CODE_TYPE_V  0x00000003U
-#define TWAI_ERR_CAPTURE_CODE_TYPE_S  6
-
-/** TWAI_ERR_WARNING_LIMIT_REG register
- *  TWAI error threshold configuration register.
- */
-#define TWAI_ERR_WARNING_LIMIT_REG(i) (REG_TWAI_BASE(i) + 0x34)
-/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
- *  The threshold that trigger error warning interrupt when this interrupt is enabled.
- *  Software has R/W permission in reset mode and RO in operation mode.
- */
-#define TWAI_ERR_WARNING_LIMIT    0x000000FFU
-#define TWAI_ERR_WARNING_LIMIT_M  (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S)
-#define TWAI_ERR_WARNING_LIMIT_V  0x000000FFU
-#define TWAI_ERR_WARNING_LIMIT_S  0
-
-/** TWAI_RX_ERR_CNT_REG register
- *  Rx error counter register.
- */
-#define TWAI_RX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x38)
-/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
- *  The RX error counter register reflects the current value of the transmit error
- *  counter. Software has R/W permission in reset mode and RO in operation mode.
- */
-#define TWAI_RX_ERR_CNT    0x000000FFU
-#define TWAI_RX_ERR_CNT_M  (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S)
-#define TWAI_RX_ERR_CNT_V  0x000000FFU
-#define TWAI_RX_ERR_CNT_S  0
-
-/** TWAI_TX_ERR_CNT_REG register
- *  Tx error counter register.
- */
-#define TWAI_TX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x3c)
-/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
- *  The TX error counter register reflects the current value of the transmit error
- *  counter. Software has R/W permission in reset mode and RO in operation mode.
- */
-#define TWAI_TX_ERR_CNT    0x000000FFU
-#define TWAI_TX_ERR_CNT_M  (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S)
-#define TWAI_TX_ERR_CNT_V  0x000000FFU
-#define TWAI_TX_ERR_CNT_S  0
-
-/** TWAI_DATA_0_REG register
- *  Data register 0.
- */
-#define TWAI_DATA_0_REG(i) (REG_TWAI_BASE(i) + 0x40)
-/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 0 and when
- *  software initiate read operation, it is rx data register 0.
- */
-#define TWAI_DATA_0    0x000000FFU
-#define TWAI_DATA_0_M  (TWAI_DATA_0_V << TWAI_DATA_0_S)
-#define TWAI_DATA_0_V  0x000000FFU
-#define TWAI_DATA_0_S  0
-
-/** TWAI_DATA_1_REG register
- *  Data register 1.
- */
-#define TWAI_DATA_1_REG(i) (REG_TWAI_BASE(i) + 0x44)
-/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 1 and when
- *  software initiate read operation, it is rx data register 1.
- */
-#define TWAI_DATA_1    0x000000FFU
-#define TWAI_DATA_1_M  (TWAI_DATA_1_V << TWAI_DATA_1_S)
-#define TWAI_DATA_1_V  0x000000FFU
-#define TWAI_DATA_1_S  0
-
-/** TWAI_DATA_2_REG register
- *  Data register 2.
- */
-#define TWAI_DATA_2_REG(i) (REG_TWAI_BASE(i) + 0x48)
-/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 2 and when
- *  software initiate read operation, it is rx data register 2.
- */
-#define TWAI_DATA_2    0x000000FFU
-#define TWAI_DATA_2_M  (TWAI_DATA_2_V << TWAI_DATA_2_S)
-#define TWAI_DATA_2_V  0x000000FFU
-#define TWAI_DATA_2_S  0
-
-/** TWAI_DATA_3_REG register
- *  Data register 3.
- */
-#define TWAI_DATA_3_REG(i) (REG_TWAI_BASE(i) + 0x4c)
-/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 3 and when
- *  software initiate read operation, it is rx data register 3.
- */
-#define TWAI_DATA_3    0x000000FFU
-#define TWAI_DATA_3_M  (TWAI_DATA_3_V << TWAI_DATA_3_S)
-#define TWAI_DATA_3_V  0x000000FFU
-#define TWAI_DATA_3_S  0
-
-/** TWAI_DATA_4_REG register
- *  Data register 4.
- */
-#define TWAI_DATA_4_REG(i) (REG_TWAI_BASE(i) + 0x50)
-/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 4 and when
- *  software initiate read operation, it is rx data register 4.
- */
-#define TWAI_DATA_4    0x000000FFU
-#define TWAI_DATA_4_M  (TWAI_DATA_4_V << TWAI_DATA_4_S)
-#define TWAI_DATA_4_V  0x000000FFU
-#define TWAI_DATA_4_S  0
-
-/** TWAI_DATA_5_REG register
- *  Data register 5.
- */
-#define TWAI_DATA_5_REG(i) (REG_TWAI_BASE(i) + 0x54)
-/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 5 and when
- *  software initiate read operation, it is rx data register 5.
- */
-#define TWAI_DATA_5    0x000000FFU
-#define TWAI_DATA_5_M  (TWAI_DATA_5_V << TWAI_DATA_5_S)
-#define TWAI_DATA_5_V  0x000000FFU
-#define TWAI_DATA_5_S  0
-
-/** TWAI_DATA_6_REG register
- *  Data register 6.
- */
-#define TWAI_DATA_6_REG(i) (REG_TWAI_BASE(i) + 0x58)
-/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 6 and when
- *  software initiate read operation, it is rx data register 6.
- */
-#define TWAI_DATA_6    0x000000FFU
-#define TWAI_DATA_6_M  (TWAI_DATA_6_V << TWAI_DATA_6_S)
-#define TWAI_DATA_6_V  0x000000FFU
-#define TWAI_DATA_6_S  0
-
-/** TWAI_DATA_7_REG register
- *  Data register 7.
- */
-#define TWAI_DATA_7_REG(i) (REG_TWAI_BASE(i) + 0x5c)
-/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
- *  mode, when software initiate write operation, it is tx data register 7 and when
- *  software initiate read operation, it is rx data register 7.
- */
-#define TWAI_DATA_7    0x000000FFU
-#define TWAI_DATA_7_M  (TWAI_DATA_7_V << TWAI_DATA_7_S)
-#define TWAI_DATA_7_V  0x000000FFU
-#define TWAI_DATA_7_S  0
-
-/** TWAI_DATA_8_REG register
- *  Data register 8.
- */
-#define TWAI_DATA_8_REG(i) (REG_TWAI_BASE(i) + 0x60)
-/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, reserved with RO. In operation mode, when software initiate write
- *  operation, it is tx data register 8 and when software initiate read operation, it
- *  is rx data register 8.
- */
-#define TWAI_DATA_8    0x000000FFU
-#define TWAI_DATA_8_M  (TWAI_DATA_8_V << TWAI_DATA_8_S)
-#define TWAI_DATA_8_V  0x000000FFU
-#define TWAI_DATA_8_S  0
-
-/** TWAI_DATA_9_REG register
- *  Data register 9.
- */
-#define TWAI_DATA_9_REG(i) (REG_TWAI_BASE(i) + 0x64)
-/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, reserved with RO. In operation mode, when software initiate write
- *  operation, it is tx data register 9 and when software initiate read operation, it
- *  is rx data register 9.
- */
-#define TWAI_DATA_9    0x000000FFU
-#define TWAI_DATA_9_M  (TWAI_DATA_9_V << TWAI_DATA_9_S)
-#define TWAI_DATA_9_V  0x000000FFU
-#define TWAI_DATA_9_S  0
-
-/** TWAI_DATA_10_REG register
- *  Data register 10.
- */
-#define TWAI_DATA_10_REG(i) (REG_TWAI_BASE(i) + 0x68)
-/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, reserved with RO. In operation mode, when software initiate write
- *  operation, it is tx data register 10 and when software initiate read operation, it
- *  is rx data register 10.
- */
-#define TWAI_DATA_10    0x000000FFU
-#define TWAI_DATA_10_M  (TWAI_DATA_10_V << TWAI_DATA_10_S)
-#define TWAI_DATA_10_V  0x000000FFU
-#define TWAI_DATA_10_S  0
-
-/** TWAI_DATA_11_REG register
- *  Data register 11.
- */
-#define TWAI_DATA_11_REG(i) (REG_TWAI_BASE(i) + 0x6c)
-/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, reserved with RO. In operation mode, when software initiate write
- *  operation, it is tx data register 11 and when software initiate read operation, it
- *  is rx data register 11.
- */
-#define TWAI_DATA_11    0x000000FFU
-#define TWAI_DATA_11_M  (TWAI_DATA_11_V << TWAI_DATA_11_S)
-#define TWAI_DATA_11_V  0x000000FFU
-#define TWAI_DATA_11_S  0
-
-/** TWAI_DATA_12_REG register
- *  Data register 12.
- */
-#define TWAI_DATA_12_REG(i) (REG_TWAI_BASE(i) + 0x70)
-/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
- *  In reset mode, reserved with RO. In operation mode, when software initiate write
- *  operation, it is tx data register 12 and when software initiate read operation, it
- *  is rx data register 12.
- */
-#define TWAI_DATA_12    0x000000FFU
-#define TWAI_DATA_12_M  (TWAI_DATA_12_V << TWAI_DATA_12_S)
-#define TWAI_DATA_12_V  0x000000FFU
-#define TWAI_DATA_12_S  0
-
-/** TWAI_RX_MESSAGE_COUNTER_REG register
- *  Received message counter register.
- */
-#define TWAI_RX_MESSAGE_COUNTER_REG(i) (REG_TWAI_BASE(i) + 0x74)
-/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
- *  Reflects the number of messages available within the RXFIFO. The value is
- *  incremented with each receive event and decremented by the release receive buffer
- *  command.
- */
-#define TWAI_RX_MESSAGE_COUNTER    0x0000007FU
-#define TWAI_RX_MESSAGE_COUNTER_M  (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S)
-#define TWAI_RX_MESSAGE_COUNTER_V  0x0000007FU
-#define TWAI_RX_MESSAGE_COUNTER_S  0
-
-/** TWAI_CLOCK_DIVIDER_REG register
- *  Clock divider register.
- */
-#define TWAI_CLOCK_DIVIDER_REG(i) (REG_TWAI_BASE(i) + 0x7c)
-/** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
- *  These bits are used to define the frequency at the external CLKOUT pin.
- */
-#define TWAI_CD    0x000000FFU
-#define TWAI_CD_M  (TWAI_CD_V << TWAI_CD_S)
-#define TWAI_CD_V  0x000000FFU
-#define TWAI_CD_S  0
-/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0;
- *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
- *  R/W permission in reset mode and RO in operation mode.
- */
-#define TWAI_CLOCK_OFF    (BIT(8))
-#define TWAI_CLOCK_OFF_M  (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S)
-#define TWAI_CLOCK_OFF_V  0x00000001U
-#define TWAI_CLOCK_OFF_S  8
-
-/** TWAI_SW_STANDBY_CFG_REG register
- *  Software configure standby pin directly.
- */
-#define TWAI_SW_STANDBY_CFG_REG(i) (REG_TWAI_BASE(i) + 0x80)
-/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
- *  Enable standby pin.
- */
-#define TWAI_SW_STANDBY_EN    (BIT(0))
-#define TWAI_SW_STANDBY_EN_M  (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S)
-#define TWAI_SW_STANDBY_EN_V  0x00000001U
-#define TWAI_SW_STANDBY_EN_S  0
-/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1;
- *  Clear standby pin.
- */
-#define TWAI_SW_STANDBY_CLR    (BIT(1))
-#define TWAI_SW_STANDBY_CLR_M  (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S)
-#define TWAI_SW_STANDBY_CLR_V  0x00000001U
-#define TWAI_SW_STANDBY_CLR_S  1
-
-/** TWAI_HW_CFG_REG register
- *  Hardware configure standby pin.
- */
-#define TWAI_HW_CFG_REG(i) (REG_TWAI_BASE(i) + 0x84)
-/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
- *  Enable function that hardware control standby pin.
- */
-#define TWAI_HW_STANDBY_EN    (BIT(0))
-#define TWAI_HW_STANDBY_EN_M  (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S)
-#define TWAI_HW_STANDBY_EN_V  0x00000001U
-#define TWAI_HW_STANDBY_EN_S  0
-
-/** TWAI_HW_STANDBY_CNT_REG register
- *  Configure standby counter.
- */
-#define TWAI_HW_STANDBY_CNT_REG(i) (REG_TWAI_BASE(i) + 0x88)
-/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
- *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
- *  is enabled.
- */
-#define TWAI_STANDBY_WAIT_CNT    0xFFFFFFFFU
-#define TWAI_STANDBY_WAIT_CNT_M  (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S)
-#define TWAI_STANDBY_WAIT_CNT_V  0xFFFFFFFFU
-#define TWAI_STANDBY_WAIT_CNT_S  0
-
-/** TWAI_IDLE_INTR_CNT_REG register
- *  Configure idle interrupt counter.
- */
-#define TWAI_IDLE_INTR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x8c)
-/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
- *  Configure the number of cycles before triggering idle interrupt.
- */
-#define TWAI_IDLE_INTR_CNT    0xFFFFFFFFU
-#define TWAI_IDLE_INTR_CNT_M  (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S)
-#define TWAI_IDLE_INTR_CNT_V  0xFFFFFFFFU
-#define TWAI_IDLE_INTR_CNT_S  0
-
-/** TWAI_ECO_CFG_REG register
- *  ECO configuration register.
- */
-#define TWAI_ECO_CFG_REG(i) (REG_TWAI_BASE(i) + 0x90)
-/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
- *  Enable eco module.
- */
-#define TWAI_RDN_ENA    (BIT(0))
-#define TWAI_RDN_ENA_M  (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S)
-#define TWAI_RDN_ENA_V  0x00000001U
-#define TWAI_RDN_ENA_S  0
-/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1;
- *  Output of eco module.
- */
-#define TWAI_RDN_RESULT    (BIT(1))
-#define TWAI_RDN_RESULT_M  (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S)
-#define TWAI_RDN_RESULT_V  0x00000001U
-#define TWAI_RDN_RESULT_S  1
-
-/** TWAI_TIMESTAMP_DATA_REG register
- *  Timestamp data register
- */
-#define TWAI_TIMESTAMP_DATA_REG(i) (REG_TWAI_BASE(i) + 0x94)
-/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0;
- *  Data of timestamp of a CAN frame.
- */
-#define TWAI_TIMESTAMP_DATA    0xFFFFFFFFU
-#define TWAI_TIMESTAMP_DATA_M  (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S)
-#define TWAI_TIMESTAMP_DATA_V  0xFFFFFFFFU
-#define TWAI_TIMESTAMP_DATA_S  0
-
-/** TWAI_TIMESTAMP_PRESCALER_REG register
- *  Timestamp configuration register
- */
-#define TWAI_TIMESTAMP_PRESCALER_REG(i) (REG_TWAI_BASE(i) + 0x98)
-/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31;
- *  Configures the clock division number of timestamp counter.
- */
-#define TWAI_TS_DIV_NUM    0x0000FFFFU
-#define TWAI_TS_DIV_NUM_M  (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S)
-#define TWAI_TS_DIV_NUM_V  0x0000FFFFU
-#define TWAI_TS_DIV_NUM_S  0
-
-/** TWAI_TIMESTAMP_CFG_REG register
- *  Timestamp configuration register
- */
-#define TWAI_TIMESTAMP_CFG_REG(i) (REG_TWAI_BASE(i) + 0x9c)
-/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0;
- *  enable the timestamp collection function.
- */
-#define TWAI_TS_ENABLE    (BIT(0))
-#define TWAI_TS_ENABLE_M  (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S)
-#define TWAI_TS_ENABLE_V  0x00000001U
-#define TWAI_TS_ENABLE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/twai_struct.h b/components/soc/esp32c5/beta3/include/soc/twai_struct.h
deleted file mode 100644
index bc3be7f3f4..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/twai_struct.h
+++ /dev/null
@@ -1,614 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of mode register
- *  TWAI mode register.
- */
-typedef union {
-    struct {
-        /** reset_mode : R/W; bitpos: [0]; default: 1;
-         *  1: reset, detection of a set reset mode bit results in aborting the current
-         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
-         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
-         *  operating mode.
-         */
-        uint32_t reset_mode:1;
-        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
-         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
-         *  TWAI-bus, even if a message is received successfully. The error counters are
-         *  stopped at the current value. 0: normal.
-         */
-        uint32_t listen_only_mode:1;
-        /** self_test_mode : R/W; bitpos: [2]; default: 0;
-         *  1: self test, in this mode a full node test is possible without any other active
-         *  node on the bus using the self reception request command. The TWAI controller will
-         *  perform a successful transmission, even if there is no acknowledge received. 0:
-         *  normal, an acknowledge is required for successful transmission.
-         */
-        uint32_t self_test_mode:1;
-        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
-         *  1:single, the single acceptance filter option is enabled (one filter with the
-         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
-         *  (two filters, each with the length of 16 bit are active).
-         */
-        uint32_t acceptance_filter_mode:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} twai_mode_reg_t;
-
-/** Type of cmd register
- *  TWAI command register.
- */
-typedef union {
-    struct {
-        /** tx_request : WO; bitpos: [0]; default: 0;
-         *  1: present, a message shall be transmitted. 0: absent
-         */
-        uint32_t tx_request:1;
-        /** abort_tx : WO; bitpos: [1]; default: 0;
-         *  1: present, if not already in progress, a pending transmission request is
-         *  cancelled. 0: absent
-         */
-        uint32_t abort_tx:1;
-        /** release_buffer : WO; bitpos: [2]; default: 0;
-         *  1: released, the receive buffer, representing the message memory space in the
-         *  RXFIFO is released. 0: no action
-         */
-        uint32_t release_buffer:1;
-        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
-         *  1: clear, the data overrun status bit is cleared. 0: no action.
-         */
-        uint32_t clear_data_overrun:1;
-        /** self_rx_request : WO; bitpos: [4]; default: 0;
-         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
-         */
-        uint32_t self_rx_request:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} twai_cmd_reg_t;
-
-/** Type of bus_timing_0 register
- *  Bit timing configuration register 0.
- */
-typedef union {
-    struct {
-        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
-         *  The period of the TWAI system clock is programmable and determines the individual
-         *  bit timing. Software has R/W permission in reset mode and RO permission in
-         *  operation mode.
-         */
-        uint32_t baud_presc:14;
-        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
-         *  The synchronization jump width defines the maximum number of clock cycles a bit
-         *  period may be shortened or lengthened. Software has R/W permission in reset mode
-         *  and RO in operation mode.
-         */
-        uint32_t sync_jump_width:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} twai_bus_timing_0_reg_t;
-
-/** Type of bus_timing_1 register
- *  Bit timing configuration register 1.
- */
-typedef union {
-    struct {
-        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
-         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
-         *  reset mode and RO in operation mode.
-         */
-        uint32_t time_segment1:4;
-        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
-         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
-         *  reset mode and RO in operation mode.
-         */
-        uint32_t time_segment2:3;
-        /** time_sampling : R/W; bitpos: [7]; default: 0;
-         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
-         *  Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t time_sampling:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_bus_timing_1_reg_t;
-
-/** Type of err_warning_limit register
- *  TWAI error threshold configuration register.
- */
-typedef union {
-    struct {
-        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
-         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
-         *  Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t err_warning_limit:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_err_warning_limit_reg_t;
-
-/** Type of clock_divider register
- *  Clock divider register.
- */
-typedef union {
-    struct {
-        /** cd : R/W; bitpos: [7:0]; default: 0;
-         *  These bits are used to define the frequency at the external CLKOUT pin.
-         */
-        uint32_t cd:8;
-        /** clock_off : R/W; bitpos: [8]; default: 0;
-         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
-         *  R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t clock_off:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_clock_divider_reg_t;
-
-/** Type of sw_standby_cfg register
- *  Software configure standby pin directly.
- */
-typedef union {
-    struct {
-        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
-         *  Enable standby pin.
-         */
-        uint32_t sw_standby_en:1;
-        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
-         *  Clear standby pin.
-         */
-        uint32_t sw_standby_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} twai_sw_standby_cfg_reg_t;
-
-/** Type of hw_cfg register
- *  Hardware configure standby pin.
- */
-typedef union {
-    struct {
-        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
-         *  Enable function that hardware control standby pin.
-         */
-        uint32_t hw_standby_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} twai_hw_cfg_reg_t;
-
-/** Type of hw_standby_cnt register
- *  Configure standby counter.
- */
-typedef union {
-    struct {
-        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
-         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
-         *  is enabled.
-         */
-        uint32_t standby_wait_cnt:32;
-    };
-    uint32_t val;
-} twai_hw_standby_cnt_reg_t;
-
-/** Type of idle_intr_cnt register
- *  Configure idle interrupt counter.
- */
-typedef union {
-    struct {
-        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
-         *  Configure the number of cycles before triggering idle interrupt.
-         */
-        uint32_t idle_intr_cnt:32;
-    };
-    uint32_t val;
-} twai_idle_intr_cnt_reg_t;
-
-/** Type of eco_cfg register
- *  ECO configuration register.
- */
-typedef union {
-    struct {
-        /** rdn_ena : R/W; bitpos: [0]; default: 0;
-         *  Enable eco module.
-         */
-        uint32_t rdn_ena:1;
-        /** rdn_result : RO; bitpos: [1]; default: 1;
-         *  Output of eco module.
-         */
-        uint32_t rdn_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} twai_eco_cfg_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of status register
- *  TWAI status register.
- */
-typedef union {
-    struct {
-        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
-         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
-         *  message is available
-         */
-        uint32_t status_receive_buffer:1;
-        /** status_overrun : RO; bitpos: [1]; default: 0;
-         *  1: overrun, a message was lost because there was not enough space for that message
-         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
-         *  overrun command was given
-         */
-        uint32_t status_overrun:1;
-        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
-         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
-         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
-         *  or is in the process of being transmitted
-         */
-        uint32_t status_transmit_buffer:1;
-        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
-         *  1: complete, last requested transmission has been successfully completed. 0:
-         *  incomplete, previously requested transmission is not yet completed
-         */
-        uint32_t status_transmission_complete:1;
-        /** status_receive : RO; bitpos: [4]; default: 0;
-         *  1: receive, the TWAI controller is receiving a message. 0: idle
-         */
-        uint32_t status_receive:1;
-        /** status_transmit : RO; bitpos: [5]; default: 0;
-         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
-         */
-        uint32_t status_transmit:1;
-        /** status_err : RO; bitpos: [6]; default: 0;
-         *  1: error, at least one of the error counters has reached or exceeded the CPU
-         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
-         *  counters are below the warning limit
-         */
-        uint32_t status_err:1;
-        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
-         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
-         *  TWAI controller is involved in bus activities
-         */
-        uint32_t status_node_bus_off:1;
-        /** status_miss : RO; bitpos: [8]; default: 0;
-         *  1: current message is destroyed because of FIFO overflow.
-         */
-        uint32_t status_miss:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_status_reg_t;
-
-/** Type of arb_lost_cap register
- *  TWAI arbiter lost capture register.
- */
-typedef union {
-    struct {
-        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
-         *  This register contains information about the bit position of losing arbitration.
-         */
-        uint32_t arbitration_lost_capture:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} twai_arb_lost_cap_reg_t;
-
-/** Type of err_code_cap register
- *  TWAI error info capture register.
- */
-typedef union {
-    struct {
-        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
-         *  This register contains information about the location of errors on the bus.
-         */
-        uint32_t err_capture_code_segment:5;
-        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
-         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
-         */
-        uint32_t err_capture_code_direction:1;
-        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
-         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
-         */
-        uint32_t err_capture_code_type:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_err_code_cap_reg_t;
-
-/** Type of rx_err_cnt register
- *  Rx error counter register.
- */
-typedef union {
-    struct {
-        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
-         *  The RX error counter register reflects the current value of the transmit error
-         *  counter. Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t rx_err_cnt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_rx_err_cnt_reg_t;
-
-/** Type of tx_err_cnt register
- *  Tx error counter register.
- */
-typedef union {
-    struct {
-        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
-         *  The TX error counter register reflects the current value of the transmit error
-         *  counter. Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t tx_err_cnt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_tx_err_cnt_reg_t;
-
-/** Type of rx_message_counter register
- *  Received message counter register.
- */
-typedef union {
-    struct {
-        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
-         *  Reflects the number of messages available within the RXFIFO. The value is
-         *  incremented with each receive event and decremented by the release receive buffer
-         *  command.
-         */
-        uint32_t rx_message_counter:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} twai_rx_message_counter_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of interrupt register
- *  Interrupt signals' register.
- */
-typedef union {
-    struct {
-        /** receive_int_st : RO; bitpos: [0]; default: 0;
-         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
-         *  within the interrupt enable register. 0: reset
-         */
-        uint32_t receive_int_st:1;
-        /** transmit_int_st : RO; bitpos: [1]; default: 0;
-         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
-         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t transmit_int_st:1;
-        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
-         *  1: this bit is set on every change (set and clear) of either the error status or
-         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
-         *  reset
-         */
-        uint32_t err_warning_int_st:1;
-        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
-         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
-         *  DOIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t data_overrun_int_st:1;
-        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
-         *  1: this bit is set then the timestamp counter reaches the maximum value and
-         *  overflow.
-         */
-        uint32_t ts_counter_ovfl_int_st:1;
-        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
-         *  1: this bit is set whenever the TWAI controller has reached the error passive
-         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
-         *  the TWAI controller is in the error passive status and enters the error active
-         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t err_passive_int_st:1;
-        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
-         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
-         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t arbitration_lost_int_st:1;
-        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
-         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
-         *  the BEIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t bus_err_int_st:1;
-        /** idle_int_st : RO; bitpos: [8]; default: 0;
-         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
-         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t idle_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_interrupt_reg_t;
-
-/** Type of interrupt_enable register
- *  Interrupt enable register.
- */
-typedef union {
-    struct {
-        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
-         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
-         *  the respective interrupt. 0: disable
-         */
-        uint32_t ext_receive_int_ena:1;
-        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
-         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
-         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
-         *  requests the respective interrupt. 0: disable
-         */
-        uint32_t ext_transmit_int_ena:1;
-        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
-         *  1: enabled, if the error or bus status change (see status register. Table 14), the
-         *  TWAI controllerrequests the respective interrupt. 0: disable
-         */
-        uint32_t ext_err_warning_int_ena:1;
-        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
-         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
-         *  the TWAI controllerrequests the respective interrupt. 0: disable
-         */
-        uint32_t ext_data_overrun_int_ena:1;
-        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
-         *  enable the timestamp counter overflow interrupt request.
-         */
-        uint32_t ts_counter_ovfl_int_ena:1;
-        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
-         *  1: enabled, if the error status of the TWAI controller changes from error active to
-         *  error passive or vice versa, the respective interrupt is requested. 0: disable
-         */
-        uint32_t err_passive_int_ena:1;
-        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
-         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
-         *  is requested. 0: disable
-         */
-        uint32_t arbitration_lost_int_ena:1;
-        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
-         *  respective interrupt. 0: disable
-         */
-        uint32_t bus_err_int_ena:1;
-        /** idle_int_ena : RO; bitpos: [8]; default: 0;
-         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
-         *  respective interrupt. 0: disable
-         */
-        uint32_t idle_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_interrupt_enable_reg_t;
-
-
-/** Group: Data Registers */
-/** Type of tx_rx_buffer register
- *  Data register.
- */
-typedef union {
-    struct {
-        /** byte : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 0 and when
-         *  software initiate read operation, it is rx data register 0.
-         */
-        uint32_t byte:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_tx_rx_buffer_reg_t;
-
-
-/** Group: Timestamp Register */
-/** Type of timestamp_data register
- *  Timestamp data register
- */
-typedef union {
-    struct {
-        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
-         *  Data of timestamp of a CAN frame.
-         */
-        uint32_t timestamp_data:32;
-    };
-    uint32_t val;
-} twai_timestamp_data_reg_t;
-
-/** Type of timestamp_prescaler register
- *  Timestamp configuration register
- */
-typedef union {
-    struct {
-        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
-         *  Configures the clock division number of timestamp counter.
-         */
-        uint32_t ts_div_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} twai_timestamp_prescaler_reg_t;
-
-/** Type of timestamp_cfg register
- *  Timestamp configuration register
- */
-typedef union {
-    struct {
-        /** ts_enable : R/W; bitpos: [0]; default: 0;
-         *  enable the timestamp collection function.
-         */
-        uint32_t ts_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} twai_timestamp_cfg_reg_t;
-
-typedef struct {
-    union {
-        struct {
-            uint32_t byte: 8;           /* ACRx[7:0] Acceptance Code */
-            uint32_t reserved8: 24;     /* Internal Reserved */
-        };
-        uint32_t val;
-    } acr[4];
-    union {
-        struct {
-            uint32_t byte: 8;           /* AMRx[7:0] Acceptance Mask */
-            uint32_t reserved8: 24;     /* Internal Reserved */
-        };
-        uint32_t val;
-    } amr[4];
-    uint32_t reserved_60[5];
-} acceptance_filter_reg_t;
-
-typedef struct twai_dev_t {
-    volatile twai_mode_reg_t mode;
-    volatile twai_cmd_reg_t cmd;
-    volatile twai_status_reg_t status;
-    volatile twai_interrupt_reg_t interrupt;
-    volatile twai_interrupt_enable_reg_t interrupt_enable;
-    uint32_t reserved_014;
-    volatile twai_bus_timing_0_reg_t bus_timing_0;
-    volatile twai_bus_timing_1_reg_t bus_timing_1;
-    uint32_t reserved_020[3];
-    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
-    volatile twai_err_code_cap_reg_t err_code_cap;
-    volatile twai_err_warning_limit_reg_t err_warning_limit;
-    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
-    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
-    volatile union {
-        acceptance_filter_reg_t acceptance_filter;
-        twai_tx_rx_buffer_reg_t tx_rx_buffer[13];
-    };
-    volatile twai_rx_message_counter_reg_t rx_message_counter;
-    uint32_t reserved_078;
-    volatile twai_clock_divider_reg_t clock_divider;
-    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
-    volatile twai_hw_cfg_reg_t hw_cfg;
-    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
-    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
-    volatile twai_eco_cfg_reg_t eco_cfg;
-    volatile twai_timestamp_data_reg_t timestamp_data;
-    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
-    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
-} twai_dev_t;
-
-extern twai_dev_t TWAI0;
-extern twai_dev_t TWAI1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/uart_channel.h b/components/soc/esp32c5/beta3/include/soc/uart_channel.h
deleted file mode 100644
index a1fc15821c..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/uart_channel.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C5.
-
-#pragma once
-
-//UART channels
-#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  10
-#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  11
-
-#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
-#define UART_RXD_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
diff --git a/components/soc/esp32c5/beta3/include/soc/uart_pins.h b/components/soc/esp32c5/beta3/include/soc/uart_pins.h
deleted file mode 100644
index fd0b0cc76d..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/uart_pins.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/io_mux_reg.h"
-
-/* Specify the number of pins for UART */
-#define SOC_UART_PINS_COUNT  (4)
-
-/* Specify the GPIO pin number for each UART signal in the IOMUX */
-#define U0RXD_GPIO_NUM 11
-#define U0TXD_GPIO_NUM 10
-#define U0RTS_GPIO_NUM (-1)
-#define U0CTS_GPIO_NUM (-1)
-
-#define U1RXD_GPIO_NUM (-1)
-#define U1TXD_GPIO_NUM (-1)
-#define U1RTS_GPIO_NUM (-1)
-#define U1CTS_GPIO_NUM (-1)
-
-#define LP_U0RXD_GPIO_NUM 4
-#define LP_U0TXD_GPIO_NUM 5
-#define LP_U0RTS_GPIO_NUM 2
-#define LP_U0CTS_GPIO_NUM 3
-
-/* The following defines are necessary for reconfiguring the UART
- * to use IOMUX, at runtime. */
-#define U0TXD_MUX_FUNC  (FUNC_U0TXD_U0TXD)
-#define U0RXD_MUX_FUNC  (FUNC_U0RXD_U0RXD)
-/* No func for the following pins, they shall not be used */
-#define U0RTS_MUX_FUNC  (-1)
-#define U0CTS_MUX_FUNC  (-1)
-/* Same goes for UART1 */
-#define U1TXD_MUX_FUNC  (-1)
-#define U1RXD_MUX_FUNC  (-1)
-#define U1RTS_MUX_FUNC  (-1)
-#define U1CTS_MUX_FUNC  (-1)
-
-#define LP_U0TXD_MUX_FUNC  (1)
-#define LP_U0RXD_MUX_FUNC  (1)
-#define LP_U0RTS_MUX_FUNC  (1)
-#define LP_U0CTS_MUX_FUNC  (1)
diff --git a/components/soc/esp32c5/beta3/include/soc/uart_reg.h b/components/soc/esp32c5/beta3/include/soc/uart_reg.h
deleted file mode 100644
index ac864940d8..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/uart_reg.h
+++ /dev/null
@@ -1,1579 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** UART_FIFO_REG register
- *  FIFO data register
- */
-#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
-/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART $n accesses FIFO via this register.
- */
-#define UART_RXFIFO_RD_BYTE    0x000000FFU
-#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
-#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define UART_RXFIFO_RD_BYTE_S  0
-
-/** UART_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
-/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
-#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
-#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_PARITY_ERR_INT_RAW_S  2
-/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define UART_FRM_ERR_INT_RAW    (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
-#define UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_FRM_ERR_INT_RAW_S  3
-/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
-#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define UART_DSR_CHG_INT_RAW    (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
-#define UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define UART_DSR_CHG_INT_RAW_S  5
-/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define UART_CTS_CHG_INT_RAW    (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
-#define UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define UART_CTS_CHG_INT_RAW_S  6
-/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define UART_BRK_DET_INT_RAW    (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
-#define UART_BRK_DET_INT_RAW_V  0x00000001U
-#define UART_BRK_DET_INT_RAW_S  7
-/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XON_INT_RAW    (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
-#define UART_SW_XON_INT_RAW_V  0x00000001U
-#define UART_SW_XON_INT_RAW_S  9
-/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XOFF_INT_RAW    (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
-#define UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define UART_SW_XOFF_INT_RAW_S  10
-/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
-#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define UART_GLITCH_DET_INT_RAW_S  11
-/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters after all data in Tx-FIFO are sent.
- */
-#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
-#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define UART_TX_DONE_INT_RAW    (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
-#define UART_TX_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_DONE_INT_RAW_S  14
-/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  This interrupt raw bit turns to high level when detects a clash between transmitter
- *  and receiver in rs485 mode.
- */
-#define UART_RS485_CLASH_INT_RAW    (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
-#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
-#define UART_RS485_CLASH_INT_RAW_S  17
-/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define UART_WAKEUP_INT_RAW    (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
-#define UART_WAKEUP_INT_RAW_V  0x00000001U
-#define UART_WAKEUP_INT_RAW_S  19
-
-/** UART_INT_ST_REG register
- *  Masked interrupt status
- */
-#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
-/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
-#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ST_S  0
-/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define UART_PARITY_ERR_INT_ST    (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
-#define UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_PARITY_ERR_INT_ST_S  2
-/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define UART_FRM_ERR_INT_ST    (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
-#define UART_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_FRM_ERR_INT_ST_S  3
-/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
-#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define UART_DSR_CHG_INT_ST    (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
-#define UART_DSR_CHG_INT_ST_V  0x00000001U
-#define UART_DSR_CHG_INT_ST_S  5
-/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define UART_CTS_CHG_INT_ST    (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
-#define UART_CTS_CHG_INT_ST_V  0x00000001U
-#define UART_CTS_CHG_INT_ST_S  6
-/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define UART_BRK_DET_INT_ST    (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
-#define UART_BRK_DET_INT_ST_V  0x00000001U
-#define UART_BRK_DET_INT_ST_S  7
-/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
-#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define UART_SW_XON_INT_ST    (BIT(9))
-#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
-#define UART_SW_XON_INT_ST_V  0x00000001U
-#define UART_SW_XON_INT_ST_S  9
-/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define UART_SW_XOFF_INT_ST    (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
-#define UART_SW_XOFF_INT_ST_V  0x00000001U
-#define UART_SW_XOFF_INT_ST_S  10
-/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define UART_GLITCH_DET_INT_ST    (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
-#define UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define UART_GLITCH_DET_INT_ST_S  11
-/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
-#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define UART_TX_DONE_INT_ST    (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
-#define UART_TX_DONE_INT_ST_V  0x00000001U
-#define UART_TX_DONE_INT_ST_S  14
-/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
- *  set to 1.
- */
-#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
- *  to 1.
- */
-#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
-#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
- *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
- */
-#define UART_RS485_CLASH_INT_ST    (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
-#define UART_RS485_CLASH_INT_ST_V  0x00000001U
-#define UART_RS485_CLASH_INT_ST_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define UART_WAKEUP_INT_ST    (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
-#define UART_WAKEUP_INT_ST_V  0x00000001U
-#define UART_WAKEUP_INT_ST_S  19
-
-/** UART_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
-/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
-#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
-#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_PARITY_ERR_INT_ENA_S  2
-/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define UART_FRM_ERR_INT_ENA    (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
-#define UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_FRM_ERR_INT_ENA_S  3
-/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
-#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define UART_DSR_CHG_INT_ENA    (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
-#define UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define UART_DSR_CHG_INT_ENA_S  5
-/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define UART_CTS_CHG_INT_ENA    (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
-#define UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define UART_CTS_CHG_INT_ENA_S  6
-/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define UART_BRK_DET_INT_ENA    (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
-#define UART_BRK_DET_INT_ENA_V  0x00000001U
-#define UART_BRK_DET_INT_ENA_S  7
-/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define UART_SW_XON_INT_ENA    (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
-#define UART_SW_XON_INT_ENA_V  0x00000001U
-#define UART_SW_XON_INT_ENA_S  9
-/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define UART_SW_XOFF_INT_ENA    (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
-#define UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define UART_SW_XOFF_INT_ENA_S  10
-/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
-#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define UART_GLITCH_DET_INT_ENA_S  11
-/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
-#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define UART_TX_DONE_INT_ENA    (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
-#define UART_TX_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_DONE_INT_ENA_S  14
-/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  This is the enable bit for rs485_clash_int_st register.
- */
-#define UART_RS485_CLASH_INT_ENA    (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
-#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
-#define UART_RS485_CLASH_INT_ENA_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define UART_WAKEUP_INT_ENA    (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
-#define UART_WAKEUP_INT_ENA_V  0x00000001U
-#define UART_WAKEUP_INT_ENA_S  19
-
-/** UART_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
-/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
-#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
-#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_PARITY_ERR_INT_CLR_S  2
-/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define UART_FRM_ERR_INT_CLR    (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
-#define UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_FRM_ERR_INT_CLR_S  3
-/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
-#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define UART_DSR_CHG_INT_CLR    (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
-#define UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define UART_DSR_CHG_INT_CLR_S  5
-/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define UART_CTS_CHG_INT_CLR    (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
-#define UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define UART_CTS_CHG_INT_CLR_S  6
-/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define UART_BRK_DET_INT_CLR    (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
-#define UART_BRK_DET_INT_CLR_V  0x00000001U
-#define UART_BRK_DET_INT_CLR_S  7
-/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define UART_SW_XON_INT_CLR    (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
-#define UART_SW_XON_INT_CLR_V  0x00000001U
-#define UART_SW_XON_INT_CLR_S  9
-/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define UART_SW_XOFF_INT_CLR    (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
-#define UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define UART_SW_XOFF_INT_CLR_S  10
-/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
-#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define UART_GLITCH_DET_INT_CLR_S  11
-/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
-#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define UART_TX_DONE_INT_CLR    (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
-#define UART_TX_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_DONE_INT_CLR_S  14
-/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
- */
-#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
- */
-#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the rs485_clash_int_raw interrupt.
- */
-#define UART_RS485_CLASH_INT_CLR    (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
-#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
-#define UART_RS485_CLASH_INT_CLR_S  17
-/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define UART_WAKEUP_INT_CLR    (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
-#define UART_WAKEUP_INT_CLR_V  0x00000001U
-#define UART_WAKEUP_INT_CLR_S  19
-
-/** UART_CLKDIV_SYNC_REG register
- *  Clock divider configuration
- */
-#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
-/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define UART_CLKDIV    0x00000FFFU
-#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
-#define UART_CLKDIV_V  0x00000FFFU
-#define UART_CLKDIV_S  0
-/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define UART_CLKDIV_FRAG    0x0000000FU
-#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
-#define UART_CLKDIV_FRAG_V  0x0000000FU
-#define UART_CLKDIV_FRAG_S  20
-
-/** UART_RX_FILT_REG register
- *  Rx Filter configuration
- */
-#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
-/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value the pulse is ignored.
- */
-#define UART_GLITCH_FILT    0x000000FFU
-#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
-#define UART_GLITCH_FILT_V  0x000000FFU
-#define UART_GLITCH_FILT_S  0
-/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define UART_GLITCH_FILT_EN    (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
-#define UART_GLITCH_FILT_EN_V  0x00000001U
-#define UART_GLITCH_FILT_EN_S  8
-
-/** UART_STATUS_REG register
- *  UART status register
- */
-#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
-/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define UART_RXFIFO_CNT    0x000000FFU
-#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
-#define UART_RXFIFO_CNT_V  0x000000FFU
-#define UART_RXFIFO_CNT_S  0
-/** UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define UART_DSRN    (BIT(13))
-#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
-#define UART_DSRN_V  0x00000001U
-#define UART_DSRN_S  13
-/** UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define UART_CTSN    (BIT(14))
-#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
-#define UART_CTSN_V  0x00000001U
-#define UART_CTSN_S  14
-/** UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define UART_RXD    (BIT(15))
-#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
-#define UART_RXD_V  0x00000001U
-#define UART_RXD_S  15
-/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define UART_TXFIFO_CNT    0x000000FFU
-#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
-#define UART_TXFIFO_CNT_V  0x000000FFU
-#define UART_TXFIFO_CNT_S  16
-/** UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define UART_DTRN    (BIT(29))
-#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
-#define UART_DTRN_V  0x00000001U
-#define UART_DTRN_S  29
-/** UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define UART_RTSN    (BIT(30))
-#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
-#define UART_RTSN_V  0x00000001U
-#define UART_RTSN_S  30
-/** UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define UART_TXD    (BIT(31))
-#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
-#define UART_TXD_V  0x00000001U
-#define UART_TXD_S  31
-
-/** UART_CONF0_SYNC_REG register
- *  a
- */
-#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
-/** UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define UART_PARITY    (BIT(0))
-#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
-#define UART_PARITY_V  0x00000001U
-#define UART_PARITY_S  0
-/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define UART_PARITY_EN    (BIT(1))
-#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
-#define UART_PARITY_EN_V  0x00000001U
-#define UART_PARITY_EN_S  1
-/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define UART_BIT_NUM    0x00000003U
-#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
-#define UART_BIT_NUM_V  0x00000003U
-#define UART_BIT_NUM_S  2
-/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define UART_STOP_BIT_NUM    0x00000003U
-#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
-#define UART_STOP_BIT_NUM_V  0x00000003U
-#define UART_STOP_BIT_NUM_S  4
-/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define UART_TXD_BRK    (BIT(6))
-#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
-#define UART_TXD_BRK_V  0x00000001U
-#define UART_TXD_BRK_S  6
-/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable IrDA loopback mode.
- */
-#define UART_IRDA_DPLX    (BIT(7))
-#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
-#define UART_IRDA_DPLX_V  0x00000001U
-#define UART_IRDA_DPLX_S  7
-/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
- *  This is the start enable bit for IrDA transmitter.
- */
-#define UART_IRDA_TX_EN    (BIT(8))
-#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
-#define UART_IRDA_TX_EN_V  0x00000001U
-#define UART_IRDA_TX_EN_S  8
-/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
- *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
- *  transmitter's 11th bit to 0.
- */
-#define UART_IRDA_WCTL    (BIT(9))
-#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
-#define UART_IRDA_WCTL_V  0x00000001U
-#define UART_IRDA_WCTL_S  9
-/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
- *  Set this bit to invert the level of  IrDA transmitter.
- */
-#define UART_IRDA_TX_INV    (BIT(10))
-#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
-#define UART_IRDA_TX_INV_V  0x00000001U
-#define UART_IRDA_TX_INV_S  10
-/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
- *  Set this bit to invert the level of IrDA receiver.
- */
-#define UART_IRDA_RX_INV    (BIT(11))
-#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
-#define UART_IRDA_RX_INV_V  0x00000001U
-#define UART_IRDA_RX_INV_S  11
-/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define UART_LOOPBACK    (BIT(12))
-#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
-#define UART_LOOPBACK_V  0x00000001U
-#define UART_LOOPBACK_S  12
-/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define UART_TX_FLOW_EN    (BIT(13))
-#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
-#define UART_TX_FLOW_EN_V  0x00000001U
-#define UART_TX_FLOW_EN_S  13
-/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
- *  Set this bit to enable IrDA protocol.
- */
-#define UART_IRDA_EN    (BIT(14))
-#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
-#define UART_IRDA_EN_V  0x00000001U
-#define UART_IRDA_EN_S  14
-/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define UART_RXD_INV    (BIT(15))
-#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
-#define UART_RXD_INV_V  0x00000001U
-#define UART_RXD_INV_S  15
-/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define UART_TXD_INV    (BIT(16))
-#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
-#define UART_TXD_INV_V  0x00000001U
-#define UART_TXD_INV_S  16
-/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define UART_DIS_RX_DAT_OVF    (BIT(17))
-#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
-#define UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define UART_DIS_RX_DAT_OVF_S  17
-/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define UART_ERR_WR_MASK    (BIT(18))
-#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
-#define UART_ERR_WR_MASK_V  0x00000001U
-#define UART_ERR_WR_MASK_S  18
-/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for detecting baudrate.
- */
-#define UART_AUTOBAUD_EN    (BIT(19))
-#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
-#define UART_AUTOBAUD_EN_V  0x00000001U
-#define UART_AUTOBAUD_EN_S  19
-/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
- *  UART memory clock gate enable signal.
- */
-#define UART_MEM_CLK_EN    (BIT(20))
-#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
-#define UART_MEM_CLK_EN_V  0x00000001U
-#define UART_MEM_CLK_EN_S  20
-/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define UART_SW_RTS    (BIT(21))
-#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
-#define UART_SW_RTS_V  0x00000001U
-#define UART_SW_RTS_S  21
-/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define UART_RXFIFO_RST    (BIT(22))
-#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
-#define UART_RXFIFO_RST_V  0x00000001U
-#define UART_RXFIFO_RST_S  22
-/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define UART_TXFIFO_RST    (BIT(23))
-#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
-#define UART_TXFIFO_RST_V  0x00000001U
-#define UART_TXFIFO_RST_S  23
-
-/** UART_CONF1_REG register
- *  Configuration register 1
- */
-#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
-/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define UART_RXFIFO_FULL_THRHD    0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
-#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_S  0
-/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
-#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_S  8
-/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define UART_CTS_INV    (BIT(16))
-#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
-#define UART_CTS_INV_V  0x00000001U
-#define UART_CTS_INV_S  16
-/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define UART_DSR_INV    (BIT(17))
-#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
-#define UART_DSR_INV_V  0x00000001U
-#define UART_DSR_INV_S  17
-/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define UART_RTS_INV    (BIT(18))
-#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
-#define UART_RTS_INV_V  0x00000001U
-#define UART_RTS_INV_S  18
-/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define UART_DTR_INV    (BIT(19))
-#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
-#define UART_DTR_INV_V  0x00000001U
-#define UART_DTR_INV_S  19
-/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define UART_SW_DTR    (BIT(20))
-#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
-#define UART_SW_DTR_V  0x00000001U
-#define UART_SW_DTR_S  20
-/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define UART_CLK_EN    (BIT(21))
-#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
-#define UART_CLK_EN_V  0x00000001U
-#define UART_CLK_EN_S  21
-
-/** UART_HWFC_CONF_SYNC_REG register
- *  Hardware flow-control configuration
- */
-#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
-/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define UART_RX_FLOW_THRHD    0x000000FFU
-#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
-#define UART_RX_FLOW_THRHD_V  0x000000FFU
-#define UART_RX_FLOW_THRHD_S  0
-/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define UART_RX_FLOW_EN    (BIT(8))
-#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
-#define UART_RX_FLOW_EN_V  0x00000001U
-#define UART_RX_FLOW_EN_S  8
-
-/** UART_SLEEP_CONF0_REG register
- *  UART sleep configure register 0
- */
-#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
-/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified wake up char1 to wake up
- */
-#define UART_WK_CHAR1    0x000000FFU
-#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
-#define UART_WK_CHAR1_V  0x000000FFU
-#define UART_WK_CHAR1_S  0
-/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
- *  This register restores the specified wake up char2 to wake up
- */
-#define UART_WK_CHAR2    0x000000FFU
-#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
-#define UART_WK_CHAR2_V  0x000000FFU
-#define UART_WK_CHAR2_S  8
-/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
- *  This register restores the specified wake up char3 to wake up
- */
-#define UART_WK_CHAR3    0x000000FFU
-#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
-#define UART_WK_CHAR3_V  0x000000FFU
-#define UART_WK_CHAR3_S  16
-/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
- *  This register restores the specified wake up char4 to wake up
- */
-#define UART_WK_CHAR4    0x000000FFU
-#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
-#define UART_WK_CHAR4_V  0x000000FFU
-#define UART_WK_CHAR4_S  24
-
-/** UART_SLEEP_CONF1_REG register
- *  UART sleep configure register 1
- */
-#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
-/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified char0 to wake up
- */
-#define UART_WK_CHAR0    0x000000FFU
-#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
-#define UART_WK_CHAR0_V  0x000000FFU
-#define UART_WK_CHAR0_S  0
-
-/** UART_SLEEP_CONF2_REG register
- *  UART sleep configure register 2
- */
-#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
-/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define UART_ACTIVE_THRESHOLD    0x000003FFU
-#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
-#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define UART_ACTIVE_THRESHOLD_S  0
-/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
- *  In wake up mode 1 this field is used to set the received data number threshold to
- *  wake up chip.
- */
-#define UART_RX_WAKE_UP_THRHD    0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
-#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_S  10
-/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
- *  This register is used to select number of wake up char.
- */
-#define UART_WK_CHAR_NUM    0x00000007U
-#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
-#define UART_WK_CHAR_NUM_V  0x00000007U
-#define UART_WK_CHAR_NUM_S  18
-/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
- *  This register is used to mask  wake up char.
- */
-#define UART_WK_CHAR_MASK    0x0000001FU
-#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
-#define UART_WK_CHAR_MASK_V  0x0000001FU
-#define UART_WK_CHAR_MASK_S  21
-/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
- *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
- *  received data number larger than
- */
-#define UART_WK_MODE_SEL    0x00000003U
-#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
-#define UART_WK_MODE_SEL_V  0x00000003U
-#define UART_WK_MODE_SEL_S  26
-
-/** UART_SWFC_CONF0_SYNC_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
-/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define UART_XON_CHAR    0x000000FFU
-#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
-#define UART_XON_CHAR_V  0x000000FFU
-#define UART_XON_CHAR_S  0
-/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define UART_XOFF_CHAR    0x000000FFU
-#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
-#define UART_XOFF_CHAR_V  0x000000FFU
-#define UART_XOFF_CHAR_S  8
-/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
- *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
- *  this status, UART Tx can not transmit XOFF even the received data number is larger
- *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
- *  UART Tx is disabled.
- */
-#define UART_XON_XOFF_STILL_SEND    (BIT(16))
-#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
-#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
-#define UART_XON_XOFF_STILL_SEND_S  16
-/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define UART_SW_FLOW_CON_EN    (BIT(17))
-#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
-#define UART_SW_FLOW_CON_EN_V  0x00000001U
-#define UART_SW_FLOW_CON_EN_S  17
-/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define UART_XONOFF_DEL    (BIT(18))
-#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
-#define UART_XONOFF_DEL_V  0x00000001U
-#define UART_XONOFF_DEL_S  18
-/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define UART_FORCE_XON    (BIT(19))
-#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
-#define UART_FORCE_XON_V  0x00000001U
-#define UART_FORCE_XON_S  19
-/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define UART_FORCE_XOFF    (BIT(20))
-#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
-#define UART_FORCE_XOFF_V  0x00000001U
-#define UART_FORCE_XOFF_S  20
-/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XON    (BIT(21))
-#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
-#define UART_SEND_XON_V  0x00000001U
-#define UART_SEND_XON_S  21
-/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XOFF    (BIT(22))
-#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
-#define UART_SEND_XOFF_V  0x00000001U
-#define UART_SEND_XOFF_S  22
-
-/** UART_SWFC_CONF1_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
-/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xon char.
- */
-#define UART_XON_THRESHOLD    0x000000FFU
-#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
-#define UART_XON_THRESHOLD_V  0x000000FFU
-#define UART_XON_THRESHOLD_S  0
-/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
- */
-#define UART_XOFF_THRESHOLD    0x000000FFU
-#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
-#define UART_XOFF_THRESHOLD_V  0x000000FFU
-#define UART_XOFF_THRESHOLD_S  8
-
-/** UART_TXBRK_CONF_SYNC_REG register
- *  Tx Break character configuration
- */
-#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
-/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define UART_TX_BRK_NUM    0x000000FFU
-#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
-#define UART_TX_BRK_NUM_V  0x000000FFU
-#define UART_TX_BRK_NUM_S  0
-
-/** UART_IDLE_CONF_SYNC_REG register
- *  Frame-end idle configuration
- */
-#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
-/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define UART_RX_IDLE_THRHD    0x000003FFU
-#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
-#define UART_RX_IDLE_THRHD_V  0x000003FFU
-#define UART_RX_IDLE_THRHD_S  0
-/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define UART_TX_IDLE_NUM    0x000003FFU
-#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
-#define UART_TX_IDLE_NUM_V  0x000003FFU
-#define UART_TX_IDLE_NUM_S  10
-
-/** UART_RS485_CONF_SYNC_REG register
- *  RS485 mode configuration
- */
-#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
-/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to choose the rs485 mode.
- */
-#define UART_RS485_EN    (BIT(0))
-#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
-#define UART_RS485_EN_V  0x00000001U
-#define UART_RS485_EN_S  0
-/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL0_EN    (BIT(1))
-#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
-#define UART_DL0_EN_V  0x00000001U
-#define UART_DL0_EN_S  1
-/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL1_EN    (BIT(2))
-#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
-#define UART_DL1_EN_V  0x00000001U
-#define UART_DL1_EN_S  2
-/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable receiver could receive data when the transmitter is
- *  transmitting data in rs485 mode.
- */
-#define UART_RS485TX_RX_EN    (BIT(3))
-#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
-#define UART_RS485TX_RX_EN_V  0x00000001U
-#define UART_RS485TX_RX_EN_S  3
-/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
- *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
- */
-#define UART_RS485RXBY_TX_EN    (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
-#define UART_RS485RXBY_TX_EN_V  0x00000001U
-#define UART_RS485RXBY_TX_EN_S  4
-/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
- *  This register is used to delay the receiver's internal data signal.
- */
-#define UART_RS485_RX_DLY_NUM    (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
-#define UART_RS485_RX_DLY_NUM_V  0x00000001U
-#define UART_RS485_RX_DLY_NUM_S  5
-/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
- *  This register is used to delay the transmitter's internal data signal.
- */
-#define UART_RS485_TX_DLY_NUM    0x0000000FU
-#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
-#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
-#define UART_RS485_TX_DLY_NUM_S  6
-
-/** UART_AT_CMD_PRECNT_SYNC_REG register
- *  Pre-sequence timing configuration
- */
-#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
-/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define UART_PRE_IDLE_NUM    0x0000FFFFU
-#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
-#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define UART_PRE_IDLE_NUM_S  0
-
-/** UART_AT_CMD_POSTCNT_SYNC_REG register
- *  Post-sequence timing configuration
- */
-#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
-/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define UART_POST_IDLE_NUM    0x0000FFFFU
-#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
-#define UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define UART_POST_IDLE_NUM_S  0
-
-/** UART_AT_CMD_GAPTOUT_SYNC_REG register
- *  Timeout configuration
- */
-#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
-/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define UART_RX_GAP_TOUT    0x0000FFFFU
-#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
-#define UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define UART_RX_GAP_TOUT_S  0
-
-/** UART_AT_CMD_CHAR_SYNC_REG register
- *  AT escape sequence detection configuration
- */
-#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
-/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define UART_AT_CMD_CHAR    0x000000FFU
-#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
-#define UART_AT_CMD_CHAR_V  0x000000FFU
-#define UART_AT_CMD_CHAR_S  0
-/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define UART_CHAR_NUM    0x000000FFU
-#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
-#define UART_CHAR_NUM_V  0x000000FFU
-#define UART_CHAR_NUM_S  8
-
-/** UART_MEM_CONF_REG register
- *  UART memory power configuration
- */
-#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
-/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define UART_MEM_FORCE_PD    (BIT(25))
-#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
-#define UART_MEM_FORCE_PD_V  0x00000001U
-#define UART_MEM_FORCE_PD_S  25
-/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define UART_MEM_FORCE_PU    (BIT(26))
-#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
-#define UART_MEM_FORCE_PU_V  0x00000001U
-#define UART_MEM_FORCE_PU_S  26
-
-/** UART_TOUT_CONF_SYNC_REG register
- *  UART threshold and allocation configuration
- */
-#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
-/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define UART_RX_TOUT_EN    (BIT(0))
-#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
-#define UART_RX_TOUT_EN_V  0x00000001U
-#define UART_RX_TOUT_EN_S  0
-/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
-#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
-#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define UART_RX_TOUT_FLOW_DIS_S  1
-/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define UART_RX_TOUT_THRHD    0x000003FFU
-#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
-#define UART_RX_TOUT_THRHD_V  0x000003FFU
-#define UART_RX_TOUT_THRHD_S  2
-
-/** UART_MEM_TX_STATUS_REG register
- *  Tx-SRAM write and read offset address.
- */
-#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
-/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
- *  This register stores the offset write address in Tx-SRAM.
- */
-#define UART_TX_SRAM_WADDR    0x000000FFU
-#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
-#define UART_TX_SRAM_WADDR_V  0x000000FFU
-#define UART_TX_SRAM_WADDR_S  0
-/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
- *  This register stores the offset read address in Tx-SRAM.
- */
-#define UART_TX_SRAM_RADDR    0x000000FFU
-#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
-#define UART_TX_SRAM_RADDR_V  0x000000FFU
-#define UART_TX_SRAM_RADDR_S  9
-
-/** UART_MEM_RX_STATUS_REG register
- *  Rx-SRAM write and read offset address.
- */
-#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
-/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
- *  This register stores the offset read address in RX-SRAM.
- */
-#define UART_RX_SRAM_RADDR    0x000000FFU
-#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
-#define UART_RX_SRAM_RADDR_V  0x000000FFU
-#define UART_RX_SRAM_RADDR_S  0
-/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
- *  This register stores the offset write address in Rx-SRAM.
- */
-#define UART_RX_SRAM_WADDR    0x000000FFU
-#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
-#define UART_RX_SRAM_WADDR_V  0x000000FFU
-#define UART_RX_SRAM_WADDR_S  9
-
-/** UART_FSM_STATUS_REG register
- *  UART transmit and receive status.
- */
-#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
-/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define UART_ST_URX_OUT    0x0000000FU
-#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
-#define UART_ST_URX_OUT_V  0x0000000FU
-#define UART_ST_URX_OUT_S  0
-/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define UART_ST_UTX_OUT    0x0000000FU
-#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
-#define UART_ST_UTX_OUT_V  0x0000000FU
-#define UART_ST_UTX_OUT_S  4
-
-/** UART_POSPULSE_REG register
- *  Autobaud high pulse register
- */
-#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
-/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two positive edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_POSEDGE_MIN_CNT    0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
-#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_S  0
-
-/** UART_NEGPULSE_REG register
- *  Autobaud low pulse register
- */
-#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
-/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two negative edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
-#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-/** UART_LOWPULSE_REG register
- *  Autobaud minimum low pulse duration register
- */
-#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
-/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the value of the minimum duration time of the low level pulse.
- *  It is used in baud rate-detect process.
- */
-#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
-#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-/** UART_HIGHPULSE_REG register
- *  Autobaud minimum high pulse duration register
- */
-#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
-/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores  the value of the maxinum duration time for the high level
- *  pulse. It is used in baud rate-detect process.
- */
-#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
-#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-/** UART_RXD_CNT_REG register
- *  Autobaud edge change count register
- */
-#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
-/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
- *  This register stores the count of rxd edge change. It is used in baud rate-detect
- *  process.
- */
-#define UART_RXD_EDGE_CNT    0x000003FFU
-#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
-#define UART_RXD_EDGE_CNT_V  0x000003FFU
-#define UART_RXD_EDGE_CNT_S  0
-
-/** UART_CLK_CONF_REG register
- *  UART core clock configuration
- */
-#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
-/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
- *  Set this bit to enable UART Tx clock.
- */
-#define UART_TX_SCLK_EN    (BIT(24))
-#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
-#define UART_TX_SCLK_EN_V  0x00000001U
-#define UART_TX_SCLK_EN_S  24
-/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
- *  Set this bit to enable UART Rx clock.
- */
-#define UART_RX_SCLK_EN    (BIT(25))
-#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
-#define UART_RX_SCLK_EN_V  0x00000001U
-#define UART_RX_SCLK_EN_S  25
-/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx.
- */
-#define UART_TX_RST_CORE    (BIT(26))
-#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
-#define UART_TX_RST_CORE_V  0x00000001U
-#define UART_TX_RST_CORE_S  26
-/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Rx.
- */
-#define UART_RX_RST_CORE    (BIT(27))
-#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
-#define UART_RX_RST_CORE_V  0x00000001U
-#define UART_RX_RST_CORE_S  27
-
-/** UART_DATE_REG register
- *  UART Version register
- */
-#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
-/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848;
- *  This is the version register.
- */
-#define UART_DATE    0xFFFFFFFFU
-#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
-#define UART_DATE_V  0xFFFFFFFFU
-#define UART_DATE_S  0
-
-/** UART_AFIFO_STATUS_REG register
- *  UART AFIFO Status
- */
-#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
-/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
- *  Full signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_FULL    (BIT(0))
-#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
-#define UART_TX_AFIFO_FULL_V  0x00000001U
-#define UART_TX_AFIFO_FULL_S  0
-/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
- *  Empty signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_EMPTY    (BIT(1))
-#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
-#define UART_TX_AFIFO_EMPTY_V  0x00000001U
-#define UART_TX_AFIFO_EMPTY_S  1
-/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
- *  Full signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_FULL    (BIT(2))
-#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
-#define UART_RX_AFIFO_FULL_V  0x00000001U
-#define UART_RX_AFIFO_FULL_S  2
-/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
- *  Empty signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_EMPTY    (BIT(3))
-#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
-#define UART_RX_AFIFO_EMPTY_V  0x00000001U
-#define UART_RX_AFIFO_EMPTY_S  3
-
-/** UART_REG_UPDATE_REG register
- *  UART Registers Configuration Update register
- */
-#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
-/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define UART_REG_UPDATE    (BIT(0))
-#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
-#define UART_REG_UPDATE_V  0x00000001U
-#define UART_REG_UPDATE_S  0
-
-/** UART_ID_REG register
- *  UART ID register
- */
-#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
-/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define UART_ID    0xFFFFFFFFU
-#define UART_ID_M  (UART_ID_V << UART_ID_S)
-#define UART_ID_V  0xFFFFFFFFU
-#define UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/uart_struct.h b/components/soc/esp32c5/beta3/include/soc/uart_struct.h
deleted file mode 100644
index 734f18d6b7..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/uart_struct.h
+++ /dev/null
@@ -1,1294 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         */
-        uint32_t rxfifo_rd_byte:32;
-    };
-    uint32_t val;
-} uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full_int_raw:1;
-        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty_int_raw:1;
-        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err_int_raw:1;
-        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg_int_raw:1;
-        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg_int_raw:1;
-        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det_int_raw:1;
-        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout_int_raw:1;
-        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon_int_raw:1;
-        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff_int_raw:1;
-        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det_int_raw:1;
-        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done_int_raw:1;
-        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done_int_raw:1;
-        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_parity_err_int_raw:1;
-        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_frm_err_int_raw:1;
-        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  This interrupt raw bit turns to high level when detects a clash between transmitter
-         *  and receiver in rs485 mode.
-         */
-        uint32_t rs485_clash_int_raw:1;
-        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det_int_raw:1;
-        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup_int_raw:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full_int_st:1;
-        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty_int_st:1;
-        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err_int_st:1;
-        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg_int_st:1;
-        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg_int_st:1;
-        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det_int_st:1;
-        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout_int_st:1;
-        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon_int_st:1;
-        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff_int_st:1;
-        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det_int_st:1;
-        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done_int_st:1;
-        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done_int_st:1;
-        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
-         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-         *  set to 1.
-         */
-        uint32_t rs485_parity_err_int_st:1;
-        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
-         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
-         *  to 1.
-         */
-        uint32_t rs485_frm_err_int_st:1;
-        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
-         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
-         */
-        uint32_t rs485_clash_int_st:1;
-        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det_int_st:1;
-        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup_int_st:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full_int_ena:1;
-        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty_int_ena:1;
-        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err_int_ena:1;
-        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg_int_ena:1;
-        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg_int_ena:1;
-        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det_int_ena:1;
-        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout_int_ena:1;
-        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon_int_ena:1;
-        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff_int_ena:1;
-        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det_int_ena:1;
-        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done_int_ena:1;
-        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_parity_err_int_ena:1;
-        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_frm_err_int_ena:1;
-        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
-         *  This is the enable bit for rs485_clash_int_st register.
-         */
-        uint32_t rs485_clash_int_ena:1;
-        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det_int_ena:1;
-        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup_int_ena:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full_int_clr:1;
-        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty_int_clr:1;
-        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err_int_clr:1;
-        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg_int_clr:1;
-        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg_int_clr:1;
-        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det_int_clr:1;
-        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout_int_clr:1;
-        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon_int_clr:1;
-        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff_int_clr:1;
-        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det_int_clr:1;
-        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done_int_clr:1;
-        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
-         */
-        uint32_t rs485_parity_err_int_clr:1;
-        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
-         */
-        uint32_t rs485_frm_err_int_clr:1;
-        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the rs485_clash_int_raw interrupt.
-         */
-        uint32_t rs485_clash_int_clr:1;
-        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det_int_clr:1;
-        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup_int_clr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv_int:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  a
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        /** irda_dplx : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable IrDA loopback mode.
-         */
-        uint32_t irda_dplx:1;
-        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
-         *  This is the start enable bit for IrDA transmitter.
-         */
-        uint32_t irda_tx_en:1;
-        /** irda_wctl : R/W; bitpos: [9]; default: 0;
-         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-         *  transmitter's 11th bit to 0.
-         */
-        uint32_t irda_wctl:1;
-        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to invert the level of  IrDA transmitter.
-         */
-        uint32_t irda_tx_inv:1;
-        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
-         *  Set this bit to invert the level of IrDA receiver.
-         */
-        uint32_t irda_rx_inv:1;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        /** irda_en : R/W; bitpos: [14]; default: 0;
-         *  Set this bit to enable IrDA protocol.
-         */
-        uint32_t irda_en:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        /** autobaud_en : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for detecting baudrate.
-         */
-        uint32_t autobaud_en:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:8;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:8;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow-control configuration
- */
-typedef union {
-    struct {
-        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:8;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configure register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified wake up char1 to wake up
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  This register restores the specified wake up char2 to wake up
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  This register restores the specified wake up char3 to wake up
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  This register restores the specified wake up char4 to wake up
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configure register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified char0 to wake up
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configure register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
-         *  In wake up mode 1 this field is used to set the received data number threshold to
-         *  wake up chip.
-         */
-        uint32_t rx_wake_up_thrhd:8;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  This register is used to select number of wake up char.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  This register is used to mask  wake up char.
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
-         *  received data number larger than
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
-         *  this status, UART Tx can not transmit XOFF even the received data number is larger
-         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
-         *  UART Tx is disabled.
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
-         */
-        uint32_t xon_threshold:8;
-        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        /** rs485_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to choose the rs485 mode.
-         */
-        uint32_t rs485_en:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable receiver could receive data when the transmitter is
-         *  transmitting data in rs485 mode.
-         */
-        uint32_t rs485tx_rx_en:1;
-        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
-         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-         */
-        uint32_t rs485rxby_tx_en:1;
-        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
-         *  This register is used to delay the receiver's internal data signal.
-         */
-        uint32_t rs485_rx_dly_num:1;
-        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
-         *  This register is used to delay the transmitter's internal data signal.
-         */
-        uint32_t rs485_tx_dly_num:4;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor.
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor.
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
-         */
-        uint32_t sclk_sel:2;
-        /** sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set this bit to enable UART Tx/Rx clock.
-         */
-        uint32_t sclk_en:1;
-        /** rst_core : R/W; bitpos: [23]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
-         */
-        uint32_t rst_core:1;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Set this bit to enable UART Tx clock.
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Set this bit to enable UART Rx clock.
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Rx.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:8;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:8;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
-         *  This register stores the offset write address in Tx-SRAM.
-         */
-        uint32_t tx_sram_waddr:8;
-        uint32_t reserved_8:1;
-        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
-         *  This register stores the offset read address in Tx-SRAM.
-         */
-        uint32_t tx_sram_raddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
-         *  This register stores the offset read address in RX-SRAM.
-         */
-        uint32_t rx_sram_raddr:8;
-        uint32_t reserved_8:1;
-        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
-         *  This register stores the offset write address in Rx-SRAM.
-         */
-        uint32_t rx_sram_waddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART AFIFO Status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Full signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Empty signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Full signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Empty signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t at_cmd_char:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Autobaud Register */
-/** Type of pospulse register
- *  Autobaud high pulse register
- */
-typedef union {
-    struct {
-        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two positive edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t posedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_pospulse_reg_t;
-
-/** Type of negpulse register
- *  Autobaud low pulse register
- */
-typedef union {
-    struct {
-        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two negative edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t negedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_negpulse_reg_t;
-
-/** Type of lowpulse register
- *  Autobaud minimum low pulse duration register
- */
-typedef union {
-    struct {
-        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the value of the minimum duration time of the low level pulse.
-         *  It is used in baud rate-detect process.
-         */
-        uint32_t lowpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_lowpulse_reg_t;
-
-/** Type of highpulse register
- *  Autobaud minimum high pulse duration register
- */
-typedef union {
-    struct {
-        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores  the value of the maxinum duration time for the high level
-         *  pulse. It is used in baud rate-detect process.
-         */
-        uint32_t highpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_highpulse_reg_t;
-
-/** Type of rxd_cnt register
- *  Autobaud edge change count register
- */
-typedef union {
-    struct {
-        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
-         *  This register stores the count of rxd edge change. It is used in baud rate-detect
-         *  process.
-         */
-        uint32_t rxd_edge_cnt:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rxd_cnt_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35680848;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART Registers Configuration Update register
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} uart_id_reg_t;
-
-
-typedef struct uart_dev_t {
-    volatile uart_fifo_reg_t fifo;
-    volatile uart_int_raw_reg_t int_raw;
-    volatile uart_int_st_reg_t int_st;
-    volatile uart_int_ena_reg_t int_ena;
-    volatile uart_int_clr_reg_t int_clr;
-    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile uart_rx_filt_reg_t rx_filt;
-    volatile uart_status_reg_t status;
-    volatile uart_conf0_sync_reg_t conf0_sync;
-    volatile uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile uart_sleep_conf0_reg_t sleep_conf0;
-    volatile uart_sleep_conf1_reg_t sleep_conf1;
-    volatile uart_sleep_conf2_reg_t sleep_conf2;
-    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile uart_swfc_conf1_reg_t swfc_conf1;
-    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile uart_mem_conf_reg_t mem_conf;
-    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile uart_mem_tx_status_reg_t mem_tx_status;
-    volatile uart_mem_rx_status_reg_t mem_rx_status;
-    volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;
-    volatile uart_negpulse_reg_t negpulse;
-    volatile uart_lowpulse_reg_t lowpulse;
-    volatile uart_highpulse_reg_t highpulse;
-    volatile uart_rxd_cnt_reg_t rxd_cnt;
-    volatile uart_clk_conf_reg_t clk_conf;
-    volatile uart_date_reg_t date;
-    volatile uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile uart_reg_update_reg_t reg_update;
-    volatile uart_id_reg_t id;
-} uart_dev_t;
-
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-extern uart_dev_t LP_UART;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/uhci_reg.h b/components/soc/esp32c5/beta3/include/soc/uhci_reg.h
deleted file mode 100644
index af11531832..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/uhci_reg.h
+++ /dev/null
@@ -1,966 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** UHCI_CONF0_REG register
- *  UHCI Configuration Register0
- */
-#define UHCI_CONF0_REG (DR_REG_UHCI_BASE + 0x0)
-/** UHCI_TX_RST : R/W; bitpos: [0]; default: 0;
- *  Write 1 then write 0 to this bit to reset decode state machine.
- */
-#define UHCI_TX_RST    (BIT(0))
-#define UHCI_TX_RST_M  (UHCI_TX_RST_V << UHCI_TX_RST_S)
-#define UHCI_TX_RST_V  0x00000001U
-#define UHCI_TX_RST_S  0
-/** UHCI_RX_RST : R/W; bitpos: [1]; default: 0;
- *  Write 1 then write 0 to this bit to reset encode state machine.
- */
-#define UHCI_RX_RST    (BIT(1))
-#define UHCI_RX_RST_M  (UHCI_RX_RST_V << UHCI_RX_RST_S)
-#define UHCI_RX_RST_V  0x00000001U
-#define UHCI_RX_RST_S  1
-/** UHCI_UART_SEL : R/W; bitpos: [4:2]; default: 7;
- *  Select which uart to connect with GDMA.
- */
-#define UHCI_UART_SEL    0x00000007U
-#define UHCI_UART_SEL_M  (UHCI_UART_SEL_V << UHCI_UART_SEL_S)
-#define UHCI_UART_SEL_V  0x00000007U
-#define UHCI_UART_SEL_S  2
-/** UHCI_SEPER_EN : R/W; bitpos: [5]; default: 1;
- *  Set this bit to separate the data frame using a special char.
- */
-#define UHCI_SEPER_EN    (BIT(5))
-#define UHCI_SEPER_EN_M  (UHCI_SEPER_EN_V << UHCI_SEPER_EN_S)
-#define UHCI_SEPER_EN_V  0x00000001U
-#define UHCI_SEPER_EN_S  5
-/** UHCI_HEAD_EN : R/W; bitpos: [6]; default: 1;
- *  Set this bit to encode the data packet with a formatting header.
- */
-#define UHCI_HEAD_EN    (BIT(6))
-#define UHCI_HEAD_EN_M  (UHCI_HEAD_EN_V << UHCI_HEAD_EN_S)
-#define UHCI_HEAD_EN_V  0x00000001U
-#define UHCI_HEAD_EN_S  6
-/** UHCI_CRC_REC_EN : R/W; bitpos: [7]; default: 1;
- *  Set this bit to enable UHCI to receive the 16 bit CRC.
- */
-#define UHCI_CRC_REC_EN    (BIT(7))
-#define UHCI_CRC_REC_EN_M  (UHCI_CRC_REC_EN_V << UHCI_CRC_REC_EN_S)
-#define UHCI_CRC_REC_EN_V  0x00000001U
-#define UHCI_CRC_REC_EN_S  7
-/** UHCI_UART_IDLE_EOF_EN : R/W; bitpos: [8]; default: 0;
- *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
- *  been in idle state.
- */
-#define UHCI_UART_IDLE_EOF_EN    (BIT(8))
-#define UHCI_UART_IDLE_EOF_EN_M  (UHCI_UART_IDLE_EOF_EN_V << UHCI_UART_IDLE_EOF_EN_S)
-#define UHCI_UART_IDLE_EOF_EN_V  0x00000001U
-#define UHCI_UART_IDLE_EOF_EN_S  8
-/** UHCI_LEN_EOF_EN : R/W; bitpos: [9]; default: 1;
- *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
- *  receiving byte count has reached the specified value. The value is payload length
- *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
- *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
- *  receiving payload data is end when 0xc0 is received.
- */
-#define UHCI_LEN_EOF_EN    (BIT(9))
-#define UHCI_LEN_EOF_EN_M  (UHCI_LEN_EOF_EN_V << UHCI_LEN_EOF_EN_S)
-#define UHCI_LEN_EOF_EN_V  0x00000001U
-#define UHCI_LEN_EOF_EN_S  9
-/** UHCI_ENCODE_CRC_EN : R/W; bitpos: [10]; default: 1;
- *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
- *  end of the payload.
- */
-#define UHCI_ENCODE_CRC_EN    (BIT(10))
-#define UHCI_ENCODE_CRC_EN_M  (UHCI_ENCODE_CRC_EN_V << UHCI_ENCODE_CRC_EN_S)
-#define UHCI_ENCODE_CRC_EN_V  0x00000001U
-#define UHCI_ENCODE_CRC_EN_S  10
-/** UHCI_CLK_EN : R/W; bitpos: [11]; default: 0;
- *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
- *  registers.
- */
-#define UHCI_CLK_EN    (BIT(11))
-#define UHCI_CLK_EN_M  (UHCI_CLK_EN_V << UHCI_CLK_EN_S)
-#define UHCI_CLK_EN_V  0x00000001U
-#define UHCI_CLK_EN_S  11
-/** UHCI_UART_RX_BRK_EOF_EN : R/W; bitpos: [12]; default: 0;
- *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
- *  received by UART.
- */
-#define UHCI_UART_RX_BRK_EOF_EN    (BIT(12))
-#define UHCI_UART_RX_BRK_EOF_EN_M  (UHCI_UART_RX_BRK_EOF_EN_V << UHCI_UART_RX_BRK_EOF_EN_S)
-#define UHCI_UART_RX_BRK_EOF_EN_V  0x00000001U
-#define UHCI_UART_RX_BRK_EOF_EN_S  12
-
-/** UHCI_INT_RAW_REG register
- *  UHCI Interrupt Raw Register
- */
-#define UHCI_INT_RAW_REG (DR_REG_UHCI_BASE + 0x4)
-/** UHCI_RX_START_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
- *  delimiter is sent successfully.
- */
-#define UHCI_RX_START_INT_RAW    (BIT(0))
-#define UHCI_RX_START_INT_RAW_M  (UHCI_RX_START_INT_RAW_V << UHCI_RX_START_INT_RAW_S)
-#define UHCI_RX_START_INT_RAW_V  0x00000001U
-#define UHCI_RX_START_INT_RAW_S  0
-/** UHCI_TX_START_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
- *  DMA detects delimiter.
- */
-#define UHCI_TX_START_INT_RAW    (BIT(1))
-#define UHCI_TX_START_INT_RAW_M  (UHCI_TX_START_INT_RAW_V << UHCI_TX_START_INT_RAW_S)
-#define UHCI_TX_START_INT_RAW_V  0x00000001U
-#define UHCI_TX_START_INT_RAW_S  1
-/** UHCI_RX_HUNG_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
- *  the required time of DMA receiving data  exceeds the configuration value.
- */
-#define UHCI_RX_HUNG_INT_RAW    (BIT(2))
-#define UHCI_RX_HUNG_INT_RAW_M  (UHCI_RX_HUNG_INT_RAW_V << UHCI_RX_HUNG_INT_RAW_S)
-#define UHCI_RX_HUNG_INT_RAW_V  0x00000001U
-#define UHCI_RX_HUNG_INT_RAW_S  2
-/** UHCI_TX_HUNG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
- *  the required time of DMA reading RAM data  exceeds the configuration value.
- */
-#define UHCI_TX_HUNG_INT_RAW    (BIT(3))
-#define UHCI_TX_HUNG_INT_RAW_M  (UHCI_TX_HUNG_INT_RAW_V << UHCI_TX_HUNG_INT_RAW_S)
-#define UHCI_TX_HUNG_INT_RAW_V  0x00000001U
-#define UHCI_TX_HUNG_INT_RAW_S  3
-/** UHCI_SEND_S_REG_Q_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
- *  when UHCI sends short packet successfully with single_send mode.
- */
-#define UHCI_SEND_S_REG_Q_INT_RAW    (BIT(4))
-#define UHCI_SEND_S_REG_Q_INT_RAW_M  (UHCI_SEND_S_REG_Q_INT_RAW_V << UHCI_SEND_S_REG_Q_INT_RAW_S)
-#define UHCI_SEND_S_REG_Q_INT_RAW_V  0x00000001U
-#define UHCI_SEND_S_REG_Q_INT_RAW_S  4
-/** UHCI_SEND_A_REG_Q_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
- *  when UHCI sends short packet successfully with always_send mode.
- */
-#define UHCI_SEND_A_REG_Q_INT_RAW    (BIT(5))
-#define UHCI_SEND_A_REG_Q_INT_RAW_M  (UHCI_SEND_A_REG_Q_INT_RAW_V << UHCI_SEND_A_REG_Q_INT_RAW_S)
-#define UHCI_SEND_A_REG_Q_INT_RAW_V  0x00000001U
-#define UHCI_SEND_A_REG_Q_INT_RAW_S  5
-/** UHCI_OUT_EOF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
- *  there are errors in EOF.
- */
-#define UHCI_OUT_EOF_INT_RAW    (BIT(6))
-#define UHCI_OUT_EOF_INT_RAW_M  (UHCI_OUT_EOF_INT_RAW_V << UHCI_OUT_EOF_INT_RAW_S)
-#define UHCI_OUT_EOF_INT_RAW_V  0x00000001U
-#define UHCI_OUT_EOF_INT_RAW_S  6
-/** UHCI_APP_CTRL0_INT_RAW : R/W; bitpos: [7]; default: 0;
- *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
- *  UHCI_APP_CTRL0_IN_SET is set to 1.
- */
-#define UHCI_APP_CTRL0_INT_RAW    (BIT(7))
-#define UHCI_APP_CTRL0_INT_RAW_M  (UHCI_APP_CTRL0_INT_RAW_V << UHCI_APP_CTRL0_INT_RAW_S)
-#define UHCI_APP_CTRL0_INT_RAW_V  0x00000001U
-#define UHCI_APP_CTRL0_INT_RAW_S  7
-/** UHCI_APP_CTRL1_INT_RAW : R/W; bitpos: [8]; default: 0;
- *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
- *  UHCI_APP_CTRL1_IN_SET is set to 1.
- */
-#define UHCI_APP_CTRL1_INT_RAW    (BIT(8))
-#define UHCI_APP_CTRL1_INT_RAW_M  (UHCI_APP_CTRL1_INT_RAW_V << UHCI_APP_CTRL1_INT_RAW_S)
-#define UHCI_APP_CTRL1_INT_RAW_V  0x00000001U
-#define UHCI_APP_CTRL1_INT_RAW_S  8
-
-/** UHCI_INT_ST_REG register
- *  UHCI Interrupt Status Register
- */
-#define UHCI_INT_ST_REG (DR_REG_UHCI_BASE + 0x8)
-/** UHCI_RX_START_INT_ST : RO; bitpos: [0]; default: 0;
- *  Indicates the interrupt status of UHCI_RX_START_INT.
- */
-#define UHCI_RX_START_INT_ST    (BIT(0))
-#define UHCI_RX_START_INT_ST_M  (UHCI_RX_START_INT_ST_V << UHCI_RX_START_INT_ST_S)
-#define UHCI_RX_START_INT_ST_V  0x00000001U
-#define UHCI_RX_START_INT_ST_S  0
-/** UHCI_TX_START_INT_ST : RO; bitpos: [1]; default: 0;
- *  Indicates the interrupt status of UHCI_TX_START_INT.
- */
-#define UHCI_TX_START_INT_ST    (BIT(1))
-#define UHCI_TX_START_INT_ST_M  (UHCI_TX_START_INT_ST_V << UHCI_TX_START_INT_ST_S)
-#define UHCI_TX_START_INT_ST_V  0x00000001U
-#define UHCI_TX_START_INT_ST_S  1
-/** UHCI_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
- *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
- */
-#define UHCI_RX_HUNG_INT_ST    (BIT(2))
-#define UHCI_RX_HUNG_INT_ST_M  (UHCI_RX_HUNG_INT_ST_V << UHCI_RX_HUNG_INT_ST_S)
-#define UHCI_RX_HUNG_INT_ST_V  0x00000001U
-#define UHCI_RX_HUNG_INT_ST_S  2
-/** UHCI_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
- *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
- */
-#define UHCI_TX_HUNG_INT_ST    (BIT(3))
-#define UHCI_TX_HUNG_INT_ST_M  (UHCI_TX_HUNG_INT_ST_V << UHCI_TX_HUNG_INT_ST_S)
-#define UHCI_TX_HUNG_INT_ST_V  0x00000001U
-#define UHCI_TX_HUNG_INT_ST_S  3
-/** UHCI_SEND_S_REG_Q_INT_ST : RO; bitpos: [4]; default: 0;
- *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
- */
-#define UHCI_SEND_S_REG_Q_INT_ST    (BIT(4))
-#define UHCI_SEND_S_REG_Q_INT_ST_M  (UHCI_SEND_S_REG_Q_INT_ST_V << UHCI_SEND_S_REG_Q_INT_ST_S)
-#define UHCI_SEND_S_REG_Q_INT_ST_V  0x00000001U
-#define UHCI_SEND_S_REG_Q_INT_ST_S  4
-/** UHCI_SEND_A_REG_Q_INT_ST : RO; bitpos: [5]; default: 0;
- *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
- */
-#define UHCI_SEND_A_REG_Q_INT_ST    (BIT(5))
-#define UHCI_SEND_A_REG_Q_INT_ST_M  (UHCI_SEND_A_REG_Q_INT_ST_V << UHCI_SEND_A_REG_Q_INT_ST_S)
-#define UHCI_SEND_A_REG_Q_INT_ST_V  0x00000001U
-#define UHCI_SEND_A_REG_Q_INT_ST_S  5
-/** UHCI_OUTLINK_EOF_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
- */
-#define UHCI_OUTLINK_EOF_ERR_INT_ST    (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (UHCI_OUTLINK_EOF_ERR_INT_ST_V << UHCI_OUTLINK_EOF_ERR_INT_ST_S)
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x00000001U
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
-/** UHCI_APP_CTRL0_INT_ST : RO; bitpos: [7]; default: 0;
- *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
- */
-#define UHCI_APP_CTRL0_INT_ST    (BIT(7))
-#define UHCI_APP_CTRL0_INT_ST_M  (UHCI_APP_CTRL0_INT_ST_V << UHCI_APP_CTRL0_INT_ST_S)
-#define UHCI_APP_CTRL0_INT_ST_V  0x00000001U
-#define UHCI_APP_CTRL0_INT_ST_S  7
-/** UHCI_APP_CTRL1_INT_ST : RO; bitpos: [8]; default: 0;
- *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
- */
-#define UHCI_APP_CTRL1_INT_ST    (BIT(8))
-#define UHCI_APP_CTRL1_INT_ST_M  (UHCI_APP_CTRL1_INT_ST_V << UHCI_APP_CTRL1_INT_ST_S)
-#define UHCI_APP_CTRL1_INT_ST_V  0x00000001U
-#define UHCI_APP_CTRL1_INT_ST_S  8
-
-/** UHCI_INT_ENA_REG register
- *  UHCI Interrupt Enable Register
- */
-#define UHCI_INT_ENA_REG (DR_REG_UHCI_BASE + 0xc)
-/** UHCI_RX_START_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
- */
-#define UHCI_RX_START_INT_ENA    (BIT(0))
-#define UHCI_RX_START_INT_ENA_M  (UHCI_RX_START_INT_ENA_V << UHCI_RX_START_INT_ENA_S)
-#define UHCI_RX_START_INT_ENA_V  0x00000001U
-#define UHCI_RX_START_INT_ENA_S  0
-/** UHCI_TX_START_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
- */
-#define UHCI_TX_START_INT_ENA    (BIT(1))
-#define UHCI_TX_START_INT_ENA_M  (UHCI_TX_START_INT_ENA_V << UHCI_TX_START_INT_ENA_S)
-#define UHCI_TX_START_INT_ENA_V  0x00000001U
-#define UHCI_TX_START_INT_ENA_S  1
-/** UHCI_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
- */
-#define UHCI_RX_HUNG_INT_ENA    (BIT(2))
-#define UHCI_RX_HUNG_INT_ENA_M  (UHCI_RX_HUNG_INT_ENA_V << UHCI_RX_HUNG_INT_ENA_S)
-#define UHCI_RX_HUNG_INT_ENA_V  0x00000001U
-#define UHCI_RX_HUNG_INT_ENA_S  2
-/** UHCI_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
- */
-#define UHCI_TX_HUNG_INT_ENA    (BIT(3))
-#define UHCI_TX_HUNG_INT_ENA_M  (UHCI_TX_HUNG_INT_ENA_V << UHCI_TX_HUNG_INT_ENA_S)
-#define UHCI_TX_HUNG_INT_ENA_V  0x00000001U
-#define UHCI_TX_HUNG_INT_ENA_S  3
-/** UHCI_SEND_S_REG_Q_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
- */
-#define UHCI_SEND_S_REG_Q_INT_ENA    (BIT(4))
-#define UHCI_SEND_S_REG_Q_INT_ENA_M  (UHCI_SEND_S_REG_Q_INT_ENA_V << UHCI_SEND_S_REG_Q_INT_ENA_S)
-#define UHCI_SEND_S_REG_Q_INT_ENA_V  0x00000001U
-#define UHCI_SEND_S_REG_Q_INT_ENA_S  4
-/** UHCI_SEND_A_REG_Q_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
- */
-#define UHCI_SEND_A_REG_Q_INT_ENA    (BIT(5))
-#define UHCI_SEND_A_REG_Q_INT_ENA_M  (UHCI_SEND_A_REG_Q_INT_ENA_V << UHCI_SEND_A_REG_Q_INT_ENA_S)
-#define UHCI_SEND_A_REG_Q_INT_ENA_V  0x00000001U
-#define UHCI_SEND_A_REG_Q_INT_ENA_S  5
-/** UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
- */
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA    (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (UHCI_OUTLINK_EOF_ERR_INT_ENA_V << UHCI_OUTLINK_EOF_ERR_INT_ENA_S)
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x00000001U
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
-/** UHCI_APP_CTRL0_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
- */
-#define UHCI_APP_CTRL0_INT_ENA    (BIT(7))
-#define UHCI_APP_CTRL0_INT_ENA_M  (UHCI_APP_CTRL0_INT_ENA_V << UHCI_APP_CTRL0_INT_ENA_S)
-#define UHCI_APP_CTRL0_INT_ENA_V  0x00000001U
-#define UHCI_APP_CTRL0_INT_ENA_S  7
-/** UHCI_APP_CTRL1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
- */
-#define UHCI_APP_CTRL1_INT_ENA    (BIT(8))
-#define UHCI_APP_CTRL1_INT_ENA_M  (UHCI_APP_CTRL1_INT_ENA_V << UHCI_APP_CTRL1_INT_ENA_S)
-#define UHCI_APP_CTRL1_INT_ENA_V  0x00000001U
-#define UHCI_APP_CTRL1_INT_ENA_S  8
-
-/** UHCI_INT_CLR_REG register
- *  UHCI Interrupt Clear Register
- */
-#define UHCI_INT_CLR_REG (DR_REG_UHCI_BASE + 0x10)
-/** UHCI_RX_START_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
- */
-#define UHCI_RX_START_INT_CLR    (BIT(0))
-#define UHCI_RX_START_INT_CLR_M  (UHCI_RX_START_INT_CLR_V << UHCI_RX_START_INT_CLR_S)
-#define UHCI_RX_START_INT_CLR_V  0x00000001U
-#define UHCI_RX_START_INT_CLR_S  0
-/** UHCI_TX_START_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
- */
-#define UHCI_TX_START_INT_CLR    (BIT(1))
-#define UHCI_TX_START_INT_CLR_M  (UHCI_TX_START_INT_CLR_V << UHCI_TX_START_INT_CLR_S)
-#define UHCI_TX_START_INT_CLR_V  0x00000001U
-#define UHCI_TX_START_INT_CLR_S  1
-/** UHCI_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
- */
-#define UHCI_RX_HUNG_INT_CLR    (BIT(2))
-#define UHCI_RX_HUNG_INT_CLR_M  (UHCI_RX_HUNG_INT_CLR_V << UHCI_RX_HUNG_INT_CLR_S)
-#define UHCI_RX_HUNG_INT_CLR_V  0x00000001U
-#define UHCI_RX_HUNG_INT_CLR_S  2
-/** UHCI_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
- */
-#define UHCI_TX_HUNG_INT_CLR    (BIT(3))
-#define UHCI_TX_HUNG_INT_CLR_M  (UHCI_TX_HUNG_INT_CLR_V << UHCI_TX_HUNG_INT_CLR_S)
-#define UHCI_TX_HUNG_INT_CLR_V  0x00000001U
-#define UHCI_TX_HUNG_INT_CLR_S  3
-/** UHCI_SEND_S_REG_Q_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
- */
-#define UHCI_SEND_S_REG_Q_INT_CLR    (BIT(4))
-#define UHCI_SEND_S_REG_Q_INT_CLR_M  (UHCI_SEND_S_REG_Q_INT_CLR_V << UHCI_SEND_S_REG_Q_INT_CLR_S)
-#define UHCI_SEND_S_REG_Q_INT_CLR_V  0x00000001U
-#define UHCI_SEND_S_REG_Q_INT_CLR_S  4
-/** UHCI_SEND_A_REG_Q_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
- */
-#define UHCI_SEND_A_REG_Q_INT_CLR    (BIT(5))
-#define UHCI_SEND_A_REG_Q_INT_CLR_M  (UHCI_SEND_A_REG_Q_INT_CLR_V << UHCI_SEND_A_REG_Q_INT_CLR_S)
-#define UHCI_SEND_A_REG_Q_INT_CLR_V  0x00000001U
-#define UHCI_SEND_A_REG_Q_INT_CLR_S  5
-/** UHCI_OUTLINK_EOF_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
- */
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR    (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (UHCI_OUTLINK_EOF_ERR_INT_CLR_V << UHCI_OUTLINK_EOF_ERR_INT_CLR_S)
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x00000001U
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
-/** UHCI_APP_CTRL0_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
- */
-#define UHCI_APP_CTRL0_INT_CLR    (BIT(7))
-#define UHCI_APP_CTRL0_INT_CLR_M  (UHCI_APP_CTRL0_INT_CLR_V << UHCI_APP_CTRL0_INT_CLR_S)
-#define UHCI_APP_CTRL0_INT_CLR_V  0x00000001U
-#define UHCI_APP_CTRL0_INT_CLR_S  7
-/** UHCI_APP_CTRL1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
- */
-#define UHCI_APP_CTRL1_INT_CLR    (BIT(8))
-#define UHCI_APP_CTRL1_INT_CLR_M  (UHCI_APP_CTRL1_INT_CLR_V << UHCI_APP_CTRL1_INT_CLR_S)
-#define UHCI_APP_CTRL1_INT_CLR_V  0x00000001U
-#define UHCI_APP_CTRL1_INT_CLR_S  8
-
-/** UHCI_CONF1_REG register
- *  UHCI Configuration Register1
- */
-#define UHCI_CONF1_REG (DR_REG_UHCI_BASE + 0x14)
-/** UHCI_CHECK_SUM_EN : R/W; bitpos: [0]; default: 1;
- *  Set this bit to enable head checksum check when receiving.
- */
-#define UHCI_CHECK_SUM_EN    (BIT(0))
-#define UHCI_CHECK_SUM_EN_M  (UHCI_CHECK_SUM_EN_V << UHCI_CHECK_SUM_EN_S)
-#define UHCI_CHECK_SUM_EN_V  0x00000001U
-#define UHCI_CHECK_SUM_EN_S  0
-/** UHCI_CHECK_SEQ_EN : R/W; bitpos: [1]; default: 1;
- *  Set this bit to  enable sequence number check when receiving.
- */
-#define UHCI_CHECK_SEQ_EN    (BIT(1))
-#define UHCI_CHECK_SEQ_EN_M  (UHCI_CHECK_SEQ_EN_V << UHCI_CHECK_SEQ_EN_S)
-#define UHCI_CHECK_SEQ_EN_V  0x00000001U
-#define UHCI_CHECK_SEQ_EN_S  1
-/** UHCI_CRC_DISABLE : R/W; bitpos: [2]; default: 0;
- *  Set this bit to support CRC calculation, and data integrity check bit should 1.
- */
-#define UHCI_CRC_DISABLE    (BIT(2))
-#define UHCI_CRC_DISABLE_M  (UHCI_CRC_DISABLE_V << UHCI_CRC_DISABLE_S)
-#define UHCI_CRC_DISABLE_V  0x00000001U
-#define UHCI_CRC_DISABLE_S  2
-/** UHCI_SAVE_HEAD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to save data packet head when UHCI receive data.
- */
-#define UHCI_SAVE_HEAD    (BIT(3))
-#define UHCI_SAVE_HEAD_M  (UHCI_SAVE_HEAD_V << UHCI_SAVE_HEAD_S)
-#define UHCI_SAVE_HEAD_V  0x00000001U
-#define UHCI_SAVE_HEAD_S  3
-/** UHCI_TX_CHECK_SUM_RE : R/W; bitpos: [4]; default: 1;
- *  Set this bit to encode data packet with checksum.
- */
-#define UHCI_TX_CHECK_SUM_RE    (BIT(4))
-#define UHCI_TX_CHECK_SUM_RE_M  (UHCI_TX_CHECK_SUM_RE_V << UHCI_TX_CHECK_SUM_RE_S)
-#define UHCI_TX_CHECK_SUM_RE_V  0x00000001U
-#define UHCI_TX_CHECK_SUM_RE_S  4
-/** UHCI_TX_ACK_NUM_RE : R/W; bitpos: [5]; default: 1;
- *  Set this bit to encode data packet with ACK when reliable data packet is ready.
- */
-#define UHCI_TX_ACK_NUM_RE    (BIT(5))
-#define UHCI_TX_ACK_NUM_RE_M  (UHCI_TX_ACK_NUM_RE_V << UHCI_TX_ACK_NUM_RE_S)
-#define UHCI_TX_ACK_NUM_RE_V  0x00000001U
-#define UHCI_TX_ACK_NUM_RE_S  5
-/** UHCI_WAIT_SW_START : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
- */
-#define UHCI_WAIT_SW_START    (BIT(7))
-#define UHCI_WAIT_SW_START_M  (UHCI_WAIT_SW_START_V << UHCI_WAIT_SW_START_S)
-#define UHCI_WAIT_SW_START_V  0x00000001U
-#define UHCI_WAIT_SW_START_S  7
-/** UHCI_SW_START : WT; bitpos: [8]; default: 0;
- *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
- */
-#define UHCI_SW_START    (BIT(8))
-#define UHCI_SW_START_M  (UHCI_SW_START_V << UHCI_SW_START_S)
-#define UHCI_SW_START_V  0x00000001U
-#define UHCI_SW_START_S  8
-
-/** UHCI_STATE0_REG register
- *  UHCI Receive Status Register
- */
-#define UHCI_STATE0_REG (DR_REG_UHCI_BASE + 0x18)
-/** UHCI_RX_ERR_CAUSE : RO; bitpos: [2:0]; default: 0;
- *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
- *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
- *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
- *  not found, but received packet is completed. 3'b110: CRC check error.
- */
-#define UHCI_RX_ERR_CAUSE    0x00000007U
-#define UHCI_RX_ERR_CAUSE_M  (UHCI_RX_ERR_CAUSE_V << UHCI_RX_ERR_CAUSE_S)
-#define UHCI_RX_ERR_CAUSE_V  0x00000007U
-#define UHCI_RX_ERR_CAUSE_S  0
-/** UHCI_DECODE_STATE : RO; bitpos: [5:3]; default: 0;
- *  Indicates UHCI decoder status.
- */
-#define UHCI_DECODE_STATE    0x00000007U
-#define UHCI_DECODE_STATE_M  (UHCI_DECODE_STATE_V << UHCI_DECODE_STATE_S)
-#define UHCI_DECODE_STATE_V  0x00000007U
-#define UHCI_DECODE_STATE_S  3
-
-/** UHCI_STATE1_REG register
- *  UHCI Transmit Status Register
- */
-#define UHCI_STATE1_REG (DR_REG_UHCI_BASE + 0x1c)
-/** UHCI_ENCODE_STATE : RO; bitpos: [2:0]; default: 0;
- *  Indicates UHCI encoder status.
- */
-#define UHCI_ENCODE_STATE    0x00000007U
-#define UHCI_ENCODE_STATE_M  (UHCI_ENCODE_STATE_V << UHCI_ENCODE_STATE_S)
-#define UHCI_ENCODE_STATE_V  0x00000007U
-#define UHCI_ENCODE_STATE_S  0
-
-/** UHCI_ESCAPE_CONF_REG register
- *  UHCI Escapes Configuration Register0
- */
-#define UHCI_ESCAPE_CONF_REG (DR_REG_UHCI_BASE + 0x20)
-/** UHCI_TX_C0_ESC_EN : R/W; bitpos: [0]; default: 1;
- *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
- */
-#define UHCI_TX_C0_ESC_EN    (BIT(0))
-#define UHCI_TX_C0_ESC_EN_M  (UHCI_TX_C0_ESC_EN_V << UHCI_TX_C0_ESC_EN_S)
-#define UHCI_TX_C0_ESC_EN_V  0x00000001U
-#define UHCI_TX_C0_ESC_EN_S  0
-/** UHCI_TX_DB_ESC_EN : R/W; bitpos: [1]; default: 1;
- *  Set this bit to enable resolve char 0xDB when DMA receiving data.
- */
-#define UHCI_TX_DB_ESC_EN    (BIT(1))
-#define UHCI_TX_DB_ESC_EN_M  (UHCI_TX_DB_ESC_EN_V << UHCI_TX_DB_ESC_EN_S)
-#define UHCI_TX_DB_ESC_EN_V  0x00000001U
-#define UHCI_TX_DB_ESC_EN_S  1
-/** UHCI_TX_11_ESC_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
- */
-#define UHCI_TX_11_ESC_EN    (BIT(2))
-#define UHCI_TX_11_ESC_EN_M  (UHCI_TX_11_ESC_EN_V << UHCI_TX_11_ESC_EN_S)
-#define UHCI_TX_11_ESC_EN_V  0x00000001U
-#define UHCI_TX_11_ESC_EN_S  2
-/** UHCI_TX_13_ESC_EN : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
- */
-#define UHCI_TX_13_ESC_EN    (BIT(3))
-#define UHCI_TX_13_ESC_EN_M  (UHCI_TX_13_ESC_EN_V << UHCI_TX_13_ESC_EN_S)
-#define UHCI_TX_13_ESC_EN_V  0x00000001U
-#define UHCI_TX_13_ESC_EN_S  3
-/** UHCI_RX_C0_ESC_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
- */
-#define UHCI_RX_C0_ESC_EN    (BIT(4))
-#define UHCI_RX_C0_ESC_EN_M  (UHCI_RX_C0_ESC_EN_V << UHCI_RX_C0_ESC_EN_S)
-#define UHCI_RX_C0_ESC_EN_V  0x00000001U
-#define UHCI_RX_C0_ESC_EN_S  4
-/** UHCI_RX_DB_ESC_EN : R/W; bitpos: [5]; default: 1;
- *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
- */
-#define UHCI_RX_DB_ESC_EN    (BIT(5))
-#define UHCI_RX_DB_ESC_EN_M  (UHCI_RX_DB_ESC_EN_V << UHCI_RX_DB_ESC_EN_S)
-#define UHCI_RX_DB_ESC_EN_V  0x00000001U
-#define UHCI_RX_DB_ESC_EN_S  5
-/** UHCI_RX_11_ESC_EN : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
- */
-#define UHCI_RX_11_ESC_EN    (BIT(6))
-#define UHCI_RX_11_ESC_EN_M  (UHCI_RX_11_ESC_EN_V << UHCI_RX_11_ESC_EN_S)
-#define UHCI_RX_11_ESC_EN_V  0x00000001U
-#define UHCI_RX_11_ESC_EN_S  6
-/** UHCI_RX_13_ESC_EN : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
- */
-#define UHCI_RX_13_ESC_EN    (BIT(7))
-#define UHCI_RX_13_ESC_EN_M  (UHCI_RX_13_ESC_EN_V << UHCI_RX_13_ESC_EN_S)
-#define UHCI_RX_13_ESC_EN_V  0x00000001U
-#define UHCI_RX_13_ESC_EN_S  7
-
-/** UHCI_HUNG_CONF_REG register
- *  UHCI Hung Configuration Register0
- */
-#define UHCI_HUNG_CONF_REG (DR_REG_UHCI_BASE + 0x24)
-/** UHCI_TXFIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
- *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
- *  data.
- */
-#define UHCI_TXFIFO_TIMEOUT    0x000000FFU
-#define UHCI_TXFIFO_TIMEOUT_M  (UHCI_TXFIFO_TIMEOUT_V << UHCI_TXFIFO_TIMEOUT_S)
-#define UHCI_TXFIFO_TIMEOUT_V  0x000000FFU
-#define UHCI_TXFIFO_TIMEOUT_S  0
-/** UHCI_TXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
- *  Configures the maximum counter value.
- */
-#define UHCI_TXFIFO_TIMEOUT_SHIFT    0x00000007U
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  (UHCI_TXFIFO_TIMEOUT_SHIFT_V << UHCI_TXFIFO_TIMEOUT_SHIFT_S)
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x00000007U
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
-/** UHCI_TXFIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
- *  Set this bit to enable TX FIFO timeout when receiving.
- */
-#define UHCI_TXFIFO_TIMEOUT_ENA    (BIT(11))
-#define UHCI_TXFIFO_TIMEOUT_ENA_M  (UHCI_TXFIFO_TIMEOUT_ENA_V << UHCI_TXFIFO_TIMEOUT_ENA_S)
-#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x00000001U
-#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
-/** UHCI_RXFIFO_TIMEOUT : R/W; bitpos: [19:12]; default: 16;
- *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
- *  RAM data.
- */
-#define UHCI_RXFIFO_TIMEOUT    0x000000FFU
-#define UHCI_RXFIFO_TIMEOUT_M  (UHCI_RXFIFO_TIMEOUT_V << UHCI_RXFIFO_TIMEOUT_S)
-#define UHCI_RXFIFO_TIMEOUT_V  0x000000FFU
-#define UHCI_RXFIFO_TIMEOUT_S  12
-/** UHCI_RXFIFO_TIMEOUT_SHIFT : R/W; bitpos: [22:20]; default: 0;
- *  Configures the maximum counter value.
- */
-#define UHCI_RXFIFO_TIMEOUT_SHIFT    0x00000007U
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  (UHCI_RXFIFO_TIMEOUT_SHIFT_V << UHCI_RXFIFO_TIMEOUT_SHIFT_S)
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x00000007U
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
-/** UHCI_RXFIFO_TIMEOUT_ENA : R/W; bitpos: [23]; default: 1;
- *  Set this bit to enable TX FIFO timeout when DMA sending data.
- */
-#define UHCI_RXFIFO_TIMEOUT_ENA    (BIT(23))
-#define UHCI_RXFIFO_TIMEOUT_ENA_M  (UHCI_RXFIFO_TIMEOUT_ENA_V << UHCI_RXFIFO_TIMEOUT_ENA_S)
-#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x00000001U
-#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
-
-/** UHCI_ACK_NUM_REG register
- *  UHCI Ack Value Configuration Register0
- */
-#define UHCI_ACK_NUM_REG (DR_REG_UHCI_BASE + 0x28)
-/** UHCI_ACK_NUM : R/W; bitpos: [2:0]; default: 0;
- *  Indicates the ACK number during software flow control.
- */
-#define UHCI_ACK_NUM    0x00000007U
-#define UHCI_ACK_NUM_M  (UHCI_ACK_NUM_V << UHCI_ACK_NUM_S)
-#define UHCI_ACK_NUM_V  0x00000007U
-#define UHCI_ACK_NUM_S  0
-/** UHCI_ACK_NUM_LOAD : WT; bitpos: [3]; default: 0;
- *  Set this bit to load the ACK value of UHCI_ACK_NUM.
- */
-#define UHCI_ACK_NUM_LOAD    (BIT(3))
-#define UHCI_ACK_NUM_LOAD_M  (UHCI_ACK_NUM_LOAD_V << UHCI_ACK_NUM_LOAD_S)
-#define UHCI_ACK_NUM_LOAD_V  0x00000001U
-#define UHCI_ACK_NUM_LOAD_S  3
-
-/** UHCI_RX_HEAD_REG register
- *  UHCI Head Register
- */
-#define UHCI_RX_HEAD_REG (DR_REG_UHCI_BASE + 0x2c)
-/** UHCI_RX_HEAD : RO; bitpos: [31:0]; default: 0;
- *  Stores the head of received packet.
- */
-#define UHCI_RX_HEAD    0xFFFFFFFFU
-#define UHCI_RX_HEAD_M  (UHCI_RX_HEAD_V << UHCI_RX_HEAD_S)
-#define UHCI_RX_HEAD_V  0xFFFFFFFFU
-#define UHCI_RX_HEAD_S  0
-
-/** UHCI_QUICK_SENT_REG register
- *  UCHI Quick send Register
- */
-#define UHCI_QUICK_SENT_REG (DR_REG_UHCI_BASE + 0x30)
-/** UHCI_SINGLE_SEND_NUM : R/W; bitpos: [2:0]; default: 0;
- *  Configures single_send mode.
- */
-#define UHCI_SINGLE_SEND_NUM    0x00000007U
-#define UHCI_SINGLE_SEND_NUM_M  (UHCI_SINGLE_SEND_NUM_V << UHCI_SINGLE_SEND_NUM_S)
-#define UHCI_SINGLE_SEND_NUM_V  0x00000007U
-#define UHCI_SINGLE_SEND_NUM_S  0
-/** UHCI_SINGLE_SEND_EN : WT; bitpos: [3]; default: 0;
- *  Set this bit to enable sending short packet with single_send mode.
- */
-#define UHCI_SINGLE_SEND_EN    (BIT(3))
-#define UHCI_SINGLE_SEND_EN_M  (UHCI_SINGLE_SEND_EN_V << UHCI_SINGLE_SEND_EN_S)
-#define UHCI_SINGLE_SEND_EN_V  0x00000001U
-#define UHCI_SINGLE_SEND_EN_S  3
-/** UHCI_ALWAYS_SEND_NUM : R/W; bitpos: [6:4]; default: 0;
- *  Configures always_send mode.
- */
-#define UHCI_ALWAYS_SEND_NUM    0x00000007U
-#define UHCI_ALWAYS_SEND_NUM_M  (UHCI_ALWAYS_SEND_NUM_V << UHCI_ALWAYS_SEND_NUM_S)
-#define UHCI_ALWAYS_SEND_NUM_V  0x00000007U
-#define UHCI_ALWAYS_SEND_NUM_S  4
-/** UHCI_ALWAYS_SEND_EN : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable sending short packet with always_send mode.
- */
-#define UHCI_ALWAYS_SEND_EN    (BIT(7))
-#define UHCI_ALWAYS_SEND_EN_M  (UHCI_ALWAYS_SEND_EN_V << UHCI_ALWAYS_SEND_EN_S)
-#define UHCI_ALWAYS_SEND_EN_V  0x00000001U
-#define UHCI_ALWAYS_SEND_EN_S  7
-
-/** UHCI_REG_Q0_WORD0_REG register
- *  UHCI Q0_WORD0 Quick Send Register
- */
-#define UHCI_REG_Q0_WORD0_REG (DR_REG_UHCI_BASE + 0x34)
-/** UHCI_SEND_Q0_WORD0 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q0_WORD0    0xFFFFFFFFU
-#define UHCI_SEND_Q0_WORD0_M  (UHCI_SEND_Q0_WORD0_V << UHCI_SEND_Q0_WORD0_S)
-#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFFU
-#define UHCI_SEND_Q0_WORD0_S  0
-
-/** UHCI_REG_Q0_WORD1_REG register
- *  UHCI Q0_WORD1 Quick Send Register
- */
-#define UHCI_REG_Q0_WORD1_REG (DR_REG_UHCI_BASE + 0x38)
-/** UHCI_SEND_Q0_WORD1 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q0_WORD1    0xFFFFFFFFU
-#define UHCI_SEND_Q0_WORD1_M  (UHCI_SEND_Q0_WORD1_V << UHCI_SEND_Q0_WORD1_S)
-#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFFU
-#define UHCI_SEND_Q0_WORD1_S  0
-
-/** UHCI_REG_Q1_WORD0_REG register
- *  UHCI Q1_WORD0 Quick Send Register
- */
-#define UHCI_REG_Q1_WORD0_REG (DR_REG_UHCI_BASE + 0x3c)
-/** UHCI_SEND_Q1_WORD0 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q1_WORD0    0xFFFFFFFFU
-#define UHCI_SEND_Q1_WORD0_M  (UHCI_SEND_Q1_WORD0_V << UHCI_SEND_Q1_WORD0_S)
-#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFFU
-#define UHCI_SEND_Q1_WORD0_S  0
-
-/** UHCI_REG_Q1_WORD1_REG register
- *  UHCI Q1_WORD1 Quick Send Register
- */
-#define UHCI_REG_Q1_WORD1_REG (DR_REG_UHCI_BASE + 0x40)
-/** UHCI_SEND_Q1_WORD1 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q1_WORD1    0xFFFFFFFFU
-#define UHCI_SEND_Q1_WORD1_M  (UHCI_SEND_Q1_WORD1_V << UHCI_SEND_Q1_WORD1_S)
-#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFFU
-#define UHCI_SEND_Q1_WORD1_S  0
-
-/** UHCI_REG_Q2_WORD0_REG register
- *  UHCI Q2_WORD0 Quick Send Register
- */
-#define UHCI_REG_Q2_WORD0_REG (DR_REG_UHCI_BASE + 0x44)
-/** UHCI_SEND_Q2_WORD0 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q2_WORD0    0xFFFFFFFFU
-#define UHCI_SEND_Q2_WORD0_M  (UHCI_SEND_Q2_WORD0_V << UHCI_SEND_Q2_WORD0_S)
-#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFFU
-#define UHCI_SEND_Q2_WORD0_S  0
-
-/** UHCI_REG_Q2_WORD1_REG register
- *  UHCI Q2_WORD1 Quick Send Register
- */
-#define UHCI_REG_Q2_WORD1_REG (DR_REG_UHCI_BASE + 0x48)
-/** UHCI_SEND_Q2_WORD1 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q2_WORD1    0xFFFFFFFFU
-#define UHCI_SEND_Q2_WORD1_M  (UHCI_SEND_Q2_WORD1_V << UHCI_SEND_Q2_WORD1_S)
-#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFFU
-#define UHCI_SEND_Q2_WORD1_S  0
-
-/** UHCI_REG_Q3_WORD0_REG register
- *  UHCI Q3_WORD0 Quick Send Register
- */
-#define UHCI_REG_Q3_WORD0_REG (DR_REG_UHCI_BASE + 0x4c)
-/** UHCI_SEND_Q3_WORD0 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q3_WORD0    0xFFFFFFFFU
-#define UHCI_SEND_Q3_WORD0_M  (UHCI_SEND_Q3_WORD0_V << UHCI_SEND_Q3_WORD0_S)
-#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFFU
-#define UHCI_SEND_Q3_WORD0_S  0
-
-/** UHCI_REG_Q3_WORD1_REG register
- *  UHCI Q3_WORD1 Quick Send Register
- */
-#define UHCI_REG_Q3_WORD1_REG (DR_REG_UHCI_BASE + 0x50)
-/** UHCI_SEND_Q3_WORD1 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q3_WORD1    0xFFFFFFFFU
-#define UHCI_SEND_Q3_WORD1_M  (UHCI_SEND_Q3_WORD1_V << UHCI_SEND_Q3_WORD1_S)
-#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFFU
-#define UHCI_SEND_Q3_WORD1_S  0
-
-/** UHCI_REG_Q4_WORD0_REG register
- *  UHCI Q4_WORD0 Quick Send Register
- */
-#define UHCI_REG_Q4_WORD0_REG (DR_REG_UHCI_BASE + 0x54)
-/** UHCI_SEND_Q4_WORD0 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q4_WORD0    0xFFFFFFFFU
-#define UHCI_SEND_Q4_WORD0_M  (UHCI_SEND_Q4_WORD0_V << UHCI_SEND_Q4_WORD0_S)
-#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFFU
-#define UHCI_SEND_Q4_WORD0_S  0
-
-/** UHCI_REG_Q4_WORD1_REG register
- *  UHCI Q4_WORD1 Quick Send Register
- */
-#define UHCI_REG_Q4_WORD1_REG (DR_REG_UHCI_BASE + 0x58)
-/** UHCI_SEND_Q4_WORD1 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q4_WORD1    0xFFFFFFFFU
-#define UHCI_SEND_Q4_WORD1_M  (UHCI_SEND_Q4_WORD1_V << UHCI_SEND_Q4_WORD1_S)
-#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFFU
-#define UHCI_SEND_Q4_WORD1_S  0
-
-/** UHCI_REG_Q5_WORD0_REG register
- *  UHCI Q5_WORD0 Quick Send Register
- */
-#define UHCI_REG_Q5_WORD0_REG (DR_REG_UHCI_BASE + 0x5c)
-/** UHCI_SEND_Q5_WORD0 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q5_WORD0    0xFFFFFFFFU
-#define UHCI_SEND_Q5_WORD0_M  (UHCI_SEND_Q5_WORD0_V << UHCI_SEND_Q5_WORD0_S)
-#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFFU
-#define UHCI_SEND_Q5_WORD0_S  0
-
-/** UHCI_REG_Q5_WORD1_REG register
- *  UHCI Q5_WORD1 Quick Send Register
- */
-#define UHCI_REG_Q5_WORD1_REG (DR_REG_UHCI_BASE + 0x60)
-/** UHCI_SEND_Q5_WORD1 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q5_WORD1    0xFFFFFFFFU
-#define UHCI_SEND_Q5_WORD1_M  (UHCI_SEND_Q5_WORD1_V << UHCI_SEND_Q5_WORD1_S)
-#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFFU
-#define UHCI_SEND_Q5_WORD1_S  0
-
-/** UHCI_REG_Q6_WORD0_REG register
- *  UHCI Q6_WORD0 Quick Send Register
- */
-#define UHCI_REG_Q6_WORD0_REG (DR_REG_UHCI_BASE + 0x64)
-/** UHCI_SEND_Q6_WORD0 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q6_WORD0    0xFFFFFFFFU
-#define UHCI_SEND_Q6_WORD0_M  (UHCI_SEND_Q6_WORD0_V << UHCI_SEND_Q6_WORD0_S)
-#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFFU
-#define UHCI_SEND_Q6_WORD0_S  0
-
-/** UHCI_REG_Q6_WORD1_REG register
- *  UHCI Q6_WORD1 Quick Send Register
- */
-#define UHCI_REG_Q6_WORD1_REG (DR_REG_UHCI_BASE + 0x68)
-/** UHCI_SEND_Q6_WORD1 : R/W; bitpos: [31:0]; default: 0;
- *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
- *  UHCI_SINGLE_SEND_NUM.
- */
-#define UHCI_SEND_Q6_WORD1    0xFFFFFFFFU
-#define UHCI_SEND_Q6_WORD1_M  (UHCI_SEND_Q6_WORD1_V << UHCI_SEND_Q6_WORD1_S)
-#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFFU
-#define UHCI_SEND_Q6_WORD1_S  0
-
-/** UHCI_ESC_CONF0_REG register
- *  UHCI Escapes Sequence Configuration Register0
- */
-#define UHCI_ESC_CONF0_REG (DR_REG_UHCI_BASE + 0x6c)
-/** UHCI_SEPER_CHAR : R/W; bitpos: [7:0]; default: 192;
- *  Configures the delimiter for encoding, default value is 0xC0.
- */
-#define UHCI_SEPER_CHAR    0x000000FFU
-#define UHCI_SEPER_CHAR_M  (UHCI_SEPER_CHAR_V << UHCI_SEPER_CHAR_S)
-#define UHCI_SEPER_CHAR_V  0x000000FFU
-#define UHCI_SEPER_CHAR_S  0
-/** UHCI_SEPER_ESC_CHAR0 : R/W; bitpos: [15:8]; default: 219;
- *  Configures the first char of SLIP escape character, default value is 0xDB.
- */
-#define UHCI_SEPER_ESC_CHAR0    0x000000FFU
-#define UHCI_SEPER_ESC_CHAR0_M  (UHCI_SEPER_ESC_CHAR0_V << UHCI_SEPER_ESC_CHAR0_S)
-#define UHCI_SEPER_ESC_CHAR0_V  0x000000FFU
-#define UHCI_SEPER_ESC_CHAR0_S  8
-/** UHCI_SEPER_ESC_CHAR1 : R/W; bitpos: [23:16]; default: 220;
- *  Configures the second char of SLIP escape character, default value is 0xDC.
- */
-#define UHCI_SEPER_ESC_CHAR1    0x000000FFU
-#define UHCI_SEPER_ESC_CHAR1_M  (UHCI_SEPER_ESC_CHAR1_V << UHCI_SEPER_ESC_CHAR1_S)
-#define UHCI_SEPER_ESC_CHAR1_V  0x000000FFU
-#define UHCI_SEPER_ESC_CHAR1_S  16
-
-/** UHCI_ESC_CONF1_REG register
- *  UHCI Escapes Sequence Configuration Register1
- */
-#define UHCI_ESC_CONF1_REG (DR_REG_UHCI_BASE + 0x70)
-/** UHCI_ESC_SEQ0 : R/W; bitpos: [7:0]; default: 219;
- *  Configures the char needing encoding, which is 0xDB as flow control char by default.
- */
-#define UHCI_ESC_SEQ0    0x000000FFU
-#define UHCI_ESC_SEQ0_M  (UHCI_ESC_SEQ0_V << UHCI_ESC_SEQ0_S)
-#define UHCI_ESC_SEQ0_V  0x000000FFU
-#define UHCI_ESC_SEQ0_S  0
-/** UHCI_ESC_SEQ0_CHAR0 : R/W; bitpos: [15:8]; default: 219;
- *  Configures the first char of SLIP escape character, default value is 0xDB.
- */
-#define UHCI_ESC_SEQ0_CHAR0    0x000000FFU
-#define UHCI_ESC_SEQ0_CHAR0_M  (UHCI_ESC_SEQ0_CHAR0_V << UHCI_ESC_SEQ0_CHAR0_S)
-#define UHCI_ESC_SEQ0_CHAR0_V  0x000000FFU
-#define UHCI_ESC_SEQ0_CHAR0_S  8
-/** UHCI_ESC_SEQ0_CHAR1 : R/W; bitpos: [23:16]; default: 221;
- *  Configures the second char of SLIP escape character, default value is 0xDD.
- */
-#define UHCI_ESC_SEQ0_CHAR1    0x000000FFU
-#define UHCI_ESC_SEQ0_CHAR1_M  (UHCI_ESC_SEQ0_CHAR1_V << UHCI_ESC_SEQ0_CHAR1_S)
-#define UHCI_ESC_SEQ0_CHAR1_V  0x000000FFU
-#define UHCI_ESC_SEQ0_CHAR1_S  16
-
-/** UHCI_ESC_CONF2_REG register
- *  UHCI Escapes Sequence Configuration Register2
- */
-#define UHCI_ESC_CONF2_REG (DR_REG_UHCI_BASE + 0x74)
-/** UHCI_ESC_SEQ1 : R/W; bitpos: [7:0]; default: 17;
- *  Configures the char needing encoding, which is 0x11 as flow control char by default.
- */
-#define UHCI_ESC_SEQ1    0x000000FFU
-#define UHCI_ESC_SEQ1_M  (UHCI_ESC_SEQ1_V << UHCI_ESC_SEQ1_S)
-#define UHCI_ESC_SEQ1_V  0x000000FFU
-#define UHCI_ESC_SEQ1_S  0
-/** UHCI_ESC_SEQ1_CHAR0 : R/W; bitpos: [15:8]; default: 219;
- *  Configures the first char of SLIP escape character, default value is 0xDB.
- */
-#define UHCI_ESC_SEQ1_CHAR0    0x000000FFU
-#define UHCI_ESC_SEQ1_CHAR0_M  (UHCI_ESC_SEQ1_CHAR0_V << UHCI_ESC_SEQ1_CHAR0_S)
-#define UHCI_ESC_SEQ1_CHAR0_V  0x000000FFU
-#define UHCI_ESC_SEQ1_CHAR0_S  8
-/** UHCI_ESC_SEQ1_CHAR1 : R/W; bitpos: [23:16]; default: 222;
- *  Configures the second char of SLIP escape character, default value is 0xDE.
- */
-#define UHCI_ESC_SEQ1_CHAR1    0x000000FFU
-#define UHCI_ESC_SEQ1_CHAR1_M  (UHCI_ESC_SEQ1_CHAR1_V << UHCI_ESC_SEQ1_CHAR1_S)
-#define UHCI_ESC_SEQ1_CHAR1_V  0x000000FFU
-#define UHCI_ESC_SEQ1_CHAR1_S  16
-
-/** UHCI_ESC_CONF3_REG register
- *  UHCI Escapes Sequence Configuration Register3
- */
-#define UHCI_ESC_CONF3_REG (DR_REG_UHCI_BASE + 0x78)
-/** UHCI_ESC_SEQ2 : R/W; bitpos: [7:0]; default: 19;
- *  Configures the char needing encoding, which is 0x13 as flow control char by default.
- */
-#define UHCI_ESC_SEQ2    0x000000FFU
-#define UHCI_ESC_SEQ2_M  (UHCI_ESC_SEQ2_V << UHCI_ESC_SEQ2_S)
-#define UHCI_ESC_SEQ2_V  0x000000FFU
-#define UHCI_ESC_SEQ2_S  0
-/** UHCI_ESC_SEQ2_CHAR0 : R/W; bitpos: [15:8]; default: 219;
- *  Configures the first char of SLIP escape character, default value is 0xDB.
- */
-#define UHCI_ESC_SEQ2_CHAR0    0x000000FFU
-#define UHCI_ESC_SEQ2_CHAR0_M  (UHCI_ESC_SEQ2_CHAR0_V << UHCI_ESC_SEQ2_CHAR0_S)
-#define UHCI_ESC_SEQ2_CHAR0_V  0x000000FFU
-#define UHCI_ESC_SEQ2_CHAR0_S  8
-/** UHCI_ESC_SEQ2_CHAR1 : R/W; bitpos: [23:16]; default: 223;
- *  Configures the second char of SLIP escape character, default value is 0xDF.
- */
-#define UHCI_ESC_SEQ2_CHAR1    0x000000FFU
-#define UHCI_ESC_SEQ2_CHAR1_M  (UHCI_ESC_SEQ2_CHAR1_V << UHCI_ESC_SEQ2_CHAR1_S)
-#define UHCI_ESC_SEQ2_CHAR1_V  0x000000FFU
-#define UHCI_ESC_SEQ2_CHAR1_S  16
-
-/** UHCI_PKT_THRES_REG register
- *  UCHI Packet Length Configuration Register
- */
-#define UHCI_PKT_THRES_REG (DR_REG_UHCI_BASE + 0x7c)
-/** UHCI_PKT_THRS : R/W; bitpos: [12:0]; default: 128;
- *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
- */
-#define UHCI_PKT_THRS    0x00001FFFU
-#define UHCI_PKT_THRS_M  (UHCI_PKT_THRS_V << UHCI_PKT_THRS_S)
-#define UHCI_PKT_THRS_V  0x00001FFFU
-#define UHCI_PKT_THRS_S  0
-
-/** UHCI_DATE_REG register
- *  UHCI Version Register
- */
-#define UHCI_DATE_REG (DR_REG_UHCI_BASE + 0x80)
-/** UHCI_DATE : R/W; bitpos: [31:0]; default: 35655936;
- *  Configures version.
- */
-#define UHCI_DATE    0xFFFFFFFFU
-#define UHCI_DATE_M  (UHCI_DATE_V << UHCI_DATE_S)
-#define UHCI_DATE_V  0xFFFFFFFFU
-#define UHCI_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/uhci_struct.h b/components/soc/esp32c5/beta3/include/soc/uhci_struct.h
deleted file mode 100644
index 1d0fa4129f..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/uhci_struct.h
+++ /dev/null
@@ -1,666 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of conf0 register
- *  UHCI Configuration Register0
- */
-typedef union {
-    struct {
-        /** tx_rst : R/W; bitpos: [0]; default: 0;
-         *  Write 1 then write 0 to this bit to reset decode state machine.
-         */
-        uint32_t tx_rst:1;
-        /** rx_rst : R/W; bitpos: [1]; default: 0;
-         *  Write 1 then write 0 to this bit to reset encode state machine.
-         */
-        uint32_t rx_rst:1;
-        /** uart_sel : R/W; bitpos: [4:2]; default: 7;
-         *  Select which uart to connect with GDMA.
-         */
-        uint32_t uart_sel:3;
-        /** seper_en : R/W; bitpos: [5]; default: 1;
-         *  Set this bit to separate the data frame using a special char.
-         */
-        uint32_t seper_en:1;
-        /** head_en : R/W; bitpos: [6]; default: 1;
-         *  Set this bit to encode the data packet with a formatting header.
-         */
-        uint32_t head_en:1;
-        /** crc_rec_en : R/W; bitpos: [7]; default: 1;
-         *  Set this bit to enable UHCI to receive the 16 bit CRC.
-         */
-        uint32_t crc_rec_en:1;
-        /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0;
-         *  If this bit is set to 1 UHCI will end the payload receiving process when UART has
-         *  been in idle state.
-         */
-        uint32_t uart_idle_eof_en:1;
-        /** len_eof_en : R/W; bitpos: [9]; default: 1;
-         *  If this bit is set to 1 UHCI decoder receiving payload data is end when the
-         *  receiving byte count has reached the specified value. The value is payload length
-         *  indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
-         *  configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder
-         *  receiving payload data is end when 0xc0 is received.
-         */
-        uint32_t len_eof_en:1;
-        /** encode_crc_en : R/W; bitpos: [10]; default: 1;
-         *  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to
-         *  end of the payload.
-         */
-        uint32_t encode_crc_en:1;
-        /** clk_en : R/W; bitpos: [11]; default: 0;
-         *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0;
-         *  If this bit is set to 1 UHCI will end payload receive process when NULL frame is
-         *  received by UART.
-         */
-        uint32_t uart_rx_brk_eof_en:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} uhci_conf0_reg_t;
-
-/** Type of conf1 register
- *  UHCI Configuration Register1
- */
-typedef union {
-    struct {
-        /** check_sum_en : R/W; bitpos: [0]; default: 1;
-         *  Set this bit to enable head checksum check when receiving.
-         */
-        uint32_t check_sum_en:1;
-        /** check_seq_en : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to  enable sequence number check when receiving.
-         */
-        uint32_t check_seq_en:1;
-        /** crc_disable : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to support CRC calculation, and data integrity check bit should 1.
-         */
-        uint32_t crc_disable:1;
-        /** save_head : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to save data packet head when UHCI receive data.
-         */
-        uint32_t save_head:1;
-        /** tx_check_sum_re : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to encode data packet with checksum.
-         */
-        uint32_t tx_check_sum_re:1;
-        /** tx_ack_num_re : R/W; bitpos: [5]; default: 1;
-         *  Set this bit to encode data packet with ACK when reliable data packet is ready.
-         */
-        uint32_t tx_ack_num_re:1;
-        uint32_t reserved_6:1;
-        /** wait_sw_start : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.
-         */
-        uint32_t wait_sw_start:1;
-        /** sw_start : WT; bitpos: [8]; default: 0;
-         *  Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.
-         */
-        uint32_t sw_start:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uhci_conf1_reg_t;
-
-/** Type of escape_conf register
- *  UHCI Escapes Configuration Register0
- */
-typedef union {
-    struct {
-        /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1;
-         *  Set this bit to enable resolve char 0xC0 when DMA receiving data.
-         */
-        uint32_t tx_c0_esc_en:1;
-        /** tx_db_esc_en : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to enable resolve char 0xDB when DMA receiving data.
-         */
-        uint32_t tx_db_esc_en:1;
-        /** tx_11_esc_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to enable resolve flow control char 0x11 when DMA receiving data.
-         */
-        uint32_t tx_11_esc_en:1;
-        /** tx_13_esc_en : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable resolve flow control char 0x13 when DMA receiving data.
-         */
-        uint32_t tx_13_esc_en:1;
-        /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to enable replacing 0xC0 with special char when DMA receiving data.
-         */
-        uint32_t rx_c0_esc_en:1;
-        /** rx_db_esc_en : R/W; bitpos: [5]; default: 1;
-         *  Set this bit to enable replacing 0xDB with special char when DMA receiving data.
-         */
-        uint32_t rx_db_esc_en:1;
-        /** rx_11_esc_en : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable replacing 0x11 with special char when DMA receiving data.
-         */
-        uint32_t rx_11_esc_en:1;
-        /** rx_13_esc_en : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable replacing 0x13 with special char when DMA receiving data.
-         */
-        uint32_t rx_13_esc_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uhci_escape_conf_reg_t;
-
-/** Type of hung_conf register
- *  UHCI Hung Configuration Register0
- */
-typedef union {
-    struct {
-        /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16;
-         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving
-         *  data.
-         */
-        uint32_t txfifo_timeout:8;
-        /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
-         *  Configures the maximum counter value.
-         */
-        uint32_t txfifo_timeout_shift:3;
-        /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1;
-         *  Set this bit to enable TX FIFO timeout when receiving.
-         */
-        uint32_t txfifo_timeout_ena:1;
-        /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16;
-         *  Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading
-         *  RAM data.
-         */
-        uint32_t rxfifo_timeout:8;
-        /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0;
-         *  Configures the maximum counter value.
-         */
-        uint32_t rxfifo_timeout_shift:3;
-        /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1;
-         *  Set this bit to enable TX FIFO timeout when DMA sending data.
-         */
-        uint32_t rxfifo_timeout_ena:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uhci_hung_conf_reg_t;
-
-/** Type of ack_num register
- *  UHCI Ack Value Configuration Register0
- */
-typedef union {
-    struct {
-        /** ack_num : R/W; bitpos: [2:0]; default: 0;
-         *  Indicates the ACK number during software flow control.
-         */
-        uint32_t ack_num:3;
-        /** ack_num_load : WT; bitpos: [3]; default: 0;
-         *  Set this bit to load the ACK value of UHCI_ACK_NUM.
-         */
-        uint32_t ack_num_load:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} uhci_ack_num_reg_t;
-
-/** Type of quick_sent register
- *  UCHI Quick send Register
- */
-typedef union {
-    struct {
-        /** single_send_num : R/W; bitpos: [2:0]; default: 0;
-         *  Configures single_send mode.
-         */
-        uint32_t single_send_num:3;
-        /** single_send_en : WT; bitpos: [3]; default: 0;
-         *  Set this bit to enable sending short packet with single_send mode.
-         */
-        uint32_t single_send_en:1;
-        /** always_send_num : R/W; bitpos: [6:4]; default: 0;
-         *  Configures always_send mode.
-         */
-        uint32_t always_send_num:3;
-        /** always_send_en : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable sending short packet with always_send mode.
-         */
-        uint32_t always_send_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uhci_quick_sent_reg_t;
-
-/** Type of reg_qn_word0 register
- *  UHCI QN_WORD0 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_word0 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_word0:32;
-    };
-    uint32_t val;
-} uhci_reg_qn_word0_reg_t;
-
-/** Type of reg_qn_word1 register
- *  UHCI QN_WORD1 Quick Send Register
- */
-typedef union {
-    struct {
-        /** send_word1 : R/W; bitpos: [31:0]; default: 0;
-         *  Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or
-         *  UHCI_SINGLE_SEND_NUM.
-         */
-        uint32_t send_word1:32;
-    };
-    uint32_t val;
-} uhci_reg_qn_word1_reg_t;
-
-/** Type of esc_conf0 register
- *  UHCI Escapes Sequence Configuration Register0
- */
-typedef union {
-    struct {
-        /** seper_char : R/W; bitpos: [7:0]; default: 192;
-         *  Configures the delimiter for encoding, default value is 0xC0.
-         */
-        uint32_t seper_char:8;
-        /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219;
-         *  Configures the first char of SLIP escape character, default value is 0xDB.
-         */
-        uint32_t seper_esc_char0:8;
-        /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220;
-         *  Configures the second char of SLIP escape character, default value is 0xDC.
-         */
-        uint32_t seper_esc_char1:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uhci_esc_conf0_reg_t;
-
-/** Type of esc_conf1 register
- *  UHCI Escapes Sequence Configuration Register1
- */
-typedef union {
-    struct {
-        /** esc_seq0 : R/W; bitpos: [7:0]; default: 219;
-         *  Configures the char needing encoding, which is 0xDB as flow control char by default.
-         */
-        uint32_t esc_seq0:8;
-        /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219;
-         *  Configures the first char of SLIP escape character, default value is 0xDB.
-         */
-        uint32_t esc_seq0_char0:8;
-        /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221;
-         *  Configures the second char of SLIP escape character, default value is 0xDD.
-         */
-        uint32_t esc_seq0_char1:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uhci_esc_conf1_reg_t;
-
-/** Type of esc_conf2 register
- *  UHCI Escapes Sequence Configuration Register2
- */
-typedef union {
-    struct {
-        /** esc_seq1 : R/W; bitpos: [7:0]; default: 17;
-         *  Configures the char needing encoding, which is 0x11 as flow control char by default.
-         */
-        uint32_t esc_seq1:8;
-        /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219;
-         *  Configures the first char of SLIP escape character, default value is 0xDB.
-         */
-        uint32_t esc_seq1_char0:8;
-        /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222;
-         *  Configures the second char of SLIP escape character, default value is 0xDE.
-         */
-        uint32_t esc_seq1_char1:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uhci_esc_conf2_reg_t;
-
-/** Type of esc_conf3 register
- *  UHCI Escapes Sequence Configuration Register3
- */
-typedef union {
-    struct {
-        /** esc_seq2 : R/W; bitpos: [7:0]; default: 19;
-         *  Configures the char needing encoding, which is 0x13 as flow control char by default.
-         */
-        uint32_t esc_seq2:8;
-        /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219;
-         *  Configures the first char of SLIP escape character, default value is 0xDB.
-         */
-        uint32_t esc_seq2_char0:8;
-        /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223;
-         *  Configures the second char of SLIP escape character, default value is 0xDF.
-         */
-        uint32_t esc_seq2_char1:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uhci_esc_conf3_reg_t;
-
-/** Type of pkt_thres register
- *  UCHI Packet Length Configuration Register
- */
-typedef union {
-    struct {
-        /** pkt_thrs : R/W; bitpos: [12:0]; default: 128;
-         *  Configures the data packet's maximum length when UHCI_HEAD_EN is 0.
-         */
-        uint32_t pkt_thrs:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} uhci_pkt_thres_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  UHCI Interrupt Raw Register
- */
-typedef union {
-    struct {
-        /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when
-         *  delimiter is sent successfully.
-         */
-        uint32_t rx_start_int_raw:1;
-        /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when
-         *  DMA detects delimiter.
-         */
-        uint32_t tx_start_int_raw:1;
-        /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when
-         *  the required time of DMA receiving data  exceeds the configuration value.
-         */
-        uint32_t rx_hung_int_raw:1;
-        /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when
-         *  the required time of DMA reading RAM data  exceeds the configuration value.
-         */
-        uint32_t tx_hung_int_raw:1;
-        /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered
-         *  when UHCI sends short packet successfully with single_send mode.
-         */
-        uint32_t send_s_reg_q_int_raw:1;
-        /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered
-         *  when UHCI sends short packet successfully with always_send mode.
-         */
-        uint32_t send_a_reg_q_int_raw:1;
-        /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when
-         *  there are errors in EOF.
-         */
-        uint32_t out_eof_int_raw:1;
-        /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0;
-         *  Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when
-         *  UHCI_APP_CTRL0_IN_SET is set to 1.
-         */
-        uint32_t app_ctrl0_int_raw:1;
-        /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0;
-         *  Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when
-         *  UHCI_APP_CTRL1_IN_SET is set to 1.
-         */
-        uint32_t app_ctrl1_int_raw:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uhci_int_raw_reg_t;
-
-/** Type of int_st register
- *  UHCI Interrupt Status Register
- */
-typedef union {
-    struct {
-        /** rx_start_int_st : RO; bitpos: [0]; default: 0;
-         *  Indicates the interrupt status of UHCI_RX_START_INT.
-         */
-        uint32_t rx_start_int_st:1;
-        /** tx_start_int_st : RO; bitpos: [1]; default: 0;
-         *  Indicates the interrupt status of UHCI_TX_START_INT.
-         */
-        uint32_t tx_start_int_st:1;
-        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
-         *  Indicates the interrupt status of UHCI_RX_HUNG_INT.
-         */
-        uint32_t rx_hung_int_st:1;
-        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
-         *  Indicates the interrupt status of UHCI_TX_HUNG_INT.
-         */
-        uint32_t tx_hung_int_st:1;
-        /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0;
-         *  Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.
-         */
-        uint32_t send_s_reg_q_int_st:1;
-        /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0;
-         *  Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.
-         */
-        uint32_t send_a_reg_q_int_st:1;
-        /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0;
-         *  Indicates the interrupt status of UHCI_OUT_EOF_INT.
-         */
-        uint32_t outlink_eof_err_int_st:1;
-        /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0;
-         *  Indicates the interrupt status of UHCI_APP_CTRL0_INT.
-         */
-        uint32_t app_ctrl0_int_st:1;
-        /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0;
-         *  Indicates the interrupt status of UHCI_APP_CTRL1_INT.
-         */
-        uint32_t app_ctrl1_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uhci_int_st_reg_t;
-
-/** Type of int_ena register
- *  UHCI Interrupt Enable Register
- */
-typedef union {
-    struct {
-        /** rx_start_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_RX_START_INT.
-         */
-        uint32_t rx_start_int_ena:1;
-        /** tx_start_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_TX_START_INT.
-         */
-        uint32_t tx_start_int_ena:1;
-        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.
-         */
-        uint32_t rx_hung_int_ena:1;
-        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.
-         */
-        uint32_t tx_hung_int_ena:1;
-        /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.
-         */
-        uint32_t send_s_reg_q_int_ena:1;
-        /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.
-         */
-        uint32_t send_a_reg_q_int_ena:1;
-        /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.
-         */
-        uint32_t outlink_eof_err_int_ena:1;
-        /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.
-         */
-        uint32_t app_ctrl0_int_ena:1;
-        /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.
-         */
-        uint32_t app_ctrl1_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uhci_int_ena_reg_t;
-
-/** Type of int_clr register
- *  UHCI Interrupt Clear Register
- */
-typedef union {
-    struct {
-        /** rx_start_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_RX_START_INT.
-         */
-        uint32_t rx_start_int_clr:1;
-        /** tx_start_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_TX_START_INT.
-         */
-        uint32_t tx_start_int_clr:1;
-        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.
-         */
-        uint32_t rx_hung_int_clr:1;
-        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.
-         */
-        uint32_t tx_hung_int_clr:1;
-        /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.
-         */
-        uint32_t send_s_reg_q_int_clr:1;
-        /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.
-         */
-        uint32_t send_a_reg_q_int_clr:1;
-        /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.
-         */
-        uint32_t outlink_eof_err_int_clr:1;
-        /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.
-         */
-        uint32_t app_ctrl0_int_clr:1;
-        /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.
-         */
-        uint32_t app_ctrl1_int_clr:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uhci_int_clr_reg_t;
-
-
-/** Group: UHCI Status Register */
-/** Type of state0 register
- *  UHCI Receive Status Register
- */
-typedef union {
-    struct {
-        /** rx_err_cause : RO; bitpos: [2:0]; default: 0;
-         *  Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet
-         *  checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC
-         *  bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is
-         *  not found, but received packet is completed. 3'b110: CRC check error.
-         */
-        uint32_t rx_err_cause:3;
-        /** decode_state : RO; bitpos: [5:3]; default: 0;
-         *  Indicates UHCI decoder status.
-         */
-        uint32_t decode_state:3;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} uhci_state0_reg_t;
-
-/** Type of state1 register
- *  UHCI Transmit Status Register
- */
-typedef union {
-    struct {
-        /** encode_state : RO; bitpos: [2:0]; default: 0;
-         *  Indicates UHCI encoder status.
-         */
-        uint32_t encode_state:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} uhci_state1_reg_t;
-
-/** Type of rx_head register
- *  UHCI Head Register
- */
-typedef union {
-    struct {
-        /** rx_head : RO; bitpos: [31:0]; default: 0;
-         *  Stores the head of received packet.
-         */
-        uint32_t rx_head:32;
-    };
-    uint32_t val;
-} uhci_rx_head_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UHCI Version Register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35655936;
-         *  Configures version.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uhci_date_reg_t;
-
-
-typedef struct uhci_dev_t {
-    volatile uhci_conf0_reg_t conf0;
-    volatile uhci_int_raw_reg_t int_raw;
-    volatile uhci_int_st_reg_t int_st;
-    volatile uhci_int_ena_reg_t int_ena;
-    volatile uhci_int_clr_reg_t int_clr;
-    volatile uhci_conf1_reg_t conf1;
-    volatile uhci_state0_reg_t state0;
-    volatile uhci_state1_reg_t state1;
-    volatile uhci_escape_conf_reg_t escape_conf;
-    volatile uhci_hung_conf_reg_t hung_conf;
-    volatile uhci_ack_num_reg_t ack_num;
-    volatile uhci_rx_head_reg_t rx_head;
-    volatile uhci_quick_sent_reg_t quick_sent;
-    volatile struct {
-        uhci_reg_qn_word0_reg_t word0;
-        uhci_reg_qn_word1_reg_t word1;
-    } q_data[7];
-    volatile uhci_esc_conf0_reg_t esc_conf0;
-    volatile uhci_esc_conf1_reg_t esc_conf1;
-    volatile uhci_esc_conf2_reg_t esc_conf2;
-    volatile uhci_esc_conf3_reg_t esc_conf3;
-    volatile uhci_pkt_thres_reg_t pkt_thres;
-    volatile uhci_date_reg_t date;
-} uhci_dev_t;
-
-extern uhci_dev_t UHCI0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index 5bc71a9d1b..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,1188 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
- *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
- *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
- *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
- *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
- *  how many data is received, then read data from UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
- *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
- *  USB Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- *  1'b1: Indicate there is data in UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  Interrupt raw status register.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when flush cmd is received for IN
- *  endpoint 2 of JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when SOF frame is received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- *  one packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when pid error is detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt bit turns to high level when CRC5 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt bit turns to high level when CRC16 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt bit turns to high level when stuff error is detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
- *  received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt bit turns to high level when usb bus reset is detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  Interrupt status register.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  Interrupt enable status register.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  Interrupt clear status register.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  PHY hardware configuration.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  Select internal/external PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- *  Enable software control USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- *  USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
- *  Control single-end input high threshold,1.76V to 2V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003U
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFH_S  3
-/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
- *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003U
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFL_S  5
-/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- *  Enable software control input  threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- *  Enable software control USB D+ D- pullup pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- *  Control USB D+ pull up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- *  Control USB D+ pull down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- *  Control USB D- pull up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- *  Control USB D- pull down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- *  Control pull up value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- *  Enable USB pad function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
- *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
- *  through GPIO Matrix.
- */
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  Registers used for debugging the PHY.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable test of the USB pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
- *  USB RCV value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
- *  USB D+ rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  JTAG FIFO status and control registers.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
- *  JTAT in fifo counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  1: JTAG in fifo is empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  1: JTAG in fifo is full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
- *  JTAT out fifo counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- *  1: JTAG out fifo is empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- *  1: JTAG out fifo is full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- *  Write 1 to reset JTAG in fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- *  Write 1 to reset JTAG out fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  Last received SOF frame index register.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
- *  Frame index of received SOF frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  Control IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  CDC-ACM IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  JTAG IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  Control OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  CDC-ACM OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
- *  Data count in OUT endpoint 1 when one packet is received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  JTAG OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  Clock enable control
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  Memory power control
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  1: power down usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  1: Force clock on for usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-/** USB_SERIAL_JTAG_CHIP_RST_REG register
- *  CDC-ACM chip reset control.
- */
-#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
-/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
- *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_RTS    (BIT(0))
-#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
-#define USB_SERIAL_JTAG_RTS_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_S  0
-/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
- *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_DTR    (BIT(1))
-#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
-#define USB_SERIAL_JTAG_DTR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_S  1
-/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable chip reset from usb serial channel to reset chip.
- */
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
- *  W0 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
-/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
- *  W1 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
-/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
-/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_S  16
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
- *  W0 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
-/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
- *  W1 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
-/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
-/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
-
-/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
- *  Configuration registers' value update
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
-/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
- *  Write 1 to this register would update the value of configure registers from APB
- *  clock domain to 48MHz clock domain.
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
-
-/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
- *  Serial AFIFO configure register
- */
-#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
- *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
-
-/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
- *  USB Bus reset status register
- */
-#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
-/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
- *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
- *  reset is released.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  Date register
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416;
- *  register version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_struct.h
deleted file mode 100644
index 3c87b7a813..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/usb_serial_jtag_struct.h
+++ /dev/null
@@ -1,941 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of ep1 register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-typedef union {
-    struct {
-        /** rdwr_byte : R/W; bitpos: [7:0]; default: 0;
-         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
-         *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
-         *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
-         *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
-         *  how many data is received, then read data from UART Rx FIFO.
-         */
-        uint32_t rdwr_byte:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} usb_serial_jtag_ep1_reg_t;
-
-/** Type of ep1_conf register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-typedef union {
-    struct {
-        /** wr_done : WT; bitpos: [0]; default: 0;
-         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
-         */
-        uint32_t wr_done:1;
-        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
-         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
-         *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
-         *  USB Host.
-         */
-        uint32_t serial_in_ep_data_free:1;
-        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
-         *  1'b1: Indicate there is data in UART Rx FIFO.
-         */
-        uint32_t serial_out_ep_data_avail:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} usb_serial_jtag_ep1_conf_reg_t;
-
-/** Type of conf0 register
- *  PHY hardware configuration.
- */
-typedef union {
-    struct {
-        /** phy_sel : R/W; bitpos: [0]; default: 0;
-         *  Select internal/external PHY
-         */
-        uint32_t phy_sel:1;
-        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
-         *  Enable software control USB D+ D- exchange
-         */
-        uint32_t exchg_pins_override:1;
-        /** exchg_pins : R/W; bitpos: [2]; default: 0;
-         *  USB D+ D- exchange
-         */
-        uint32_t exchg_pins:1;
-        /** vrefh : R/W; bitpos: [4:3]; default: 0;
-         *  Control single-end input high threshold,1.76V to 2V, step 80mV
-         */
-        uint32_t vrefh:2;
-        /** vrefl : R/W; bitpos: [6:5]; default: 0;
-         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
-         */
-        uint32_t vrefl:2;
-        /** vref_override : R/W; bitpos: [7]; default: 0;
-         *  Enable software control input  threshold
-         */
-        uint32_t vref_override:1;
-        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
-         *  Enable software control USB D+ D- pullup pulldown
-         */
-        uint32_t pad_pull_override:1;
-        /** dp_pullup : R/W; bitpos: [9]; default: 1;
-         *  Control USB D+ pull up.
-         */
-        uint32_t dp_pullup:1;
-        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
-         *  Control USB D+ pull down.
-         */
-        uint32_t dp_pulldown:1;
-        /** dm_pullup : R/W; bitpos: [11]; default: 0;
-         *  Control USB D- pull up.
-         */
-        uint32_t dm_pullup:1;
-        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
-         *  Control USB D- pull down.
-         */
-        uint32_t dm_pulldown:1;
-        /** pullup_value : R/W; bitpos: [13]; default: 0;
-         *  Control pull up value.
-         */
-        uint32_t pullup_value:1;
-        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
-         *  Enable USB pad function.
-         */
-        uint32_t usb_pad_enable:1;
-        /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
-         *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
-         *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
-         *  through GPIO Matrix.
-         */
-        uint32_t usb_jtag_bridge_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_conf0_reg_t;
-
-/** Type of test register
- *  Registers used for debugging the PHY.
- */
-typedef union {
-    struct {
-        /** test_enable : R/W; bitpos: [0]; default: 0;
-         *  Enable test of the USB pad
-         */
-        uint32_t test_enable:1;
-        /** test_usb_oe : R/W; bitpos: [1]; default: 0;
-         *  USB pad oen in test
-         */
-        uint32_t test_usb_oe:1;
-        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
-         *  USB D+ tx value in test
-         */
-        uint32_t test_tx_dp:1;
-        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
-         *  USB D- tx value in test
-         */
-        uint32_t test_tx_dm:1;
-        /** test_rx_rcv : RO; bitpos: [4]; default: 1;
-         *  USB RCV value in test
-         */
-        uint32_t test_rx_rcv:1;
-        /** test_rx_dp : RO; bitpos: [5]; default: 1;
-         *  USB D+ rx value in test
-         */
-        uint32_t test_rx_dp:1;
-        /** test_rx_dm : RO; bitpos: [6]; default: 0;
-         *  USB D- rx value in test
-         */
-        uint32_t test_rx_dm:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} usb_serial_jtag_test_reg_t;
-
-/** Type of misc_conf register
- *  Clock enable control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_misc_conf_reg_t;
-
-/** Type of mem_conf register
- *  Memory power control
- */
-typedef union {
-    struct {
-        /** usb_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  1: power down usb memory.
-         */
-        uint32_t usb_mem_pd:1;
-        /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
-         *  1: Force clock on for usb memory.
-         */
-        uint32_t usb_mem_clk_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_serial_jtag_mem_conf_reg_t;
-
-/** Type of chip_rst register
- *  CDC-ACM chip reset control.
- */
-typedef union {
-    struct {
-        /** rts : RO; bitpos: [0]; default: 0;
-         *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
-         */
-        uint32_t rts:1;
-        /** dtr : RO; bitpos: [1]; default: 0;
-         *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
-         */
-        uint32_t dtr:1;
-        /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to disable chip reset from usb serial channel to reset chip.
-         */
-        uint32_t usb_uart_chip_rst_dis:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} usb_serial_jtag_chip_rst_reg_t;
-
-/** Type of get_line_code_w0 register
- *  W0 of GET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
-         *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_dw_dte_rate:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_get_line_code_w0_reg_t;
-
-/** Type of get_line_code_w1 register
- *  W1 of GET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
-         *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bdata_bits:8;
-        /** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
-         *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bparity_type:8;
-        /** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
-         *  The value of bDataBits set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bchar_format:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} usb_serial_jtag_get_line_code_w1_reg_t;
-
-/** Type of config_update register
- *  Configuration registers' value update
- */
-typedef union {
-    struct {
-        /** config_update : WT; bitpos: [0]; default: 0;
-         *  Write 1 to this register would update the value of configure registers from APB
-         *  clock domain to 48MHz clock domain.
-         */
-        uint32_t config_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_config_update_reg_t;
-
-/** Type of ser_afifo_config register
- *  Serial AFIFO configure register
- */
-typedef union {
-    struct {
-        /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
-         */
-        uint32_t serial_in_afifo_reset_wr:1;
-        /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
-         */
-        uint32_t serial_in_afifo_reset_rd:1;
-        /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
-         */
-        uint32_t serial_out_afifo_reset_wr:1;
-        /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
-         */
-        uint32_t serial_out_afifo_reset_rd:1;
-        /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
-         *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
-         */
-        uint32_t serial_out_afifo_rempty:1;
-        /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
-         *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
-         */
-        uint32_t serial_in_afifo_wfull:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} usb_serial_jtag_ser_afifo_config_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_raw register
- *  Interrupt raw status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when flush cmd is received for IN
-         *  endpoint 2 of JTAG.
-         */
-        uint32_t jtag_in_flush_int_raw:1;
-        /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when SOF frame is received.
-         */
-        uint32_t sof_int_raw:1;
-        /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
-         *  one packet.
-         */
-        uint32_t serial_out_recv_pkt_int_raw:1;
-        /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
-         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
-         */
-        uint32_t serial_in_empty_int_raw:1;
-        /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when pid error is detected.
-         */
-        uint32_t pid_err_int_raw:1;
-        /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when CRC5 error is detected.
-         */
-        uint32_t crc5_err_int_raw:1;
-        /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when CRC16 error is detected.
-         */
-        uint32_t crc16_err_int_raw:1;
-        /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when stuff error is detected.
-         */
-        uint32_t stuff_err_int_raw:1;
-        /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
-         *  received.
-         */
-        uint32_t in_token_rec_in_ep1_int_raw:1;
-        /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when usb bus reset is detected.
-         */
-        uint32_t usb_bus_reset_int_raw:1;
-        /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
-         *  zero palyload.
-         */
-        uint32_t out_ep1_zero_payload_int_raw:1;
-        /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
-         *  zero palyload.
-         */
-        uint32_t out_ep2_zero_payload_int_raw:1;
-        /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
-         *  is changed.
-         */
-        uint32_t rts_chg_int_raw:1;
-        /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
-         *  is changed.
-         */
-        uint32_t dtr_chg_int_raw:1;
-        /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
-         *  received.
-         */
-        uint32_t get_line_code_int_raw:1;
-        /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
-         *  received.
-         */
-        uint32_t set_line_code_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_raw_reg_t;
-
-/** Type of int_st register
- *  Interrupt status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_st:1;
-        /** sof_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
-         */
-        uint32_t sof_int_st:1;
-        /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_st:1;
-        /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_st:1;
-        /** pid_err_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_st:1;
-        /** crc5_err_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_st:1;
-        /** crc16_err_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_st:1;
-        /** stuff_err_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_st:1;
-        /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
-         *  interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_st:1;
-        /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_st:1;
-        /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
-         *  interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_st:1;
-        /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
-         *  interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_st:1;
-        /** rts_chg_int_st : RO; bitpos: [12]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_st:1;
-        /** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_st:1;
-        /** get_line_code_int_st : RO; bitpos: [14]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_st:1;
-        /** set_line_code_int_st : RO; bitpos: [15]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_ena:1;
-        /** sof_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
-         */
-        uint32_t sof_int_ena:1;
-        /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_ena:1;
-        /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_ena:1;
-        /** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_ena:1;
-        /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_ena:1;
-        /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_ena:1;
-        /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_ena:1;
-        /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_ena:1;
-        /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_ena:1;
-        /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_ena:1;
-        /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_ena:1;
-        /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_ena:1;
-        /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_ena:1;
-        /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_ena:1;
-        /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_clr:1;
-        /** sof_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
-         */
-        uint32_t sof_int_clr:1;
-        /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_clr:1;
-        /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_clr:1;
-        /** pid_err_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_clr:1;
-        /** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_clr:1;
-        /** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_clr:1;
-        /** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_clr:1;
-        /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_clr:1;
-        /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_clr:1;
-        /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_clr:1;
-        /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_clr:1;
-        /** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_clr:1;
-        /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_clr:1;
-        /** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_clr:1;
-        /** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_clr_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of jfifo_st register
- *  JTAG FIFO status and control registers.
- */
-typedef union {
-    struct {
-        /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
-         *  JTAT in fifo counter.
-         */
-        uint32_t in_fifo_cnt:2;
-        /** in_fifo_empty : RO; bitpos: [2]; default: 1;
-         *  1: JTAG in fifo is empty.
-         */
-        uint32_t in_fifo_empty:1;
-        /** in_fifo_full : RO; bitpos: [3]; default: 0;
-         *  1: JTAG in fifo is full.
-         */
-        uint32_t in_fifo_full:1;
-        /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
-         *  JTAT out fifo counter.
-         */
-        uint32_t out_fifo_cnt:2;
-        /** out_fifo_empty : RO; bitpos: [6]; default: 1;
-         *  1: JTAG out fifo is empty.
-         */
-        uint32_t out_fifo_empty:1;
-        /** out_fifo_full : RO; bitpos: [7]; default: 0;
-         *  1: JTAG out fifo is full.
-         */
-        uint32_t out_fifo_full:1;
-        /** in_fifo_reset : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to reset JTAG in fifo.
-         */
-        uint32_t in_fifo_reset:1;
-        /** out_fifo_reset : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to reset JTAG out fifo.
-         */
-        uint32_t out_fifo_reset:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} usb_serial_jtag_jfifo_st_reg_t;
-
-/** Type of fram_num register
- *  Last received SOF frame index register.
- */
-typedef union {
-    struct {
-        /** sof_frame_index : RO; bitpos: [10:0]; default: 0;
-         *  Frame index of received SOF frame.
-         */
-        uint32_t sof_frame_index:11;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} usb_serial_jtag_fram_num_reg_t;
-
-/** Type of in_ep0_st register
- *  Control IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep0_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 0.
-         */
-        uint32_t in_ep0_state:2;
-        /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 0.
-         */
-        uint32_t in_ep0_wr_addr:7;
-        /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 0.
-         */
-        uint32_t in_ep0_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep0_st_reg_t;
-
-/** Type of in_ep1_st register
- *  CDC-ACM IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep1_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 1.
-         */
-        uint32_t in_ep1_state:2;
-        /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 1.
-         */
-        uint32_t in_ep1_wr_addr:7;
-        /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 1.
-         */
-        uint32_t in_ep1_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep1_st_reg_t;
-
-/** Type of in_ep2_st register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep2_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 2.
-         */
-        uint32_t in_ep2_state:2;
-        /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 2.
-         */
-        uint32_t in_ep2_wr_addr:7;
-        /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 2.
-         */
-        uint32_t in_ep2_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep2_st_reg_t;
-
-/** Type of in_ep3_st register
- *  JTAG IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep3_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 3.
-         */
-        uint32_t in_ep3_state:2;
-        /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 3.
-         */
-        uint32_t in_ep3_wr_addr:7;
-        /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 3.
-         */
-        uint32_t in_ep3_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep3_st_reg_t;
-
-/** Type of out_ep0_st register
- *  Control OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep0_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 0.
-         */
-        uint32_t out_ep0_state:2;
-        /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
-         */
-        uint32_t out_ep0_wr_addr:7;
-        /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 0.
-         */
-        uint32_t out_ep0_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep0_st_reg_t;
-
-/** Type of out_ep1_st register
- *  CDC-ACM OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep1_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 1.
-         */
-        uint32_t out_ep1_state:2;
-        /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
-         */
-        uint32_t out_ep1_wr_addr:7;
-        /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 1.
-         */
-        uint32_t out_ep1_rd_addr:7;
-        /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
-         *  Data count in OUT endpoint 1 when one packet is received.
-         */
-        uint32_t out_ep1_rec_data_cnt:7;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep1_st_reg_t;
-
-/** Type of out_ep2_st register
- *  JTAG OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep2_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 2.
-         */
-        uint32_t out_ep2_state:2;
-        /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
-         */
-        uint32_t out_ep2_wr_addr:7;
-        /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 2.
-         */
-        uint32_t out_ep2_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep2_st_reg_t;
-
-/** Type of set_line_code_w0 register
- *  W0 of SET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
-         *  The value of dwDTERate set by host through SET_LINE_CODING command.
-         */
-        uint32_t dw_dte_rate:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_set_line_code_w0_reg_t;
-
-/** Type of set_line_code_w1 register
- *  W1 of SET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** bchar_format : RO; bitpos: [7:0]; default: 0;
-         *  The value of bCharFormat set by host through SET_LINE_CODING command.
-         */
-        uint32_t bchar_format:8;
-        /** bparity_type : RO; bitpos: [15:8]; default: 0;
-         *  The value of bParityTpye set by host through SET_LINE_CODING command.
-         */
-        uint32_t bparity_type:8;
-        /** bdata_bits : RO; bitpos: [23:16]; default: 0;
-         *  The value of bDataBits set by host through SET_LINE_CODING command.
-         */
-        uint32_t bdata_bits:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} usb_serial_jtag_set_line_code_w1_reg_t;
-
-/** Type of bus_reset_st register
- *  USB Bus reset status register
- */
-typedef union {
-    struct {
-        /** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
-         *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
-         *  reset is released.
-         */
-        uint32_t usb_bus_reset_st:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_bus_reset_st_reg_t;
-
-
-/** Group: Version Registers */
-/** Type of date register
- *  Date register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 34640416;
-         *  register version.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_date_reg_t;
-
-
-typedef struct usb_serial_jtag_dev_t {
-    volatile usb_serial_jtag_ep1_reg_t ep1;
-    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
-    volatile usb_serial_jtag_int_raw_reg_t int_raw;
-    volatile usb_serial_jtag_int_st_reg_t int_st;
-    volatile usb_serial_jtag_int_ena_reg_t int_ena;
-    volatile usb_serial_jtag_int_clr_reg_t int_clr;
-    volatile usb_serial_jtag_conf0_reg_t conf0;
-    volatile usb_serial_jtag_test_reg_t test;
-    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
-    volatile usb_serial_jtag_fram_num_reg_t fram_num;
-    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
-    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
-    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
-    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
-    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
-    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
-    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
-    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
-    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
-    volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
-    volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
-    volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
-    volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
-    volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
-    volatile usb_serial_jtag_config_update_reg_t config_update;
-    volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
-    volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
-    uint32_t reserved_06c[5];
-    volatile usb_serial_jtag_date_reg_t date;
-} usb_serial_jtag_dev_t;
-
-extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/wdev_reg.h b/components/soc/esp32c5/beta3/include/soc/wdev_reg.h
deleted file mode 100644
index 27550805eb..0000000000
--- a/components/soc/esp32c5/beta3/include/soc/wdev_reg.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc.h"
-#include "soc/lpperi_reg.h"
-
-/* Hardware random number generator register */
-#define WDEV_RND_REG LPPERI_RNG_DATA_REG
diff --git a/components/soc/esp32c5/beta3/interrupts.c b/components/soc/esp32c5/beta3/interrupts.c
deleted file mode 100644
index d688b00afe..0000000000
--- a/components/soc/esp32c5/beta3/interrupts.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/interrupts.h"
-
-const char *const esp_isr_names[] = {
-    [ETS_WIFI_MAC_INTR_SOURCE] = "WIFI_MAC",
-    [ETS_WIFI_MAC_NMI_SOURCE] = "WIFI_MAC_NMI",
-    [ETS_WIFI_PWR_INTR_SOURCE] = "WIFI_PWR",
-    [ETS_WIFI_BB_INTR_SOURCE] = "WIFI_BB",
-    [ETS_BT_MAC_INTR_SOURCE] = "BT_MAC",
-    [ETS_BT_BB_INTR_SOURCE] = "BT_BB",
-    [ETS_BT_BB_NMI_SOURCE] = "BT_BB_NMI",
-    [ETS_LP_TIMER_INTR_SOURCE] = "LP_TIMER",
-    [ETS_COEX_INTR_SOURCE] = "COEX",
-    [ETS_BLE_TIMER_INTR_SOURCE] = "BLE_TIMER",
-    [ETS_BLE_SEC_INTR_SOURCE] = "BLE_SEC",
-    [ETS_I2C_MASTER_SOURCE] = "I2C_MASTER",
-    [ETS_ZB_MAC_INTR_SOURCE] = "ZB_MAC",
-    [ETS_PMU_INTR_SOURCE] = "PMU",
-    [ETS_EFUSE_INTR_SOURCE] = "EFUSE",
-    [ETS_LP_RTC_TIMER_INTR_SOURCE] = "LP_RTC_TIMER",
-    [ETS_LP_UART_INTR_SOURCE] = "LP_UART",
-    [ETS_LP_I2C_INTR_SOURCE] = "LP_I2C",
-    [ETS_LP_WDT_INTR_SOURCE] = "LP_WDT",
-    [ETS_LP_PERI_TIMEOUT_INTR_SOURCE] = "LP_PERI_TIMEOUT",
-    [ETS_LP_APM_M0_INTR_SOURCE] = "LP_APM_M0",
-    [ETS_LP_APM_M1_INTR_SOURCE] = "LP_APM_M1",
-    [ETS_HUK_INTR_SOURCE] = "HUK",
-    [ETS_FROM_CPU_INTR0_SOURCE] = "FROM_CPU_INTR0",
-    [ETS_FROM_CPU_INTR1_SOURCE] = "FROM_CPU_INTR1",
-    [ETS_FROM_CPU_INTR2_SOURCE] = "FROM_CPU_INTR2",
-    [ETS_FROM_CPU_INTR3_SOURCE] = "FROM_CPU_INTR3",
-    [ETS_ASSIST_DEBUG_INTR_SOURCE] = "ASSIST_DEBUG",
-    [ETS_TRACE_INTR_SOURCE] = "TRACE",
-    [ETS_CACHE_INTR_SOURCE] = "CACHE",
-    [ETS_CPU_PERI_TIMEOUT_INTR_SOURCE] = "CPU_PERI_TIMEOUT",
-    [ETS_GPIO_INTR_SOURCE] = "GPIO_INTR",
-    [ETS_GPIO_NMI_SOURCE] = "GPIO_NMI",
-    [ETS_GPIO_SD_INTR_SOURCE] = "GPIO_SD_INTR",
-    [ETS_PAU_INTR_SOURCE] = "PAU",
-    [ETS_HP_PERI_TIMEOUT_INTR_SOURCE] = "HP_PERI_TIMEOUT",
-    [ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE] = "MODEM_PERI_TIMEOUT",
-    [ETS_HP_APM_M0_INTR_SOURCE] = "HP_APM_M0",
-    [ETS_HP_APM_M1_INTR_SOURCE] = "HP_APM_M1",
-    [ETS_HP_APM_M2_INTR_SOURCE] = "HP_APM_M2",
-    [ETS_HP_APM_M3_INTR_SOURCE] = "HP_APM_M3",
-    [ETS_LP_APM0_INTR_SOURCE] = "LP_APM0",
-    [ETS_MSPI_INTR_SOURCE] = "MSPI",
-    [ETS_I2S1_INTR_SOURCE] = "I2S1",
-    [ETS_UHCI0_INTR_SOURCE] = "UHCI0",
-    [ETS_UART0_INTR_SOURCE] = "UART0",
-    [ETS_UART1_INTR_SOURCE] = "UART1",
-    [ETS_LEDC_INTR_SOURCE] = "LEDC",
-    [ETS_TWAI0_INTR_SOURCE] = "TWAI0",
-    [ETS_TWAI1_INTR_SOURCE] = "TWAI1",
-    [ETS_USB_SERIAL_JTAG_INTR_SOURCE] = "USB_SERIAL_JTAG",
-    [ETS_RMT_INTR_SOURCE] = "RMT",
-    [ETS_I2C_EXT0_INTR_SOURCE] = "I2C_EXT0",
-    [ETS_TG0_T0_LEVEL_INTR_SOURCE] = "TG0_T0_LEVEL",
-    [ETS_TG0_T1_LEVEL_INTR_SOURCE] = "TG0_T1_LEVEL",
-    [ETS_TG0_WDT_LEVEL_INTR_SOURCE] = "TG0_WDT_LEVEL",
-    [ETS_TG1_T0_LEVEL_INTR_SOURCE] = "TG1_T0_LEVEL",
-    [ETS_TG1_T1_LEVEL_INTR_SOURCE] = "TG1_T1_LEVEL",
-    [ETS_TG1_WDT_LEVEL_INTR_SOURCE] = "TG1_WDT_LEVEL",
-    [ETS_SYSTIMER_TARGET0_INTR_SOURCE] = "SYSTIMER_TARGET0",
-    [ETS_SYSTIMER_TARGET1_INTR_SOURCE] = "SYSTIMER_TARGET1",
-    [ETS_SYSTIMER_TARGET2_INTR_SOURCE] = "SYSTIMER_TARGET2",
-    [ETS_APB_ADC_INTR_SOURCE] = "APB_ADC",
-    [ETS_MCPWM0_INTR_SOURCE] = "MCPWM0",
-    [ETS_PCNT_INTR_SOURCE] = "PCNT",
-    [ETS_PARL_IO_TX_INTR_SOURCE] = "PARL_IO_TX",
-    [ETS_PARL_IO_RX_INTR_SOURCE] = "PARL_IO_RX",
-    [ETS_SLC0_INTR_SOURCE] = "SLC0_INTR",
-    [ETS_SLC1_INTR_SOURCE] = "SLC1_INTR",
-    [ETS_USB_OTG20_INTR_SOURCE] = "USB_OTG_INTR",
-    [ETS_USB_OTG20_MULTI_PROC_INTR_SOURCE] = "USB_OTG_MULTI",
-    [ETS_USB_OTG20_MISC_INTR_SOURCE] = "USB_OTG_MISC",
-    [ETS_DMA_IN_CH0_INTR_SOURCE] = "DMA_IN_CH0",
-    [ETS_DMA_IN_CH1_INTR_SOURCE] = "DMA_IN_CH1",
-    [ETS_DMA_IN_CH2_INTR_SOURCE] = "DMA_IN_CH2",
-    [ETS_DMA_OUT_CH0_INTR_SOURCE] = "DMA_OUT_CH0",
-    [ETS_DMA_OUT_CH1_INTR_SOURCE] = "DMA_OUT_CH1",
-    [ETS_DMA_OUT_CH2_INTR_SOURCE] = "DMA_OUT_CH2",
-    [ETS_GPSPI2_INTR_SOURCE] = "GPSPI2",
-    [ETS_AES_INTR_SOURCE] = "AES",
-    [ETS_SHA_INTR_SOURCE] = "SHA",
-    [ETS_RSA_INTR_SOURCE] = "RSA",
-    [ETS_ECC_INTR_SOURCE] = "ECC",
-    [ETS_ECDSA_INTR_SOURCE] = "ECDSA",
-    [ETS_KM_INTR_SOURCE] = "KM"
-};
diff --git a/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
deleted file mode 100644
index 54c687aff3..0000000000
--- a/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-PROVIDE ( UART0               = 0x60000000 );
-PROVIDE ( UART1               = 0x60001000 );
-PROVIDE ( SPIMEM0             = 0x60002000 );
-PROVIDE ( SPIMEM1             = 0x60003000 );
-PROVIDE ( I2C0                = 0x60004000 );
-PROVIDE ( UHCI0               = 0x60005000 );
-PROVIDE ( RMT                 = 0x60006000 );
-PROVIDE ( RMTMEM              = 0x60006400 );
-PROVIDE ( LEDC                = 0x60007000 );
-PROVIDE ( TIMERG0             = 0x60008000 );
-PROVIDE ( TIMERG1             = 0x60009000 );
-PROVIDE ( SYSTIMER            = 0x6000A000 );
-PROVIDE ( TWAI0               = 0x6000B000 );
-PROVIDE ( I2S                 = 0x6000C000 );
-PROVIDE ( TWAI1               = 0x6000D000 );
-PROVIDE ( APB_SARADC          = 0x6000E000 );
-PROVIDE ( USB_SERIAL_JTAG     = 0x6000F000 );
-PROVIDE ( INTMTX              = 0x60010000 );
-PROVIDE ( PCNT                = 0x60012000 );
-PROVIDE ( SOC_ETM             = 0x60013000 );
-PROVIDE ( MCPWM               = 0x60014000 );
-PROVIDE ( PARL_IO             = 0x60015000 );
-PROVIDE ( PVT_MONITOR         = 0x60019000 );
-
-PROVIDE ( GDMA                = 0x60080000 );
-PROVIDE ( GPSPI2              = 0x60081000 );
-PROVIDE ( BITSCRAMBLER        = 0x60082000 );
-PROVIDE ( KEYMNG              = 0x60087000 );
-PROVIDE ( AES                 = 0x60088000 );
-PROVIDE ( SHA                 = 0x60089000 );
-PROVIDE ( RSA                 = 0x6008A000 );
-PROVIDE ( ECC                 = 0x6008B000 );
-PROVIDE ( DS                  = 0x6008C000 );
-PROVIDE ( HMAC                = 0x6008D000 );
-PROVIDE ( ECDSA               = 0x6008E000 );
-
-PROVIDE ( IO_MUX              = 0x60090000 );
-PROVIDE ( GPIO                = 0x60091000 );
-PROVIDE ( GPIO_EXT            = 0x60091f00 );
-PROVIDE ( SDM                 = 0x60091f00 );
-PROVIDE ( GLITCH_FILTER       = 0x60091f30 );
-PROVIDE ( GPIO_ETM            = 0x60091f60 );
-PROVIDE ( MEM_MONITOR         = 0x60092000 );
-PROVIDE ( PAU                 = 0x60093000 );
-PROVIDE ( HP_SYSTEM           = 0x60095000 );
-PROVIDE ( PCR                 = 0x60096000 );
-PROVIDE ( TEE                 = 0x60098000 );
-PROVIDE ( HP_APM              = 0x60099000 );
-PROVIDE ( LP_APM0             = 0x60099800 );
-PROVIDE ( MISC                = 0x6009F000 );
-
-PROVIDE ( MODEM               = 0x600A4000 );
-PROVIDE ( MODEM_PWR           = 0x600AD000 );
-PROVIDE ( MODEM_SYSCON        = 0x600A9800 );
-PROVIDE ( MODEM_LPCON         = 0x600AF000 );
-
-PROVIDE ( PMU                 = 0x600B0000 );
-PROVIDE ( LP_CLKRST           = 0x600B0400 );
-PROVIDE ( EFUSE               = 0x600B0800 );
-PROVIDE ( LP_TIMER            = 0x600B0C00 );
-PROVIDE ( LP_AON              = 0x600B1000 );
-PROVIDE ( LP_UART             = 0x600B1400 );
-PROVIDE ( LP_I2C              = 0x600B1800 );
-PROVIDE ( LP_WDT              = 0x600B1C00 );
-PROVIDE ( LP_IO               = 0x600B2000 );
-PROVIDE ( LP_I2C_ANA_MST      = 0x600B2400 );
-PROVIDE ( LPPERI              = 0x600B2800 );
-PROVIDE ( LP_ANA_PERI         = 0x600B2C00 );
-PROVIDE ( HUK                 = 0x600B3000 );
-PROVIDE ( LP_TEE              = 0x600B3400 );
-PROVIDE ( LP_APM              = 0x600B3800 );
-PROVIDE ( OTP_DEBUG           = 0x600B3C00 );
-
-PROVIDE ( TRACE               = 0x600C0000 );
-PROVIDE ( ASSIST_DEBUG        = 0x600C2000 );
-PROVIDE ( INTPRI              = 0x600C5000 );
-PROVIDE ( CACHE               = 0x600C8000 );
-PROVIDE ( IEEE802154          = 0x600A3000 );
diff --git a/components/soc/esp32c5/beta3/spi_periph.c b/components/soc/esp32c5/beta3/spi_periph.c
deleted file mode 100644
index 6775e72e95..0000000000
--- a/components/soc/esp32c5/beta3/spi_periph.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stddef.h>
-#include "soc/spi_periph.h"
-
-/*
- Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
-*/
-const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
-    {
-        // MSPI has dedicated iomux pins
-        .spiclk_out = -1,
-        .spiclk_in = -1,
-        .spid_out = -1,
-        .spiq_out = -1,
-        .spiwp_out = -1,
-        .spihd_out = -1,
-        .spid_in = -1,
-        .spiq_in = -1,
-        .spiwp_in = -1,
-        .spihd_in = -1,
-        .spics_out = {-1},
-        .spics_in = -1,
-        .spiclk_iomux_pin = -1,
-        .spid_iomux_pin = -1,
-        .spiq_iomux_pin = -1,
-        .spiwp_iomux_pin = -1,
-        .spihd_iomux_pin = -1,
-        .spics0_iomux_pin = -1,
-        .irq = -1,
-        .irq_dma = -1,
-        .module = -1,
-        .hw = NULL,
-        .func = -1,
-    }, {
-        .spiclk_out = FSPICLK_OUT_MUX_IDX,
-        .spiclk_in = FSPICLK_IN_IDX,
-        .spid_out = FSPID_OUT_IDX,
-        .spiq_out = FSPIQ_OUT_IDX,
-        .spiwp_out = FSPIWP_OUT_IDX,
-        .spihd_out = FSPIHD_OUT_IDX,
-        .spid_in = FSPID_IN_IDX,
-        .spiq_in = FSPIQ_IN_IDX,
-        .spiwp_in = FSPIWP_IN_IDX,
-        .spihd_in = FSPIHD_IN_IDX,
-        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
-        .spics_in = FSPICS0_IN_IDX,
-        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
-        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
-        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
-        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
-        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
-        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
-        .irq = ETS_GPSPI2_INTR_SOURCE,
-        .irq_dma = -1,
-        .module = PERIPH_GPSPI2_MODULE,
-        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
-    },
-};
diff --git a/components/soc/esp32c5/beta3/system_retention_periph.c b/components/soc/esp32c5/beta3/system_retention_periph.c
deleted file mode 100644
index 52822f9272..0000000000
--- a/components/soc/esp32c5/beta3/system_retention_periph.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/regdma.h"
-#include "soc/system_periph_retention.h"
-#include "soc/timer_periph.h"
-#include "soc/uart_reg.h"
-#include "soc/systimer_reg.h"
-#include "soc/timer_group_reg.h"
-#include "soc/spi_mem_reg.h"
-#include "soc/hp_system_reg.h"
-#include "soc/tee_reg.h"
-#include "soc/hp_apm_reg.h"
-#include "soc/gpio_reg.h"
-#include "soc/io_mux_reg.h"
-#include "soc/interrupt_matrix_reg.h"
-
-/* Interrupt Matrix Registers Context */
-#define N_REGS_INTR_MATRIX()    (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1)
-const regdma_entries_config_t intr_matrix_regs_retention[] = {
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_MATRIX_BASE, DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* intr matrix */
-};
-_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");
-
-/* HP System Registers Context */
-#define N_REGS_HP_SYSTEM()      (((HP_SYS_MEM_TEST_CONF_REG - DR_REG_HP_SYS_BASE) / 4) + 1)
-const regdma_entries_config_t hp_system_regs_retention[] = {
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYS_BASE, DR_REG_HP_SYS_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* hp system */
-};
-_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions");
-
-/* TEE/APM Registers Context */
-#define N_REGS_TEE()    (((TEE_CLOCK_GATE_REG - DR_REG_TEE_BASE) / 4) + 1)
-#define N_REGS_APM()    (((HP_APM_CLOCK_GATE_REG - DR_REG_HP_APM_BASE) / 4) + 1)
-const regdma_entries_config_t tee_apm_regs_retention[] = {
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0), DR_REG_HP_APM_BASE, DR_REG_HP_APM_BASE, N_REGS_APM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* apm */
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(1), DR_REG_TEE_BASE,    DR_REG_TEE_BASE,    N_REGS_TEE(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* tee */
-};
-const regdma_entries_config_t tee_apm_highpri_regs_retention[] = {
-    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TEEAPM_LINK(2), TEE_M4_MODE_CTRL_REG, 0x0, 0xffffffff, 1, 0), .owner = ENTRY(2) }
-};
-_Static_assert((ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN) && (ARRAY_SIZE(tee_apm_highpri_regs_retention) == TEE_APM_HIGH_PRI_RETENTION_LINK_LEN), "Inconsistent TEE_APM retention link length definitions");
-
-/* IO MUX Registers Context */
-#define N_REGS_IOMUX_0()    (((IO_MUX_GPIO26_REG - REG_IO_MUX_BASE) / 4) + 1)
-#define N_REGS_IOMUX_1()    (((GPIO_FUNC30_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1)
-#define N_REGS_IOMUX_2()    (((GPIO_FUNC124_IN_SEL_CFG_REG - GPIO_STATUS_NEXT_REG) / 4) + 1)
-#define N_REGS_IOMUX_3()    (((GPIO_PIN30_REG - DR_REG_GPIO_BASE) / 4) + 1)
-const regdma_entries_config_t iomux_regs_retention[] = {
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE,            REG_IO_MUX_BASE,            N_REGS_IOMUX_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* io_mux */
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_IOMUX_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_STATUS_NEXT_REG,       GPIO_STATUS_NEXT_REG,       N_REGS_IOMUX_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), DR_REG_GPIO_BASE,           DR_REG_GPIO_BASE,           N_REGS_IOMUX_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }
-};
-_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions");
-
-/* Memory SPI Registers Context */
-#define N_REGS_SPI1_MEM_0()     (((SPI_SMEM_DDR_REG(1) - REG_SPI_MEM_BASE(1)) / 4) + 1)
-#define N_REGS_SPI1_MEM_1()     (((SPI_SMEM_AC_REG(1) - SPI_FMEM_PMS0_ATTR_REG(1)) / 4) + 1)
-#define N_REGS_SPI1_MEM_2()     (1)
-#define N_REGS_SPI1_MEM_3()     (((SPI_MEM_DATE_REG(1) - SPI_MEM_MMU_POWER_CTRL_REG(1)) / 4) + 1)
-#define N_REGS_SPI0_MEM_0()     (((SPI_SMEM_DDR_REG(0) - REG_SPI_MEM_BASE(0)) / 4) + 1)
-#define N_REGS_SPI0_MEM_1()     (((SPI_SMEM_AC_REG(0) - SPI_FMEM_PMS0_ATTR_REG(0)) / 4) + 1)
-#define N_REGS_SPI0_MEM_2()     (1)
-#define N_REGS_SPI0_MEM_3()     (((SPI_MEM_DATE_REG(0) - SPI_MEM_MMU_POWER_CTRL_REG(0)) / 4) + 1)
-const regdma_entries_config_t spimem_regs_retention[] = {
-    /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
-    [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), REG_SPI_MEM_BASE(1),               REG_SPI_MEM_BASE(1),               N_REGS_SPI1_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_FMEM_PMS0_ATTR_REG(1),         SPI_FMEM_PMS0_ATTR_REG(1), N_REGS_SPI1_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI_MEM_CLOCK_GATE_REG(1),         SPI_MEM_CLOCK_GATE_REG(1),         N_REGS_SPI1_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI_MEM_MMU_POWER_CTRL_REG(1),     SPI_MEM_MMU_POWER_CTRL_REG(1),     N_REGS_SPI1_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
-
-    /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), REG_SPI_MEM_BASE(0),               REG_SPI_MEM_BASE(0),               N_REGS_SPI0_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */
-    [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_FMEM_PMS0_ATTR_REG(0),         SPI_FMEM_PMS0_ATTR_REG(0), N_REGS_SPI0_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_CLOCK_GATE_REG(0),         SPI_MEM_CLOCK_GATE_REG(0),         N_REGS_SPI0_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x07), SPI_MEM_MMU_POWER_CTRL_REG(0),     SPI_MEM_MMU_POWER_CTRL_REG(0),     N_REGS_SPI0_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }
-};
-_Static_assert(ARRAY_SIZE(spimem_regs_retention) == SPIMEM_RETENTION_LINK_LEN, "Inconsistent SPI Mem retention link length definitions");
-
-/* Systimer Registers Context */
-#define N_REGS_SYSTIMER_0()     (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1)
-const regdma_entries_config_t systimer_regs_retention[] = {
-    [0]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT0_OP_REG,       SYSTIMER_TIMER_UNIT0_UPDATE_M,    SYSTIMER_TIMER_UNIT0_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer */
-    [1]  = { .config = REGDMA_LINK_WAIT_INIT      (REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT0_OP_REG,       SYSTIMER_TIMER_UNIT0_VALUE_VALID, SYSTIMER_TIMER_UNIT0_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
-    [2]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT0_VALUE_HI_REG, SYSTIMER_UNIT0_LOAD_HI_REG,       2,                                0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [3]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT0_LOAD_REG,     SYSTIMER_TIMER_UNIT0_LOAD_M,      SYSTIMER_TIMER_UNIT0_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
-
-    [4]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_UNIT1_OP_REG,       SYSTIMER_TIMER_UNIT1_UPDATE_M,    SYSTIMER_TIMER_UNIT1_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) },
-    [5]  = { .config = REGDMA_LINK_WAIT_INIT      (REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_UNIT1_OP_REG,       SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) },
-    [6]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG,       2,                                0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [7]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_UNIT1_LOAD_REG,     SYSTIMER_TIMER_UNIT1_LOAD_M,      SYSTIMER_TIMER_UNIT1_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
-
-    [8]  = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_TARGET0_HI_REG,     SYSTIMER_TARGET0_HI_REG,          N_REGS_SYSTIMER_0(),              0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */
-
-    [9]  = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_COMP0_LOAD_REG,     SYSTIMER_TIMER_COMP0_LOAD,        SYSTIMER_TIMER_COMP0_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [10] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0a), SYSTIMER_COMP1_LOAD_REG,     SYSTIMER_TIMER_COMP1_LOAD,        SYSTIMER_TIMER_COMP1_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [11] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0b), SYSTIMER_COMP2_LOAD_REG,     SYSTIMER_TIMER_COMP2_LOAD,        SYSTIMER_TIMER_COMP2_LOAD,        1, 0), .owner = ENTRY(0) | ENTRY(2) },
-
-    [12] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0c), SYSTIMER_TARGET0_CONF_REG,   0,                                SYSTIMER_TARGET0_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [13] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0d), SYSTIMER_TARGET0_CONF_REG,   SYSTIMER_TARGET0_PERIOD_MODE_M,   SYSTIMER_TARGET0_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
-
-    [14] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0e), SYSTIMER_TARGET1_CONF_REG,   0,                                SYSTIMER_TARGET1_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [15] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x0f), SYSTIMER_TARGET1_CONF_REG,   SYSTIMER_TARGET1_PERIOD_MODE_M,   SYSTIMER_TARGET1_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
-
-    [16] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_SYSTIMER_LINK(0x10), SYSTIMER_TARGET2_CONF_REG,   0,                                SYSTIMER_TARGET2_PERIOD_MODE_M,   1, 0), .owner = ENTRY(0) | ENTRY(2) },
-
-    [17] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x11), SYSTIMER_CONF_REG,           SYSTIMER_CONF_REG,                1,                                0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */
-    [18] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x12), SYSTIMER_INT_ENA_REG,        SYSTIMER_INT_ENA_REG,             1,                                0, 0), .owner = ENTRY(0) | ENTRY(2) }  /* Systimer intr enable */
-};
-_Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions");
diff --git a/components/soc/esp32c5/beta3/uart_periph.c b/components/soc/esp32c5/beta3/uart_periph.c
deleted file mode 100644
index 49af724e26..0000000000
--- a/components/soc/esp32c5/beta3/uart_periph.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/uart_periph.h"
-#include "soc/uart_reg.h"
-
-/*
- Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
-*/
-const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
-   { // HP UART0
-        .pins = {
-            [SOC_UART_TX_PIN_IDX] = {
-                .default_gpio = U0TXD_GPIO_NUM,
-                .iomux_func = U0TXD_MUX_FUNC,
-                .input = 0,
-                .signal = U0TXD_OUT_IDX,
-            },
-
-            [SOC_UART_RX_PIN_IDX] = {
-                .default_gpio = U0RXD_GPIO_NUM,
-                .iomux_func = U0RXD_MUX_FUNC,
-                .input = 1,
-                .signal = U0RXD_IN_IDX,
-            },
-
-            [SOC_UART_RTS_PIN_IDX] = {
-                .default_gpio = U0RTS_GPIO_NUM,
-                .iomux_func = U0RTS_MUX_FUNC,
-                .input = 0,
-                .signal = U0RTS_OUT_IDX,
-            },
-
-            [SOC_UART_CTS_PIN_IDX] = {
-                .default_gpio = U0CTS_GPIO_NUM,
-                .iomux_func = U0CTS_MUX_FUNC,
-                .input = 1,
-                .signal = U0CTS_IN_IDX,
-            }
-        },
-        .irq = ETS_UART0_INTR_SOURCE,
-    },
-
-    { // HP UART1
-        .pins = {
-            [SOC_UART_TX_PIN_IDX] = {
-                .default_gpio = U1TXD_GPIO_NUM,
-                .iomux_func = U1TXD_MUX_FUNC,
-                .input = 0,
-                .signal = U1TXD_OUT_IDX,
-            },
-
-            [SOC_UART_RX_PIN_IDX] = {
-                .default_gpio = U1RXD_GPIO_NUM,
-                .iomux_func = U1RXD_MUX_FUNC,
-                .input = 1,
-                .signal = U1RXD_IN_IDX,
-            },
-
-            [SOC_UART_RTS_PIN_IDX] = {
-                .default_gpio = U1RTS_GPIO_NUM,
-                .iomux_func = U1RTS_MUX_FUNC,
-                .input = 0,
-                .signal = U1RTS_OUT_IDX,
-            },
-
-            [SOC_UART_CTS_PIN_IDX] = {
-                .default_gpio = U1CTS_GPIO_NUM,
-                .iomux_func = U1CTS_MUX_FUNC,
-                .input = 1,
-                .signal = U1CTS_IN_IDX,
-            },
-        },
-        .irq = ETS_UART1_INTR_SOURCE,
-    },
-
-    { // LP UART0
-        .pins = {
-            [SOC_UART_TX_PIN_IDX] = {
-                .default_gpio = LP_U0TXD_GPIO_NUM,
-                .iomux_func = LP_U0TXD_MUX_FUNC,
-                .input = 0,
-                .signal = UINT8_MAX, // Signal not available in signal map
-            },
-
-            [SOC_UART_RX_PIN_IDX] = {
-                .default_gpio = LP_U0RXD_GPIO_NUM,
-                .iomux_func = LP_U0RXD_MUX_FUNC,
-                .input = 1,
-                .signal = UINT8_MAX, // Signal not available in signal map
-            },
-
-            [SOC_UART_RTS_PIN_IDX] = {
-                .default_gpio = LP_U0RTS_GPIO_NUM,
-                .iomux_func = LP_U0RTS_MUX_FUNC,
-                .input = 0,
-                .signal = UINT8_MAX, // Signal not available in signal map
-            },
-
-            [SOC_UART_CTS_PIN_IDX] = {
-                .default_gpio = LP_U0CTS_GPIO_NUM,
-                .iomux_func = LP_U0CTS_MUX_FUNC,
-                .input = 1,
-                .signal = UINT8_MAX, // Signal not available in signal map
-            },
-        },
-        .irq = ETS_LP_UART_INTR_SOURCE,
-    },
-};
-
-/**
- * UART registers to be saved during sleep retention
- *
- * Reset TXFIFO and RXFIFO
- * UART registers require set the reg_update bit to make the configuration take effect
- */
-#define N_REGS_UART(uart_num)   (((UART_ID_REG(uart_num) - UART_INT_RAW_REG(uart_num)) / 4) + 1)
-#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
-    [0] = {.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_UART_LINK(0x00), \
-                                                 UART_INT_RAW_REG(uart_num), UART_INT_RAW_REG(uart_num), \
-                                                 N_REGS_UART(uart_num), 0, 0 \
-                                                ), \
-           .owner = ENTRY(0) | ENTRY(2) }, \
-    [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \
-                                            UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \
-                                            UART_REG_UPDATE_M, 1, 0 \
-                                           ), \
-           .owner = ENTRY(0) | ENTRY(2) }, \
-    [2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \
-                                           UART_REG_UPDATE_REG(uart_num), 0x0, \
-                                           UART_REG_UPDATE_M, 1, 0 \
-                                          ), \
-           .owner = ENTRY(0) | ENTRY(2) }, \
-}
-
-static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
-static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
-
-const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
-    [0] = {
-        .regdma_entry_array = uart0_regdma_entries,
-        .array_size = ARRAY_SIZE(uart0_regdma_entries),
-    },
-    [1] = {
-        .regdma_entry_array = uart1_regdma_entries,
-        .array_size = ARRAY_SIZE(uart1_regdma_entries),
-    },
-};
diff --git a/components/soc/esp32c5/mp/gdma_periph.c b/components/soc/esp32c5/gdma_periph.c
similarity index 100%
rename from components/soc/esp32c5/mp/gdma_periph.c
rename to components/soc/esp32c5/gdma_periph.c
diff --git a/components/soc/esp32c5/mp/gpio_periph.c b/components/soc/esp32c5/gpio_periph.c
similarity index 100%
rename from components/soc/esp32c5/mp/gpio_periph.c
rename to components/soc/esp32c5/gpio_periph.c
diff --git a/components/soc/esp32c5/mp/i2s_periph.c b/components/soc/esp32c5/i2s_periph.c
similarity index 100%
rename from components/soc/esp32c5/mp/i2s_periph.c
rename to components/soc/esp32c5/i2s_periph.c
diff --git a/components/soc/esp32c5/beta3/include/modem/modem_lpcon_reg.h b/components/soc/esp32c5/include/modem/modem_lpcon_reg.h
similarity index 72%
rename from components/soc/esp32c5/beta3/include/modem/modem_lpcon_reg.h
rename to components/soc/esp32c5/include/modem/modem_lpcon_reg.h
index 75830a7f71..2e16b2e54c 100644
--- a/components/soc/esp32c5/beta3/include/modem/modem_lpcon_reg.h
+++ b/components/soc/esp32c5/include/modem/modem_lpcon_reg.h
@@ -1,18 +1,16 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_MODEM_LPCON_REG_H_
-#define _SOC_MODEM_LPCON_REG_H_
-
+#pragma once
 
+#include <stdint.h>
+#include "modem/reg_base.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "modem/reg_base.h"
-
 #define MODEM_LPCON_TEST_CONF_REG          (DR_REG_MODEM_LPCON_BASE + 0x0)
 /* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: .*/
@@ -117,13 +115,19 @@ extern "C" {
 #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V  0x1
 #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S  0
 
-#define MODEM_LPCON_I2C_MST_CLK_CONF_REG          (DR_REG_MODEM_LPCON_BASE + 0x10)
-/* MODEM_LPCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[0] ;default: 1'b0 ; */
+#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG          (DR_REG_MODEM_LPCON_BASE + 0x10)
+/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
 /*description: .*/
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M    (BIT(0))
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_M  (BIT(0))
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_V  0x1
-#define MODEM_LPCON_CLK_I2C_MST_SEL_160M_S  0
+#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO    (BIT(2))
+#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M  (BIT(2))
+#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V  0x1
+#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S  2
+/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: .*/
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE    0x00000003
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M  ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S))
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V  0x3
+#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S  0
 
 #define MODEM_LPCON_MODEM_32K_CLK_CONF_REG          (DR_REG_MODEM_LPCON_BASE + 0x14)
 /* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
@@ -252,81 +256,81 @@ extern "C" {
 #define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S  0
 
 #define MODEM_LPCON_MEM_CONF_REG          (DR_REG_MODEM_LPCON_BASE + 0x2C)
-/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */
 /*description: .*/
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD    (BIT(11))
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_M  (BIT(11))
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_V  0x1
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PD_S  11
-/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU : R/W ;bitpos:[10] ;default: 1'b0 ; */
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE    (BIT(23))
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M  (BIT(23))
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V  0x1
+#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S  23
+/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
 /*description: .*/
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU    (BIT(10))
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_M  (BIT(10))
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_V  0x1
-#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_PU_S  10
-/* MODEM_LPCON_I2C_MST_MEM_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE    0x00000007
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M  ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S))
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V  0x7
+#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S  20
+/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */
 /*description: .*/
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD    (BIT(9))
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_M  (BIT(9))
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_V  0x1
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PD_S  9
-/* MODEM_LPCON_I2C_MST_MEM_FORCE_PU : R/W ;bitpos:[8] ;default: 1'b0 ; */
+#define MODEM_LPCON_I2C_MST_MEM_FORCE    (BIT(19))
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_M  (BIT(19))
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_V  0x1
+#define MODEM_LPCON_I2C_MST_MEM_FORCE_S  19
+/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */
 /*description: .*/
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU    (BIT(8))
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_M  (BIT(8))
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_V  0x1
-#define MODEM_LPCON_I2C_MST_MEM_FORCE_PU_S  8
-/* MODEM_LPCON_BC_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+#define MODEM_LPCON_I2C_MST_MEM_MODE    0x00000007
+#define MODEM_LPCON_I2C_MST_MEM_MODE_M  ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S))
+#define MODEM_LPCON_I2C_MST_MEM_MODE_V  0x7
+#define MODEM_LPCON_I2C_MST_MEM_MODE_S  16
+/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */
 /*description: .*/
-#define MODEM_LPCON_BC_MEM_FORCE_PD    (BIT(7))
-#define MODEM_LPCON_BC_MEM_FORCE_PD_M  (BIT(7))
-#define MODEM_LPCON_BC_MEM_FORCE_PD_V  0x1
-#define MODEM_LPCON_BC_MEM_FORCE_PD_S  7
-/* MODEM_LPCON_BC_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b0 ; */
+#define MODEM_LPCON_BC_MEM_FORCE    (BIT(15))
+#define MODEM_LPCON_BC_MEM_FORCE_M  (BIT(15))
+#define MODEM_LPCON_BC_MEM_FORCE_V  0x1
+#define MODEM_LPCON_BC_MEM_FORCE_S  15
+/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */
 /*description: .*/
-#define MODEM_LPCON_BC_MEM_FORCE_PU    (BIT(6))
-#define MODEM_LPCON_BC_MEM_FORCE_PU_M  (BIT(6))
-#define MODEM_LPCON_BC_MEM_FORCE_PU_V  0x1
-#define MODEM_LPCON_BC_MEM_FORCE_PU_S  6
-/* MODEM_LPCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+#define MODEM_LPCON_BC_MEM_MODE    0x00000007
+#define MODEM_LPCON_BC_MEM_MODE_M  ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S))
+#define MODEM_LPCON_BC_MEM_MODE_V  0x7
+#define MODEM_LPCON_BC_MEM_MODE_S  12
+/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */
 /*description: .*/
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD    (BIT(5))
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD_M  (BIT(5))
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD_V  0x1
-#define MODEM_LPCON_PBUS_MEM_FORCE_PD_S  5
-/* MODEM_LPCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+#define MODEM_LPCON_PBUS_MEM_FORCE    (BIT(11))
+#define MODEM_LPCON_PBUS_MEM_FORCE_M  (BIT(11))
+#define MODEM_LPCON_PBUS_MEM_FORCE_V  0x1
+#define MODEM_LPCON_PBUS_MEM_FORCE_S  11
+/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
 /*description: .*/
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU    (BIT(4))
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU_M  (BIT(4))
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU_V  0x1
-#define MODEM_LPCON_PBUS_MEM_FORCE_PU_S  4
-/* MODEM_LPCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+#define MODEM_LPCON_PBUS_MEM_MODE    0x00000007
+#define MODEM_LPCON_PBUS_MEM_MODE_M  ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S))
+#define MODEM_LPCON_PBUS_MEM_MODE_V  0x7
+#define MODEM_LPCON_PBUS_MEM_MODE_S  8
+/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
 /*description: .*/
-#define MODEM_LPCON_AGC_MEM_FORCE_PD    (BIT(3))
-#define MODEM_LPCON_AGC_MEM_FORCE_PD_M  (BIT(3))
-#define MODEM_LPCON_AGC_MEM_FORCE_PD_V  0x1
-#define MODEM_LPCON_AGC_MEM_FORCE_PD_S  3
-/* MODEM_LPCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+#define MODEM_LPCON_AGC_MEM_FORCE    (BIT(7))
+#define MODEM_LPCON_AGC_MEM_FORCE_M  (BIT(7))
+#define MODEM_LPCON_AGC_MEM_FORCE_V  0x1
+#define MODEM_LPCON_AGC_MEM_FORCE_S  7
+/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */
 /*description: .*/
-#define MODEM_LPCON_AGC_MEM_FORCE_PU    (BIT(2))
-#define MODEM_LPCON_AGC_MEM_FORCE_PU_M  (BIT(2))
-#define MODEM_LPCON_AGC_MEM_FORCE_PU_V  0x1
-#define MODEM_LPCON_AGC_MEM_FORCE_PU_S  2
-/* MODEM_LPCON_DC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+#define MODEM_LPCON_AGC_MEM_MODE    0x00000007
+#define MODEM_LPCON_AGC_MEM_MODE_M  ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S))
+#define MODEM_LPCON_AGC_MEM_MODE_V  0x7
+#define MODEM_LPCON_AGC_MEM_MODE_S  4
+/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */
 /*description: .*/
-#define MODEM_LPCON_DC_MEM_FORCE_PD    (BIT(1))
-#define MODEM_LPCON_DC_MEM_FORCE_PD_M  (BIT(1))
-#define MODEM_LPCON_DC_MEM_FORCE_PD_V  0x1
-#define MODEM_LPCON_DC_MEM_FORCE_PD_S  1
-/* MODEM_LPCON_DC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+#define MODEM_LPCON_DC_MEM_FORCE    (BIT(3))
+#define MODEM_LPCON_DC_MEM_FORCE_M  (BIT(3))
+#define MODEM_LPCON_DC_MEM_FORCE_V  0x1
+#define MODEM_LPCON_DC_MEM_FORCE_S  3
+/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
 /*description: .*/
-#define MODEM_LPCON_DC_MEM_FORCE_PU    (BIT(0))
-#define MODEM_LPCON_DC_MEM_FORCE_PU_M  (BIT(0))
-#define MODEM_LPCON_DC_MEM_FORCE_PU_V  0x1
-#define MODEM_LPCON_DC_MEM_FORCE_PU_S  0
+#define MODEM_LPCON_DC_MEM_MODE    0x00000007
+#define MODEM_LPCON_DC_MEM_MODE_M  ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S))
+#define MODEM_LPCON_DC_MEM_MODE_V  0x7
+#define MODEM_LPCON_DC_MEM_MODE_S  0
 
 #define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG          (DR_REG_MODEM_LPCON_BASE + 0x30)
-/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h2070 ; */
+/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */
 /*description: .*/
 #define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL    0xFFFFFFFF
 #define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M  ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S))
@@ -341,19 +345,34 @@ extern "C" {
 #define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V  0xFFFFFFFF
 #define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S  0
 
-#define MODEM_LPCON_DATE_REG          (DR_REG_MODEM_LPCON_BASE + 0x38)
-/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2304240 ; */
+#define MODEM_LPCON_APB_MEM_SEL_REG          (DR_REG_MODEM_LPCON_BASE + 0x38)
+/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_LPCON_AGC_MEM_EN    (BIT(2))
+#define MODEM_LPCON_AGC_MEM_EN_M  (BIT(2))
+#define MODEM_LPCON_AGC_MEM_EN_V  0x1
+#define MODEM_LPCON_AGC_MEM_EN_S  2
+/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */
+/*description: .*/
+#define MODEM_LPCON_PBUS_MEM_EN    (BIT(1))
+#define MODEM_LPCON_PBUS_MEM_EN_M  (BIT(1))
+#define MODEM_LPCON_PBUS_MEM_EN_V  0x1
+#define MODEM_LPCON_PBUS_MEM_EN_S  1
+/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN    (BIT(0))
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M  (BIT(0))
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V  0x1
+#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S  0
+
+#define MODEM_LPCON_DATE_REG          (DR_REG_MODEM_LPCON_BASE + 0x3C)
+/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */
 /*description: .*/
 #define MODEM_LPCON_DATE    0x0FFFFFFF
 #define MODEM_LPCON_DATE_M  ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S))
 #define MODEM_LPCON_DATE_V  0xFFFFFFF
 #define MODEM_LPCON_DATE_S  0
 
-
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_MODEM_LPCON_REG_H_ */
diff --git a/components/soc/esp32c5/beta3/include/modem/modem_lpcon_struct.h b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h
similarity index 67%
rename from components/soc/esp32c5/beta3/include/modem/modem_lpcon_struct.h
rename to components/soc/esp32c5/include/modem/modem_lpcon_struct.h
index 9155a7ec31..cb8e4ff8a5 100644
--- a/components/soc/esp32c5/beta3/include/modem/modem_lpcon_struct.h
+++ b/components/soc/esp32c5/include/modem/modem_lpcon_struct.h
@@ -1,12 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
 #include <stdint.h>
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -14,7 +13,7 @@ extern "C" {
 typedef volatile struct {
     union {
         struct {
-            uint32_t clk_en                    :    1;
+            uint32_t reg_clk_en                    :    1;
             uint32_t reserved1                     :    1;
             uint32_t reserved2                     :    30;
         };
@@ -22,57 +21,58 @@ typedef volatile struct {
     } test_conf;
     union {
         struct {
-            uint32_t clk_lp_timer_sel_osc_slow :    1;
-            uint32_t clk_lp_timer_sel_osc_fast :    1;
-            uint32_t clk_lp_timer_sel_xtal     :    1;
-            uint32_t clk_lp_timer_sel_xtal32k  :    1;
-            uint32_t clk_lp_timer_div_num      :    12;
+            uint32_t reg_clk_lp_timer_sel_osc_slow :    1;
+            uint32_t reg_clk_lp_timer_sel_osc_fast :    1;
+            uint32_t reg_clk_lp_timer_sel_xtal     :    1;
+            uint32_t reg_clk_lp_timer_sel_xtal32k  :    1;
+            uint32_t reg_clk_lp_timer_div_num      :    12;
             uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } lp_timer_conf;
     union {
         struct {
-            uint32_t clk_coex_lp_sel_osc_slow  :    1;
-            uint32_t clk_coex_lp_sel_osc_fast  :    1;
-            uint32_t clk_coex_lp_sel_xtal      :    1;
-            uint32_t clk_coex_lp_sel_xtal32k   :    1;
-            uint32_t clk_coex_lp_div_num       :    12;
+            uint32_t reg_clk_coex_lp_sel_osc_slow  :    1;
+            uint32_t reg_clk_coex_lp_sel_osc_fast  :    1;
+            uint32_t reg_clk_coex_lp_sel_xtal      :    1;
+            uint32_t reg_clk_coex_lp_sel_xtal32k   :    1;
+            uint32_t reg_clk_coex_lp_div_num       :    12;
             uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } coex_lp_clk_conf;
     union {
         struct {
-            uint32_t clk_wifipwr_lp_sel_osc_slow:    1;
-            uint32_t clk_wifipwr_lp_sel_osc_fast:    1;
-            uint32_t clk_wifipwr_lp_sel_xtal   :    1;
-            uint32_t clk_wifipwr_lp_sel_xtal32k:    1;
-            uint32_t clk_wifipwr_lp_div_num    :    12;
+            uint32_t reg_clk_wifipwr_lp_sel_osc_slow:    1;
+            uint32_t reg_clk_wifipwr_lp_sel_osc_fast:    1;
+            uint32_t reg_clk_wifipwr_lp_sel_xtal   :    1;
+            uint32_t reg_clk_wifipwr_lp_sel_xtal32k:    1;
+            uint32_t reg_clk_wifipwr_lp_div_num    :    12;
             uint32_t reserved16                    :    16;
         };
         uint32_t val;
     } wifi_lp_clk_conf;
     union {
         struct {
-            uint32_t clk_i2c_mst_sel_160m      :    1;
-            uint32_t reserved1                     :    31;
+            uint32_t reg_clk_modem_aon_force       :    2;
+            uint32_t reg_modem_pwr_clk_src_fo      :    1;
+            uint32_t reserved3                     :    29;
         };
         uint32_t val;
-    } i2c_mst_clk_conf;
+    } modem_src_clk_conf;
     union {
         struct {
-            uint32_t clk_modem_32k_sel         :    2;
+            uint32_t reg_clk_modem_32k_sel         :    2;
             uint32_t reserved2                     :    30;
         };
         uint32_t val;
     } modem_32k_clk_conf;
     union {
         struct {
-            uint32_t clk_wifipwr_en            :    1;
-            uint32_t clk_coex_en               :    1;
-            uint32_t clk_i2c_mst_en            :    1;
-            uint32_t clk_lp_timer_en           :    1;
+            uint32_t reg_clk_wifipwr_en            :    1;
+            uint32_t reg_clk_coex_en               :    1;
+            uint32_t reg_clk_i2c_mst_en            :    1;
+            uint32_t reg_clk_lp_timer_en           :    1;
             uint32_t reserved4                     :    1;
             uint32_t reserved5                     :    1;
             uint32_t reserved6                     :    1;
@@ -106,11 +106,11 @@ typedef volatile struct {
     } clk_conf;
     union {
         struct {
-            uint32_t clk_wifipwr_fo            :    1;
-            uint32_t clk_coex_fo               :    1;
-            uint32_t clk_i2c_mst_fo            :    1;
-            uint32_t clk_lp_timer_fo           :    1;
-            uint32_t clk_fe_mem_fo             :    1;
+            uint32_t reg_clk_wifipwr_fo            :    1;
+            uint32_t reg_clk_coex_fo               :    1;
+            uint32_t reg_clk_i2c_mst_fo            :    1;
+            uint32_t reg_clk_lp_timer_fo           :    1;
+            uint32_t reg_clk_fe_mem_fo             :    1;
             uint32_t reserved5                     :    1;
             uint32_t reserved6                     :    1;
             uint32_t reserved7                     :    1;
@@ -144,19 +144,19 @@ typedef volatile struct {
     union {
         struct {
             uint32_t reserved0                     :    16;
-            uint32_t clk_wifipwr_st_map        :    4;
-            uint32_t clk_coex_st_map           :    4;
-            uint32_t clk_i2c_mst_st_map        :    4;
-            uint32_t clk_lp_apb_st_map         :    4;
+            uint32_t reg_clk_wifipwr_st_map        :    4;
+            uint32_t reg_clk_coex_st_map           :    4;
+            uint32_t reg_clk_i2c_mst_st_map        :    4;
+            uint32_t reg_clk_lp_apb_st_map         :    4;
         };
         uint32_t val;
     } clk_conf_power_st;
     union {
         struct {
-            uint32_t rst_wifipwr               :    1;
-            uint32_t rst_coex                  :    1;
-            uint32_t rst_i2c_mst               :    1;
-            uint32_t rst_lp_timer              :    1;
+            uint32_t reg_rst_wifipwr               :    1;
+            uint32_t reg_rst_coex                  :    1;
+            uint32_t reg_rst_i2c_mst               :    1;
+            uint32_t reg_rst_lp_timer              :    1;
             uint32_t reserved4                     :    1;
             uint32_t reserved5                     :    1;
             uint32_t reserved6                     :    1;
@@ -190,30 +190,25 @@ typedef volatile struct {
     } rst_conf;
     union {
         struct {
-            uint32_t modem_pwr_tick_target     :    6;
+            uint32_t reg_modem_pwr_tick_target     :    6;
             uint32_t reserved6                     :    26;
         };
         uint32_t val;
     } tick_conf;
     union {
         struct {
-            uint32_t dc_mem_force_pu           :    1;
-            uint32_t dc_mem_force_pd           :    1;
-            uint32_t agc_mem_force_pu          :    1;
-            uint32_t agc_mem_force_pd          :    1;
-            uint32_t pbus_mem_force_pu         :    1;
-            uint32_t pbus_mem_force_pd         :    1;
-            uint32_t bc_mem_force_pu           :    1;
-            uint32_t bc_mem_force_pd           :    1;
-            uint32_t i2c_mst_mem_force_pu      :    1;
-            uint32_t i2c_mst_mem_force_pd      :    1;
-            uint32_t chan_freq_mem_force_pu    :    1;
-            uint32_t chan_freq_mem_force_pd    :    1;
-            uint32_t reserved12                    :    8;
-            uint32_t reserved20                    :    1;
-            uint32_t reserved21                    :    1;
-            uint32_t reserved22                    :    1;
-            uint32_t reserved23                    :    1;
+            uint32_t reg_dc_mem_mode               :    3;
+            uint32_t reg_dc_mem_force              :    1;
+            uint32_t reg_agc_mem_mode              :    3;
+            uint32_t reg_agc_mem_force             :    1;
+            uint32_t reg_pbus_mem_mode             :    3;
+            uint32_t reg_pbus_mem_force            :    1;
+            uint32_t reg_bc_mem_mode               :    3;
+            uint32_t reg_bc_mem_force              :    1;
+            uint32_t reg_i2c_mst_mem_mode          :    3;
+            uint32_t reg_i2c_mst_mem_force         :    1;
+            uint32_t reg_chan_freq_mem_mode        :    3;
+            uint32_t reg_chan_freq_mem_force       :    1;
             uint32_t reserved24                    :    1;
             uint32_t reserved25                    :    1;
             uint32_t reserved26                    :    1;
@@ -229,7 +224,16 @@ typedef volatile struct {
     uint32_t mem_rf2_aux_ctrl;
     union {
         struct {
-            uint32_t date                      :    28;
+            uint32_t reg_chan_freq_mem_en          :    1;
+            uint32_t reg_pbus_mem_en               :    1;
+            uint32_t reg_agc_mem_en                :    1;
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } apb_mem_sel;
+    union {
+        struct {
+            uint32_t reg_date                      :    28;
             uint32_t reserved28                    :    4;
         };
         uint32_t val;
@@ -239,7 +243,7 @@ typedef volatile struct {
 extern modem_lpcon_dev_t MODEM_LPCON;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(modem_lpcon_dev_t) == 0x3c, "Invalid size of modem_lpcon_dev_t structure");
+_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure");
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32c5/beta3/include/modem/modem_syscon_reg.h b/components/soc/esp32c5/include/modem/modem_syscon_reg.h
similarity index 84%
rename from components/soc/esp32c5/beta3/include/modem/modem_syscon_reg.h
rename to components/soc/esp32c5/include/modem/modem_syscon_reg.h
index e150c13f2e..765cb3a00c 100644
--- a/components/soc/esp32c5/beta3/include/modem/modem_syscon_reg.h
+++ b/components/soc/esp32c5/include/modem/modem_syscon_reg.h
@@ -1,19 +1,53 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_MODEM_SYSCON_REG_H_
-#define _SOC_MODEM_SYSCON_REG_H_
-
+#pragma once
 
+#include <stdint.h>
+#include "modem/reg_base.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "reg_base.h"
-
 #define MODEM_SYSCON_TEST_CONF_REG          (DR_REG_MODEM_SYSCON_BASE + 0x0)
+/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: .*/
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE    (BIT(8))
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M  (BIT(8))
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V  0x1
+#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S  8
+/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10    (BIT(7))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M  (BIT(7))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V  0x1
+#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S  7
+/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20    (BIT(6))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M  (BIT(6))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V  0x1
+#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S  6
+/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40    (BIT(5))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M  (BIT(5))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V  0x1
+#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S  5
+/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80    (BIT(4))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M  (BIT(4))
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V  0x1
+#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S  4
+/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH    (BIT(3))
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M  (BIT(3))
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V  0x1
+#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S  3
 /* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */
 /*description: .*/
 #define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI    (BIT(2))
@@ -100,6 +134,42 @@ extern "C" {
 #define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M  (BIT(21))
 #define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V  0x1
 #define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S  21
+/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M    (BIT(12))
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M  (BIT(12))
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V  0x1
+#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S  12
+/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA    (BIT(11))
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M  (BIT(11))
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V  0x1
+#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S  11
+/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA    (BIT(10))
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M  (BIT(10))
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V  0x1
+#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S  10
+/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA    (BIT(9))
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M  (BIT(9))
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V  0x1
+#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S  9
+/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */
+/*description: .*/
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM    0x000000FF
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M  ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S))
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V  0xFF
+#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S  1
+/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA    (BIT(0))
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M  (BIT(0))
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V  0x1
+#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S  0
 
 #define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG          (DR_REG_MODEM_SYSCON_BASE + 0x8)
 /* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */
@@ -268,6 +338,12 @@ extern "C" {
 #define MODEM_SYSCON_RST_ZBMAC_M  (BIT(24))
 #define MODEM_SYSCON_RST_ZBMAC_V  0x1
 #define MODEM_SYSCON_RST_ZBMAC_S  24
+/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_ZBMAC_APB    (BIT(23))
+#define MODEM_SYSCON_RST_ZBMAC_APB_M  (BIT(23))
+#define MODEM_SYSCON_RST_ZBMAC_APB_V  0x1
+#define MODEM_SYSCON_RST_ZBMAC_APB_S  23
 /* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */
 /*description: .*/
 #define MODEM_SYSCON_RST_ETM    (BIT(22))
@@ -484,7 +560,7 @@ extern "C" {
 #define MODEM_SYSCON_WIFI_BB_CFG_S  0
 
 #define MODEM_SYSCON_MEM_RF1_CONF_REG          (DR_REG_MODEM_SYSCON_BASE + 0x1C)
-/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h2070 ; */
+/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */
 /*description: .*/
 #define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL    0xFFFFFFFF
 #define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M  ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S))
@@ -492,7 +568,7 @@ extern "C" {
 #define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S  0
 
 #define MODEM_SYSCON_MEM_RF2_CONF_REG          (DR_REG_MODEM_SYSCON_BASE + 0x20)
-/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */
 /*description: .*/
 #define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL    0xFFFFFFFF
 #define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M  ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S))
@@ -500,18 +576,13 @@ extern "C" {
 #define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S  0
 
 #define MODEM_SYSCON_DATE_REG          (DR_REG_MODEM_SYSCON_BASE + 0x24)
-/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2304170 ; */
+/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2312050 ; */
 /*description: .*/
 #define MODEM_SYSCON_DATE    0x0FFFFFFF
 #define MODEM_SYSCON_DATE_M  ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S))
 #define MODEM_SYSCON_DATE_V  0xFFFFFFF
 #define MODEM_SYSCON_DATE_S  0
 
-
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_MODEM_SYSCON_REG_H_ */
diff --git a/components/soc/esp32c5/include/modem/modem_syscon_struct.h b/components/soc/esp32c5/include/modem/modem_syscon_struct.h
new file mode 100644
index 0000000000..b7086ad37a
--- /dev/null
+++ b/components/soc/esp32c5/include/modem/modem_syscon_struct.h
@@ -0,0 +1,174 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;
+            uint32_t reg_modem_ant_force_sel_bt    :    1;
+            uint32_t reg_modem_ant_force_sel_wifi  :    1;
+            uint32_t reg_fpga_debug_clkswitch      :    1;
+            uint32_t reg_fpga_debug_clk80          :    1;
+            uint32_t reg_fpga_debug_clk40          :    1;
+            uint32_t reg_fpga_debug_clk20          :    1;
+            uint32_t reg_fpga_debug_clk10          :    1;
+            uint32_t reg_modem_mem_mode_force      :    1;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } test_conf;
+    union {
+        struct {
+            uint32_t reg_pwdet_sar_clock_ena       :    1;
+            uint32_t reg_pwdet_clk_div_num         :    8;
+            uint32_t reg_clk_tx_dac_inv_ena        :    1;
+            uint32_t reg_clk_rx_adc_inv_ena        :    1;
+            uint32_t reg_clk_pwdet_adc_inv_ena     :    1;
+            uint32_t reg_clk_i2c_mst_sel_160m      :    1;
+            uint32_t reserved13                    :    8;
+            uint32_t reg_clk_data_dump_mux         :    1;
+            uint32_t reg_clk_etm_en                :    1;
+            uint32_t reg_clk_zb_apb_en             :    1;
+            uint32_t reg_clk_zbmac_en              :    1;
+            uint32_t reg_clk_modem_sec_ecb_en      :    1;
+            uint32_t reg_clk_modem_sec_ccm_en      :    1;
+            uint32_t reg_clk_modem_sec_bah_en      :    1;
+            uint32_t reg_clk_modem_sec_apb_en      :    1;
+            uint32_t reg_clk_modem_sec_en          :    1;
+            uint32_t reg_clk_ble_timer_en          :    1;
+            uint32_t reg_clk_data_dump_en          :    1;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t reg_clk_wifibb_fo             :    1;
+            uint32_t reg_clk_wifimac_fo            :    1;
+            uint32_t reg_clk_wifi_apb_fo           :    1;
+            uint32_t reg_clk_fe_fo                 :    1;
+            uint32_t reg_clk_fe_apb_fo             :    1;
+            uint32_t reg_clk_btbb_fo               :    1;
+            uint32_t reg_clk_btmac_fo              :    1;
+            uint32_t reg_clk_bt_apb_fo             :    1;
+            uint32_t reg_clk_zbmac_fo              :    1;
+            uint32_t reg_clk_zbmac_apb_fo          :    1;
+            uint32_t reserved10                    :    13;
+            uint32_t reserved23                    :    1;
+            uint32_t reserved24                    :    1;
+            uint32_t reserved25                    :    1;
+            uint32_t reserved26                    :    1;
+            uint32_t reserved27                    :    1;
+            uint32_t reg_clk_etm_fo                :    1;
+            uint32_t reg_clk_modem_sec_fo          :    1;
+            uint32_t reg_clk_ble_timer_fo          :    1;
+            uint32_t reg_clk_data_dump_fo          :    1;
+        };
+        uint32_t val;
+    } clk_conf_force_on;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;
+            uint32_t reg_clk_zb_st_map             :    4;
+            uint32_t reg_clk_fe_st_map             :    4;
+            uint32_t reg_clk_bt_st_map             :    4;
+            uint32_t reg_clk_wifi_st_map           :    4;
+            uint32_t reg_clk_modem_peri_st_map     :    4;
+            uint32_t reg_clk_modem_apb_st_map      :    4;
+        };
+        uint32_t val;
+    } clk_conf_power_st;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t reserved1                     :    1;
+            uint32_t reserved2                     :    1;
+            uint32_t reserved3                     :    1;
+            uint32_t reserved4                     :    1;
+            uint32_t reserved5                     :    1;
+            uint32_t reserved6                     :    1;
+            uint32_t reserved7                     :    1;
+            uint32_t reg_rst_wifibb                :    1;
+            uint32_t reg_rst_wifimac               :    1;
+            uint32_t reg_rst_fe_pwdet_adc          :    1;
+            uint32_t reg_rst_fe_dac                :    1;
+            uint32_t reg_rst_fe_adc                :    1;
+            uint32_t reg_rst_fe_ahb                :    1;
+            uint32_t reg_rst_fe                    :    1;
+            uint32_t reg_rst_btmac_apb             :    1;
+            uint32_t reg_rst_btmac                 :    1;
+            uint32_t reg_rst_btbb_apb              :    1;
+            uint32_t reg_rst_btbb                  :    1;
+            uint32_t reserved19                    :    3;
+            uint32_t reg_rst_etm                   :    1;
+            uint32_t reg_rst_zbmac_apb             :    1;
+            uint32_t reg_rst_zbmac                 :    1;
+            uint32_t reg_rst_modem_ecb             :    1;
+            uint32_t reg_rst_modem_ccm             :    1;
+            uint32_t reg_rst_modem_bah             :    1;
+            uint32_t reserved28                    :    1;
+            uint32_t reg_rst_modem_sec             :    1;
+            uint32_t reg_rst_ble_timer             :    1;
+            uint32_t reg_rst_data_dump             :    1;
+        };
+        uint32_t val;
+    } modem_rst_conf;
+    union {
+        struct {
+            uint32_t reg_clk_wifibb_22m_en         :    1;
+            uint32_t reg_clk_wifibb_40m_en         :    1;
+            uint32_t reg_clk_wifibb_44m_en         :    1;
+            uint32_t reg_clk_wifibb_80m_en         :    1;
+            uint32_t reg_clk_wifibb_40x_en         :    1;
+            uint32_t reg_clk_wifibb_80x_en         :    1;
+            uint32_t reg_clk_wifibb_40x1_en        :    1;
+            uint32_t reg_clk_wifibb_80x1_en        :    1;
+            uint32_t reg_clk_wifibb_160x1_en       :    1;
+            uint32_t reg_clk_wifimac_en            :    1;
+            uint32_t reg_clk_wifi_apb_en           :    1;
+            uint32_t reg_clk_fe_20m_en             :    1;
+            uint32_t reg_clk_fe_40m_en             :    1;
+            uint32_t reg_clk_fe_80m_en             :    1;
+            uint32_t reg_clk_fe_160m_en            :    1;
+            uint32_t reg_clk_fe_apb_en             :    1;
+            uint32_t reg_clk_bt_apb_en             :    1;
+            uint32_t reg_clk_btbb_en               :    1;
+            uint32_t reg_clk_btmac_en              :    1;
+            uint32_t reg_clk_fe_pwdet_adc_en       :    1;
+            uint32_t reg_clk_fe_adc_en             :    1;
+            uint32_t reg_clk_fe_dac_en             :    1;
+            uint32_t reserved22                    :    1;
+            uint32_t reserved23                    :    1;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } clk_conf1;
+    uint32_t wifi_bb_cfg;
+    uint32_t mem_rf1_conf;
+    uint32_t mem_rf2_conf;
+    union {
+        struct {
+            uint32_t reg_date                      :    28;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } date;
+} modem_syscon_dev_t;
+
+extern modem_syscon_dev_t MODEM_SYSCON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/include/modem/reg_base.h b/components/soc/esp32c5/include/modem/reg_base.h
new file mode 100644
index 0000000000..37b441740c
--- /dev/null
+++ b/components/soc/esp32c5/include/modem/reg_base.h
@@ -0,0 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#define DR_REG_MODEM_SYSCON_BASE  0x600A9C00
+#define DR_REG_MODEM_LPCON_BASE   0x600AF000
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index e5e3b806d2..e36ec0f749 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -3,10 +3,774 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
-if IDF_TARGET_ESP32C5_BETA3_VERSION
-    source "$IDF_PATH/components/soc/esp32c5/include/soc/../../beta3/include/soc/Kconfig.soc_caps.in"
-endif
+config SOC_UART_SUPPORTED
+    bool
+    default y
 
-if IDF_TARGET_ESP32C5_MP_VERSION
-    source "$IDF_PATH/components/soc/esp32c5/include/soc/../../mp/include/soc/Kconfig.soc_caps.in"
-endif
+config SOC_GDMA_SUPPORTED
+    bool
+    default y
+
+config SOC_AHB_GDMA_SUPPORTED
+    bool
+    default y
+
+config SOC_GPTIMER_SUPPORTED
+    bool
+    default y
+
+config SOC_PCNT_SUPPORTED
+    bool
+    default y
+
+config SOC_MCPWM_SUPPORTED
+    bool
+    default y
+
+config SOC_ASYNC_MEMCPY_SUPPORTED
+    bool
+    default y
+
+config SOC_SUPPORTS_SECURE_DL_MODE
+    bool
+    default y
+
+config SOC_EFUSE_KEY_PURPOSE_FIELD
+    bool
+    default y
+
+config SOC_EFUSE_SUPPORTED
+    bool
+    default y
+
+config SOC_RTC_FAST_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_RTC_MEM_SUPPORTED
+    bool
+    default y
+
+config SOC_I2S_SUPPORTED
+    bool
+    default y
+
+config SOC_RMT_SUPPORTED
+    bool
+    default y
+
+config SOC_GPSPI_SUPPORTED
+    bool
+    default y
+
+config SOC_LEDC_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_SUPPORTED
+    bool
+    default y
+
+config SOC_AES_SUPPORTED
+    bool
+    default y
+
+config SOC_MPI_SUPPORTED
+    bool
+    default y
+
+config SOC_SHA_SUPPORTED
+    bool
+    default y
+
+config SOC_RSA_SUPPORTED
+    bool
+    default y
+
+config SOC_HMAC_SUPPORTED
+    bool
+    default y
+
+config SOC_DIG_SIGN_SUPPORTED
+    bool
+    default y
+
+config SOC_ECC_SUPPORTED
+    bool
+    default y
+
+config SOC_ECC_EXTENDED_MODES_SUPPORTED
+    bool
+    default y
+
+config SOC_FLASH_ENC_SUPPORTED
+    bool
+    default y
+
+config SOC_SECURE_BOOT_SUPPORTED
+    bool
+    default y
+
+config SOC_SPI_FLASH_SUPPORTED
+    bool
+    default y
+
+config SOC_ECDSA_SUPPORTED
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_40M
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_48M
+    bool
+    default y
+
+config SOC_AES_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_AES_GDMA
+    bool
+    default y
+
+config SOC_AES_SUPPORT_AES_128
+    bool
+    default y
+
+config SOC_AES_SUPPORT_AES_256
+    bool
+    default y
+
+config SOC_ADC_PERIPH_NUM
+    int
+    default 1
+
+config SOC_ADC_MAX_CHANNEL_NUM
+    int
+    default 7
+
+config SOC_SHARED_IDCACHE_SUPPORTED
+    bool
+    default y
+
+config SOC_CACHE_FREEZE_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_CORES_NUM
+    int
+    default 1
+
+config SOC_CPU_INTR_NUM
+    int
+    default 32
+
+config SOC_CPU_HAS_FLEXIBLE_INTC
+    bool
+    default y
+
+config SOC_INT_CLIC_SUPPORTED
+    bool
+    default y
+
+config SOC_INT_HW_NESTED_SUPPORTED
+    bool
+    default y
+
+config SOC_BRANCH_PREDICTOR_SUPPORTED
+    bool
+    default y
+
+config SOC_CPU_BREAKPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINTS_NUM
+    int
+    default 4
+
+config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
+    hex
+    default 0x100
+
+config SOC_CPU_HAS_PMA
+    bool
+    default y
+
+config SOC_CPU_IDRAM_SPLIT_USING_PMP
+    bool
+    default y
+
+config SOC_DS_SIGNATURE_MAX_BIT_LEN
+    int
+    default 3072
+
+config SOC_DS_KEY_PARAM_MD_IV_LENGTH
+    int
+    default 16
+
+config SOC_DS_KEY_CHECK_MAX_WAIT_US
+    int
+    default 1100
+
+config SOC_DMA_CAN_ACCESS_FLASH
+    bool
+    default y
+
+config SOC_AHB_GDMA_VERSION
+    int
+    default 2
+
+config SOC_GDMA_NUM_GROUPS_MAX
+    int
+    default 1
+
+config SOC_GDMA_PAIRS_PER_GROUP_MAX
+    int
+    default 3
+
+config SOC_GPIO_PORT
+    int
+    default 1
+
+config SOC_GPIO_PIN_COUNT
+    int
+    default 29
+
+config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
+    bool
+    default y
+
+config SOC_GPIO_IN_RANGE_MAX
+    int
+    default 28
+
+config SOC_GPIO_OUT_RANGE_MAX
+    int
+    default 28
+
+config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
+    int
+    default 0
+
+config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
+    hex
+    default 0x0000000001FFFF00
+
+config SOC_GPIO_SUPPORT_FORCE_HOLD
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
+    bool
+    default y
+
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
+config SOC_RTCIO_PIN_COUNT
+    int
+    default 0
+
+config SOC_I2C_NUM
+    int
+    default 1
+
+config SOC_HP_I2C_NUM
+    int
+    default 1
+
+config SOC_I2S_NUM
+    int
+    default 1
+
+config SOC_I2S_HW_VERSION_2
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_TX_SYNC_CNT
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_XTAL
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PLL_F240M
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PCM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM_TX
+    bool
+    default y
+
+config SOC_I2S_PDM_MAX_TX_LINES
+    int
+    default 2
+
+config SOC_I2S_SUPPORTS_TDM
+    bool
+    default y
+
+config SOC_I2S_TDM_FULL_DATA_WIDTH
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_SUPPORT_XTAL_CLOCK
+    bool
+    default y
+
+config SOC_LEDC_CHANNEL_NUM
+    int
+    default 6
+
+config SOC_LEDC_TIMER_BIT_WIDTH
+    int
+    default 20
+
+config SOC_LEDC_SUPPORT_FADE_STOP
+    bool
+    default y
+
+config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
+    bool
+    default y
+
+config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
+    int
+    default 16
+
+config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
+    int
+    default 10
+
+config SOC_MMU_PERIPH_NUM
+    int
+    default 1
+
+config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
+    int
+    default 1
+
+config SOC_MMU_DI_VADDR_SHARED
+    bool
+    default y
+
+config SOC_PCNT_GROUPS
+    int
+    default 1
+
+config SOC_PCNT_UNITS_PER_GROUP
+    int
+    default 4
+
+config SOC_PCNT_CHANNELS_PER_UNIT
+    int
+    default 2
+
+config SOC_PCNT_THRES_POINT_PER_UNIT
+    int
+    default 2
+
+config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
+    bool
+    default y
+
+config SOC_PCNT_SUPPORT_CLEAR_SIGNAL
+    bool
+    default y
+
+config SOC_RMT_GROUPS
+    int
+    default 1
+
+config SOC_RMT_TX_CANDIDATES_PER_GROUP
+    int
+    default 2
+
+config SOC_RMT_RX_CANDIDATES_PER_GROUP
+    int
+    default 2
+
+config SOC_RMT_CHANNELS_PER_GROUP
+    int
+    default 4
+
+config SOC_RMT_MEM_WORDS_PER_CHANNEL
+    int
+    default 48
+
+config SOC_RMT_SUPPORT_RX_PINGPONG
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_RX_DEMODULATION
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_ASYNC_STOP
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_LOOP_COUNT
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_SYNCHRO
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
+    bool
+    default y
+
+config SOC_RMT_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_MCPWM_GROUPS
+    int
+    default 1
+
+config SOC_MCPWM_TIMERS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_OPERATORS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_COMPARATORS_PER_OPERATOR
+    int
+    default 2
+
+config SOC_MCPWM_GENERATORS_PER_OPERATOR
+    int
+    default 2
+
+config SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR
+    int
+    default 2
+
+config SOC_MCPWM_TRIGGERS_PER_OPERATOR
+    int
+    default 2
+
+config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
+    bool
+    default y
+
+config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
+    int
+    default 3
+
+config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
+    int
+    default 3
+
+config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
+    bool
+    default y
+
+config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
+    bool
+    default y
+
+config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
+    bool
+    default y
+
+config SOC_MPI_MEM_BLOCKS_NUM
+    int
+    default 4
+
+config SOC_MPI_OPERATIONS_NUM
+    int
+    default 3
+
+config SOC_RSA_MAX_BIT_LEN
+    int
+    default 3072
+
+config SOC_SHA_DMA_MAX_BUFFER_SIZE
+    int
+    default 3968
+
+config SOC_SHA_SUPPORT_DMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_RESUME
+    bool
+    default y
+
+config SOC_SHA_GDMA
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA1
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA224
+    bool
+    default y
+
+config SOC_SHA_SUPPORT_SHA256
+    bool
+    default y
+
+config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
+    bool
+    default y
+
+config SOC_SPI_PERIPH_NUM
+    int
+    default 2
+
+config SOC_SPI_MAX_CS_NUM
+    int
+    default 6
+
+config SOC_SPI_MAXIMUM_BUFFER_SIZE
+    int
+    default 64
+
+config SOC_SPI_SUPPORT_DDRCLK
+    bool
+    default y
+
+config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CD_SIG
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_SLAVE_HD_VER2
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CLK_XTAL
+    bool
+    default y
+
+config SOC_MEMSPI_IS_INDEPENDENT
+    bool
+    default y
+
+config SOC_SPI_MAX_PRE_DIVIDER
+    int
+    default 16
+
+config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
+    bool
+    default y
+
+config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
+    bool
+    default y
+
+config SOC_SYSTIMER_COUNTER_NUM
+    int
+    default 2
+
+config SOC_SYSTIMER_ALARM_NUM
+    int
+    default 3
+
+config SOC_SYSTIMER_BIT_WIDTH_LO
+    int
+    default 32
+
+config SOC_SYSTIMER_BIT_WIDTH_HI
+    int
+    default 20
+
+config SOC_SYSTIMER_FIXED_DIVIDER
+    bool
+    default y
+
+config SOC_SYSTIMER_SUPPORT_RC_FAST
+    bool
+    default y
+
+config SOC_SYSTIMER_INT_LEVEL
+    bool
+    default y
+
+config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
+    bool
+    default y
+
+config SOC_TIMER_GROUPS
+    int
+    default 2
+
+config SOC_TIMER_GROUP_TIMERS_PER_GROUP
+    int
+    default 1
+
+config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
+    int
+    default 54
+
+config SOC_TIMER_GROUP_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_TIMER_GROUP_TOTAL_TIMERS
+    int
+    default 2
+
+config SOC_EFUSE_ECDSA_KEY
+    bool
+    default y
+
+config SOC_SECURE_BOOT_V2_RSA
+    bool
+    default y
+
+config SOC_SECURE_BOOT_V2_ECC
+    bool
+    default y
+
+config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
+    int
+    default 3
+
+config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
+    bool
+    default y
+
+config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
+    bool
+    default y
+
+config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
+    int
+    default 64
+
+config SOC_FLASH_ENCRYPTION_XTS_AES
+    bool
+    default y
+
+config SOC_FLASH_ENCRYPTION_XTS_AES_128
+    bool
+    default y
+
+config SOC_UART_NUM
+    int
+    default 3
+
+config SOC_UART_HP_NUM
+    int
+    default 2
+
+config SOC_UART_LP_NUM
+    int
+    default 1
+
+config SOC_UART_FIFO_LEN
+    int
+    default 128
+
+config SOC_LP_UART_FIFO_LEN
+    int
+    default 16
+
+config SOC_UART_SUPPORT_XTAL_CLK
+    bool
+    default y
+
+config SOC_PM_SUPPORT_MODEM_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_XTAL32K_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RC32K_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RC_FAST_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_VDDSDIO_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_TOP_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_HP_AON_PD
+    bool
+    default y
+
+config SOC_PM_SUPPORT_RTC_PERIPH_PD
+    bool
+    default y
+
+config SOC_MODEM_CLOCK_IS_INDEPENDENT
+    bool
+    default y
+
+config SOC_CLK_XTAL32K_SUPPORTED
+    bool
+    default y
+
+config SOC_CLK_OSC_SLOW_SUPPORTED
+    bool
+    default y
+
+config SOC_CLK_RC32K_SUPPORTED
+    bool
+    default y
+
+config SOC_RCC_IS_INDEPENDENT
+    bool
+    default y
diff --git a/components/soc/esp32c5/beta3/include/soc/adc_channel.h b/components/soc/esp32c5/include/soc/adc_channel.h
similarity index 82%
rename from components/soc/esp32c5/beta3/include/soc/adc_channel.h
rename to components/soc/esp32c5/include/soc/adc_channel.h
index dcdfb8633b..0f7c05d929 100644
--- a/components/soc/esp32c5/beta3/include/soc/adc_channel.h
+++ b/components/soc/esp32c5/include/soc/adc_channel.h
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+// TODO: [ESP32-C5] IDF-8701 Check the channel
 #define ADC1_GPIO0_CHANNEL      0
 #define ADC1_CHANNEL_0_GPIO_NUM 0
 
diff --git a/components/soc/esp32c5/mp/include/soc/aes_reg.h b/components/soc/esp32c5/include/soc/aes_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/aes_reg.h
rename to components/soc/esp32c5/include/soc/aes_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/aes_struct.h b/components/soc/esp32c5/include/soc/aes_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/aes_struct.h
rename to components/soc/esp32c5/include/soc/aes_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/ahb_dma_reg.h b/components/soc/esp32c5/include/soc/ahb_dma_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ahb_dma_reg.h
rename to components/soc/esp32c5/include/soc/ahb_dma_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/ahb_dma_struct.h b/components/soc/esp32c5/include/soc/ahb_dma_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ahb_dma_struct.h
rename to components/soc/esp32c5/include/soc/ahb_dma_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/include/soc/apb_saradc_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/apb_saradc_reg.h
rename to components/soc/esp32c5/include/soc/apb_saradc_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/include/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/apb_saradc_struct.h
rename to components/soc/esp32c5/include/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/assist_debug_reg.h b/components/soc/esp32c5/include/soc/assist_debug_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/assist_debug_reg.h
rename to components/soc/esp32c5/include/soc/assist_debug_reg.h
index 4b7e6b6ff5..042490974b 100644
--- a/components/soc/esp32c5/mp/include/soc/assist_debug_reg.h
+++ b/components/soc/esp32c5/include/soc/assist_debug_reg.h
@@ -115,7 +115,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
+ *  DBUS busy monitor enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
@@ -295,7 +295,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
+ *  DBUS busy monitor interrupt enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
diff --git a/components/soc/esp32c5/mp/include/soc/assist_debug_struct.h b/components/soc/esp32c5/include/soc/assist_debug_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/assist_debug_struct.h
rename to components/soc/esp32c5/include/soc/assist_debug_struct.h
index 243b6959aa..ca55d0cb8f 100644
--- a/components/soc/esp32c5/mp/include/soc/assist_debug_struct.h
+++ b/components/soc/esp32c5/include/soc/assist_debug_struct.h
@@ -83,7 +83,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_ena:1;
         /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
+         *  DBUS busy monitor enable
          */
         uint32_t core_0_dram0_exception_monitor_ena:1;
         uint32_t reserved_12:20;
@@ -372,7 +372,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_intr_ena:1;
         /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
+         *  DBUS busy monitor interrupt enable
          */
         uint32_t core_0_dram0_exception_monitor_intr_ena:1;
         uint32_t reserved_12:20;
@@ -441,7 +441,7 @@ typedef union {
 } assist_debug_core_0_intr_clr_reg_t;
 
 
-/** Group: pc reording configuration register */
+/** Group: pc recording configuration register */
 /** Type of core_0_rcd_en register
  *  HP CPU PC logging enable register
  */
@@ -465,7 +465,7 @@ typedef union {
 } assist_debug_core_0_rcd_en_reg_t;
 
 
-/** Group: pc reording status register */
+/** Group: pc recording status register */
 /** Type of core_0_rcd_pdebugpc register
  *  PC logging register
  */
@@ -493,7 +493,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugsp_reg_t;
 
 
-/** Group: exception monitor regsiter */
+/** Group: exception monitor register */
 /** Type of core_0_iram0_exception_monitor_0 register
  *  exception monitor status register0
  */
diff --git a/components/soc/esp32c5/mp/include/soc/bitscrambler_reg.h b/components/soc/esp32c5/include/soc/bitscrambler_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/bitscrambler_reg.h
rename to components/soc/esp32c5/include/soc/bitscrambler_reg.h
index a78ec1de6a..405f7d7309 100644
--- a/components/soc/esp32c5/mp/include/soc/bitscrambler_reg.h
+++ b/components/soc/esp32c5/include/soc/bitscrambler_reg.h
@@ -216,7 +216,7 @@ extern "C" {
 #define BITSCRAMBLER_TX_COND_MODE_S  4
 /** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
  *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
+ *  by reset, 1: fetch by instructions
  */
 #define BITSCRAMBLER_TX_FETCH_MODE    (BIT(5))
 #define BITSCRAMBLER_TX_FETCH_MODE_M  (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
@@ -291,7 +291,7 @@ extern "C" {
 #define BITSCRAMBLER_RX_COND_MODE_S  4
 /** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
  *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
+ *  by reset, 1: fetch by instructions
  */
 #define BITSCRAMBLER_RX_FETCH_MODE    (BIT(5))
 #define BITSCRAMBLER_RX_FETCH_MODE_M  (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
diff --git a/components/soc/esp32c5/mp/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/include/soc/bitscrambler_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/bitscrambler_struct.h
rename to components/soc/esp32c5/include/soc/bitscrambler_struct.h
index 44c3445851..7bf84e8264 100644
--- a/components/soc/esp32c5/mp/include/soc/bitscrambler_struct.h
+++ b/components/soc/esp32c5/include/soc/bitscrambler_struct.h
@@ -208,7 +208,7 @@ typedef union {
         uint32_t tx_cond_mode:1;
         /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
          *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
+         *  by reset, 1: fetch by instructions
          */
         uint32_t tx_fetch_mode:1;
         /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
@@ -261,7 +261,7 @@ typedef union {
         uint32_t rx_cond_mode:1;
         /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
          *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
+         *  by reset, 1: fetch by instructions
          */
         uint32_t rx_fetch_mode:1;
         /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
diff --git a/components/soc/esp32c5/mp/include/soc/cache_reg.h b/components/soc/esp32c5/include/soc/cache_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/cache_reg.h
rename to components/soc/esp32c5/include/soc/cache_reg.h
index 80d3221805..f6ca76381f 100644
--- a/components/soc/esp32c5/mp/include/soc/cache_reg.h
+++ b/components/soc/esp32c5/include/soc/cache_reg.h
@@ -4077,7 +4077,7 @@ extern "C" {
 #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254)
 /** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request gets response but not completed.
  */
 #define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
@@ -4085,7 +4085,7 @@ extern "C" {
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
 /** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request gets response but not completed.
  */
 #define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
 #define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
@@ -4107,7 +4107,7 @@ extern "C" {
 #define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
 /** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 cache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request gets response but not completed.
  */
 #define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
 #define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
@@ -5937,7 +5937,7 @@ extern "C" {
 #define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0)
 /** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l2 icache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request gets response but not completed.
  */
 #define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
 #define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
diff --git a/components/soc/esp32c5/mp/include/soc/cache_struct.h b/components/soc/esp32c5/include/soc/cache_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/cache_struct.h
rename to components/soc/esp32c5/include/soc/cache_struct.h
index 10807e94fa..de47a02fb3 100644
--- a/components/soc/esp32c5/mp/include/soc/cache_struct.h
+++ b/components/soc/esp32c5/include/soc/cache_struct.h
@@ -5100,12 +5100,12 @@ typedef union {
     struct {
         /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request gets response but not completed.
          */
         uint32_t l1_icache0_unalloc_clr:1;
         /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request gets response but not completed.
          */
         uint32_t l1_icache1_unalloc_clr:1;
         /** l1_icache2_unalloc_clr : R/W; bitpos: [2]; default: 0;
@@ -5118,7 +5118,7 @@ typedef union {
         uint32_t l1_icache3_unalloc_clr:1;
         /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request gets response but not completed.
          */
         uint32_t l1_cache_unalloc_clr:1;
         uint32_t reserved_5:27;
@@ -5134,7 +5134,7 @@ typedef union {
         uint32_t reserved_0:5;
         /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request gets response but not completed.
          */
         uint32_t l2_cache_unalloc_clr:1;
         uint32_t reserved_6:26;
diff --git a/components/soc/esp32c5/mp/include/soc/clic_reg.h b/components/soc/esp32c5/include/soc/clic_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/clic_reg.h
rename to components/soc/esp32c5/include/soc/clic_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/clint_reg.h b/components/soc/esp32c5/include/soc/clint_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/clint_reg.h
rename to components/soc/esp32c5/include/soc/clint_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/clk_tree_defs.h
rename to components/soc/esp32c5/include/soc/clk_tree_defs.h
diff --git a/components/soc/esp32c5/beta3/include/soc/clkout_channel.h b/components/soc/esp32c5/include/soc/clkout_channel.h
similarity index 100%
rename from components/soc/esp32c5/beta3/include/soc/clkout_channel.h
rename to components/soc/esp32c5/include/soc/clkout_channel.h
diff --git a/components/soc/esp32c5/mp/include/soc/dport_access.h b/components/soc/esp32c5/include/soc/dport_access.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/dport_access.h
rename to components/soc/esp32c5/include/soc/dport_access.h
diff --git a/components/soc/esp32c5/mp/include/soc/ds_reg.h b/components/soc/esp32c5/include/soc/ds_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ds_reg.h
rename to components/soc/esp32c5/include/soc/ds_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/ds_struct.h b/components/soc/esp32c5/include/soc/ds_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ds_struct.h
rename to components/soc/esp32c5/include/soc/ds_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/ecc_mult_reg.h b/components/soc/esp32c5/include/soc/ecc_mult_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ecc_mult_reg.h
rename to components/soc/esp32c5/include/soc/ecc_mult_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/include/soc/ecc_mult_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ecc_mult_struct.h
rename to components/soc/esp32c5/include/soc/ecc_mult_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/ecdsa_reg.h b/components/soc/esp32c5/include/soc/ecdsa_reg.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/ecdsa_reg.h
rename to components/soc/esp32c5/include/soc/ecdsa_reg.h
index aca4b64b19..4893390ced 100644
--- a/components/soc/esp32c5/mp/include/soc/ecdsa_reg.h
+++ b/components/soc/esp32c5/include/soc/ecdsa_reg.h
@@ -211,7 +211,7 @@ extern "C" {
  */
 #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
 /** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
  *  after configuration.
  */
 #define ECDSA_START    (BIT(0))
@@ -299,7 +299,7 @@ extern "C" {
  */
 #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
 /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_START    (BIT(0))
@@ -312,7 +312,7 @@ extern "C" {
  */
 #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
 /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_CONTINUE    (BIT(0))
diff --git a/components/soc/esp32c5/mp/include/soc/ecdsa_struct.h b/components/soc/esp32c5/include/soc/ecdsa_struct.h
similarity index 97%
rename from components/soc/esp32c5/mp/include/soc/ecdsa_struct.h
rename to components/soc/esp32c5/include/soc/ecdsa_struct.h
index bed383c9da..858a4ffc5f 100644
--- a/components/soc/esp32c5/mp/include/soc/ecdsa_struct.h
+++ b/components/soc/esp32c5/include/soc/ecdsa_struct.h
@@ -57,7 +57,7 @@ typedef union {
 typedef union {
     struct {
         /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
          *  after configuration.
          */
         uint32_t start:1;
@@ -260,7 +260,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_start:1;
@@ -275,7 +275,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_continue:1;
diff --git a/components/soc/esp32c5/beta3/include/soc/efuse_defs.h b/components/soc/esp32c5/include/soc/efuse_defs.h
similarity index 100%
rename from components/soc/esp32c5/beta3/include/soc/efuse_defs.h
rename to components/soc/esp32c5/include/soc/efuse_defs.h
diff --git a/components/soc/esp32c5/mp/include/soc/efuse_reg.h b/components/soc/esp32c5/include/soc/efuse_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/efuse_reg.h
rename to components/soc/esp32c5/include/soc/efuse_reg.h
index 2ade523d2a..9942226ab8 100644
--- a/components/soc/esp32c5/mp/include/soc/efuse_reg.h
+++ b/components/soc/esp32c5/include/soc/efuse_reg.h
@@ -263,14 +263,14 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFH    0x00000003U
 #define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
 #define EFUSE_USB_DREFH_V  0x00000003U
 #define EFUSE_USB_DREFH_S  21
 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
  */
 #define EFUSE_USB_DREFL    0x00000003U
 #define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
@@ -2259,7 +2259,7 @@ extern "C" {
 #define EFUSE_CLK_EN_S  16
 
 /** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
 /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
diff --git a/components/soc/esp32c5/mp/include/soc/efuse_struct.h b/components/soc/esp32c5/include/soc/efuse_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/efuse_struct.h
rename to components/soc/esp32c5/include/soc/efuse_struct.h
index f4525d6b4d..67bd83eee3 100644
--- a/components/soc/esp32c5/mp/include/soc/efuse_struct.h
+++ b/components/soc/esp32c5/include/soc/efuse_struct.h
@@ -241,11 +241,11 @@ typedef union {
          */
         uint32_t dis_download_manual_encrypt:1;
         /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefh:2;
         /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
          */
         uint32_t usb_drefl:2;
         /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
@@ -2013,7 +2013,7 @@ typedef union {
 
 /** Group: EFUSE Configure Registers */
 /** Type of conf register
- *  eFuse operation mode configuraiton register
+ *  eFuse operation mode configuration register
  */
 typedef union {
     struct {
@@ -4229,7 +4229,7 @@ typedef union {
 } efuse_apb2otp_blk10_w10_reg_t;
 
 
-/** Group: EFUSE_APB2OTP Function Enable Singal */
+/** Group: EFUSE_APB2OTP Function Enable Signal */
 /** Type of apb2otp_en register
  *  eFuse apb2otp enable configuration register.
  */
diff --git a/components/soc/esp32c5/mp/include/soc/ext_mem_defs.h b/components/soc/esp32c5/include/soc/ext_mem_defs.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ext_mem_defs.h
rename to components/soc/esp32c5/include/soc/ext_mem_defs.h
diff --git a/components/soc/esp32c5/mp/include/soc/gdma_channel.h b/components/soc/esp32c5/include/soc/gdma_channel.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/gdma_channel.h
rename to components/soc/esp32c5/include/soc/gdma_channel.h
diff --git a/components/soc/esp32c5/mp/include/soc/gpio_ext_reg.h b/components/soc/esp32c5/include/soc/gpio_ext_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/gpio_ext_reg.h
rename to components/soc/esp32c5/include/soc/gpio_ext_reg.h
index e1df33b20e..2b839bccb6 100644
--- a/components/soc/esp32c5/mp/include/soc/gpio_ext_reg.h
+++ b/components/soc/esp32c5/include/soc/gpio_ext_reg.h
@@ -127,7 +127,7 @@ extern "C" {
 #define GPIO_EXT_XPD_COMP_0_V  0x00000001U
 #define GPIO_EXT_XPD_COMP_0_S  0
 /** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0;
- *  Configures the reference voltage for analog PAD voltage comparater.. \\
+ *  Configures the reference voltage for analog PAD voltage comparator.. \\
  *  0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
  *  used as a regular GPIO\\
  *  1: Reference voltage is the voltage on the GPIO8 PAD\\
diff --git a/components/soc/esp32c5/mp/include/soc/gpio_ext_struct.h b/components/soc/esp32c5/include/soc/gpio_ext_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/gpio_ext_struct.h
rename to components/soc/esp32c5/include/soc/gpio_ext_struct.h
index 8511152aab..b00b5a40a4 100644
--- a/components/soc/esp32c5/mp/include/soc/gpio_ext_struct.h
+++ b/components/soc/esp32c5/include/soc/gpio_ext_struct.h
@@ -75,7 +75,7 @@ typedef union {
          */
         uint32_t xpd_comp_0:1;
         /** mode_comp_0 : R/W; bitpos: [1]; default: 0;
-         *  Configures the reference voltage for analog PAD voltage comparater.. \\
+         *  Configures the reference voltage for analog PAD voltage comparator.. \\
          *  0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
          *  used as a regular GPIO\\
          *  1: Reference voltage is the voltage on the GPIO8 PAD\\
diff --git a/components/soc/esp32c5/mp/include/soc/gpio_num.h b/components/soc/esp32c5/include/soc/gpio_num.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/gpio_num.h
rename to components/soc/esp32c5/include/soc/gpio_num.h
diff --git a/components/soc/esp32c5/mp/include/soc/gpio_pins.h b/components/soc/esp32c5/include/soc/gpio_pins.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/gpio_pins.h
rename to components/soc/esp32c5/include/soc/gpio_pins.h
diff --git a/components/soc/esp32c5/mp/include/soc/gpio_reg.h b/components/soc/esp32c5/include/soc/gpio_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/gpio_reg.h
rename to components/soc/esp32c5/include/soc/gpio_reg.h
diff --git a/components/soc/esp32c5/include/soc/gpio_sig_map.h b/components/soc/esp32c5/include/soc/gpio_sig_map.h
index b7a085102d..813f0a0515 100644
--- a/components/soc/esp32c5/include/soc/gpio_sig_map.h
+++ b/components/soc/esp32c5/include/soc/gpio_sig_map.h
@@ -6,12 +6,241 @@
 
 #pragma once
 
-#include "sdkconfig.h"
-
-// TODO: IDF-9197 This file is created to glob the gpio_sig_map.h files correctly in esp-docs
-
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-#include "../../beta3/include/soc/gpio_sig_map.h"
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-#include "../../mp/include/soc/gpio_sig_map.h"
-#endif
+#define EXT_ADC_START_IDX                       0
+#define LEDC_LS_SIG_OUT0_IDX                    0
+#define LEDC_LS_SIG_OUT1_IDX                    1
+#define LEDC_LS_SIG_OUT2_IDX                    2
+#define LEDC_LS_SIG_OUT3_IDX                    3
+#define LEDC_LS_SIG_OUT4_IDX                    4
+#define LEDC_LS_SIG_OUT5_IDX                    5
+#define U0RXD_IN_IDX                            6
+#define U0TXD_OUT_IDX                           6
+#define U0CTS_IN_IDX                            7
+#define U0RTS_OUT_IDX                           7
+#define U0DSR_IN_IDX                            8
+#define U0DTR_OUT_IDX                           8
+#define U1RXD_IN_IDX                            9
+#define U1TXD_OUT_IDX                           9
+#define U1CTS_IN_IDX                            10
+#define U1RTS_OUT_IDX                           10
+#define U1DSR_IN_IDX                            11
+#define U1DTR_OUT_IDX                           11
+#define I2S_MCLK_IN_IDX                         12
+#define I2S_MCLK_OUT_IDX                        12
+#define I2SO_BCK_IN_IDX                         13
+#define I2SO_BCK_OUT_IDX                        13
+#define I2SO_WS_IN_IDX                          14
+#define I2SO_WS_OUT_IDX                         14
+#define I2SI_SD_IN_IDX                          15
+#define I2SO_SD_OUT_IDX                         15
+#define I2SI_BCK_IN_IDX                         16
+#define I2SI_BCK_OUT_IDX                        16
+#define I2SI_WS_IN_IDX                          17
+#define I2SI_WS_OUT_IDX                         17
+#define I2SO_SD1_OUT_IDX                        18
+#define CPU_TESTBUS0_IDX                        19
+#define CPU_TESTBUS1_IDX                        20
+#define CPU_TESTBUS2_IDX                        21
+#define CPU_TESTBUS3_IDX                        22
+#define CPU_TESTBUS4_IDX                        23
+#define CPU_TESTBUS5_IDX                        24
+#define CPU_TESTBUS6_IDX                        25
+#define CPU_TESTBUS7_IDX                        26
+#define CPU_GPIO_IN0_IDX                        27
+#define CPU_GPIO_OUT0_IDX                       27
+#define CPU_GPIO_IN1_IDX                        28
+#define CPU_GPIO_OUT1_IDX                       28
+#define CPU_GPIO_IN2_IDX                        29
+#define CPU_GPIO_OUT2_IDX                       29
+#define CPU_GPIO_IN3_IDX                        30
+#define CPU_GPIO_OUT3_IDX                       30
+#define CPU_GPIO_IN4_IDX                        31
+#define CPU_GPIO_OUT4_IDX                       31
+#define CPU_GPIO_IN5_IDX                        32
+#define CPU_GPIO_OUT5_IDX                       32
+#define CPU_GPIO_IN6_IDX                        33
+#define CPU_GPIO_OUT6_IDX                       33
+#define CPU_GPIO_IN7_IDX                        34
+#define CPU_GPIO_OUT7_IDX                       34
+#define USB_JTAG_TDO_IDX                        35
+#define USB_JTAG_TRST_IDX                       35
+#define USB_JTAG_SRST_IDX                       36
+#define USB_JTAG_TCK_IDX                        37
+#define USB_JTAG_TMS_IDX                        38
+#define USB_JTAG_TDI_IDX                        39
+#define CPU_USB_JTAG_TDO_IDX                    40
+#define USB_EXTPHY_VP_IDX                       41
+#define USB_EXTPHY_OEN_IDX                      41
+#define USB_EXTPHY_VM_IDX                       42
+#define USB_EXTPHY_SPEED_IDX                    42
+#define USB_EXTPHY_RCV_IDX                      43
+#define USB_EXTPHY_VPO_IDX                      43
+#define USB_EXTPHY_VMO_IDX                      44
+#define USB_EXTPHY_SUSPND_IDX                   45
+#define I2CEXT0_SCL_IN_IDX                      46
+#define I2CEXT0_SCL_OUT_IDX                     46
+#define I2CEXT0_SDA_IN_IDX                      47
+#define I2CEXT0_SDA_OUT_IDX                     47
+#define PARL_RX_DATA0_IDX                       48
+#define PARL_TX_DATA0_IDX                       48
+#define PARL_RX_DATA1_IDX                       49
+#define PARL_TX_DATA1_IDX                       49
+#define PARL_RX_DATA2_IDX                       50
+#define PARL_TX_DATA2_IDX                       50
+#define PARL_RX_DATA3_IDX                       51
+#define PARL_TX_DATA3_IDX                       51
+#define PARL_RX_DATA4_IDX                       52
+#define PARL_TX_DATA4_IDX                       52
+#define PARL_RX_DATA5_IDX                       53
+#define PARL_TX_DATA5_IDX                       53
+#define PARL_RX_DATA6_IDX                       54
+#define PARL_TX_DATA6_IDX                       54
+#define PARL_RX_DATA7_IDX                       55
+#define PARL_TX_DATA7_IDX                       55
+#define FSPICLK_IN_IDX                          56
+#define FSPICLK_OUT_IDX                         56
+#define FSPIQ_IN_IDX                            57
+#define FSPIQ_OUT_IDX                           57
+#define FSPID_IN_IDX                            58
+#define FSPID_OUT_IDX                           58
+#define FSPIHD_IN_IDX                           59
+#define FSPIHD_OUT_IDX                          59
+#define FSPIWP_IN_IDX                           60
+#define FSPIWP_OUT_IDX                          60
+#define FSPICS0_IN_IDX                          61
+#define FSPICS0_OUT_IDX                         61
+#define PARL_RX_CLK_IN_IDX                      62
+#define PARL_RX_CLK_OUT_IDX                     62
+#define PARL_TX_CLK_IN_IDX                      63
+#define PARL_TX_CLK_OUT_IDX                     63
+#define RMT_SIG_IN0_IDX                         64
+#define RMT_SIG_OUT0_IDX                        64
+#define RMT_SIG_IN1_IDX                         65
+#define RMT_SIG_OUT1_IDX                        65
+#define TWAI0_RX_IDX                            66
+#define TWAI0_TX_IDX                            66
+#define TWAI0_BUS_OFF_ON_IDX                    67
+#define TWAI0_CLKOUT_IDX                        68
+#define TWAI0_STANDBY_IDX                       69
+#define TWAI1_RX_IDX                            70
+#define TWAI1_TX_IDX                            70
+#define TWAI1_BUS_OFF_ON_IDX                    71
+#define TWAI1_CLKOUT_IDX                        72
+#define TWAI1_STANDBY_IDX                       73
+#define EXTERN_PRIORITY_I_IDX                   74
+#define EXTERN_PRIORITY_O_IDX                   74
+#define EXTERN_ACTIVE_I_IDX                     75
+#define EXTERN_ACTIVE_O_IDX                     75
+#define PCNT_RST_IN0_IDX                        76
+#define GPIO_SD0_OUT_IDX                        76
+#define PCNT_RST_IN1_IDX                        77
+#define GPIO_SD1_OUT_IDX                        77
+#define PCNT_RST_IN2_IDX                        78
+#define GPIO_SD2_OUT_IDX                        78
+#define PCNT_RST_IN3_IDX                        79
+#define GPIO_SD3_OUT_IDX                        79
+#define PWM0_SYNC0_IN_IDX                       80
+#define PWM0_OUT0A_IDX                          80
+#define PWM0_SYNC1_IN_IDX                       81
+#define PWM0_OUT0B_IDX                          81
+#define PWM0_SYNC2_IN_IDX                       82
+#define PWM0_OUT1A_IDX                          82
+#define PWM0_F0_IN_IDX                          83
+#define PWM0_OUT1B_IDX                          83
+#define PWM0_F1_IN_IDX                          84
+#define PWM0_OUT2A_IDX                          84
+#define PWM0_F2_IN_IDX                          85
+#define PWM0_OUT2B_IDX                          85
+#define PWM0_CAP0_IN_IDX                        86
+#define PWM0_CAP1_IN_IDX                        87
+#define PWM0_CAP2_IN_IDX                        88
+#define GPIO_EVENT_MATRIX_IN0_IDX               89
+#define GPIO_TASK_MATRIX_OUT0_IDX               89
+#define GPIO_EVENT_MATRIX_IN1_IDX               90
+#define GPIO_TASK_MATRIX_OUT1_IDX               90
+#define GPIO_EVENT_MATRIX_IN2_IDX               91
+#define GPIO_TASK_MATRIX_OUT2_IDX               91
+#define GPIO_EVENT_MATRIX_IN3_IDX               92
+#define GPIO_TASK_MATRIX_OUT3_IDX               92
+#define CLK_OUT_OUT1_IDX                        93
+#define CLK_OUT_OUT2_IDX                        94
+#define CLK_OUT_OUT3_IDX                        95
+#define SIG_IN_FUNC_97_IDX                      97
+#define SIG_IN_FUNC97_IDX                       97
+#define SIG_IN_FUNC_98_IDX                      98
+#define SIG_IN_FUNC98_IDX                       98
+#define SIG_IN_FUNC_99_IDX                      99
+#define SIG_IN_FUNC99_IDX                       99
+#define SIG_IN_FUNC_100_IDX                     100
+#define SIG_IN_FUNC100_IDX                      100
+#define PCNT_SIG_CH0_IN0_IDX                    101
+#define FSPICS1_OUT_IDX                         101
+#define PCNT_SIG_CH1_IN0_IDX                    102
+#define FSPICS2_OUT_IDX                         102
+#define PCNT_CTRL_CH0_IN0_IDX                   103
+#define FSPICS3_OUT_IDX                         103
+#define PCNT_CTRL_CH1_IN0_IDX                   104
+#define FSPICS4_OUT_IDX                         104
+#define PCNT_SIG_CH0_IN1_IDX                    105
+#define FSPICS5_OUT_IDX                         105
+#define PCNT_SIG_CH1_IN1_IDX                    106
+#define MODEM_DIAG0_IDX                         106
+#define PCNT_CTRL_CH0_IN1_IDX                   107
+#define MODEM_DIAG1_IDX                         107
+#define PCNT_CTRL_CH1_IN1_IDX                   108
+#define MODEM_DIAG2_IDX                         108
+#define PCNT_SIG_CH0_IN2_IDX                    109
+#define MODEM_DIAG3_IDX                         109
+#define PCNT_SIG_CH1_IN2_IDX                    110
+#define MODEM_DIAG4_IDX                         110
+#define PCNT_CTRL_CH0_IN2_IDX                   111
+#define MODEM_DIAG5_IDX                         111
+#define PCNT_CTRL_CH1_IN2_IDX                   112
+#define MODEM_DIAG6_IDX                         112
+#define PCNT_SIG_CH0_IN3_IDX                    113
+#define MODEM_DIAG7_IDX                         113
+#define PCNT_SIG_CH1_IN3_IDX                    114
+#define MODEM_DIAG8_IDX                         114
+#define PCNT_CTRL_CH0_IN3_IDX                   115
+#define MODEM_DIAG9_IDX                         115
+#define PCNT_CTRL_CH1_IN3_IDX                   116
+#define MODEM_DIAG10_IDX                        116
+#define MODEM_DIAG11_IDX                        117
+#define MODEM_DIAG12_IDX                        118
+#define MODEM_DIAG13_IDX                        119
+#define MODEM_DIAG14_IDX                        120
+#define MODEM_DIAG15_IDX                        121
+#define MODEM_DIAG16_IDX                        122
+#define MODEM_DIAG17_IDX                        123
+#define MODEM_DIAG18_IDX                        124
+#define MODEM_DIAG19_IDX                        125
+#define MODEM_DIAG20_IDX                        126
+#define MODEM_DIAG21_IDX                        127
+#define MODEM_DIAG22_IDX                        128
+#define MODEM_DIAG23_IDX                        129
+#define MODEM_DIAG24_IDX                        130
+#define MODEM_DIAG25_IDX                        131
+#define MODEM_DIAG26_IDX                        132
+#define MODEM_DIAG27_IDX                        133
+#define MODEM_DIAG28_IDX                        134
+#define MODEM_DIAG29_IDX                        135
+#define MODEM_DIAG30_IDX                        136
+#define MODEM_DIAG31_IDX                        137
+#define ANT_SEL0_IDX                            138
+#define ANT_SEL1_IDX                            139
+#define ANT_SEL2_IDX                            140
+#define ANT_SEL3_IDX                            141
+#define ANT_SEL4_IDX                            142
+#define ANT_SEL5_IDX                            143
+#define ANT_SEL6_IDX                            144
+#define ANT_SEL7_IDX                            145
+#define ANT_SEL8_IDX                            146
+#define ANT_SEL9_IDX                            147
+#define ANT_SEL10_IDX                           148
+#define ANT_SEL11_IDX                           149
+#define ANT_SEL12_IDX                           150
+#define ANT_SEL13_IDX                           151
+#define ANT_SEL14_IDX                           152
+#define ANT_SEL15_IDX                           153
+#define SIG_GPIO_OUT_IDX                        256
+// version date 2311280
diff --git a/components/soc/esp32c5/mp/include/soc/gpio_struct.h b/components/soc/esp32c5/include/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/gpio_struct.h
rename to components/soc/esp32c5/include/soc/gpio_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/hmac_reg.h b/components/soc/esp32c5/include/soc/hmac_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/hmac_reg.h
rename to components/soc/esp32c5/include/soc/hmac_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/hmac_struct.h b/components/soc/esp32c5/include/soc/hmac_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/hmac_struct.h
rename to components/soc/esp32c5/include/soc/hmac_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/hp_apm_reg.h b/components/soc/esp32c5/include/soc/hp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/hp_apm_reg.h
rename to components/soc/esp32c5/include/soc/hp_apm_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/hp_apm_struct.h b/components/soc/esp32c5/include/soc/hp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/hp_apm_struct.h
rename to components/soc/esp32c5/include/soc/hp_apm_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/hp_system_reg.h b/components/soc/esp32c5/include/soc/hp_system_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/hp_system_reg.h
rename to components/soc/esp32c5/include/soc/hp_system_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/hp_system_struct.h b/components/soc/esp32c5/include/soc/hp_system_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/hp_system_struct.h
rename to components/soc/esp32c5/include/soc/hp_system_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/huk_reg.h b/components/soc/esp32c5/include/soc/huk_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/huk_reg.h
rename to components/soc/esp32c5/include/soc/huk_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/huk_struct.h b/components/soc/esp32c5/include/soc/huk_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/huk_struct.h
rename to components/soc/esp32c5/include/soc/huk_struct.h
diff --git a/components/soc/esp32c5/beta3/include/soc/hwcrypto_reg.h b/components/soc/esp32c5/include/soc/hwcrypto_reg.h
similarity index 100%
rename from components/soc/esp32c5/beta3/include/soc/hwcrypto_reg.h
rename to components/soc/esp32c5/include/soc/hwcrypto_reg.h
diff --git a/components/soc/esp32c5/beta3/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c5/beta3/include/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/i2c_reg.h b/components/soc/esp32c5/include/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/i2c_reg.h
rename to components/soc/esp32c5/include/soc/i2c_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/i2c_struct.h b/components/soc/esp32c5/include/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/i2c_struct.h
rename to components/soc/esp32c5/include/soc/i2c_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/i2s_reg.h b/components/soc/esp32c5/include/soc/i2s_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/i2s_reg.h
rename to components/soc/esp32c5/include/soc/i2s_reg.h
index 2396b034ba..330382b7ed 100644
--- a/components/soc/esp32c5/mp/include/soc/i2s_reg.h
+++ b/components/soc/esp32c5/include/soc/i2s_reg.h
@@ -328,7 +328,7 @@ extern "C" {
 #define I2S_TX_SLAVE_MOD_V  0x00000001U
 #define I2S_TX_SLAVE_MOD_S  3
 /** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
  */
 #define I2S_TX_STOP_EN    (BIT(4))
 #define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
diff --git a/components/soc/esp32c5/mp/include/soc/i2s_struct.h b/components/soc/esp32c5/include/soc/i2s_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/i2s_struct.h
rename to components/soc/esp32c5/include/soc/i2s_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/interrupt_matrix_reg.h
rename to components/soc/esp32c5/include/soc/interrupt_matrix_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/interrupt_matrix_struct.h
rename to components/soc/esp32c5/include/soc/interrupt_matrix_struct.h
diff --git a/components/soc/esp32c5/beta3/include/soc/interrupt_reg.h b/components/soc/esp32c5/include/soc/interrupt_reg.h
similarity index 100%
rename from components/soc/esp32c5/beta3/include/soc/interrupt_reg.h
rename to components/soc/esp32c5/include/soc/interrupt_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/interrupts.h b/components/soc/esp32c5/include/soc/interrupts.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/interrupts.h
rename to components/soc/esp32c5/include/soc/interrupts.h
diff --git a/components/soc/esp32c5/mp/include/soc/intpri_reg.h b/components/soc/esp32c5/include/soc/intpri_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/intpri_reg.h
rename to components/soc/esp32c5/include/soc/intpri_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/intpri_struct.h b/components/soc/esp32c5/include/soc/intpri_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/intpri_struct.h
rename to components/soc/esp32c5/include/soc/intpri_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/io_mux_reg.h b/components/soc/esp32c5/include/soc/io_mux_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/io_mux_reg.h
rename to components/soc/esp32c5/include/soc/io_mux_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/io_mux_struct.h b/components/soc/esp32c5/include/soc/io_mux_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/io_mux_struct.h
rename to components/soc/esp32c5/include/soc/io_mux_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/keymng_reg.h b/components/soc/esp32c5/include/soc/keymng_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/keymng_reg.h
rename to components/soc/esp32c5/include/soc/keymng_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/keymng_struct.h b/components/soc/esp32c5/include/soc/keymng_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/keymng_struct.h
rename to components/soc/esp32c5/include/soc/keymng_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/ledc_reg.h b/components/soc/esp32c5/include/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ledc_reg.h
rename to components/soc/esp32c5/include/soc/ledc_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/ledc_struct.h b/components/soc/esp32c5/include/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/ledc_struct.h
rename to components/soc/esp32c5/include/soc/ledc_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_analog_peri_reg.h
rename to components/soc/esp32c5/include/soc/lp_analog_peri_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_analog_peri_struct.h
rename to components/soc/esp32c5/include/soc/lp_analog_peri_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_aon_reg.h b/components/soc/esp32c5/include/soc/lp_aon_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/lp_aon_reg.h
rename to components/soc/esp32c5/include/soc/lp_aon_reg.h
index 9627ac52d4..32d0007632 100644
--- a/components/soc/esp32c5/mp/include/soc/lp_aon_reg.h
+++ b/components/soc/esp32c5/include/soc/lp_aon_reg.h
@@ -501,7 +501,7 @@ extern "C" {
  */
 #define LP_AON_BACKUP_DMA_CFG0_REG (DR_REG_LP_AON_BASE + 0x70)
 /** LP_AON_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
- *  Set this field to configure max value of burst in signle transfer.
+ *  Set this field to configure max value of burst in single transfer.
  */
 #define LP_AON_BURST_LIMIT_AON    0x0000001FU
 #define LP_AON_BURST_LIMIT_AON_M  (LP_AON_BURST_LIMIT_AON_V << LP_AON_BURST_LIMIT_AON_S)
diff --git a/components/soc/esp32c5/mp/include/soc/lp_aon_struct.h b/components/soc/esp32c5/include/soc/lp_aon_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/lp_aon_struct.h
rename to components/soc/esp32c5/include/soc/lp_aon_struct.h
index e01e64a12d..22fa8d0176 100644
--- a/components/soc/esp32c5/mp/include/soc/lp_aon_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_aon_struct.h
@@ -462,7 +462,7 @@ typedef union {
 typedef union {
     struct {
         /** burst_limit_aon : R/W; bitpos: [4:0]; default: 10;
-         *  Set this field to configure max value of burst in signle transfer.
+         *  Set this field to configure max value of burst in single transfer.
          */
         uint32_t burst_limit_aon:5;
         /** read_interval_aon : R/W; bitpos: [11:5]; default: 10;
diff --git a/components/soc/esp32c5/mp/include/soc/lp_apm0_reg.h b/components/soc/esp32c5/include/soc/lp_apm0_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_apm0_reg.h
rename to components/soc/esp32c5/include/soc/lp_apm0_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/include/soc/lp_apm0_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_apm0_struct.h
rename to components/soc/esp32c5/include/soc/lp_apm0_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_apm_reg.h b/components/soc/esp32c5/include/soc/lp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_apm_reg.h
rename to components/soc/esp32c5/include/soc/lp_apm_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_apm_struct.h b/components/soc/esp32c5/include/soc/lp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_apm_struct.h
rename to components/soc/esp32c5/include/soc/lp_apm_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_clkrst_reg.h b/components/soc/esp32c5/include/soc/lp_clkrst_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/lp_clkrst_reg.h
rename to components/soc/esp32c5/include/soc/lp_clkrst_reg.h
index 4e755c6939..bb60f70095 100644
--- a/components/soc/esp32c5/mp/include/soc/lp_clkrst_reg.h
+++ b/components/soc/esp32c5/include/soc/lp_clkrst_reg.h
@@ -213,7 +213,7 @@ extern "C" {
 #define LP_CLKRST_ANA_PERI_RESET_EN_S  31
 
 /** LP_CLKRST_RESET_CAUSE_REG register
- *  Represents the reset casue
+ *  Represents the reset cause
  */
 #define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
 /** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
diff --git a/components/soc/esp32c5/mp/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/lp_clkrst_struct.h
rename to components/soc/esp32c5/include/soc/lp_clkrst_struct.h
index ec986d13f4..ae1ef229db 100644
--- a/components/soc/esp32c5/mp/include/soc/lp_clkrst_struct.h
+++ b/components/soc/esp32c5/include/soc/lp_clkrst_struct.h
@@ -173,7 +173,7 @@ typedef union {
 } lp_clkrst_lp_rst_en_reg_t;
 
 /** Type of reset_cause register
- *  Represents the reset casue
+ *  Represents the reset cause
  */
 typedef union {
     struct {
diff --git a/components/soc/esp32c5/mp/include/soc/lp_gpio_reg.h b/components/soc/esp32c5/include/soc/lp_gpio_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_gpio_reg.h
rename to components/soc/esp32c5/include/soc/lp_gpio_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_gpio_struct.h b/components/soc/esp32c5/include/soc/lp_gpio_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_gpio_struct.h
rename to components/soc/esp32c5/include/soc/lp_gpio_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_i2c_ana_mst_reg.h
rename to components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_i2c_ana_mst_struct.h
rename to components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/include/soc/lp_i2c_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_i2c_reg.h
rename to components/soc/esp32c5/include/soc/lp_i2c_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/include/soc/lp_i2c_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_i2c_struct.h
rename to components/soc/esp32c5/include/soc/lp_i2c_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_iomux_reg.h b/components/soc/esp32c5/include/soc/lp_iomux_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_iomux_reg.h
rename to components/soc/esp32c5/include/soc/lp_iomux_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_iomux_struct.h b/components/soc/esp32c5/include/soc/lp_iomux_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_iomux_struct.h
rename to components/soc/esp32c5/include/soc/lp_iomux_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_tee_reg.h b/components/soc/esp32c5/include/soc/lp_tee_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_tee_reg.h
rename to components/soc/esp32c5/include/soc/lp_tee_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_tee_struct.h b/components/soc/esp32c5/include/soc/lp_tee_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_tee_struct.h
rename to components/soc/esp32c5/include/soc/lp_tee_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_timer_reg.h b/components/soc/esp32c5/include/soc/lp_timer_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_timer_reg.h
rename to components/soc/esp32c5/include/soc/lp_timer_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_timer_struct.h b/components/soc/esp32c5/include/soc/lp_timer_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_timer_struct.h
rename to components/soc/esp32c5/include/soc/lp_timer_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_uart_reg.h b/components/soc/esp32c5/include/soc/lp_uart_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_uart_reg.h
rename to components/soc/esp32c5/include/soc/lp_uart_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_uart_struct.h b/components/soc/esp32c5/include/soc/lp_uart_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_uart_struct.h
rename to components/soc/esp32c5/include/soc/lp_uart_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_wdt_reg.h b/components/soc/esp32c5/include/soc/lp_wdt_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_wdt_reg.h
rename to components/soc/esp32c5/include/soc/lp_wdt_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/include/soc/lp_wdt_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lp_wdt_struct.h
rename to components/soc/esp32c5/include/soc/lp_wdt_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/lpperi_reg.h b/components/soc/esp32c5/include/soc/lpperi_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lpperi_reg.h
rename to components/soc/esp32c5/include/soc/lpperi_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/lpperi_struct.h b/components/soc/esp32c5/include/soc/lpperi_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/lpperi_struct.h
rename to components/soc/esp32c5/include/soc/lpperi_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/mcpwm_reg.h b/components/soc/esp32c5/include/soc/mcpwm_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/mcpwm_reg.h
rename to components/soc/esp32c5/include/soc/mcpwm_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/mcpwm_struct.h b/components/soc/esp32c5/include/soc/mcpwm_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/mcpwm_struct.h
rename to components/soc/esp32c5/include/soc/mcpwm_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/mem_monitor_reg.h b/components/soc/esp32c5/include/soc/mem_monitor_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/mem_monitor_reg.h
rename to components/soc/esp32c5/include/soc/mem_monitor_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/include/soc/mem_monitor_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/mem_monitor_struct.h
rename to components/soc/esp32c5/include/soc/mem_monitor_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/parl_io_reg.h b/components/soc/esp32c5/include/soc/parl_io_reg.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/parl_io_reg.h
rename to components/soc/esp32c5/include/soc/parl_io_reg.h
index f62624aba0..1cdf9089ae 100644
--- a/components/soc/esp32c5/mp/include/soc/parl_io_reg.h
+++ b/components/soc/esp32c5/include/soc/parl_io_reg.h
@@ -256,7 +256,7 @@ extern "C" {
 #define PARL_IO_TX_READY_S  31
 
 /** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 #define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
@@ -282,7 +282,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ENA_S  2
 
 /** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 #define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
 /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
@@ -308,7 +308,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_RAW_S  2
 
 /** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 #define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
 /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
@@ -334,7 +334,7 @@ extern "C" {
 #define PARL_IO_TX_EOF_INT_ST_S  2
 
 /** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 #define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
 /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
diff --git a/components/soc/esp32c5/mp/include/soc/parl_io_struct.h b/components/soc/esp32c5/include/soc/parl_io_struct.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/parl_io_struct.h
rename to components/soc/esp32c5/include/soc/parl_io_struct.h
index 8990ada4ea..4c3e326433 100644
--- a/components/soc/esp32c5/mp/include/soc/parl_io_struct.h
+++ b/components/soc/esp32c5/include/soc/parl_io_struct.h
@@ -252,7 +252,7 @@ typedef union {
 
 /** Group: PARL_IO Interrupt Configuration and Status */
 /** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
+ *  Parallel IO interrupt enable signal configuration register.
  */
 typedef union {
     struct {
@@ -274,7 +274,7 @@ typedef union {
 } parl_io_int_ena_reg_t;
 
 /** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
+ *  Parallel IO interrupt raw signal status register.
  */
 typedef union {
     struct {
@@ -296,7 +296,7 @@ typedef union {
 } parl_io_int_raw_reg_t;
 
 /** Type of int_st register
- *  Parallel IO interrupt singal status register.
+ *  Parallel IO interrupt signal status register.
  */
 typedef union {
     struct {
@@ -318,7 +318,7 @@ typedef union {
 } parl_io_int_st_reg_t;
 
 /** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
+ *  Parallel IO interrupt  clear signal configuration register.
  */
 typedef union {
     struct {
diff --git a/components/soc/esp32c5/mp/include/soc/pau_reg.h b/components/soc/esp32c5/include/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pau_reg.h
rename to components/soc/esp32c5/include/soc/pau_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/pau_struct.h b/components/soc/esp32c5/include/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pau_struct.h
rename to components/soc/esp32c5/include/soc/pau_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/pcnt_reg.h b/components/soc/esp32c5/include/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pcnt_reg.h
rename to components/soc/esp32c5/include/soc/pcnt_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/pcnt_struct.h b/components/soc/esp32c5/include/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pcnt_struct.h
rename to components/soc/esp32c5/include/soc/pcnt_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/pcr_reg.h b/components/soc/esp32c5/include/soc/pcr_reg.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/pcr_reg.h
rename to components/soc/esp32c5/include/soc/pcr_reg.h
index 8631b0273f..b8e084f1a7 100644
--- a/components/soc/esp32c5/mp/include/soc/pcr_reg.h
+++ b/components/soc/esp32c5/include/soc/pcr_reg.h
@@ -226,7 +226,7 @@ extern "C" {
 #define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
 /** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
  *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+ *  clock-source to drive clk_mspi_fast. Only available when the clock-source is a
  *  low-speed clock-source such as XTAL/FOSC.
  */
 #define PCR_MSPI_FAST_DIV_NUM    0x000000FFU
@@ -1396,7 +1396,7 @@ extern "C" {
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
 #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  Configures the clock source of PVT MONITER.\\
+ *  Configures the clock source of PVT MONITOR.\\
  *  0 (default): XTAL_CLK\\
  *  1: PLL_F160M_CLK\\
  */
@@ -1983,8 +1983,8 @@ extern "C" {
  */
 #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
 /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+ *  Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
  *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
  */
 #define PCR_CPU_DIV_NUM    0x000000FFU
@@ -1997,8 +1997,8 @@ extern "C" {
  */
 #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
 /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+ *  Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
+ *  div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
  *  low-speed clock-source such as XTAL/FOSC, and should be used together with
  *  PCR_CPU_DIV_NUM.
  */
@@ -2025,7 +2025,7 @@ extern "C" {
 #define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
 #define PCR_APB_DECREASE_DIV_NUM_S  0
 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+ *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
  *  div1(default)/div2/div4 of clk_ahb.
  */
 #define PCR_APB_DIV_NUM    0x000000FFU
@@ -2057,72 +2057,72 @@ extern "C" {
  */
 #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128)
 /** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_240M_CLK_EN    (BIT(0))
 #define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
 #define PCR_PLL_240M_CLK_EN_V  0x00000001U
 #define PCR_PLL_240M_CLK_EN_S  0
 /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_160M_CLK_EN    (BIT(1))
 #define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
 #define PCR_PLL_160M_CLK_EN_V  0x00000001U
 #define PCR_PLL_160M_CLK_EN_S  1
 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_120M_CLK_EN    (BIT(2))
 #define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
 #define PCR_PLL_120M_CLK_EN_V  0x00000001U
 #define PCR_PLL_120M_CLK_EN_S  2
 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_80M_CLK_EN    (BIT(3))
 #define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
 #define PCR_PLL_80M_CLK_EN_V  0x00000001U
 #define PCR_PLL_80M_CLK_EN_S  3
 /** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_60M_CLK_EN    (BIT(4))
 #define PCR_PLL_60M_CLK_EN_M  (PCR_PLL_60M_CLK_EN_V << PCR_PLL_60M_CLK_EN_S)
 #define PCR_PLL_60M_CLK_EN_V  0x00000001U
 #define PCR_PLL_60M_CLK_EN_S  4
 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_48M_CLK_EN    (BIT(5))
 #define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
 #define PCR_PLL_48M_CLK_EN_V  0x00000001U
 #define PCR_PLL_48M_CLK_EN_S  5
 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_40M_CLK_EN    (BIT(6))
 #define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
 #define PCR_PLL_40M_CLK_EN_V  0x00000001U
 #define PCR_PLL_40M_CLK_EN_S  6
 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1;
- *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_20M_CLK_EN    (BIT(7))
 #define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
 #define PCR_PLL_20M_CLK_EN_V  0x00000001U
 #define PCR_PLL_20M_CLK_EN_S  7
 /** PCR_PLL_12M_CLK_EN : R/W; bitpos: [8]; default: 1;
- *  This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+ *  This field is used to open 12 MHz clock (div40 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
  */
 #define PCR_PLL_12M_CLK_EN    (BIT(8))
 #define PCR_PLL_12M_CLK_EN_M  (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S)
diff --git a/components/soc/esp32c5/mp/include/soc/pcr_struct.h b/components/soc/esp32c5/include/soc/pcr_struct.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/pcr_struct.h
rename to components/soc/esp32c5/include/soc/pcr_struct.h
index 8cb23928b6..6ffbbb0ba7 100644
--- a/components/soc/esp32c5/mp/include/soc/pcr_struct.h
+++ b/components/soc/esp32c5/include/soc/pcr_struct.h
@@ -192,7 +192,7 @@ typedef union {
     struct {
         /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0;
          *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
+         *  clock-source to drive clk_mspi_fast. Only available when the clock-source is a
          *  low-speed clock-source such as XTAL/FOSC.
          */
         uint32_t mspi_fast_div_num:8;
@@ -1195,7 +1195,7 @@ typedef union {
         uint32_t pvt_monitor_func_clk_div_num:4;
         uint32_t reserved_4:16;
         /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  Configures the clock source of PVT MONITER.\\
+         *  Configures the clock source of PVT MONITOR.\\
          *  0 (default): XTAL_CLK\\
          *  1: PLL_F160M_CLK\\
          */
@@ -1706,8 +1706,8 @@ typedef union {
 typedef union {
     struct {
         /** cpu_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
+         *  Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
          *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
          */
         uint32_t cpu_div_num:8;
@@ -1722,8 +1722,8 @@ typedef union {
 typedef union {
     struct {
         /** ahb_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
-         *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
+         *  Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
+         *  div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
          *  low-speed clock-source such as XTAL/FOSC, and should be used together with
          *  PCR_CPU_DIV_NUM.
          */
@@ -1749,7 +1749,7 @@ typedef union {
          */
         uint32_t apb_decrease_div_num:8;
         /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
+         *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
          *  div1(default)/div2/div4 of clk_ahb.
          */
         uint32_t apb_div_num:8;
@@ -1764,48 +1764,48 @@ typedef union {
 typedef union {
     struct {
         /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_240m_clk_en:1;
         /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
-         *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_160m_clk_en:1;
         /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
-         *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_120m_clk_en:1;
         /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
-         *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_80m_clk_en:1;
         /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  This field is used to open 60 MHz clock (div8 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_60m_clk_en:1;
         /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_48m_clk_en:1;
         /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1;
-         *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_40m_clk_en:1;
         /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1;
-         *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_20m_clk_en:1;
         /** pll_12m_clk_en : R/W; bitpos: [8]; default: 1;
-         *  This field is used to open 12 MHz clock (div40 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
+         *  This field is used to open 12 MHz clock (div40 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
          */
         uint32_t pll_12m_clk_en:1;
         uint32_t reserved_9:23;
diff --git a/components/soc/esp32c5/mp/include/soc/periph_defs.h b/components/soc/esp32c5/include/soc/periph_defs.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/periph_defs.h
rename to components/soc/esp32c5/include/soc/periph_defs.h
diff --git a/components/soc/esp32c5/mp/include/soc/pmu_icg_mapping.h b/components/soc/esp32c5/include/soc/pmu_icg_mapping.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pmu_icg_mapping.h
rename to components/soc/esp32c5/include/soc/pmu_icg_mapping.h
diff --git a/components/soc/esp32c5/mp/include/soc/pmu_reg.h b/components/soc/esp32c5/include/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pmu_reg.h
rename to components/soc/esp32c5/include/soc/pmu_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/pmu_struct.h b/components/soc/esp32c5/include/soc/pmu_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pmu_struct.h
rename to components/soc/esp32c5/include/soc/pmu_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/pvt_reg.h b/components/soc/esp32c5/include/soc/pvt_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pvt_reg.h
rename to components/soc/esp32c5/include/soc/pvt_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/pvt_struct.h b/components/soc/esp32c5/include/soc/pvt_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/pvt_struct.h
rename to components/soc/esp32c5/include/soc/pvt_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/reg_base.h
rename to components/soc/esp32c5/include/soc/reg_base.h
diff --git a/components/soc/esp32c5/mp/include/soc/regi2c_bbpll.h b/components/soc/esp32c5/include/soc/regi2c_bbpll.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/regi2c_bbpll.h
rename to components/soc/esp32c5/include/soc/regi2c_bbpll.h
diff --git a/components/soc/esp32c5/mp/include/soc/regi2c_defs.h b/components/soc/esp32c5/include/soc/regi2c_defs.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/regi2c_defs.h
rename to components/soc/esp32c5/include/soc/regi2c_defs.h
diff --git a/components/soc/esp32c5/mp/include/soc/regi2c_dig_reg.h b/components/soc/esp32c5/include/soc/regi2c_dig_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/regi2c_dig_reg.h
rename to components/soc/esp32c5/include/soc/regi2c_dig_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/reset_reasons.h b/components/soc/esp32c5/include/soc/reset_reasons.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/reset_reasons.h
rename to components/soc/esp32c5/include/soc/reset_reasons.h
index 7f221eaf8c..f86a798e28 100644
--- a/components/soc/esp32c5/mp/include/soc/reset_reasons.h
+++ b/components/soc/esp32c5/include/soc/reset_reasons.h
@@ -48,7 +48,7 @@ typedef enum {
     RESET_REASON_CORE_USB_JTAG   = 0x16, // USB JTAG resets the digital core (hp system)
     RESET_REASON_CPU0_JTAG       = 0x18, // JTAG resets the CPU 0
     RESET_REASON_CORE_PWR_GLITCH = 0x19, // Glitch on power resets the digital core and rtc module
-    RESET_REASON_CPU0_LOCKUP     = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this)
+    RESET_REASON_CPU0_LOCKUP     = 0x1A, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this)
 } soc_reset_reason_t;
 
 
diff --git a/components/soc/esp32c5/mp/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/retention_periph_defs.h
rename to components/soc/esp32c5/include/soc/retention_periph_defs.h
diff --git a/components/soc/esp32c5/mp/include/soc/rmt_reg.h b/components/soc/esp32c5/include/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/rmt_reg.h
rename to components/soc/esp32c5/include/soc/rmt_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/rmt_struct.h b/components/soc/esp32c5/include/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/rmt_struct.h
rename to components/soc/esp32c5/include/soc/rmt_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/rsa_reg.h b/components/soc/esp32c5/include/soc/rsa_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/rsa_reg.h
rename to components/soc/esp32c5/include/soc/rsa_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/rsa_struct.h b/components/soc/esp32c5/include/soc/rsa_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/rsa_struct.h
rename to components/soc/esp32c5/include/soc/rsa_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/rtc_io_reg.h b/components/soc/esp32c5/include/soc/rtc_io_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/rtc_io_reg.h
rename to components/soc/esp32c5/include/soc/rtc_io_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/rtc_io_struct.h b/components/soc/esp32c5/include/soc/rtc_io_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/rtc_io_struct.h
rename to components/soc/esp32c5/include/soc/rtc_io_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/sha_reg.h b/components/soc/esp32c5/include/soc/sha_reg.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/sha_reg.h
rename to components/soc/esp32c5/include/soc/sha_reg.h
index ab9f346e77..4dd7f4a2d9 100644
--- a/components/soc/esp32c5/mp/include/soc/sha_reg.h
+++ b/components/soc/esp32c5/include/soc/sha_reg.h
@@ -161,7 +161,7 @@ extern "C" {
 #define SHA_DATE_S  0
 
 /** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
+ *  Sha H memory which contains intermediate hash or final hash.
  */
 #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
 #define SHA_H_MEM_SIZE_BYTES 64
diff --git a/components/soc/esp32c5/mp/include/soc/sha_struct.h b/components/soc/esp32c5/include/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/sha_struct.h
rename to components/soc/esp32c5/include/soc/sha_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/soc.h
rename to components/soc/esp32c5/include/soc/soc.h
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index 92ea81c451..9f2762b069 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -1,17 +1,581 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/*
+ * These defines are parsed and imported as kconfig variables via the script
+ * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
+ *
+ * If this file is changed the script will automatically run the script
+ * and generate the kconfig variables as part of the pre-commit hooks.
+ *
+ * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md`
+ */
+
 #pragma once
 
-#include "sdkconfig.h"
+/*-------------------------- COMMON CAPS ---------------------------------------*/
+// #define SOC_ADC_SUPPORTED               1  // TODO: [ESP32C5] IDF-8701
+// #define SOC_DEDICATED_GPIO_SUPPORTED    1  // TODO: [ESP32C5] IDF-8725
+#define SOC_UART_SUPPORTED              1     // TODO: [ESP32C5] IDF-8722
+#define SOC_GDMA_SUPPORTED              1
+#define SOC_AHB_GDMA_SUPPORTED          1
+#define SOC_GPTIMER_SUPPORTED           1
+#define SOC_PCNT_SUPPORTED              1
+#define SOC_MCPWM_SUPPORTED             1
+// #define SOC_TWAI_SUPPORTED              1  // TODO: [ESP32C5] IDF-8691
+// #define SOC_ETM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8693
+// #define SOC_PARLIO_SUPPORTED            1  // TODO: [ESP32C5] IDF-8685, IDF-8686
+#define SOC_ASYNC_MEMCPY_SUPPORTED      1
+// #define SOC_USB_SERIAL_JTAG_SUPPORTED   1  // TODO: [ESP32C5] IDF-8721
+// #define SOC_TEMP_SENSOR_SUPPORTED       1  // TODO: [ESP32C5] IDF-8727
+// #define SOC_WIFI_SUPPORTED              1  // TODO: [ESP32C5] IDF-8851
+#define SOC_SUPPORTS_SECURE_DL_MODE     1
+// #define SOC_LP_CORE_SUPPORTED           1  // TODO: [ESP32C5] IDF-8637
+#define SOC_EFUSE_KEY_PURPOSE_FIELD     1
+#define SOC_EFUSE_SUPPORTED             1
+#define SOC_RTC_FAST_MEM_SUPPORTED      1
+#define SOC_RTC_MEM_SUPPORTED           1
+#define SOC_I2S_SUPPORTED               1
+#define SOC_RMT_SUPPORTED               1
+// #define SOC_SDM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8687
+#define SOC_GPSPI_SUPPORTED             1
+#define SOC_LEDC_SUPPORTED              1
+// #define SOC_I2C_SUPPORTED               1  // TODO: [ESP32C5] IDF-8694, IDF-8696
+#define SOC_SYSTIMER_SUPPORTED          1     // TODO: [ESP32C5] IDF-8707
+#define SOC_AES_SUPPORTED               1
+#define SOC_MPI_SUPPORTED               1
+#define SOC_SHA_SUPPORTED               1
+#define SOC_RSA_SUPPORTED               1
+#define SOC_HMAC_SUPPORTED              1
+#define SOC_DIG_SIGN_SUPPORTED          1
+#define SOC_ECC_SUPPORTED               1
+#define SOC_ECC_EXTENDED_MODES_SUPPORTED   1
+#define SOC_FLASH_ENC_SUPPORTED         1
+#define SOC_SECURE_BOOT_SUPPORTED       1
+// #define SOC_BOD_SUPPORTED               1  // TODO: [ESP32C5] IDF-8647
+// #define SOC_APM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8614, IDF-8615
+// #define SOC_PMU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8667
+// #define SOC_PAU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8638
+// #define SOC_LP_TIMER_SUPPORTED          1  // TODO: [ESP32C5] IDF-8636
+// #define SOC_LP_AON_SUPPORTED            1  // TODO: [ESP32C5] IDF-8638
+// #define SOC_LP_PERIPHERALS_SUPPORTED    1  // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719
+// #define SOC_LP_I2C_SUPPORTED            1  // TODO: [ESP32C5] IDF-8634
+// #define SOC_ULP_LP_UART_SUPPORTED       1  // TODO: [ESP32C5] IDF-8633
+// #define SOC_CLK_TREE_SUPPORTED          1  // TODO: [ESP32C5] IDF-8642
+// #define SOC_ASSIST_DEBUG_SUPPORTED      1  // TODO: [ESP32C5] IDF-8663
+// #define SOC_WDT_SUPPORTED               1  // TODO: [ESP32C5] IDF-8650
+#define SOC_SPI_FLASH_SUPPORTED         1     // TODO: [ESP32C5] IDF-8715
+// #define SOC_BITSCRAMBLER_SUPPORTED      1  // TODO: [ESP32C5] IDF-8711
+#define SOC_ECDSA_SUPPORTED             1
+// #define SOC_KEY_MANAGER_SUPPORTED       1  // TODO: [ESP32C5] IDF-8621
+// #define SOC_HUK_SUPPORTED               1  // TODO: [ESP32C5] IDF-8617
+// #define SOC_MODEM_CLOCK_SUPPORTED       1  // TODO: [ESP32C5] IDF-8845
+// #define SOC_PM_SUPPORTED                1  // TODO: [ESP32C5] IDF-8643
 
-// TODO: IDF-9197 This file is created to glob the soc_caps correctly in esp-docs
+/*-------------------------- XTAL CAPS ---------------------------------------*/
+#define SOC_XTAL_SUPPORT_40M            1
+#define SOC_XTAL_SUPPORT_48M            1
 
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-#include "../../beta3/include/soc/soc_caps.h"   // recursive, condition: IDF_TARGET_ESP32C5_BETA3_VERSION
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-#include "../../mp/include/soc/soc_caps.h"      // recursive, condition: IDF_TARGET_ESP32C5_MP_VERSION
-#endif
+/*-------------------------- AES CAPS -----------------------------------------*/
+#define SOC_AES_SUPPORT_DMA     (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_AES_GDMA            (1)
+
+#define SOC_AES_SUPPORT_AES_128 (1)
+#define SOC_AES_SUPPORT_AES_256 (1)
+
+/*-------------------------- ADC CAPS -------------------------------*/
+/*!< SAR ADC Module*/
+// #define SOC_ADC_DIG_CTRL_SUPPORTED              1
+// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
+// #define SOC_ADC_MONITOR_SUPPORTED               1
+// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
+// #define SOC_ADC_DMA_SUPPORTED                   1
+#define SOC_ADC_PERIPH_NUM                      (1U)
+// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (7)
+#define SOC_ADC_MAX_CHANNEL_NUM                 (7)
+// #define SOC_ADC_ATTEN_NUM                       (4)
+
+/*!< Digital */
+// #define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
+// #define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
+// #define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
+// #define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
+// #define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
+// #define SOC_ADC_DIGI_MONITOR_NUM                (2)
+// #define SOC_ADC_DIGI_RESULT_BYTES               (4)
+// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
+/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
+// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
+// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+
+/*!< RTC */
+// #define SOC_ADC_RTC_MIN_BITWIDTH                (12)
+// #define SOC_ADC_RTC_MAX_BITWIDTH                (12)
+
+/*!< Calibration */
+// #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
+// #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
+// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
+
+/*!< Interrupt */
+// #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
+
+/*!< ADC power control is shared by PWDET */
+// #define SOC_ADC_SHARED_POWER                    1
+
+// ESP32C5-TODO: Copy from esp32C5, need check
+/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
+// #define SOC_APB_BACKUP_DMA              (0)
+
+/*-------------------------- BROWNOUT CAPS -----------------------------------*/
+// #define SOC_BROWNOUT_RESET_SUPPORTED 1
+
+/*-------------------------- CACHE CAPS --------------------------------------*/
+#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_CACHE_FREEZE_SUPPORTED              1
+
+/*-------------------------- CPU CAPS ----------------------------------------*/
+#define SOC_CPU_CORES_NUM               (1U)
+#define SOC_CPU_INTR_NUM                32
+#define SOC_CPU_HAS_FLEXIBLE_INTC       1
+#define SOC_INT_CLIC_SUPPORTED          1
+#define SOC_INT_HW_NESTED_SUPPORTED     1       // Support for hardware interrupts nesting
+#define SOC_BRANCH_PREDICTOR_SUPPORTED  1
+
+#define SOC_CPU_BREAKPOINTS_NUM         4
+#define SOC_CPU_WATCHPOINTS_NUM         4
+#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE         0x100 // bytes
+
+#define SOC_CPU_HAS_PMA                 1
+#define SOC_CPU_IDRAM_SPLIT_USING_PMP   1
+
+/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
+/** The maximum length of a Digital Signature in bits. */
+#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
+
+/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
+#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
+
+/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
+    See TRM DS chapter for more details */
+#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
+
+/*-------------------------- DMA Common CAPS ----------------------------------------*/
+#define SOC_DMA_CAN_ACCESS_FLASH 1 /*!< DMA can access Flash memory */
+
+/*-------------------------- GDMA CAPS -------------------------------------*/
+#define SOC_AHB_GDMA_VERSION            2
+#define SOC_GDMA_NUM_GROUPS_MAX         1U
+#define SOC_GDMA_PAIRS_PER_GROUP_MAX    3
+// #define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule TODO: IDF-9224
+// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1  // TODO: IDF-9225
+
+/*-------------------------- ETM CAPS --------------------------------------*/
+// #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
+// #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
+
+/*-------------------------- GPIO CAPS ---------------------------------------*/
+// ESP32-C5 has 1 GPIO peripheral
+#define SOC_GPIO_PORT                      1U
+#define SOC_GPIO_PIN_COUNT                 29
+// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
+// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
+#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER      1
+
+// GPIO peripheral has the ETM extension
+// #define SOC_GPIO_SUPPORT_ETM          1
+
+// Target has the full LP IO subsystem
+// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
+// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
+// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  // TODO: [ESP32C5] IDF-8719
+
+#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
+
+#define SOC_GPIO_IN_RANGE_MAX           28
+#define SOC_GPIO_OUT_RANGE_MAX          28
+
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
+
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL
+
+// Support to force hold all IOs
+#define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
+// Support to hold a single digital I/O when the digital domain is powered off
+#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
+
+// The Clock Out signal is route to the pin by GPIO matrix
+// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
+
+/*-------------------------- RTCIO CAPS --------------------------------------*/
+#define SOC_RTCIO_PIN_COUNT                 0UL
+// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1  /* This macro indicates that the target has separate RTC IOMUX hardware feature,
+                                            //  * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
+                                            //  * when the pins are switched to RTC function.
+                                            //  */
+// #define SOC_RTCIO_HOLD_SUPPORTED            1
+// #define SOC_RTCIO_WAKE_SUPPORTED            1
+
+/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
+// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
+// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
+// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
+
+/*-------------------------- I2C CAPS ----------------------------------------*/
+// ESP32-C5 has 1 I2C
+#define SOC_I2C_NUM                 (1U)
+#define SOC_HP_I2C_NUM              (1U)
+
+// #define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
+// #define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
+// #define SOC_I2C_SUPPORT_SLAVE       (1)
+
+// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
+// #define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+
+// #define SOC_I2C_SUPPORT_XTAL        (1)
+// #define SOC_I2C_SUPPORT_RTC         (1)
+// #define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
+// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
+// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
+// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
+// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
+
+// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693
+
+/*-------------------------- LP_I2C CAPS -------------------------------------*/
+// ESP32-C5 has 1 LP_I2C
+// #define SOC_LP_I2C_NUM              (1U)
+
+// #define SOC_LP_I2C_FIFO_LEN         (16) /*!< LP_I2C hardware FIFO depth */
+
+/*-------------------------- I2S CAPS ----------------------------------------*/
+#define SOC_I2S_NUM                 (1U)
+#define SOC_I2S_HW_VERSION_2        (1)
+#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
+// #define SOC_I2S_SUPPORTS_RX_RECOMB  (1) //TODO[C5] IDF-9966
+#define SOC_I2S_SUPPORTS_XTAL       (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
+#define SOC_I2S_SUPPORTS_PLL_F240M  (1)
+#define SOC_I2S_SUPPORTS_PCM        (1)
+#define SOC_I2S_SUPPORTS_PDM        (1)
+#define SOC_I2S_SUPPORTS_PDM_TX     (1)
+#define SOC_I2S_PDM_MAX_TX_LINES    (2)
+#define SOC_I2S_SUPPORTS_TDM        (1)
+#define SOC_I2S_TDM_FULL_DATA_WIDTH (1)  /*!< No limitation to data bit width when using multiple slots */
+
+/*-------------------------- LEDC CAPS ---------------------------------------*/
+#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_CHANNEL_NUM                (6)
+#define SOC_LEDC_TIMER_BIT_WIDTH            (20)
+#define SOC_LEDC_SUPPORT_FADE_STOP          (1)
+#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
+#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
+#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+
+/*-------------------------- MMU CAPS ----------------------------------------*/
+// TODO: [ESP32C5] IDF-8658
+// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (1)
+#define SOC_MMU_PERIPH_NUM                    (1U)
+#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM     (1U)
+#define SOC_MMU_DI_VADDR_SHARED               (1) /*!< D/I vaddr are shared */
+
+/*-------------------------- MPU CAPS ----------------------------------------*/
+// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
+// #define SOC_MPU_MIN_REGION_SIZE                   0x20000000U
+// #define SOC_MPU_REGIONS_MAX_NUM                   8
+// #define SOC_MPU_REGION_RO_SUPPORTED               0
+// #define SOC_MPU_REGION_WO_SUPPORTED               0
+
+/*-------------------------- PCNT CAPS ---------------------------------------*/
+#define SOC_PCNT_GROUPS                       1U
+#define SOC_PCNT_UNITS_PER_GROUP              4
+#define SOC_PCNT_CHANNELS_PER_UNIT            2
+#define SOC_PCNT_THRES_POINT_PER_UNIT         2
+#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
+#define SOC_PCNT_SUPPORT_CLEAR_SIGNAL         1
+// #define SOC_PCNT_SUPPORT_STEP_NOTIFY          1 // IDF-7984
+
+/*--------------------------- RMT CAPS ---------------------------------------*/
+#define SOC_RMT_GROUPS                        1U /*!< One RMT group */
+#define SOC_RMT_TX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Transmit */
+#define SOC_RMT_RX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Receive */
+#define SOC_RMT_CHANNELS_PER_GROUP            4  /*!< Total 4 channels */
+#define SOC_RMT_MEM_WORDS_PER_CHANNEL         48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
+#define SOC_RMT_SUPPORT_RX_PINGPONG           1  /*!< Support Ping-Pong mode on RX path */
+#define SOC_RMT_SUPPORT_RX_DEMODULATION       1  /*!< Support signal demodulation on RX path (i.e. remove carrier) */
+#define SOC_RMT_SUPPORT_TX_ASYNC_STOP         1  /*!< Support stop transmission asynchronously */
+#define SOC_RMT_SUPPORT_TX_LOOP_COUNT         1  /*!< Support transmit specified number of cycles in loop mode */
+#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP     1  /*!< Hardware support of auto-stop in loop mode */
+#define SOC_RMT_SUPPORT_TX_SYNCHRO            1  /*!< Support coordinate a group of TX channels to start simultaneously */
+#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY  1  /*!< TX carrier can be modulated to data phase only */
+#define SOC_RMT_SUPPORT_XTAL                  1  /*!< Support set XTAL clock as the RMT clock source */
+// #define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST as the RMT clock source */
+
+/*-------------------------- MCPWM CAPS --------------------------------------*/
+#define SOC_MCPWM_GROUPS                         1U ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
+#define SOC_MCPWM_TIMERS_PER_GROUP               3  ///< The number of timers that each group has
+#define SOC_MCPWM_OPERATORS_PER_GROUP            3  ///< The number of operators that each group has
+#define SOC_MCPWM_COMPARATORS_PER_OPERATOR       2  ///< The number of comparators that each operator has
+#define SOC_MCPWM_GENERATORS_PER_OPERATOR        2  ///< The number of generators that each operator has
+#define SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR 2  ///< The number of event comparators that each operator has
+#define SOC_MCPWM_TRIGGERS_PER_OPERATOR          2  ///< The number of triggers that each operator has
+#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP          3  ///< The number of fault signal detectors that each group has
+#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP       1  ///< The number of capture timers that each group has
+#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER     3  ///< The number of capture channels that each capture timer has
+#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP        3  ///< The number of GPIO synchros that each group has
+#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE           1  ///< Software sync event can be routed to its output
+// #define SOC_MCPWM_SUPPORT_ETM                    1  ///< Support ETM (Event Task Matrix)
+#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR       1  ///< Support event comparator (based on ETM)
+#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP         1  ///< Capture timer shares clock with other PWM timers
+
+/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
+// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
+
+/*-------------------------- PARLIO CAPS --------------------------------------*/
+// #define SOC_PARLIO_GROUPS                    1U  /*!< Number of parallel IO peripherals */
+// #define SOC_PARLIO_TX_UNITS_PER_GROUP        1U  /*!< number of TX units in each group */
+// #define SOC_PARLIO_RX_UNITS_PER_GROUP        1U  /*!< number of RX units in each group */
+// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
+// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
+// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT     1   /*!< TX and RX unit share the same interrupt source number */
+
+/*--------------------------- MPI CAPS ---------------------------------------*/
+#define SOC_MPI_MEM_BLOCKS_NUM (4)
+#define SOC_MPI_OPERATIONS_NUM (3)
+
+/*--------------------------- RSA CAPS ---------------------------------------*/
+#define SOC_RSA_MAX_BIT_LEN    (3072)
+
+/*--------------------------- SHA CAPS ---------------------------------------*/
+
+/* Max amount of bytes in a single DMA operation is 4095,
+   for SHA this means that the biggest safe amount of bytes is
+   31 blocks of 128 bytes = 3968
+*/
+#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
+#define SOC_SHA_SUPPORT_DMA             (1)
+
+/* The SHA engine is able to resume hashing from a user */
+#define SOC_SHA_SUPPORT_RESUME          (1)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_SHA_GDMA             (1)
+
+/* Supported HW algorithms */
+#define SOC_SHA_SUPPORT_SHA1            (1)
+#define SOC_SHA_SUPPORT_SHA224          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
+
+/*--------------------------- ECDSA CAPS ---------------------------------------*/
+#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY     (1)
+
+/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
+// #define SOC_SDM_GROUPS               1U
+// #define SOC_SDM_CHANNELS_PER_GROUP   4
+// #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
+// #define SOC_SDM_CLK_SUPPORT_XTAL     1
+
+/*-------------------------- SPI CAPS ----------------------------------------*/
+#define SOC_SPI_PERIPH_NUM          2
+#define SOC_SPI_PERIPH_CS_NUM(i)    6
+#define SOC_SPI_MAX_CS_NUM          6
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
+
+#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
+#define SOC_SPI_SUPPORT_CD_SIG              1
+#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+#define SOC_SPI_SUPPORT_CLK_XTAL            1
+// #define SOC_SPI_SUPPORT_CLK_PLL_F80M        1
+// #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
+
+// Peripheral supports DIO, DOUT, QIO, or QOUT
+// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
+#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)  ({(void)host_id; 1;})
+
+#define SOC_MEMSPI_IS_INDEPENDENT 1
+#define SOC_SPI_MAX_PRE_DIVIDER 16
+
+/*-------------------------- SPI MEM CAPS ---------------------------------------*/
+// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
+// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
+// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
+// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
+// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
+// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
+// #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
+
+// TODO: [ESP32C5] IDF-8649
+#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED         1
+#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
+#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
+
+/*-------------------------- SYSTIMER CAPS ----------------------------------*/
+// TODO: [ESP32C5] IDF-8707
+#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
+#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
+#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
+#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
+#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
+#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
+#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
+#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+// #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event
+
+/*-------------------------- LP_TIMER CAPS ----------------------------------*/
+// #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
+// #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
+
+/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
+#define SOC_TIMER_GROUPS                  (2)
+#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
+#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
+#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
+#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
+// #define SOC_TIMER_SUPPORT_ETM             (1)
+// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
+
+/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
+// #define SOC_MWDT_SUPPORT_XTAL              (1)
+
+/*-------------------------- TWAI CAPS ---------------------------------------*/
+// #define SOC_TWAI_CONTROLLER_NUM         2
+// #define SOC_TWAI_CLK_SUPPORT_XTAL       1
+// #define SOC_TWAI_BRP_MIN                2
+// #define SOC_TWAI_BRP_MAX                32768
+// #define SOC_TWAI_SUPPORTS_RX_STATUS     1
+
+/*-------------------------- eFuse CAPS----------------------------*/
+// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
+// #define SOC_EFUSE_DIS_PAD_JTAG 1
+// #define SOC_EFUSE_DIS_USB_JTAG 1
+// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
+// #define SOC_EFUSE_SOFT_DIS_JTAG 1
+// #define SOC_EFUSE_DIS_ICACHE 1
+#define SOC_EFUSE_ECDSA_KEY 1
+
+/*-------------------------- Secure Boot CAPS----------------------------*/
+#define SOC_SECURE_BOOT_V2_RSA              1
+#define SOC_SECURE_BOOT_V2_ECC              1
+#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
+#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS   1
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY  1
+
+/*-------------------------- Flash Encryption CAPS----------------------------*/
+#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (64)
+#define SOC_FLASH_ENCRYPTION_XTS_AES        1
+#define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
+
+/*------------------------ Anti DPA (Security) CAPS --------------------------*/
+// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED     1
+
+/*-------------------------- UART CAPS ---------------------------------------*/
+// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
+#define SOC_UART_NUM                    (3)
+#define SOC_UART_HP_NUM                 (2)
+#define SOC_UART_LP_NUM                 (1U)
+#define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
+#define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
+// #define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
+// #define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
+// #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */
+#define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
+// #define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
+
+// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
+// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
+
+/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
+// #define SOC_COEX_HW_PTI                 (1)
+
+/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
+// #define SOC_EXTERNAL_COEX_ADVANCE              (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
+// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE       (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
+
+/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
+// #define SOC_PHY_DIG_REGS_MEM_SIZE       (21*4)
+
+/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
+// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
+
+/*-------------------------- Power Management CAPS ----------------------------*/
+// #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
+// #define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
+// #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
+// #define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
+// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
+// #define SOC_PM_SUPPORT_CPU_PD           (1)
+#define SOC_PM_SUPPORT_MODEM_PD         (1)
+#define SOC_PM_SUPPORT_XTAL32K_PD       (1)
+#define SOC_PM_SUPPORT_RC32K_PD         (1)
+#define SOC_PM_SUPPORT_RC_FAST_PD       (1)
+#define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
+#define SOC_PM_SUPPORT_TOP_PD           (1)
+#define SOC_PM_SUPPORT_HP_AON_PD        (1)
+// #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
+#define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
+
+// #define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
+/* macro redefine for pass esp_wifi headers md5sum check */
+// #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
+
+// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
+
+// #define SOC_PM_CPU_RETENTION_BY_SW          (1)
+// #define SOC_PM_MODEM_RETENTION_BY_REGDMA    (1)
+// #define SOC_PM_RETENTION_HAS_CLOCK_BUG      (1)
+
+// #define SOC_PM_PAU_LINK_NUM             (4)
+
+/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
+// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1) // TODO: IDF-8642
+#define SOC_MODEM_CLOCK_IS_INDEPENDENT            (1)
+
+#define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
+#define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
+#define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
+
+#define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
+
+/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
+// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
+// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)
+// #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
+
+/*------------------------------------ WI-FI CAPS ------------------------------------*/
+// #define SOC_WIFI_HW_TSF                     (1)    /*!< Support hardware TSF */
+// #define SOC_WIFI_FTM_SUPPORT                (0)    /*!< Support FTM */
+// #define SOC_WIFI_GCMP_SUPPORT               (1)    /*!< Support GCMP(GCMP128 and GCMP256) */
+// #define SOC_WIFI_WAPI_SUPPORT               (1)    /*!< Support WAPI */
+// #define SOC_WIFI_CSI_SUPPORT                (1)    /*!< Support CSI */
+// #define SOC_WIFI_MESH_SUPPORT               (1)    /*!< Support WIFI MESH */
+// #define SOC_WIFI_HE_SUPPORT                 (1)    /*!< Support Wi-Fi 6 */
+
+/*---------------------------------- Bluetooth CAPS ----------------------------------*/
+// #define SOC_BLE_SUPPORTED               (1)    /*!< Support Bluetooth Low Energy hardware */
+// #define SOC_BLE_MESH_SUPPORTED          (1)    /*!< Support BLE MESH */
+// #define SOC_ESP_NIMBLE_CONTROLLER       (1)    /*!< Support BLE EMBEDDED controller V1 */
+// #define SOC_BLE_50_SUPPORTED            (1)    /*!< Support Bluetooth 5.0 */
+// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1)   /*!< Support BLE device privacy mode */
+// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1)    /*!< Support Bluetooth Power Control */
+// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED  (1)    /*!< Support For BLE Periodic Adv Enhancements */
+// #define SOC_BLUFI_SUPPORTED             (1)    /*!< Support BLUFI */
+// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1)    /*!< Support multiple connections optimization */
+
+// #define SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND (1)
+
+/*------------------------------------- PHY CAPS -------------------------------------*/
+// #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
diff --git a/components/soc/esp32c5/mp/include/soc/soc_etm_reg.h b/components/soc/esp32c5/include/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/soc_etm_reg.h
rename to components/soc/esp32c5/include/soc/soc_etm_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/soc_etm_source.h b/components/soc/esp32c5/include/soc/soc_etm_source.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/soc_etm_source.h
rename to components/soc/esp32c5/include/soc/soc_etm_source.h
diff --git a/components/soc/esp32c5/mp/include/soc/soc_etm_struct.h b/components/soc/esp32c5/include/soc/soc_etm_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/soc_etm_struct.h
rename to components/soc/esp32c5/include/soc/soc_etm_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/soc_pins.h b/components/soc/esp32c5/include/soc/soc_pins.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/soc_pins.h
rename to components/soc/esp32c5/include/soc/soc_pins.h
diff --git a/components/soc/esp32c5/mp/include/soc/spi1_mem_reg.h b/components/soc/esp32c5/include/soc/spi1_mem_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/spi1_mem_reg.h
rename to components/soc/esp32c5/include/soc/spi1_mem_reg.h
index d92aeec9a6..13e4c84156 100644
--- a/components/soc/esp32c5/mp/include/soc/spi1_mem_reg.h
+++ b/components/soc/esp32c5/include/soc/spi1_mem_reg.h
@@ -321,7 +321,7 @@ extern "C" {
 /** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
+ *  SPI clock is always on.
  */
 #define SPI_MEM_CLK_MODE    0x00000003U
 #define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
@@ -1153,7 +1153,7 @@ extern "C" {
 #define SPI_MEM_WAITI_IDLE_DELAY_TIME_V  0x000003FFU
 #define SPI_MEM_WAITI_IDLE_DELAY_TIME_S  0
 /** SPI_MEM_WAITI_IDLE_DELAY_TIME_EN : R/W; bitpos: [10]; default: 0;
- *  Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable.
+ *  Enable SPI1 wait idle gap time count function. 1: Enable. 0: Disable.
  */
 #define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN    (BIT(10))
 #define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_M  (SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_V << SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_S)
@@ -1301,7 +1301,7 @@ extern "C" {
 #define SPI_MEM_MST_ST_END_INT_RAW_S  4
 /** SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
  *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
- *  chip is loosing power and RTC module sends out brown out close flash request to
+ *  chip is losing power and RTC module sends out brown out close flash request to
  *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  *  and MSPI returns to idle state. 0: Others.
  */
diff --git a/components/soc/esp32c5/mp/include/soc/spi1_mem_struct.h b/components/soc/esp32c5/include/soc/spi1_mem_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/spi1_mem_struct.h
rename to components/soc/esp32c5/include/soc/spi1_mem_struct.h
index 9c5ced7384..a7306b71c7 100644
--- a/components/soc/esp32c5/mp/include/soc/spi1_mem_struct.h
+++ b/components/soc/esp32c5/include/soc/spi1_mem_struct.h
@@ -334,7 +334,7 @@ typedef union {
         /** clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on.
+         *  SPI clock is always on.
          */
         uint32_t clk_mode:2;
         /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
@@ -721,7 +721,7 @@ typedef union {
          */
         uint32_t waiti_idle_delay_time:10;
         /** waiti_idle_delay_time_en : R/W; bitpos: [10]; default: 0;
-         *  Enable SPI1 wait idle gap time count functon. 1: Enable. 0: Disable.
+         *  Enable SPI1 wait idle gap time count function. 1: Enable. 0: Disable.
          */
         uint32_t waiti_idle_delay_time_en:1;
         uint32_t reserved_11:21;
@@ -1149,7 +1149,7 @@ typedef union {
         uint32_t reserved_5:5;
         /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
          *  The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-         *  chip is loosing power and RTC module sends out brown out close flash request to
+         *  chip is losing power and RTC module sends out brown out close flash request to
          *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
          *  and MSPI returns to idle state. 0: Others.
          */
diff --git a/components/soc/esp32c5/mp/include/soc/spi_mem_reg.h b/components/soc/esp32c5/include/soc/spi_mem_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/spi_mem_reg.h
rename to components/soc/esp32c5/include/soc/spi_mem_reg.h
index 689f10aac8..40b9b2fef8 100644
--- a/components/soc/esp32c5/mp/include/soc/spi_mem_reg.h
+++ b/components/soc/esp32c5/include/soc/spi_mem_reg.h
@@ -199,7 +199,7 @@ extern "C" {
 /** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
+ *  SPI clock is always on.
  */
 #define SPI_MEM_CLK_MODE    0x00000003U
 #define SPI_MEM_CLK_MODE_M  (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S)
@@ -959,7 +959,7 @@ extern "C" {
 #define SPI_MEM_SCLKCNT_N_V  0x000000FFU
 #define SPI_MEM_SCLKCNT_N_S  16
 /** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
- *  For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk
+ *  For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk
  *  is divided from system clock.
  */
 #define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
@@ -3346,8 +3346,8 @@ extern "C" {
 #define SPI_MEM_NAND_FLASH_LUT_EN_V  0x00000001U
 #define SPI_MEM_NAND_FLASH_LUT_EN_S  17
 /** SPI_MEM_NAND_FLASH_SEQ_USR_WEND : HRO; bitpos: [18]; default: 0;
- *  Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indecate the last page program ,and to
- *  excute page excute. 1: write end 0: write in a page size.
+ *  Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to
+ *  execute page execute. 1: write end 0: write in a page size.
  */
 #define SPI_MEM_NAND_FLASH_SEQ_USR_WEND    (BIT(18))
 #define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_M  (SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V << SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S)
@@ -3804,7 +3804,7 @@ extern "C" {
  */
 #define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
 /** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
- *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
+ *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
  *  The bigger the number is, the more secure the cryption is. (Note that the
  *  performance of cryption will decrease together with this number increasing)
  */
@@ -3844,21 +3844,21 @@ extern "C" {
 #define SPI_MEM_MODE_PSEUDO_V  0x00000003U
 #define SPI_MEM_MODE_PSEUDO_S  0
 /** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7;
- *  xts aes peseudo function base round that must be peformed.
+ *  xts aes peseudo function base round that must be performed.
  */
 #define SPI_MEM_PSEUDO_RNG_CNT    0x00000007U
 #define SPI_MEM_PSEUDO_RNG_CNT_M  (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S)
 #define SPI_MEM_PSEUDO_RNG_CNT_V  0x00000007U
 #define SPI_MEM_PSEUDO_RNG_CNT_S  2
 /** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2;
- *  xts aes peseudo function base round that must be peformed.
+ *  xts aes peseudo function base round that must be performed.
  */
 #define SPI_MEM_PSEUDO_BASE    0x0000000FU
 #define SPI_MEM_PSEUDO_BASE_M  (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S)
 #define SPI_MEM_PSEUDO_BASE_V  0x0000000FU
 #define SPI_MEM_PSEUDO_BASE_S  5
 /** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2;
- *  xts aes peseudo function increment round that will be peformed randomly between 0 &
+ *  xts aes peseudo function increment round that will be performed randomly between 0 &
  *  2**(inc+1).
  */
 #define SPI_MEM_PSEUDO_INC    0x00000003U
diff --git a/components/soc/esp32c5/mp/include/soc/spi_mem_struct.h b/components/soc/esp32c5/include/soc/spi_mem_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/spi_mem_struct.h
rename to components/soc/esp32c5/include/soc/spi_mem_struct.h
index 01012608b1..d3c23acc78 100644
--- a/components/soc/esp32c5/mp/include/soc/spi_mem_struct.h
+++ b/components/soc/esp32c5/include/soc/spi_mem_struct.h
@@ -69,7 +69,7 @@ typedef volatile struct spi_mem_dev_s {
     } ctrl;
     union {
         struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
             uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
             uint32_t reserved2                     :    9;  /*reserved*/
             uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
@@ -271,7 +271,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
             uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
             uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
+            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/
         };
         uint32_t val;
     } sram_clk;
@@ -388,7 +388,7 @@ typedef volatile struct spi_mem_dev_s {
             uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
             uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
             uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
             uint32_t reserved11                    :    21;  /*reserved*/
         };
         uint32_t val;
@@ -1025,7 +1025,7 @@ typedef volatile struct spi_mem_dev_s {
     } mmu_power_ctrl;
     union {
         struct {
-            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
+            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
             uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
             uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
             uint32_t reserved5                     :    27;  /*reserved*/
diff --git a/components/soc/esp32c5/mp/include/soc/spi_pins.h b/components/soc/esp32c5/include/soc/spi_pins.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/spi_pins.h
rename to components/soc/esp32c5/include/soc/spi_pins.h
diff --git a/components/soc/esp32c5/mp/include/soc/spi_reg.h b/components/soc/esp32c5/include/soc/spi_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/spi_reg.h
rename to components/soc/esp32c5/include/soc/spi_reg.h
index 96220db134..cce0834349 100644
--- a/components/soc/esp32c5/mp/include/soc/spi_reg.h
+++ b/components/soc/esp32c5/include/soc/spi_reg.h
@@ -273,7 +273,7 @@ extern "C" {
 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
  *  Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
  *  0: SPI_CLK is divided from APB_CLK.\\
- *  1: SPI_CLK is eqaul to APB_CLK.\\
+ *  1: SPI_CLK is equal to APB_CLK.\\
  *  Can be configured in CONF state.
  */
 #define SPI_CLK_EQU_SYSCLK    (BIT(31))
diff --git a/components/soc/esp32c5/mp/include/soc/spi_struct.h b/components/soc/esp32c5/include/soc/spi_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/spi_struct.h
rename to components/soc/esp32c5/include/soc/spi_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/system_reg.h b/components/soc/esp32c5/include/soc/system_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/system_reg.h
rename to components/soc/esp32c5/include/soc/system_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/systimer_reg.h b/components/soc/esp32c5/include/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/systimer_reg.h
rename to components/soc/esp32c5/include/soc/systimer_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/systimer_struct.h b/components/soc/esp32c5/include/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/systimer_struct.h
rename to components/soc/esp32c5/include/soc/systimer_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/tee_reg.h b/components/soc/esp32c5/include/soc/tee_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/tee_reg.h
rename to components/soc/esp32c5/include/soc/tee_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/tee_struct.h b/components/soc/esp32c5/include/soc/tee_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/tee_struct.h
rename to components/soc/esp32c5/include/soc/tee_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/timer_group_reg.h b/components/soc/esp32c5/include/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/timer_group_reg.h
rename to components/soc/esp32c5/include/soc/timer_group_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/timer_group_struct.h b/components/soc/esp32c5/include/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/timer_group_struct.h
rename to components/soc/esp32c5/include/soc/timer_group_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/trace_reg.h b/components/soc/esp32c5/include/soc/trace_reg.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/trace_reg.h
rename to components/soc/esp32c5/include/soc/trace_reg.h
index 1abfbbcd04..785965af2c 100644
--- a/components/soc/esp32c5/mp/include/soc/trace_reg.h
+++ b/components/soc/esp32c5/include/soc/trace_reg.h
@@ -76,7 +76,7 @@ extern "C" {
 #define TRACE_FIFO_EMPTY_S  0
 /** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
  *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
- *  state becasue hart is halted or in reset \\3: Lost state\\
+ *  state because hart is halted or in reset \\3: Lost state\\
  */
 #define TRACE_WORK_STATUS    0x00000003U
 #define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
@@ -186,7 +186,7 @@ extern "C" {
 #define TRACE_DM_TRIGGER_ENA_V  0x00000001U
 #define TRACE_DM_TRIGGER_ENA_S  0
 /** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
- *  Configure whether to reset, when enabeld, if cpu have reset, the encoder will
+ *  Configure whether to reset, when enabled, if cpu have reset, the encoder will
  *  output a packet to report the address of the last instruction, and upon reset
  *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
  */
@@ -216,7 +216,7 @@ extern "C" {
 #define TRACE_FULL_ADDRESS_V  0x00000001U
 #define TRACE_FULL_ADDRESS_S  4
 /** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
- *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
+ *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
  *  exception address, only exception cause in exception packets.\\1: enabled\\0:
  *  disabled\\
  */
@@ -418,7 +418,7 @@ extern "C" {
  */
 #define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
 /** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
- *  Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4
+ *  Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4
  *  \\4:INCR8 \\Others:Invalid
  */
 #define TRACE_HBURST    0x00000007U
@@ -440,7 +440,7 @@ extern "C" {
 /** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Configures register clock gating. \\0: Support clock only when the application
  *  writes registers to save power. \\1:Always force the clock on for registers \\ This
- *  bit does't affect register access.
+ *  bit doesn't affect register access.
  */
 #define TRACE_CLK_EN    (BIT(0))
 #define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
diff --git a/components/soc/esp32c5/mp/include/soc/trace_struct.h b/components/soc/esp32c5/include/soc/trace_struct.h
similarity index 98%
rename from components/soc/esp32c5/mp/include/soc/trace_struct.h
rename to components/soc/esp32c5/include/soc/trace_struct.h
index a8337ed0fd..e3de8f54ab 100644
--- a/components/soc/esp32c5/mp/include/soc/trace_struct.h
+++ b/components/soc/esp32c5/include/soc/trace_struct.h
@@ -81,7 +81,7 @@ typedef union {
         uint32_t fifo_empty:1;
         /** work_status : RO; bitpos: [2:1]; default: 0;
          *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
-         *  state becasue hart is halted or in reset \\3: Lost state\\
+         *  state because hart is halted or in reset \\3: Lost state\\
          */
         uint32_t work_status:2;
         uint32_t reserved_3:29;
@@ -184,7 +184,7 @@ typedef union {
          */
         uint32_t dm_trigger_ena:1;
         /** reset_ena : R/W; bitpos: [1]; default: 0;
-         *  Configure whether to reset, when enabeld, if cpu have reset, the encoder will
+         *  Configure whether to reset, when enabled, if cpu have reset, the encoder will
          *  output a packet to report the address of the last instruction, and upon reset
          *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
          */
@@ -202,7 +202,7 @@ typedef union {
          */
         uint32_t full_address:1;
         /** implicit_except : R/W; bitpos: [5]; default: 0;
-         *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
+         *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
          *  exception address, only exception cause in exception packets.\\1: enabled\\0:
          *  disabled\\
          */
@@ -381,7 +381,7 @@ typedef union {
 typedef union {
     struct {
         /** hburst : R/W; bitpos: [2:0]; default: 0;
-         *  Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4
+         *  Configures the AHB burst mode. \\0: SIGNAL \\1: INCR(length not defined) \\2:INCR4
          *  \\4:INCR8 \\Others:Invalid
          */
         uint32_t hburst:3;
@@ -404,7 +404,7 @@ typedef union {
         /** clk_en : R/W; bitpos: [0]; default: 1;
          *  Configures register clock gating. \\0: Support clock only when the application
          *  writes registers to save power. \\1:Always force the clock on for registers \\ This
-         *  bit does't affect register access.
+         *  bit doesn't affect register access.
          */
         uint32_t clk_en:1;
         uint32_t reserved_1:31;
diff --git a/components/soc/esp32c5/mp/include/soc/twaifd_reg.h b/components/soc/esp32c5/include/soc/twaifd_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/twaifd_reg.h
rename to components/soc/esp32c5/include/soc/twaifd_reg.h
index 5e3b6c48a5..bf9f45f249 100644
--- a/components/soc/esp32c5/mp/include/soc/twaifd_reg.h
+++ b/components/soc/esp32c5/include/soc/twaifd_reg.h
@@ -129,7 +129,7 @@ extern "C" {
 #define TWAIFD_ACF_V  0x00000001U
 #define TWAIFD_ACF_S  7
 /** TWAIFD_TSTM : R/W; bitpos: [8]; default: 0;
- *  Test Mode. In test mode several registers have special features. Reffer to
+ *  Test Mode. In test mode several registers have special features. Refer to
  *  description of Test mode for further
  *  Details.
  */
@@ -186,7 +186,7 @@ extern "C" {
 #define TWAIFD_RTRTH_V  0x0000000FU
 #define TWAIFD_RTRTH_S  17
 /** TWAIFD_ILBP : R/W; bitpos: [21]; default: 0;
- *  Internal Loop Back mode. When enabled, CTU CAN FD receives any frame it transmitts.
+ *  Internal Loop Back mode. When enabled, CTU CAN FD receives any frame it transmits.
  *  0b0 - INT_LOOP_DISABLED - Internal loop-back is disabled.
  *  0b1 - INT_LOOP_ENABLED - Internal loop-back is enabled.
  */
@@ -426,7 +426,7 @@ extern "C" {
 /** TWAIFD_ERCRST : WO; bitpos: [4]; default: 0;
  *  Error Counters Reset. When unit is bus off, issuing this command will request
  *  erasing TEC, REC counters after
- *  128 consecutive ocurrences of 11 recessive bits. Upon completion, TEC and REC are
+ *  128 consecutive occurrences of 11 recessive bits. Upon completion, TEC and REC are
  *  erased and fault confinement
  *  State is set to error-active. When unit is not bus-off, or when unit is bus-off due
  *  to being disabled (SETTINGS[ENA]
@@ -1929,7 +1929,7 @@ extern "C" {
  */
 #define TWAIFD_DEBUG_REG(i) (REG_TWAI_BASE(i) + 0x8c)
 /** TWAIFD_STUFF_COUNT : RO; bitpos: [2:0]; default: 0;
- *  Actual stuff count modulo 8 as definned in ISO FD protocol. Stuff count is erased
+ *  Actual stuff count modulo 8 as defined in ISO FD protocol. Stuff count is erased
  *  in the beginning
  *  of CAN frame and increased by one with each stuff bit until Stuff count field in
  *  ISO FD frame. Then it stays fixed
diff --git a/components/soc/esp32c5/mp/include/soc/twaifd_struct.h b/components/soc/esp32c5/include/soc/twaifd_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/twaifd_struct.h
rename to components/soc/esp32c5/include/soc/twaifd_struct.h
index 28e7a71bee..1ab2d31c3b 100644
--- a/components/soc/esp32c5/mp/include/soc/twaifd_struct.h
+++ b/components/soc/esp32c5/include/soc/twaifd_struct.h
@@ -103,7 +103,7 @@ typedef union {
          */
         uint32_t acf:1;
         /** tstm : R/W; bitpos: [8]; default: 0;
-         *  Test Mode. In test mode several registers have special features. Reffer to
+         *  Test Mode. In test mode several registers have special features. Refer to
          *  description of Test mode for further
          *  Details.
          */
@@ -143,7 +143,7 @@ typedef union {
          */
         uint32_t rtrth:4;
         /** ilbp : R/W; bitpos: [21]; default: 0;
-         *  Internal Loop Back mode. When enabled, CTU CAN FD receives any frame it transmitts.
+         *  Internal Loop Back mode. When enabled, CTU CAN FD receives any frame it transmits.
          *  0b0 - INT_LOOP_DISABLED - Internal loop-back is disabled.
          *  0b1 - INT_LOOP_ENABLED - Internal loop-back is enabled.
          */
@@ -223,7 +223,7 @@ typedef union {
         /** ercrst : WO; bitpos: [4]; default: 0;
          *  Error Counters Reset. When unit is bus off, issuing this command will request
          *  erasing TEC, REC counters after
-         *  128 consecutive ocurrences of 11 recessive bits. Upon completion, TEC and REC are
+         *  128 consecutive occurrences of 11 recessive bits. Upon completion, TEC and REC are
          *  erased and fault confinement
          *  State is set to error-active. When unit is not bus-off, or when unit is bus-off due
          *  to being disabled (SETTINGS[ENA]
@@ -1710,7 +1710,7 @@ typedef union {
 typedef union {
     struct {
         /** stuff_count : RO; bitpos: [2:0]; default: 0;
-         *  Actual stuff count modulo 8 as definned in ISO FD protocol. Stuff count is erased
+         *  Actual stuff count modulo 8 as defined in ISO FD protocol. Stuff count is erased
          *  in the beginning
          *  of CAN frame and increased by one with each stuff bit until Stuff count field in
          *  ISO FD frame. Then it stays fixed
diff --git a/components/soc/esp32c5/mp/include/soc/uart_channel.h b/components/soc/esp32c5/include/soc/uart_channel.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/uart_channel.h
rename to components/soc/esp32c5/include/soc/uart_channel.h
diff --git a/components/soc/esp32c5/mp/include/soc/uart_pins.h b/components/soc/esp32c5/include/soc/uart_pins.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/uart_pins.h
rename to components/soc/esp32c5/include/soc/uart_pins.h
diff --git a/components/soc/esp32c5/mp/include/soc/uart_reg.h b/components/soc/esp32c5/include/soc/uart_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/uart_reg.h
rename to components/soc/esp32c5/include/soc/uart_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/uart_struct.h b/components/soc/esp32c5/include/soc/uart_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/uart_struct.h
rename to components/soc/esp32c5/include/soc/uart_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/uhci_reg.h b/components/soc/esp32c5/include/soc/uhci_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/uhci_reg.h
rename to components/soc/esp32c5/include/soc/uhci_reg.h
diff --git a/components/soc/esp32c5/mp/include/soc/uhci_struct.h b/components/soc/esp32c5/include/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/uhci_struct.h
rename to components/soc/esp32c5/include/soc/uhci_struct.h
diff --git a/components/soc/esp32c5/mp/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/usb_serial_jtag_reg.h
rename to components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h
index e9e9b83373..5a8b1d4a06 100644
--- a/components/soc/esp32c5/mp/include/soc/usb_serial_jtag_reg.h
+++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h
@@ -653,7 +653,7 @@ extern "C" {
 #define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
 #define USB_SERIAL_JTAG_TEST_ENABLE_S  0
 /** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test
+ *  USB pad one in test
  */
 #define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
 #define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
@@ -1144,7 +1144,7 @@ extern "C" {
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
 /** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
  */
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
diff --git a/components/soc/esp32c5/mp/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
similarity index 99%
rename from components/soc/esp32c5/mp/include/soc/usb_serial_jtag_struct.h
rename to components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
index b9149fef7a..0223eaf833 100644
--- a/components/soc/esp32c5/mp/include/soc/usb_serial_jtag_struct.h
+++ b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
@@ -131,7 +131,7 @@ typedef union {
          */
         uint32_t test_enable:1;
         /** test_usb_oe : R/W; bitpos: [1]; default: 0;
-         *  USB pad oen in test
+         *  USB pad one in test
          */
         uint32_t test_usb_oe:1;
         /** test_tx_dp : R/W; bitpos: [2]; default: 0;
@@ -290,7 +290,7 @@ typedef union {
          */
         uint32_t serial_out_afifo_reset_rd:1;
         /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
-         *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+         *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
          */
         uint32_t serial_out_afifo_rempty:1;
         /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
diff --git a/components/soc/esp32c5/mp/include/soc/wdev_reg.h b/components/soc/esp32c5/include/soc/wdev_reg.h
similarity index 100%
rename from components/soc/esp32c5/mp/include/soc/wdev_reg.h
rename to components/soc/esp32c5/include/soc/wdev_reg.h
diff --git a/components/soc/esp32c5/mp/interrupts.c b/components/soc/esp32c5/interrupts.c
similarity index 100%
rename from components/soc/esp32c5/mp/interrupts.c
rename to components/soc/esp32c5/interrupts.c
diff --git a/components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld b/components/soc/esp32c5/ld/esp32c5.peripherals.ld
similarity index 100%
rename from components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
rename to components/soc/esp32c5/ld/esp32c5.peripherals.ld
diff --git a/components/soc/esp32c5/mp/ledc_periph.c b/components/soc/esp32c5/ledc_periph.c
similarity index 100%
rename from components/soc/esp32c5/mp/ledc_periph.c
rename to components/soc/esp32c5/ledc_periph.c
diff --git a/components/soc/esp32c5/mp/mcpwm_periph.c b/components/soc/esp32c5/mcpwm_periph.c
similarity index 100%
rename from components/soc/esp32c5/mp/mcpwm_periph.c
rename to components/soc/esp32c5/mcpwm_periph.c
diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
deleted file mode 100644
index 81cd9099a9..0000000000
--- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
+++ /dev/null
@@ -1,800 +0,0 @@
-#####################################################
-# This file is auto-generated from SoC caps
-# using gen_soc_caps_kconfig.py, do not edit manually
-#####################################################
-
-config SOC_UART_SUPPORTED
-    bool
-    default y
-
-config SOC_GDMA_SUPPORTED
-    bool
-    default y
-
-config SOC_AHB_GDMA_SUPPORTED
-    bool
-    default y
-
-config SOC_GPTIMER_SUPPORTED
-    bool
-    default y
-
-config SOC_PCNT_SUPPORTED
-    bool
-    default y
-
-config SOC_MCPWM_SUPPORTED
-    bool
-    default y
-
-config SOC_ASYNC_MEMCPY_SUPPORTED
-    bool
-    default y
-
-config SOC_SUPPORTS_SECURE_DL_MODE
-    bool
-    default y
-
-config SOC_EFUSE_KEY_PURPOSE_FIELD
-    bool
-    default y
-
-config SOC_EFUSE_SUPPORTED
-    bool
-    default y
-
-config SOC_RTC_FAST_MEM_SUPPORTED
-    bool
-    default y
-
-config SOC_RTC_MEM_SUPPORTED
-    bool
-    default y
-
-config SOC_I2S_SUPPORTED
-    bool
-    default y
-
-config SOC_RMT_SUPPORTED
-    bool
-    default y
-
-config SOC_GPSPI_SUPPORTED
-    bool
-    default y
-
-config SOC_LEDC_SUPPORTED
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORTED
-    bool
-    default y
-
-config SOC_AES_SUPPORTED
-    bool
-    default y
-
-config SOC_MPI_SUPPORTED
-    bool
-    default y
-
-config SOC_SHA_SUPPORTED
-    bool
-    default y
-
-config SOC_RSA_SUPPORTED
-    bool
-    default y
-
-config SOC_HMAC_SUPPORTED
-    bool
-    default y
-
-config SOC_DIG_SIGN_SUPPORTED
-    bool
-    default y
-
-config SOC_ECC_SUPPORTED
-    bool
-    default y
-
-config SOC_ECC_EXTENDED_MODES_SUPPORTED
-    bool
-    default y
-
-config SOC_FLASH_ENC_SUPPORTED
-    bool
-    default y
-
-config SOC_SECURE_BOOT_SUPPORTED
-    bool
-    default y
-
-config SOC_LP_PERIPHERALS_SUPPORTED
-    bool
-    default y
-
-config SOC_SPI_FLASH_SUPPORTED
-    bool
-    default y
-
-config SOC_ECDSA_SUPPORTED
-    bool
-    default y
-
-config SOC_XTAL_SUPPORT_40M
-    bool
-    default y
-
-config SOC_XTAL_SUPPORT_48M
-    bool
-    default y
-
-config SOC_XTAL_SUPPORT_EFUSE_SEL
-    bool
-    default y
-
-config SOC_AES_SUPPORT_DMA
-    bool
-    default y
-
-config SOC_AES_GDMA
-    bool
-    default y
-
-config SOC_AES_SUPPORT_AES_128
-    bool
-    default y
-
-config SOC_AES_SUPPORT_AES_256
-    bool
-    default y
-
-config SOC_ADC_PERIPH_NUM
-    int
-    default 1
-
-config SOC_ADC_MAX_CHANNEL_NUM
-    int
-    default 7
-
-config SOC_SHARED_IDCACHE_SUPPORTED
-    bool
-    default y
-
-config SOC_CACHE_FREEZE_SUPPORTED
-    bool
-    default y
-
-config SOC_CPU_CORES_NUM
-    int
-    default 1
-
-config SOC_CPU_INTR_NUM
-    int
-    default 32
-
-config SOC_CPU_HAS_FLEXIBLE_INTC
-    bool
-    default y
-
-config SOC_INT_CLIC_SUPPORTED
-    bool
-    default y
-
-config SOC_INT_HW_NESTED_SUPPORTED
-    bool
-    default y
-
-config SOC_BRANCH_PREDICTOR_SUPPORTED
-    bool
-    default y
-
-config SOC_CPU_BREAKPOINTS_NUM
-    int
-    default 4
-
-config SOC_CPU_WATCHPOINTS_NUM
-    int
-    default 4
-
-config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
-    hex
-    default 0x100
-
-config SOC_CPU_HAS_PMA
-    bool
-    default y
-
-config SOC_CPU_IDRAM_SPLIT_USING_PMP
-    bool
-    default y
-
-config SOC_DS_SIGNATURE_MAX_BIT_LEN
-    int
-    default 3072
-
-config SOC_DS_KEY_PARAM_MD_IV_LENGTH
-    int
-    default 16
-
-config SOC_DS_KEY_CHECK_MAX_WAIT_US
-    int
-    default 1100
-
-config SOC_DMA_CAN_ACCESS_FLASH
-    bool
-    default y
-
-config SOC_AHB_GDMA_VERSION
-    int
-    default 2
-
-config SOC_GDMA_NUM_GROUPS_MAX
-    int
-    default 1
-
-config SOC_GDMA_PAIRS_PER_GROUP_MAX
-    int
-    default 3
-
-config SOC_GPIO_PORT
-    int
-    default 1
-
-config SOC_GPIO_PIN_COUNT
-    int
-    default 29
-
-config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
-    bool
-    default y
-
-config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
-    bool
-    default y
-
-config SOC_GPIO_IN_RANGE_MAX
-    int
-    default 28
-
-config SOC_GPIO_OUT_RANGE_MAX
-    int
-    default 28
-
-config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
-    int
-    default 0
-
-config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
-    hex
-    default 0x0000000001FFFF00
-
-config SOC_GPIO_SUPPORT_FORCE_HOLD
-    bool
-    default y
-
-config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
-    bool
-    default y
-
-config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
-    int
-    default 3
-
-config SOC_RTCIO_PIN_COUNT
-    int
-    default 0
-
-config SOC_I2C_NUM
-    int
-    default 1
-
-config SOC_HP_I2C_NUM
-    int
-    default 1
-
-config SOC_I2S_NUM
-    int
-    default 1
-
-config SOC_I2S_HW_VERSION_2
-    bool
-    default y
-
-config SOC_I2S_SUPPORTS_TX_SYNC_CNT
-    bool
-    default y
-
-config SOC_I2S_SUPPORTS_XTAL
-    bool
-    default y
-
-config SOC_I2S_SUPPORTS_PLL_F160M
-    bool
-    default y
-
-config SOC_I2S_SUPPORTS_PLL_F240M
-    bool
-    default y
-
-config SOC_I2S_SUPPORTS_PCM
-    bool
-    default y
-
-config SOC_I2S_SUPPORTS_PDM
-    bool
-    default y
-
-config SOC_I2S_SUPPORTS_PDM_TX
-    bool
-    default y
-
-config SOC_I2S_PDM_MAX_TX_LINES
-    int
-    default 2
-
-config SOC_I2S_SUPPORTS_TDM
-    bool
-    default y
-
-config SOC_I2S_TDM_FULL_DATA_WIDTH
-    bool
-    default y
-
-config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-    bool
-    default y
-
-config SOC_LEDC_SUPPORT_XTAL_CLOCK
-    bool
-    default y
-
-config SOC_LEDC_CHANNEL_NUM
-    int
-    default 6
-
-config SOC_LEDC_TIMER_BIT_WIDTH
-    int
-    default 20
-
-config SOC_LEDC_SUPPORT_FADE_STOP
-    bool
-    default y
-
-config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
-    bool
-    default y
-
-config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
-    int
-    default 16
-
-config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
-    int
-    default 10
-
-config SOC_MMU_PERIPH_NUM
-    int
-    default 1
-
-config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
-    int
-    default 1
-
-config SOC_MMU_DI_VADDR_SHARED
-    bool
-    default y
-
-config SOC_PCNT_GROUPS
-    int
-    default 1
-
-config SOC_PCNT_UNITS_PER_GROUP
-    int
-    default 4
-
-config SOC_PCNT_CHANNELS_PER_UNIT
-    int
-    default 2
-
-config SOC_PCNT_THRES_POINT_PER_UNIT
-    int
-    default 2
-
-config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
-    bool
-    default y
-
-config SOC_PCNT_SUPPORT_CLEAR_SIGNAL
-    bool
-    default y
-
-config SOC_RMT_GROUPS
-    int
-    default 1
-
-config SOC_RMT_TX_CANDIDATES_PER_GROUP
-    int
-    default 2
-
-config SOC_RMT_RX_CANDIDATES_PER_GROUP
-    int
-    default 2
-
-config SOC_RMT_CHANNELS_PER_GROUP
-    int
-    default 4
-
-config SOC_RMT_MEM_WORDS_PER_CHANNEL
-    int
-    default 48
-
-config SOC_RMT_SUPPORT_RX_PINGPONG
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_RX_DEMODULATION
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_ASYNC_STOP
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_LOOP_COUNT
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_SYNCHRO
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
-    bool
-    default y
-
-config SOC_RMT_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_MCPWM_GROUPS
-    int
-    default 1
-
-config SOC_MCPWM_TIMERS_PER_GROUP
-    int
-    default 3
-
-config SOC_MCPWM_OPERATORS_PER_GROUP
-    int
-    default 3
-
-config SOC_MCPWM_COMPARATORS_PER_OPERATOR
-    int
-    default 2
-
-config SOC_MCPWM_GENERATORS_PER_OPERATOR
-    int
-    default 2
-
-config SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR
-    int
-    default 2
-
-config SOC_MCPWM_TRIGGERS_PER_OPERATOR
-    int
-    default 2
-
-config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
-    int
-    default 3
-
-config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
-    bool
-    default y
-
-config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
-    int
-    default 3
-
-config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
-    int
-    default 3
-
-config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
-    bool
-    default y
-
-config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
-    bool
-    default y
-
-config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
-    bool
-    default y
-
-config SOC_MPI_MEM_BLOCKS_NUM
-    int
-    default 4
-
-config SOC_MPI_OPERATIONS_NUM
-    int
-    default 3
-
-config SOC_RSA_MAX_BIT_LEN
-    int
-    default 3072
-
-config SOC_SHA_DMA_MAX_BUFFER_SIZE
-    int
-    default 3968
-
-config SOC_SHA_SUPPORT_DMA
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_RESUME
-    bool
-    default y
-
-config SOC_SHA_GDMA
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_SHA1
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_SHA224
-    bool
-    default y
-
-config SOC_SHA_SUPPORT_SHA256
-    bool
-    default y
-
-config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
-    bool
-    default y
-
-config SOC_SPI_PERIPH_NUM
-    int
-    default 2
-
-config SOC_SPI_MAX_CS_NUM
-    int
-    default 6
-
-config SOC_SPI_MAXIMUM_BUFFER_SIZE
-    int
-    default 64
-
-config SOC_SPI_SUPPORT_DDRCLK
-    bool
-    default y
-
-config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_CD_SIG
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_SLAVE_HD_VER2
-    bool
-    default y
-
-config SOC_SPI_SUPPORT_CLK_XTAL
-    bool
-    default y
-
-config SOC_MEMSPI_IS_INDEPENDENT
-    bool
-    default y
-
-config SOC_SPI_MAX_PRE_DIVIDER
-    int
-    default 16
-
-config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
-    bool
-    default y
-
-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
-config SOC_TIMER_GROUPS
-    int
-    default 2
-
-config SOC_TIMER_GROUP_TIMERS_PER_GROUP
-    int
-    default 1
-
-config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
-    int
-    default 54
-
-config SOC_TIMER_GROUP_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_TIMER_GROUP_TOTAL_TIMERS
-    int
-    default 2
-
-config SOC_EFUSE_ECDSA_KEY
-    bool
-    default y
-
-config SOC_SECURE_BOOT_V2_RSA
-    bool
-    default y
-
-config SOC_SECURE_BOOT_V2_ECC
-    bool
-    default y
-
-config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
-    int
-    default 3
-
-config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
-    bool
-    default y
-
-config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
-    bool
-    default y
-
-config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
-    int
-    default 64
-
-config SOC_FLASH_ENCRYPTION_XTS_AES
-    bool
-    default y
-
-config SOC_FLASH_ENCRYPTION_XTS_AES_128
-    bool
-    default y
-
-config SOC_UART_NUM
-    int
-    default 3
-
-config SOC_UART_HP_NUM
-    int
-    default 2
-
-config SOC_UART_LP_NUM
-    int
-    default 1
-
-config SOC_UART_FIFO_LEN
-    int
-    default 128
-
-config SOC_LP_UART_FIFO_LEN
-    int
-    default 16
-
-config SOC_UART_BITRATE_MAX
-    int
-    default 5000000
-
-config SOC_UART_SUPPORT_XTAL_CLK
-    bool
-    default y
-
-config SOC_UART_SUPPORT_WAKEUP_INT
-    bool
-    default y
-
-config SOC_UART_HAS_LP_UART
-    bool
-    default y
-
-config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
-    bool
-    default y
-
-config SOC_PM_SUPPORT_MODEM_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_XTAL32K_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_RC32K_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_RC_FAST_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_VDDSDIO_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_TOP_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_HP_AON_PD
-    bool
-    default y
-
-config SOC_PM_SUPPORT_RTC_PERIPH_PD
-    bool
-    default y
-
-config SOC_MODEM_CLOCK_IS_INDEPENDENT
-    bool
-    default y
-
-config SOC_CLK_XTAL32K_SUPPORTED
-    bool
-    default y
-
-config SOC_CLK_OSC_SLOW_SUPPORTED
-    bool
-    default y
-
-config SOC_CLK_RC32K_SUPPORTED
-    bool
-    default y
-
-config SOC_RCC_IS_INDEPENDENT
-    bool
-    default y
diff --git a/components/soc/esp32c5/mp/include/soc/clkout_channel.h b/components/soc/esp32c5/mp/include/soc/clkout_channel.h
deleted file mode 100644
index 719893aee4..0000000000
--- a/components/soc/esp32c5/mp/include/soc/clkout_channel.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "esp_assert.h"
-#include "soc/soc_caps.h"
-#include "soc/io_mux_reg.h"
-#include "soc/gpio_sig_map.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum clock_out_channel {
-    CLKOUT_CHANNEL_1,
-    CLKOUT_CHANNEL_2,
-    CLKOUT_CHANNEL_3,
-    CLKOUT_CHANNEL_MAX,
-} clock_out_channel_t;
-
-#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
-                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
-                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
-
-
-#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
-                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
-                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
-
-#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
-                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
-                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
-
-ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/mp/include/soc/efuse_defs.h b/components/soc/esp32c5/mp/include/soc/efuse_defs.h
deleted file mode 100644
index 48cc4ce65d..0000000000
--- a/components/soc/esp32c5/mp/include/soc/efuse_defs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define EFUSE_WRITE_OP_CODE 0x5a5a
-#define EFUSE_READ_OP_CODE 0x5aa5
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/mp/include/soc/gpio_sig_map.h b/components/soc/esp32c5/mp/include/soc/gpio_sig_map.h
deleted file mode 100644
index 813f0a0515..0000000000
--- a/components/soc/esp32c5/mp/include/soc/gpio_sig_map.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#define EXT_ADC_START_IDX                       0
-#define LEDC_LS_SIG_OUT0_IDX                    0
-#define LEDC_LS_SIG_OUT1_IDX                    1
-#define LEDC_LS_SIG_OUT2_IDX                    2
-#define LEDC_LS_SIG_OUT3_IDX                    3
-#define LEDC_LS_SIG_OUT4_IDX                    4
-#define LEDC_LS_SIG_OUT5_IDX                    5
-#define U0RXD_IN_IDX                            6
-#define U0TXD_OUT_IDX                           6
-#define U0CTS_IN_IDX                            7
-#define U0RTS_OUT_IDX                           7
-#define U0DSR_IN_IDX                            8
-#define U0DTR_OUT_IDX                           8
-#define U1RXD_IN_IDX                            9
-#define U1TXD_OUT_IDX                           9
-#define U1CTS_IN_IDX                            10
-#define U1RTS_OUT_IDX                           10
-#define U1DSR_IN_IDX                            11
-#define U1DTR_OUT_IDX                           11
-#define I2S_MCLK_IN_IDX                         12
-#define I2S_MCLK_OUT_IDX                        12
-#define I2SO_BCK_IN_IDX                         13
-#define I2SO_BCK_OUT_IDX                        13
-#define I2SO_WS_IN_IDX                          14
-#define I2SO_WS_OUT_IDX                         14
-#define I2SI_SD_IN_IDX                          15
-#define I2SO_SD_OUT_IDX                         15
-#define I2SI_BCK_IN_IDX                         16
-#define I2SI_BCK_OUT_IDX                        16
-#define I2SI_WS_IN_IDX                          17
-#define I2SI_WS_OUT_IDX                         17
-#define I2SO_SD1_OUT_IDX                        18
-#define CPU_TESTBUS0_IDX                        19
-#define CPU_TESTBUS1_IDX                        20
-#define CPU_TESTBUS2_IDX                        21
-#define CPU_TESTBUS3_IDX                        22
-#define CPU_TESTBUS4_IDX                        23
-#define CPU_TESTBUS5_IDX                        24
-#define CPU_TESTBUS6_IDX                        25
-#define CPU_TESTBUS7_IDX                        26
-#define CPU_GPIO_IN0_IDX                        27
-#define CPU_GPIO_OUT0_IDX                       27
-#define CPU_GPIO_IN1_IDX                        28
-#define CPU_GPIO_OUT1_IDX                       28
-#define CPU_GPIO_IN2_IDX                        29
-#define CPU_GPIO_OUT2_IDX                       29
-#define CPU_GPIO_IN3_IDX                        30
-#define CPU_GPIO_OUT3_IDX                       30
-#define CPU_GPIO_IN4_IDX                        31
-#define CPU_GPIO_OUT4_IDX                       31
-#define CPU_GPIO_IN5_IDX                        32
-#define CPU_GPIO_OUT5_IDX                       32
-#define CPU_GPIO_IN6_IDX                        33
-#define CPU_GPIO_OUT6_IDX                       33
-#define CPU_GPIO_IN7_IDX                        34
-#define CPU_GPIO_OUT7_IDX                       34
-#define USB_JTAG_TDO_IDX                        35
-#define USB_JTAG_TRST_IDX                       35
-#define USB_JTAG_SRST_IDX                       36
-#define USB_JTAG_TCK_IDX                        37
-#define USB_JTAG_TMS_IDX                        38
-#define USB_JTAG_TDI_IDX                        39
-#define CPU_USB_JTAG_TDO_IDX                    40
-#define USB_EXTPHY_VP_IDX                       41
-#define USB_EXTPHY_OEN_IDX                      41
-#define USB_EXTPHY_VM_IDX                       42
-#define USB_EXTPHY_SPEED_IDX                    42
-#define USB_EXTPHY_RCV_IDX                      43
-#define USB_EXTPHY_VPO_IDX                      43
-#define USB_EXTPHY_VMO_IDX                      44
-#define USB_EXTPHY_SUSPND_IDX                   45
-#define I2CEXT0_SCL_IN_IDX                      46
-#define I2CEXT0_SCL_OUT_IDX                     46
-#define I2CEXT0_SDA_IN_IDX                      47
-#define I2CEXT0_SDA_OUT_IDX                     47
-#define PARL_RX_DATA0_IDX                       48
-#define PARL_TX_DATA0_IDX                       48
-#define PARL_RX_DATA1_IDX                       49
-#define PARL_TX_DATA1_IDX                       49
-#define PARL_RX_DATA2_IDX                       50
-#define PARL_TX_DATA2_IDX                       50
-#define PARL_RX_DATA3_IDX                       51
-#define PARL_TX_DATA3_IDX                       51
-#define PARL_RX_DATA4_IDX                       52
-#define PARL_TX_DATA4_IDX                       52
-#define PARL_RX_DATA5_IDX                       53
-#define PARL_TX_DATA5_IDX                       53
-#define PARL_RX_DATA6_IDX                       54
-#define PARL_TX_DATA6_IDX                       54
-#define PARL_RX_DATA7_IDX                       55
-#define PARL_TX_DATA7_IDX                       55
-#define FSPICLK_IN_IDX                          56
-#define FSPICLK_OUT_IDX                         56
-#define FSPIQ_IN_IDX                            57
-#define FSPIQ_OUT_IDX                           57
-#define FSPID_IN_IDX                            58
-#define FSPID_OUT_IDX                           58
-#define FSPIHD_IN_IDX                           59
-#define FSPIHD_OUT_IDX                          59
-#define FSPIWP_IN_IDX                           60
-#define FSPIWP_OUT_IDX                          60
-#define FSPICS0_IN_IDX                          61
-#define FSPICS0_OUT_IDX                         61
-#define PARL_RX_CLK_IN_IDX                      62
-#define PARL_RX_CLK_OUT_IDX                     62
-#define PARL_TX_CLK_IN_IDX                      63
-#define PARL_TX_CLK_OUT_IDX                     63
-#define RMT_SIG_IN0_IDX                         64
-#define RMT_SIG_OUT0_IDX                        64
-#define RMT_SIG_IN1_IDX                         65
-#define RMT_SIG_OUT1_IDX                        65
-#define TWAI0_RX_IDX                            66
-#define TWAI0_TX_IDX                            66
-#define TWAI0_BUS_OFF_ON_IDX                    67
-#define TWAI0_CLKOUT_IDX                        68
-#define TWAI0_STANDBY_IDX                       69
-#define TWAI1_RX_IDX                            70
-#define TWAI1_TX_IDX                            70
-#define TWAI1_BUS_OFF_ON_IDX                    71
-#define TWAI1_CLKOUT_IDX                        72
-#define TWAI1_STANDBY_IDX                       73
-#define EXTERN_PRIORITY_I_IDX                   74
-#define EXTERN_PRIORITY_O_IDX                   74
-#define EXTERN_ACTIVE_I_IDX                     75
-#define EXTERN_ACTIVE_O_IDX                     75
-#define PCNT_RST_IN0_IDX                        76
-#define GPIO_SD0_OUT_IDX                        76
-#define PCNT_RST_IN1_IDX                        77
-#define GPIO_SD1_OUT_IDX                        77
-#define PCNT_RST_IN2_IDX                        78
-#define GPIO_SD2_OUT_IDX                        78
-#define PCNT_RST_IN3_IDX                        79
-#define GPIO_SD3_OUT_IDX                        79
-#define PWM0_SYNC0_IN_IDX                       80
-#define PWM0_OUT0A_IDX                          80
-#define PWM0_SYNC1_IN_IDX                       81
-#define PWM0_OUT0B_IDX                          81
-#define PWM0_SYNC2_IN_IDX                       82
-#define PWM0_OUT1A_IDX                          82
-#define PWM0_F0_IN_IDX                          83
-#define PWM0_OUT1B_IDX                          83
-#define PWM0_F1_IN_IDX                          84
-#define PWM0_OUT2A_IDX                          84
-#define PWM0_F2_IN_IDX                          85
-#define PWM0_OUT2B_IDX                          85
-#define PWM0_CAP0_IN_IDX                        86
-#define PWM0_CAP1_IN_IDX                        87
-#define PWM0_CAP2_IN_IDX                        88
-#define GPIO_EVENT_MATRIX_IN0_IDX               89
-#define GPIO_TASK_MATRIX_OUT0_IDX               89
-#define GPIO_EVENT_MATRIX_IN1_IDX               90
-#define GPIO_TASK_MATRIX_OUT1_IDX               90
-#define GPIO_EVENT_MATRIX_IN2_IDX               91
-#define GPIO_TASK_MATRIX_OUT2_IDX               91
-#define GPIO_EVENT_MATRIX_IN3_IDX               92
-#define GPIO_TASK_MATRIX_OUT3_IDX               92
-#define CLK_OUT_OUT1_IDX                        93
-#define CLK_OUT_OUT2_IDX                        94
-#define CLK_OUT_OUT3_IDX                        95
-#define SIG_IN_FUNC_97_IDX                      97
-#define SIG_IN_FUNC97_IDX                       97
-#define SIG_IN_FUNC_98_IDX                      98
-#define SIG_IN_FUNC98_IDX                       98
-#define SIG_IN_FUNC_99_IDX                      99
-#define SIG_IN_FUNC99_IDX                       99
-#define SIG_IN_FUNC_100_IDX                     100
-#define SIG_IN_FUNC100_IDX                      100
-#define PCNT_SIG_CH0_IN0_IDX                    101
-#define FSPICS1_OUT_IDX                         101
-#define PCNT_SIG_CH1_IN0_IDX                    102
-#define FSPICS2_OUT_IDX                         102
-#define PCNT_CTRL_CH0_IN0_IDX                   103
-#define FSPICS3_OUT_IDX                         103
-#define PCNT_CTRL_CH1_IN0_IDX                   104
-#define FSPICS4_OUT_IDX                         104
-#define PCNT_SIG_CH0_IN1_IDX                    105
-#define FSPICS5_OUT_IDX                         105
-#define PCNT_SIG_CH1_IN1_IDX                    106
-#define MODEM_DIAG0_IDX                         106
-#define PCNT_CTRL_CH0_IN1_IDX                   107
-#define MODEM_DIAG1_IDX                         107
-#define PCNT_CTRL_CH1_IN1_IDX                   108
-#define MODEM_DIAG2_IDX                         108
-#define PCNT_SIG_CH0_IN2_IDX                    109
-#define MODEM_DIAG3_IDX                         109
-#define PCNT_SIG_CH1_IN2_IDX                    110
-#define MODEM_DIAG4_IDX                         110
-#define PCNT_CTRL_CH0_IN2_IDX                   111
-#define MODEM_DIAG5_IDX                         111
-#define PCNT_CTRL_CH1_IN2_IDX                   112
-#define MODEM_DIAG6_IDX                         112
-#define PCNT_SIG_CH0_IN3_IDX                    113
-#define MODEM_DIAG7_IDX                         113
-#define PCNT_SIG_CH1_IN3_IDX                    114
-#define MODEM_DIAG8_IDX                         114
-#define PCNT_CTRL_CH0_IN3_IDX                   115
-#define MODEM_DIAG9_IDX                         115
-#define PCNT_CTRL_CH1_IN3_IDX                   116
-#define MODEM_DIAG10_IDX                        116
-#define MODEM_DIAG11_IDX                        117
-#define MODEM_DIAG12_IDX                        118
-#define MODEM_DIAG13_IDX                        119
-#define MODEM_DIAG14_IDX                        120
-#define MODEM_DIAG15_IDX                        121
-#define MODEM_DIAG16_IDX                        122
-#define MODEM_DIAG17_IDX                        123
-#define MODEM_DIAG18_IDX                        124
-#define MODEM_DIAG19_IDX                        125
-#define MODEM_DIAG20_IDX                        126
-#define MODEM_DIAG21_IDX                        127
-#define MODEM_DIAG22_IDX                        128
-#define MODEM_DIAG23_IDX                        129
-#define MODEM_DIAG24_IDX                        130
-#define MODEM_DIAG25_IDX                        131
-#define MODEM_DIAG26_IDX                        132
-#define MODEM_DIAG27_IDX                        133
-#define MODEM_DIAG28_IDX                        134
-#define MODEM_DIAG29_IDX                        135
-#define MODEM_DIAG30_IDX                        136
-#define MODEM_DIAG31_IDX                        137
-#define ANT_SEL0_IDX                            138
-#define ANT_SEL1_IDX                            139
-#define ANT_SEL2_IDX                            140
-#define ANT_SEL3_IDX                            141
-#define ANT_SEL4_IDX                            142
-#define ANT_SEL5_IDX                            143
-#define ANT_SEL6_IDX                            144
-#define ANT_SEL7_IDX                            145
-#define ANT_SEL8_IDX                            146
-#define ANT_SEL9_IDX                            147
-#define ANT_SEL10_IDX                           148
-#define ANT_SEL11_IDX                           149
-#define ANT_SEL12_IDX                           150
-#define ANT_SEL13_IDX                           151
-#define ANT_SEL14_IDX                           152
-#define ANT_SEL15_IDX                           153
-#define SIG_GPIO_OUT_IDX                        256
-// version date 2311280
diff --git a/components/soc/esp32c5/mp/include/soc/hwcrypto_reg.h b/components/soc/esp32c5/mp/include/soc/hwcrypto_reg.h
deleted file mode 100644
index 098f0d3ffd..0000000000
--- a/components/soc/esp32c5/mp/include/soc/hwcrypto_reg.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/aes_reg.h"
-#include "soc/ds_reg.h"
-#include "soc/hmac_reg.h"
-#include "soc/rsa_reg.h"
-#include "soc/sha_reg.h"
diff --git a/components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h
deleted file mode 100644
index 4089e68b3e..0000000000
--- a/components/soc/esp32c5/mp/include/soc/i2c_ana_mst_reg.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define I2C_ANA_MST_I2C0_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x0)
-/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C0_BUSY    (BIT(25))
-#define I2C_ANA_MST_I2C0_BUSY_M  (BIT(25))
-#define I2C_ANA_MST_I2C0_BUSY_V  0x1
-#define I2C_ANA_MST_I2C0_BUSY_S  25
-/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C0_CTRL    0x01FFFFFF
-#define I2C_ANA_MST_I2C0_CTRL_M  ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S))
-#define I2C_ANA_MST_I2C0_CTRL_V  0x1FFFFFF
-#define I2C_ANA_MST_I2C0_CTRL_S  0
-
-#define I2C_ANA_MST_I2C1_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x4)
-/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C1_BUSY    (BIT(25))
-#define I2C_ANA_MST_I2C1_BUSY_M  (BIT(25))
-#define I2C_ANA_MST_I2C1_BUSY_V  0x1
-#define I2C_ANA_MST_I2C1_BUSY_S  25
-/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C1_CTRL    0x01FFFFFF
-#define I2C_ANA_MST_I2C1_CTRL_M  ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S))
-#define I2C_ANA_MST_I2C1_CTRL_V  0x1FFFFFF
-#define I2C_ANA_MST_I2C1_CTRL_S  0
-
-#define I2C_ANA_MST_I2C0_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0x8)
-/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C0_STATUS    0x000000FF
-#define I2C_ANA_MST_I2C0_STATUS_M  ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S))
-#define I2C_ANA_MST_I2C0_STATUS_V  0xFF
-#define I2C_ANA_MST_I2C0_STATUS_S  24
-/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C0_CONF    0x00FFFFFF
-#define I2C_ANA_MST_I2C0_CONF_M  ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S))
-#define I2C_ANA_MST_I2C0_CONF_V  0xFFFFFF
-#define I2C_ANA_MST_I2C0_CONF_S  0
-
-#define I2C_ANA_MST_I2C1_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0xC)
-/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C1_STATUS    0x000000FF
-#define I2C_ANA_MST_I2C1_STATUS_M  ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S))
-#define I2C_ANA_MST_I2C1_STATUS_V  0xFF
-#define I2C_ANA_MST_I2C1_STATUS_S  24
-/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C1_CONF    0x00FFFFFF
-#define I2C_ANA_MST_I2C1_CONF_M  ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S))
-#define I2C_ANA_MST_I2C1_CONF_V  0xFFFFFF
-#define I2C_ANA_MST_I2C1_CONF_S  0
-
-#define I2C_ANA_MST_I2C_BURST_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0x10)
-/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_BURST_CTRL    0xFFFFFFFF
-#define I2C_ANA_MST_BURST_CTRL_M  ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S))
-#define I2C_ANA_MST_BURST_CTRL_V  0xFFFFFFFF
-#define I2C_ANA_MST_BURST_CTRL_S  0
-
-#define I2C_ANA_MST_I2C_BURST_STATUS_REG          (DR_REG_I2C_ANA_MST_BASE + 0x14)
-/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
-/*description: .*/
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT    0x00000FFF
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M  ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S))
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V  0xFFF
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S  20
-/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ANA_MST1_BURST_ERR_FLAG    (BIT(2))
-#define I2C_ANA_MST1_BURST_ERR_FLAG_M  (BIT(2))
-#define I2C_ANA_MST1_BURST_ERR_FLAG_V  0x1
-#define I2C_ANA_MST1_BURST_ERR_FLAG_S  2
-/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ANA_MST0_BURST_ERR_FLAG    (BIT(1))
-#define I2C_ANA_MST0_BURST_ERR_FLAG_M  (BIT(1))
-#define I2C_ANA_MST0_BURST_ERR_FLAG_V  0x1
-#define I2C_ANA_MST0_BURST_ERR_FLAG_S  1
-/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ANA_MST_BURST_DONE    (BIT(0))
-#define I2C_ANA_MST_BURST_DONE_M  (BIT(0))
-#define I2C_ANA_MST_BURST_DONE_V  0x1
-#define I2C_ANA_MST_BURST_DONE_S  0
-
-#define I2C_ANA_MST_ANA_CONF0_REG          (DR_REG_I2C_ANA_MST_BASE + 0x18)
-/* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_ANA_STATUS0    0x000000FF
-#define I2C_ANA_MST_ANA_STATUS0_M  ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S))
-#define I2C_ANA_MST_ANA_STATUS0_V  0xFF
-#define I2C_ANA_MST_ANA_STATUS0_S  24
-/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
-/*description: .*/
-#define I2C_ANA_MST_ANA_CONF0    0x00FFFFFF
-#define I2C_ANA_MST_ANA_CONF0_M  ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
-#define I2C_ANA_MST_ANA_CONF0_V  0xFFFFFF
-#define I2C_ANA_MST_ANA_CONF0_S  0
-
-#define I2C_ANA_MST_ANA_CONF1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x1C)
-/* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_ANA_STATUS1    0x000000FF
-#define I2C_ANA_MST_ANA_STATUS1_M  ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S))
-#define I2C_ANA_MST_ANA_STATUS1_V  0xFF
-#define I2C_ANA_MST_ANA_STATUS1_S  24
-/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
-/*description: .*/
-#define I2C_ANA_MST_ANA_CONF1    0x00FFFFFF
-#define I2C_ANA_MST_ANA_CONF1_M  ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
-#define I2C_ANA_MST_ANA_CONF1_V  0xFFFFFF
-#define I2C_ANA_MST_ANA_CONF1_S  0
-
-#define I2C_ANA_MST_ANA_CONF2_REG          (DR_REG_I2C_ANA_MST_BASE + 0x20)
-/* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_ANA_STATUS2    0x000000FF
-#define I2C_ANA_MST_ANA_STATUS2_M  ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
-#define I2C_ANA_MST_ANA_STATUS2_V  0xFF
-#define I2C_ANA_MST_ANA_STATUS2_S  24
-/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
-/*description: .*/
-#define I2C_ANA_MST_ANA_CONF2    0x00FFFFFF
-#define I2C_ANA_MST_ANA_CONF2_M  ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
-#define I2C_ANA_MST_ANA_CONF2_V  0xFFFFFF
-#define I2C_ANA_MST_ANA_CONF2_S  0
-
-#define I2C_ANA_MST_I2C0_CTRL1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x24)
-/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD    0x0000001F
-#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M  ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S))
-#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V  0x1F
-#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S  6
-/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR    0x0000003F
-#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M  ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
-#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V  0x3F
-#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S  0
-
-#define I2C_ANA_MST_I2C1_CTRL1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x28)
-/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD    0x0000001F
-#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M  ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S))
-#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V  0x1F
-#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S  6
-/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
-/*description: .*/
-#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR    0x0000003F
-#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M  ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S))
-#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V  0x3F
-#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S  0
-
-#define I2C_ANA_MST_HW_I2C_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x2C)
-/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_ARBITER_DIS    (BIT(11))
-#define I2C_ANA_MST_ARBITER_DIS_M  (BIT(11))
-#define I2C_ANA_MST_ARBITER_DIS_V  0x1
-#define I2C_ANA_MST_ARBITER_DIS_S  11
-/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
-/*description: .*/
-#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD    0x0000001F
-#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M  ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S))
-#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V  0x1F
-#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S  6
-/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
-/*description: .*/
-#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR    0x0000003F
-#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M  ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S))
-#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V  0x3F
-#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S  0
-
-#define I2C_ANA_MST_NOUSE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x30)
-/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_NOUSE    0xFFFFFFFF
-#define I2C_ANA_MST_NOUSE_M  ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
-#define I2C_ANA_MST_NOUSE_V  0xFFFFFFFF
-#define I2C_ANA_MST_NOUSE_S  0
-
-#define I2C_ANA_MST_DATE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x34)
-/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
-/*description: .*/
-#define I2C_ANA_MST_CLK_EN    (BIT(28))
-#define I2C_ANA_MST_CLK_EN_M  (BIT(28))
-#define I2C_ANA_MST_CLK_EN_V  0x1
-#define I2C_ANA_MST_CLK_EN_S  28
-/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */
-/*description: .*/
-#define I2C_ANA_MST_DATE    0x0FFFFFFF
-#define I2C_ANA_MST_DATE_M  ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S))
-#define I2C_ANA_MST_DATE_V  0xFFFFFFF
-#define I2C_ANA_MST_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/mp/include/soc/interrupt_reg.h b/components/soc/esp32c5/mp/include/soc/interrupt_reg.h
deleted file mode 100644
index 4bfbc07b86..0000000000
--- a/components/soc/esp32c5/mp/include/soc/interrupt_reg.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#include "soc/clic_reg.h"
-#include "soc/soc_caps.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * ESP32C5 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
- */
-#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG   (CLIC_INT_THRESH_REG)
-
-/* We only have a single core on the C5, CORE0 */
-#define INTERRUPT_CORE0_CPU_INT_THRESH_REG      INTERRUPT_CURRENT_CORE_INT_THRESH_REG
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h
deleted file mode 100644
index 36606db909..0000000000
--- a/components/soc/esp32c5/mp/include/soc/soc_caps.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * These defines are parsed and imported as kconfig variables via the script
- * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
- *
- * If this file is changed the script will automatically run the script
- * and generate the kconfig variables as part of the pre-commit hooks.
- *
- * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md`
- */
-
-#pragma once
-
-/*-------------------------- COMMON CAPS ---------------------------------------*/
-// #define SOC_ADC_SUPPORTED               1  // TODO: [ESP32C5] IDF-8701
-// #define SOC_DEDICATED_GPIO_SUPPORTED    1  // TODO: [ESP32C5] IDF-8725
-#define SOC_UART_SUPPORTED              1
-#define SOC_GDMA_SUPPORTED              1
-#define SOC_AHB_GDMA_SUPPORTED          1
-#define SOC_GPTIMER_SUPPORTED           1
-#define SOC_PCNT_SUPPORTED              1
-#define SOC_MCPWM_SUPPORTED             1
-// #define SOC_TWAI_SUPPORTED              1  // TODO: [ESP32C5] IDF-8691
-// #define SOC_ETM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8693
-// #define SOC_PARLIO_SUPPORTED            1  // TODO: [ESP32C5] IDF-8685, IDF-8686
-#define SOC_ASYNC_MEMCPY_SUPPORTED      1
-// #define SOC_USB_SERIAL_JTAG_SUPPORTED   1  // TODO: [ESP32C5] IDF-8721
-// #define SOC_TEMP_SENSOR_SUPPORTED       1  // TODO: [ESP32C5] IDF-8727
-// #define SOC_WIFI_SUPPORTED              1  // TODO: [ESP32C5] IDF-8851
-#define SOC_SUPPORTS_SECURE_DL_MODE     1
-// #define SOC_LP_CORE_SUPPORTED           1  // TODO: [ESP32C5] IDF-8637
-#define SOC_EFUSE_KEY_PURPOSE_FIELD     1
-#define SOC_EFUSE_SUPPORTED             1
-#define SOC_RTC_FAST_MEM_SUPPORTED      1
-#define SOC_RTC_MEM_SUPPORTED           1
-#define SOC_I2S_SUPPORTED               1
-#define SOC_RMT_SUPPORTED               1
-// #define SOC_SDM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8687
-#define SOC_GPSPI_SUPPORTED             1
-#define SOC_LEDC_SUPPORTED              1
-// #define SOC_I2C_SUPPORTED               1  // TODO: [ESP32C5] IDF-8694, IDF-8696
-#define SOC_SYSTIMER_SUPPORTED          1     // TODO: [ESP32C5] IDF-8707
-#define SOC_AES_SUPPORTED               1
-#define SOC_MPI_SUPPORTED               1
-#define SOC_SHA_SUPPORTED               1
-#define SOC_RSA_SUPPORTED               1
-#define SOC_HMAC_SUPPORTED              1
-#define SOC_DIG_SIGN_SUPPORTED          1
-#define SOC_ECC_SUPPORTED               1
-#define SOC_ECC_EXTENDED_MODES_SUPPORTED   1
-#define SOC_FLASH_ENC_SUPPORTED         1
-#define SOC_SECURE_BOOT_SUPPORTED       1
-// #define SOC_BOD_SUPPORTED               1  // TODO: [ESP32C5] IDF-8647
-// #define SOC_APM_SUPPORTED               1  // TODO: [ESP32C5] IDF-8614, IDF-8615
-// #define SOC_PMU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8667
-// #define SOC_PAU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8638
-// #define SOC_LP_TIMER_SUPPORTED          1  // TODO: [ESP32C5] IDF-8636
-// #define SOC_LP_AON_SUPPORTED            1  // TODO: [ESP32C5] IDF-8638
-#define SOC_LP_PERIPHERALS_SUPPORTED    1
-// #define SOC_LP_I2C_SUPPORTED            1  // TODO: [ESP32C5] IDF-8634
-// #define SOC_ULP_LP_UART_SUPPORTED       1  // TODO: [ESP32C5] IDF-8633
-// #define SOC_CLK_TREE_SUPPORTED          1  // TODO: [ESP32C5] IDF-8642
-// #define SOC_ASSIST_DEBUG_SUPPORTED      1  // TODO: [ESP32C5] IDF-8663
-// #define SOC_WDT_SUPPORTED               1  // TODO: [ESP32C5] IDF-8650
-#define SOC_SPI_FLASH_SUPPORTED         1     // TODO: [ESP32C5] IDF-8715
-// #define SOC_BITSCRAMBLER_SUPPORTED      1  // TODO: [ESP32C5] IDF-8711
-#define SOC_ECDSA_SUPPORTED             1
-// #define SOC_KEY_MANAGER_SUPPORTED       1  // TODO: [ESP32C5] IDF-8621
-// #define SOC_HUK_SUPPORTED               1  // TODO: [ESP32C5] IDF-8617
-// #define SOC_MODEM_CLOCK_SUPPORTED       1  // TODO: [ESP32C5] IDF-8845
-// #define SOC_PM_SUPPORTED                1  // TODO: [ESP32C5] IDF-8643
-
-/*-------------------------- XTAL CAPS ---------------------------------------*/
-#define SOC_XTAL_SUPPORT_40M            1
-#define SOC_XTAL_SUPPORT_48M            1
-#define SOC_XTAL_SUPPORT_EFUSE_SEL      1   // XTAL freq in runtime determined through EFUSE_XTAL_48M_SEL
-
-/*-------------------------- AES CAPS -----------------------------------------*/
-#define SOC_AES_SUPPORT_DMA     (1)
-
-/* Has a centralized DMA, which is shared with all peripherals */
-#define SOC_AES_GDMA            (1)
-
-#define SOC_AES_SUPPORT_AES_128 (1)
-#define SOC_AES_SUPPORT_AES_256 (1)
-
-/*-------------------------- ADC CAPS -------------------------------*/
-/*!< SAR ADC Module*/
-// #define SOC_ADC_DIG_CTRL_SUPPORTED              1
-// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
-// #define SOC_ADC_MONITOR_SUPPORTED               1
-// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
-// #define SOC_ADC_DMA_SUPPORTED                   1
-#define SOC_ADC_PERIPH_NUM                      (1U)
-// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (7)
-#define SOC_ADC_MAX_CHANNEL_NUM                 (7)
-// #define SOC_ADC_ATTEN_NUM                       (4)
-
-/*!< Digital */
-// #define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
-// #define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
-// #define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
-// #define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
-// #define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
-// #define SOC_ADC_DIGI_MONITOR_NUM                (2)
-// #define SOC_ADC_DIGI_RESULT_BYTES               (4)
-// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
-/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
-// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
-// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
-
-/*!< RTC */
-// #define SOC_ADC_RTC_MIN_BITWIDTH                (12)
-// #define SOC_ADC_RTC_MAX_BITWIDTH                (12)
-
-/*!< Calibration */
-// #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
-// #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
-// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
-
-/*!< Interrupt */
-// #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
-
-/*!< ADC power control is shared by PWDET */
-// #define SOC_ADC_SHARED_POWER                    1
-
-// ESP32C5-TODO: Copy from esp32C5, need check
-/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
-// #define SOC_APB_BACKUP_DMA              (0)
-
-/*-------------------------- BROWNOUT CAPS -----------------------------------*/
-// #define SOC_BROWNOUT_RESET_SUPPORTED 1
-
-/*-------------------------- CACHE CAPS --------------------------------------*/
-#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
-#define SOC_CACHE_FREEZE_SUPPORTED              1
-
-/*-------------------------- CPU CAPS ----------------------------------------*/
-#define SOC_CPU_CORES_NUM               (1U)
-#define SOC_CPU_INTR_NUM                32
-#define SOC_CPU_HAS_FLEXIBLE_INTC       1
-#define SOC_INT_CLIC_SUPPORTED          1
-#define SOC_INT_HW_NESTED_SUPPORTED     1       // Support for hardware interrupts nesting
-#define SOC_BRANCH_PREDICTOR_SUPPORTED  1
-
-#define SOC_CPU_BREAKPOINTS_NUM         4
-#define SOC_CPU_WATCHPOINTS_NUM         4
-#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE         0x100 // bytes
-
-#define SOC_CPU_HAS_PMA                 1
-#define SOC_CPU_IDRAM_SPLIT_USING_PMP   1
-
-/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
-/** The maximum length of a Digital Signature in bits. */
-#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
-
-/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
-#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
-
-/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
-    See TRM DS chapter for more details */
-#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
-
-/*-------------------------- DMA Common CAPS ----------------------------------------*/
-#define SOC_DMA_CAN_ACCESS_FLASH 1 /*!< DMA can access Flash memory */
-
-/*-------------------------- GDMA CAPS -------------------------------------*/
-#define SOC_AHB_GDMA_VERSION            2
-#define SOC_GDMA_NUM_GROUPS_MAX         1U
-#define SOC_GDMA_PAIRS_PER_GROUP_MAX    3
-// #define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule TODO: IDF-9224
-// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1  // TODO: IDF-9225
-
-/*-------------------------- ETM CAPS --------------------------------------*/
-// #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
-// #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
-
-/*-------------------------- GPIO CAPS ---------------------------------------*/
-// ESP32-C5 has 1 GPIO peripheral
-#define SOC_GPIO_PORT                      1U
-#define SOC_GPIO_PIN_COUNT                 29
-// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
-// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
-#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER      1
-
-// GPIO peripheral has the ETM extension
-// #define SOC_GPIO_SUPPORT_ETM          1
-
-// Target has the full LP IO subsystem
-// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
-#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
-// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
-// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  // TODO: [ESP32C5] IDF-8719
-
-#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
-#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
-
-#define SOC_GPIO_IN_RANGE_MAX           28
-#define SOC_GPIO_OUT_RANGE_MAX          28
-
-#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
-
-// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
-#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL
-
-// Support to force hold all IOs
-#define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
-// Support to hold a single digital I/O when the digital domain is powered off
-#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
-
-// The Clock Out signal is route to the pin by GPIO matrix
-// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
-#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
-
-/*-------------------------- RTCIO CAPS --------------------------------------*/
-#define SOC_RTCIO_PIN_COUNT                 0UL
-// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1  /* This macro indicates that the target has separate RTC IOMUX hardware feature,
-                                            //  * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
-                                            //  * when the pins are switched to RTC function.
-                                            //  */
-// #define SOC_RTCIO_HOLD_SUPPORTED            1
-// #define SOC_RTCIO_WAKE_SUPPORTED            1
-
-/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
-// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
-// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
-// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
-
-/*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C5 has 1 I2C
-#define SOC_I2C_NUM                 (1U)
-#define SOC_HP_I2C_NUM              (1U)
-
-// #define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-// #define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-// #define SOC_I2C_SUPPORT_SLAVE       (1)
-
-// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
-// #define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
-
-// #define SOC_I2C_SUPPORT_XTAL        (1)
-// #define SOC_I2C_SUPPORT_RTC         (1)
-// #define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
-
-// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693
-
-/*-------------------------- LP_I2C CAPS -------------------------------------*/
-// ESP32-C5 has 1 LP_I2C
-// #define SOC_LP_I2C_NUM              (1U)
-
-// #define SOC_LP_I2C_FIFO_LEN         (16) /*!< LP_I2C hardware FIFO depth */
-
-/*-------------------------- I2S CAPS ----------------------------------------*/
-#define SOC_I2S_NUM                 (1U)
-#define SOC_I2S_HW_VERSION_2        (1)
-#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
-// #define SOC_I2S_SUPPORTS_RX_RECOMB  (1) //TODO[C5] IDF-9966
-#define SOC_I2S_SUPPORTS_XTAL       (1)
-#define SOC_I2S_SUPPORTS_PLL_F160M  (1)
-#define SOC_I2S_SUPPORTS_PLL_F240M  (1)
-#define SOC_I2S_SUPPORTS_PCM        (1)
-#define SOC_I2S_SUPPORTS_PDM        (1)
-#define SOC_I2S_SUPPORTS_PDM_TX     (1)
-#define SOC_I2S_PDM_MAX_TX_LINES    (2)
-#define SOC_I2S_SUPPORTS_TDM        (1)
-#define SOC_I2S_TDM_FULL_DATA_WIDTH (1)  /*!< No limitation to data bit width when using multiple slots */
-
-/*-------------------------- LEDC CAPS ---------------------------------------*/
-#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
-#define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
-#define SOC_LEDC_CHANNEL_NUM                (6)
-#define SOC_LEDC_TIMER_BIT_WIDTH            (20)
-#define SOC_LEDC_SUPPORT_FADE_STOP          (1)
-#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
-#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
-#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
-
-/*-------------------------- MMU CAPS ----------------------------------------*/
-// TODO: [ESP32C5] IDF-8658
-// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (1)
-#define SOC_MMU_PERIPH_NUM                    (1U)
-#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM     (1U)
-#define SOC_MMU_DI_VADDR_SHARED               (1) /*!< D/I vaddr are shared */
-
-/*-------------------------- MPU CAPS ----------------------------------------*/
-// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
-// #define SOC_MPU_MIN_REGION_SIZE                   0x20000000U
-// #define SOC_MPU_REGIONS_MAX_NUM                   8
-// #define SOC_MPU_REGION_RO_SUPPORTED               0
-// #define SOC_MPU_REGION_WO_SUPPORTED               0
-
-/*-------------------------- PCNT CAPS ---------------------------------------*/
-#define SOC_PCNT_GROUPS                       1U
-#define SOC_PCNT_UNITS_PER_GROUP              4
-#define SOC_PCNT_CHANNELS_PER_UNIT            2
-#define SOC_PCNT_THRES_POINT_PER_UNIT         2
-#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
-#define SOC_PCNT_SUPPORT_CLEAR_SIGNAL         1
-// #define SOC_PCNT_SUPPORT_STEP_NOTIFY          1 // IDF-7984
-
-/*--------------------------- RMT CAPS ---------------------------------------*/
-#define SOC_RMT_GROUPS                        1U /*!< One RMT group */
-#define SOC_RMT_TX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Transmit */
-#define SOC_RMT_RX_CANDIDATES_PER_GROUP       2  /*!< Number of channels that capable of Receive */
-#define SOC_RMT_CHANNELS_PER_GROUP            4  /*!< Total 4 channels */
-#define SOC_RMT_MEM_WORDS_PER_CHANNEL         48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
-#define SOC_RMT_SUPPORT_RX_PINGPONG           1  /*!< Support Ping-Pong mode on RX path */
-#define SOC_RMT_SUPPORT_RX_DEMODULATION       1  /*!< Support signal demodulation on RX path (i.e. remove carrier) */
-#define SOC_RMT_SUPPORT_TX_ASYNC_STOP         1  /*!< Support stop transmission asynchronously */
-#define SOC_RMT_SUPPORT_TX_LOOP_COUNT         1  /*!< Support transmit specified number of cycles in loop mode */
-#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP     1  /*!< Hardware support of auto-stop in loop mode */
-#define SOC_RMT_SUPPORT_TX_SYNCHRO            1  /*!< Support coordinate a group of TX channels to start simultaneously */
-#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY  1  /*!< TX carrier can be modulated to data phase only */
-#define SOC_RMT_SUPPORT_XTAL                  1  /*!< Support set XTAL clock as the RMT clock source */
-// #define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST as the RMT clock source */
-
-/*-------------------------- MCPWM CAPS --------------------------------------*/
-#define SOC_MCPWM_GROUPS                         1U ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
-#define SOC_MCPWM_TIMERS_PER_GROUP               3  ///< The number of timers that each group has
-#define SOC_MCPWM_OPERATORS_PER_GROUP            3  ///< The number of operators that each group has
-#define SOC_MCPWM_COMPARATORS_PER_OPERATOR       2  ///< The number of comparators that each operator has
-#define SOC_MCPWM_GENERATORS_PER_OPERATOR        2  ///< The number of generators that each operator has
-#define SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR 2  ///< The number of event comparators that each operator has
-#define SOC_MCPWM_TRIGGERS_PER_OPERATOR          2  ///< The number of triggers that each operator has
-#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP          3  ///< The number of fault signal detectors that each group has
-#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP       1  ///< The number of capture timers that each group has
-#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER     3  ///< The number of capture channels that each capture timer has
-#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP        3  ///< The number of GPIO synchros that each group has
-#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE           1  ///< Software sync event can be routed to its output
-// #define SOC_MCPWM_SUPPORT_ETM                    1  ///< Support ETM (Event Task Matrix)
-#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR       1  ///< Support event comparator (based on ETM)
-#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP         1  ///< Capture timer shares clock with other PWM timers
-
-/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
-// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
-
-/*-------------------------- PARLIO CAPS --------------------------------------*/
-// #define SOC_PARLIO_GROUPS                    1U  /*!< Number of parallel IO peripherals */
-// #define SOC_PARLIO_TX_UNITS_PER_GROUP        1U  /*!< number of TX units in each group */
-// #define SOC_PARLIO_RX_UNITS_PER_GROUP        1U  /*!< number of RX units in each group */
-// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
-// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
-// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT     1   /*!< TX and RX unit share the same interrupt source number */
-
-/*--------------------------- MPI CAPS ---------------------------------------*/
-#define SOC_MPI_MEM_BLOCKS_NUM (4)
-#define SOC_MPI_OPERATIONS_NUM (3)
-
-/*--------------------------- RSA CAPS ---------------------------------------*/
-#define SOC_RSA_MAX_BIT_LEN    (3072)
-
-/*--------------------------- SHA CAPS ---------------------------------------*/
-
-/* Max amount of bytes in a single DMA operation is 4095,
-   for SHA this means that the biggest safe amount of bytes is
-   31 blocks of 128 bytes = 3968
-*/
-#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
-#define SOC_SHA_SUPPORT_DMA             (1)
-
-/* The SHA engine is able to resume hashing from a user */
-#define SOC_SHA_SUPPORT_RESUME          (1)
-
-/* Has a centralized DMA, which is shared with all peripherals */
-#define SOC_SHA_GDMA             (1)
-
-/* Supported HW algorithms */
-#define SOC_SHA_SUPPORT_SHA1            (1)
-#define SOC_SHA_SUPPORT_SHA224          (1)
-#define SOC_SHA_SUPPORT_SHA256          (1)
-
-/*--------------------------- ECDSA CAPS ---------------------------------------*/
-#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY     (1)
-
-/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
-// #define SOC_SDM_GROUPS               1U
-// #define SOC_SDM_CHANNELS_PER_GROUP   4
-// #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
-// #define SOC_SDM_CLK_SUPPORT_XTAL     1
-
-/*-------------------------- SPI CAPS ----------------------------------------*/
-#define SOC_SPI_PERIPH_NUM          2
-#define SOC_SPI_PERIPH_CS_NUM(i)    6
-#define SOC_SPI_MAX_CS_NUM          6
-#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
-
-#define SOC_SPI_SUPPORT_DDRCLK              1
-#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
-#define SOC_SPI_SUPPORT_CD_SIG              1
-#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
-#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
-#define SOC_SPI_SUPPORT_CLK_XTAL            1
-// #define SOC_SPI_SUPPORT_CLK_PLL_F80M        1
-// #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
-
-// Peripheral supports DIO, DOUT, QIO, or QOUT
-// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
-#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)  ({(void)host_id; 1;})
-
-#define SOC_MEMSPI_IS_INDEPENDENT 1
-#define SOC_SPI_MAX_PRE_DIVIDER 16
-
-/*-------------------------- SPI MEM CAPS ---------------------------------------*/
-// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
-// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
-// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
-// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
-// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
-// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
-// #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
-
-// TODO: [ESP32C5] IDF-8649
-#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED         1
-
-/*-------------------------- SYSTIMER CAPS ----------------------------------*/
-// TODO: [ESP32C5] IDF-8707
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
-// #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event
-
-/*-------------------------- LP_TIMER CAPS ----------------------------------*/
-// #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
-// #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
-
-/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
-#define SOC_TIMER_GROUPS                  (2)
-#define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
-#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
-#define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
-#define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
-// #define SOC_TIMER_SUPPORT_ETM             (1)
-// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
-
-/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
-// #define SOC_MWDT_SUPPORT_XTAL              (1)
-
-/*-------------------------- TWAI CAPS ---------------------------------------*/
-// #define SOC_TWAI_CONTROLLER_NUM         2
-// #define SOC_TWAI_CLK_SUPPORT_XTAL       1
-// #define SOC_TWAI_BRP_MIN                2
-// #define SOC_TWAI_BRP_MAX                32768
-// #define SOC_TWAI_SUPPORTS_RX_STATUS     1
-
-/*-------------------------- eFuse CAPS----------------------------*/
-// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
-// #define SOC_EFUSE_DIS_PAD_JTAG 1
-// #define SOC_EFUSE_DIS_USB_JTAG 1
-// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
-// #define SOC_EFUSE_SOFT_DIS_JTAG 1
-// #define SOC_EFUSE_DIS_ICACHE 1
-#define SOC_EFUSE_ECDSA_KEY 1
-
-/*-------------------------- Secure Boot CAPS----------------------------*/
-#define SOC_SECURE_BOOT_V2_RSA              1
-#define SOC_SECURE_BOOT_V2_ECC              1
-#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
-#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS   1
-#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY  1
-
-/*-------------------------- Flash Encryption CAPS----------------------------*/
-#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX   (64)
-#define SOC_FLASH_ENCRYPTION_XTS_AES        1
-#define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
-
-/*------------------------ Anti DPA (Security) CAPS --------------------------*/
-// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED     1
-
-/*-------------------------- UART CAPS ---------------------------------------*/
-// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
-#define SOC_UART_NUM                    (3)
-#define SOC_UART_HP_NUM                 (2)
-#define SOC_UART_LP_NUM                 (1U)
-#define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
-#define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
-#define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
-// #define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
-// #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */ // TODO: [ESP32C5] IDF-8642
-#define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
-#define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
-#define SOC_UART_HAS_LP_UART            (1)         /*!< Support LP UART */
-
-// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
-
-/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
-// #define SOC_COEX_HW_PTI                 (1)
-
-/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
-// #define SOC_EXTERNAL_COEX_ADVANCE              (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
-// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE       (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
-
-/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
-// #define SOC_PHY_DIG_REGS_MEM_SIZE       (21*4)
-
-/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
-// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH  (12)
-
-/*-------------------------- Power Management CAPS ----------------------------*/
-// #define SOC_PM_SUPPORT_WIFI_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_BEACON_WAKEUP    (1)
-// #define SOC_PM_SUPPORT_BT_WAKEUP        (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP      (1)
-// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN   (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
-// #define SOC_PM_SUPPORT_CPU_PD           (1)
-#define SOC_PM_SUPPORT_MODEM_PD         (1)
-#define SOC_PM_SUPPORT_XTAL32K_PD       (1)
-#define SOC_PM_SUPPORT_RC32K_PD         (1)
-#define SOC_PM_SUPPORT_RC_FAST_PD       (1)
-#define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
-#define SOC_PM_SUPPORT_TOP_PD           (1)
-#define SOC_PM_SUPPORT_HP_AON_PD        (1)
-// #define SOC_PM_SUPPORT_MAC_BB_PD        (1)
-#define SOC_PM_SUPPORT_RTC_PERIPH_PD    (1)
-
-// #define SOC_PM_SUPPORT_PMU_MODEM_STATE  (1)
-/* macro redefine for pass esp_wifi headers md5sum check */
-// #define MAC_SUPPORT_PMU_MODEM_STATE     SOC_PM_SUPPORT_PMU_MODEM_STATE
-
-// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
-
-// #define SOC_PM_CPU_RETENTION_BY_SW          (1)
-// #define SOC_PM_MODEM_RETENTION_BY_REGDMA    (1)
-// #define SOC_PM_RETENTION_HAS_CLOCK_BUG      (1)
-
-// #define SOC_PM_PAU_LINK_NUM             (4)
-
-/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
-// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1) // TODO: IDF-8642
-#define SOC_MODEM_CLOCK_IS_INDEPENDENT            (1)
-
-#define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
-#define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
-#define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
-
-#define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
-
-/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
-// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
-// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)
-// #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
-
-/*------------------------------------ WI-FI CAPS ------------------------------------*/
-// #define SOC_WIFI_HW_TSF                     (1)    /*!< Support hardware TSF */
-// #define SOC_WIFI_FTM_SUPPORT                (0)    /*!< Support FTM */
-// #define SOC_WIFI_GCMP_SUPPORT               (1)    /*!< Support GCMP(GCMP128 and GCMP256) */
-// #define SOC_WIFI_WAPI_SUPPORT               (1)    /*!< Support WAPI */
-// #define SOC_WIFI_CSI_SUPPORT                (1)    /*!< Support CSI */
-// #define SOC_WIFI_MESH_SUPPORT               (1)    /*!< Support WIFI MESH */
-// #define SOC_WIFI_HE_SUPPORT                 (1)    /*!< Support Wi-Fi 6 */
-
-/*---------------------------------- Bluetooth CAPS ----------------------------------*/
-// #define SOC_BLE_SUPPORTED               (1)    /*!< Support Bluetooth Low Energy hardware */
-// #define SOC_BLE_MESH_SUPPORTED          (1)    /*!< Support BLE MESH */
-// #define SOC_ESP_NIMBLE_CONTROLLER       (1)    /*!< Support BLE EMBEDDED controller V1 */
-// #define SOC_BLE_50_SUPPORTED            (1)    /*!< Support Bluetooth 5.0 */
-// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1)   /*!< Support BLE device privacy mode */
-// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1)    /*!< Support Bluetooth Power Control */
-// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED  (1)    /*!< Support For BLE Periodic Adv Enhancements */
-// #define SOC_BLUFI_SUPPORTED             (1)    /*!< Support BLUFI */
-// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1)    /*!< Support multiple connections optimization */
-
-// #define SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND (1)
-
-/*------------------------------------- PHY CAPS -------------------------------------*/
-// #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
diff --git a/components/soc/esp32c5/mp/mpi_periph.c b/components/soc/esp32c5/mp/mpi_periph.c
deleted file mode 100644
index b41e252944..0000000000
--- a/components/soc/esp32c5/mp/mpi_periph.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/rsa_reg.h"
-#include "soc/mpi_periph.h"
-
-const uint32_t MPI_BLOCK_BASES[SOC_MPI_MEM_BLOCKS_NUM] = {
-    RSA_X_MEM,
-    RSA_Y_MEM,
-    RSA_Z_MEM,
-    RSA_M_MEM,
-};
-
-const uint32_t MPI_OPERATIONS_REG[SOC_MPI_OPERATIONS_NUM] = {
-    RSA_SET_START_MULT_REG,
-    RSA_SET_START_MODMULT_REG,
-    RSA_SET_START_MODEXP_REG,
-};
diff --git a/components/soc/esp32c5/mp/pcnt_periph.c b/components/soc/esp32c5/mp/pcnt_periph.c
deleted file mode 100644
index 162db5aa27..0000000000
--- a/components/soc/esp32c5/mp/pcnt_periph.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/pcnt_periph.h"
-#include "soc/gpio_sig_map.h"
-
-const pcnt_signal_conn_t pcnt_periph_signals = {
-    .groups = {
-        [0] = {
-            .irq = ETS_PCNT_INTR_SOURCE,
-            .units = {
-                [0] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = PCNT_CTRL_CH0_IN0_IDX,
-                            .pulse_sig = PCNT_SIG_CH0_IN0_IDX
-                        },
-                        [1] = {
-                            .control_sig = PCNT_CTRL_CH1_IN0_IDX,
-                            .pulse_sig = PCNT_SIG_CH1_IN0_IDX
-                        }
-                    },
-                    .clear_sig = PCNT_RST_IN0_IDX
-                },
-                [1] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = PCNT_CTRL_CH0_IN1_IDX,
-                            .pulse_sig = PCNT_SIG_CH0_IN1_IDX,
-                        },
-                        [1] = {
-                            .control_sig = PCNT_CTRL_CH1_IN1_IDX,
-                            .pulse_sig = PCNT_SIG_CH1_IN1_IDX
-                        }
-                    },
-                    .clear_sig = PCNT_RST_IN1_IDX
-                },
-                [2] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = PCNT_CTRL_CH0_IN2_IDX,
-                            .pulse_sig = PCNT_SIG_CH0_IN2_IDX,
-                        },
-                        [1] = {
-                            .control_sig = PCNT_CTRL_CH1_IN2_IDX,
-                            .pulse_sig = PCNT_SIG_CH1_IN2_IDX
-                        }
-                    },
-                    .clear_sig = PCNT_RST_IN2_IDX
-                },
-                [3] = {
-                    .channels = {
-                        [0] = {
-                            .control_sig = PCNT_CTRL_CH0_IN3_IDX,
-                            .pulse_sig = PCNT_SIG_CH0_IN3_IDX,
-                        },
-                        [1] = {
-                            .control_sig = PCNT_CTRL_CH1_IN3_IDX,
-                            .pulse_sig = PCNT_SIG_CH1_IN3_IDX
-                        }
-                    },
-                    .clear_sig = PCNT_RST_IN3_IDX
-                }
-            }
-        }
-    }
-};
diff --git a/components/soc/esp32c5/mp/rmt_periph.c b/components/soc/esp32c5/mp/rmt_periph.c
deleted file mode 100644
index 29600b11c0..0000000000
--- a/components/soc/esp32c5/mp/rmt_periph.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/rmt_periph.h"
-#include "soc/gpio_sig_map.h"
-
-const rmt_signal_conn_t rmt_periph_signals = {
-    .groups = {
-        [0] = {
-            .irq = ETS_RMT_INTR_SOURCE,
-            .channels = {
-                [0] = {
-                    .tx_sig = RMT_SIG_OUT0_IDX,
-                    .rx_sig = -1
-                },
-                [1] = {
-                    .tx_sig = RMT_SIG_OUT1_IDX,
-                    .rx_sig = -1
-                },
-                [2] = {
-                    .tx_sig = -1,
-                    .rx_sig = RMT_SIG_IN0_IDX
-                },
-                [3] = {
-                    .tx_sig = -1,
-                    .rx_sig = RMT_SIG_IN1_IDX
-                },
-            }
-        }
-    }
-};
diff --git a/components/soc/esp32c5/mp/timer_periph.c b/components/soc/esp32c5/mp/timer_periph.c
deleted file mode 100644
index 7036e7ca81..0000000000
--- a/components/soc/esp32c5/mp/timer_periph.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/timer_periph.h"
-
-const timer_group_signal_conn_t timer_group_periph_signals = {
-    .groups = {
-        [0] = {
-            .module = PERIPH_TIMG0_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
-            }
-        },
-        [1] = {
-            .module = PERIPH_TIMG1_MODULE,
-            .timer_irq_id = {
-                [0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
-            }
-        }
-    }
-};
-
-#if SOC_TIMER_SUPPORT_SLEEP_RETENTION
-#define N_REGS_TGWDT          6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
-
-static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
-    /*Timer group backup. should get of write project firstly. wdt used by RTOS.*/
-    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0),    TIMG_WDTCONFIG0_REG(0),  N_REGS_TGWDT,              0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [2] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(0),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(0),TIMG_INT_ENA_TIMERS_REG(0), 1,                      0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(0),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
-};
-
-static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
-    /*Timer group0 backup. T0_wdt should get of write project firstly. wdt used by RTOS.*/
-    [0] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1),   TIMG_WDT_WKEY_VALUE,     TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_INT_ENA_TIMERS_REG(1),TIMG_INT_ENA_TIMERS_REG(1), 1,                      0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(1),    TIMG_WDTCONFIG0_REG(1),  N_REGS_TGWDT,              0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [3] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1),    TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [4] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(1),       TIMG_WDT_FEED,           TIMG_WDT_FEED_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT     (REGDMA_TG1_WDT_LINK(0x04), TIMG_WDTWPROTECT_REG(1),   0,                       TIMG_WDT_WKEY_M,           1, 0), .owner = ENTRY(0) | ENTRY(2) },
-};
-
-/*  Registers in retention context:
- *      TIMG_T0CONFIG_REG
- *      TIMG_T0ALARMLO_REG
- *      TIMG_T0ALARMHI_REG
- *      TIMG_INT_ENA_TIMERS_REG
- *      TIMG_REGCLK_REG
- */
-#define N_REGS_TG_TIMER_CFG            5
-static const uint32_t tg_timer_regs_map[4] = {0x10000031, 0x80000000, 0, 0};
-
-const regdma_entries_config_t tg0_timer_regs_retention[] = {
-    [0] = {
-        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x00),         TIMG_T0CONFIG_REG(0),   TIMG_T0CONFIG_REG(0),   N_REGS_TG_TIMER_CFG, 0, 0, \
-                                            tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]),  .owner = ENTRY(0) | ENTRY(2)
-    },
-    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x01),        TIMG_T0UPDATE_REG(0),   TIMG_T0_UPDATE,         TIMG_T0_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) },
-    [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02),         TIMG_T0UPDATE_REG(0),   0x0,                    TIMG_T0_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) },
-    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x03),   TIMG_T0LO_REG(0),       TIMG_T0LOADLO_REG(0),   2,                   0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x04),   TIMG_T0HI_REG(0),       TIMG_T0LOADHI_REG(0),   2,                   0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05),        TIMG_T0LOAD_REG(0),     0x1,                    TIMG_T0_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
-};
-
-const regdma_entries_config_t tg1_timer_regs_retention[] = {
-    [0] = {
-        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x00),         TIMG_T0CONFIG_REG(1),   TIMG_T0CONFIG_REG(1),   N_REGS_TG_TIMER_CFG, 0, 0, \
-                                            tg_timer_regs_map[0], tg_timer_regs_map[1], tg_timer_regs_map[2], tg_timer_regs_map[3]),  .owner = ENTRY(0) | ENTRY(2)
-    },
-    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x01),        TIMG_T0UPDATE_REG(1),   TIMG_T0_UPDATE,         TIMG_T0_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) },
-    [2] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02),         TIMG_T0UPDATE_REG(0),   0x0,                    TIMG_T0_UPDATE_M,    0, 1), .owner = ENTRY(0) | ENTRY(2) },
-    [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x03),   TIMG_T0LO_REG(1),       TIMG_T0LOADLO_REG(1),   2,                   0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x04),   TIMG_T0HI_REG(1),       TIMG_T0LOADHI_REG(1),   2,                   0, 0), .owner = ENTRY(0) | ENTRY(2) },
-    [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05),        TIMG_T0LOAD_REG(1),     0x1,                    TIMG_T0_LOAD_M,      1, 0), .owner = ENTRY(0) | ENTRY(2) },
-};
-
-const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
-    [0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
-    [1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
-};
-
-const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = {
-    [0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)},
-    [1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)},
-};
-#endif
diff --git a/components/soc/esp32c5/beta3/mpi_periph.c b/components/soc/esp32c5/mpi_periph.c
similarity index 100%
rename from components/soc/esp32c5/beta3/mpi_periph.c
rename to components/soc/esp32c5/mpi_periph.c
diff --git a/components/soc/esp32c5/beta3/pcnt_periph.c b/components/soc/esp32c5/pcnt_periph.c
similarity index 100%
rename from components/soc/esp32c5/beta3/pcnt_periph.c
rename to components/soc/esp32c5/pcnt_periph.c
diff --git a/components/soc/esp32c5/beta3/rmt_periph.c b/components/soc/esp32c5/rmt_periph.c
similarity index 100%
rename from components/soc/esp32c5/beta3/rmt_periph.c
rename to components/soc/esp32c5/rmt_periph.c
diff --git a/components/soc/esp32c5/mp/spi_periph.c b/components/soc/esp32c5/spi_periph.c
similarity index 100%
rename from components/soc/esp32c5/mp/spi_periph.c
rename to components/soc/esp32c5/spi_periph.c
diff --git a/components/soc/esp32c5/beta3/timer_periph.c b/components/soc/esp32c5/timer_periph.c
similarity index 100%
rename from components/soc/esp32c5/beta3/timer_periph.c
rename to components/soc/esp32c5/timer_periph.c
diff --git a/components/soc/esp32c5/mp/uart_periph.c b/components/soc/esp32c5/uart_periph.c
similarity index 100%
rename from components/soc/esp32c5/mp/uart_periph.c
rename to components/soc/esp32c5/uart_periph.c
diff --git a/components/soc/esp32c61/include/soc/adc_channel.h b/components/soc/esp32c61/include/soc/adc_channel.h
new file mode 100644
index 0000000000..c3a9f1c748
--- /dev/null
+++ b/components/soc/esp32c61/include/soc/adc_channel.h
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+// TODO: [ESP32-C61] IDF-9302 Check the channel
+#define ADC1_GPIO0_CHANNEL      0
+#define ADC1_CHANNEL_0_GPIO_NUM 0
+
+#define ADC1_GPIO1_CHANNEL      1
+#define ADC1_CHANNEL_1_GPIO_NUM 1
+
+#define ADC1_GPIO2_CHANNEL      2
+#define ADC1_CHANNEL_2_GPIO_NUM 2
+
+#define ADC1_GPIO3_CHANNEL      3
+#define ADC1_CHANNEL_3_GPIO_NUM 3
+
+#define ADC1_GPIO4_CHANNEL      4
+#define ADC1_CHANNEL_4_GPIO_NUM 4
+
+#define ADC1_GPIO5_CHANNEL      5
+#define ADC1_CHANNEL_5_GPIO_NUM 5
+
+#define ADC1_GPIO6_CHANNEL      6
+#define ADC1_CHANNEL_6_GPIO_NUM 6
diff --git a/components/soc/include/soc/rtc_cntl_periph.h b/components/soc/include/soc/rtc_cntl_periph.h
index 6c94268640..dfc3003371 100644
--- a/components/soc/include/soc/rtc_cntl_periph.h
+++ b/components/soc/include/soc/rtc_cntl_periph.h
@@ -10,7 +10,7 @@
 #include "soc/soc_caps.h"
 
 // TODO: IDF-5645
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
+#if CONFIG_IDF_TARGET_ESP32C6
 #include "soc/lp_io_reg.h"
 #include "soc/lp_io_struct.h"
 #include "soc/lp_aon_reg.h"
@@ -22,7 +22,7 @@
 // ESP32H2-TODO: IDF-6327
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "soc/lp_aon_reg.h"
-#elif CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
+#elif CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
 #include "soc/lp_gpio_reg.h"
 #include "soc/lp_gpio_struct.h"
 #include "soc/lp_iomux_reg.h"