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fix(lp_uart): Fixed LP UART bus clock initialization flow

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This MR updates the LP UART bus clock initialization flow to avoid
a lock up when accessing the LP UART peripheral.
This commit is contained in:
Sudeep Mohanty 2024-03-15 09:28:35 +01:00
parent 3cd174ab09
commit 6d73dda897
1 changed files with 5 additions and 3 deletions
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8
components/ulp/lp_core/lp_core_uart.c
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@ -35,9 +35,6 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
return ESP_ERR_INVALID_ARG;
}
/* Initialize LP UART HAL with default parameters */
uart_hal_init(&hal, LP_UART_PORT_NUM);
/* Get LP UART source clock frequency */
uint32_t sclk_freq = 0;
soc_periph_lp_uart_clk_src_t clk_src = cfg->lp_uart_source_clk ? cfg->lp_uart_source_clk : LP_UART_SCLK_DEFAULT;
@ -49,9 +46,14 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
// LP UART clock source is mixed with other peripherals in the same register
LP_UART_SRC_CLK_ATOMIC() {
/* Enable LP UART bus clock */
lp_uart_ll_enable_bus_clock(0, true);
lp_uart_ll_set_source_clk(hal.dev, clk_src);
}
/* Initialize LP UART HAL with default parameters */
uart_hal_init(&hal, LP_UART_PORT_NUM);
/* Override protocol parameters from the configuration */
lp_uart_ll_set_baudrate(hal.dev, cfg->uart_proto_cfg.baud_rate, sclk_freq);
uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);