From 6d73dda8976e26ac4ffd4cbcdf508e08a6dfc2a2 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Fri, 15 Mar 2024 09:28:35 +0100 Subject: [PATCH] fix(lp_uart): Fixed LP UART bus clock initialization flow This MR updates the LP UART bus clock initialization flow to avoid a lock up when accessing the LP UART peripheral. --- components/ulp/lp_core/lp_core_uart.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/components/ulp/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core_uart.c index 7ab414ec16..7f32c04b65 100644 --- a/components/ulp/lp_core/lp_core_uart.c +++ b/components/ulp/lp_core/lp_core_uart.c @@ -35,9 +35,6 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg) return ESP_ERR_INVALID_ARG; } - /* Initialize LP UART HAL with default parameters */ - uart_hal_init(&hal, LP_UART_PORT_NUM); - /* Get LP UART source clock frequency */ uint32_t sclk_freq = 0; soc_periph_lp_uart_clk_src_t clk_src = cfg->lp_uart_source_clk ? cfg->lp_uart_source_clk : LP_UART_SCLK_DEFAULT; @@ -49,9 +46,14 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg) // LP UART clock source is mixed with other peripherals in the same register LP_UART_SRC_CLK_ATOMIC() { + /* Enable LP UART bus clock */ + lp_uart_ll_enable_bus_clock(0, true); lp_uart_ll_set_source_clk(hal.dev, clk_src); } + /* Initialize LP UART HAL with default parameters */ + uart_hal_init(&hal, LP_UART_PORT_NUM); + /* Override protocol parameters from the configuration */ lp_uart_ll_set_baudrate(hal.dev, cfg->uart_proto_cfg.baud_rate, sclk_freq); uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);