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Code Issues Actions 2 Packages Projects Releases Wiki Activity

1. Optimize 32k xtal configure param to get optimal startup time for ESP32S2;

Browse Source 
2. Solve bug of wakeup fail when pd peripheral for ESP32S2;
3. clear rtc force pu configuration when goto deepsleep after lightsleep.
This commit is contained in:
chaijie 2020-12-30 16:47:41 +08:00
parent 24f98bf80b
commit 6d6fbc3860
2 changed files with 4 additions and 3 deletions
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6
components/soc/soc/esp32s2/include/soc/rtc.h
View File

@ -102,7 +102,7 @@ extern "C" {
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
@ -238,9 +238,9 @@ typedef struct {
} x32k_config_t;
#define X32K_CONFIG_DEFAULT() { \
.dac = 1, \
.dac = 3, \
.dres = 3, \
.dgm = 0, \
.dgm = 3, \
.dbuf = 1, \
}

1
components/soc/src/esp32s2/rtc_sleep.c
View File

@ -101,6 +101,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
if (cfg.deep_slp) {
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,