From 6d6fbc38605906f40ad75b8d304fae20bc52d498 Mon Sep 17 00:00:00 2001 From: chaijie Date: Wed, 30 Dec 2020 16:47:41 +0800 Subject: [PATCH] 1. Optimize 32k xtal configure param to get optimal startup time for ESP32S2; 2. Solve bug of wakeup fail when pd peripheral for ESP32S2; 3. clear rtc force pu configuration when goto deepsleep after lightsleep. --- components/soc/soc/esp32s2/include/soc/rtc.h | 6 +++--- components/soc/src/esp32s2/rtc_sleep.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/components/soc/soc/esp32s2/include/soc/rtc.h b/components/soc/soc/esp32s2/include/soc/rtc.h index 2f7ba5c4e6..99893b8650 100644 --- a/components/soc/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/soc/esp32s2/include/soc/rtc.h @@ -102,7 +102,7 @@ extern "C" { #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 #define RTC_CNTL_CK8M_WAIT_DEFAULT 20 -#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 #define RTC_CNTL_SCK_DCAP_DEFAULT 255 @@ -238,9 +238,9 @@ typedef struct { } x32k_config_t; #define X32K_CONFIG_DEFAULT() { \ - .dac = 1, \ + .dac = 3, \ .dres = 3, \ - .dgm = 0, \ + .dgm = 3, \ .dbuf = 1, \ } diff --git a/components/soc/src/esp32s2/rtc_sleep.c b/components/soc/src/esp32s2/rtc_sleep.c index b0ceeb79ca..70b3c31db9 100644 --- a/components/soc/src/esp32s2/rtc_sleep.c +++ b/components/soc/src/esp32s2/rtc_sleep.c @@ -101,6 +101,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT); if (cfg.deep_slp) { + CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,