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https://github.com/espressif/esp-idf.git
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Merge branch 'bugfix/i2s_fix_incorrect_sclk_in_legacy_driver' into 'master'
i2s: fix incorrect sclk in legacy driver See merge request espressif/esp-idf!21997
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5d61788032
@ -654,12 +654,12 @@ static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint3
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/* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */
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return real_freq;
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}
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return esp_clk_apb_freq() * 2;
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return I2S_LL_DEFAULT_PLL_CLK_FREQ;
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#else
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if (use_apll) {
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ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_SRC_DEFAULT as default clock source");
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}
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return esp_clk_apb_freq() * 2;
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return I2S_LL_DEFAULT_PLL_CLK_FREQ;
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#endif
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -746,12 +746,13 @@ static void i2s_test_common_sample_rate(i2s_chan_handle_t rx_chan, i2s_std_clk_c
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esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_rx_ws_sig, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_WS_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0);
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// Test common sample rate
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uint32_t test_freq[16] = {8000, 10000, 11025, 12000, 16000, 22050, 24000,
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/* Test common sample rate
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* Workaround: set 12000 as 12001 to bypass the unknown failure, TODO: IDF-6705 */
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uint32_t test_freq[] = {8000, 10000, 11025, 12001, 16000, 22050, 24000,
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32000, 44100, 48000, 64000, 88200, 96000,
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128000, 144000, 196000};
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int real_pulse = 0;
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int case_cnt = 16;
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int case_cnt = sizeof(test_freq) / sizeof(uint32_t);
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#if SOC_I2S_HW_VERSION_2
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// Can't support a very high sample rate while using XTAL as clock source
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if (clk_cfg->clk_src == I2S_CLK_SRC_XTAL) {
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -874,10 +874,12 @@ static void i2s_test_common_sample_rate(i2s_port_t id)
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esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_WS_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0);
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// Test common sample rate
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uint32_t test_freq[15] = {8000, 11025, 12000, 16000, 22050, 24000,
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/* Test common sample rate
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* Workaround: set 12000 as 12001 to bypass the unknown failure, TODO: IDF-6705 */
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uint32_t test_freq[] = {8000, 10000, 11025, 12001, 16000, 22050, 24000,
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32000, 44100, 48000, 64000, 88200, 96000,
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128000, 144000, 196000};
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int case_cnt = sizeof(test_freq) / sizeof(uint32_t);
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int real_pulse = 0;
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// Acquire the PM lock incase Dynamic Frequency Scaling(DFS) lower the frequency
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@ -887,7 +889,7 @@ static void i2s_test_common_sample_rate(i2s_port_t id)
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TEST_ESP_OK(esp_pm_lock_create(pm_type, 0, "legacy_i2s_test", &pm_lock));
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esp_pm_lock_acquire(pm_lock);
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#endif
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for (int i = 0; i < 15; i++) {
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for (int i = 0; i < case_cnt; i++) {
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int expt_pulse = (int16_t)((float)test_freq[i] * (TEST_I2S_PERIOD_MS / 1000.0));
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TEST_ESP_OK(i2s_set_clk(id, test_freq[i], SAMPLE_BITS, I2S_CHANNEL_STEREO));
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vTaskDelay(1); // Waiting for hardware totally started
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@ -46,6 +46,7 @@ extern "C" {
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#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
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#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
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#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
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/* I2S clock configuration structure */
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typedef struct {
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@ -33,6 +33,7 @@ extern "C" {
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#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
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#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
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#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
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/* I2S clock configuration structure */
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typedef struct {
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -34,6 +34,7 @@ extern "C" {
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#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
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#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
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#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
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/* I2S clock configuration structure */
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typedef struct {
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@ -34,6 +34,7 @@ extern "C" {
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#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
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#define I2S_LL_PLL_F96M_CLK_FREQ (96 * 1000000) // PLL_F96M_CLK: 96MHz
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#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F96M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
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/* I2S clock configuration structure */
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typedef struct {
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@ -43,6 +43,7 @@ extern "C" {
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#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
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#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
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#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
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/* I2S clock configuration structure */
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typedef struct {
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@ -34,6 +34,7 @@ extern "C" {
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#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
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#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
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#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
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/* I2S clock configuration structure */
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typedef struct {
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@ -318,6 +319,7 @@ static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
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}
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}
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finish:
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
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if (denominator == 0 || numerator == 0) {
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hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
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hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
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@ -335,7 +337,6 @@ finish:
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hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
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}
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
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}
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/**
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@ -392,6 +393,7 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
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}
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}
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finish:
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
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if (denominator == 0 || numerator == 0) {
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hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
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hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
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@ -409,7 +411,6 @@ finish:
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hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
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}
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
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}
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/**
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