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i2s_test: fix output half sample rate failure

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This commit is contained in:
laokaiyao 2023-01-13 15:55:20 +08:00
parent c25fc7d242
commit 3908f4c84d
3 changed files with 12 additions and 9 deletions
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9
components/driver/test_apps/i2s_test_apps/i2s/main/test_i2s.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -746,12 +746,13 @@ static void i2s_test_common_sample_rate(i2s_chan_handle_t rx_chan, i2s_std_clk_c
esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_rx_ws_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_WS_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0);
// Test common sample rate
uint32_t test_freq[16] = {8000, 10000, 11025, 12000, 16000, 22050, 24000,
/* Test common sample rate
* Workaround: set 12000 as 12001 to bypass the unknown failure, TODO: IDF-6705 */
uint32_t test_freq[] = {8000, 10000, 11025, 12001, 16000, 22050, 24000,
32000, 44100, 48000, 64000, 88200, 96000,
128000, 144000, 196000};
int real_pulse = 0;
int case_cnt = 16;
int case_cnt = sizeof(test_freq) / sizeof(uint32_t);
#if SOC_I2S_HW_VERSION_2
// Can't support a very high sample rate while using XTAL as clock source
if (clk_cfg->clk_src == I2S_CLK_SRC_XTAL) {

8
components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/main/test_legacy_i2s.c
View File

@ -874,10 +874,12 @@ static void i2s_test_common_sample_rate(i2s_port_t id)
esp_rom_gpio_connect_out_signal(MASTER_WS_IO, i2s_periph_signal[0].m_tx_ws_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_WS_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0);
// Test common sample rate
uint32_t test_freq[16] = {8000, 10000, 11025, 12000, 16000, 22050, 24000,
/* Test common sample rate
* Workaround: set 12000 as 12001 to bypass the unknown failure, TODO: IDF-6705 */
uint32_t test_freq[] = {8000, 10000, 11025, 12001, 16000, 22050, 24000,
32000, 44100, 48000, 64000, 88200, 96000,
128000, 144000, 196000};
int case_cnt = sizeof(test_freq) / sizeof(uint32_t);
int real_pulse = 0;
// Acquire the PM lock incase Dynamic Frequency Scaling(DFS) lower the frequency
@ -887,7 +889,7 @@ static void i2s_test_common_sample_rate(i2s_port_t id)
TEST_ESP_OK(esp_pm_lock_create(pm_type, 0, "legacy_i2s_test", &pm_lock));
esp_pm_lock_acquire(pm_lock);
#endif
for (int i = 0; i < 16; i++) {
for (int i = 0; i < case_cnt; i++) {
int expt_pulse = (int16_t)((float)test_freq[i] * (TEST_I2S_PERIOD_MS / 1000.0));
TEST_ESP_OK(i2s_set_clk(id, test_freq[i], SAMPLE_BITS, I2S_CHANNEL_STEREO));
vTaskDelay(1); // Waiting for hardware totally started

4
components/hal/esp32s3/include/hal/i2s_ll.h
View File

@ -319,6 +319,7 @@ static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
}
}
finish:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
if (denominator == 0 || numerator == 0) {
hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
@ -336,7 +337,6 @@ finish:
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
}
/**
@ -393,6 +393,7 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
}
}
finish:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
if (denominator == 0 || numerator == 0) {
hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
@ -410,7 +411,6 @@ finish:
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
}
/**