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fix: remove wno format in esp_hw_support component

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This commit is contained in:
gaoxu 2023-09-13 19:15:53 +08:00 committed by Gao Xu
parent a0ae1bbc61
commit 5b4469f973
11 changed files with 33 additions and 33 deletions
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2
components/esp_hw_support/CMakeLists.txt
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@ -153,5 +153,3 @@ if(NOT BOOTLOADER_BUILD)
target_link_libraries(${COMPONENT_LIB} PRIVATE "-u esp_crypto_dpa_prot_include_impl") target_link_libraries(${COMPONENT_LIB} PRIVATE "-u esp_crypto_dpa_prot_include_impl")
endif() endif()
endif() endif()
target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format")

2
components/esp_hw_support/clk_ctrl_os.c
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@ -113,7 +113,7 @@ esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq, uint32_t *real_freq)
*real_freq = apll_freq; *real_freq = apll_freq;
if (need_config) { if (need_config) {
ESP_LOGD(TAG, "APLL will working at %d Hz with coefficients [sdm0] %d [sdm1] %d [sdm2] %d [o_div] %d", ESP_LOGD(TAG, "APLL will working at %"PRIu32" Hz with coefficients [sdm0] %"PRIu32" [sdm1] %"PRIu32" [sdm2] %"PRIu32" [o_div] %"PRIu32"",
apll_freq, sdm0, sdm1, sdm2, o_div); apll_freq, sdm0, sdm1, sdm2, o_div);
/* Set coefficients for APLL, notice that it doesn't mean APLL will start */ /* Set coefficients for APLL, notice that it doesn't mean APLL will start */
rtc_clk_apll_coeff_set(o_div, sdm0, sdm1, sdm2); rtc_clk_apll_coeff_set(o_div, sdm0, sdm1, sdm2);

2
components/esp_hw_support/dma/gdma.c
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@ -364,7 +364,7 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t
} }
if (psram_alignment > data_cache_line_size) { if (psram_alignment > data_cache_line_size) {
ESP_RETURN_ON_FALSE(((psram_alignment % data_cache_line_size) == 0), ESP_ERR_INVALID_ARG, ESP_RETURN_ON_FALSE(((psram_alignment % data_cache_line_size) == 0), ESP_ERR_INVALID_ARG,
TAG, "psram_alignment(%d) should be multiple of the data_cache_line_size(%d)", TAG, "psram_alignment(%d) should be multiple of the data_cache_line_size(%"PRIu32")",
psram_alignment, data_cache_line_size); psram_alignment, data_cache_line_size);
} }

2
components/esp_hw_support/intr_alloc.c
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@ -649,7 +649,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
free(ret); free(ret);
} }
ESP_EARLY_LOGD(TAG, "Connected src %d to int %d (cpu %d)", source, intr, cpu); ESP_EARLY_LOGD(TAG, "Connected src %d to int %d (cpu %"PRIu32")", source, intr, cpu);
return ESP_OK; return ESP_OK;
} }

20
components/esp_hw_support/mspi_timing_by_mspi_delay.c
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@ -413,15 +413,15 @@ static uint32_t s_select_best_tuning_config_dtr(const mspi_timing_config_t *conf
if (consecutive_length <= 2 || consecutive_length >= 6) { if (consecutive_length <= 2 || consecutive_length >= 6) {
//tuning is FAIL, select default point, and generate a warning //tuning is FAIL, select default point, and generate a warning
best_point = configs->default_config_id; best_point = configs->default_config_id;
ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point); ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %"PRIu32"", best_point);
} else if (consecutive_length <= 4) { } else if (consecutive_length <= 4) {
//consecutive length : 3 or 4 //consecutive length : 3 or 4
best_point = end - 1; best_point = end - 1;
ESP_EARLY_LOGD(TAG, "tuning success, best point is index %d", best_point); ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point);
} else { } else {
//consecutive point list length equals 5 //consecutive point list length equals 5
best_point = end - 2; best_point = end - 2;
ESP_EARLY_LOGD(TAG, "tuning success, best point is index %d", best_point); ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point);
} }
return best_point; return best_point;
@ -449,13 +449,13 @@ static uint32_t s_select_best_tuning_config_dtr(const mspi_timing_config_t *conf
max_freq = temp_max_freq; max_freq = temp_max_freq;
best_point = current_point; best_point = current_point;
} }
ESP_EARLY_LOGD(TAG, "sample point %d, max pll is %d mhz, min pll is %d\n", current_point, temp_max_freq, temp_min_freq); ESP_EARLY_LOGD(TAG, "sample point %"PRIu32", max pll is %"PRIu32" mhz, min pll is %"PRIu32"\n", current_point, temp_max_freq, temp_min_freq);
} }
if (max_freq == 0) { if (max_freq == 0) {
ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %d", end + 1 - consecutive_length); ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %"PRIu32"", end + 1 - consecutive_length);
best_point = end + 1 - consecutive_length; best_point = end + 1 - consecutive_length;
} else { } else {
ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %dmhz, best point is index %d", max_freq, best_point); ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %"PRIu32"mhz, best point is index %"PRIu32"", max_freq, best_point);
} }
return best_point; return best_point;
@ -477,11 +477,11 @@ static uint32_t s_select_best_tuning_config_str(const mspi_timing_config_t *conf
if (consecutive_length <= 2|| consecutive_length >= 5) { if (consecutive_length <= 2|| consecutive_length >= 5) {
//tuning is FAIL, select default point, and generate a warning //tuning is FAIL, select default point, and generate a warning
best_point = configs->default_config_id; best_point = configs->default_config_id;
ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point); ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %"PRIu32"", best_point);
} else { } else {
//consecutive length : 3 or 4 //consecutive length : 3 or 4
best_point = end - consecutive_length / 2; best_point = end - consecutive_length / 2;
ESP_EARLY_LOGD(TAG, "tuning success, best point is index %d", best_point); ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point);
} }
return best_point; return best_point;
@ -507,7 +507,7 @@ uint32_t mspi_timing_flash_select_best_tuning_config(const void *configs, uint32
{ {
const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs; const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs;
uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, true); uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, true);
ESP_EARLY_LOGI(TAG, "Flash timing tuning index: %d", best_point); ESP_EARLY_LOGI(TAG, "Flash timing tuning index: %"PRIu32"", best_point);
return best_point; return best_point;
} }
@ -516,7 +516,7 @@ uint32_t mspi_timing_psram_select_best_tuning_config(const void *configs, uint32
{ {
const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs; const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs;
uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, false); uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, false);
ESP_EARLY_LOGI(TAG, "PSRAM timing tuning index: %d", best_point); ESP_EARLY_LOGI(TAG, "PSRAM timing tuning index: %"PRIu32"", best_point);
return best_point; return best_point;
} }

4
components/esp_hw_support/mspi_timing_tuning.c
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@ -213,9 +213,9 @@ static void s_sweep_for_success_sample_points(uint8_t *reference_data, void *con
#endif #endif
if (memcmp(reference_data, read_data, sizeof(read_data)) == 0) { if (memcmp(reference_data, read_data, sizeof(read_data)) == 0) {
out_array[config_idx] = 1; out_array[config_idx] = 1;
ESP_EARLY_LOGD(TAG, "%d, good", config_idx); ESP_EARLY_LOGD(TAG, "%"PRIu32", good", config_idx);
} else { } else {
ESP_EARLY_LOGD(TAG, "%d, bad", config_idx); ESP_EARLY_LOGD(TAG, "%"PRIu32", bad", config_idx);
} }
} }

8
components/esp_hw_support/port/esp32/rtc_clk_init.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -163,18 +163,18 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
xtal_freq = RTC_XTAL_FREQ_26M; xtal_freq = RTC_XTAL_FREQ_26M;
break; break;
case 32 ... 33: case 32 ... 33:
ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz); ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 26 MHz", freq_mhz);
xtal_freq = RTC_XTAL_FREQ_26M; xtal_freq = RTC_XTAL_FREQ_26M;
break; break;
case 34 ... 35: case 34 ... 35:
ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz); ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 40 MHz", freq_mhz);
xtal_freq = RTC_XTAL_FREQ_40M; xtal_freq = RTC_XTAL_FREQ_40M;
break; break;
case 36 ... 45: case 36 ... 45:
xtal_freq = RTC_XTAL_FREQ_40M; xtal_freq = RTC_XTAL_FREQ_40M;
break; break;
default: default:
ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz); ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %"PRIu32" MHz", freq_mhz);
xtal_freq = RTC_XTAL_FREQ_AUTO; xtal_freq = RTC_XTAL_FREQ_AUTO;
break; break;
} }

9
components/esp_hw_support/port/esp32c3/esp_memprot.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -17,6 +17,7 @@
#include "hal/memprot_types.h" #include "hal/memprot_types.h"
#include "esp_private/esp_memprot_internal.h" #include "esp_private/esp_memprot_internal.h"
#include "esp_memprot.h" #include "esp_memprot.h"
#include <inttypes.h>
extern int _iram_text_end; extern int _iram_text_end;
extern int _rtc_text_end; extern int _rtc_text_end;
@ -779,8 +780,8 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string)
sprintf(*dump_info_string, sprintf(*dump_info_string,
"Split line settings (lock=%u):\n" "Split line settings (lock=%u):\n"
" IRAM0:\n line ID (main): 0x%08X (cat=0x%08X)\n line I0: 0x%08X (cat=0x%08X)\n line I1: 0x%08X (cat=0x%08X)\n" " IRAM0:\n line ID (main): 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n"
" DRAM0:\n line D0: 0x%08X (cat=0x%08X)\n line D1: 0x%08X (cat=0x%08X)\n", " DRAM0:\n line D0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line D1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n",
line_lock, line_ID, line_ID_cat, line_I0, line_I0_cat, line_I1, line_I1_cat, line_D0, line_D0_cat, line_D1, line_D1_cat); line_lock, line_ID, line_ID_cat, line_I0, line_I0_cat, line_I1, line_I1_cat, line_D0, line_D0_cat, line_D1, line_D1_cat);
uint32_t offset = strlen(*dump_info_string); uint32_t offset = strlen(*dump_info_string);
@ -790,7 +791,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string)
if (err != ESP_OK) { if (err != ESP_OK) {
sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err)); sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err));
} else { } else {
sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08X (world=0)\n", (uint32_t)line_RTC); sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08"PRIX32" (world=0)\n", (uint32_t)line_RTC);
} }
offset = strlen(*dump_info_string); offset = strlen(*dump_info_string);

11
components/esp_hw_support/port/esp32s3/esp_memprot.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -17,6 +17,7 @@
#include "hal/memprot_types.h" #include "hal/memprot_types.h"
#include "esp_private/esp_memprot_internal.h" #include "esp_private/esp_memprot_internal.h"
#include "esp_memprot.h" #include "esp_memprot.h"
#include <inttypes.h>
/* /*
* LD section boundaries * LD section boundaries
@ -1251,7 +1252,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string)
sprintf(*dump_info_string, sprintf(*dump_info_string,
"Memory sections:\n" "Memory sections:\n"
" _iram_text_start: 0x%08X\n _iram_text_end: 0x%08X\n", " _iram_text_start: 0x%08"PRIX32"\n _iram_text_end: 0x%08"PRIX32"\n",
(uint32_t)&_iram_text_start, (uint32_t)&_iram_text_end); (uint32_t)&_iram_text_start, (uint32_t)&_iram_text_end);
uint32_t offset = strlen(*dump_info_string); uint32_t offset = strlen(*dump_info_string);
@ -1270,8 +1271,8 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string)
sprintf((*dump_info_string + offset), sprintf((*dump_info_string + offset),
"Split line settings (lock=%u):\n" "Split line settings (lock=%u):\n"
" IRAM0:\n line ID (main): 0x%08X (cat=0x%08X)\n line I0: 0x%08X (cat=0x%08X)\n line I1: 0x%08X (cat=0x%08X)\n" " IRAM0:\n line ID (main): 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n"
" DRAM0:\n line D0: 0x%08X (cat=0x%08X)\n line D1: 0x%08X (cat=0x%08X)\n", " DRAM0:\n line D0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line D1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n",
line_lock, line_ID, line_ID_cat, line_I0, line_I0_cat, line_I1, line_I1_cat, line_D0, line_D0_cat, line_D1, line_D1_cat); line_lock, line_ID, line_ID_cat, line_I0, line_I0_cat, line_I1, line_I1_cat, line_D0, line_D0_cat, line_D1, line_D1_cat);
offset = strlen(*dump_info_string); offset = strlen(*dump_info_string);
@ -1281,7 +1282,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string)
if (err != ESP_OK) { if (err != ESP_OK) {
sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err)); sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err));
} else { } else {
sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08X (world=0)\n", (uint32_t)line_RTC); sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08"PRIX32" (world=0)\n", (uint32_t)line_RTC);
} }
offset = strlen(*dump_info_string); offset = strlen(*dump_info_string);

2
components/esp_hw_support/port/esp_clk_tree_common.c
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@ -64,7 +64,7 @@ static uint32_t clk_tree_rtc_slow_calibration(uint32_t slowclk_cycles)
cal_val = (uint32_t)(cal_dividend / source_approx_freq); cal_val = (uint32_t)(cal_dividend / source_approx_freq);
} }
if (cal_val) { if (cal_val) {
ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val); ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %"PRIu32"", cal_val);
// Update the calibration value of RTC_SLOW_CLK // Update the calibration value of RTC_SLOW_CLK
esp_clk_slowclk_cal_set(cal_val); esp_clk_slowclk_cal_set(cal_val);
} }

4
components/esp_hw_support/sleep_cpu.c
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@ -118,7 +118,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c
s_cpu_retention.retent.tagmem.icache.enable = (code_seg_size != 0) ? 1 : 0; s_cpu_retention.retent.tagmem.icache.enable = (code_seg_size != 0) ? 1 : 0;
icache_tagmem_blk_gs = s_cpu_retention.retent.tagmem.icache.vld_size ? s_cpu_retention.retent.tagmem.icache.vld_size : sets * waysgrp; icache_tagmem_blk_gs = s_cpu_retention.retent.tagmem.icache.vld_size ? s_cpu_retention.retent.tagmem.icache.vld_size : sets * waysgrp;
icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs); icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs);
ESP_LOGD(TAG, "I-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (imode.cache_size>>10), ESP_LOGD(TAG, "I-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (imode.cache_size>>10),
imode.cache_line_size, imode.cache_ways, sets, index, icache_tagmem_blk_gs); imode.cache_line_size, imode.cache_ways, sets, index, icache_tagmem_blk_gs);
/* calculate/prepare d-cache tag memory retention parameters */ /* calculate/prepare d-cache tag memory retention parameters */
@ -142,7 +142,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c
#endif #endif
dcache_tagmem_blk_gs = s_cpu_retention.retent.tagmem.dcache.vld_size ? s_cpu_retention.retent.tagmem.dcache.vld_size : sets * waysgrp; dcache_tagmem_blk_gs = s_cpu_retention.retent.tagmem.dcache.vld_size ? s_cpu_retention.retent.tagmem.dcache.vld_size : sets * waysgrp;
dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs); dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs);
ESP_LOGD(TAG, "D-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (dmode.cache_size>>10), ESP_LOGD(TAG, "D-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (dmode.cache_size>>10),
dmode.cache_line_size, dmode.cache_ways, sets, index, dcache_tagmem_blk_gs); dmode.cache_line_size, dmode.cache_ways, sets, index, dcache_tagmem_blk_gs);
/* For I or D cache tagmem retention, backup and restore are performed through /* For I or D cache tagmem retention, backup and restore are performed through