From 5b4469f973edbc48a21f03f6d797689cfa111d1e Mon Sep 17 00:00:00 2001 From: gaoxu Date: Wed, 13 Sep 2023 19:15:53 +0800 Subject: [PATCH] fix: remove wno format in esp_hw_support component --- components/esp_hw_support/CMakeLists.txt | 2 -- components/esp_hw_support/clk_ctrl_os.c | 2 +- components/esp_hw_support/dma/gdma.c | 2 +- components/esp_hw_support/intr_alloc.c | 2 +- .../mspi_timing_by_mspi_delay.c | 20 +++++++++---------- .../esp_hw_support/mspi_timing_tuning.c | 4 ++-- .../esp_hw_support/port/esp32/rtc_clk_init.c | 8 ++++---- .../esp_hw_support/port/esp32c3/esp_memprot.c | 9 +++++---- .../esp_hw_support/port/esp32s3/esp_memprot.c | 11 +++++----- .../esp_hw_support/port/esp_clk_tree_common.c | 2 +- components/esp_hw_support/sleep_cpu.c | 4 ++-- 11 files changed, 33 insertions(+), 33 deletions(-) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 9bd322b0f7..c269eba0f3 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -153,5 +153,3 @@ if(NOT BOOTLOADER_BUILD) target_link_libraries(${COMPONENT_LIB} PRIVATE "-u esp_crypto_dpa_prot_include_impl") endif() endif() - -target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format") diff --git a/components/esp_hw_support/clk_ctrl_os.c b/components/esp_hw_support/clk_ctrl_os.c index 4e580aa513..f35932ed9e 100644 --- a/components/esp_hw_support/clk_ctrl_os.c +++ b/components/esp_hw_support/clk_ctrl_os.c @@ -113,7 +113,7 @@ esp_err_t periph_rtc_apll_freq_set(uint32_t expt_freq, uint32_t *real_freq) *real_freq = apll_freq; if (need_config) { - ESP_LOGD(TAG, "APLL will working at %d Hz with coefficients [sdm0] %d [sdm1] %d [sdm2] %d [o_div] %d", + ESP_LOGD(TAG, "APLL will working at %"PRIu32" Hz with coefficients [sdm0] %"PRIu32" [sdm1] %"PRIu32" [sdm2] %"PRIu32" [o_div] %"PRIu32"", apll_freq, sdm0, sdm1, sdm2, o_div); /* Set coefficients for APLL, notice that it doesn't mean APLL will start */ rtc_clk_apll_coeff_set(o_div, sdm0, sdm1, sdm2); diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index ac2b2a7934..fd7aa1686d 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -364,7 +364,7 @@ esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_t } if (psram_alignment > data_cache_line_size) { ESP_RETURN_ON_FALSE(((psram_alignment % data_cache_line_size) == 0), ESP_ERR_INVALID_ARG, - TAG, "psram_alignment(%d) should be multiple of the data_cache_line_size(%d)", + TAG, "psram_alignment(%d) should be multiple of the data_cache_line_size(%"PRIu32")", psram_alignment, data_cache_line_size); } diff --git a/components/esp_hw_support/intr_alloc.c b/components/esp_hw_support/intr_alloc.c index a216a8e26e..02d72ccd5d 100644 --- a/components/esp_hw_support/intr_alloc.c +++ b/components/esp_hw_support/intr_alloc.c @@ -649,7 +649,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre free(ret); } - ESP_EARLY_LOGD(TAG, "Connected src %d to int %d (cpu %d)", source, intr, cpu); + ESP_EARLY_LOGD(TAG, "Connected src %d to int %d (cpu %"PRIu32")", source, intr, cpu); return ESP_OK; } diff --git a/components/esp_hw_support/mspi_timing_by_mspi_delay.c b/components/esp_hw_support/mspi_timing_by_mspi_delay.c index bc88d88783..efa5dbbd1b 100644 --- a/components/esp_hw_support/mspi_timing_by_mspi_delay.c +++ b/components/esp_hw_support/mspi_timing_by_mspi_delay.c @@ -413,15 +413,15 @@ static uint32_t s_select_best_tuning_config_dtr(const mspi_timing_config_t *conf if (consecutive_length <= 2 || consecutive_length >= 6) { //tuning is FAIL, select default point, and generate a warning best_point = configs->default_config_id; - ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point); + ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %"PRIu32"", best_point); } else if (consecutive_length <= 4) { //consecutive length : 3 or 4 best_point = end - 1; - ESP_EARLY_LOGD(TAG, "tuning success, best point is index %d", best_point); + ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point); } else { //consecutive point list length equals 5 best_point = end - 2; - ESP_EARLY_LOGD(TAG, "tuning success, best point is index %d", best_point); + ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point); } return best_point; @@ -449,13 +449,13 @@ static uint32_t s_select_best_tuning_config_dtr(const mspi_timing_config_t *conf max_freq = temp_max_freq; best_point = current_point; } - ESP_EARLY_LOGD(TAG, "sample point %d, max pll is %d mhz, min pll is %d\n", current_point, temp_max_freq, temp_min_freq); + ESP_EARLY_LOGD(TAG, "sample point %"PRIu32", max pll is %"PRIu32" mhz, min pll is %"PRIu32"\n", current_point, temp_max_freq, temp_min_freq); } if (max_freq == 0) { - ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %d", end + 1 - consecutive_length); + ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %"PRIu32"", end + 1 - consecutive_length); best_point = end + 1 - consecutive_length; } else { - ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %dmhz, best point is index %d", max_freq, best_point); + ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %"PRIu32"mhz, best point is index %"PRIu32"", max_freq, best_point); } return best_point; @@ -477,11 +477,11 @@ static uint32_t s_select_best_tuning_config_str(const mspi_timing_config_t *conf if (consecutive_length <= 2|| consecutive_length >= 5) { //tuning is FAIL, select default point, and generate a warning best_point = configs->default_config_id; - ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %d", best_point); + ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %"PRIu32"", best_point); } else { //consecutive length : 3 or 4 best_point = end - consecutive_length / 2; - ESP_EARLY_LOGD(TAG, "tuning success, best point is index %d", best_point); + ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point); } return best_point; @@ -507,7 +507,7 @@ uint32_t mspi_timing_flash_select_best_tuning_config(const void *configs, uint32 { const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs; uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, true); - ESP_EARLY_LOGI(TAG, "Flash timing tuning index: %d", best_point); + ESP_EARLY_LOGI(TAG, "Flash timing tuning index: %"PRIu32"", best_point); return best_point; } @@ -516,7 +516,7 @@ uint32_t mspi_timing_psram_select_best_tuning_config(const void *configs, uint32 { const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs; uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, false); - ESP_EARLY_LOGI(TAG, "PSRAM timing tuning index: %d", best_point); + ESP_EARLY_LOGI(TAG, "PSRAM timing tuning index: %"PRIu32"", best_point); return best_point; } diff --git a/components/esp_hw_support/mspi_timing_tuning.c b/components/esp_hw_support/mspi_timing_tuning.c index 246a565b55..2b524fb7e3 100644 --- a/components/esp_hw_support/mspi_timing_tuning.c +++ b/components/esp_hw_support/mspi_timing_tuning.c @@ -213,9 +213,9 @@ static void s_sweep_for_success_sample_points(uint8_t *reference_data, void *con #endif if (memcmp(reference_data, read_data, sizeof(read_data)) == 0) { out_array[config_idx] = 1; - ESP_EARLY_LOGD(TAG, "%d, good", config_idx); + ESP_EARLY_LOGD(TAG, "%"PRIu32", good", config_idx); } else { - ESP_EARLY_LOGD(TAG, "%d, bad", config_idx); + ESP_EARLY_LOGD(TAG, "%"PRIu32", bad", config_idx); } } diff --git a/components/esp_hw_support/port/esp32/rtc_clk_init.c b/components/esp_hw_support/port/esp32/rtc_clk_init.c index 75e6fa8987..aef313626e 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32/rtc_clk_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -163,18 +163,18 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void) xtal_freq = RTC_XTAL_FREQ_26M; break; case 32 ... 33: - ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz); + ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 26 MHz", freq_mhz); xtal_freq = RTC_XTAL_FREQ_26M; break; case 34 ... 35: - ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz); + ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 40 MHz", freq_mhz); xtal_freq = RTC_XTAL_FREQ_40M; break; case 36 ... 45: xtal_freq = RTC_XTAL_FREQ_40M; break; default: - ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz); + ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %"PRIu32" MHz", freq_mhz); xtal_freq = RTC_XTAL_FREQ_AUTO; break; } diff --git a/components/esp_hw_support/port/esp32c3/esp_memprot.c b/components/esp_hw_support/port/esp32c3/esp_memprot.c index b6a073dc86..fc315281ae 100644 --- a/components/esp_hw_support/port/esp32c3/esp_memprot.c +++ b/components/esp_hw_support/port/esp32c3/esp_memprot.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ #include "hal/memprot_types.h" #include "esp_private/esp_memprot_internal.h" #include "esp_memprot.h" +#include extern int _iram_text_end; extern int _rtc_text_end; @@ -779,8 +780,8 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) sprintf(*dump_info_string, "Split line settings (lock=%u):\n" - " IRAM0:\n line ID (main): 0x%08X (cat=0x%08X)\n line I0: 0x%08X (cat=0x%08X)\n line I1: 0x%08X (cat=0x%08X)\n" - " DRAM0:\n line D0: 0x%08X (cat=0x%08X)\n line D1: 0x%08X (cat=0x%08X)\n", + " IRAM0:\n line ID (main): 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n" + " DRAM0:\n line D0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line D1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n", line_lock, line_ID, line_ID_cat, line_I0, line_I0_cat, line_I1, line_I1_cat, line_D0, line_D0_cat, line_D1, line_D1_cat); uint32_t offset = strlen(*dump_info_string); @@ -790,7 +791,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) if (err != ESP_OK) { sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err)); } else { - sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08X (world=0)\n", (uint32_t)line_RTC); + sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08"PRIX32" (world=0)\n", (uint32_t)line_RTC); } offset = strlen(*dump_info_string); diff --git a/components/esp_hw_support/port/esp32s3/esp_memprot.c b/components/esp_hw_support/port/esp32s3/esp_memprot.c index a72a11c835..34f49362e9 100644 --- a/components/esp_hw_support/port/esp32s3/esp_memprot.c +++ b/components/esp_hw_support/port/esp32s3/esp_memprot.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ #include "hal/memprot_types.h" #include "esp_private/esp_memprot_internal.h" #include "esp_memprot.h" +#include /* * LD section boundaries @@ -1251,7 +1252,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) sprintf(*dump_info_string, "Memory sections:\n" - " _iram_text_start: 0x%08X\n _iram_text_end: 0x%08X\n", + " _iram_text_start: 0x%08"PRIX32"\n _iram_text_end: 0x%08"PRIX32"\n", (uint32_t)&_iram_text_start, (uint32_t)&_iram_text_end); uint32_t offset = strlen(*dump_info_string); @@ -1270,8 +1271,8 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) sprintf((*dump_info_string + offset), "Split line settings (lock=%u):\n" - " IRAM0:\n line ID (main): 0x%08X (cat=0x%08X)\n line I0: 0x%08X (cat=0x%08X)\n line I1: 0x%08X (cat=0x%08X)\n" - " DRAM0:\n line D0: 0x%08X (cat=0x%08X)\n line D1: 0x%08X (cat=0x%08X)\n", + " IRAM0:\n line ID (main): 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line I1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n" + " DRAM0:\n line D0: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n line D1: 0x%08"PRIX32" (cat=0x%08"PRIX32")\n", line_lock, line_ID, line_ID_cat, line_I0, line_I0_cat, line_I1, line_I1_cat, line_D0, line_D0_cat, line_D1, line_D1_cat); offset = strlen(*dump_info_string); @@ -1281,7 +1282,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) if (err != ESP_OK) { sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err)); } else { - sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08X (world=0)\n", (uint32_t)line_RTC); + sprintf((*dump_info_string + offset), " RTCFAST:\n line main: 0x%08"PRIX32" (world=0)\n", (uint32_t)line_RTC); } offset = strlen(*dump_info_string); diff --git a/components/esp_hw_support/port/esp_clk_tree_common.c b/components/esp_hw_support/port/esp_clk_tree_common.c index 71a3ec507c..a5e701f0c4 100644 --- a/components/esp_hw_support/port/esp_clk_tree_common.c +++ b/components/esp_hw_support/port/esp_clk_tree_common.c @@ -64,7 +64,7 @@ static uint32_t clk_tree_rtc_slow_calibration(uint32_t slowclk_cycles) cal_val = (uint32_t)(cal_dividend / source_approx_freq); } if (cal_val) { - ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val); + ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %"PRIu32"", cal_val); // Update the calibration value of RTC_SLOW_CLK esp_clk_slowclk_cal_set(cal_val); } diff --git a/components/esp_hw_support/sleep_cpu.c b/components/esp_hw_support/sleep_cpu.c index 8ed524e74a..39633d56e7 100644 --- a/components/esp_hw_support/sleep_cpu.c +++ b/components/esp_hw_support/sleep_cpu.c @@ -118,7 +118,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c s_cpu_retention.retent.tagmem.icache.enable = (code_seg_size != 0) ? 1 : 0; icache_tagmem_blk_gs = s_cpu_retention.retent.tagmem.icache.vld_size ? s_cpu_retention.retent.tagmem.icache.vld_size : sets * waysgrp; icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs); - ESP_LOGD(TAG, "I-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (imode.cache_size>>10), + ESP_LOGD(TAG, "I-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (imode.cache_size>>10), imode.cache_line_size, imode.cache_ways, sets, index, icache_tagmem_blk_gs); /* calculate/prepare d-cache tag memory retention parameters */ @@ -142,7 +142,7 @@ static uint32_t cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t c #endif dcache_tagmem_blk_gs = s_cpu_retention.retent.tagmem.dcache.vld_size ? s_cpu_retention.retent.tagmem.dcache.vld_size : sets * waysgrp; dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs); - ESP_LOGD(TAG, "D-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (dmode.cache_size>>10), + ESP_LOGD(TAG, "D-cache size:%"PRIu32" KiB, line size:%d B, ways:%d, sets:%"PRIu32", index:%"PRIu32", tag block groups:%"PRIu32"", (dmode.cache_size>>10), dmode.cache_line_size, dmode.cache_ways, sets, index, dcache_tagmem_blk_gs); /* For I or D cache tagmem retention, backup and restore are performed through