Merge branch 'bugfix/riscv_interrupt_function_naming_v5.0' into 'release/v5.0'

riscv: Fix interrupt function naming and redundancy (v5.0)

See merge request espressif/esp-idf!20220

components/README.md

@@ -42,7 +42,7 @@ This can also contain files provided by the architecture vendor.
 Example:
 
 - `xt_set_exception_handler`
-- `riscv_global_interrupts_enable`
+- `rv_utils_intr_enable`
 - `ERI_PERFMON_MAX`
 
 #### `esp_common`

components/esp_system/port/soc/esp32c2/system_internal.c

@@ -11,8 +11,7 @@
 #include "esp_attr.h"
 #include "esp_efuse.h"
 #include "esp_log.h"
-#include "riscv/riscv_interrupts.h"
-#include "riscv/interrupt.h"
+#include "riscv/rv_utils.h"
 #include "esp_rom_uart.h"
 #include "soc/gpio_reg.h"
 #include "soc/rtc_cntl_reg.h"
@@ -35,7 +34,7 @@
 void IRAM_ATTR esp_restart_noos(void)
 {
     // Disable interrupts
-    riscv_global_interrupts_disable();
+    rv_utils_intr_global_disable();
     // Enable RTC watchdog for 1 second
     wdt_hal_context_t rtc_wdt_ctx;
     wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);

components/esp_system/port/soc/esp32c3/system_internal.c

@@ -11,8 +11,7 @@
 #include "esp_attr.h"
 #include "esp_efuse.h"
 #include "esp_log.h"
-#include "riscv/riscv_interrupts.h"
-#include "riscv/interrupt.h"
+#include "riscv/rv_utils.h"
 #include "esp_rom_uart.h"
 #include "soc/gpio_reg.h"
 #include "soc/rtc_cntl_reg.h"
@@ -36,7 +35,7 @@
 void IRAM_ATTR esp_restart_noos(void)
 {
     // Disable interrupts
-    riscv_global_interrupts_disable();
+    rv_utils_intr_global_disable();
     // Enable RTC watchdog for 1 second
     wdt_hal_context_t rtc_wdt_ctx;
     wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);

components/esp_system/port/soc/esp32h2/system_internal.c

@@ -11,8 +11,7 @@
 #include "esp_attr.h"
 #include "esp_efuse.h"
 #include "esp_log.h"
-#include "riscv/riscv_interrupts.h"
-#include "riscv/interrupt.h"
+#include "riscv/rv_utils.h"
 #include "esp_rom_uart.h"
 #include "soc/gpio_reg.h"
 #include "soc/rtc_cntl_reg.h"
@@ -35,7 +34,7 @@
 void IRAM_ATTR esp_restart_noos(void)
 {
     // Disable interrupts
-    riscv_global_interrupts_disable();
+    rv_utils_intr_global_disable();
     // Enable RTC watchdog for 1 second
     wdt_hal_context_t rtc_wdt_ctx;
     wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);

components/esp_system/test/test_reset_reason.c

@@ -2,11 +2,11 @@
 #include "esp_system.h"
 #include "esp_task_wdt.h"
 #include "esp_attr.h"
+#include "esp_sleep.h"
 #include "soc/rtc.h"
 #include "hal/wdt_hal.h"
-#include "esp_sleep.h"
 #if CONFIG_IDF_TARGET_ARCH_RISCV
-#include "riscv/riscv_interrupts.h"
+#include "riscv/rv_utils.h"
 #endif
 
 #define RTC_BSS_ATTR __attribute__((section(".rtc.bss")))
@@ -199,7 +199,7 @@ static void do_int_wdt_hw(void)
 {
     setup_values();
 #if CONFIG_IDF_TARGET_ARCH_RISCV
-    riscv_global_interrupts_disable();
+    rv_utils_intr_global_disable();
 #else
     XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);
 #endif

components/esp_wifi/esp32c2/esp_adapter.c

@@ -18,7 +18,6 @@
 #include "freertos/event_groups.h"
 #include "freertos/portmacro.h"
 #include "riscv/interrupt.h"
-#include "riscv/riscv_interrupts.h"
 #include "esp_types.h"
 #include "esp_random.h"
 #include "esp_mac.h"

components/esp_wifi/esp32c3/esp_adapter.c

@@ -18,7 +18,6 @@
 #include "freertos/event_groups.h"
 #include "freertos/portmacro.h"
 #include "riscv/interrupt.h"
-#include "riscv/riscv_interrupts.h"
 #include "esp_types.h"
 #include "esp_random.h"
 #include "esp_mac.h"

components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c

@@ -12,7 +12,7 @@
 #include "hal/systimer_hal.h"
 #include "hal/systimer_ll.h"
 #include "riscv/rvruntime-frames.h"
-#include "riscv/riscv_interrupts.h"
+#include "riscv/rv_utils.h"
 #include "riscv/interrupt.h"
 #include "esp_private/crosscore_int.h"
 #include "esp_private/esp_int_wdt.h"
@@ -397,7 +397,6 @@ void vPortYieldFromISR( void )
 
 // ----------------- Scheduler Start/End -------------------
 
-extern void esprv_intc_int_set_threshold(int); // FIXME, this function is in ROM only
 BaseType_t xPortStartScheduler(void)
 {
     uxInterruptNesting = 0;
@@ -408,7 +407,7 @@ BaseType_t xPortStartScheduler(void)
     vPortSetupTimer();
 
     esprv_intc_int_set_threshold(1); /* set global INTC masking level */
-    riscv_global_interrupts_enable();
+    rv_utils_intr_global_enable();
 
     vPortYield();
 

components/freertos/FreeRTOS-Kernel/portable/riscv/port.c

@@ -44,7 +44,7 @@
 #include "hal/systimer_hal.h"
 #include "hal/systimer_ll.h"
 #include "riscv/rvruntime-frames.h"
-#include "riscv/riscv_interrupts.h"
+#include "riscv/rv_utils.h"
 #include "riscv/interrupt.h"
 #include "esp_private/crosscore_int.h"
 #include "esp_attr.h"
@@ -88,7 +88,6 @@ StackType_t *xIsrStackTop = &xIsrStack[0] + (configISR_STACK_SIZE & (~((portPOIN
 
 // ----------------- Scheduler Start/End -------------------
 
-extern void esprv_intc_int_set_threshold(int); // FIXME, this function is in ROM only
 BaseType_t xPortStartScheduler(void)
 {
     uxInterruptNesting = 0;
@@ -99,7 +98,7 @@ BaseType_t xPortStartScheduler(void)
     vPortSetupTimer();
 
     esprv_intc_int_set_threshold(1); /* set global INTC masking level */
-    riscv_global_interrupts_enable();
+    rv_utils_intr_global_enable();
 
     vPortYield();
 

components/riscv/include/riscv/interrupt.h

@@ -115,7 +115,7 @@ int esprv_intc_int_get_priority(int rv_int_num);
  *
  * @param priority_threshold  Interrupt priority threshold, 0 to 7
  */
-void esprv_intc_set_threshold(int priority_threshold);
+void esprv_intc_int_set_threshold(int priority_threshold);
 
 /**
  * @brief Get interrupt unmask

components/riscv/include/riscv/riscv_interrupts.h

@@ -1,45 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Enable CPU interrupt
- * @param rv_int_num  CPU interrupt number
- */
-void riscv_interrupt_enable(int rv_int_num);
-
-/**
- * Disable CPU interrupt
- * @param rv_int_num  CPU interrupt number
- */
-void riscv_interrupt_disable(int rv_int_num);
-
-/**
- * Globally enable CPU interrupts
- */
-void riscv_global_interrupts_enable(void);
-
-/**
- * Globally disable CPU interrupts
- */
-void riscv_global_interrupts_disable(void);
-
-#ifdef __cplusplus
-}
-#endif

components/riscv/include/riscv/rv_utils.h

@@ -83,7 +83,7 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val)
 
 FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask)
 {
-    //Disable all interrupts to make updating of the interrupt mask atomic.
+    // Disable all interrupts to make updating of the interrupt mask atomic.
     unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
     esprv_intc_int_enable(intr_mask);
     RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
@@ -91,7 +91,7 @@ FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask)
 
 FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask)
 {
-    //Disable all interrupts to make updating of the interrupt mask atomic.
+    // Disable all interrupts to make updating of the interrupt mask atomic.
     unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
     esprv_intc_int_disable(intr_mask);
     RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
@@ -107,6 +107,16 @@ FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(int intr_num)
     REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
 }
 
+FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void)
+{
+    RV_SET_CSR(mstatus, MSTATUS_MIE);
+}
+
+FORCE_INLINE_ATTR void rv_utils_intr_global_disable(void)
+{
+    RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
+}
+
 /* -------------------------------------------------- Memory Ports -----------------------------------------------------
  *
  * ------------------------------------------------------------------------------------------------------------------ */

components/riscv/interrupt.c

@@ -67,16 +67,6 @@ void intr_matrix_route(int intr_src, int intr_num)
     REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num);
 }
 
-void riscv_global_interrupts_enable(void)
-{
-    RV_SET_CSR(mstatus, MSTATUS_MIE);
-}
-
-void riscv_global_interrupts_disable(void)
-{
-    RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
-}
-
 uint32_t esprv_intc_get_interrupt_unmask(void)
 {
     return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);

tools/ci/check_copyright_ignore.txt

@@ -957,7 +957,6 @@ components/pthread/test/test_pthread_local_storage.c
 components/riscv/include/riscv/csr.h
 components/riscv/include/riscv/encoding.h
 components/riscv/include/riscv/instruction_decode.h
-components/riscv/include/riscv/riscv_interrupts.h
 components/riscv/include/riscv/rvruntime-frames.h
 components/riscv/instruction_decode.c
 components/sdmmc/sdmmc_common.c