From 0c8ac295c545d1da54c4760aeee11b9bd46401ff Mon Sep 17 00:00:00 2001 From: Darian Leung Date: Tue, 26 Jul 2022 22:07:58 +0800 Subject: [PATCH 1/2] riscv: Remove redundant riscv_interrupts.h header This commit removes the riscv_interrupts.h header is it has become redundant. The previously exposed API has been handled as follows: - "riscv_interrupt_enable()" and "riscv_interrupt_disable()" have been removed. These functions were declarations only and never had any implementation. - "riscv_global_interrupts_enable()" and "riscv_global_interrupts_disable()" renamed to "rv_utils_intr_global_enable()" and "rv_utils_intr_global_disable()" respectively and now placed in rv_utils.h --- components/README.md | 2 +- .../port/soc/esp32c2/system_internal.c | 5 +-- .../port/soc/esp32c3/system_internal.c | 5 +-- .../port/soc/esp32h2/system_internal.c | 5 +-- .../esp_system/test/test_reset_reason.c | 6 +-- components/esp_wifi/esp32c2/esp_adapter.c | 1 - components/esp_wifi/esp32c3/esp_adapter.c | 1 - .../FreeRTOS-Kernel-SMP/portable/riscv/port.c | 4 +- .../FreeRTOS-Kernel/portable/riscv/port.c | 4 +- .../riscv/include/riscv/riscv_interrupts.h | 45 ------------------- components/riscv/include/riscv/rv_utils.h | 14 +++++- components/riscv/interrupt.c | 10 ----- tools/ci/check_copyright_ignore.txt | 1 - 13 files changed, 26 insertions(+), 77 deletions(-) delete mode 100644 components/riscv/include/riscv/riscv_interrupts.h diff --git a/components/README.md b/components/README.md index b913c28026..ab36e41a86 100644 --- a/components/README.md +++ b/components/README.md @@ -42,7 +42,7 @@ This can also contain files provided by the architecture vendor. Example: - `xt_set_exception_handler` -- `riscv_global_interrupts_enable` +- `rv_utils_intr_enable` - `ERI_PERFMON_MAX` #### `esp_common` diff --git a/components/esp_system/port/soc/esp32c2/system_internal.c b/components/esp_system/port/soc/esp32c2/system_internal.c index 551b4a672f..f14e225df4 100644 --- a/components/esp_system/port/soc/esp32c2/system_internal.c +++ b/components/esp_system/port/soc/esp32c2/system_internal.c @@ -11,8 +11,7 @@ #include "esp_attr.h" #include "esp_efuse.h" #include "esp_log.h" -#include "riscv/riscv_interrupts.h" -#include "riscv/interrupt.h" +#include "riscv/rv_utils.h" #include "esp_rom_uart.h" #include "soc/gpio_reg.h" #include "soc/rtc_cntl_reg.h" @@ -35,7 +34,7 @@ void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); diff --git a/components/esp_system/port/soc/esp32c3/system_internal.c b/components/esp_system/port/soc/esp32c3/system_internal.c index 950538da0f..f5ca5ddda0 100644 --- a/components/esp_system/port/soc/esp32c3/system_internal.c +++ b/components/esp_system/port/soc/esp32c3/system_internal.c @@ -11,8 +11,7 @@ #include "esp_attr.h" #include "esp_efuse.h" #include "esp_log.h" -#include "riscv/riscv_interrupts.h" -#include "riscv/interrupt.h" +#include "riscv/rv_utils.h" #include "esp_rom_uart.h" #include "soc/gpio_reg.h" #include "soc/rtc_cntl_reg.h" @@ -36,7 +35,7 @@ void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index f335416a35..a7dd7548f3 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -11,8 +11,7 @@ #include "esp_attr.h" #include "esp_efuse.h" #include "esp_log.h" -#include "riscv/riscv_interrupts.h" -#include "riscv/interrupt.h" +#include "riscv/rv_utils.h" #include "esp_rom_uart.h" #include "soc/gpio_reg.h" #include "soc/rtc_cntl_reg.h" @@ -35,7 +34,7 @@ void IRAM_ATTR esp_restart_noos(void) { // Disable interrupts - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); // Enable RTC watchdog for 1 second wdt_hal_context_t rtc_wdt_ctx; wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false); diff --git a/components/esp_system/test/test_reset_reason.c b/components/esp_system/test/test_reset_reason.c index 9347b8b013..2cfc7c4276 100644 --- a/components/esp_system/test/test_reset_reason.c +++ b/components/esp_system/test/test_reset_reason.c @@ -2,11 +2,11 @@ #include "esp_system.h" #include "esp_task_wdt.h" #include "esp_attr.h" +#include "esp_sleep.h" #include "soc/rtc.h" #include "hal/wdt_hal.h" -#include "esp_sleep.h" #if CONFIG_IDF_TARGET_ARCH_RISCV -#include "riscv/riscv_interrupts.h" +#include "riscv/rv_utils.h" #endif #define RTC_BSS_ATTR __attribute__((section(".rtc.bss"))) @@ -199,7 +199,7 @@ static void do_int_wdt_hw(void) { setup_values(); #if CONFIG_IDF_TARGET_ARCH_RISCV - riscv_global_interrupts_disable(); + rv_utils_intr_global_disable(); #else XTOS_SET_INTLEVEL(XCHAL_NMILEVEL); #endif diff --git a/components/esp_wifi/esp32c2/esp_adapter.c b/components/esp_wifi/esp32c2/esp_adapter.c index 2b7827683a..96b32a1f7d 100644 --- a/components/esp_wifi/esp32c2/esp_adapter.c +++ b/components/esp_wifi/esp32c2/esp_adapter.c @@ -18,7 +18,6 @@ #include "freertos/event_groups.h" #include "freertos/portmacro.h" #include "riscv/interrupt.h" -#include "riscv/riscv_interrupts.h" #include "esp_types.h" #include "esp_random.h" #include "esp_mac.h" diff --git a/components/esp_wifi/esp32c3/esp_adapter.c b/components/esp_wifi/esp32c3/esp_adapter.c index 65f594dc00..c5d1d7c5ab 100644 --- a/components/esp_wifi/esp32c3/esp_adapter.c +++ b/components/esp_wifi/esp32c3/esp_adapter.c @@ -18,7 +18,6 @@ #include "freertos/event_groups.h" #include "freertos/portmacro.h" #include "riscv/interrupt.h" -#include "riscv/riscv_interrupts.h" #include "esp_types.h" #include "esp_random.h" #include "esp_mac.h" diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c index 2474875022..dcd1b990ec 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c @@ -12,7 +12,7 @@ #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" #include "riscv/rvruntime-frames.h" -#include "riscv/riscv_interrupts.h" +#include "riscv/rv_utils.h" #include "riscv/interrupt.h" #include "esp_private/crosscore_int.h" #include "esp_private/esp_int_wdt.h" @@ -408,7 +408,7 @@ BaseType_t xPortStartScheduler(void) vPortSetupTimer(); esprv_intc_int_set_threshold(1); /* set global INTC masking level */ - riscv_global_interrupts_enable(); + rv_utils_intr_global_enable(); vPortYield(); diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c index c493ded1f2..51c9d9ef49 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c @@ -44,7 +44,7 @@ #include "hal/systimer_hal.h" #include "hal/systimer_ll.h" #include "riscv/rvruntime-frames.h" -#include "riscv/riscv_interrupts.h" +#include "riscv/rv_utils.h" #include "riscv/interrupt.h" #include "esp_private/crosscore_int.h" #include "esp_attr.h" @@ -99,7 +99,7 @@ BaseType_t xPortStartScheduler(void) vPortSetupTimer(); esprv_intc_int_set_threshold(1); /* set global INTC masking level */ - riscv_global_interrupts_enable(); + rv_utils_intr_global_enable(); vPortYield(); diff --git a/components/riscv/include/riscv/riscv_interrupts.h b/components/riscv/include/riscv/riscv_interrupts.h deleted file mode 100644 index b3d225d58c..0000000000 --- a/components/riscv/include/riscv/riscv_interrupts.h +++ /dev/null @@ -1,45 +0,0 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Enable CPU interrupt - * @param rv_int_num CPU interrupt number - */ -void riscv_interrupt_enable(int rv_int_num); - -/** - * Disable CPU interrupt - * @param rv_int_num CPU interrupt number - */ -void riscv_interrupt_disable(int rv_int_num); - -/** - * Globally enable CPU interrupts - */ -void riscv_global_interrupts_enable(void); - -/** - * Globally disable CPU interrupts - */ -void riscv_global_interrupts_disable(void); - -#ifdef __cplusplus -} -#endif diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h index f0c2e5f8dd..5fc0b2e426 100644 --- a/components/riscv/include/riscv/rv_utils.h +++ b/components/riscv/include/riscv/rv_utils.h @@ -83,7 +83,7 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val) FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask) { - //Disable all interrupts to make updating of the interrupt mask atomic. + // Disable all interrupts to make updating of the interrupt mask atomic. unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); esprv_intc_int_enable(intr_mask); RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); @@ -91,7 +91,7 @@ FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask) FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask) { - //Disable all interrupts to make updating of the interrupt mask atomic. + // Disable all interrupts to make updating of the interrupt mask atomic. unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); esprv_intc_int_disable(intr_mask); RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); @@ -107,6 +107,16 @@ FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(int intr_num) REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num); } +FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void) +{ + RV_SET_CSR(mstatus, MSTATUS_MIE); +} + +FORCE_INLINE_ATTR void rv_utils_intr_global_disable(void) +{ + RV_CLEAR_CSR(mstatus, MSTATUS_MIE); +} + /* -------------------------------------------------- Memory Ports ----------------------------------------------------- * * ------------------------------------------------------------------------------------------------------------------ */ diff --git a/components/riscv/interrupt.c b/components/riscv/interrupt.c index 24b4d5d033..5984d0d374 100644 --- a/components/riscv/interrupt.c +++ b/components/riscv/interrupt.c @@ -67,16 +67,6 @@ void intr_matrix_route(int intr_src, int intr_num) REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num); } -void riscv_global_interrupts_enable(void) -{ - RV_SET_CSR(mstatus, MSTATUS_MIE); -} - -void riscv_global_interrupts_disable(void) -{ - RV_CLEAR_CSR(mstatus, MSTATUS_MIE); -} - uint32_t esprv_intc_get_interrupt_unmask(void) { return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG); diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index d753b30582..946d975b9a 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -957,7 +957,6 @@ components/pthread/test/test_pthread_local_storage.c components/riscv/include/riscv/csr.h components/riscv/include/riscv/encoding.h components/riscv/include/riscv/instruction_decode.h -components/riscv/include/riscv/riscv_interrupts.h components/riscv/include/riscv/rvruntime-frames.h components/riscv/instruction_decode.c components/sdmmc/sdmmc_common.c From ebc57e14f6c6ba6747b2292dce4d873bafc77301 Mon Sep 17 00:00:00 2001 From: Darian Leung Date: Wed, 27 Jul 2022 16:54:24 +0800 Subject: [PATCH 2/2] riscv: Fix esprv_intc_int_set_threshold() naming This commit fixes the function declaration naming from esprv_intc_set_threshold() to esprv_intc_int_set_threshold(), thus allowing the underlying ROM funciton to be exposed via the header. --- components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c | 1 - components/freertos/FreeRTOS-Kernel/portable/riscv/port.c | 1 - components/riscv/include/riscv/interrupt.h | 2 +- 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c index dcd1b990ec..e9e10b1972 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/riscv/port.c @@ -397,7 +397,6 @@ void vPortYieldFromISR( void ) // ----------------- Scheduler Start/End ------------------- -extern void esprv_intc_int_set_threshold(int); // FIXME, this function is in ROM only BaseType_t xPortStartScheduler(void) { uxInterruptNesting = 0; diff --git a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c index 51c9d9ef49..f001259166 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c +++ b/components/freertos/FreeRTOS-Kernel/portable/riscv/port.c @@ -88,7 +88,6 @@ StackType_t *xIsrStackTop = &xIsrStack[0] + (configISR_STACK_SIZE & (~((portPOIN // ----------------- Scheduler Start/End ------------------- -extern void esprv_intc_int_set_threshold(int); // FIXME, this function is in ROM only BaseType_t xPortStartScheduler(void) { uxInterruptNesting = 0; diff --git a/components/riscv/include/riscv/interrupt.h b/components/riscv/include/riscv/interrupt.h index e98115410d..c3b88084b9 100644 --- a/components/riscv/include/riscv/interrupt.h +++ b/components/riscv/include/riscv/interrupt.h @@ -115,7 +115,7 @@ int esprv_intc_int_get_priority(int rv_int_num); * * @param priority_threshold Interrupt priority threshold, 0 to 7 */ -void esprv_intc_set_threshold(int priority_threshold); +void esprv_intc_int_set_threshold(int priority_threshold); /** * @brief Get interrupt unmask